Bai Giang VXL VDK Chuan 2009 2010

TRNG I HC K THUT CNG NGHIP
KHOA IN T
B MN K THUT MY TNH

BI GING PHT CHO SINH VIN
(LU HNH NI B)
Theo chng trnh 150 TC thay 180 TC hoc tng ng
S dng cho nm hc 2009 2010

Tn bi ging: Vi x l Vi iu khin
S tn ch: 03

BI GING PHT CHO SINH VIN
(LU HNH NI B)
Theo chng trnh 150 TC thay 180 TC hoc tng ng
S dng cho nm hc 2009 - 2010
Tn bi ging: Vi x l Vi iu khin
S tn ch: 03

Thi Nguyn, ngy 25 thng 03 nm 2009
Trng b mn

Ths. Nguyn Tun Linh
Trng khoa in T

PGS. TS. Nguyn Hu Cng

B mn K thut my tnh Khoa in t - Trng H K thut Cng nghip 3

MC LC

CHNG 1. TNG QUAN V VI X L VI IU KHIN........................................................5
1.1 GII THIU CHUNG V VI X L VI IU KHIN........................................... 6
1.1.1 Tng quan................................................................................................................ 6
1.1.2 Lch s pht trin ca cc b x l.......................................................................... 6
1.1.3 Vi x l v vi iu khin......................................................................................... 7
1.2 Cu trc chung ca h vi x l........................................................................................ 7
1.2.1 Khi x l trung tm (CPU).................................................................................... 8
1.2.2 B nh (Memory).................................................................................................... 9
1.2.3 Khi phi ghp vo/ra (I/O) .................................................................................. 11
1.2.4 H thng bus.......................................................................................................... 12
1.3 nh dng d liu v biu din thng tin trong h vi x l vi iu khin.................. 13
1.3.1 Cc h m............................................................................................................ 13
1.3.2 Biu din s v k t............................................................................................. 14
1.3.3 Cc php ton s hc trn h m nh phn.......................................................... 15
CHNG 2. H VI X L INTEL 80x86.......................................................................................16
2.1 Cu trc phn cng ca b vi x l 8086...................................................................... 17
2.1.1 Tng quan.............................................................................................................. 17
2.1.2 Cu trc bn trong v s hot ng....................................................................... 17
2.1.3 M t chc nng cc chn ..................................................................................... 21
2.2 Ch a ch................................................................................................................ 21
2.2.1 Khi nim ch a ch ....................................................................................... 21
2.2.2 Cc ch a ch ................................................................................................. 24
2.2.3 Gii m a ch ...................................................................................................... 27
2.3 Tp lnh......................................................................................................................... 30
2.3.1 Gii thiu chung.................................................................................................... 30
2.3.2 Cc nhm lnh....................................................................................................... 30
2.4 Biu thi gian ghi/c .............................................................................................. 57
2.4.1 Xung nhp v chu k my...................................................................................... 57
2.4.2 Chu k c/ghi ca vi x l 8086 ......................................................................... 58
2.5 Lp trnh hp ng (Assembly) cho vi x l 80x86 ....................................................... 60
2.5.1 Gii thiu chung v hp ng................................................................................. 60
2.5.2 Cu trc chung ca chng trnh hp ng............................................................ 60
2.5.3 Cc cu trc iu khin c bn.............................................................................. 67
2.5.4 Cc bc khi lp trnh ........................................................................................... 68
2.5.5 Cc bi tp v d.................................................................................................... 70
2.6 Cu hi v bi tp.......................................................................................................... 84
CHNG 3. GII THIU CHUNG V VI IU KHIN ..............................................................86
3.1 Gii thiu chung............................................................................................................ 87
3.1.1 ng dng ca vi iu khin .................................................................................. 88
3.1.2 Hot ng ca vi iu khin.................................................................................. 88
3.1.3 Cu trc chung ca vi iu khin .......................................................................... 89
3.2 Kin trc vi iu khin 8051 ......................................................................................... 93
3.2.1 Chun 8051............................................................................................................ 93
3.2.2 Chn vi iu khin 8051........................................................................................ 95
3.2.3 Cng vo/ra ........................................................................................................... 96
3.2.4 T chc b nh trong.......................................................................................... 101
3.2.5 T chc b nh ngoi ......................................................................................... 103


3.2.6 Cc thanh ghi chc nng c bit (SFRs - Special Function Registers) ............ 105
3.2.7 B m v b nh thi ....................................................................................... 108
3.2.8 Truyn thng khng ng b (UART)................................................................ 113
3.2.9 Ngt vi iu khin 8051 ...................................................................................... 118
3.3 Tp lnh 8051 v lp trnh hp ng cho 8051............................................................. 120
3.3.1 Tp lnh............................................................................................................... 120
3.3.2 Lp trnh Assembly ............................................................................................. 127
3.3.3 Cu hi v bi tp................................................................................................ 133
CHNG 4. CC H VI IU KHIN TIN TIN V NG DNG........................................136
4.1 Cc h vi iu khin tin tin ...................................................................................... 137
4.1.1 Atmel AVR.......................................................................................................... 137
4.1.2 Vi iu khin PIC................................................................................................ 142
4.1.3 ARM.................................................................................................................... 144
4.2 Cc v d ng dng ..................................................................................................... 148
4.2.1 Nhp nhy dy LED n..................................................................................... 148
4.2.2 Timer T0 trong ch chia tch ......................................................................... 149
4.2.3 S dng Timer T2 ............................................................................................... 150
4.2.4 Dng ngt ngoi. ................................................................................................. 152
4.2.5 Lp trnh ngt ngoi theo sn xung................................................................. 153
4.2.6 S dng LED 7 thanh.......................................................................................... 154
4.2.7 Vit ch s trn LED 7 thanh.............................................................................. 154
4.2.8 Thng bo bng vn bn trn mn hnh LCD..................................................... 156
4.2.9 Nhn d liu qua UART...................................................................................... 161
4.2.10 Truyn d liu qua UART................................................................................... 162
4.2.11 Chng trnh con phc v truyn thng ni tip................................................. 163
4.2.12 Truyn thng UART cho 8051 bng phn mm................................................. 164
4.2.13 Ghp ni 8051 vi ADC0804, chuyn i ADC ................................................ 166
4.2.14 Chuyn i s nh phn sang s thp phn ......................................................... 167
4.2.15 Ghp ni vi iu khin vi bn phm.................................................................. 167
4.2.16 Ghp ni vi iu khin vi step motor ................................................................ 168
Ti liu tham kho ....................................................................................................................................169

Bn mm b sch ny, c xut bn ti trang web ca:
Nguyn Tun Anh, BM K thut My tnh, khoa in T, H KTCN, TN, VN
http://picat.dieukhien.net

Bi ging Chng 1
Vi x l - Vi iu khin Tng quan v vi x l vi iu khin

CHNG 1.
TNG QUAN V VI X L VI IU KHIN

Mc tiu:
Gip sinh vin hiu v lch s ra i ca h vi x l vi iu khin; khi nim, cu
to v nguyn l ca h vi x l vi iu khin; n li kin thc v cc h thng s
m.

Tm tt chng:
Chng chia lm 3 phn:
Gii thiu chung v vi x l vi iu khin
Tng quan
Lch s pht trin ca cc b x l
Vi x l v vi iu khin
Cu trc chung ca h vi x l
Khi x l trung tm (CPU)
B nh (Memory)
Khi phi ghp vo/ra (I/O)
H thng bus
nh dng d liu v biu din thng tin trong h vi x l vi iu khin
Cc h m
Biu din s v k t
Cc php ton s hc trn h m nh phn

Bi ging Chng 1

1.1 GII THIU CHUNG V VI X L VI IU KHIN
1.1.1 Tng quan
Vi x l (vit tt l P hay uP), i khi cn
c gi l b vi x l, l mt linh kin in t
my tnh c ch to t cc tranzito thu nh tch
hp ln trn mt vi mch tch hp n. Khi x
l trung tm (CPU) l mt b vi x l c nhiu
ngi bit n nhng ngoi ra nhiu thnh phn
khc trong my tnh cng c b vi x l ring ca
n, v d trn cc mn hnh (video card) chng ta
cng c mt b vi x l.
Trc khi xut hin cc b vi x l, cc
CPU c xy dng t cc mch tch hp c nh ring bit, mi mch tch hp ch
cha khong vo chc tranzito. Do , mt CPU c th l mt bng mch gm hng
ngn hay hng triu vi mch tch hp. Ngy nay, cng ngh tch hp pht trin, mt
CPU c th tch hp ln mt hoc vi vi mch tch hp c ln, mi vi mch tch hp
c ln cha hng ngn hoc hng triu tranzito. Nh cng sut tiu th v gi thnh
ca b vi x l gim ng k.
Vi iu khin l mt my tnh c tch hp trn mt chp, n thng c s
dng iu khin cc thit b in t. Vi iu khin, thc cht, l mt h thng bao
gm mt vi x l c hiu sut dng v gi thnh thp (khc vi cc b vi x l a
nng dng trong my tnh) kt hp vi cc khi ngoi vi nh b nh, cc m un
vo/ra, cc m un bin i s sang tng t v tng t sang s,... my tnh th cc
m un thng c xy dng bi cc chp v mch ngoi.
Vi iu khin thng c dng xy dng cc h thng nhng. N xut hin kh
nhiu trong cc dng c in t, thit b in, my git, l vi sng, in thoi, u c
DVD, thit b a phng tin, dy chuyn t ng, v.v.
Hu ht cc vi iu khin ngy nay c xy dng da trn kin trc Harvard, kin
trc ny nh ngha bn thnh phn cn thit ca mt h thng nhng. Nhng thnh
phn ny l li CPU, b nh chng trnh (thng thng l ROM hoc b nh Flash),
b nh d liu (RAM), mt hoc vi b nh thi v cc cng vo/ra giao tip vi cc
thit b ngoi vi v cc mi trng bn ngoi - tt c cc khi ny c thit k trong
mt vi mch tch hp. Vi iu khin khc vi cc b vi x l a nng ch l n c th
hot ng ch vi vi vi mch h tr bn ngoi.
1.1.2 Lch s pht trin ca cc b x l
- Th h 1 (1971 - 1973): vi x l 4 bit, i din l 4004, 4040, 8080 (Intel) hay IPM-16
(National Semiconductor).
+ di word thng l 4 bit (c th ln hn).
+ Ch to bng cng ngh PMOS vi mt phn t nh, tc thp, dng ti thp
nhng gi thnh r.
+ Tc 10 - 60 s / lnh vi tn s xung nhp 0.1 - 0.8 MHz. + Tp lnh n gin v phi
cn nhiu vi mch ph tr.

Hnh 1-1.B vi x l Intel 80486DX2
Bi ging Chng 1

- Th h 2 (1974 - 1977): vi x l 8 bit, i din l 8080, 8085 (Intel) hay Z80 (Zilog).
+ Tp lnh phong ph hn.
+ a ch c th n 64 KB. Mt s b vi x l c th phn bit 256 a ch cho thit b
ngoi vi.
+ S dng cng ngh NMOS hay CMOS.
+ Tc 1 - 8 s / lnh vi tn s xung nhp 1 - 5 MHz
- Th h 3 (1978 - 1982): vi x l 16 bit, i din l 68000/68010 (Motorola) hay 8086/
80286/ 80386 (Intel)
+ Tp lnh a dng vi cc lnh nhn, chia v x l chui.
+ a ch b nh c th t 1 - 16 MB v c th phn bit ti 64KB a ch cho ngoi vi
+ S dng cng ngh HMOS.
+ Tc 0.1 - 1 s / lnh vi tn s xung nhp 5 - 10 MHz.
- Th h 4: vi x l 32 bit 68020/68030/68040/68060 (Motorola) hay 80386/80486 (Intel) v
vi x l 32 bit Pentium (Intel)
+ Bus a ch 32 bit, phn bit 4 GB b nh. + C th dng thm cc b ng x l
(coprocessor). + C kh nng lm vic vi b nh o.
+ C cc c ch pipeline, b nh cache.
+ S dng cng ngh HCMOS.
- Th h 5: vi x l 64 bit

1.1.3 Vi x l v vi iu khin
Khi nim vi x l (microprocessor) v vi iu khin (microcontroller).
V c bn hai khi nim ny khng khc nhau nhiu, vi x l l thut ng chung
dng cp n k thut ng dng cc cng ngh vi in t, cng ngh tch hp v
kh nng x l theo chng trnh vo cc lnh vc khc nhau. Vo nhng giai on
u trong qu trnh pht trin ca cng ngh vi x l, cc chip (hay cc vi x l) c
ch to ch tch hp nhng phn cng thit yu nh CPU cng cc mch giao tip gia
CPU v cc phn cng khc. Trong giai on ny, cc phn cng khc (k c b nh)
thng khng c tch hp trn chip m phi ghp ni thm bn ngoi. Cc phn
cng ny c gi l cc ngoi vi (Peripherals). V sau, nh s pht trin vt bc ca
cng ngh tch hp, cc ngoi vi cng c tch hp vo bn trong IC v ngi ta gi
cc vi x l c tch hp thm cc ngoi vi l cc vi iu khin.
Vic tch hp thm cc ngoi vi vo trong cng mt IC vi CPU to ra nhiu li
ch nh lm gim thiu cc ghp ni bn ngoi, gim thiu s lng linh kin in t
ph, gim chi ph cho thit k h thng, n gin ha vic thit k, nng cao hiu sut
v tnh linh hot. Trong ti liu ny, ranh gii gia hai khi nim vi x l v vi iu
khin thc s khng cn phi phn bit r rng. Chng ti s dng thut ng vi x
l khi cp n cc khi nim c bn ca k thut vi x l ni chung v s dng
thut ng vi iu khin khi i su nghin cu mt h chip c th.
1.2 Cu trc chung ca h vi x l
V c bn kin trc ca mt vi x l gm nhng phn cng sau:
- n v x l trung tm CPU (Central Processing Unit).
- Cc b nh (Memories).
- Cc cng vo/ra (song song (Parallel I/O Ports), ni tip (Serial I/O Ports))
Bi ging Chng 1

- Cc b m/b nh thi (Timers).
- H thng BUS (a ch, d liu, iu khin)
Ngoi ra vi mi loi vi iu khin c th cn c th c thm mt s phn cng
khc nh b bin i tng t-s ADC, b bin i s-tng t DAC, cc mch iu
ch dng sng WG, iu ch rng xung PWMB no ca mi vi x l chnh l
CPU, cc phn cng khc ch l cc c quan chp hnh di quyn ca CPU. Mi c
quan ny u c mt c ch hot ng nht nh m CPU phi tun theo khi giao tip
vi chng.

Hnh 1-2. Cu trc chung ca h vi x l
c th giao tip v iu khin cc c quan chp hnh (cc ngoi vi), CPU s
dng 03 loi tn hiu c bn l tn hiu a ch (Address), tn hiu d liu (Data) v tn
hiu iu khin (Control). V mt vt l th cc tn hiu ny l cc ng nh dn in
ni t CPU n cc ngoi vi hoc thm ch l gia cc ngoi vi vi nhau. Tp hp cc
ng tn hiu c cng chc nng gi l cc bus. Nh vy ta c cc bus a ch, bus d
liu v bus iu khin.
1.2.1 Khi x l trung tm (CPU)
CPU c cu to gm c n v x l s hc v lgic (ALU), cc thanh ghi, cc
khi lgic v cc mch giao tip. Chc nng ca CPU l tin hnh cc thao tc tnh
ton x l, a ra cc tn hiu a ch, d liu v iu khin nhm thc hin mt nhim
v no do ngi lp trnh a ra thng qua cc lnh (Instructions).
Bi ging Chng 1

Hnh 1-3. Khi x l trung tm
1.2.2 B nh (Memory)
Vi chu k c: thi gian truy xut l thi gian tnh t lc a ch mi xut hin
b nh cho n khi c d liu ng ng ra ca b nh.
Vi chu k ghi: thi gian truy xut l thi gian tnh t lc a ch mi xut hin
b nh cho n khi d liu a vo b nh.
Thi gian chu k (cycle time): l thi gian t lc bt u chu k b nh n khi bt
u chu k k tip.
Ngoi ra, P c th s dng thm mt s trng thi ch khi c b nh.

Hnh 1-4. Cc ng tr hon trong giao tip P vi b nh
- t
dbuf
: thi gian tr hon b m d liu (data buffer)
- t
abuf
: thi gian tr hon b m a ch (address buffer)
Bi ging Chng 1

- t
OE
: thi gian p ng ca b nh vi tn hiu cho php ng ra (ouput
enable)
- t
CS
: thi gian b nh truy xut t Chip Select
- t
ACC
: thi gian b nh truy xut t a ch, thng thng tACC = tcs
- tdec: thi gian tr hon b gii m (decoder)

nh th c b nh:
Thi gian truy xut tng cng ca h thng b nh chnh l tng thi gian tr hon
trong cc b m v thi gian truy xut (access time) b nh.
Hiu gia thi gian truy xut cn thit bi P vi thi gian truy xut tht s ca b
nh gi l bin nh th (timing margin).
- t
DS
(Data Setup): thi gian thit lp d liu cung cp bi h thng b nh
- t
DH
(Data Hold): thi gian gi d liu cung cp bi h thng b nh

Hnh 1-5. nh th c b nh

Bi ging Chng 1

nh th ghi b nh

Hnh 1-6. nh th ghi b nh
- taw: thi gian truy xut ghi (access write)
- twp: rng xung ghi ti thiu (write pulse)
- tAS: thi gian a ch hp l trc khi WR = 0
Thng thng, ta khng quan tm n a ch cho n khi xc nhn CS nn thng
tcw=taw.

1.2.3 Khi phi ghp vo/ra (I/O)

Hnh 1-7. Khi ghp ni vo ra
Bi ging Chng 1

Chu k c ghi c bn:

Hnh 1-8. Chu k c c bn
1.2.4 H thng bus
Bus a ch - Address bus
- L cc ng tn hiu song song 1 chiu ni t CPU n b nh
- rng bus: l s cc ng tn hiu, c th l 8, 18, 20, 24, 32 hay 64.
- CPU gi gi tr a ch ca nh cn truy nhp (c/ghi) trn cc ng tn
hiu ny.
- 1 CPU vi n ng a ch s c th a ch ho c 2
n
nh. V d, 1 Cpu
c 16 ng a ch c th a ch ho c 2
16
hay 65,536 (64K) nh.
Bus d liu - Data bus
- rng Bus: 4, 8, 16, 32 hay 64 bits
- L cc ng tn hiu song song 2 chiu, nhiu thit b khc nhau c th
c ni vi bus d liu; nhng ti mt thi im, ch c 1 thit b duy nht
c th c php a d liu ln bus d liu.
- Bt k thit b no c kt ni n bus d liu phi c u ra dng 3 trng
thi, sao cho n c th trng thi treo (tr khng cao) nu khng c s
dng.
Bus iu khin - Control bus
- Bao gm 4 n 10 ng tn hiu song song.
- CPU gi tn hiu ra bus iu khin cho php cc u ra ca nh hay cc
cng I/O c a ch ho. Cc tn hiu iu khin thng l: c/ ghi b
nh - memory read, memory write, c/ ghi cng vo/ra - I/O read, I/O
write.
Bi ging Chng 1

- V d, c 1 byte d liu t nh s cn n cc hot ng sau:
1.2.5 CPU a ra a ch ca nh cn c ln bus a ch.
1.2.6 CPU a ra tn hiu c b nh - Memory Read trn bus iu
khin.
1.2.7 Tn hiu iu khin ny s cho php thit b nh c a ch
ho a byte d liu ln bus d liu.
1.2.8 Byte d liu t nh s c truyn ti qua bus d liu n CPU.
1.3 nh dng d liu v biu din thng tin trong h vi x l vi iu
khin
1.3.1 Cc h m
H thp phn - Decimal
H nh phn - Binary
H16 - Hexadecimal
M BCD (standard BCD, gray code)
M hin th 7 on (7-segment display code)

Hnh 1-9.LED 7 thanh v cch m ha

M k t - Alphanumeric CODE (ASCII, EBCDIC)
Cc m h m thng dng
H 10 H 2 H 8 H 16 Binary-Coded Decimal
Reflected
Gray Code
7-Segment Display
(1=on)
8421 BCD EXCESS-3 abcdefg Display
0 0000 0 0 0000 0011 0011 0000 1111110 0
1 0001 1 1 0001 0011 0100 0001 0110000 1
2 0010 2 2 0010 0011 0101 0011 1101101 2
3 0011 3 3 0011 0011 0110 0010 1111001 3
4 0100 4 4 0100 0011 0111 0110 0110011 4
5 0101 5 5 0101 0011 1000 0111 1011011 5
6 0110 6 6 0110 0011 1001 0101 1011111 6
7 0111 7 7 0111 0011 1010 0100 1110000 7
8 1000 10 8 1000 0011 1011 1100 1111111 8
9 1001 11 9 1001 0011 1100 1101 1110011 9
10 1010 12 A 0001 0000 0100 0011 1111 1111101 A
Bi ging Chng 1

11 1011 13 B 0001 0001 0100 0100 1110 0011111 B
12 1100 14 C 0001 0010 0100 0101 1010 0001101 C
13 1101 15 D 0001 0011 0100 0110 1011 0111101 D
14 1110 16 E 0001 0100 0100 0111 1001 1101111 E
15 1111 17 F 0001 0101 0100 1000 1000 1000111 F

1.3.2 Biu din s v k t

Hnh 1-10. Bng m ASCII
Bi ging Chng 1

1.3.3 Cc php ton s hc trn h m nh phn
Php cng nh phn
Vo Ra
A B B
IN
D B
OUT

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Php tr nh phn
Vo Ra
A B B
IN
D B
OUT

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Php tr nh phn, chnh l php cng nh phn vi s b 2 ca s tr, trng hp
kt qu dng:

Trng hp kt qu m:

Php nhn, php chia, ngh sinh vin t nghin cu.

Bi ging Chng 2
Vi x l - Vi iu khin H vi x l Intel 80x86

CHNG 2.
H VI X L INTEL 80x86

Mc tiu:
Hiu c cu trc phn cng ca h vi x l; hiu v vn dng c cc ch a
ch; nm c tp lnh v lp trnh cho h vi x l 80x86

Tm tt chng:

Cu trc phn cng ca b vi x l 8086
Ch a ch
Tp lnh
Cc mch ph tr
Biu thi gian ghi/c
Lp trnh hp ng (Assembly) cho vi x l 80x86

Bi ging Chng 2

2.1 Cu trc phn cng ca b vi x l 8086
2.1.1 Tng quan

Hnh 2-1.Tng quan v phn cng b x l
Control Unit (CU) to ra tt c cc tn hiu iu khin trong CPU. N khi to
cc thanh ghi khi m ngun, to ra cc tn hiu ly lnh cho ALU. Khi iu
khin c th c thc hin hon ton bi phn cng (iu khin cng, v d nh
s dng mt b m trng thi v mt mng logic kh lp trinh) hay kt hp gia
cc lnh phn mm (vi lnh c lu tr trong CPU) v phn cng (b iu khin
vi chng trnh. C hai h vi x l Intel 8086 v Motorola 68000 u s dng cc
b iu khin vi chng trnh.
Registers l cc b nh nh, nhanh, thng c s dng lu d liu v a
ch gn vi (tng ng vi) cc m lnh ca chng trnh.
ALU thc hin cc php ton s hc v logic
2.1.2 Cu trc bn trong v s hot ng
C 8088/8086 p dng c ch x l song song.
Cha 2 n v x l: n v thi hnh (EU) v n v giao tip bus (BIU); hot
ng ng thi.
BIU a ra tn hiu a ch, ly lnh t b nh, c d liu t cng I/O v b nh,
ghi d liu ra cc cng I/O v b nh. C ngha l BIU qun l ton b vic trao
i d liu trn cc bus phc v cho n v thi hnh EU.
EU a ra cc yu cu cho BIU v ni ly lnh v d liu, gii m v thi hnh cc
lnh.
Bi ging Chng 2

Hnh 2-2.S hot ng ca CPU
S khi bn trong ca 8086

Hnh 2-3.S khi bn trong 8086
Bi ging Chng 2

n v giao tip Bus (BIU)
Thc hin cc hot ng hng bus: nh ly lnh, c/ghi d liu t/ln b nh,
vo/ra d liu vi thit b ngoi vi.
Thc hin cc chc nng khc nh qun l hng i lnh v thu thp d liu.
- 8-bit (16-bit) bi-directional data bus for 8088 (8086).
- 20-bit address bus can address any one of the 2
20
(1,048,576) bytes.
Cha cc thanh ghi on, con tr lnh, b cng to a ch, logic iu khin bus v 1
hng i lnh.
S dng hng i lnh cung cp kin trc ng ng (ly trc 4 (6) byte m lnh
i vi 8088 (8086) sau lu tr v truy xut cc m lnh theo th t FO).
n v x l lnh (EU)
C nhim v gii m v thc hin lnh.
Cha: arithmetic logic unit (ALU), status and control flags, general purpose
registers, v temporary-operand register.
EU truy xut lnh t u ca hng i lnh v d liu t cc thnah ghi chc nng
chung.
N c lnh, gii m chng v to ra cc a ch ton hng nu cn, chuyn chng
cho BIU v yu cu thc hin chu k c/ghi b nh hay I/O v thc hin cc hot
ng c th c ch nh bi lnh trn cc ton hng.
Trong qu trnh thi hnh lnh, EU c th kim tra trng thi ca cc c iu khien
v cp nht cc c ny da trn kt qu ca vic thc thi lnh.
Cc thanh ghi c
Cc c ch th tnh trng ca b vi x l cng nh iu khin s hot ng ca n.
Mt thanh ghi c l 1 flip-flop m n ch th mt s tnh trng c to bi vic thc
thi 1 lnh hay cc hot ng iu khin c th ca EU. Thanh ghi c 16-bit trong EU c
9 c.
- Cc c iu kin - conditional flags: C 6 c c gi l c iu kin. Chng
c lp hay xo l bi EU, da trn kt qu ca cc php ton s hc.
- C iu khin - control flags : 3 c cn li trong thanh ghi c c s dng
iu khin mt s hot ng ca vi x l. Chng c gi l cc c iu
khin.
Bit pos 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Func U U U U OF DF IF TF SF ZF U AF U PF U CF
- Carry Flag (CF)- set by carry out of MSB.
- Parity Flag (PF)- set if result has even parity.
- Auxiliary carry Flag (AF)- for BCD
- Zero Flag (ZF)- set if results = 0
- Sign Flag (SF) = MSB of result
Bi ging Chng 2

- TF- single step trap flag
- IF- interrupt enable flag
- DF- string direction flag
- Overflow Flag (OF)- overflow flag
Cc c iu kin
- c nh - carry flag (CF)- ch th nh mt sau php cng hay mn 1 sau
php tr, n cng cn ch th cc iu kin .
- c chn l - parity flag (PF)- c gi tr logic 0 vi s l, gi tr logic 1
vi s chn.
- c nh ph - auxiliary carry flag (AF)- c ngha quan trng i vi php
cng v php tr cc s BCD; v gi s nh (mn) sau php cng (tr) gia
bit th 3 v bit th 4. Ch c s dng vi lnh DAA v DAS hiu chnh
gi tr ca AL sau php cng (tr) s BCD.
- c khng - zero flag (ZF)- ch th rng kt qa ca php ton s hc hay
logic l bng 0.
- c du - sign flag (SF)- ch th du s hc ca kt qu sau 1 php ton s hc.
- c trn - overflow flag (OF)- xy ra khi cc s c du c cng thm hay
tr i. Mt ch th trn c ngha l kt qu vt qu kh nng ca my
(dung lng nh ca ton hng).
Cc c iu khin
Cc c iu khin c lp hay xo thng qua cc lnh c bit trong chng trnh
ngi dng. Ba c iu khin l:
- c by - trap flag (TF) - c s dng cho vic chy chng trnh tng lnh
mt;
- c ngt - interrupt flag (IF) - c s dng cho php hay cm ngt ca 1
chng trnh;
- c hng - direction flag (DF) - c s dng vi cc lnh chui.
Khng c lnh ring lp c TF.
Cc thanh ghi mc ch chung (a nng)
EU c tm thanh ghi a nng 8 bit, c k hiu l AH, AL, BH, BL, CH, CL, DH,
DL. Cc thanh ghi ny c th c s dng c lp lu tr tm thi d liu 8 bit.
Cc cp AH-AL, BH-BL, CH-CL, v DH-DL c th c s dng t hp to
thnh cc thanh ghi 16 bit: AX, BX, CX, v DX.
Thanh ghi AL cn c gi l thanh ghi tch lu (accumulator). N c 1 s tnh nng
m cc thanh ghi khc khng c
Bi ging Chng 2

2.1.3 M t chc nng cc chn

Hnh 2-4. S chn 8086/8088
8088 v 8086 l gn tng t nh nhau, ch khc ch 8088 c 8bit d liu cn
8086 c 16 bit d liu ngoi.
C 2 b x l u c:
- rng bus d liu ni l 16 bit
- 20 ng a ch (16 address/data + 4 address/status), cho php a ch ho
khng gian b nh ti a l 1Mbyte ch dn knh address/data pins
(8088 only multiplexes 8 pins)
- 2 ch hot ng (maximum v minimum mode)
- Cng 1 tp lnh
2.2 Ch a ch
2.2.1 Khi nim ch a ch
Trc khi i vo cc ch a ch ca Vi x l 8086 ta ni qua v cch m ho lnh
trong vi x l 8086.
Lnh ca b vi x l c ghi bng cc k t di dng gi nh ngi s dng d
nhn bit. i vi bn thn b vi x l th lnh cho n c m ho di dng cc s 0
v 1 (cn gi l m my) v l dng biu din thng tin duy nht m my c th hiu
c. V lnh cho b vi x l c cho di dng m nn sau khi nhn lnh, b vi x l
phi thc hin gii m lnh ri sau mi thc hin lnh
Mt lnh c th c di mt vi byte tu theo b vi x l. i vi vi x l 8086
mt lnh c di t 1 n 6 byte. Ta s dng lnh MOV gii thch cch ghi lnh ni
chung ca 8086.
Bi ging Chng 2

1 0 0 0 1 0
D W MOD REG R/M Opcode
Byte 1 Byte 2 Byte 3 Byte 4
DispL DispH
Hoc
a ch trc tip
phn thp
Disp: Displacement (dch chuyn) a ch trc tip
phn cao

Dng thc cc byte m lnh ca lnh MOV
T y ta thy m ho lnh MOV cn t nht 2 byte. Trong 6 bit u dng
cha m lnh, 6 bit ny lun l 100010. i vi cc thanh ghi on th iu ny li khc.
Bit W dng ch ra rng mt byte (W=0) hoc mt t (W=1) s c chuyn i. Trong
thao tc chuyn d liu, mt ton hng lun bt buc phi l thanh ghi. B vi x l s
dng 2 hoc 3 bit (REG) m ho cc thanh ghi trong CPU nh sau:

Thanh ghi on M
CS 01
DS 11
ES 00
SS 10

Bit D l hng i ca d liu. D = 1 th d liu n thanh ghi, D = 0 th d liu i ra
t thanh ghi.
Hai bit MOD (ch ) cng vi ba bit R/M (thanh ghi/b nh) to ra 5 bit dng
ch ra ch a ch cho cc ton hng ca lnh. Bng 2.2 cho ta thy cch m ho cc
ch a ch.
Bng 2.2 Phi hp MOD v R/M to ra cc ch a ch
MOD
R/M
00 01 10 11
W=0 W=1
000 [BX+SI] [BX+SI]+d8 [BX+SI]+d16 AL AX
001 [BX+DI] [BX+DI]+d8 [BX+DI]+d16 CL CX
010 [BP+SI] [BP+SI]+d8 [BP+SI]+d16 DL DX
011 [BP+DI] [BP+DI]+d8 [BP+DI]+d16 BL BX
100 [SI] [SI]+d8 [SI]+d16 AH SP
101 [DI] [DI]+d8 [DI]+d16 CH BP
110 D16(/c trc tip) [BP]+d8 [BP]+d16 DH SI
111 [BX] [BX]+d8 [BX]+d16 BH DI
Thanh ghi M
W = 1 W = 0
AX AL 000
BX BL 011
CX CL 001
DX DL 010
SP AH 100
DI BH 111
BP CH 101
SI DH 110
Bi ging Chng 2

V d 1: MOV CL, [BX]
Byte 2 Byte 1
Opcode R/M REG MOD W D
0 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1

M lnh MOV: 100010
D = 1: Chuyn ti thanh ghi
W = 0: Chuyn 1 byte
MOD: ch 00 v R/M l 111
REG: 001 m ho CL
V d 2: MOV AH, 2Ah
Byte 2 Byte 1
Opcode R/M REG MOD W D
0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 0
2Ah
Byte 3

M lnh MOV: 100010
W = 0: Chuyn 1 byte
MOD: ch 00 v R/M l 110: a ch trc tip
REG: 100 m ho AH
2Ah = 00101010 d liu cn chuyn ti AH
V d 3: MOV CX, [BX][SI]+DATA
DATA l mt bin trong b nh, l a ch lch v l mt hng (v d nh 0BFF).
Lnh ny s s dng 4 byte t chc nh sau:
Byte 3
FFh
1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0
D W MOD REG R/M Opcode
Byte 1 Byte 2
1 0 0 0 0 1 0 1
0Bh
Byte 4

M lnh MOV: 100010
W =1: Chuyn 1 Word
MOD: ch 10 (offset 16 bit) v R/M l 000 (s dng thanh ghi c s
BX v thanh ghi ch s SI).
REG: 001 m ho thanh ghi CX.
Nh vy trong k hiu nh phn v hexa ta c.
Byte 1 Byte 2 Byte 3 Byte 4
10001011 10001000 11111111 00001011
Bi ging Chng 2

8Bh 88h FFh 0Bh
2.2.2 Cc ch a ch
Ch a ch (addressing mode) l cch CPU tm thy ton hng cho cc lnh
ca n khi hot ng. Mt b vi x l c th c nhiu ch a ch. Cc ch a ch
ny c xc nh ngay t khi ch to v khng th thay i c. B vi x l
8086/8088 c 9 ch a ch sau:
- Ch a ch thanh ghi.
- Ch a ch tc th.
- Ch a ch trc tip.
- Ch a ch gin tip qua thanh ghi.
- Ch a ch tng i c s.
- Ch a ch tng i ch s.
- Ch a ch tng i c s ch s.
- Ch a ch chui (String) mng.
- Ch a ch cng (Port).
CH A CH THANH GHI
Trong ch a ch ny ngi ta s dng cc thanh ghi c sn trong CPU nh l cc
ton hng cha d liu cn thao tc, v vy khi thc hin c th t tc truy nhp
cao hn so vi cc lnh truy nhp n b nh.
V d: MOV BX, DX ;copy noi dung DX vao BX
ADD AX, BX ;AX=AX+BX
CH A CH TC TH
Trong ch ny ton hng ch l mt thanh ghi hay mt nh, cn ton hng
ngun l mt hng s. Ta c th dng ch a ch ny np d liu cn thao tc vo
bt k thanh ghi no (tr thanh ghi on v thanh ghi c) v bt k nh no trong on
d liu DS.
V d:
MOV CL, 100 ;chuyen 100 vao CL.
MOV AX, 0BC8h ;chuyen 0BC8h vao AX de roi
MOV DS, AX ;copy noi dung AX vao DS (vi
;khong duoc chuyen truc tiep vao thanh ghi doan).
MOV [BX], 20 ;chuyen 20 vao o nho tai dia chi
;DS:BX.
CH A CH TRC TIP
Trong ch a ch ny mt ton hng cha a ch lch ca nh dng cha d
liu, cn ton hng kia c th l thanh ghi m khng c l nh.
V d:
MOV AL, [0243H];chuyen noi dung o nho DS:0243 vao AL
Bi ging Chng 2

MOV [4320], CX ;chuyen noi dung CX vao hai o nho
;lien tiep DS:4320 va DS:4321
CH A CH GIN TIP QUA THANH GHI
Trong ch a ch ny mt ton hng l mt thanh ghi c s dng cha a
ch lch ca nh d liu, cn ton hng kia ch c th l thanh ghi m khng c l
nh. V d:
MOV AL, [BX] ;copy noi dung o nho co dia chi DS:BX
MOV [SI], CL ;copy noi dung CL vao o nho co dia ch
;DS:SI
MOV [DI], AX ;copy noi dung AX vao hai o nho lien
;tiep co dia chi DS:DI va DS:(DI+1)
CH A CH TNG I C S
Trong ch a ch ny cc thanh ghi c s nh BX v BP v cc hng s
biu din cc gi tr dch chuyn c dng tnh a ch hiu dng ca ton hng
trong cc vng nh DS v SS. V d:
MOV CX, [BX]+10 ;copy noi dung hai o nho lien tiep
;co dia chi DS:BX+10 va DS:BX+11
;vao CX
MOV CX, [BX+10] ;cach viet khac cua lenh tren
MOV CX, 10+[BX] ;cach viet khac cua lenh tren
MOV AL, [BP]+5 ;chuyen noi dung o nho co dia chi
;SS:BP+5 vao AL
Quan st trn ta thy: 10 v 5 l cc dch chuyn ca cc ton hng tng ng.
BX+10, BP+5 gi l a ch hiu dng.
DS:BX+10, SS:BP+5 chnh l a ch logic ng vi a ch vt l.
CH A CH TNG I CH S
Trong ch a ch ny cc thanh ghi ch s nh SI v DI v cc hng s biu din
cc gi tr dch chuyn c dng tnh a ch hiu dng ca ton hng trong cc
vng nh DS. V d
MOV CX, [SI]+10 ;copy noi dung hai o nho lien tiep
;co dia chi DS:SI+10 va DS:SI+11 vao CX
MOV CX, [SI +10] ;cach viet khac cua lenh tren
MOV CX, 10+[SI] ;cach viet khac cua lenh tren
MOV AL, [DI]+5 ;chuyen noi dung o nho co dia chi
;DS:DI+5 vao AL
CH A CH TNG I CH S C S
Kt hp hai ch a ch ch s v c s ta c ch a ch ch s c s. Trong
ch ny ta dng c hai thanh ghi c s ln thanh ghi ch s tnh a ch ca ton
Bi ging Chng 2

hng. Nu ta dng thm c thnh phn biu din s dch chuyn ca a ch th ta c ch
a ch tng hp nht: Ch a ch tng i ch s c s. V d:
MOV BX, [BX]+[SI]+10 ;chuyen noi dung hai o nho
;lien tiep co dia chi DS:BX+SI+10 va DS:BX+SI+11 vao CX
MOV AL, [BP+DI+5] ;copy ni dung th: DS:BP+DI+5 vao AL
Cc ch a ch trnh by trn c th tm tt li trong bng sau:
Ch a ch Ton hng Thanh ghi on ngm nh
Thanh ghi Reg
Tc th Data
Trc tip [offset] DS
Gin tip qua thanh ghi
[BX]
[SI]
[DI]
DS
DS
DS
Tng i c s
[BX]+Disp
[BP]+Disp
DS
SS
Tng i ch s
[DI]+Disp
[SI]+Disp
DS
DS
Tng i ch s c s
[BX]+[DI]+Disp
[BX]+[SI]+Disp
[BP]+[DI]+Disp
[BP]+[SI]+Disp
DS
DS
SS
SS
Ch : Reg: Thanh ghi, Data: D liu tc th, Disp: Dch chuyn.
CH A CH CHUI (STRING) MNG
Mt chui (string) l mt dy cc byte hoc word lin tip trong b nh. Cc lnh
thao tc vi chui khng s dng bt k mt ch a ch no trn. Mt chui c th
c di ti a ln ti 64K-bytes (mt segments). Ch a ch chui s dng cc
thanh ghi SI, DI, DS v ES. Vi tt c cc lnh thao tc chui u s dng SI tr vo
byte u tin ca chui ngun v DI tr vo byte u tin ca chui ch.
V d: Gi s: DS=1000h, ES=2000h, SI=10h, DI=20h)
MOVSB ;Sao chp chui t 10010h n 20020h
CH A CH CNG (PORT)
Trong h vi x l 80x86 ca Intel c khng gian a ch cho b nh v cng vo/ra l
tch bit nhau. Khng gian a ch cng c th ln n 65536 cng (64K-ports).
a ch ca mt cng c th c xc nh bi mt hng gi tr kiu byte (phm vi =
0..255)
V d:
IN AL, 40h ;c cng sao chp ni dung ti
;cng c a ch 40h v thanh ghi AL
Bi ging Chng 2

OUT 80h, AL ;Ghi cng gi d liu trong thanh
;ghi AL ti cng c a ch 80h
a ch ca cng cng c th c xc nh gin tip qua thanh ghi (Khi ny phm
vi ti s l 65536 cng).
V d:
IN AL, DX ;c cng c a ch l ni dung ca
;thanh ghi DX
OUT DX, AX ;Ghi mt word trong AX ti cng c a
;ch l ni dung ca thanh ghi DX.
2.2.3 Gii m a ch
Mi mch nh ni ghp vi CPU cn phi c CPU quy chiu ti mt cch chnh
xc khi thc hin cc thao tc c ghi. iu c ngha l mi mch nh phi c gn
cho mt vng ring bit c a ch xc nh nm trong khng gian a ch tng th ca
b nh. Vic gn a ch c th cho mch nh c thc hin nh mt xung chn v
c ly t mch gii m a ch. Khi CPU mun thc hin trao i thng tin vi b nh
hay thit b ngoi vi, n a ra a ch ca thit b cn trao i trn BUS a ch, sau
qua mt b gii m a ch s xut tn hiu chn chip CS (Chip Select) hoc tn hiu cho
php CE (Chip Enable) gi ti b nh hay thit b vo/ra cn thit. B nh hay thit b
vo/ra no nhn c tn hiu chn s c php trao i d liu vi CPU cn cc mch
giao tip khc s b cm (u ra trng thi Hi Z).
V nguyn tc mt b gii m a ch thng c cu to nh sau (hnh 2.4.4)
CS2
CS1
Mch gii
m a ch
CSn
Tn hiu
a ch
Tn hiu
iu khin
Cc tn hiu
chn v

Hnh 2-5. Mch gii m a ch tng qut
Trong phn ny ta a ra 3 cch gii m a ch:
- Gii m a ch bng cc mch NAND.
- Gii m a ch bng mch gii m 74LS138.
- Gii m a ch dng PROM.
Thc hin gii m bng cc mch NAND
Bng cc mch ca NAND ta c th xy dng c mch gii m a ch n gin
vi s u ra hn ch. Ta phi a n u vo ca mch ca nhiu li vo mt t hp
thch hp ca cc bit a ch nhn c u ra ca n tn hiu chn v cho mch
nh (hnh 2.4.4a).
y l mch gii m cho EPROM 2716, xung chn v s tc ng khi ta c b nh
c a ch trong khong FF800H FFFFFH. 9 bit a ch phn cao ca Bus a ch (t
Bi ging Chng 2

A11 A19) mc 1 s phi hp cng xung IO/M ( c o) to ra xung chn
vng 2KB t ti a ch cao nht trong khng gian a ch ca 8086. Mi nh c th
trong 2KB ca mch nh EPROM 2716 s do cc bit thp cn li ca Bus a ch (A0
A10) chn ra.
BUS A
ca 8086
2716
(2Kx8)
A0-A10
D0-D7
BUS D
ca 8086
A11
A12
A19
IO/M
RD
CE OE

Hnh 2-6.Mch gii m NAND
A19A18A17A16 A14 A15 A12 A13 A8 A9 A10 A11 A7A6A5A4 A0 A1 A2 A3
0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
=FF800H
=FFFFFH
Phn a ch khng i Phn a ch thay i

Mch gii m dng mch NAND
Thc hin gi m bng mch gii m 74LS138
Khi ta mun c nhiu u ra chn v t b gii m m
vn dng cc mch logic th khi thit k mch s rt cng
knh do phi s dng s lng cc mch ca tng ln.
Trong trng hp nh vy ta thng s dng cc mch
gii m c sn. Mt trong cc mch gii m c s dng
rng ri nht l 74LS138. S hnh dng ngoi v bng
chc nng ca 74LS138.
V d: S dng mch nh EPROM 2764 (8Kx8) c a
ch t F0000H FFFFFH. Ta s dng mch gii m a
ch 74LS138 thc hin gii m a ch.

Cc u vo
Chn Cho php
Cc u ra
C B A E3 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
x x x 1 x x 1 1 1 1 1 1 1 1
x x x x 1 x 1 1 1 1 1 1 1 1
x x x x x 0 1 1 1 1 1 1 1 1
0 0 0 0 0 1 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 0 1 1 1 1 1 1
A
1
B
2
C
3
E1
6
E2
4
E3
5
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9
Y7
7
U1
74HC138
Hnh 2-7.74HC138

Bi ging Chng 2

0 1 0 0 0 1 1 1 0 1 1 1 1 1
0 1 1 0 0 1 1 1 1 0 1 1 1 1
1 0 0 0 0 1 1 1 1 1 0 1 1 1
1 0 1 0 0 1 1 1 1 1 1 0 1 1
1 1 0 0 0 1 1 1 1 1 1 1 0 1
1 1 1 0 0 1 1 1 1 1 1 1 1 0
x: khng quan tm.
Hnh dng ngoi v bng chc nng ca 74LS138
T bng chc nng ta thy Y0 = 0 khi m cc u vo chn c C = 0, B = 0, A = 0.
Cc u vo cho php G2A = 0, G2B = 0, G1 = 1. V vy s ghp ni 74LS138 vi
EPROM 2764
Cc bit a ch A16 A19 c t bng 1 trong A16, A17, A18 a qua mch
logic NAND v a vo G2A.
Tn hiu IO/M a vo chn G2B
A13, A14, A15 c t bng 0 v ln lt a vo chn A, B, C.
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
A
B
C
G2A
G2B
G1
BUS D
ca 8086
A19
A18
A17
A16
IO/M
A15
A14
A13
Cc chn chn v
cho 7 vi mch
2764 khc
FE000H-FFFFFH
RD
F0000H-F1FFFH
D0-D7
A0-A12
2764
(8Kx8)
BUS A
ca 8086
OE CE

Hnh 2-8. Mch gii m dng 74LS138
Ti v d ny ta thy: Mch gii m a ch 74LS138 c s lng u vo a ch v
u vo cho php b hn ch. Nu ta c s lng u vo a ch ln m ta li phi gii
m y th thc hin b gii m hon chnh ta vn phi dng thm cc mch logic
ph. y cng l l do ngi ta thay th cc b gii m kiu ny bng cc b gii m
PROM. Vi u im chnh l chng c rt nhiu u vo cho cc bit a ch v v th rt
thch hp trong h vi x l sau ny vi khng gian a ch ln.
Bi ging Chng 2

2.3 Tp lnh
2.3.1 Gii thiu chung
Tp lnh ca h vi x l 80x86 m bo tng thch th h sau vi th h trc. iu
c ngha l cc chng trnh vit cho 8086 vn chy c trn cc b vi x l mi
hn m khng phi thay i (khng m bo th t ngc li). Tp lnh ca mt b vi
x l thng c rt nhiu lnh (hng trm lnh), v th m vic tip cn v lm ch
chng l trng i kh khn.
C nhiu cch trnh by tp lnh ca b vi x l: Trnh by theo nhm lnh hoc theo
th t abc. c th nhanh chng v d dng s dng cc lnh c bn v lp trnh c
ngay, ta s tip cn tp lnh ca b vi x l theo nhm cc thao tc c bn trong qu
trnh x l v iu khin. Vi mi thao tc ni trn, ta lm quen vi mt vi lnh tiu
biu (c gi c th tra cu thm cc lnh khc trong phn ph lc). Cc chc nng c
bn ca mt b vi x l thng gm:
- Nhm cc lnh vn chuyn (sao chp) d liu.
- Nhm cc lnh tnh ton s hc.
- Nhm cc lnh tnh ton logic.
- Nhm cc lnh dch, quay ton hng.
- Nhm cc lnh nhy (r nhnh).
- Nhm cc lnh lp.
- Nhm cc lnh iu khin, c bit khc.
2.3.2 Cc nhm lnh
Nhm cc lnh vn chuyn (sao chp) d liu
1. LDS Load register and DS with words from memory (np mt t (t b nh) vo
thanh ghi cho trong lnh v mt t tip theo vo DS).
Dng lnh: LDS ch, Ngun
Trong :
- ch l mt trong cc thanh ghi: AX, BX, CX, DX, SP, BP, SI, DI.
- Ngun l nh trong on DS c ch ra trong lnh.
y l lnh np vo thanh ghi chn v vo DS t 4 nh lin tip. Mt trong
nhng ng dng ca lnh ny l lm cho SI v DS ch vo a ch u ca vng nh
cha chui Ngun trc khi n lnh thao tc chui.
Cc c b thay i: khng.
V d:
LDS SI, STR_PTR
Np vo thanh ghi SI ni dung 2 nh STR_PTR v STR_PTR+1 v np vo
DS ni dung 2 nh STR_PTR+3 v STR_PTR+4. cc nh ny u nm trong on
Bi ging Chng 2

d liu DS v cha a ch ca chui Ngun. Do vy sau DS:SI ch vo u chui
Ngun cn thao tc.
2. LEA Load Effective Address (np a ch hiu dng vo thanh ghi).
Dng lnh: LEA ch, Ngun
Trong :
- ch l mt trong cc thanh ghi: BX, CX, DX, BP, SI, DI.
- Ngun l tn bin trong on DS c ch r trong lnh hoc nh c th.
cha ch lch ca Ngun, hoc
cha ch hiu dng ca Ngun
y l lnh tnh a ch lch ca bin hoc a ch ca nh chn lm Ngun
ri np vo thanh ghi chn.
V d:
LEA DX, Label ;nap dia chi lech cua Label vao DX
LEA CX, [BX][DI] ;nap vao CX dia chi hieu dung do
;BX va DI chi ra EA=BX+DI
3. LES Load register and ES with words from memory (np mt t (t b nh) vo
thanh ghi cho trong lnh v mt t tip theo vo ES).
Dng lnh: LES ch, Ngun
Trong :
- ch l mt trong cc thanh ghi: AX, BX, CX, DX, SP, BP, SI, DI.
- Ngun l nh trong on DS c ch ra trong lnh.
y l lnh np vo thanh ghi chn v vo ES t 4 nh lin tip. Mt trong
nhng ng dng ca lnh ny l lm cho DI v ES ch vo a ch u ca vng nh
cha chui Ngun trc khi n lnh thao tc chui.
V d:
LDS DI, [BX]
Np vo thanh ghi DI ni dung 2 nh BX v BX+1 v np vo ES ni dung 2
nh BX+3 v BX+4. cc nh ny u nm trong on d liu ES v cha a ch ca
chui Ngun. Do vy sau ES:SI ch vo u chui Ngun cn thao tc.
4. MOV MOV a byte or word (chuyn mt byte hay t)
Dng lnh: MOV ch, Ngun
M t: chNgun
Trong ton hng ch v Ngun c th tm c theo cc ch a ch khc
nhau, nhng phi c cng di v khng c php ng thi l hai nh hoc hai
thanh ghi on.
Bi ging Chng 2

V d:
MOV AL, AH ;ALAH
MOV CX, 50 ;CX50
MOV DL, [SI] ;DL{DS:SI}
5. MOVS/MOVSB/MOVSW Move String byte or String word (chuyn mt phn t
ca mt chui sang mt chui khc).
Dng lnh:
MOVS Chui_ch, Chui_Ngun
MOVSB
MOVSW
M t: Phn t chui_chphn t chui_Ngun
Lnh ny dng chuyn tng byte hay tng t ca chui Ngun sang chui
ch, trong .
- DS:SI l a ch ca phn t trong chui Ngun.
- ES: DI l a ch ca phn t trong chui ch.
- Sau mi ln chuyn th SISI1, DIDI1 hoc SISI2, DIDI2 mt cch t
ng tu thuc c hng DF l 0 hay 1 v chui l chui byte hay t.
C hai cch ch ra chui l chui byte hay chui t. Cch u tin l ta khai
bo chui_ch, chui_Ngun l loi g ngay t u chng trnh. Cch th hai l ta
thm vo lnh MOVS ui B cho chui byte hoc ui W cho chui t (xem r
trong lnh COMPS).
V d:
CLD ;xoa co huong lam viec voi chuoi theo chieu
MOV DI, OFFSET Chuoi_dich
;lay dia chi lech cua chuoi_dich tai ES vao DI
MOV SI, OFFSET Chuoi_goc
;lay dia chi lech cua chuoi_goc tai DS vao SI
MOVSB ;chuyen 1byte, SI va DI tang them 1

on chng trnh m phng hot ng ca lnh mov:
ORG 100h ; this directive required for a simple 1
;segment .com program.
MOV AX, 0B800h ; set AX to hexadecimal value of B800h.
MOV DS, AX ; copy value of AX to DS.
MOV CL, 'A' ; set CL to ASCII CODE of 'A', it is 41h.
MOV CH, 1101_1111b ; set CH to binary value.
MOV BX, 15Eh ; set BX to 15Eh.
MOV [BX], CX ; copy contents of CX to memory at
Bi ging Chng 2

; B800:015E
RET ; returns to operating system.
6. OUT Output a byte or a work to a port.
Dng lnh: OUT Port, Acc
M t: Acc{Port}
Trong {port} l d liu ca cng c a ch port. Port l a ch 8 bit ca cng, n c
th l cc gi tr trong khong 00...FFH. Nh vy c th c cc kh nng sau y.
- Nu Acc l AL th d liu 8 bit c a ra cng Port.
- Nu Acc l AX th d liu 16 bit c a ra cng Port v Port + 1.
C mt cch khc cha a ch cng l thng qua thanh ghi DX. Khi dng thanh ghi
DX cha a ch cng ta c kh nng a ch ho cng mm do hn. Lc ny a ch cng
nm trong di 0000H FFFFH v vit lnh theo dng:
OUT DX, Acc
V d:
OUT 45H, AL ;dua du lieu tu AL ra cong 45H
MOV DX, 0 ;xoa DX
MOV DX, 00FFH ;nap dia chi cong vao DX
OUT DX, AX ;dua du lieu tu AX ra 00FFH
7. POP Pop word from top of Stack (ly li 1 t vo thanh ghi t nh ngn xp)
Dng lnh: POP ch
M t:
ch{SP}
SPSP+2
Ton hng ch ch c th l cc thanh ghi a nng, thanh ghi on (nhng khng c
l thanh ghi on m CS) hoc nh.
V d:
POP DX ;lay 2 byte tu dinh ngan xep dua vao DX
8. POPF Pop word from top of Stack to Flag register (ly 1 t vo thanh ghi c t nh ngn
xp).
Dng lnh: POPF
M t:
FR{SP}
SPSP+2
Chuyn cc bit xc nh ca t nh ca Stack (c SP tr ti) ti cc c v bng
cch n thay th tt c cc c hin thi.
Bi ging Chng 2

Cc c b thay i: tt c cc c.
9. PUSH Push word on the Stack (ct 1 t vo ngn xp)
Dng lnh: PUSH Ngun
M t:
SPSP-2
Ngun{SP}
Ton hng ch ch c th l cc thanh ghi a nng, thanh ghi on(k c CS) hoc
nh.
V d:
PUSH BX
;cat BX vao ngan xep tai vi tri do SP chi ra
10. PUSHF Push Flag register to the Stack (ct thanh ghi c vo ngn xp)
Dng lnh: PUSHF
M t:
SPSP-2
FR{SP}
PUSH gim SP i 2 byte v nh n chuyn tt c cc c ti nh ca Stack.
V d:
PUSH BX
;cat BX vao ngan xep tai vi tri do SP chi ra
11. XCHG Exchange (hon i ni dung hai ton hng)
Dng lnh: XCHG ch, Ngun
M t: ch Ngun
Ton hng ch v Ngun phi c cng di, khng c ng thi l 2 nh cng
khng c l thanh ghi on. Sau lnh XCHG ton hng ny cha ni dung c ca ton hng
kia v ngc li.
V d:
XCHG AH, AL ;trao noi dung AH va AL
XCHG AX, BX ;trao noi dung AX va BX
Nhm cc lnh tnh ton s hc
12. ADC Add with Carry (cng c nh)
Dng lnh: ADC ch, Ngun
M t: ch ch + Ngun + CF
Bi ging Chng 2

Cng hai ton hng ch v Ngun vi c CF kt qu lu vo ch.
Cc c b thay i: AF, CF, OF, PF, SF, ZF.
V d:
ADC AL, 74H ;ALAL+74+CF
ADC CL, BL ;CLCL+BL+CF
ADC DL, [SI] ;DLDL+(DS:SI)+CF
13. ADD Add (cng hai ton hng)
Dng lnh: ADD ch, Ngun
M t: ch ch + Ngun
Cng hai ton hng ch v Ngun kt qu lu vo ch.
V d:
ADD DX, CX ;DXDX+CX
ADD AX, 400 ;AXAX+400
14. DEC Decrement (gim byte hay word i mt gi tr)
Dng lnh: DEC ch
DEC tr ton hng ch i 1. Ton hng ch c th l byte hay word.
Cc c b thay i: AF, OF, PF, SF, ZF.
V d:
MOV BX, 1200H ;chuyen 1200H vao BX
DEC BX ;BX=11FFH
15. DIV Division (chia khng du)
Dng lnh: DIV Ngun
Ton hng Ngun l s chia. Tu theo di ton hng Ngun ta c hai trng hp b
tr php chia.
- Nu Ngun l l s 8 bit: AX/Ngun, thng vo AL, s d vo AH
- Nu Ngun l s 16 bit: DXAX/Ngun, thng vo AX, s d vo DX
Nu thng khng phi l s nguyn n c lm trn theo s nguyn st di. Nu
Ngun bng 0 hoc thng thu c ln hn FFH hoc FFFFH (tu theo di ca ton hng
Ngun) th 8086 thc hin lnh ngt INT 0.
V d:
MOV AX, 0033H ;chuyen 0033H vao AX
MOV BL, 25
DIV BL ;AL=02H va AH=01H
16. IDIV Integer Division (chia c du)
Dng lnh: IDIV Ngun
Bi ging Chng 2

Thc hin mt php chia c du thanh ghi tng (v phn m rng ca n) cho ton hng
Ngun.
- Sau php chia AL (AX) cha thng s (s c du), AH (DX) cha s d (s c
du).
- Du ca s d trng vi du ca s b chia.
- Nu Ngun = 0 hoc thng nm ngoi di -128+127 hoc -3276832767 (tu
theo di Ngun) th 8086 thc hin lnh ngt INT 0.
V d:
IDIV CL
IDIV BX
17. IMUL Integer Multiplication (nhn c du)
Dng lnh: IMUL Ngun
Tu theo di ton hng Ngun ta c 2 trng hp b tr php nhn, ch ngm
nh cho s b nhn v kt qu.
- Nu Ngun l s c du 8 bit: ALxNgun. Sau khi nhn AXtch.
- Nu Ngun l s c du 16 bit: AXxNgun. Sau khi nhn DXAXtch.
Nu tch thu c nh, khng lp y ht c cc ch dnh cho n th cc bit
khng dng n c thay bng bit du.
Nu byte cao (hoc 16 bit cao) ca 16 (hoc 32) bit kt qu ch cha cc bit du th
CF = OF = 0.
Nu byte cao (hoc 16 bit cao) ca 16 (hoc 32) bit kt qu cha mt phn kt qu
th CF = OF = 1.
Nh vy CF v OF bo cho ta bit kt qu cn di bao nhiu.
Cc c b thay i: CF, OF.
V d:
IMUL CL
18. IN Input data from a port (c d liu t cng vo thanh ghi Acc).
Dng lnh: IN Acc, a_ch_cng
Lnh IN truyn mt byte hoc mt t t mt cng vo ln lt ti thanh ghi AL
hoc AX. a ch ca cng c th c xc nh l mt hng tc th kiu byte cho php truy
nhp cc cng t 0255 hoc thng qua mt s c a ra trc trong thanh ghi
DX m cho php truy nhp cc cng t 065535.
V d:
IN AL, 45H ;doc mot byte tu mot cong duoc xac
;dinh trong che do tuc thi
IN AX, 0046H ;doc hai byte tu mot cong duoc xac
Bi ging Chng 2

;dinh trong che do tuc thi
IN AX, DX ;doc mot tu tu mot cong dang bien
19. INC Increment (tng ton hng ln 1)
Dng lnh: INC ch
M t: ch ch + 1
Lnh ny tng ch ln 1, tng ng vi vic ADD ch, 1 nhng chy nhanh
hn.
Cc c b thay i: AF, OF, PF, SF, ZF.
V d:
INC AL
INC BX
20. MUL Multiply unsigned byte or word (nhn s khng du)
Dng lnh: MUL Ngun
Thc hin php nhn khng du vi ton hng Ngun ( nh hoc thanh ghi) vi
thanh ghi tng.
- Nu Ngun l s 8 bit: AL*Ngun. S b nhn phi l s 8 bit t trong AL, sau khi
nhn tch lu vo AX
- Nu Ngun l s 16 bit: AX*Ngun. S b nhn phi l s 16 bit t trong AX, sau
khi nhn tch lu vo DXAX.
Nu byte cao (hoc 16 bit cao) ca 16 (hoc 32) bit kt qu cha 0 th CF=OF=0.
V d:
MUL CX ;AXxCX DXAX
MUL BL ;ALxBL AX
21. NEG Negation (ly b hai ca mt ton hng, o du ca mt ton hng).
Dng lnh: NEG ch
M t: ch0-ch
NEG ly 0 tr cho ch (c th l 1 byte hoc 1 t) v tr li kt qu cho ton hng
ch, nu ta ly b hai ca -128 hoc -32768 ta s c kt qu khng i nhng OF=1
bo l kt qu b trn v s dng ln nht biu din c l +127 v +32767.
Cc c b thay i: AF, CF, OF, PF, SF, ZF
V d:
NEG AL ;AL0-(AL)
22. SBB Substract with Borrow (tr c mn).
Dng lnh: SBB ch, Ngun
M t: chch-Ngun-CF
Bi ging Chng 2

Ton hng ch vo Ngun phi cha cng mt loi d liu v khng c ng
thi l hai nh, cng khng c l thanh ghi on.
V d:
SBB AL, 78H ;ALAL-78H-CF
SBB BL, CL ;BLBL-CL-CF
SBB DL, [SI] ;DLDL-{DS:SI}-CF
23. SUB Substract (tr hai ton hng)
Dng lnh: SUB ch, Ngun
M t: chch - Ngun
Ton hng ch vo Ngun phi cha cng mt loi d liu v khng c ng
thi l hai nh, cng khng c l thanh ghi on.
V d:
SUB AL, 78H ;ALAL-78H
SUB BL, CL ;BLBL-CL
SUB DL, [SI] ;DLDL-{DS:SI}
Nhm cc lnh tnh ton logic
24. AND (php v logic)
Dng lnh: AND ch, Ngun
M t: ch ch ^ Ngun
Thc hin php v logic hai ton hng v lu kt qu vo ton hng ch. Ngi ta
thng s dng che i/gi li mt vi bit no ca mt ton hng bng cch nhn logic
ton hng vi ton hng tc th c cc bit 0/1 cc v tr cn che i/gi li tng ng.
Cc c b thay i: CF, OF, PF, SF, ZF.
V d:
AND DX, CX ;DXDX AND CX theo tung bit
AND AL, 0FH ;che 4 bit cao cua AL
25. NOT Logical Negation (ph nh logic)
Dng lnh: NOT ch
NOT o cc gi tr ca cc bit ca ton hng ch.
V d:
MOV AL, 02H ;AL=(0000 0010)B
NOT AL ;AL=(1111 1101)B
26. OR Logic OR (php hoc logic)
Bi ging Chng 2

Dng lnh: OR ch, Ngun
M t: ch = ch Ngun
Ton hng ch v Ngun phi cha d liu cng di v khng c php ng
thi l hai nh v cng khng c l thanh ghi on. Php OR thng dng lp mt
vi bit no ca ton hng bng cch cng logic ton hng vi cc ton hng tc thi
c cc bit 1 ti v tr tng ng cn thit lp.
V d:
OR AX, BX ;AXAXBX theo tung bit
OR CL, 30H ;lap bit b4 va b5 cua CL len 1
Nhm cc lnh dch, quay ton hng
27. RCL Rotate though CF to the Left (quay tri thng qua c nh)
Dng lnh: RCL ch, CL
M t:
MSB LSB CF

Lnh ny quay ton hng sang tri thng qua c CF, CL phi c cha sn s
ln quay. Trong trng hp quay 1 ln c th vit RCL ch, 1
Nu s ln quay l 9 th ton hng khng i v cp CF v ton hng quay ng mt
vng (nu ton hng ch l 8 bit).
Sau lnh RCL c CF mang gi tr c ca MSB, cn c OF1 nu sau khi quay 1
ln m bit MSB b thay i so vi trc khi quay, c OF s khng c xc nh sau nhiu
ln quay.
V d:
MOV CL, 3 ;so lan quay la 3
RCL AL, CL
Trc khi thc hin lnh: AL = 01011110, CF = 0.
Sau khi thc hin lnh: AL = 11110001, CF = 0.
28. RCR Rotate though CF to the Right (quay phi thng qua c nh)
Dng lnh: RCR ch, CL
M t:
MSB LSB CF

Bi ging Chng 2

Lnh ny quay ton hng sang phi thng qua c CF, CL phi c cha sn s
ln quay. Trong trng hp quay 1 ln c th vit RCR ch, 1
Nu s ln quay l 9 th ton hng khng i v cp CF v ton hng quay ng mt
vng (nu ton hng ch l 8 bit).
Sau lnh RCR c CF mang gi tr c ca LSB, cn c OF1 nu sau khi quay 1 ln
m bit MSB b thay i so vi trc khi quay, c OF s khng c xc nh sau nhiu ln
quay.
V d:
RCR AL, CL
Trc khi thc hin lnh: AL = 11000010, CF = 1.
Sau khi thc hin lnh: AL = 01110000, CF = 1.
29. ROL Rotate all bit to the Left (quay vng sang tri).
Dng lnh: ROL ch, CL.
M t:
CF MSB LSB

Lnh ny dng quay vng ton hng sang tri, MSB c a sang c CF v
LSB. CL phi cha sn s ln quay mong mun. Trong trng hp quay 1 ln c th vit
ROL ch, 1. Nu s ln quay l 8 (CL=8) th ton hng khng i v ton hng quay ng
mt vng (nu ton hng ch l 8 bit), cn nu CL=4 th 4 bit cao i ch cho 4 bit thp.
Sau lnh ROL c CF mang gi tr c ca MSB, cn c OF1 nu sau khi quay 1
ln m bit MSB b thay i so vi trc khi quay, c OF s khng c xc nh sau nhiu
ln quay. Lnh ny thng dng to c CF t gi tr ca MSB lm iu kin cho lnh
nhy c iu kin.
V d:
ROL AL, CL
Trc khi thc hin lnh: AL = 11001100, CF = 1
Sau khi thc hin lnh: AL = 00110011, CF = 1
30. ROR Rotate all bit to the Left (quay vng sang phi).
Dng lnh: ROR ch, CL
M t:
Bi ging Chng 2

MSB LSB CF

Lnh ny dng quay vng ton hng sang phi, LSB c a sang c CF v
MSB. CL phi cha sn s ln quay mong mun. Trong trng hp quay 1 ln c th vit
ROR ch, 1. Nu s ln quay l 8 (CL=8) th ton hng khng i v ton hng quay ng
mt vng (nu ton hng ch l 8 bit), cn nu CL=4 th 4 bit cao i ch cho 4 bit thp.
Sau lnh ROR c CF mang gi tr c ca LSB, cn c OF1 nu sau khi quay 1 ln
m bit MSB b thay i so vi trc khi quay, c OF s khng c xc nh sau nhiu ln
quay. Lnh ny thng dng to c CF t gi tr ca LSB lm iu kin cho lnh nhy c
iu kin.
V d:
ROR AL, CL
31. SAL/SHL - Shift Arithmetically Left (dch tri s hc)/Shift Logically Left (dch tri
logic).
Dng lnh:
SAL ch, CL
SHL ch, CL
M t:
MSB LSB CF 0

Hai lnh ny c tc dng dch tri s hc ton hng (cn gi l dch tri logic). Mi
ln dch MSB c a vo CF cn 0 c a vo LSB. CL phi cha sn s ln quay
mong mun. Trong trng hp quay 1 ln c th vit SAL ch, 1
Sau lnh SAL hoc SHL c CF mang gi tr c ca MSB, cn c OF1 nu sau khi
quay 1 ln m bit MSB b thay i so vi trc khi quay, c OF s khng c xc nh sau
nhiu ln quay. Lnh ny thng dng to c CF t gi tr ca MSB lm iu kin cho
lnh nhy c iu kin.
Cc c b thay i: SF, ZF, CF, OF, PF.
V d:
SAL AL, CL
Bi ging Chng 2

32. SAR - Shift Arithmetically Right (dch phi s hc).
Dng lnh: SAR ch, CL
M t:
MSB LSB CF

Lnh ny c tc dng dch phi s hc ton hng. Mi ln dch MSB c gi li (nu
ta hiu y l bit du th du lun khng i) cn LSB c a vo CF. CL phi cha sn s
ln quay mong mun. Trong trng hp quay 1 ln th ta c th vit SAR ch, 1.
Sau lnh SAR c CF mang gi tr c ca LSB, cn c OF1 nu sau khi quay 1 ln m
bit MSB b thay i so vi trc khi quay, c OF s khng c xc nh sau nhiu ln quay.
Lnh ny thng dng to c CF t gi tr ca MSB lm iu kin cho lnh nhy c iu
kin.
V d:
SAR AL, CL
33. SHR Shift logically Right (dch phi logic)
Dng lnh: SHR ch, CL
M t:
MSB LSB CF 0

Lnh ny c tc dng dch phi logic ton hng. Mi ln dch LSB c a vo CF cn
0 c a vo MSB. CL phi cha sn s ln quay mong mun. Trong trng hp quay 1 ln
c th vit SHR ch, 1
Sau lnh SHR c CF mang gi tr c ca LSB, cn c OF1 nu sau khi quay 1 ln m
bit MSB b thay i so vi trc khi quay, c OF s khng c xc nh sau nhiu ln quay.
Lnh ny thng dng to c CF t gi tr ca LSB lm iu kin cho lnh nhy c iu
kin.
V d:
SHR AL, CL
Bi ging Chng 2

34. TEST Logic Camparison (lnh so snh logic)
Dng lnh: TEST ch, Ngun
M t: ch Ngun
TEST thc hin php v hai ton hng (dng byte hoc t) v cp nht cc c nhng
khng tr li kt qu (tc l khng c ton hng no thay i, khng lu kt qu). Nu pha sau
lnh TES l lnh JNZ (nhy nu khc 0) th mt lnh nhy s c thc hin nu c mt cp
cc bit tng ng u bng 1.
V d:
TEST AL, 3FH
TEST AX, 0034H
35. XOR Exclusive OR (lnh logic XOR (hoc o)).
Dng lnh: XOR ch, Ngun
M t: chchNgun.
Lnh XOR thc hin logic XOR (hoc o) gia hai ton hng v kt qu c lu vo
trong ch, mt bit kt qu c t bng 1 nu nu cc bit tng ng hai ton hng l i nhau.
Nu ton hng ch trng ton hng Ngun th kt qu bng 0, do lnh ny cn c dng
xo thanh ghi v 0 km theo cc c CF v OF cng b xo.
V d:
XOR AX, AX
XOR BX, BX
MOV AX, 5857H
MOV BX, 58A8H
XOR AX, BX
Trc khi thc hin lnh XOR Sau khi thc hin lnh XOR
AX=5857H AX=00FFH
BX=58A8H BX=58A8H
Nhm cc lnh so snh
36. CMP Compare (so snh)
Dng lnh: CMP ch, Ngun
CMP tr ton hng ch cho ton hng Ngun, chng c th l cc byte hoc cc t,
nhng khng lu tr kt qu. Cc ton hng khng b thay i. Kt qu ca lnh ny dng
cp nht cc c v c th c dng lm iu kin cho cc lnh nhy c iu kin tip theo.
Cc c chnh theo quan h ch v Ngun khi so snh hai s khng du.
CF ZF
Bi ging Chng 2

ch = Ngun 0 1
ch > Ngun 0 0
ch < Ngun 1 0
37. CMPS/CMPSB/CMPSW Compare String Bytes or String Words (so snh hai chui byte
hay hai chui t).
Dng lnh:
CMPS Chui_ch, Chui_Ngun
CMPSB
CMPSW
Lnh ny so snh tng phn t (byte hay t) ca hai xu c cc phn t cng loi. Lnh
ch to cc c, khng lu kt qu so snh, sau khi so snh cc ton hng khng b thay i.
Trong lnh ny ngm nh cc thanh ghi vi cc chc nng:
- DS:SI l a ch ca phn t so snh trong chui Ngun.
- ES: DI l a ch ca phn t so snh trong chui ch.
- Sau mi ln so snh SISI 1, DIDI 1 hoc SISI 2, DIDI 2 mt cch t
ng tu thuc vo c hng DF l 0 hay 1 v chui thao tc l chui byte hay t.
V d:
StrByte1 DB chuoi byte1
StrByte2 DB chuoi byte2
StrWord1 DW chuoi word1
StrWord2 DW chuoi word2
LEA SI, StrByte1 ;nap gia tri hieu dung
;StrByte1 vao SI
LEA DI, StrByte2 ;nap gia tri hieu dung
;StrByte2 vaoDI
COMPS StrByte2, StrByte1
;co the thay bang COMPSB LEA SI, StrWord1
;nap gia tri hieu dung StrWord1 vao SI
LEA DI, StrWord2 ;nap gia tri hieu dung
;StrWord2 vaoDI
COMPS StrWord2, StrWord1
;co the thay bang COMPSW
Nhm cc lnh nhy (r nhnh)
38. JA/JNBE Jump if Above/Jump if Not Below or Equal (nhy nu cao hn/nhy nu khng
thp hn hoc bng).
Dng lnh:
JA NHAN
Bi ging Chng 2

JNBE NHAN
M t: IPIP+dch chuyn
Hai lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu CF + ZF
= 0. Quan h cao hn/thp l quan h dnh cho vic so snh (do lnh CMP thc hin) ln
hai s khng du. NHAN phi nm cch xa mt khong -128+127 byte so vi lnh tip
theo sau lnh JA/JNBE. Chng trnh s cn c vo v tr NHAN xc nh gi tr dch
chuyn.

V d:
CMP AX, 12ABH ;so sanh AX voi 12ABH
JA THOI ;nhay den THOI neu AX cao hon
;12ABH
39. JAE/JNB/JNC Jump if Above or Equal/Jump if Not Below/Jump if No Carry (nhy
nu ln hn hoc bng/nhy nu khng thp hn/nhy nu khng c nh).
Dng lnh:
JAE NHAN
JNB NHAN
JNC NHAN
M t: IPIP+dch chuyn
Ba lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu CF = 0.
Quan h cao hn/thp l quan h dnh cho vic so snh (do lnh CMP thc hin) ln hai
s khng du. NHAN phi nm cch xa mt khong -128+127 byte so vi lnh tip theo
sau lnh JAE/JNB/JNC. Chng trnh s cn c vo v tr NHAN xc nh gi tr dch
chuyn.
V d:
CMP AL, 10H ;so sanh AL voi 10H
JAE THOI ;nhay den THOI neu AL cao hon hoac
;bang 10H
40. JB/JC/JNAE Jump if Below/Jump if Carry/Jump if Not Above or Equal (nhy nu
thp hn/nhy nu c nh/nhy nu khng cao hn hoc bng).
Dng lnh:
JB NHAN
JC NHAN
JNAE NHAN
M t: IPIP+dch chuyn
Bi ging Chng 2

Ba lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu CF = 1. Quan
h cao hn/thp l quan h dnh cho vic so snh (do lnh CMP thc hin) ln hai s khng
du. NHAN phi nm cch xa mt khong -128+127 byte so vi lnh tip theo sau lnh
JB/JC/JNAE. Chng trnh s cn c vo v tr NHAN xc nh gi tr dch chuyn.
V d:
JB THOI ;nhay den THOI neu AL thap hon 10H
41. JBE/JNA Jump if Below or Equal/Jump if Not Above (nhy nu thp hn hoc bng/nhy
nu khng cao hn).
Dng lnh:
JBE NHAN
JNA NHAN
M t: IPIP+dch chuyn
Hai lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu
CF +ZF = 1. Quan h cao hn/thp l quan h dnh cho vic so snh (do lnh CMP thc
hin) ln hai s khng du. NHAN phi nm cch xa mt khong -128+127 byte so vi
lnh tip theo sau lnh JBE/JNA. Chng trnh s cn c vo v tr NHAN xc nh gi tr
dch chuyn.
V d:
JBE THOI ;nhay den THOI neu AL thap hon hoac
;bang 10H
42. JCXZ Jump if CX register is Zero (nhy nu ni dung thanh m CX rng).
Dng lnh: JCXZ NHAN
M t: IPIP+dch chuyn
Lnh trn biu din thao tc nhy c iu kin ti NHAN nu CX = 0 v khng lin
quan n ZF. NHAN phi nm cch xa mt khong -128+127 byte so vi lnh tip theo sau
lnh JCXZ. Chng trnh s cn c vo v tr NHAN xc nh gi tr dch chuyn.
V d:
JCXZ THOI ;nhay den THOI neu CX=0
43. JE/JZ Jump if Equal/Jump if Zero (nhy nu bng nhau/nhy nu kt qu bng khng)
Dng lnh:
JE NHAN
JZ NHAN
Bi ging Chng 2

M t: IPIP+dch chuyn
Lnh trn biu din thao tc nhy c iu kin ti NHAN nu ZF = 1. NHAN phi
nm cch xa mt khong -128+127 byte so vi lnh tip theo sau lnh JE/JZ. Chng
trnh s cn c vo v tr NHAN xc nh gi tr dch chuyn.
V d:
SUB AL, 10H ;tru AL cho 10H
JE THOI ;nhay den THOI neu AL bang 10H
44. JG/JNLE Jump if Greater than/Jump if Not Less than or Equal (nhy nu ln
hn/nhy nu khng b hn hoc bng)
Dng lnh:
JG NHAN
JNLE NHAN
M t: IPIP+dch chuyn
Hai lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu (SF xor
OF)+ZF = 0. Quan h ln hn/b hn l quan h dnh cho vic so snh (do lnh CMP thc
hin) ca hai s c du. Ln hn c ngha l dng hn. NHAN phi nm cch xa mt
khong -128+127 byte so vi lnh tip theo sau lnh JG/JNLE. Chng trnh s cn c
vo v tr NHAN xc nh gi tr dch chuyn.
V d:
JG THOI ;nhay den THOI neu AL lon hon 10H
45. JGE/JNL Jump if Greater than or Equal/Jump if Not Less than (nhy nu ln hn
hoc bng/nhy nu khng nh hn)
Dng lnh:
JGE NHAN
JNL NHAN
M t: IPIP+dch chuyn
OF) = 0. Quan h ln hn/b hn l quan h dnh cho vic so snh (do lnh CMP thc hin)
ca hai s c du. Ln hn c ngha l dng hn. NHAN phi nm cch xa mt khong -
128+127 byte so vi lnh tip theo sau lnh JGE/JNL. Chng trnh s cn c vo v tr
NHAN xc nh gi tr dch chuyn.
V d:
JGE THOI ;nhay den THOI neu AL lon hon hoac
Bi ging Chng 2

;bang 10H
46. JL/JNGE Jump if Less than/Jump if Not Greater than or Equal (nhy nu b hn/nhy
nu khng ln hn hoc bng).
Dng lnh:
JL NHAN
JNGE NHAN
M t: IPIP+dch chuyn
OF)= 1. Quan h ln hn/b hn l quan h dnh cho vic so snh (do lnh CMP thc hin) ca
hai s c du. Ln hn c ngha l dng hn. NHAN phi nm cch xa mt khong -
128+127 byte so vi lnh tip theo sau lnh JL/JNGE. Chng trnh s cn c vo v tr
V d:
JL THOI ;nhay den THOI neu AL nho hon 10H
47. JLE/JNG Jump if Less than or Equal/Jump if Not Greater than (nhy nu nh hn hoc
bng/nhy nu khng ln hn)
Dng lnh:
JLE NHAN
JNG NHAN
M t: IPIP+dch chuyn
OF)+ZF= 1. Quan h ln hn/b hn l quan h dnh cho vic so snh (do lnh CMP thc hin)
ca hai s c du. Ln hn c ngha l dng hn. NHAN phi nm cch xa mt khong -
128+127 byte so vi lnh tip theo sau lnh JLE/JNG. Chng trnh s cn c vo v tr
V d:
JLE THOI ;nhay den THOI neu AL nho hon hoac
;bang 10H
48. JMP Unconditional Jump (lnh nhy khng iu kin).
JMP trao quyn iu khin cho vng mc tiu mt cch khng iu kin. Lnh ny
c cc ch ging nh lnh CALL v n cng phn bit nhy gn, nhy xa.
Dng lnh: Sau y l nhng cch vit lnh khng iu kin.
JMP NHAN
Bi ging Chng 2

Lnh mi ny bt u a ch ng vi NHAN. Chng trnh s cn c vo khong
dch gia NHAN v lnh nhy xc nh xem n l:
+ Nhy ngn: Trong trng hp ny NHAN phi nm cch xa (dch i mt khong).
-128127 byte so vi lnh tip theo sau lnh JMP. Chng trnh dch s cn c vo
v tr NHAN xc nh gi tr dch chuyn. Do
IPIP+dch chuyn
y l lnh nhy trc tip v dch chuyn trc tip trong m lnh.
nh hng cho chng trnh dch lm vic nn vit lnh di dng:
JMP SHORT NHAN
+ Nhy gn: Trong trng hp ny NHAN phi nm cch xa (dch i mt khong)
-32768+32767 byte so vi lnh tip theo sau lnh JMP. Chng trnh dch s cn
c vo v tr NHAN xc nh gi tr dch chuyn. Do
IPIP+dch chuyn
y l lnh nhy trc tip v dch chuyn trc tip trong m lnh.
nh hng cho chng trnh dch lm vic nn vit lnh di dng:
JMP NEAR NHAN
+ Nhy xa: Trong trng hp ny NHAN nm on m khc so vi lnh tip theo
sau lnh JMP. Chng trnh s cn c vo v tr NHAN xc nh gi tr a ch nhy n
(CS:IP ca NHAN). Sau :
IPIP ca NHAN
CSCS ca NHAN
JMP BX
y l lnh nhy gn, trc BX phi cha a ch lch ca lnh nh nhy n
trong on CS. Khi thc hin lnh ny th IPBX. y l lnh nhy gin tip v a ch
lch nm trong thanh ghi. nh hng cho chng trnh dch lm vic ta nn vit lnh
di dng:
JMP NEAR PTR BX
JMP [BX]
y l lnh nhy gn. IP mi c ly t ni dung 2 nh do BX v BX+1 ch ra
trong on DS (SI, DI c th dng thay ch ca BX). y l lnh nhy gin tip v a ch
lch trong nh. nh hng cho chng trnh dch lm vic ta nn vit lnh di
dng:
JMP WORD PTR [BX]
Mt bin dng khc ca lnh trn thu c khi ta vit lnh di dng:
JMP DWORD PTR [BX]
Bi ging Chng 2

y l lnh nhy xa. a ch nhy n ng vi CS:IP. Gi tr gn cho IP v CS c
cha trong 4 nh do BX v BX+1 (cho IP), BX+2 v BX+3 cho (CS) ch ra trong on DS
(SI, DI c th s dng thay ch ca BX)
y cng l lnh nhy gin tip v a ch lch v a ch c s nm trong nh.
49. JNE/JNZ Jump if Not Equal/Jump if Not Zero (nhy nu khng bng nhau/nhy nu kt
qu khng rng).
Dng lnh:
JNE NHAN
JNZ NHAN
M t: IPIP+dch chuyn
Hai lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu ZF = 0.
NHN phi nm cch xa (dch i mt khong) -128127 byte so vi lnh tip theo sau lnh
JNE/JNZ. Chng trnh dch s cn c vo v tr NHAN xc nh dch chuyn.
V d:
JNE THOI ;nhay den THOI neu AL khac 10H
50. JNO Jump if Not Overflow (nhy nu khng trn)
Dng lnh: JNO NHAN
M t: IPIP+dch chuyn
y l lnh nhy c iu kin ti NHAN nu OF = 0. NHN phi nm cch xa (dch i
mt khong) -128127 byte so vi lnh tip theo sau lnh JNO. Chng trnh dch s cn c
vo v tr NHAN xc nh dch chuyn.
V d:
MUL AL, BL ;nhan AL voi BL
JNO THOI ;nhay den THOI neu khong tran
51. JNP/JPO Jump if Not Parity/Jump if Parity Odd (nhy nu parity l).
Dng lnh:
JNP NHAN
JPO NHAN
M t: IPIP+dch chuyn
Hai lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu PF = 0.
NHAN phi nm cch xa (dch i mt khong) -128127 byte so vi lnh tip theo sau lnh
JNP/JPO. Chng trnh dch s cn c vo v tr NHAN xc nh dch chuyn.
Bi ging Chng 2

V d:
IN AL, 98H ;doc ky tu tu cong
OR AL, AL ;tao co
JNP THOI ;nhay den THOI neu parity le
52. JNS - Jump Not Signed (nhy nu kt qu dng).
Dng lnh: JNS NHAN
M t: IPIP+dch chuyn
y l lnh nhy c iu kin ti NHAN nu SF = 0. Kt qu l dng sau khi thc
hin cc php ton c du. NHAN phi nm cch xa (dch i mt khong) -128127 byte so
vi lnh tip theo sau lnh JNS. Chng trnh dch s cn c vo v tr NHAN xc nh
dch chuyn.
V d:
SUB AL, AH ;tru hai so co dau AL cho AH
JNS THOI ;nhay den THOI neu ket qua duong
53. JO Jump if Overflow (nhy nu trn)
Dng lnh: JO NHAN
M t: IPIP+dch chuyn
y l lnh nhy c iu kin ti NHAN nu OF = 1. Tc l sy xa trn sau khi thc
hin cc php ton c du. NHAN phi nm cch xa (dch i mt khong) -128127 byte so
vi lnh tip theo sau lnh JO. Chng trnh dch s cn c vo v tr NHAN xc nh
dch chuyn.
V d:
ADD AL, AH ;cong AL voi AH
JO THOI ;nhay den THOI neu co tran
54. JP/JPE Jump if Parity/Jump if Parity Even (nhy nu parity chn)
Dng lnh:
JP NHAN
JPE NHAN
M t: IPIP+dch chuyn
Hai lnh trn biu din cng mt thao tc nhy c iu kin ti NHAN nu PF = 1.
NHAN phi nm cch xa (dch i mt khong) -128127 byte so vi lnh tip theo sau lnh
JP/JPE. Chng trnh dch s cn c vo v tr NHAN xc nh dch chuyn.
V d:
IN AL, 99H ;doc ky tu tu cong
OR AL, AL ;tao co
Bi ging Chng 2

JP THOI ;nhay den THOI neu parity chan
55. JS Jump if Sign (nhy nu m)
Dng lnh: JS NHAN
M t: IPIP+dch chuyn
y l lnh nhy c iu kin ti NHAN nu SF = 1. Kt qu l m sau khi thc hin
cc php ton c du. NHAN phi nm cch xa (dch i mt khong) -128127 byte so vi
lnh tip theo sau lnh JS. Chng trnh dch s cn c vo v tr NHAN xc nh dch
chuyn.
V d:
SUB AL, AH ;tru hai so co dau AL cho AH
JS THOI ;nhay den THOI neu ket qua duong
Nhm cc lnh lp
56. LOOP Loop if CX is not 0 (lp nu CX 0)
Dng lnh: LOOP NHAN
M t: Lnh ny dng lp li on chng trnh (gm cc lnh nm trong khong t
NHAN n ht lnh LOOP NHAN) cho n khi s ln lp CX=0. iu ny c ngha l trc
khi vo vng lp ta phi a s ln lp mong mun vo CX, v sau mi ln lp th CX t ng
gim i 1.
NHAN phi nm cch xa (dch i mt khong) ti a -128 byte so vi lnh tip theo sau
lnh LOOP.
V d:
MOV AL, 0 ;xoa AL
MOV CX, 10 ;nap so lan lap vao CX
LAP: INC AL ;tang AL len 1
LOOP LAP ;lap lai 10 lan, AL=10
57. LOOPE/LOOPZ Loop while CX=0 or ZF=0 (lp li on chng trnh cho n khi
CX=0 hoc ZF=0).
Dng lnh:
LOOPE NHAN
LOOPZ NHAN
M t: Lnh ny dng lp li on chng trnh (gm cc lnh nm trong khong t
NHAN n ht lnh LOOPE NHAN hoc LOOPZ NHAN) cho n khi s ln lp CX=0 hoc
c ZF=0. iu ny c ngha l trc khi vo vng lp ta phi a s ln lp mong mun vo
CX, v sau mi ln lp th CX t ng gim i 1.
NHAN phi nm cch xa (dch i mt khong) ti a -128 byte so vi lnh tip
theo sau lnh LOOPE/LOOPZ.
Bi ging Chng 2

V d:
MOV AL, AH ;AL=AH
LAP: INC AL ;tang AL
COMP AL, 16 ;so sanh AL voi 16
LOOPE LAP ;lap lai cho den khi AL16 hoac CX=0
58. LOOPNE/LOOPNZ Loop while CX=0 or ZF=1 (lp li on chng trnh cho
n khi CX=0 hoc ZF=1).
Dng lnh:
LOOPNE NHAN
LOOPNZ NHAN
M t: Lnh ny dng lp li on chng trnh (gm cc lnh nm trong
khong t NHAN n ht lnh LOOPNE NHAN hoc LOOPNZ NHAN) cho n khi
s ln lp CX=0 hoc c ZF=1. iu ny c ngha l trc khi vo vng lp ta phi a
s ln lp mong mun vo CX, v sau mi ln lp th CX t ng gim i 1.
NHAN phi nm cch xa (dch i mt khong) ti a -128 byte so vi lnh tip
theo sau lnh LOOPNE/LOOPNZ.
V d:
MOV AL, AH ;AL=AH
LAP: INC AL ;tang AL
COMP AL, 16 ;so sanh AL voi 16
LOOPNE LAP ;lap lai cho den khi AL=16 hoac CX=0
59. REP Repeat String Instruction until CX=0 (lp li lnh vit sau cho ti khi
CX=0).
y l tip u ng dng vit trc cc lnh thao tc vi chui liu m ta
mun lp li mt s ln. S ln lp phi trc trong CX. Khi cc lnh ny c thc
hin th CX t ng gim i 1. Qu trnh lp kt thc khi CX=0.
V d:
REP MOVSB ;lap lai lenh chuyen byte cua chuoi
;toi khi CX=0
60. REPE/REPZ Repeat String Instruction until CX=0 or ZF=0 (lp li lnh vit sau cho
ti khi CX=0 hoc ZF=0).
y l tip u ng dng vit trc cc lnh thao tc vi chui liu m ta mun
lp li mt s ln. S ln lp phi trc trong CX. Khi cc lnh ny c thc hin th CX t
Bi ging Chng 2

ng gim i 1. Qu trnh lp kt thc khi CX=0 hoc khi hai phn t so snh khc nhau
(ZF=0).
V d:
REPE CMPSB ;lap lai lenh so sanh cac byte cua
;chuoi toi khi CX=0 hoac ZF=0
61. REPNE/REPNZ Repeat String Instruction until CX=0 or ZF=1 (lp li lnh vit sau
cho ti khi CX=0 hoc ZF=1).
y l tip u ng dng vit trc cc lnh thao tc vi chui liu m ta mun
lp li mt s ln. S ln lp phi trc trong CX. Khi cc lnh ny c thc hin th CX t
ng gim i 1. Qu trnh lp kt thc khi CX=0 hoc khi Acc bng phn t ca chui (ZF=1).
V d:
REPNE SCASB ;lap lai lenh quet cac byte cua chuoi
;toi khi het chuoi (CX=0) hoac AL bang
;mot phan tu cua chuoi
Nhm cc lnh iu khin, c bit khc
62. CALL Call a procedure (gi chng trnh con)
Dng lnh: CALL Th_tc
M t: Lnh ny dng chuyn hot ng ca vi x l t chng trnh chnh (CTC)
sang chng trnh con (ctc). Nu ctc nm trong cng mt on m vi CTC ta c gi gn (near
call). Nu ctc v CTC nm hai on m khc nhau ta c gi xa (far call).
- Nu gi gn: Lu vo Stack gi tr IP ca a ch tr v (v CS khng i) v cc thao
tc khi gi ctc din ra nh sau:
+ Ni dung thanh ghi SP gim i 2 byte, SPSP 2.
+ Ni dung thanh ghi IP c ct vo ngn xp (lu a ch tr v) {SP}IP.
+ a ch lch ca ctc (ln ti 32K) c lu vo thanh ghi IP.
+ Khi gp lnh RET cui ctc th VXL ly li a ch tr v IP t Stack v tng
SP ln 2 byte.
- Nu gi xa: Lu vo Stack gi tr IP v CS ca a ch tr v v cc thao tc khi
gi ctc din ra nh sau:
+ Ni dung thanh ghi SP gim i 2 byte, SPSP 2 v CS c lu vo
ngn xp.
+ Ni dung ca CS c thay bng a ch on ca ctc c gi.
+ Ni dung thanh ghi SP li gim i 2 byte v IP c ct vo ngn xp.
+ a ch lch ca ctc c lu vo thanh ghi IP.
+ Khi gp lnh RET cui ctc th VXL ly li a ch tr v IP t Stack v
tng SP ln 2 byte sau tip tc ly li CS v tng SP ln 2 byte.
Bi ging Chng 2

V d:
CALL NEAR
CALL FAR
63. CLC Clear the Carry flag (xo c nh)
Dng lnh: CLC
Xo c nh CF v khng lm nh hng n cc c khc.
Cc c b thay i: CF.
64. CLD Clear the Direction flag (xo c hng)
Dng lnh: CLD
Xo c hng DF v khng lm nh hng n cc c khc.
Cc c b thay i: DF.
65. CLI Clear the Interrupt flag (xo c ngt)
Dng lnh: CLD
Xo c ngt IF v khng lm nh hng n cc c khc. Cc yu cu ngt che
c s b che
Cc c b thay i: IF.
66. CMC Complement the Carry flag (o c nh).
Dng lnh: CMC
M t:
CF CF =
. o c nh CF
Cc c b thay i: CF
67. HLT Halt processing (dng)
Dng lnh: HLT
Khi gp lnh ny, cc hot ng ca vi x l 8086 b tm dng v bc vo trng
thi dng. thot khi trng thi dng ch c cch tc ng vo mt trong cc chn INTR,
NMI, RESET ca b vi x l.
68. INT Interrupt (lnh gi ngt)
Dng lnh: INT N (N=0FFH)
Cc thao tc ca 8086 khi chy lnh: INT N
- To a ch mi ca Stack, ct thanh ghi c vo Stack: SPSP-2, {FR}SP.
- Cm cc ngt khc tc ng vo vi x l, cho vi x l chy ch tng lnh: IF0,
TF0.
- To a ch mi ca Stack, ct a ch on ca a ch tr v vo Stack: SPSP-2,
SPCS.
Bi ging Chng 2

- To a ch mi ca Stack, ct a ch lch ca a ch tr v vo Stack: SPSP-2, SPIP.
- Vi x l ly lnh ti a ch mi, a ch con tr ngt c tnh ton nh sau:
{Nx4}IP, {Nx4+2}CS
V d: vi N = 8 th CS{0022H} v IP{0020H}
69. IRET Interrupt Return (tr v CTC t ctc phc v ngt)
Dng lnh: IRET
Tr v chng trnh chnh t chng trnh con phc v ngt. Tr li quyn iu khin
cho chng trnh ti v tr xy ra ngt bng cch ly li cc gi tr thanh ghi IP, CS v cc c t
vng Stack.
- {SP}IP, SPSP+2
- {SP}CS, SPSP+2
- {SP}FR, SPSP+2
Cc c b thay i: tt c cc c (c phc hi nh trc khi din ra ngt).
70. NOP No Operation (CPU khng lm g)
Dng lnh: NOP
Lnh ny khng thc hin mt cng vic g ngoi vic lm tng ni dung ca IP v tiu
tn 3 chu k ng h. N thng c dng tnh thi gian tr trong cc vng tr hoc
chim ch cc lnh cn thm vo chng trnh sau ny m khng lm nh hng dn di
chng trnh.
71. RET Return from Procedure to Calling Program (tr v chng trnh chnh t chng trnh
con).
Dng lnh: RET hoc RET N (N l s nguyn dng)
M t: RET c t cui ctc vi x l ly li a ch tr v, m n c t ng
ct ti ngn xp khi c lnh gi ctc. c bit nu dng lnh RET n th sau khi ly li c
a ch tr v (ch c IP hoc c IP v CS) th SPSP+n (dng nhy qua m khng ly li
cc thng s khc ca chng trnh cn li trong ngn xp.
72. STC Set the Carry Flag (lp c nh)
Dng lnh: STC
M t: CF1
STC thit lp c nh bng 1 v khng nh hng n cc c khc.
Cc c b thay i: CF=1.
73. STD Set the Direction Flag (lp c hng).
Dng lnh: STD
M t: DF1
Bi ging Chng 2

STD thit lp c hng bng 1 v khng nh hng n cc c khc. Lnh ny nh
hng thao tc cho cc lnh lm vic vi chui theo chiu (). Cc thanh ghi SI, DI lin quan
s c gim i khi lm vic xong vi phn t ca chui.
Cc c b thay i: DF=1.
74. STI Set the Interrupt Flag (lp c cho php ngt)
Dng lnh: STI
M t: IF1
Lnh ny lp c cho php ngt cho php cc yu cu ngt tc ng vo chn INTR
c CPU nhn bit. Khi IF=1 nu c tn hiu INTR=1 th 8086 s b ngt, n s t ng ct
thanh ghi c v a ch tr v vo ngn xp ri chuyn sang chng trnh phc v ngt. Ti cui
chng trnh phc v ngt s c lnh tr v CTC (lnh IRET) 8086 ly li t ngn xp gi tr
thanh ghi c v a ch tr v.
Cc c b thay i: IF=1
75. WAIT Wait for TEST or INTR Signal (ch tn hiu t chn TEST hoc INTR).
Dng lnh: WAIT
M t: Lnh ny a b vi x l 8086 vo trng thi ngh v n s trng thi ngy cho
n khi c tn hiu mc thp tc ng vo chn TEST hoc khi c tn hiu mc cao tc ng
vo chn INTR. Nu c yu cu ngt v yu cu ny c php tc ng vo chn INTR th sau
khi chng trnh phc v ngt c thc hin n s li tr v trng thi ngh. Lnh ny dng
ng b ho hot ng ca 8086 vi cc b ng x l bn ngoi.
2.4 Biu thi gian ghi/c
2.4.1 Xung nhp v chu k my
Trn hnh 2.5.1a l hnh v m t mt chu k xung nhp (chu k ng h), mt chu
k ng h bao gm 2 pha i xng gi l pha 1 (tn hiu ng h mc thp) v pha 2 (tn
hiu ng h mc cao). Cc chu k ng h ny c a n li vo xung nhp ca vi x
l. Mt chu k xung nhp cn c gi l mt nhp. Thi gian cn thit v s xung nhp c
s cho mt thao tc ca vi x l gi l mt chu k my. Mi mt chu k my c 4 nhp.
Hnh 2.5.1b l gin thi gian thc hin chu k bus ca vi x l 8086.
Sn ln
Mc thp
Mc cao
Sn xung

Hnh 2.5.1a: Xung nhp
Nhn vo chu k bus ta c th phn ra lm 4 pha nh sau:
- Pha T1: Cc ng trng thi hot ng xc nh kiu thao tc no c CPU thc
hin, ng thi cc a ch b nh I/O cng c truyn.
Bi ging Chng 2

- Pha T2: Cc tn hiu a ch c thay th bng cc tn hiu d liu, cc tn hiu c/ghi
tr nn tch cc.
- Pha T3: Trc tin cc tn hiu trng thi c truyn i bo hiu sp ht mt chu k
Bus, v sau tn hiu iu khin cng c truyn i.
- Pha T4: Ni chung y l pha rnh ri, trong pha ny CPU v cc khi bn ngoi c thi
gi v hiu ho Bus d liu.

ng truyn
a ch/d liu
Tn hiu
iu khin
RD, WR
T1 T2 T3 T4 T4
Trng thi hp l
a ch D liu
ng truyn
trng thi

Hnh 2.5.1a: Thi gian thc hin chu k Bus ca vi x l 8086
2.4.2 Chu k c/ghi ca vi x l 8086
Hnh 2.5.2a ch ra mt chu k c ca vi x l 8086, ngoi pha 1 c m t nh
trn ta cn ch n cc pha cn li. Cng cn ch rng theo c im k thut th d liu
phi tn ti t nht 20 ns trc khi kt thc T3 v vn phi tn ti t nht 10 ns sau khi kt
thc T4. Trong khi ta c th hu b ng thi tn hiu bo c (0 ns).
a ch
RD
AD0-AD15
D liu a ch
T4 T3 T2 T1
Xung nhp
1
2
3
4
5
6
7
8

Hnh 2.5.2a: Chu k c ca vi x l
Trong cc ng:
1. t
CRAZ
: ng h mc tht cho n khi bus a ch trng thi Hi-Z = 35ns Max.
Bi ging Chng 2

2. t
CLRL
: ng h mc thp cho n khi RD hot ng = 70ns Max.
3. t
AZLN
: Bus a ch c th ni cho n khi RD hot ng = 0ns Min.
4. t
OVCL
: D liu hp l cho n khi ng h mc thp cho n khi ng h mc thp =
20ns Min.
5. t
CLDX
: ng h mc thp cho n khi d liu khng hp l = 10ns Min.
6. t
CLRH
: ng h mc thp cho n khi RD mc cao = 10ns Min.
7. t
RMAV
: RD mc cao cho n khi cc a ch hp l = 85ns Min.
8. t
RHDX
: c d liu mc cao cho n khi d liu khng hp l = 0 Min.
Vic truy nhp b nh ko di t T1 T3 (gn 3 chu k ng h 3*T = 3*200 =
600ns). Trong tng s thi gian ny phi tnh n thi gian tr khi truyn a ch ttrach =
110ns, thi gian gi ca d liu khi c tgi = 30ns v thi gian tr do truyn tn hiu qua
cc mch m nhiu nht l ttr m = 40ns. Nh vy cc b nh ni vi 8086 5MHz cn
phi c thi gian thm nhp nh hn:
3*T - t
trach
- t
gi
- t
trm
= 600 110 30 40 = 420ns
Hnh 2.5.2b ch ra mt chu k ghi ca vi x l 8086, ngoi pha T1 c m t nh
trn ta cn ch n cc pha sau:
- Pha T2: Trong pha ny CPU xut ra d liu cn c ghi v tn hiu bo ghi ti b
nh hoc I/O.
- Pha T3: Trong giai on ny d liu ghi l n nh v tn hiu bo ghi c to
ra.
- Pha T4: Tn hiu bo ghi b v hiu ho v sau d liu cn ghi cng b hu b
dnh ch cho cc a ch ca pha T1 ca chu k tip theo.
Xung nhp
a ch D liu a ch
5
4
3
2
1
T1 T2 T3 T4
AD0-AD15
WR

Hnh 2.5.2b. Chu k ghi ca vi x l 8086
1. t
CLDV
: ng h mc thp cho n khi d liu hp l = 44ns Max.
2. t
CVTCV
: ng h mc thp cho n khi WR hot ng = 70ns Max.
3. t
CVCTX
: ng h mc thp cho n khi WR khng hot ng = 55ns Max.
4. t
CHDX
: ng h mc cao cho n khi d liu khng hp l = 10ns Min.
5. WR khng hot ng cho n khi d liu khng hot ng = 10ns.
Bi ging Chng 2

2.5 Lp trnh hp ng (Assembly) cho vi x l 80x86
[Tham kho: http://wapedia.mobi/vi ]

2.5.1 Gii thiu chung v hp ng
Hp ng (assembly language) l mt ngn ng cp thp dng vit cc chng
trnh my tnh. Cch dng cc thut nh (mnemonics) thn thin vit chng trnh
thay th cch lp trnh trc tip ln my tnh bng m my dng s (numeric machine
code) - tng p dng cho nhng my tnh u tin - vn rt mt nhc, d gy li v tn
nhiu thi gi. Mt chng trnh vit bng hp ng s c dch sang ngn ng my
bng mt tin ch gi l trnh hp dch. Lu rng, trnh hp dch khc hon ton vi
trnh bin dch, vn dng bin dch cc ngn ng cp cao sang cc ch th lnh cp
thp m sau s c trnh hp dch chuyn i sang ngn ng my. Cc chng trnh
hp ng thng ph thuc cht ch vo mt kin trc my tnh xc nh, n khc vi
ngn ng cp cao thng c lp i vi cc nn tng kin trc phn cng. Nhiu trnh
hp dch phc tp ngoi cc tnh nng c bn cn cung cp thm cc c ch gip cho
vic vit chng trnh, kim sot qu trnh dch cng nh vic g ri c d dng hn.
Hp ng tng c dng rng ri trong tt c cc kha cnh lp trnh, nhng ngy
nay n c xu hng ch c dng trong mt s lnh vc hp, ch yu giao tip trc
tip vi phn cng hoc x l cc vn lin quan n tc cao in hnh nh cc
trnh iu khin thit b, cc h thng nhng cp thp v cc ng dng thi gian thc..
2.5.2 Cu trc chung ca chng trnh hp ng
Cu trc ca mt lnh hp ng
Tham kho: http://www.emu8086.com/
Mt dng lnh trong chng trnh hp ng gm c cc trng sau:
Tn Lnh Ton hng Ch thch
A: Mov AH, 10h ; a gi tr 10h vo thanh ghi AH

Cu trc thng thng ca mt chng trnh hp ng

.model <Khai bo kiu chng trnh>
.stack <Khai bo kch thc ngn xp>
.data
<Khai bo d liu>
.code
<Cc lnh>
end
V d: Chng trnh sau in ra mn hnh dng ch Hello !
.model small
.stack 100h
.data
s DB Hello !$ ; khai bo xu k t cn in
.code
mov AX,@data ; ly a ch data segment ghi vo DS
mov DS,AX ; V model small, y cng l a ch
; segment ca xu s
Bi ging Chng 2

; xut chui
mov DX, OFFSET s ; ly a ch offset ghi vo DX
mov AH , 9
int 21h ; gi hm 9, ngt 21h in

mov AH, 4Ch ; Thot khi chng trnh
int 21h
end
Lu :
- Mi chng trnh u phi c on CODE thot khi chng trnh, nu khng
chng trnh s khng dng khi ht chng trnh ca mnh.

Khung chng trnh dch ra .exe
data segment
; add your data here!
pkey db "press any key to exit ...$"
ends
stack segment
dw 128 dup(0)
ends
CODE segment
start:
; set segment registers:
MOV ax, data
MOV ds, ax
MOV es, ax

; add your CODE here

lea dx, pkey
MOV ah, 9
int 21h ; output string at ds:dx

; wait for any key....
MOV ah, 1
int 21h

MOV ax, 4c00h ; exit to operating system.
int 21h
ends
END start ; set entry point and stop the assembler.
Khung chng trnh dch ra .com
; You may customize this and other start-up templates;
; The location of this template is
;c:\emu8086\inc\0_com_template.txt
CSEG SEGMENT ; code segment starts here.
org 100h
; add your CODE here
ret
Bi ging Chng 2

Khai bo quy m s dng b nh
CPU 8086 c th truy nhp ti a 1MB b nh RAM. Dung lng ny l tha s
dng cho bt k loi my tnh no.
Bn b nh ca my tnh
IBM PC
a ch vt l ca vng nh
(HEX)
Gii thch vn tt
00000 - 00400
Vector ngt. B mo phng s load file ny:
c:\emu8086\INT_VECT ti a ch vt l 000000
00400 - 00500 Vng thng tin h thng.
00500 - A0000
Mt vng nh t do. Mi khi l 654,080 byte. Ti y c
th load chng trnh
A0000 - B1000
Vng nh mn hnh cho VGA, monochrome, v cho cc b
iu hp khc
B1000 - B8000 D tr
B8000 - C0000
32kb nh mn hnh cho ch ha mu (CGA). B m
phng s dng vng nh ny lu 8 trang vng nh mn
hnh. Mn hnh m phng c th thay i kch thc, nn
b nh ti thiu c yu cu cho mi trang, mc d b
m phng lun lun s dng 1000h (4096 byte) cho mi
trang (xem ngt 10h, AH=05h)
C0000 - F4000 D tr
F4000 - 10FFEF
ROM BIOS v m rng. B m phng ti file BIOS_ROM
ti a ch vt l 0F4000h. a ch ca bng vector ngt ch
ti vng nh ny to hm ngt m phng.

Bng vector ngt (vng nh t 00000h n 00400h)
S hiu
ngt (HEX)
a ch
vector ngt
a ch ca chng trnh con BIOS
(address of BIOS sub-program )
00 00x4 = 00 F400:0170 CPU to, li chia
04 04x4 = 10 F400:0180 - CPU to, pht hin INTO trn
10 10x4 = 40 F400:0190 Hm video
11 11x4 = 44 F400:01D0 Nhn danh sch thit b BIOS
12 12x4 = 48 F400:01A0 Nhn kch thc b nh
13 13x4 = 4C F400:01B0 - Cc hm v a
15 15x4 = 54 F400:01E0 Cc hm BIOS
16 16x4 = 58 F400:01C0 - Cc hm bn phm
17 17x4 = 5C F400:0400 My in
19 19x4 = 64 FFFF:0000 Khi ng li
1A 1Ax4 = 68 F400:0160 Hm thi gian
1E 1Ex4 = 78 F400:AFC7 vector tham s a
20 20x4 = 80 F400:0150 Hm DOS: Kt thc chng trnh
21 21x4 = 84 F400:0200 Cc hm ca DOS
33 33x4 = CC F400:0300 Cc hm chut
Cc hm khc ??x4 = ?? F400:0100 Cc ngt mc nh

Vng thng tin h thng (B nh t 00400h to 00500h)
Bi ging Chng 2

a ch (HEX) Kch thc Gii thch
0040h:0010 WORD
Danh sch thit b BIOS

Trng bit BIOS tm thy phn cng c ci:
bit(s) Gii thch
15-14 S thit b song song
13 D tr
12 Cng game c ci
11-9 S thit b ni tip
8 D tr
7-6 S a mm (tr 1):
00 a mm n;
01 Hai da mm;
10 Ba a mm;
11 Bn a mm;
5-4 Khi to ch Video:
00 EGA,VGA,PGA, hoc on-board video BIOS
khc;
01 40x25 CGA mu.
10 80x25 CGA mu (M phng mc nh).
11 80x25 en trng.
3 D tr.
2 Chut PS/2.
1 B x l ton hc;
0 c ci khi khi ng t a mm.
0040h:0013 WORD
kilobytes bt u vng nh lin tip ti a ch 00000h
t ny cng c tr v AX bi INT 12h
gi tr ny c t l 0280h (640KB)
0040h:004A WORD
S ct trn mn hnh.
Mc nh l 0032h (50 ct)
0040h:004E WORD
a ch bt u trang mn hnh hin hnh trong b nh mn
hnh (sau 0B800:0000)
Gi tr mc nh: 0000h
0040h:0050 8 WORD
Bao gm v tr hng v ct cho con tr trong mi ca tm
trang nh mn hnh.
Gi tr mc nh: 00h (cho tt c 8 t (words)
0040h:0062 BYTE
S trang mn hnh hin hnh
Mc nh: 00h (trang u tin)
0040h:0084 BYTE
Hng trn mn hnh tr 1
Gi tr mc nh: 13h (19+1=20 ct)

Khai bo hng, bin
C php:
<tn bin> D<Kiu DL> <gi tr khi to>
hoc
<tn bin> D<Kiu DL> <s phn t> dup(<gi tr khi to>)

Cc kiu d liu: B (1 byte), W (2 bytes), D (4 bytes)
Nu khng khi to, dng du hi ?
Bi ging Chng 2

V d:

Khai bo trong C Khai bo bin trong hp ng
char ch; ch DB ?
char ch = a; ch DB a
char ch = 5; ch DB 5
char s[]=\nhello world! s DB 10,13,hello world!$
int i=100; i DW 100
long L; L DD ?
char a[] = {1,2,3}; a DB 1,2,3
char a[100]; a DB 100 dup(?)
char a[100][50]; a DB 100 dup(50 dup(?))

Hng s:
Khai bo hng s trong chng trnh hp ng bng lnh EQU.
V d:
TA EQU 19, 81
TACT EQU 2, 11
Chng trnh con
Chng trnh con l mt phn ca m ngun m c th gi chng trong chng trnh ca bn
lm mt vi nhim v nht nh no . Chng trnh con lm cho chng trnh c cu trc hn
v d hiu hn. Thng thng, chng trnh con tr li ngay sau im gi n.
Cu trc mt chng trnh con nh sau:
TN PROC

; y l m lnh ca chng trnh con

RET
TN ENDP

TN l tn ca chng trnh con, tn phi ging nhau trn v di ca chng trnh con, l
cch kim tra im kt thc ca chng trnh con.
Hu nh chc chn, bn bit rng lnh RET c s dng tr v h iu hnh. Lnh
tng t cng c s dng tr v t chng trnh con (thc s, OS coi chng trnh ca
chng ta nh mt chng trnh con c bit)
PROC v ENDP l cc nh hng chng trnh dch, nn chng khng c dch ra m my.
Chng trnh dch nh a ch ca chng trnh con.
Lnh CALL c s dng gi chng trnh con
y l mt v d:
ORG 100h
CALL ta
MOV AX, 2

RET ; Tr v OS
ta PROC
MOV BX, 5
RET ; Tr v sau im gi.
ta ENDP
END
Bi ging Chng 2

V d trn gi chng trnh con ta, thc hin lnh MOV BX, 5 , v tr v sau lnh gi n
MOV AX, 2
C vi cch truyn tham s cho chng trnh con, cch n gin nht l s dng cc thanh
ghi, di y l mt v d khc v cch gi chng trnh con v cch truyn tham s cho n qua
thanh ghi AL v BL, nhn hai tham s vi nhau v tr kt qu v trong thanh ghi AX:
ORG 100h
MOV AL, 1
MOV BL, 2
CALL m2
CALL m2
CALL m2
CALL m2
RET ; Tr v HH
m2 PROC
MUL BL ; AX = AL * BL.
RET ; Tr v sau im gi n.
m2 ENDP
END
Trong v d trn, gi tr ca thnh ghi AL c cp nht mi ln chng trnh con c gi,
thanh ghi BL khng thay i, nn thut ton trn l tnh 2
4
, kt qu lu trong AX l 16 (hay
10h)
Di y l mt v d khc, s dng chng trnh con in xu PICAT.dieukhien.net :
ORG 100h
LEA SI, tbao_tw ; Ly a ch ca msg vo SI.
CALL In_Xau
RET ; tr v h iu hnh.
;=================================================
; Chng trnh ny in 1 xu, xu phi kt thc
; bng k t null (phi c 0 cui xu)
; a ch ca xu phi c t trong thanh ghi SI:

In_Xau PROC
next_char:
CMP b.[SI], 0 ; kim tra nu = 0 th dng
JE stop ;
MOV AL, [SI] ; ly k t tip theo.
MOV AH, 0Eh ; s hiu in k t.
INT 10h ; s dng ngt in k t trong AL.
ADD SI, 1 ; Tng con tr cn in ln 1.
JMP next_char ; tr li, in k t tip.
stop:
RET ; tr v sau im gi.
print_me ENDP
; ===================================================
tbao_tw DB 'PICAT.dieukhien.net',0; xu kt thc: null.

END
Tip u ng b. trc [SI] ngha l so snh byte, khng phi t. Nu bn cn so snh t, bn
dng tip u ng w. thay th vo. Khi mt ton hng nm trog thanh ghi, n khng yu
cu na bi v
Bi ging Chng 2

Lnh b (Macro)
Macro tng t nh chng trnh con nhng khng thc s l chng trnh con. Macro nhn c
v nh chng trnh con, nhng chng ch tn ti cho n khi chng trnh c dch, sau khi
chng trnh c dch tt c cc macro c thay th bng lnh thc s. Nu bn khai bo mt
macro v khng bao gi s dng chng trong m ngun, chng trnh dch s b qua n.
Khai bo:

name MACRO [tham s,...]

<Lnh>
ENDM

Khng nh chng trnh con, macro phi khai bo bn trn on m ngun gi n, v d:

MyMacro MACRO p1, p2, p3

MOV AX, p1
MOV BX, p2
MOV CX, p3

ENDM

ORG 100h

MyMacro 1, 2, 3
MyMacro 4, 5, DX

RET
on m ngun trn s c m rng thnh:
MOV AX, 00001h
MOV BX, 00002h
MOV CX, 00003h
MOV AX, 00004h
MOV BX, 00005h
MOV CX, DX

Vi iu thc s quan trng v Macro v chng trnh con:
Khi mun s dng mt chng trnh con, bn phi s dng t kha CALL, v d:
Call TA_Proc
Khi bn s dng mt Macro, bn ch cn g tn ca chng, v d:
Ta_Macr
Chng trnh con c nh v ti mt a ch c th trong b nh, v nu bn s dng
100 ln chng trnh con , CPU ch chuyn iu khin n vng nh ca chng trnh
con thi. iu khin s tr li chng trnh khi gp lnh RET. Stack c s dng
gi a ch tr v. Lnh CALL ch tn ht 3 byte, nn kch thc ca chng trnh thc
thi nh, khng quan trng vic gi chng trnh con bao nhiu ln.
Macro m rng trc tip cc lnh ca n vo m ngun, nu macro m rng 100 ln (gi
100 ln) s lm cho chng trnh thc thi ln hn rt nhiu, cng ln khi macro c
gi cng nhiu.
Bi ging Chng 2

Bn phi s dng Stack hoc bt k thanh ghi no truyn tham s cho chng trnh
con
truyn tham s cho maco, bn ch cn g chng sau tn ca macro khi gi, v d:
TA_mac 1, 2, 3
nh du kt thc macro, ch cn t kha ENDM l
nh du kt thc chng trnh con bn cn phi nh tn ca chng trnh con
trc t kha ENDP

Macro c m rng trc tip trong m ngun ca bn, v th nu bn c nhiu nhn
ging nhau trong khai bo macro bn c th nhn thng bo li Khai bo trng lp khi
macro c s dng 2 ln hoc nhiu hn. loi b li ny, bn dng t kha LOCAL
khai bo rng nhn sau n l nhn cc b, nhn cc b c th l bin, nhn, hoc
chng trnh con. V d:
MyMacro2 MACRO
LOCAL label1, label2
CMP AX, 2
JE label1
CMP AX, 3
JE label2
label1: INC AX
label2: ADD AX, 2
ENDM
ORG 100h
MyMacro2
MyMacro2
RET
Nu bn c k hoch s dng macro nhiu ln, mt hay l nn t tt c cc macro
trong mt file. V t file trong th mc INC v s dng ch th INCLUDE <Tn-
file> c th s dng macro .
2.5.3 Cc cu trc iu khin c bn
Cu trc repeat until CX=0
Repeat
<action>
Until <condition>
Ngn ng Assembly
LOOP:
<action>
JUMP_if_not_<condition>,LOOP
VD: Cu trc repeat until
Repeat
...
Until CX = 0
Ngn ng Assembly
Mov CX, 10
Start:
.
LOOP Start
V d:
Bi ging Chng 2

org 100h

mov bx, 0 ; total step counter.

mov cx, 5
k1: add bx, 1
mov al, '1'
mov ah, 0eh
int 10h
push cx
mov cx, 5
k2: add bx, 1
mov al, '2'
mov ah, 0eh
int 10h
push cx
mov cx, 5
k3: add bx, 1
mov al, '3'
mov ah, 0eh
int 10h
loop k3 ; internal in internal loop.
pop cx
loop k2 ; internal loop.
pop cx
loop k1 ; external loop.

Ret

2.5.4 Cc bc khi lp trnh
Lp trnh trn phn mm emu8086
- Bc 1: M chng trnh emu8086, chn file \ new Vi cc la chn: New
com template, new exe template, new bin template, new boot template.
- Bc 2: Vit m ngun
- Bc 3: dch v g ri (bm F5)
- Bc 4: to file t chy: assembler \ Compile

Dch, lin kt, chy v chn li chng trnh t du nhc DOS:
Cn c cc file: tasm.exe (dch), tlink.exe (lin kt), td.exe (chn li). Cc bc nh sau:
B1. Thit lp ng dn
path = %path%;<ng dn n th mc cha cc file k trn>

B2. Bin dch t file .ASM sang file .OBJ
Tasm <tn file chng trnh>.ASM

B3. Bin dch t file .OBJ sang file .EXE
Tlink <tn file>.OBJ
Bi ging Chng 2

B4: chy chng trnh:
<tn file>.EXE
B5: chn li (nu cn thit)
Td <tn file>.EXE
t ng ha, ta c th to file .BAT cha cc lnh trn.
V d:
To file RunASM.bat trong cng th mc vi tp tin .ASM vi ni dung nh sau :
tasm %1
tlink %1
%1
(%1 l ly tham s th nht trong command line)
Sau bin dch, lin kt v thc thi chng trnh hello.ASM ta ch cn g :
RunASM hello

Chng trnh emu8086:
Chng trnh emu8086 l chng trnh lp trnh m phng cho 8086 (tng thch
Intel v AMD) bao gm b dch ASM v gio trnh (ting anh) cho ngi mi bt u.
Chng trnh c th chy ht hoc chy tng bc, ta c th nhn thy cc thanh ghi, b
nh, stack, bin,

Bi ging Chng 2

2.5.5 Cc bi tp v d
V d 1. Hello word n gin (COM file)
; the easiest way to print "hello, world!"
name "hi"
org 100h
JMP start ; jump over string declaration
msg db "hello, world!", 0Dh,0Ah, 24h
start: lea dx, msg ; load effective address of
;msg into dx.
MOV ah, 09h ; print function is 9.
int 21h ; do it!

MOV ah, 0
int 16h ; wait for any key any....
RET ; return to operating system.

V d 2. Hello Word (EXE file)
; a tiny example of multi segment executable file.
; data is stored in a separate segment, segment registers must be set correctly.
name "testexe"
data segment
msg db "hello, world!", 0dh,0ah, '$'
ends
stack segment
Bi ging Chng 2

db 30 dup(0)
ends
CODE segment
start:
; set segment registers:
MOV ax, data
MOV ds, ax
MOV es, ax
; print "hello, world!":
lea dx, msg
MOV ah, 09h
int 21h
; wait for any key...
MOV ah, 0
int 16h
; return control to os:
MOV ah, 4ch
int 21h
ends
END start ; set entry point and stop the assembler.

V d 3. V mt hnh ch nht trong ch VGA

name "vga"
; this program draws a tiny rectangle in vga mode.
org 100h
JMP code
; dimensions of the rectangle:
; width: 10 pixels
; height: 5 pixels
w equ 10
h equ 5
; set video mode 13h - 320x200
code: MOV ah, 0
MOV al, 13h
int 10h
; draw upper line:
MOV cx, 100+w ; column
MOV dx, 20 ; row
MOV al, 15 ; white
u1: MOV ah, 0ch ; put pixel
int 10h
dec cx
cmp cx, 100
jae u1
; draw bottom line:
MOV dx, 20+h ; row
MOV al, 15 ; white
Bi ging Chng 2

int 10h
dec cx
cmp cx, 100
ja u2
; draw left line:
MOV cx, 100 ; column
MOV dx, 20+h ; row
MOV al, 15 ; white
int 10h
dec dx
cmp dx, 20
ja u3
; draw right line:
MOV dx, 20+h ; row
MOV al, 15 ; white
int 10h
dec dx
cmp dx, 20
ja u4
; pause the screen for dos compatibility:
;wait for keypress
MOV ah,00
int 16h
; return to text mode:
MOV ah,00
MOV al,03 ;text mode 3
int 10h
ret

V d 4. In mt s nh phn ra mn hnh:
name "add-sub"
org 100h
MOV al, 5 ; bin=00000101b
MOV bl, 10 ; hex=0ah or bin=00001010b
; 5 + 10 = 15 (decimal) or hex=0fh or bin=00001111b
add bl, al
; 15 - 1 = 14 (decimal) or hex=0eh or bin=00001110b
sub bl, 1
; print result in binary:
MOV cx, 8
print: MOV ah, 2 ; print function.
MOV dl, '0'
test bl, 10000000b ; test first bit.
jz zero
MOV dl, '1'
zero: int 21h
Bi ging Chng 2

shl bl, 1
loop print
; print binary suffix:
MOV dl, 'b'
int 21h
; wait for any key press:
MOV ah, 0
int 16h
ret

V d 5. Nhp xu t bn phm, ENTER: v u dng, Ctr_Enter: xung dng, ESC: Exit

; this sample shows the use of keyboard functions.
; try typing something into emulator screen.
; keyboard buffer is used, when someone types too fast.
; for realistic emulation, run this example at maximum speed
; this CODE will loop until you press esc key,
; all other keys will be printed.
name "keybrd"
org 100h
; print a welcome message:
MOV dx, offset msg
MOV ah, 9
int 21h
;============================
; eternal loop to get
; and print keys:
wait_for_key:

; check for keystroke in
; keyboard buffer:
MOV ah, 1
int 16h
jz wait_for_key

; get keystroke from keyboard:
; (remove from the buffer)
MOV ah, 0
int 16h

; print the key:
MOV ah, 0eh
int 10h

; press 'esc' to exit:
cmp al, 1bh
jz exit

JMP wait_for_key
;============================
Bi ging Chng 2

exit:
ret

msg db 'type anything...', 0Dh,0Ah
db '[enter] - carriage return.', 0Dh,0Ah
db '[ctrl]+[enter] - line feed.', 0Dh,0Ah
db 'you may hear a beep', 0Dh,0Ah
db ' when buffer is overflown.', 0Dh,0Ah
db 'press esc to exit.', 0Dh,0Ah, '$'

end

V d 6. T ci t ngt (Custom Interrupt)

; interrupt vector (memory from 00000h to 00400h)
; keeps addresses of all interrupts (from 00h to 0ffh).
; you can add new interrupt or modify existing interrupts.
; address of interrupt M is stored in vector at offset M * 4,
; for example: interrupt 10h is stored at offset 10h * 4.
; first goes the offset, then segment (total of 2 bytes).

; for more information refer to "global memory table" in c:\emu8086\documentation.

; note: this is simplified example, it is not recommended to make changes to it
; and run it on the real computer, especially it is not recommended to replace disk
; processing interrupts because this may cause data loss and other instability problems.

name "custint"
org 100h
start:
; set video mode to 3 - 16 color 80x25
MOV ah, 0
MOV al, 3
int 10h

; set es to "0000":
MOV ax, 0
MOV es, ax
; calculate vector address for interrupt 90h:
MOV al, 90h
; multiply 90h by 4, store result in ax:
MOV bl, 4h
mul bl
MOV bx, ax
; copy offset into interrupt vector:
MOV si, offset [test1]
MOV es:[bx], si
add bx, 2
; copy segment into interrupt vector:
Bi ging Chng 2

MOV ax, cs
MOV es:[bx], ax

int 90h ; test newly created interrupt.

; wait for any key press:
MOV ah, 0
int 16h

int 20h ; halt execution.

; interrupt 90h starts here:
test1: pusha ; store all registers.

; make sure data segment is CODE segment:
push cs
pop ds

; set segment register to video memory:
MOV ax, 0b800h
MOV es, ax

; print message, each character is written as
; a word, high byte is color and low byte is
; ascii code:
lea si, msg ; load offset of msg to si.
MOV di, 0 ; point to start of the screen.
print:
cmp [si], 0 ; if "0" then stop.
je stop
MOV bl, [si] ; read ascii CODE from msg.
MOV bh, 0f1h ; set colors: white background, blue text.
MOV es:[di], bx ; write to vidio memory.
add di, 2 ; go to next position on screen.
inc si ; next char.
JMP print
stop:
popa ; re-store all registers.
iRET ; return from interrupt.

msg db "test of custom interrupt!", 0

V d 7. Gi ngt xa (ln hn 1 segment)
; far_call.asm
name "callfar"
; examples shows how to call int 10h
; without using int instruction.
org 100h
; set es:bx to point to int 10h vector
; in interrupt vector table
Bi ging Chng 2

MOV bx, 0h
MOV es, bx
MOV bx, 40h
MOV ah, 0eh ; set up int 10h params
MOV al, '$'
pushf
call far es:[bx] ; do a far cal to int10h vector

MOV ah, 0
int 16h

ret

V d 8. Gi chng trnh con xa (nng cao)
name "faradv"
org 100h ; set location counter to 100h

JMP start
adr_a dw offset a
seg_a dw ?

adr_c dw offset c
seg_c dw ?
; set segments, requred because we don't know where
; the program will be loaded by the operating system
start:
MOV ax, cs
MOV seg_a, ax
MOV seg_c, ax
call far adr_a
call b
call far adr_c
MOV ax, offset d
call ax
RET ; return to os. ;-----------------------------
a proc
MOV ax, 1
retf ; far return, pop ip and cs.
a endp ;----------------------------------
b proc
add ax, 2
RET ; return, pop ip only.
b endp ;------ -------------------------
c proc
add ax, 3
retf ; far return, pop ip and cs.
c endp ;---- ----------------------------
d proc
add ax, 4
Bi ging Chng 2

RET ; return, pop ip only.
d endp ;------ -------------------------

; note: assembler automatically replaces RET (C3) with retf (CB)
; if proc has far label, for example:
; c proc far
; ....

V d 9. Gi xa, khai bo v s dng chng trnh con
name "far2"
; the correct use of far call for defined procedures.
org 100h
JMP start
off_print_me dw ?
seg_print_me dw ?
start:
MOV off_print_me, printme
MOV seg_print_me, seg printme
call far off_print_me
db 'hello', 0
MOV ah, 0
int 16h
ret
;*******************************
printme proc far
MOV cs:origSI, si ; protect SI register.
MOV cs:origDS, ds ; protect DS register.
pop si ; get return address (IP).
pop ds ; get return segment.
push ax ; store ax register.
next_char:
MOV al, ds:[si]
inc si ; next byte.
cmp al, 0
jz printed
MOV ah, 0eh ; teletype function.
int 10h
JMP next_char ; loop.
printed:
pop ax ; re-store ax register.
push ds ; ds:si should point to next
;command after the call instruction and string definition.
MOV ds, cs:origDS ; re-store ds register.
push si ; save new return address into
;the stack.
MOV si, cs:origSI ; re-store si register.
retf
; variables to store the original value
;of SI and DS registers:
origSI dw ?
Bi ging Chng 2

origDS dw ?
endp
;*******************************

V d 10. Truyn tham s khi chy chng trnh

; this sample prints out the command line parameters.
; in dos you simply add this line after the executable,
; for example:

; param p1 p2 p3

; in emulator it is possible to set parameters
; by selecting "set command line paramters" from the "file" menu.

name "param"
org 100h

JMP start
buffer db 30 dup (' ')
msg db 'no command line parameters!', 0Dh,0Ah, '$'
start:
MOV si, 80h ; cmd parameters offset.
; copy command line to our buffer:
xor cx, cx ; zero cx register.
MOV cl, [si] ; get command line size.
lea di, buffer ; load buffer address to di.

cmp cx, 0 ; cx = 0 ?
jz no_param ; then skip the copy.

inc si ; copy from second byte.
next_char:
MOV al, [si]
MOV [di], al
inc si
inc di
loop next_char

; set '$' sign in the END of the buffer:
MOV byte ptr [di], '$'

; print out the buffer:
lea dx, buffer
MOV ah, 09h
int 21h

JMP exit ; skip error message.

no_param:
Bi ging Chng 2

; print out the error message:
lea dx, msg
MOV ah, 09h
int 21h

exit:
MOV ah, 0
int 16h

RET ; return control to the operating system.

V d 11. File:
File example:
org 100h
MOV ah, 3ch
MOV cx, 0
MOV dx, offset filename
MOV ah, 3ch
int 21h ; create file...
MOV handle, ax

MOV bx, handle
MOV dx, offset data
MOV cx, data_size
MOV ah, 40h
int 21h ; write to file...

MOV al, 0
MOV bx, handle
MOV cx, 0
MOV dx, 7
MOV ah, 42h
int 21h ; seek...

MOV bx, handle
MOV dx, offset buffer
MOV cx, 4
MOV ah, 3fh
int 21h ; read from file...

MOV bx, handle
MOV ah, 3eh
int 21h ; close file...
ret

filename db "myfile.txt", 0
handle dw ?
data db " hello files! "
data_size=$-offset data
Bi ging Chng 2

buffer db 4 dup(' ')
V d 12. File IO

name "fileio"
; general rules for file system emulation:
; 1. the emulator emulates all drive paths in c:\emu8086\vdrive\
; for example: the real path for "c:\test1" is "c:\emu8086\vdrive\c\test1"
; 2. paths without drive letter are emulated to c:\emu8086\MyBuild\
; for example: the real path for "myfile.txt" is "c:\emu8086\MyBuild\myfile.txt"
; 3. if compiled file is running outside of the emulator rules 1 and 2 do not apply.
; ==========================================================
; run this example slowly in step-by-step mode and observe what it does.
; ===========================================================
org 100h

JMP start

dir1 db "c:\test1", 0
dir2 db "test2", 0
dir3 db "newname", 0
file1 db "c:\test1\file1.txt", 0
file2 db "c:\test1\newfile.txt", 0
file3 db "t1.txt", 0
handle dw ?

text db "lazy dog jumps over red fox."
text_size = $ - offset text
text2 db "hi!"
text2_size = $ - offset text2

start:
MOV ax, cs
MOV dx, ax
MOV es, ax

; create c:\emu8086\vdrive\C\test1
MOV dx, offset dir1
MOV ah, 39h
int 21h

; create c:\emu8086\MyBuild\test2
MOV dx, offset dir2
MOV ah, 39h
int 21h

; rename directory: c:\emu8086\MyBuild\test2 to c:\emu8086\MyBuild\newname
MOV ah, 56h
MOV dx, offset dir2 ; existing.
MOV di, offset dir3 ; new.
int 21h
Bi ging Chng 2

; create and open file: c:\emu8086\vdrive\C\test1\file1.txt
MOV ah, 3ch
MOV cx, 0
MOV dx, offset file1
int 21h
jc err
MOV handle, ax
; write to file:
MOV ah, 40h
MOV bx, handle
MOV dx, offset text
MOV cx, text_size
int 21h
; close c:\emu8086\vdrive\C\test1\file1.txt
MOV ah, 3eh
MOV bx, handle
int 21h
err:
nop
; rename fileL c:\emu8086\vdrive\C\test1\file1.txt to c:\test1\newfile.txt
MOV ah, 56h
MOV dx, offset file1 ; existing.
MOV di, offset file2 ; new.
int 21h
; delete file c:\emu8086\vdrive\C\test1\newfile.txt
MOV ah, 41h
int 21h

; delete directory: c:\emu8086\vdrive\C\test1
MOV ah, 3ah
MOV dx, offset dir1
int 21h

; create and open file: c:\emu8086\MyBuild\t1.txt
MOV ah, 3ch
MOV cx, 0
int 21h
jc err2
MOV handle, ax
; seek:
MOV ah, 42h
MOV bx, handle
MOV al, 0
MOV cx, 0
MOV dx, 10
int 21h
; write to file:
Bi ging Chng 2

MOV ah, 40h
MOV bx, handle
MOV dx, offset text
MOV cx, text_size
int 21h
; seek:
MOV ah, 42h
MOV bx, handle
MOV al, 0
MOV cx, 0
MOV dx, 2
int 21h
; write to file:
MOV ah, 40h
MOV bx, handle
MOV dx, offset text2
MOV cx, text2_size
int 21h
; close c:\emu8086\MyBuild\t1.txt
MOV ah, 3eh
MOV bx, handle
int 21h
err2:
nop
; delete file c:\emu8086\MyBuild\t1.txt
MOV ah, 41h
int 21h
; delete directory: c:\emu8086\MyBuild\newname
MOV ah, 3ah
MOV dx, offset dir3
int 21h

ret
V d 13. Giao tip 8255, nhp xut qua khe cm ISA
.MODEL SMALL
.STACK 100h
.DATA
Led_data DB 01h,02h,04h,08h,10h,20h,40h,80h
.CODE
Main PROC
MOV AX,@DATA
MOV DS, AX ; Gn a ch cho Data segment
MOV AL,80h ; nh cu hnh cho 8255
MOV DX,303h ; Port A: xut, Port B: xut
OUT DX,AL ; Port C: xut
MOV BX,0

Lap:
MOV AL,Led_data[BX]
Bi ging Chng 2

MOV DX,300h ; a ch LED
OUT DX,AL

MOV CX,0FFh
Delay: ; To thi gian tr
PUSH CX
MOV CX,0FFFFh
LOOP $
POP CX
LOOP delay

INC BX
CMP BX,8 ; LED c 8 trng thi
JNE lap

MOV AH,4Ch ; Kt thc chuong trnh
INT 21h
Main ENDP
END Main

Bi ging Chng 2

2.6 Cu hi v bi tp

Bi 1. Vit CT nhp vo 1 k t, xut ra k t
V d:
Moi ban nhap 1 ky tu: b
Ky tu va nhp: b
Bi 2. Vit chng trnh xut ra mn hnh mt s dng.
V d:
De chay duoc 1 CT hop ngu ban can thuc hien cac buoc sau:
Dich file ASM thanh file OBJ
Lien ket file OBJ thanh file EXE
Chay file EXE
Bi 3. Vit CT nhp vo 1 k t, xut ra k t lin trc v lin sau.
V d:
Ky tu lien truoc: a
Ky tu lien sau: c

Bi 4. Vit CT nhp vo 1 k t thng. In ra k t Hoa
V d:
Ky tu Hoa: B

Bi 5. Vit CT nhp vo 1 k t hoa. In ra k t thng
V d:
Moi ban nhap 1 ky tu: B
Ky tu thng: b

Bi 6. Vit chng trnh nhp vo 2 s nguyn dng x1, x2 (1 x2 < x1 < 9). Xut ra kt qu
cc php tnh: x1-1, x1 +2, x1+x2, x1-x2
V d:
x1 = 5
x2 = 3
x1 1 = 4
x1 + 1 = 6
x1 + x2 = 8
x1 x2 = 7
M rng
1. T tm hiu xem hm no trong ngt 21h dng nhp mt xu k t ? Ngoi ngt 21h,
cn ngt no c th dng nhp xut t bn phm ? (dng NortonGuide hoc
TechHelp).
2. Vit chng trnh nhp tn v in ra mn hnh cu Hello + tn nhp.
3. Tm hiu xem ti sao khng c lnh MOV x1, x2 (x1,x2 l hai bin trong b nh)
4. Hai lnh INC AX v ADD AX, 1 khc nhau ch no ?
Hng dn
Bi 1. nhp 1 mt k t s dng hm 1 ca ngt 21h, xut, s dng hm 2.
V d:
MOV AH,1
int 21h ; kt qu trong AL
Bi ging Chng 2

MOV DL,AL ; k t cn xut trong DL
MOV AH,2
int 21h
Bi 2. Cp k t xung dng l 10,13. C th khai bo nhiu xu k t hoc chung mt xu.
V d:
Msg3 DB 10,13,9,1. Dich file ASM thanh file OBJ.$
Msg4 DB 10,13,9,2. Lien ket file OBJ thanh file EXE.$

Hoc

Msg34 DB 10,13,9,1. Dich file ASM thanh file OBJ.
DB 10,13,9,2. Lien ket file OBJ thanh file EXE.$

Bi 3, 4. K t hoa v k t thng ca cng mt ch ci ting Anh cch nhau 20h. Do ,
chuyn i ch hoa thnh ch thng v ngc li, ch cn dng lnh ADD, SUB.

Bi 5. chuyn i cc k t 0 9 thnh s 0 9 ch cn thc hin php tr i 48 (m ca
0). Sau khi thc hin php tnh, chuyn i thnh k t v in ra mn hnh (c th dng biu
din Hex).

Bi ging Chng 3
Vi x l - Vi iu khin Gii thiu chung v vi iu khin

CHNG 3.
GII THIU CHUNG V VI IU KHIN

Mc tiu:

Gip sinh vin hiu c cu trc phn cng, s chn v cc mch ph tr ca h vi iu
khin 8051; nm c v bit cch vn dng cc ch a ch trong lp trnh; nm c tp
lnh v phng php lp trnh cho h vi iu khin 8051.

Tm tt hc phn:

Cu trc phn cng v t chc b nh
Gii thiu chung
S cu trc
M t chc nng cc chn
Hot ng Reset
T chc b nh
Cc ch nh a ch
Tp lnh
Lp trnh hp ng (Assembly) cho vi iu khin 8051
Trnh dch hp ng
Cng vo/ra v lp trnh
B m/nh thi v lp trnh
Lp trnh ngt
Bi ging Chng 3

3.1 Gii thiu chung
B Vi x l c kh nng vt bc so vi cc h thng khc v kh nng tnh ton,
x l, v thay i chng trnh linh hot theo mc ch ngi dng, c bit hiu qu
i vi cc bi ton v h thng ln.Tuy nhin i vi cc ng dng nh, tm tnh ton
khng i hi kh nng tnh ton ln th vic ng dng vi x l cn cn nhc. Bi v h
thng d ln hay nh, nu dng vi x l th cng i hi cc khi mch in giao tip
phc tp nh nhau. Cc khi ny bao gm b nh cha d liu v chng trnh thc
hin, cc mch in giao tip ngoi vi xut nhp v iu khin tr li, cc khi ny
cng lin kt vi vi x l th mi thc hin c cng vic. kt ni cc khi ny i
hi ngi thit k phi hiu bit tinh tng v cc thnh phn vi x l, b nh, cc thit
b ngoi vi. H thng c to ra kh phc tp, chim nhiu khng gian, mch in phc
tp v vn chnh l trnh ngi thit k. Kt qu l gi thnh sn phm cui cng
rt cao, khng ph hp p dng cho cc h thng nh.
V mt s nhc im trn nn cc nh ch to tch hp mt t b nh v mt s
mch giao tip ngoi vi cng vi vi x l vo mt IC duy nht c gi l
Microcontroller-Vi iu khin. Vi iu khin c kh nng tng t nh kh nng ca vi
x l, nhng cu trc phn cng dnh cho ngi dng n gin hn nhiu. Vi iu
khin ra i mang li s tin li i vi ngi dng, h khng cn nm vng mt khi
lng kin thc qu ln nh ngi dng vi x l, kt cu mch in dnh cho ngi
dng cng tr nn n gin hn nhiu v c kh nng giao tip trc tip vi cc thit b
bn ngoi. Vi iu khin tuy c xy dng vi phn cng dnh cho ngi s dng n
gin hn, nhng thay vo li im ny l kh nng x l b gii hn (tc x l chm
hn v kh nng tnh ton t hn, dung lng chng trnh b gii hn). Thay vo , Vi
iu khin c gi thnh r hn nhiu so vi vi x l, vic s dng n gin, do n
c ng dng rng ri vo nhiu ng dng c chc nng n gin, khng i hi tnh
ton phc tp.
Vi iu khin c ng dng trong cc dy chuyn t ng loi nh, cc robot c
chc nng n gin, trong my git, t v.v...
Nm 1976 Intel gii thiu b vi iu khin (microcontroller) 8748, mt chip tng
t nh cc b vi x l v l chip u tin trong h MCS-48. phc tp, kch thc v
kh nng ca Vi iu khin tng thm mt bc quan trng vo nm 1980 khi intel tung
ra chip 8051, b Vi iu khin u tin ca h MCS-51 v l chun cng ngh cho nhiu
h Vi iu khin c sn xut sau ny. Sau rt nhiu h Vi iu khin ca nhiu nh
Bi ging Chng 3

ch to khc nhau ln lt c a ra th trng vi tnh nng c ci tin ngy cng
mnh.
3.1.1 ng dng ca vi iu khin
V c bn, vi iu khin rt n gin. Chng ch bao gm ti thiu mt s thnh phn
sau:
- Mt b vi x l ti gin c s dng nh b no ca h thng
- Ty theo cng ngh ca mi hng sn xut, c th c thm b nh, cc chn nhp/xut
tn hiu, b m, b nh thi, cc b chuyn i tng t/s (A/D),
- Tt c chng c t trong mt v chp tiu chun.
- Mt phn mm n gin c th iu khin c ton b hot ng ca vi iu khin v
c th d dng cho ngi s dng nm bt.
Da trn nguyn tc c bn trn, rt nhiu h vi iu khin c pht trin v ng dng
mt cch thm lng nhng mnh m vo mi mt ca i sng ca con ngi. Mt s ng dng
c bn thnh cng c th k ra sau y:
- Nhng thnh phn in t c nhng vo vi iu khin c th trc tip hoc qua cc
thit b vo ra (cng tc, nt bm, cm bin, LCD, r le, ) iu khin rt nhiu thit b
v h thng nh thit b t ng trong cng nghip, iu khin nhit , dng in, ng
c,
- Gi thnh rt thp khin cho chng c nhng vo rt nhiu thit b thng minh trong
i sng con ngi nh ti vi, my git, iu ha nhit , my nghe nhc,
3.1.2 Hot ng ca vi iu khin.
Mc d c rt nhiu h vi iu khin c pht trin cng nh nhiu chng trnh iu
khin to ra cho chng, nhng tt c chng vn c mt s im chung c bn. Do nu ta hiu
cn k mt h th vic tm hiu thm mt h vi iu khin mi l hon ton n gin. Mt kch
bn chung cho hot ng ca mt vi iu khin nh sau:
1. Khi khng c ngun in cung cp, vi iu khin ch l mt con chip c chng trnh
np sn vo trong v khng c hot ng g xy ra.
2. Khi c ngun in, mi hot ng bt u c xy ra vi tc cao. n v iu khin
logic c nhim v iu khin tt c mi hot ng. N kha tt c cc mch khc, tr
mch giao ng thch anh. Sau mini giy u tin tt c sn sng hot ng.
3. in p ngun nui t n gi tr ti a ca n v tn s giao ng tr nn n nh. Cc
bit ca cc thanh ghi SFR cho bit trng thi ca tt c cc mch trong vi iu khin.
Ton b vi iu khin hot ng theo chu k ca chui xung chnh.
4. Thanh ghi b m chng trnh (Program Counter) c xa v 0. Cu lnh t a ch
ny c gi ti b gii m lnh sau c thc thi ngay lp tc.
Bi ging Chng 3

5. Gi tr trong thanh ghi PC c tng ln 1 v ton b qu trnh c lp li vi triu
ln trong mt giy.

3.1.3 Cu trc chung ca vi iu khin
Nh ta thy, tt c cc hot ng trong cc vi iu khin c thc hin tc cao v kh n
gin, nhng vi iu khin chnh n s khng c tht s hu ch nu khng c mch c bit
lm cho n hon thin. C mt s mch c th sau y.
Read Only Memory (ROM)
Read Only Memory (ROM) l mt loi b nh c s dng lu vnh vin cc chng trnh
c thc thi. Kch c ca chng trnh c th c vit ph thuc vo kch c ca b nh ny.
ROM c th c tch hp trong vi iu khin hay thm vo nh l mt chip gn bn ngoi,
ty thuc vo loi vi iu khin. C hai ty chn c mt s nhc im. Nu ROM c thm
vo nh l mt chip bn ngoi, cc vi iu khin l r hn v cc chng trnh c th tn ti lu
hn ng k. Nhng ng thi, lm gim s lng cc chn vo/ra vi iu khin s dng vi
mc ch khc. ROM ni thng l nh hn v t tin hn, nhng l ghim thm c sn kt
ni vi mi trng ngoi vi. Kch thc ca dy ROM t 512B n 64KB
Random Access Memory (RAM)
Random Access Memory (RAM) l mt loi b nh s dng cho cc d liu lu tr
tm thi v kt qu trung gian c to ra v c s dng trong qu trnh hot ng
ca b vi iu khin. Ni dung ca b nh ny b xa mt khi ngun cung cp b tt.
Electrically Erasable Programmable ROM (EEPROM)
EEPROM l mt kiu c bit ca b nh ch c mt s loi vi iu khin. Ni
dung ca n c th c thay i trong qu trnh thc hin chng trnh (tng t nh
RAM), nhng vn cn lu gi vnh vin, ngay c sau khi mt in (tng t nh ROM).
Bi ging Chng 3

N thng c dng lu tr cc gi tr c to ra v c s dng trong qu trnh
hot ng (nh cc gi tr hiu chun, m, cc gi tr m, v.v..), m cn phi c
lu sau khi ngun cung cp ngt. Mt bt li ca b nh ny l qu trnh ghi vo l
tng i chm.

Cc thanh ghi chc nng c bit (SFR)
Thanh ghi chc nng c bit (Special Function Registers) l mt phn ca b nh RAM. Mc
ch ca chng c nh trc bi nh sn xut v khng th thay i c. Cc bit ca chng
c lin kt vt l ti cc mch trong vi iu khin nh b chuyn i A/D, modul truyn
thng ni tip, Mi s thay i trng thi ca cc bit s tc ng ti hot ng ca vi iu
khin hoc cc vi mch.
B m chng trnh (Program Counter)
B m chng trnh cha a ch ch n nh cha cu lnh tip theo s c kch hot. Sau
mi khi thc hin lnh, gi tr ca b m c tng ln 1. V l do nn chng trnh ch
thc hin c c tng lnh trong mt thi im.
Central Processor Unit (CPU)
y l mt n v c nhim v iu khin v gim st tt c cc hot ng bn trong
vi iu khin v ngi s dng khng th tc ng vo hot ng ca n. N bao gm
mt s n v con nh hn, trong quan trng nht l:
Bi ging Chng 3

- Instruction decoder is a part of the electronics which recognizes program
instructions and runs other circuits on the basis of that. The abilities of this
circuit are expressed in the "instruction set" which is different for each
microcontroller family.
- B gii m lnh c nhim v nhn dng cu lnh v iu khin cc mch
khc theo lnh gii m. Vic gii m pcj thc hin nh c tp lnh
instruction set. Mi h vi iu khin thng c cc tp lnh khc nhau.
- Arithmetical Logical Unit (ALU) Thc thi tt c cc thao tc tnh ton s hc
v logic.
- Thanh ghi tch ly (Accumulator) l mt thanh ghi SFR lin quan mt thit
vi hot ng ca ALU. N lu tr tt c cc d liu cho qu trnh tnh ton
v lu gi tr kt qu chun b cho cc tnh ton tip theo. Mt trong cc
thanh ghi SFR khc c gi l thanh ghi trng thi (Status Register) cho bit
trng thi ca cc gi tr lu trong thanh ghi tch ly.
Cc cng vo/ra (I/O Ports)
vi iu khin c th hot ng hu ch, n cn c s kt ni vi cc thit b ngoi
vi. Mi vi iu khin s c mt hoc mt s thanh ghi (c gi l cng) c kt ni
vi cc chn ca vi iu khin.

Chng c gi l cng vo/ra (I/O port) bi v chng c th thay i chc nng,
chiu vo/ra theo yu cu ca ngi dng.

Bi ging Chng 3

B dao ng (Oscillator)

B dao ng ng vai tr nhc trng lm nhim v ng b ha hot ng ca tt c cc mch
bn trong vi iu khin. N thng c to bi thch anh hoc gm n nh tn s. Cc
lnh khng c thc thi theo tc ca b dao ng m thng chm hn, bi v mi cu lnh
c thc hin qua nhiu bc. Mi loi vi iu khin cn s chu k khc nhau thc hin
lnh.
B nh thi/m (Timers/Counters)
Hu ht cc chng trnh s dng cc b nh thi trong hot ng ca mnh. Chng thng l
cc thanh ghi SFR 8 hoc 16 bit, sau mi xung dao ng clock, gi tr ca chng c tng ln.
Ngay khi thanh ghi trn, mt ngt s c pht sinh.

Bi ging Chng 3

Truyn thng ni tip

Kt ni song song gia vi iu khin v thit b ngoi vi c thc hin qua cc cng
vo/ra l gii php l tng vi khong cch ngn trong vi mt. Tuy nhin khi cn
truyn thng gia cc thit b khong cch xa th khng th dng kt ni song song, v
vy truyn thng ni tip l gii php tt nht.
Ngy nay, hu ht cc vi iu khin c mt s b iu khin truyn thng ni tip
nh mt trang b tiu chun. Chng c s dng ph thuc vo nhiu yu t khc nhau
nh:
- Bao nhiu thit b vi iu khin mun trao i d liu
- Tc trao i d liu
- Khong cch truyn
- Truyn/nhn d liu ng thi hay khng?
Chng trnh
Khng ging nh cc mch tch hp, ch cn kt ni cc thnh phn vi nhau v bt
ngun, vi iu khin cn phi lp trnh trc. vit mt chng trnh cho vi iu
khin, c mt vi ngn ng lp trnh bc thp c th s dng nh Assembly, C hay
Basic. Vit mt chng trnh bao gm vic vit cc cu lnh n gin theo mt th t
chng c th thc thi. C rt nhiu phn mm chy trn mi trng Windows cho php
xy dng cc chng trnh hon chnh cho cc h vi iu khin
3.2 Kin trc vi iu khin 8051
3.2.1 Chun 8051
H vi iu khin MCS-51 do Intel sn xut u tin vo nm 1980 l cc IC
thit k cho cc ng dng hng iu khin. Cc IC ny chnh l mt h thng vi x
l hon chnh bao gm cc cc thnh phn ca h vi x l: CPU, b nh, cc mch giao
tip, iu khin ngt.
MCS-51 l h vi iu khin s dng c ch CISC (Complex Instruction Set
Computer), c di v thi gian thc thi ca cc lnh khc nhau. Tp lnh cung cp cho
MCS-51 c cc lnh dng cho iu khin xut / nhp tc ng n tng bit.
MCS-51 bao gm nhiu vi iu khin khc nhau, b vi iu khin u tin l
8051 c 4KB ROM, 128 byte RAM v 8031, khng c ROM ni, phi s dng b nh
ngoi. Sau ny, cc nh sn xut khc nh Siemens, Fujitsu, cng c cp php
lm nh cung cp th hai.
MCS-51 bao gm nhiu phin bn khc nhau, mi phin bn sau tng thm mt s
Bi ging Chng 3

thanh ghi iu khin hot ng ca MCS-51.

AT89C51 l vi iu khin do Atmel sn xut, ch to theo cng ngh CMOS
c cc c tnh nh sau:
- 4 KB PEROM (Flash Programmable and Erasable Read Only Memory), c kh nng
ti 1000 chu k ghi xo
- Tn s hot ng t: 0Hz n 24 MHz
- 3 mc kha b nh lp trnh
- 128 Byte RAM ni.
- 4 Port xut /nhp I/O 8 bit.
- 2 b Timer/counter 16 Bit.
- 6 ngun ngt.
- Giao tip ni tip iu khin bng phn cng.
- 64 KB vng nh m ngoi
- 64 KB vng nh d liu ngoi.
- Cho php x l bit.
- 210 v tr nh c th nh v bit.
- 4 chu k my (4 s i vi thch anh 12MHz) cho hot ng nhn hoc chia.
- C cc ch ngh (Low-power Idle) v ch ngun gim (Power-down).
- Ngoi ra, mt s IC khc ca h MCS-51 c thm b nh thi th 3 v 256 byte RAM
ni.
Bi ging Chng 3

3.2.2 Chn vi iu khin 8051

Chip AT89C51 c cc tn hiu iu khin cn phi lu nh sau:
Tn hiu vo /EA trn chn 31 thng t ln mc cao ( +5V) hoc mc thp (GND).
Nu mc cao, 8951 thi hnh chng trnh t ROM ni trong khong a ch thp (4K hoc ti
a 8k i vi 89C52). Nu mc thp, chng trnh c thi hnh t b nh m rng (ti a
n 64Kbyte). Ngoi ra ngi ta cn dng /EA lm chn cp in p 12V khi lp trnh
EEPROM trong 8051.
Chn PSEN (Program store enable):
PSEN l chn tn hiu ra trn chn 29. N l tn hiu iu khin cho php chng trnh m
rng, PSEN thng c ni n chn /OE (Output Enable) ca mt EPROM hoc ROM
cho php c cc bytes m lnh.
Hy nh rng : bnh thng chn /PSEN s c th trng ( No Connect).Ch khi no cho /EA
mc thp th lc :
/PSEN s mc thp trong thi gian ly lnh. Cc m nh phn ca chng trnh c ly t
EPROM qua bus d liu v c cht vo thanh ghi lnh ca 8951 gii m lnh.
/PSEN mc th ng (mc cao) nu thi hnh chng trnh trong ROM ni ca 8951.
CC CHN NGUN:
AT89C51 hot ng ngun n +5V. Vcc c ni vo chn 40, v Vss (GND) c ni vo
chn 20.
Bi ging Chng 3

3.2.3 Cng vo/ra
Tt c cc vi iu khin 8051 u c 4 cng vo/ra 8 bit c th thit lp nh cng vo
hoc ra. Nh vy c tt c 32 chn I/O cho php vi iu khin c th kt ni vi cc thit
b ngoi vi.

Bi ging Chng 3

Chn vo/ra (I/O)
Hnh trn m t s n gin ca mch bn trong cc chn vi iu khin tr cng
P0 l khng c in tr ko ln (pull-up).

Chn ra
Mt mc logic 0 t vo bit ca thanh ghi P lm cho transistor m, ni chn tng
ng vi t.

Chn vo
Mt bit 1 t vo mt bit ca thanh ghi cng, transistor ng v chn tng ng
c ni vi ngun Vcc qua tr ko ln.

Port 0
Bi ging Chng 3

Port 0 l port c 2 chc nng cc chn 32 39 ca AT89C51:
- Chc nng I/O (xut/nhp): dng cho cc thit k nh. Tuy nhin, khi
dng chc nng ny th Port 0 phi dng thm cc in tr ko ln (pull-
up), gi tr ca in tr ph thuc vo thnh phn kt ni vi Port.
- Khi dng lm ng vo, Port 0 phi c set mc logic 1 trc .
- Chc nng a ch / d liu a hp: khi dng cc thit k ln, i hi phi
s dng b nh ngoi th Port 0 va l bus d liu (8 bit) va l bus a ch
(8 bit thp).
Ngoi ra khi lp trnh cho AT89C51, Port 0 cn dng nhn m khi lp trnh v
xut m khi kim tra (qu trnh kim tra i hi phi c in tr ko ln).

Port 1:
Port1 (chn 1 8) ch c mt chc nng l I/O, khng dng cho mc ch khc
(ch trong 8032/8052/8952 th dng thm P1.0 v P1.1 cho b nh thi th 3). Ti
Port 1 c in tr ko ln nn khng cn thm in tr ngoi.
Port 1 c kh nng ko c 4 ng TTL v cn dng lm 8 bit a ch thp
trong qu trnh lp trnh hay kim tra.
Khi dng lm ng vo, Port 1 phi c set mc logic 1 trc .
Port 2:
Port 2 (chn 21 28) l port c 2 chc nng:
- Chc nng I/O (xut / nhp)
- Chc nng a ch: dng lm 8 bit a ch cao khi cn b nh ngoi c a
ch 16 bit. Khi , Port 2 khng c dng cho mc ch I/O.
- Khi dng lm ng vo, Port 2 phi c set mc logic 1 trc .
- Khi lp trnh, Port 2 dng lm 8 bit a ch cao hay mt s tn hiu iu
khin.
Port 3:
Port 3 (chn 10 17) l port c 2 chc nng:
- Chc nng I/O. Khi dng lm ng vo, Port 3 phi c set mc logic 1
trc .
- Chc nng khc: m t nh bng 1.1
Bng 1.1: Chc nng cc chn ca Port 3

Bit Tn Chc nng
P3.0 RxD Ng vo port ni tip
P3.1 TxD Ng ra port ni tip
Bi ging Chng 3

P3.2

INT0
Ngt ngoi 0
P3.3
INT1
Ngt ngoi 1
P3.4 T0 Ng vo ca b nh thi 0
P3.5 T1 Ng vo ca b nh thi 1

P3.6

WR

Tn hiu iu khin ghi d liu ln b nh ngoi.
P3.7
RD
Tn hiu iu khin c t b nh d liu ngoi.

Cc chn ngun:

Chn 40: VCC = 5V 20%
Chn 20: GND
/PSEN (Program Store Enable):
/PSEN (chn 29) cho php c b nh chng trnh m rng i vi cc ng
dng s dng ROM ngoi, thng c ni n chn /OC (Output Control) ca
ROM c cc byte m lnh. /PSEN s mc logic 0 trong thi gian AT89C51 ly
lnh.Trong qu trnh ny, / PSEN s tch cc 2 ln trong 1 chu k my.
M lnh ca chng trnh c c t ROM thng qua bus d liu (Port0) v bus
a ch (Port0 + Port2).
Khi 8051 thi hnh chng trnh trong ROM ni, PSEN s mc logic 1.

ALE/ PROG (Address Latch Enable / Program):

ALE/ PROG (chn 30) cho php tch cc ng a ch v d liu ti Port 0
khi truy xut b nh ngoi. ALE thng ni vi chn Clock ca IC cht (74373,
74573).
Cc xung tn hiu ALE c tc bng 1/6 ln tn s dao ng trn chip v c th
c dng lm tn hiu clock cho cc phn khc ca h thng. Xung ny c th cm bng
cch set bit 0 ca SFR ti a ch 8Eh ln 1. Khi , ALE ch c tc dng khi dng lnh
MOVX hay MOVC. Ngoi ra, chn ny cn c dng lm ng vo
xung lp trnh cho ROM ni ( /PROG ).

EA /VPP (External Access) :

EA (chn 31) dng cho php thc thi chng trnh t ROM ngoi. Khi ni
chn 31 vi Vcc, AT89C51 s thc thi chng trnh t ROM ni (ti a 8KB), ngc
li th thc thi t ROM ngoi (ti a 64KB).

Ngoi ra, chn /EA c ly lm chn cp ngun 12V khi lp trnh cho ROM.
RST (Reset):
RST (chn 9) cho php reset AT89C51 khi ng vo tn hiu a ln mc 1
Bi ging Chng 3

trong t nht l 2 chu k my.
X1,X2:
Ng vo v ng ra b dao ng, khi s dng c th ch cn kt ni thm thch anh
v cc t nh hnh v trong s . Tn s thch anh thng s dng cho
AT89C51 l 12Mhz.

Gi tr C
1
, C
2
= 30 pF 10 pF

Hnh 1.3 S kt ni thch anh
3.1.1. T chc b nh 8051

Hnh 1.5 - Cc vng nh trong AT89C51

B nh ca h MCS-51 c th chia thnh 2 phn: b nh trong v b nh
ngoi. B nh trong bao gm 4 KB ROM v 128 byte RAM (256 byte trong 8052).
Cc byte RAM c a ch t 00h 7Fh v cc thanh ghi chc nng c bit (SFR) c
a ch t 80h 0FFh c th truy xut trc tip. i vi 8052, 128 byte RAM cao (a
ch t 80h 0FFh) khng th truy xut trc tip m ch c th truy xut gin tip (xem
thm trong phn tp lnh).

B nh chng trnh 64 KB
0000h FFFFh
iu khin bng PSEN

B nh d liu 64 KB
0000h FFFFh
iu khin bng RD v WR
ROM 4KB
0000h 0FFFh
RAM 128 byte
00h 7Fh

SFR
80h 0FFh
B nh trong B nh ngoi
Bi ging Chng 3

B nh ngoi bao gm b nh chng trnh (iu khin c bng tn hiu
PSEN ) v b nh d liu (iu khin bng tn hiu RD hay WR cho php c
hay ghi d liu). Do s ng a ch ca MCS-51 l 16 bit (Port 0 cha 8 bit thp v
Port 2 cha 8 bit cao) nn b nh ngoi c th gii m ti a l 64KB.
3.2.4 T chc b nh trong
B nh trong ca MCS-51 gm ROM v RAM. RAM bao gm nhiu vng c
mc ch khc nhau: vng RAM a dng (a ch byte t 30h 7Fh v c thm vng
80h 0FFh ng vi 8052), vng c th a ch ha tng bit (a ch byte t 20h
2Fh, gm 128 bit c nh a ch bit t 00h 7Fh), cc bank thanh ghi (t 00h
1Fh) v cc thanh ghi chc nng c bit (t 80h 0FFh).

Cc thanh ghi chc nng c bit (SFR Special Function Registers):
Bng 1.2 Cc thanh ghi chc nng c bit
a
ch
byte
C th
nh a
ch bit
Khng nh a ch bit
F8h
F0h B
E8h
E0h ACC
D8h
D0h PSW
C8h (T2CON) (RCAP2L) (RCAP2H) (TL2) (TH2)
C0h
B8h IP SADEN
B0h P3
A8h IE SADDR
A0h P2
98h SCON SBUF BRL BDRCON
90h P1
88h TCON TMOD TL0 TH0 TL1 TH1 AUXR CKCON
80h P0 SP DPL DPH PCON

Bi ging Chng 3

Cc thanh ghi c th nh a ch bit s c a ch bit bt u v a ch byte
trng nhau. V d nh: thanh ghi P0 c a ch byte l 80h v c a ch bit bt u t
80h (ng vi P0.0) n 87h (ng vi P0.7). Chc nng cc thanh ghi ny s m t
trong phn sau.
RAM ni:
chia thnh cc vng phn bit: vng RAM a dng (30h 7Fh), vng RAM c
th nh a ch bit (20h 2Fh) v cc bank thanh ghi (00h 1Fh).

a ch byte a ch bit Chc nng
7F

30

Vng RAM a dng
2F 7F 7E 7D 7C 7B 7A 79 78
2E 77 76 75 74 73 72 71 70
2D 6F 6E 6D 6C 6B 6A 69 68
2C 67 66 65 64 63 62 61 60
2B 5F 5E 5D 5C 5B 5A 59 58
2A 57 56 55 54 53 52 51 50
29 4F 4E 4D 4C 4B 4A 49 48
28 47 46 45 44 43 42 41 40
27 3F 3E 3D 3C 3B 3A 39 38
26 37 36 35 34 33 32 31 30
25 2F 2E 2D 2C 2B 2A 29 28
24 27 26 25 24 23 22 21 20
23 1F 1E 1D 1C 1B 1A 19 18
22 17 16 15 14 13 12 11 10
21 0F 0E 0D 0C 0B 0A 09 08
20 07 06 05 04 03 02 01 00

Vng c th nh a ch bit
1F
18

Bank 3
17
10

Bank 2
1F
08

Bank 1
07
00

Bank thanh ghi 0 ( mc nh cho R0-R7)

Cc bank thanh ghi

RAM a dng:
RAM a dng c 80 byte t a ch 30h 7Fh c th truy xut mi ln 8 bit
bng cch dng ch a ch trc tip hay gin tip.
Cc vng a ch thp t 00h 2Fh cng c th s dng cho mc ich nh trn
ngoi cc chc nng cp nh phn sau.
RAM c th nh a ch bit:
Bi ging Chng 3

Vng a ch t 20h 2Fh gm 16 byte (= 128 bit) c th thc hin ging nh
vng RAM a dng (mi ln 8 bit) hay thc hin truy xut mi ln 1 bit bng cc lnh
x l bit. Vng RAM ny c cc a ch bit bt u ti gi tr 00h v kt thc ti 7Fh.
Nh vy, a ch bt u 20h (gm 8 bit) c a ch bit t 00h 07h; a ch kt
thc 2Fh c a ch bit t 78h Fh.
Cc bank thanh ghi:
Vng a ch t 00h 1Fh c chia thnh 4 bank thanh ghi: bank 0 t 00h
07h, bank 1 t 08h 0Fh, bank 2 t 10h 17h v bank 3 t 18h 1Fh. Cc bank
thanh ghi ny c i din bng cc thanh ghi t R0 n R7. Sau khi khi ng h
thng th bank thanh ghi c s dng l bank 0.
Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi c
truy xut bi cc thanh ghi R0 n R7. Vic thay i bank thanh ghi c th thc hin
thng qua thanh ghi t trng thi chng trnh (PSW). Cc bank thanh ghi ny cng
c th truy xut bnh thng nh vng RAM a dng ni trn.
3.2.5 T chc b nh ngoi
MCS-51 c b nh theo cu trc Harvard: phn bit b nh chng trnh v d
liu. Chng trnh v d liu c th cha bn trong nhng vn c th kt ni vi
64KB chng trnh v 64KB d liu. B nh chng trnh c truy xut thng qua
chn PSEN cn b nh d liu c truy xut thng qua chn WR hay RD .
Lu rng vic truy xut b nh chng trnh lun lun s dng a ch 16 bit cn
b nh d liu c th l 8 bit hay 16 bit tu theo cu lnh s dng. Khi dng b nh d
liu 8 bit th c th dng Port 2 nh l Port I/O thng thng cn khi dng ch 16
bit th Port 2 ch dng lm cc bit a ch cao.
Port 0 c dng lm a ch thp/ d liu a hp. Tn hiu ALE tch byte a
ch v a vo b cht ngoi.
Trong chu k ghi, byte d liu s tn ti Port 0 va trc khi /WR tch cc v
c gi cho n khi /WR khng tch cc.Trong chu k c, byte nhn c chp
nhn va trc khi /RD khng tch cc.
B nh chng trnh ngoi c x l 1 trong 2 iu kin sau:
- Tn hiu /EA tch cc ( = 0).
- Gi tr ca b m chng trnh (PC Program Counter) ln hn kch
thc b nh.

Bi ging Chng 3

PCH: Program Counter High PCL: Program Counter Low
DPH: Data Pointer High DPL: Data Pointer Low
Hnh 1.7 Thc thi b nh chng trnh ngoi
B nh chng trnh ngoi:
Qu trnh thc thi lnh khi dng b nh chng trnh ngoi c th m t nh
hnh 1.7. Trong qu trnh ny, Port 0 v Port 2 khng cn l cc Port xut nhp m
cha a ch v d liu. S kt ni vi b nh chng trnh ngoi m t nh hnh
1.8.
Trong mt chu k my, tn hiu ALE tch cc 2 ln. Ln th nht cho php
74HC573 m cng cht a ch byte thp, khi ALE xung 0 th byte thp v byte cao
ca b m chng trnh u c nhng ROM cha xut v PSEN cha tch cc, khi
tn hiu ALE ln 1 tr li th Port 0 c d liu l m lnh. ALE tch cc ln th hai
c gii thch tng t v byte 2 c c t b nh chng trnh. Nu lnh ang thc
thi l lnh 1 byte th CPU ch c Opcode, cn byte th hai b qua.

Bi ging Chng 3

B nh d liu ngoi:
B nh d liu ngoi c truy xut bng lnh MOVX thng qua cc thanh ghi xc
nh a ch DPTR (16 bit) hay R0, R1 (8 bit). S kt ni vi b nh d liu ngoi
m t nh hnh 1.9.

Qu trnh thc hin c hay ghi d liu c cho php bng tn hiu RD
hay

WR
(chn P3.7 v P3.6).
B nh chng trnh v d liu dng chung:
Trong cc ng dng pht trin phn mm xy dng da trn AT89C51, ROM s
c lp trnh nhiu ln nn d lm h hng ROM. Mt gii php t ra l s dng
RAM cha cc chng trnh tm thi. Khi , RAM va l b nh chng trnh
va l b nh d liu. Yu cu ny c th thc hin bng cch kt hp chn RD
v
chn
PSEN
thng qua cng AND. Khi thc hin c m lnh, chn
PSEN
tch cc
cho php c t RAM v khi c d liu, chn
RD
s tch cc. S kt ni m t
nh hnh 1.10.
Gii m a ch
Trong cc ng dng da trn AT89C51, ngoi giao tip b nh d liu, vi iu
khin cn thc hin giao tip vi cc thit b khc nh bn phm, led, ng c, Cc
thit b ny c th giao tip trc tip thng qua cc Port. Tuy nhin, khi s lng cc
thit b ln, cc Port s khng thc hin iu khin. Gii php a ra l xem cc
thit b ny ging nh b nh d liu. Khi , cn phi thc hin qu trnh gii m a
ch phn bit cc thit b ngoi vi khc nhau.
Qu trnh gii m a ch thng c thc hin thng qua cc IC gii m nh
74139 (2 -> 4), 74138 ( 3 -> 8), 74154 (4 -> 16). Ng ra ca cc IC gii m s c
a ti chn chn chip ca RAM hay b m khi iu khin ngoi vi.
3.2.6 Cc thanh ghi chc nng c bit (SFRs - Special Function Registers)
Thanh ghi tch lu (Accumulator)
Thanh ghi tch lu l thanh ghi s dng nhiu nht trong AT89C51, c k
hiu trong cu lnh l A. Ngoi ra, trong cc lnh x l bit, thanh ghi tch lu c k
hiu l ACC.
Thanh ghi tch lu c th truy xut trc tip thng qua a ch E0h (byte) hay truy
xut tng bit thng qua a ch bit t E0h n E7h.
VD: Cu lnh:

MOV A,#1
MOV 0E0h,#1
c cng kt qu.
Hay:

SETB ACC.4
SETB 0E4h
cng tng t.

Bi ging Chng 3

Thanh ghi B
Thanh ghi B dng cho cc php ton nhn, chia v c th dng nh mt thanh ghi
tm, cha cc kt qu trung gian.
Thanh ghi B c a ch byte F0h v a ch bit t F0h F7h c th truy xut ging
nh thanh ghi A.
Thanh ghi t trng thi chng trnh (PSW - Program Status Word)
Thanh ghi t trng thi chng trnh PSW nm ti a ch D0h v c cc a ch
bit t D0h D7h, bao gm 7 bit (1 bit khng s dng) c cc chc nng nh sau:
Bng 1.3 Chc nng cc bit trong thanh ghi PSW
Bit 7 6 5 4 3 2 1 0
Chc
nng

CY

AC

F0

RS1

RS0

OV

-

P

CY (Carry): c nh, thng c dng cho cc lnh ton hc (C = 1 khi c
nh trong php cng hay mn trong php tr)
AC (Auxiliary Carry): c nh ph (thng dng cho cc php ton BCD). F0
(Flag 0): c s dng tu theo yu cu ca ngi s dng.
RS1, RS0: dng chn bank thanh ghi s dng. Khi reset h thng, bank 0 s
c s dng.
Bng 1.4 Chn bank thanh ghi
RS1 RS0 Bank thanh ghi
0 0 Bank 0
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3

OV (Overflow): c trn. C OV = 1 khi c hin tng trn s hc xy ra (dng
cho s nguyn c du).
P (Parity): kim tra parity (chn). C P = 1 khi tng s bit 1 trong thanh ghi A
l s l (ngha l tng s bit 1 ca thanh ghi A cng thm c P l s chn). V d nh:
A = 10101010b c tng cng 4 bit 1 nn P = 0. C P thng c dng kim tra
li truyn d liu.
Thanh ghi con tr stack (SP Stack Pointer)
Con tr stack SP nm ti a ch 81h v khng cho php nh a ch bit. SP
dng ch n nh ca stack. Stack l mt dng b nh lu tr dng LIFO (Last In
First Out) thng dng lu tr a ch tr v khi gi mt chng trnh con. Ngoi ra,
stack cn dng nh b nh tm lu li v khi phc cc gi tr cn thit.
i vi AT89C51, stack c cha trong RAM ni (128 byte i vi
8031/8051 hay 256 byte i vi 8032/8052). Mc nh khi khi ng, gi tr ca SP l
07h, ngha l stack bt u t a ch 08h (do hot ng lu gi tr vo stack yu cu
phi tng ni dung thanh ghi SP trc khi lu). Nh vy, nu khng gn gi tr cho
thanh ghi SP th khng c s dng cc bank thanh ghi 1, 2, 3 v c th lm sai d
liu.

i vi cc ng dng thng thng khng cn dng nhiu n stack, c th
Bi ging Chng 3

khng cn khi ng SP m dng gi tr mc nh l 07h. Tuy nhin, nu cn, ta c th
xc nh li vng stack cho MCS-51.
Con tr d liu DPTR (Data Pointer)
Con tr d liu DPTR l thanh ghi 16 bit bao gm 2 thanh ghi 8 bit: DPH
(High) nm ti a ch 83h v DPL (Low) nm ti a ch 82h. Cc thanh ghi ny
khng cho php nh a ch bit. DPTR c dng khi truy xut n b nh c a ch
16 bit.
Cc thanh ghi port
Cc thanh ghi P0 ti a ch 80h, P1 ti a ch 90h, P2, ti a ch A0h, P3 ti a
ch B0h l cc thanh ghi cht cho 4 port xut / nhp (Port 0, 1, 2, 3). Tt c cc thanh
ghi ny u cho php nh a ch bit trong a ch bit ca P0 t 80h 87h,
P1 t 90h 97h, P2 t A0h A7h, P3 t B0h B7h. Cc a ch bit ny c th thay
th bng ton t .
V d nh: 2 lnh sau l tng ng:

SETB P0.0
SETB 80h
Thanh ghi port ni tip (SBUF - Serial Data Buffer)
Thanh ghi port ni tip ti a ch 99h thc cht bao gm 2 thanh ghi: thanh ghi
nhn v thanh ghi truyn. Nu d liu a ti SBUF th l thanh ghi truyn, nu d liu
c c t SBUF th l thanh ghi nhn. Cc thanh ghi ny khng cho php nh a
ch bit.
Cc thanh ghi nh thi (Timer Register)
Cc cp thanh ghi (TH0, TL0), (TH1, TL1) v (TH2, TL2) l cc thanh ghi
dng cho cc b nh thi 0, 1 v 2 trong b nh thi 2 ch c trong 8032/8052.
Ngoi ra, i vi h 8032/8052 cn c thm cp thanh ghi (RCAP2L, RCAP2H) s
dng cho b nh thi 2 (s tho lun trong phn hot ng nh thi).
Cc thanh ghi iu khin
Bao gm cc thanh ghi IP (Interrupt Priority), IE (Interrupt Enable), TMOD
(Timer Mode), TCON (Timer Control), T2CON (Timer 2 Control), SCON (Serial port
control) v PCON (Power control).
- Thanh ghi IP ti a ch B8h cho php chn mc u tin ngt khi c 2 ngt
xy ra ng thi. IP cho php nh a ch bit t B8h BFh.
- Thanh ghi IE ti a ch A8h cho php hay cm cc ngt. IE c a ch bit
t A8h AFh.
- Thanh ghi TMOD ti a ch 89h dng chn ch hot ng cho cc
b nh thi (0, 1) v khng cho php nh a ch bit.
- Thanh ghi TCON ti a ch 88h iu khin hot ng ca b nh thi v
ngt. TCON c a ch bit t 88h 8Fh.
- Thanh ghi T2CON ti a ch C8h iu khin hot ng ca b nh
thi 2. T2CON c a ch bit t C8h CFh.
Bi ging Chng 3

- Thanh ghi SCON ti a ch 98h iu khin hot ng ca port ni tip.
SCON c a ch bit t 98h 9Fh.
Cc thanh ghi ni trn s c tho lun thm cc phn sau.
Thanh ghi iu khin ngun PCON
Thanh ghi PCON ti a ch 87h khng cho php nh a ch bit bao gm cc bit
nh sau:
Bng 1.5 Chc nng cc bit trong thanh ghi PCON
Bit 7 6 5 4 3 2 1 0
Chc
nng

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

SMOD1 (Serial Mode 1): = 1 cho php tng gp i tc port ni tip trong
ch 1, 2 v 3.
SMOD0 (Serial Mode 0): cho php chn bit SM0 hay FE trong thanh ghi
SCON ( = 1 chn bit FE).
POF (Power-off Flag): dng nhn dng loi reset. POF = 1 khi m ngun. Do
, xc nh loi reset, cn phi xo bit POF trc .
GF1, GF0 (General purpose Flag): cc bit c dnh cho ngi s dng.
PD (Power Down): c xo bng phn cng khi hot ng reset xy ra. Khi
bit PD = 1 th vi iu khin s chuyn sang ch ngun gim. Trong ch ny:
- Ch c th thot khi ch ngun gim bng cch reset.
- Ni dung RAM v mc logic trn cc port c duy tr.
- Mch dao ng bn trong v cc chc nng khc ngng hot ng.
- Chn ALE v PSEN
mc thp.

-
Yu cu Vcc phi c in p t nht l 2V v phc hi Vcc = 5V t nht 10 chu
k trc khi chn RESET xung mc thp ln na.
IDL (Idle): c xo bng phn cng khi hot ng reset hay c ngt xy ra. Khi
bit IDL = 1 th vi iu khin s chuyn sang ch ngh. Trong ch ny:
- Ch c th thot khi ch ngun gim bng cch reset hay c ngt xy ra.
- Trng thi hin hnh ca vi iu khin c duy tr v ni dung cc thanh ghi
khng i.
- Mch dao ng bn trong khng gi c tn hiu n CPU.

- Chn ALE v PSEN
mc cao.

Lu rng cc bit iu khin PD v IDL c tc dng chnh trong tt c cc IC
h MSC-51 nhng ch c th thc hin c trong cc phin bn CMOS.

3.2.7 B m v b nh thi
8051 c hai b nh thi l Timer 0 v Timer1, phn ny chng ta bn v cc thanh
ghi ca chng v sau trnh by cch lp trnh chng nh th no to ra cc tr
thi gian.
Cc thanh ghi c s ca b nh thi.
C hai b nh thi Timer 0 v Timer 1 u c di 16 bt c truy cp nh hai
thanh ghi tch bit byte thp v byte cao. Chng ta s bn ring v tng thanh ghi.
Bi ging Chng 3

Cc thanh ghi ca b Timer 0.
Thanh ghi 16 bt ca b Timer 0 c truy cp nh byte thp v byte cao. Thanh ghi
byte thp c gi l TL0 (Timer 0 bow byte) v thanh ghi byte cao l TH0 (Timer 0
High byte). Cc thanh ghi ny c th c truy cp nh mi thanh ghi khc chng hn
nh A, B, R0, R1, R2 v.v... V d, lnh MOV TL0, #4FH l chuyn gi tr 4FH vo
TL0, byte thp ca b nh thi 0. Cc thanh ghi ny cng c th c c nh cc
thanh ghi khc. V d MOV R5, TH0 l lu byte cao TH0 ca Timer 0 vo R5.

TH0 TL0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Hnh: Cc thanh ghi ca b Timer 0
Cc thanh ghi ca b Timer 1.
B nh thi gian Timer 1 cng di 16 bt v thanh ghi 16 bt ca n c chia ra
thnh hai byte l TL1 v TH1. Cc thanh ghi ny c truy cp v c ging nh cc
thanh ghi ca b Timer 0 trn.

TH1 TL1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Hnh: Cc thanh ghi ca b Timer 1
Thanh ghi TMOD (ch ca b nh thi).
C hai b nh thi Timer 0 v Timer 1 u dng chung mt thanh ghi c gi l
IMOD thit lp cc ch lm vic khc nhau ca b nh thi. Thanh ghi TMOD l
thanh ghi 8 bt gm c 4 bt thp c thit lp dnh cho b Timer 0 v 4 bt cao dnh
cho Timer 1. Trong hai bt thp ca chng dng thit lp ch ca b nh thi,
cn 2 bt cao dng xc nh php ton. Cc php ton ny s c bn di y.

TMOD Register
MSB LSB
GATE C/T M1 M0 GATE C/T M1 M0
Timer1 Timer0
Cc bt M1, M0:
L cc bt ch ca cc b Timer 0 v Timer 1. Chng chn ch ca cc b nh
thi: 0, 1, 2 v 3. Ch 0 l mt b nh thi 13, ch 1 l mt b nh thi 16 bt v
ch 2 l b nh thi 8 bt. Chng ta ch tp chung vo cc ch thng c s
dng rng ri nht l ch 1 v 2. Chng ta s sm khm ph ra cc c tnh c cc
ch ny sau khi khm phn cn li ca thanh ghi TMOD. Cc ch c thit lp
theo trng thi ca M1 v M0 nh sau:

M1 M0 Ch Ch hot ng
0 0 0 B nh thi 13 bt gm 8 bt l b nh thi/ b m 5 bt t trc
0 1 1 B nh thi 16 bt (khng c t trc)
1 0 2 B nh thi 8 bt t np li
1 1 3 Ch b nh thi chia tch
Bi ging Chng 3

C/ T (ng h/ b nh thi).
Bt ny trong thanh ghi TMOD c dng quyt nh xem b nh thi c dng
nh mt my to tr hay b m s kin. Nu bt C/T = 0 th n c dng nh mt
b nh thi to ch thi gian. Ngun ng h cho ch tr thi gian l tn s thch
anh ca 8051. phn ny ch bn v la chn ny, cng dng ca b nh thi nh b
m s kin th s c bn phn k tip.

V d : Hy cho bit ch no v b nh thi no i vi cc trng hp sau:
a) MOV TMOD, #01H b) MOV TMOD, #20H c) MOV TMOD, #12H
Li gii: Chng ta chuyn i gi tr t s Hex sang nh phn v i chiu vi tng bt trong
thanh ghi TMOD ta c:
a) TMOD = 0000 0001, ch 1 ca b nh thi Timer 0 c chn.
b) TMOD = 0010 0000, ch 1 ca b nh thi Timer 1 c chn.
c) TMOD = 0001 0010, ch 1 ca b nh thi Timer 0 v ch 1 ca Timer 1 c
chn.
Ngun xung ng h cho b nh thi:
Nh chng ta bit, mi b nh thi cn mt xung ng h gi nhp. Vy ngun
xung ng h cho cc b nh thi trn 8051 ly u? Nu C/T = 0 th tn s thch anh
i lin vi 8051 c lm ngun cho ng h ca b nh thi. iu c ngha l
ln ca tn s thch anh i km vi 8051 quyt nh tc nhp ca cc b nh thi
trn 8051. Tn s ca b nh thi lun bng 1/12 tn s ca thch anh gn vi 8051.
V d:
Hy tm tn s ng b v chu k ca b nh thi cho cc h da trn 8051 vi cc tn
s thch anh sau:
a) 12MHz
b) 16MHz
c) 11,0592MHz

Li gii:
a) MHz 1 MHz 12
12
1
= v s 1
MHz 1 / 1
1
T = =
b) Mz 111 , 1 MHz 16
12
1
= v s 75 , 0
MHz 333 , 1
1
T = =
c) kHz 6 , 921 MHz 0592 , 11
12
1
= v s 085 , 1
MHz 9216 , 0
1
T = =

Mc d cc h thng da trn 8051 khc vi tn s thch anh t 10 n 40MHz, song
ta ch tp chung vo tn s thch anh 11,0592MHz. L do ng sau mt s l nh vy l
phi lm vic vi tn sut baud i vi truyn thng ni tip ca 8051. Tn s XTAL =
11,0592MHz cho php h 8051 truyn thng vi IBM PC m khng c li.
Bt cng GATE.
Mt bt khc ca thanh ghi TMOD l bt cng GATE. trn thanh ghi TMOD ta
thy c hai b nh thi Timer0 v Timer1 u c bt GATE. Vy bt GATE dng
lm g? Mi b nh thi thc hin im khi ng v dng. Mt s b nh thi thc
B dao ng
thch anh
12
Tn s ng h ca b
nh thi
Bi ging Chng 3

hin iu ny bng phn mm, mt s khc bng phn cng v mt s khc va bng
phn cng va bng phn mm. Cc b nh thi trn 8051 c c hai. Vic khi ng v
dng b nh thi c khi ng bng phn mm bi cc bt khi ng b nh thi
TR l TR0 v TR1. iu ny c c nh cc lnh SETB TR1 v CLR TR1 i vi
b Timer1 v SETB TR0 v CLR TR0 i vi b Timer0. Lnh SETB khi ng b
nh thi v lnh CLR dng dng n. Cc lnh ny khi ng v dng cc b nh
thi khi bt GATE = 0 trong thanh ghi TMOD. Khi ng v ngng b nh thi bng
phn cng t ngun ngoi bng cch t bt GATE = 1 trong thanh ghi TMOD. Tuy
nhin, trnh s ln ln ngay t by gi ta t GATE = 0 c ngha l khng cn khi
ng v dng cc b nh thi bng phn cng t bn ngoi. s dng phn mm
khi ng v dng cc b nh thi phn mm khi ng v dng cc b nh thi
khi GATE = 0. Chng ta ch cn cc lnh SETB TRx v CLR TRx.

V d:
Tm gi tr cho TMOD nu ta mun lp trnh b Timer0 ch 2 s dng thch anh
XTAL 8051 lm ngun ng h v s dng cc lnh khi ng v dng b nh thi.
Li gii:
TMOD = 0000 0010: B nh thi Timer0, ch 2 C/T = 0 dng ngun XTAL GATE
= 0 dng phn mm trong khi ng v dng b nh thi.

Cc ch ca b m/nh thi
Nh vy, by gi chng ta c hiu bit c bn v vai tr ca thanh ghi TMOD,
chng ta s xt ch ca b nh thi v cch chng c lp trnh nh th no to
ra mt tr thi gian. Do ch 1 v ch 2 c s dng rng ri nn ta i xt chi
tit tng ch mt.

Bi ging Chng 3

Bi ging Chng 3

Ngt timer.
Cc ngt timer c a ch Vector ngt l 000BH (timer 0) v 001BH (timer 1). Ngt
timer xy ra khi cc thanh ghi timer (TLx ITHx) trn v set c bo trn (TFx) ln 1. Cc
c timer (TFx) khng b xa bng phn mm. Khi cho php cc ngt, TFx t ng b
xa bng phn cng khi CPU chuyn n ngt.

3.2.8 Truyn thng khng ng b (UART)
8051 c 1 cng UART lm vic chun TTL, mc nh sau khi khi ng tt cc
cng ca 8051 du lm vic ch d vo ra s, v th c th s dng UART cn phi
cu hnh cho cng ny lm vic thng qua cc thanh ghi iu khin v ghp ni tng
thch vi chun rs232.

Ghp ni RS232 vi 8051
Bi ging Chng 3

Cc thanh ghi iu khin trong ch d UART:
a) SBUF: Vng m truyn thng d liu ra/vo cng ni tip.

- Vic truyn d liu tng ng vi vic np cho SBUF mt gi tr
- D liu nhn t RxD cng c lu vo SBUF
b) SCON: Thanh ghi iu khin hot ng cng ni tip

Trong :
Bit M t
SM0
SM1
SM2
La chn mode lm vic
REN = 1: Cho php nhn
= 0: Ch truyn
TB8 (=1) Bit truyn thng th 8, c s dng khi truyn
thng ch 9 bit
RB8 (=1) Bit truyn thng th 8, h thng s t t n =1
nu pht hin khung truyn l 9bit
TI C ngt truyn. Khi mt byte trong SBUF c truyn
thnh cng th TI=1. Trc khi truyn byte khc bit
ny cn phi c xa bng phn mm
RI C ngt nhn, Khi nhn thnh cng 1 byte vo SBUF
th RI=1. Sau khi c SUBF, RI cn phaic xa
bng phn mm

La chn mode lm vic

SM0 SM1 Mode Description Baud Rate
Bi ging Chng 3

0 0 0
Thanh ghi dch
8 bit
1/12 tn s clock
0 1 1 8-bit UART Cu hnh qua timer1
1 0 2 9-bit UART
1/32 tn s clock (hoc
1/64)
1 1 3 9-bit UART Cu hnh qua timer 1

Mode 0
y l ch thanh ghi dch 8 bit, khng c bit start/stop, ch ny RxD l
chn truyn nhn, cn TxD pht xung ng b.

- Qua trnh truyn bt u khi ghi gi tr co SBUF, kt thc c bo qua TI

- Qu trnh nhn t ng bi h thng v kt thc khi RI=1
Bi ging Chng 3

Mode 1
Truyn thng bt ng b vi frame truyn 10 bit, gm 1 start, 8 bit d liu v 1
stop. TxD thc hin truyn, RxD nhn d liu, tc truyn ci t qua Timer 1

- Qu trnh truyn:

- Qu trnh nhn

Mode 2
Truyn thng bt ng b vi frame truyn 11 bit, gm 1 start, 8 bit d liu, 1 bit
lp trnh c(nu truyn l TB8, nhn l RB8) v 1 bit stop. TxD thc hin truyn,
Bi ging Chng 3

RxD nhn d liu, tc truyn ci t qua Timer 1. Bit th 9 thng c dng l bit
pht hin li party.
- Qu trnh truyn

- Qu trnh nhn:

Mode 3
Mode 3 tng t mode 2 v mi mt ngoi tr tc pause
Tc Baud
Trong mt s mode hot ng ca cng ni tip th tc baud ph thuc vo timer 1.
ci t cn qua cc bc sau:
- Cho php timer 1 hot ng v cho php ngt trn timer 1
- Cu hnh cho timer 1 lm vic ch t np li
- t gi tr cho thanh ghi TH1 ty thuc vo tc mong mun theo bng di
Tn s thch anh
Baud
Rate
11.0592 12 14.7456 16 20
Bit
SMOD
150 40 h 30 h 00 h 0
300 A0 h 98 h 80 h 75 h 52 h 0
600 D0 h CC h C0 h BB h A9 h 0
1200 E8 h E6 h E0 h DE h D5 h 0
2400 F4 h F3 h F0 h EF h EA h 0
4800 F3 h EF h EF h 1
4800 FA h F8 h F5 h 0
9600 FD h FC h 0
9600 F5 h 1
Bi ging Chng 3

19200 FD h FC h 1
38400 FE h 1
76800 FF h 1

3.2.9 Ngt vi iu khin 8051
8051 h tr 5 loi ngt, c th cho php hoc cm ngt vi tng loi thng qua
thanh ghi iu khin ngt IE, hoc c th cm tt c cc ngt thng qua bit EA.
Cc tn hiu iu khin ngt c th c m t nh hnh di

hnh trn ch c 1 im ch l hai tn hiu IT0 v IT1, hai bit ny la chn
nguyn nhn ngt cho 2 ngt ngoi INTR0 v INTR1. Nu =1 th ngt ti sn m, =0
ngt ti sn dng
Thanh ghi iu khin ngt IE

Trong :
Bit M t
EA Cho php/cm ngt ton cc
= 0: Cm tt c cc ngt
= 1: Cho php cc ngt
ES = 0: Cm ngt truyn thng ni tip
Bi ging Chng 3

= 1: Cho php ngt truyn thng ni
tip
ET1 = 0: Cm ngt Timer 1
= 1: Cho php ngt Timer 1
EX1 = 0: Cm ngt ngoi vi INT0
= 1: Cho php ngt ngoi v INT0
ET0 = 0: Cm ngt Timer 0
= 1: Cho php ngt timer 0

EX0 = 0: Cm ngt ngoi vi INT1
= 1: Cho php

Th t u tin ngt
Khi c hai hay nhiu ngt cng lc xy ra, hoc mt ngt ang thc hin th m
ngt khc yu cu th ngt no c u tin hn s c u tin x l.
C 3 cp u tin ngt trong 8051
- Ngt reset l ngt c mc u tin cao nht, khi reset xy ra tt c cc ngt khc v
chng trnh u b dng v vi iu khin tr v ch khi dng ban u.
- Ngt mc 1, ch c reset mi c th cm ngt ny
- Ngt mc 0, cc ngt mc 1 v reset c th cm ngt ny.
Vic t chn mc u tin ngt l 1 hoc 0 thng qua thanh ghi IP. Vic x l u tin
ngt ca 8051 nh sau:
- Nu 1 c u tin cao hn mt ngt ang c x l xut hin th, ngt c u
tin thp ngay lp tc b dng ngt kia c thc hin
- Nu 2 ngt cng yu cu vo 1 hi im th ngt c mc u tin hn s c x
l trc
- Nu 2 ngt c cng mc u tin cng yu cu vo 1 thi im th th t c
chn nh sau:
o INTR 0
o Timer 0
o INTR 1
o Timer 1
o UART
Thanh ghi IP
Bi ging Chng 3

Trong : Cc bit t 0 n 5 t mc ngt l 0 hoc 1 cho cc ngt tng ng nh sau:
- PS: UART
- PT1: Timer 1
- PX1: INTR 1
- PT0: Timer 0
- PX0: INTR 0
Lp trnh ngt
Khi c mt ngt, chng trnh chnh s b dng, con tr chng trnh ngay lp
tc c chuyn n mt a ch quy nh sn trong bn vector ngt nh hnh di:

3.3 Tp lnh 8051 v lp trnh hp ng cho 8051
Lp trnh cho vi iu khin cng tng t nh lp trnh cho my tnh, bn cht l
ta gia lnh cho vi iu khin thc hin 1 danh sch cc lnh c bn c sp xp theo
mt trnh t no c th hon thnh mt nhim v ra. V tt c nhng lnh m vi
iu khin c th hiu c g l tp lnh. Cc vi iu khin tng thch vi 8051 c
255 lnh.
3.3.1 Tp lnh
Cc ch a ch
a) a ch trc tip
Ton hng l tn hoc a ch ca cc thanh ghi trong vng RAM thp (0-127) v
vng cha cc thanh ghi chc nng c bit SFR.

Bi ging Chng 3

b) a ch gin tip
Ton hng c th nm trong c vng RAM thp v cao, hoc RAM ngoi, khng
dng cho vng SFR. a ch ca ton hng cha trong thanh ghi con tr (R0 hoc R1 vi
RAM trong, DPTR i vi RAM ngoi). c im nhn ra ch ny l lun c k t
@ ng trc ton hng.
c) Ch a ch thanh ghi
Dng cho cc ton hng l 1 trong cc thanh ghi Ri ca cc bank c chn.
d) Ch a ch tc thi
ch ny gi tr ca ton hng c a ngay trong cu lnh. Trc cc hng
s th hin gi tr c k t #.
e) Ch a ch ch s
Ch dng c cu lnh movc, lnh c b nh chng trnh, thn dng cho vic
tra bng. ng trc ton hng l k t @, sau l mt ton hng to bi 1 thanh ghi
16bit (PC hoc DPTR) vi thanh ghi Acc. Thanh ghi 16 bit cha a ch u mng, cn
thanh ghi A cha lch ca nh cn c so vi u bng. Gi tr c ra s c ghi
vo thanh ghi A (xem m t tp lnh bit chi tit hn).
Phn loi tp lnh
Ty thuc vo cch v chc nng ca mi lnh, c th chia ra thnh 5 nhm lnh
nh sau:
- Cc lnh ton hc
- Cc lnh iu khin chng trnh
- Cc lnh vn chuyn d liu
- Cc lnh logic
- Cc lnh thao tc bit
Cu trc chung ca mi lnh:
M_lnh Ton_hng1 Ton_hng2 Ton_hng1

Trong :
- M_lnh: Tn gi nh cho chc nng ca lnh. (VD nh add cho addition)
- Ton_hng1, Ton_hng2, Ton_hng3: L cc ton hnh ca lnh, ty thuc vo
mi lnh s ton hng c th khng c, c 1, 2 hoc 3.
VD:
- RET (Kt thc chng trnh con) Lnh ny khng c ton hng
Bi ging Chng 3

- JZ TEMP (Chuyn con tr chng trnh n v tr TEMP) Ch c 1 ton hng
- ADD A, R3 (A = A + R3) C 2 ton hng
- CJNE A, #20, LOOP (So snh A vi 20, nu khng bng th chuyn con tr
chng trnh n nh LOOP) C 3 ton hng
Cc k hiu s dng m t lnh
K hiu M t
A: Thanh ghi cha (Accumulator).
B: Thanh ghi B.
Ri: Thanh ghi R0 hoc R1 ca bt k bng thanh ghi no
trong 4 bng thanh ghi trong RAM.
Rn: Rn: bt k thanh ghi no ca bt k bng thanh ghi no
trong 4 bng thanh ghi trong RAM.
Dptr: thanh ghi con tr d liu (c rng 16bit c kt hp
t 2 thanh ghi 8 bit l DPH v DPL).
Direct: Direct: l mt bin 8 bit(hay chnh l nh) bt k trong
RAM (tr 32 thanh ghi Rn u RAM).
#data: mt hng s 8 bit bt k.
#data16: mt hng s 16 bit bt k
<rel>: a ch bt k nm trong khong [PC-128 ; PC+127]
<addr11>: a ch bt k nm trong khong 0 2Kbyte tnh t a ch
ca lnh tip theo.
<addr16>:

a ch bt k trong khng gian 64K (p dng cho c
khng gian nh chng trnh v khng gian nh d liu).
<bit>: bit bt k c th nh a ch c (khng dng cho cc
bit khng nh c a ch).

Cc lnh ton hc
Cc k hiu dng trong vic m t tp lnh
Thc hin cc php tnh c bn nh +, -, *, /, Kt qu sau khi thc hin lnh
c lu vo ton hng u tin trong lnh
Bi ging Chng 3

C php
STT
M lnh Ton hng
M t
S
byte
S
chu
k
1 ADD A, Rn A = A + Rn 1 1
ADD A,direct A = A + direct 2 1
ADD A,@Ri A = A + @Ri 1 1
ADD A,#data A = A + #data 2 1
ADDC A,Rn A = A + Rn + C 1 1
6 ADDC A,direct A = A + direct + C 2 1
7 ADDC A,@Ri A = A + @Ri + C 1 1
8 ADDC A,#data A = A + #data + C 2 1
9 SUBB A,Rn A = A Rn C 1 1
10 SUBB A,direct A = A direct C 2 1
11 SUBB A,@Ri A = A @Ri C 1 1
12 SUBB A,#data A = A #data C 2 1
13 INC A A = A + 1 1 1
14 INC Rn Rn = Rn + 1 1 1
15 INC Direct direct = direct + 1 2 1
16 INC @Ri @Ri = @Ri + 1 1 1
17 DEC A A = A 1 1 1
18 DEC Rn Rn = Rn 1 1 1
19 DEC Direct direct = direct 1 2 1
20 DEC @Ri @Ri = @Ri 1 1 1
21 INC Dptr dptr = dptr + 1 1 2
22 MUL AB B:A = A*B 1 4
23 DIV AB A/B = A(thng) + B (d) 1 4
24 DA A Hiu chnh thp phn s liu
trong thanh ghi A
1 1

Bi ging Chng 3

Cc lnh logic
Thc hin cc php ton logic

STT C php M t
S
byte
S
chu
k
M lnh Ton hng
1 ANL A,Rn A = (A)and(Rn) 1 1
2 A,direct A = (A)and(direct) 2 1
3 A,@Ri A = (A)and(@Ri ) 1 1
4 A,#data A = (A)and(#data) 2 1
5 direct,A direct = (direct)and(A) 2 1
6 Direct,#data direct = (direct)and(#data) 3 2
7 ORL A,Rn A = (A)or(Rn) 1 1
8 A,direct A = (A)or(direct) 2 1
9 A,@Ri A = (A)or(@Ri ) 1 1
10 A,#data A = (A)or(#data) 2 1
11 direct,A direct = (direct)or(A) 2 1
12 Direct,#data direct = (direct)or(#data) 3 2
13 XRL A,Rn A = (A)xor(Rn) 1 1
14 A,direct A = (A)xor(direct) 2 1
15 A,@Ri A = (A)xor(@Ri ) 1 1
16 A,#data A = (A)xor(#data) 2 1
17 direct,A direct = (direct)xor(A) 2 1
18 Direct,#data direct = (direct)xor(#data) 3 2
19 CLR A A = 0 1 1
20 CPL A A = not(A) 1 1
21 RL A Quay tri A 1 1
22 RLC A Quay tri A qua c C 1 1
23 RR A Quay phi A 1 1
24 RRC A Quay phi A qua c C 1 1
25 SWAP A Hon i 2 na ca A 1 1

Cc lnh vn chuyn d liu
Di chuyn d liu t nh ny n nh khc, hoc gia hai thanh ghi, thanh
ghi o nh.

C php
STT
M lnh Ton hng
M t
S
byte
S
chu
k
1 MOV A,Rn 1 1
2 MOV A,direct 2 1
3 MOV A,@Ri
Copy gi tr ca ton hng bn
phi cho vo ton hng bn tri
(cc ton hng u l 8bit)
1 1
Bi ging Chng 3

4 MOV A,#data 2 1
5 MOV Rn,A 1 1
6 MOV Rn,direct 2 2
7 MOV Rn,#data 2 1
8 MOV Direct,A 2 1
9 MOV Direct,Rn 2 2
10 MOV Direct,direct 3 2
11 MOV Direct,@Ri 2 2
12 MOV Direct,#data 3 2
13 MOV @Ri,A 1 1
14 MOV @Ri,direct 2 1
15 MOV @Ri,#data 2 1
16 MOV Dptr,#data16 a gi tr 16bit vo thanh
ghi DPTR
3 2
17 MOVC A,@A+dptr c gi tr b nh chng
trnh ti a ch =
A + DPTR, ct kt qu
vo A
1 2
18 MOVC A,@A+PC c gi tr b nh chng
trnh ti a ch =
A + PC, ct kt qu vo A
1 2
19 MOVX A,@Ri c vo A gi tr ca b nh
ngoi ti a ch = Ri
1 2
20 MOVX A,@dptr c vo A gi tr ca b nh
ngoi ti a ch = DPTR
1 2
21 MOVX @dptr,A Ghi gi tr ca A vo b nh
ngoi ti a ch = DPTR
1 2
22 MOVX @dptr,A Ghi gi tr ca A vo b nh
ngoi ti a ch =
DPTR
2 2
23 PUSH Direct Ct ni dung ca bin trong
RAM vo nh ngn
xp
2 2
24 POP Direct Ly byte nh ngn xp
cho vo bin trong RAM
2 2
25 XCH A,Rn 1 1
26 XCH A,direct 2 1
27 XCH A,@Ri
Hon i gi tr ca A v gi tr
cn li
1 1
28 XCHD A,@Ri Hon i 4 bit thp giaA
v mt nh trong Ram ti
a ch = Ri
1 1

Cc lnh thao tc bit
Ton hng l bit
Bi ging Chng 3

STT C php M t
S
byte
S
chu
k
M lnh Ton hng
1 CLR C Xa c C v 0 1 1
2 CLR Bit Xa bit v 0 2 1
3 SETB C t c C = 1 1 12
4 SETB Bit t bit = 1 2 1
5 CPL C o gi tr ca c C 1 1
6 CPL Bit o gi tr ca bit 2 1
7 ANL C,bit C = (C)and(bit) 2 2
8 ANL C,/bit C = (C)and(o ca bit) 2 2
9 ORL C,bit C = (C)or(bit) 2 2
10 ORL C,/bit C = (C)or(o ca bit) 2 2
11 MOV C,bit C = bit 2 1
12 MOV Bit,C Bit = C 2 2
13 JC <rel> nhy n nhn <rel> nu C =
1
2 2
14 JNC Bit, <rel> nhy n nhn <rel> nu bit=
1
3 2
15 JB Bit, <rel> nhy n nhn <rel> nu bit=
1
3 2
16 JNB Bit, <rel> nhy n nhn <rel> nu bit=
0
3 2
17 JBC Bit, <rel> nhy n nhn <rel> nu bit =
1 v sau xa lun bit v 0
3 2

Cc lnh iu khin chng trnh (r nhnh)
Nhm lnh iu khin chng trnh c th chia thnh 2 loi:
- Nhy v iu kin: Chuyn con tr chng trnh n v tr khc t v tr hin thi
- Nhy c iu kin: Ch chuyn con tr chng trnh n v tr khc t v tr hin
thi nu th mn iu kin

STT C php
M lnh Ton hng
M t
S
byte
S
chu
k
1 ACALL <addr11> gi chng trnh con (nm
trong phm vi 2k mem)
3 2
2 LCALL <addr16> gi chng trnh con (trong
pham vi 64k mem)
3 2
3 RET tr v t chng trnh con 1 2
4 RETI tr v t chng trnh
phc v ngt
1 2
Bi ging Chng 3

5 AJMP <addr11> nhy n nhn (trong phm vi
2k mem)
2 2
6 LJMP <addr16> nhy n nhn (trong phm vi
64 mem)
3 2
7 SJMP <rel> nhy n nhn 2 2
8 JMP @A+DPTR nhy n a ch =
A+DPTR
1 2
9 JZ <rel> nhy n nhn nu A = 0 2 2
10 JNZ <rel> nhy n nhn nu A #0 2 2
11 CJNE A,direct,<rel> So snh v nhy n
nhn nu A # direct
3 2
12 CJNE A,#data,<rel> So snh v nhy n nhn
nu A#data
3 2
13 Rn,#data,<rel> So snh v nhy n
nhn nu Rn#data
3 2
14 @Ri,#data,<rel> So snh v nhy n nhn
nu byte c a ch
= Ri c ni dung khc vi
data
3 2
15 DJNZ Rn,<rel> Gim Rn i 1 v nhy
n nhn nu cha gim v 0
2 2
16 DJNZ direct,<rel> Gim direct i 1 v nhy
n nhn nu cha gim v 0
3 2
17 NOP Khng lm g c 1 1

3.3.2 Lp trnh Assembly
Cc thnh phn c bn ca ngn ng Assembly:
- Lables: Nhn nh du cho mt on lnh
- Orders: Lnh
- Directives: nh hng chng trnh dch
- Comments: Cc li ch thch
VD:
Bi ging Chng 3

Cc quy tc ca Assembly
c th dch thnh file m my dng HEX-Code trc khi download vo Chip
th mt chng trnh assembly phi tun th cc nguyn tc sau:
- Mi dng lnh khng vt qu 255 k t
- Mi dng lnh phi bt u bng 1 k t, nhn, lnh hoc ch th nh hng
chng trnh dch
- M th sau du ; c xem l li gii thch v chng trnh dch s b qua.
- Cc thnh phn ca mi dng lnh cch bit nhau it nht bng mt du cch.
Hng s trong Assembly
a) C s 10
Bi ging Chng 3

S dng 10 k t (0,1,2,..,9) m ha cc s. Trong hu ht cc vi iu khin c
s dng 2 byte lu cc s c s 10, nh vy s ln nht c th l 65535. tng
minh cho 1 s s mi th sau cc k t s km theo k t D.
VD: 1234D
b) S Hexa
S dng 16 k t (0,1,2,..,9,A,B,C,D,E,F) m ha cc s, tng t c s 10 hu
ht cc vi iu khin s dng 2 byte lu cc s hexa, v th s ln nht c th l
FFFF (65535). Mi s hexa kt thc bi k t h.
VD: 23h
c) S nh phn
S dng 2 l t 0 v 1 m ha. Cc s nh phn kt thc bng k t B
VD: 1101010101B
3.3.3.3. Cc ton t
K hiu Thc hin V d Kt qu
+ Cng 10+5 15
- Tr 25-17 8
* Nhn 7*4 28
/ Chia nguyn 7/4 1
MOD Chia ly d 7 MOD 4 3
SHR Dch phi 1000B SHR 2 0010B
SHL Dch tri 1010B SHL 2 101000B
NOT o NOT 1 1111111111111110B
AND And bit 1101B AND 0101B 0101B
OR Or bit 1101B OR 0101B 1101B
XOR Xor 1101B XOR 0101B 1000B
LOW Ly byte thp LOW(0AADDH) 0DDH
HIGH Ly byte cao HIGH(0AADDH) 0AAH
EQ, = So snh bng 7 EQ 4 or 7=4 0 (false)
NE,<> SS Khng bng 7 NE 4 or 7<>4 0FFFFH (true)
GT, > SS ln hn 7 GT 4 or 7>4 0FFFFH (true)
GE, >=
SS nh hn hoc
bng
7 GE 4 or 7>=4 0FFFFH (true)
LT, < SS nh hn 7 LT 4 or 7<4 0 (false)
Bi ging Chng 3

LE,<=
SS nh hn hoc
bng
7 LE 4 or 7<=4 0 (false)

Cch t tn
Thay v phi nh tn tng thanh ghi, hay tng bit, ta c th gn cho n mt ci
nh gi nh tng ngs vi chc nng ca n, assembly h tr vic t tn theo quy tc
sau:
- Tn c t hp t cc k t (A-Z, a-z), cc s (0-9), cc k t c bit (? V
_) v khng ph bit ch ci v ch thng.
- di tn ti a l 255 k t, nhng ch 32 k t u c dng phn bit
- Tn phi bt u bng k t.
- Khng c trng vi cc t kha sau:
A AB ACALL ADD
ADDC AJMP AND ANL
AR0 AR1 AR2 AR3
AR4 AR5 AR6 AR7
BIT BSEG C CALL
CJNE CLR CODE CPL
CSEG DA DATA DB
DBIT DEC DIV DJNZ
DPTR DS DSEG DW
END EQ EQU GE
GT HIGH IDATA INC
ISEG JB JBC JC
JMP JNB JNC JNZ
JZ LCALL LE LJMP
LOW LT MOD MOV
MOVC MOVX MUL NE
NOP NOT OR ORG
ORL PC POP PUSH
R0 R1 R2 R3
Bi ging Chng 3

R4 R5 R6 R7
RET RETI RL RLC
RR RRC SET SETB
SHL SHR SJMP SUBB
SWAP USING XCH XCHD
XDATA XOR XRL XSEG

nh hng chng trnh dch
Khng ging nh cc lnh s c dch thnh m my v ghi vo b nh ca vi
iu khin, cc ch th nh hng chng trnh dch l cc lnh ca chnh Assembly, c
tc dng cho trnh bin dch m khng c tc dng cho vi iu khin
Mt s ch th nh hng chng trnh dch:
- EQU: thay symbol bng hng s.
VD bien_x EQU 96
- BIT: Thay th mt a ch bit bng mt symbol.
VD motor BIT P0.0
- CODE: nh du vng m lnh
- DATA: nh du vng d liu khai bo
- XDATA: Gn mt tn cho mt vng nh b nh ngoi
o VD: Bien xdata 1000
- IDATA: Gn mt tn cho mt vng nh b nh trong
o VD: Bien idata 1000
- ORG: Ch ra a ch ca vng nh trong b nh chng trnh lu cc on
chng trnh sau ch th ny
o VD: ORG 100h
- USING: Ch ra bank thanh ghi no c dng
o VD: USING 2
- END: nh dau kt thc mt chng trnh
- DBIT: t nhn cho mt bit trong vng a ch bit trong RAM (dng khai bo
1 bit kiu bit)
Bi ging Chng 3

- DB: t nhn cho mt vng byte trong RAM (dng khai bo 1 bin kiu byte)
- DW: t nhn cho mt vng 2byte trong RAM (dng khai bo bin kiu
nguyn)
Cu trc mt chng trnh ASSEMBLY
Mt dng lnh trong chng trnh hp ng gm c cc trng sau:
Tn Lnh Ton hng Ch thch
A: Mov AH, 10h ; a gi tr 10h vo thanh ghi AH

Cu trc thng thng ca mt chng trnh hp ng

.model <Khai bo kiu chng trnh>
.stack <Khai bo kch thc ngn xp>
.data
<Khai bo d liu>
.code
<Cc lnh>
end

Khung chng trnh dch ra .exe
data segment
; Thm d liu y
pkey db "press any key to exit ...$"
ends
stack segment
dw 128 dup(0)
ends
CODE segment
start:
;Thit lp gi tr cho thanh ghi on
MOV ax, data
MOV ds, ax
MOV es, ax

; Thm m ngun vo y

lea dx, pkey
MOV ah, 9
int 21h ;Xut chui ti ds:dx

; Ch bm 1 phm bt k...
MOV ah, 1
int 21h

MOV ax, 4c00h ; Thot v H iu hnh.
int 21h
ends
END start ; Dng chng trnh ASM.
Bi ging Chng 3

Khung chng trnh dch ra .com
; C th chn kiu cu hnh nh th ny hoc chn kiu khc theo
; m t trong file: c:\emu8086\inc\0_com_template.txt
CSEG SEGMENT ; M segment bt u ti y.

org 100h

; M ngun y

ret

V d: Chng trnh sau in ra mn hnh dng ch Hello !
.model small
.stack 100h
.data
s DB Hello !$; khai bo xu k t cn in
.code
mov AX,@data ; ly a ch data segment ghi vo DS
mov DS,AX ; V model small, y cng l a ch
; segment ca xu s
; xut chui
mov DX, OFFSET s ; ly a ch offset ghi vo DX
mov AH , 9
int 21h ; gi hm 9, ngt 21h in

mov AH, 4Ch ; Thot khi chng trnh
int 21h
end
Lu :
- Mi chng trnh u phi c on CODE thot khi chng trnh, nu khng
chng trnh s khng dng khi ht chng trnh ca mnh.

3.3.3 Cu hi v bi tp
Cu 1. Nu cc bc cu hnh cho timer 0 mode 1 s dng ngt
Cu 2. Nu cc bc cu hnh cho timer 1 mode 1 s dng ngt
Cu 3. Nu cc bc cu hnh cho counter 0 mode 1 s dng ngt
Cu 4. Nu cc bc cu hnh cho counter 1 mode 2 s dng ngt
Cu 5. Nu cc bc khi to truyn thng ni tip
Cu 6. Nu cc bc khi to ngt ngoi 0 theo mc thp
Cu 7. Nu cc bc khi to ngt ngoi 0 theo sn xung
Cu 8. Nu cc bc khi to ngt ngoi 1 theo mc thp
Cu 9. Nu cc bc khi to ngt ngoi 1 theo sn xung
Cu 10. Tnh gi tr TH, TL cho Timer 0, trn sau mi 60s, bit tn s thch anh l
16Mhz
12Mhz
Cu 12. Tnh gi tr TH, TL cho Timer 1, trn sau mi 60ms, bit tn s thch anh l
20Mhz
Bi ging Chng 3

11.0592Mhz
Cu 14. Cho tn s thch anh Fxtal= 8MHz, baud=9600bps, tnh gi tr TH1
Cu 15. Cho tn s thch anh Fxtal=10MHz, baud=9600bps, tnh gi tr TH1
Cu 16. Cho tn s thch anh Fxtal= 8MHz, baud=19200bps, tnh gi tr TH1
Cu 17. Cho tn s thch anh Fxtal=10MHz, baud=19200bps, tnh gi tr TH1
Cu 18. Cho tn s thch anh Fxtal= 8MHz, baud=19200bps (cu hnh nhn i tc
baud), tnh gi tr TH1
Cu 19. Cho tn s thch anh Fxtal=10MHz, baud=19200bps(cu hnh nhn i tc
baud), tnh gi tr TH1
Cu 20. Vit chng trnh mi khi bm v gi phm th n LED nhp nhy. Bit phm
bm tch cc mc 0, ghp vo chn P0.0, LED mc cc dng vo P2.0, cc m qua tr
280 xung GND
Cu 21. Vit chng trnh mi khi bm v gi phm th n LED nhp nhy. Bit phm
bm tch cc mc 0, ghp vo chn P0.1, LED mc cc dng vo P2.1, cc m qua tr
280 xung GND
Cu 22. Vit chng trnh lin tc nhp nhy n LED, nu bm v gi phm th ngng
nhp nhy LED. Bit phm bm tch cc mc 0, ghp vo chn P0.0, LED mc cc
dng vo P2.3, cc m qua tr 280 xung GND
Cu 23. Vit chng trnh lin tc nhp nhy n LED, nu bm v gi phm th ngng
nhp nhy LED. Bit phm bm tch cc mc 0, ghp vo chn P1.0, LED mc cc
dng vo P2.5, cc m qua tr 280 xung GND
Cu 24. Vit chng trnh con ngt v khi to ngt Timer 0, mode 1, vi tn s trn l
200KHz, bit tn s thch anh F
xtal
=8MHz
xtal
=11.0592MHz
Cu 26. Vit chng trnh con ngt v khi to ngt Timer 0, mode 2, vi chu k trn l
T=255s, bit tn s thch anh F
xtal
=8MHz
xtal
=11.0592MHz
xtal
=8MHz
xtal
=11.0592MHz
xtal
=8MHz
xtal
=11.0592MHz
Cu 32. Vit on lnh khi to truyn thng ni tip bit tn s thch anh l 8MHz, tc
baud=9600bps.
baud=9600bps.
baud=19200bps.
baud=19200bps.
Cu 36. Thit k v vit chng trnh con c ma trn 2x2 nt bm (nt bm c nh
s t 1 n n), kt qu tr v l s th t nt bm, nu khng c nt no c bm, tr
v 0. Bit nt bm c ghp hng vo P1, ct vo P2.
Bi ging Chng 3

Cu 37. Thit k v lp trnh hin th s 1234 4 LED 7 thanh. Bit 4 LED l chung m,
mc chung BUS d liu (a..h).
Cu 38. Thit k v lp trnh hin th s 1234 4 LED 7 thanh. Bit 4 LED l chung
dng, mc chung BUS d liu (a..h).
Cu 39. Vit chng trnh truyn lin tc tn mnh ln my tnh qua ng RS232, vi
tc baud = 4800bps
Cu 40. Vit chng trnh truyn lin tc tn mnh ln my tnh qua ng RS232, vi
tc baud = 9600bps
Cu 41. Hy lp trnh cho 8051 nhn cc byte d liu ni tip v t chng vo cng
P1. t tc baud l 4800bps, 8 bt d liu v 1 bt Stop.
Cu 42. Hy lp trnh cho 8051 nhn cc byte d liu ni tip v t chng vo cng
P2. t tc baud l 9600bps, 8 bt d liu v 1 bt Stop.
Cu 43. Vit chng trnh truyn thng vi my tnh, nu my tnh gi k t a th 8051
gi tr v k t b, nu my tnh gi k t b th 8051 gi tr v k t c,
Cu 44. Vit chng trnh truyn thng vi my tnh nu my tnh gi xung ch Ten
th 8051 gi tr v tn mnh (th sinh).
Cu 45. Hy vit chng trnh nhn lin tc d liu 8 bt cng P0 v gi n n cng
P1 trong khi n cng lc to ra mt sng vung chu k 200s trn chn P2.1. Hy s
dng b Timer0 to ra sng vung, tn s ca 8051 l F
XTAL
=11.0592MHz.
Cu 46. Hy vit chng trnh nhn lin tc d liu 8 bt cng P0 v gi n n cng
P1 trong khi n cng lc to ra mt sng vung vi mc cao ko di 1085s v mc
thp di 15s vi gi thit tn s F
XTAL
= 11.0592MHz. Hy s dng b nh thi
Timer1.
Cu 47. S dng ngt ngoi lp trnh gii quyt bi ton sau: Gi s chn INT1 c ni
n cng tc bnh thng mc cao. Mi khi n xung thp phi bt mt n LED. n
LED c ni n chn P1.3 v bnh thng ch tt. Khi n c bt ln n phi
sng vi phn trm giy. Chng no cng tc c n xung thp n LED phi sng
lin tc.
Cu 48. Gi thit chn P3.3 (INT1) c ni vi mt my to xung, hy vit mt chng
trnh trong sn xung ca xung s gi mt tn hiu cao n chn P1.3 ang c ni
ti n LED (hoc mt ci bo). Hay ni cch khc, n LED c bt v tt cng tn
s vi cc xung c cp ti chn INT1
Cu 49. Hy vit chng trnh trong 8051 c d liu t cng P1 v ghi n ti cng
P2 lin tc trong khi a mt bn sao d liu ti cng COM ni tip thc hin truyn
ni tip gi thit tn s XTAL l 11.0592MHz v tc baud l 9600bps.
Cu 50. Hy vit chng trnh trong 8051 nhn d liu t cng P1 v gi lin tc n
cng P2 trong khi d liu i vo t cng ni tip COM c gi n cng P0. Bit
tn s F
XTAL
=11.0592MHz v tc baud 9600bps.
Cu 51. Hy vit mt chng trnh thc hin cc cng vic sau:
a. Nhn d liu ni tip v gi n n cng P0.
b. c d liu t cng P1, truyn ni tip v sao chp n cng P2.
c. S dng Timer0 to sng vung tn s 5kHz trn chn P0.1
gi thit tn s XTAL = 11.0592MHz v tc baud 4800.

Bi ging Chng 4
Vi x l - Vi iu khin Cc h vi iu khin tin tin v ng dng

CHNG 4.
CC H VI IU KHIN TIN TIN V NG DNG

Mc tiu

Gip sinh vin bit v cc h vi iu khin hin i v ph bin trong thc t sn
xut; v ng dng c bn ca chng.

Tm tt:

Tm hiu v cc vi iu khin hin i h AVR, h PIC v ARM
ng dng cc vi iu khin lp trnh giao tip vi th gii thc thng qua cc
v d:
- Ghp ni vi iu khin vi hin th 7 thanh
- Ghp ni vi iu khin vi mn hnh LCD
- Ghp ni vi iu khin vi bn phm
- Ghp ni vi iu khin vi cc b chuyn i ADC v DAC
- Ghp ni vi iu khin vi step motor
Bi ging Chng 4

4.1 Cc h vi iu khin tin tin
4.1.1 Atmel AVR

Atmel AVR ATmega8 PDIP
AVR l mt kin trc Harvard sa i 8-bit RISC n chip vi iu khin (C) c
pht trin bi Atmel vo nm 1996. Cc AVR l mt trong nhng h vi iu khin u
tin s dng on-chip b nh flash lu tr chng trnh, tri vi One-Time
Programmable ROM, EPROM hoc EEPROM c s dng bi vi iu khin khc vo
lc .
4.1.1.1 Lch s h AVR
Ngi ta tin vo kin trc AVR c bn c hnh thnh bi hai sinh vin ti Vin
Cng ngh Na Uy (th n) Alf-Egil Bogen v Vegard Wollan.
Cc AVR MCU bn gc c pht trin ti mt ngi nh ASIC thuc a phng
Trondheim, Na Uy, ni m hai thnh vin sng lp ca Atmel Na Uy lm vic nh
sinh vin. N c bit n nh mt RISC (Micro RISC). Khi cng ngh c bn
cho Atmel, kin trc ni b c pht trin thm bi Alf v Vegard ti Atmel Na Uy,
mt cng ty con ca Atmel thnh lp bi hai kin trc s.
Atmel AVR ni rng cc tn khng phi l mt t vit tt v khng phi l bt c iu g
c bit. Nhng ngi sng to AVR khng c cu tr li dt khot v thut ng vit tt
"AVR".

Lu rng vic s dng "AVR" trong bi vit ny thng cp n 8-bit RISC dng
vi iu khin Atmel AVR.
Trong s nhng thnh vin u tin ca dng AVR l AT90S8515, ng v trong gi
40-pin DIP c chn ra ging nh mt vi iu khin 8051, bao gm a ch BUS
multiplexed bn ngoi v d liu. Tn hiu RESET i ngc, 8051 RESET mc cao,
AVR RESET mc thp), nhng khc vi , chn ra l ging ht nhau.
4.1.1.2 Tng quan v thit b
AVR l mt kin trc my Modified Harvard vi chng trnh v d liu c lu
tr trong cc h thng b nh vt l ring bit xut hin trong khng gian a ch
khc nhau, nhng c kh nng c ghi d liu t b nh bng cch s dng lnh c
bit.
C bn v h AVR
AVRs thng phn thnh bn nhm rng:
Bi ging Chng 4

TinyAVR - chui Attiny
o 0,5-8 kBb nh chng trnh
o ng v 6-32-chn
o Tp ngoi vi hu hn
MegaAVR - chui Atmega
o 4-256 kB b nh chng trnh
o ng v 28-100-chn
o Tp lnh m rng (Lnh nhn v lnh cho qun l b nh ln hn).
o M rng hn v thit b ngoi vi
XMEGA - chui Atxmega
o 16-384 kB b nh chng trnh.
o ng v 44-64-100-chn (A4, A3, A1)
o M rng cc tnh nng hiu sut, chng hn nh DMA, "S kin h
thng", v h tr mt m.
o Thit b ngoi vi c m rng vi DACs
ng dng c th AVR
o megaAVRs vi cc tnh nng c bit khng tm thy trn cc thnh vin
khc ca gia nh AVR, chng hn nh b iu khin LCD, USB, iu
khin, nng cao PWM, CAN v.v..
o Atmel At94k FPSLIC (Field Programmable System Level Circuit), mt li
trn AVR vi mt FPGA. FPSLIC s dng SRAM cho m chng trnh
AVR, khng ging nh tt c cc AVRs khc. Mt phn do s khc bit
tc tng i gia SRAM v flash, li AVR trong FPSLIC c th chy
ln n 50 MHz.
4.1.1.3 Kin trc thit b
Flash, EEPROM, v SRAM tt c c tch hp vo mt chip duy nht, loi b s cn
thit ca b nh ngoi trong hu ht cc ng dng. Mt s thit b c BUS m rng song
song cho php thm d liu b sung (hoc m) b nh, hoc b nh nh x thit b.
Tt c cc thit b c giao tip ni tip, m c th c s dng kt ni EEPROMs
ni tip chip flash.
4.1.1.4 Program Memory (Flash)
M lnh chng trnh c lu tr trong b nh Flash chng xa (non-volatile
Flash). Mc d h l 8-bit MCUs, mi lnh mt 1 hoc 2 t 16-bit.
Kch c ca b nh chng trnh thng c ch nh trong vic t tn ca
thit b chnh (v d, dng ATmega64x c 64 kB ca Flash, tuy nhin ATmega32x ch
c 32kB).
4.1.1.5 EEPROM
Hu nh tt c cc vi iu khin AVR u c Electrically Erasable Programmable
Read Only Memory (EEPROM) lu na vnh vin d liu lu tr. Cng ging nh
b nh Flash, EEPROM c th duy tr ni dung ca n khi c g b.
Bi ging Chng 4

Trong hu ht cc bin th ca kin trc AVR, b nh EEPROM ni b ny
khng phi l nh x vo khng gian a ch b nh ca MCU. N ch c th c truy
cp cng mt cch nh l thit b ngoi vi bn ngoi, thanh ghi s dng con tr c bit
v c / ghi hng dn m lm cho truy cp EEPROM chm hn nhiu so vi RAM ni
b khc.
Tuy nhin, mt s thit b trong dng SecureAVR (AT90SC) s dng mt bn
EEPROM c bit n cc d liu hoc b nh chng trnh ty thuc vo cu hnh.
Dng XMEGA cng cho php EEPROM nh x vo khng gian a ch d liu.

K t khi s lng cc ln ghi EEPROM khng phi l khng gii hn - Atmel ch c
100.000 chu k ghi.

4.1.1.6 Chng trnh thc thi

Atmel's AVRs c hai giai on, thit k kiu ng ng (pipeline) duy nht. iu ny c
ngha l ch lnh k tip l c ly khi lnh ny ang thc hin. Hu ht cc lnh ch
mt mt hoc hai chu k ng h, lm cho AVRs tng i nhanh trong s vi iu khin
8-bit.

H AVR ca b vi x l c thit k vi s thc hin hiu qu ca m C.
4.1.1.7 Tp lnh

Tp lnh AVR hn l trc giao vi hu ht cc vi iu khin tm-bit, c bit l 8051 v
vi iu khin PIC vi AVR m ngy nay ang cnh tranh. Tuy nhin, n khng phi l
hon ton bnh thng:
Con tr ghi X, Y, v Z c kh nng nh a ch khc vi nhau.
V tr thanh ghi R0 n R15 c kh nng nh a ch khc hn v tr thnah ghi
R16 n R31.
I / O port 0-31 c kh nng nh a ch khc so vi I / O ports 32-63.
CLR nh hng n cc c, trong khi SER khng, ngay c khi chng c lnh
b sung. CLR xa tt c cc bit v khng v SER t chng ln mt.
Truy cp d liu ch c c lu trong b nh chng trnh (flash) yu cu lnh
c bit LPM.
Ngoi ra, mt s chip-s khc bit c th nh hng n cc th h m. M con tr (bao
gm c cc a ch tr li stack) l hai byte trn chip ln n 128 KBytes b nh flash,
nhng ba byte trn chip ln hn, khng phi tt c cc chip c s nhn phn cng; chip
vi hn 8 Kbytes flash c nhnh v gi lnh vi khong rng hn; v.v. .
Lp trnh cho n bng cch s dng lp trnh C (hoc thm ch Ada) trnh bin
dch kh n gin. GCC bao gm h tr AVR t kh lu, v h tr c s dng
rng ri. Trong thc t, Atmel g gm u vo t cc nh pht trin chnh ca trnh bin
Bi ging Chng 4

dch cho vi iu khin nh, tch hp tnh nng cho cc tp lnh hu dng nht trong
mt trnh bin dch cho cc ngn ng cp cao.
4.1.1.8 Tc MCU

Dng AVR bnh thng c th h tr tc ng h 0-20 MHz, vi mt s thit b
t 32 MHz. H tr hot ng thp hn thng i hi mt tc gim. Tt c gn y
(Tiny v Mega, nhng khng phi 90S) AVRs tch hp oscillator-chip, loi b s cn
thit ca ng h bn ngoi hoc mch dao ng. Mt s AVRs cng c mt prescaler
ng h h thng, c th chia xung ng h ca h thng ln n 1024. Prescaler ny
c th c cu hnh li bng phn mm trong thi gian chy, cho php ti u ha tc
ng h.
V tt c cc hot ng (tr literals) trn thanh ghi R0 - R31 l n chu k, cc AVR
c th t c ln n 1MIPS mi MHz. Ti v lu tr vo / ra b nh mt 2 chu k,
phn nhnh phi mt 3 chu k.
4.1.1.9 Nhng c tnh
AVRs hin cung cp mt lot cc tnh nng:
My a chc nng, Bi-directional General Purpose I / O port vi cu hnh, built-
in pull-up resistors
Nhiu ni Oscillators, bao gm c RC oscillator m khng c b phn bn ngoi
Ni, lnh Self-Programmable Flash Memory ln n 256 KB (384 KB trn
XMega)
o In-System Programmable s dng ni tip / song song h th c quyn
hoc cc giao din JTAG
o Ty chn khi ng vi bo v Lock Bits c lp.
On-chip g li (OCD) h tr thng qua JTAG hoc debugWIRE trn hu ht cc
thit b
o tn hiu JTAG (TMS, TDI, TDO, v TCK) l multiplexed ngy GPIOs.
Nhng Pin c th c cu hnh vi chc nng nh JTAG hoc GPIO ty
thuc vo thit lp ca mt vi cu ch (FUSES), c th c lp trnh
thng qua ISP hoc HVSP. Theo mc nh, AVRs vi JTAG i km vi
giao din JTAG bt.
o debugWIRE s dng chn /RESET nh mt knh giao tip hai hng
truy cp vo mch debug-chip. l hin nay trn cc thit b vi s
lng chn t, v n ch cn mt chn.
Internal Data EEPROM ln n 4 kB
Internal SRAM ln n 8 kB (32 kB trn XMega)
Ngoi 64KB d liu trn cc m hnh khng gian nht nh, bao gm c
Mega8515 v Mega162.
o Trong mt s thnh vin ca lot XMEGA, d liu khng gian bn ngoi
c tng cng h tr c hai SRAM v SDRAM. ng thi, cc
Bi ging Chng 4

d liu a ch, cc ch c m rng cho php ln n 16MB b
nh ca d liu c cp trc tip.
o AVR thng khng h tr thc thi m t b nh bn ngoi. Mt s ASSP
bng cch s dng m AVR lm b nh h tr chng trnh bn ngoi.
8-Bit v 16-Bit Timers
o PWM u ra (thi gian cht my pht in trn mt s thit b)
o vo capture
So snh Analog
o 10 hoc 12-Bit A / D Converters, vi multiplex ln n 16 knh
o 12-bit D / A Converters
Mt lot cc giao tip ni tip, bao gm c
o IC tng thch Two-Wire Interface (TWI)
o Thit b ngoi vi Synchronous / Asynchronous Serial (UART / USART)
(c s dng vi RS-232, RS-485, v nhiu hn na)
o Thit b giao din Serial Bus (SPI)
o Universal Serial Interface (USI) cho 2 hoc 3 dy truyn thng ng b
ni tip.
Brownout Detection
Watchdog Timer (WDT)
Nhiu ch tit kim in (Power-Saving Sleep)
iu khin nh sng v iu khin ng c (c th l PWM ) iu khin m hnh
H tr CAN Controller
H tr USB Controller
o USB Full speed (12 Mbit / s) iu khin phn cng & Hub vi AVR
nhng.
o Cng sn sng t do vi tc thp (1,5 Mbit / s) (HID) bitbanging
EMULATIONS phn mm
H tr Ethernet Controller
H tr LCD Controller
Hot ng mc in p thp, c th xung n 1.8v (n 0.7v vi loi h tr
chuyn i DC-DC)
Thit b picoPower
b iu khin DMA v truyn thng "S kin h thng" ngoi vi.
M ha v gii m nhanh, h tr cho AES v DES
Bi ging Chng 4

4.1.2 Vi iu khin PIC

PIC 1655A

Cc dng PIC khc
PIC l mt h vi iu khin RISC c sn xut bi cng ty Microchip Technology.
Dng PIC u tin l PIC1650 c pht trin bi Microelectronics Division thuc
General Instrument .
PIC bt ngun l ch vit tt ca "Programmable Intelligent Computer" (My tnh
kh trnh thng minh) l mt sn phm ca hng General Instruments t cho dng sn
phm u tin ca h l PIC1650. Lc ny, PIC1650 c dng giao tip vi cc
thit b ngoi vi cho my ch 16bit CP1600, v vy, ngi ta cng gi PIC vi ci tn
"Peripheral Interface Controller" (B iu khin giao tip ngoi vi). CP1600 l mt CPU
tt, nhng li km v cc hot ng xut nhp, v v vy PIC 8-bit c pht trin vo
khong nm 1975 h tr hot ng xut nhp cho CP1600. PIC s dng microcode
n gin t trong ROM, v mc d, cm t RISC cha c s dng thi by gi,
nhng PIC thc s l mt vi iu khin vi kin trc RISC, chy mt lnh mt chu k
my (4 chu k ca b dao ng).
Nm 1985 General Instruments bn b phn vi in t ca h, v ch s hu mi
hy b hu ht cc d n - lc qu li thi. Tuy nhin PIC c b sung
EEPROM to thnh 1 b iu khin vo ra kh trnh. Ngy nay rt nhiu dng PIC
c xut xng vi hng lot cc module ngoi vi tch hp sn (nh USART, PWM,
ADC...), vi b nh chng trnh t 512 Word n 32K Word.
Lp trnh cho PIC
PIC s dng tp lnh RISC, vi dng PIC low-end ( di m lnh 12 bit, v d:
PIC12Cxxx) v mid-range ( di m lnh 14 bit, v d: PIC16Fxxxx), tp lnh bao gm
khong 35 lnh, v 70 lnh i vi cc dng PIC high-end ( di m lnh 16 bit, v d:
PIC18Fxxxx). Tp lnh bao gm cc lnh tnh ton trn cc thanh ghi, vi cc hng s,
hoc cc v tr b nh, cng nh c cc lnh iu kin, lnh nhy/gi hm, v cc lnh
quay tr v, n cng c cc tnh nng phn cng khc nh ngt hoc sleep (ch
hot ng tit kin in). Microchip cung cp mi trng lp trnh MPLAB, n bao gm
phn mm m phng v trnh dch ASM.
Mt s cng ty khc xy dng cc trnh dch C, Basic, Pascal cho PIC. Microchip
cng bn trnh dch "C18" (cho dng PIC high-end) v "C30" (cho dng dsPIC30Fxxx).
H cng cung cp cc bn "student edition/demo" dnh cho sinh vin hoc ngi dng
th, nhng version ny khng c chc nng ti u ho code v c thi hn s dng gii
hn. Nhng trnh dch m ngun m cho C, Pascal, JAL, v Forth, cng c cung cp
bi PicForth.
GPUTILS l mt kho m ngun m cc cng c, c cung cp theo cng c v
bn quyn ca GNU General Public License. GPUTILS bao gm cc trnh dch, trnh
Bi ging Chng 4

lin kt, chy trn nn Linux, Mac OS X, OS/2 v Microsoft Windows. GPSIM cng l
mt trnh m phng dnh cho vi iu khin PIC thit k ng vi tng module phn
cng, cho php gi lp cc thit b c bit c kt ni vi PIC, v d nh LCD, LED...
Mt vi c tnh
Hin nay c kh nhiu dng PIC v c rt nhiu khc bit v phn cng, nhng
chng ta c th im qua mt vi nt nh sau:
8/16 bit CPU, xy dng theo kin trc Harvard c sa i
Flash v ROM c th tu chn t 256 byte n 256 Kbyte
Cc cng Xut/Nhp (I/O ports) (mc logic thng t 0V n 5.5V, ng vi logic 0 v
logic 1)
8/16 Bit Timer
Cng ngh Nanowatt
Cc chun Giao Tip Ngoi Vi Ni Tip ng b/Khng ng b USART, AUSART,
EUSARTs
B chuyn i ADC Analog-to-digital converters, 10/12 bit
B so snh in p (Voltage Comparators)
Cc module Capture/Compare/PWM
LCD
MSSP Peripheral dng cho cc giao tip IC, SPI, v IS
B nh ni EEPROM - c th ghi/xo ln ti 1 triu ln
Module iu khin ng c, c encoder
H tr giao tip USB
H tr iu khin Ethernet
H tr giao tip CAN
H tr giao tip LIN
H tr giao tip IrDA
Mt s dng c tch hp b RF (PIC16F639, v rfPIC)
KEELOQ M ho v gii m
DSP nhng tnh nng x l tn hiu s (dsPIC)
H vi iu khin PIC 8/16-bit
Cc link ny c ly t trang ch www.microchip.com, tuy nhin hin nay trang
ny ang rt thng b cht, c th do lng truy cp qu nhiu, v cc ng dn lun
thay i, v vy, c th link s b cht.
Vi iu khin 8-bit
PIC10, PIC12, PIC14, PIC16, PIC17, PIC18
Vi iu khin 16-bit:
PIC24
B iu khin x l tn hiu s 16-bit (dsPIC):
dsPIC30
dsPIC33F
B iu khin x l tn hiu s 32-bit (PIC32):
PIC32
Bi ging Chng 4

4.1.3 ARM
Cu trc ARM
Cu trc ARM (vit tt t tn gc l Acorn RISC Machine) l mt loi cu trc vi x
l 32-bit kiu RISC c s dng rng ri trong cc thit k nhng. Do c c im tit
kim nng lng, cc b CPU ARM chim u th trong cc sn phm in t di ng,
m vi cc sn phm ny vic tiu tn cng sut thp l mt mc tiu thit k quan trng
hng u.
Ngy nay, hn 75% CPU nhng 32-bit l thuc h ARM, iu ny khin ARM tr
thnh cu trc 32-bit c sn xut nhiu nht trn th gii. CPU ARM c tm thy
khp ni trong cc sn phm thng mi in t, t thit b cm tay (PDA, in thoi di
ng, my a phng tin, my tr chi cm tay, v my tnh cm tay) cho n cc thit
b ngoi vi my tnh ( a cng, b nh tuyn bn.) Mt nhnh ni ting ca h
ARM l cc vi x l Xscale ca Intel.

Tr s chnh ca cng ty ARM ti Cambridge Anh)

Mt b vi x l Conexant c dng
ch yu trong cc b nh tuyn

Lch s pht trin
Vic thit k ARM c bt u t nm 1983 trong mt d n pht trin ca cng ty
my tnh Acorn.
Nhm thit k, dn u bi Roger Wilson v Steve Furber, bt u pht trin mt b
vi x l c nhiu im tng ng vi K thut MOS 6502 tin tin. Acorn tng sn
xut nhiu my tnh da trn 6502, v vy vic to ra mt chip nh vy l mt bc tin
ng k ca cng ty ny.
Nhm thit k hon thnh vic pht trin mu gi l ARM1 vo nm 1985, v vo
nm sau, nhm hon thnh sn phm thc gi l ARM2. ARM2 c tuyn d liu 32-
bit, khng gian a ch 26-bit tc cho php qun l n 64 Mbyte a ch v 16 thanh ghi
32-bit. Mt trong nhng thanh ghi ny ng vai tr l b m chng trnh vi 6 bit cao
nht v 2 bit thp nht lu gi cc c trng thi ca b vi x l. C th ni ARM2 l b
vi x l 32-bit kh dng n gin nht trn th gii, vi ch gm 30.000 transistor (so
vi b vi x l lu hn bn nm ca Motorola l 68000 vi khong 68.000 transistor).
S n gin nh vy c c nh ARM khng c vi chng trnh (m chim khong
n 1/3 trong 68000) v cng ging nh hu ht cc CPU vo thi , khng h cha
cache. S n gin ny a n c im tiu th cng sut thp ca ARM, m li c
tnh nng tt hn c 286. Th h sau, ARM3, c to ra vi 4KB cache v c chc
nng c ci thin tt hn na.
Bi ging Chng 4

Vo nhng nm cui thp nin 80, hng my tnh Apple Computer bt u hp tc
vi Acorn pht trin cc th h li ARM mi . Cng vic ny tr nn quan trng n
ni Acorn nng nhm thit k tr thnh mt cng ty mi gi l Advanced RISC
Machines. V l do bn thng c gii thch ARM l ch vit tt ca Advanced
RISC Machines thay v Acorn RISC Machine. Advanced RISC Machines tr thnh cng
ty ARM Limited khi cng ty ny c a ra sn chng khon London v NASDAQ
nm 1998.
Kt qu s hp tc ny l ARM6. Mu u tin c cng b vo nm 1991 v
Apple s dng b vi x l ARM 610 da trn ARM6 lm c s cho PDA hiu Apple
Newton. Vo nm 1994, Acorn dng ARM 610 lm CPU trong cc my vi tnh RiscPC
ca h.
Tri qua nhiu th h nhng li ARM gn nh khng thay i kch thc. ARM2 c
30.000 transistors trong khi ARM6 ch tng ln n 35.000. tng ca nh sn xut li
ARM l sao cho ngi s dng c th ghp li ARM vi mt s b phn ty chn no
to ra mt CPU hon chnh, mt loi CPU m c th to ra trn nhng nh my
sn xut bn dn c v vn tip tc to ra c sn phm vi nhiu tnh nng m gi
thnh vn thp.
Th h thnh cng nht c l l ARM7TDMI vi hng trm triu li c s dng
trong cc my in thoi di ng, h thng video game cm tay, v Sega Dreamcast.
Trong khi cng ty ARM ch tp trung vo vic bn li IP, cng c mt s giy php to
ra b vi iu khin da trn li ny.
Dreamcast a ra b vi x l SH4 m ch mn mt s tng t ARM (tiu tn
cng sut thp, tp lnh gn ) nhng phn cn li th khc vi ARM. Dreamcast cng
to ra mt chip x l m thanh c thit k bi Yamaha vi li ARM7. Bn cnh ,
Gameboy Advance ca Nintendo, dng ARM7TDMI tn s 16,78 MHz.
Hng DEC cng bn giy php v li cu trc ARM (i khi chng ta c th b nhm
ln v h cng sn xut ra DEC Alpha) v sn xut ra th h Strong ARM. Hot ng
tn s 233 MHz m CPU ny ch tiu tn khong 1 watt cng sut (nhng i sau cn
tiu tn t cng sut hn na). Sau nhng kin tng, Intel cng c chp nhn sn xut
ARM v Intel nm ly c hi ny b sung vo th h gi ci i960 ca h bng
Strong ARM. T , Intel pht trin cho chnh h mt sn phm chc nng cao gi
tn l Xscale.
Cc dng li
H Li c tnh Cache (I/D)/MMU
MIPS in
hnh @ MHz
ng dng
ARM7TDMI
ARM7TDMI
(-S)
3-tng pipeline khng
15 MIPS @
16.8 MHz
Game Boy
Advance, Nintendo
DS, iPod
ARM710T MMU
36 MIPS @ 40
MHz
Psion 5 series
ARM720T 8KB unified, MMU
60 MIPS @
59.8 MHz

ARM740T MPU
ARM7EJ-S Jazelle DBX khng
ARM9TDMI ARM9TDMI 5-tng pipeline khng
Bi ging Chng 4

ARM920T 16KB/16KB, MMU
200 MIPS @
180 MHz
GP32,GP2X (li
u tin), Tapwave
Zodiac (Motorola i.
MX1)
ARM922T 8KB/8KB, MMU
ARM940T 4KB/4KB, MPU GP2X (li th hai)
ARM9E ARM946E-S
thay i c,
tightly coupled
memories, MPU

Nintendo DS, Nokia
N-Gage, Conexant
802.11 chips
ARM966E-S
khng c cache,
TCMs

ST Micro STR91xF,
includes Ethernet
[1]
ARM968E-S
khng c cache,
TCMs

ARM926EJ-S Jazelle DBX
thay i c,
TCMs, MMU
220 MIPS @
200 MHz
in thoi di ng:
Sony Ericsson (K,
W series),Siemens
and Benq (i x65
v i mi hn)
ARM996HS
Clockless
processor
khng caches,
TCMs, MPU

ARM10E ARM1020E (VFP) 32KB/32KB, MMU
ARM1022E (VFP) 16KB/16KB, MMU

ARM1026EJ-
S
Jazelle DBX
variable, MMU or
MPU

ARM11
ARM1136J
(F)-S
SIMD, Jazelle
DBX, (VFP)
variable, MMU

ARM1156T2
(F)-S
SIMD, Thumb-2,
(VFP)
thay i c,
MPU

ARM1176JZ
(F)-S
SIMD, Jazelle
DBX, (VFP)
thay i c,
MMU+TrustZone

ARM11
MPCore
1-4 core SMP,
SIMD, Jazelle
DBX, (VFP)
thay i c,
MMU

Cortex Cortex-A8
Application
profile, NEON,
Jazelle RCT,
Thumb-2
variable (L1+L2),
MMU+TrustZone
ln n 2000
(2.0
DMIPS/MHz
in speed from
600 MHz to
greater than 1
GHz)
Texas Instruments
OMAP3
Cortex-R4 Embedded profile
variable cache,
MMU optional
600 DMIPS
Broadcom l mt
hng s dng
Cortex-M3
Microcontroller
profile
no cache, (MPU)
120 DMIPS @
100MHz
Luminary Micro[2]
microcontroller
family
XScale
80200/IOP310
/IOP315
I/O Processor
80219
IOP321 Iyonix
IOP33x
Bi ging Chng 4

PXA210
/PXA250
Applications
processor
Zaurus SL-5600
PXA255 32KB/32KB, MMU
400 BogoMips
@400 MHz
Gumstix
PXA26x
PXA27x
800 MIPS @
624 MHz
HTC Universal,
Zaurus SL-C1000
PXA800(E)F
Monahans
1000 MIPS @
1.25 GHz

PXA900 Blackberry 8700
IXC1100
Control Plane
Processor

IXP2400
/IXP2800

IXP2850

IXP2325
/IXP2350

IXP42x NSLU2

IXP460
/IXP465

Cc lu v thit k
t c mt thit k gn, n gin v nhanh, cc nh thit k ARM xy dng n
theo kiu ni cng khng c vi chng trnh, ging vi b vi x l 8-bit 6502 tng
c dng trong cc my vi tnh trc ca hng Acorn.
Cu trc ARM bao gm cc c tnh ca RISC nh sau:
- Cu trc np/lu tr.
- Khng cho php truy xut b nh khng thng hng (by gi cho php
trong li Arm v6)
- Tp lnh trc giao
- File thanh ghi ln gm 16 x 32-bit
- Chiu di m my c nh l 32 bit d gii m v thc hin pipeline, t
c iu ny phi chp nhn gim mt m my.
- Hu ht cc lnh u thc hin trong vng mt chu k n.
So vi cc b vi x l cng thi nh Intel 80286 v Motorola 68020, trong ARM c
mt s tnh cht kh c o nh sau:
- Hu ht tt c cc lnh u cho php thc thi c iu kin, iu ny lm gim
vic phi vit cc tiu r nhnh cng nh b cho vic khng c mt b d
on r nhnh.
- Trong cc lnh s hc, ch ra iu kin thc hin, ngi lp trnh ch cn
sa m iu kin
Bi ging Chng 4

- C mt thanh ghi dch ng thng 32-bit m c th s dng vi chc nng
hon ho vi hu ht cc lnh s hc v vic tnh ton a ch.
- C cc kiu nh a ch theo ch s rt mnh
- C h thng con thc hin ngt hai mc u tin n gin nhng rt nhanh,
km theo cho php chuyn tng nhm thanh ghi.
4.2 Cc v d ng dng
4.2.1 Nhp nhy dy LED n
Mc ch ca v d ny khng phi l chng minh hot ng ca n LED, n
dng biu th tc hot ng ca cc vi iu khin. n gin ch cn kch hot n
LED nhp nhy c nhn thy c, cn thit phi cung cp thi gian vt
qua gia trng thi bt / tt ca n LED. Trong v d ny, thi gian tr c cung cp
bng cch thc hin mt chng trnh con tr, c gi l Delay. N l 3 vng lp lng
nhau s dng thanh ghi R0, R1 hoc R2. Sau khi tr v t cc chng trnh con, trng
thi ca chn l o ngc v cc th tc tng t c lp i lp li ...

;************************************************************************
;* PROGRAM NAME : Delay.ASM
;* DESCRIPTION: Program turns on/off LED on the pin P1.0
;* Software delay is used (Delay).
;************************************************************************
;BASIC DIRECTIVES
$MOD53
$TITLE(DELAY.ASM)
$PAGEWIDTH(132)
$DEBUG
$OBJECT
$NOPAGING

;STACK
DSEG AT 03FH
STACK_START: DS 040H

;RESET VECTORS
CSEG AT 0
JMP XRESET ;Reset vector
ORG 100H

XRESET: MOV SP,#STACK_START ;Define Stack pointer
MOV P1,#0FFh ;All pins are configured as inputs
LOOP:
CPL P1.0 ;Pin P1.0 state is inverted
LCALL Delay ;Time delay
SJMP LOOP
Delay:
MOV R2,#20 ;500 ms time delay
F02: MOV R1,#50 ;25 ms
F01: MOV R0,#230
DJNZ R0,$
DJNZ R1,F01
DJNZ R2,F02

END ;End of program
Bi ging Chng 4

4.2.2 Timer T0 trong ch chia tch
Tng t nh cc v d trc, chng trnh dnh phn ln thi gian ca mnh trong
vng mt gi l LOOP1. T 16-bit Timer T0 c chia thnh hai 8-bit timers, cng c hai
ngun ngt.
Ngt u tin c to ra sau khi Reset timer T0. Th tc TIM0_ISR, thc hin bit logic
khng (0) xoay quanh cng P1. Nhn t bn ngoi, c v nh l di chuyn LED.
Mt ngt c to ra khi thit lp li Timer T1. Th tc TIM1_ISR thc hin mt bit
HNG dng o chiu ca bit trc. K t khi bit ny xc nh hng bit sng LED, LED
s quay theo hng ca bit HNG. Nu bn bm mt nt nhn T1 ti mt s im, mt logic
s khng (0) trn u vo P3.2 s v hiu ha Timer T1.
;************************************************************************
;* PROGRAM NAME : Split.ASM
;* DESCRIPTION: Timer TL0 rotates bit on port P1, while TL1 determines
;* the rotation direction. Both timers operate in mode
;* 3. Logic zero (0) on output P3.2 disables rotation on port P1.
;************************************************************************

;BASIC DIRECTIVES

$MOD53
$TITLE(SPLIT.ASM)
$PAGEWIDTH(132)
$DEBUG
$OBJECT
$NOPAGING

;DECLARATION OF VARIABLES

BSEG AT 0

;DECLARATION OF BIT-VARIABLES

SEMAPHORE: DBIT 8
DIRECTION BIT SEMAPHORE

;STACK
DSEG AT 03FH

;RESET VECTORS

CSEG AT 0
JMP XRESET ; Reset vector
ORG 00BH

JMP TIM0_ISR ; Timer T0 reset vector

ORG 01BH
JMP TIM1_ISR ; Timer T1 reset vector

ORG 100H
XRESET: MOV SP,#STACK_START ; Define Stack pointer
MOV TMOD,#00001011B ; Define MOD3
MOV A,#0FFH
MOV P1,#0FFH
MOV R0,#30D
SETB TR0 ; TL0 is turned on
SETB TR1 ; TL1 is turned on
Bi ging Chng 4

MOV IE,#08AH ; Interrupt enabled
CLR C
CLR DIRECTION ; Rotate to the right

LOOP1: SJMP LOOP1 ; Remain here

TIM0_ISR:
DJNZ R0,LAB3 ; Slow down rotation by 256 times
JB DIRECTION,LAB1
RRC A ; Rotate contents of Accumulator
;to the right through
; Carry flag

SJMP LAB2
LAB1: RLC A ; Rotate contents of Accumulator
;to the left through
; Carry flag
LAB2: MOV P1,A ; Contents of Accumulator is
;moved to port P1
LAB3: RETI ; Return from interrupt

TIM1_ISR:
DJNZ R1,LAB4 ; Slow down direction
;of rotation by 256 times
DJNZ R2,LAB4 ; When time expires,
;change rotation direction
CPL SMER
MOV R2,#30D
LAB4: RETI

END ; End of program
4.2.3 S dng Timer T2
V d ny m t vic s dng cc Timer T2 cu hnh hot ng ch t ng
cp nht. Trong trng hp ny, n LED c kt ni vi cng P3 trong khi cc nt
nhn c s dng bt buc thit lp li b m thi gian (T2EX) c kt ni vi
chn P1.1.
Chng trnh thc hin tng t nh cc v d trc. Khi kt thc gi m, mt ngt
c kch hot v chng trnh con TIM2_ISR c thi hnh, do quay mt logic
khng (0) trong accumulator v di chuyn ni dung ca accumulator vi chn P3. Cui
cng, c gy ra mt ngt, c xa v tr v chng trnh cho vng lp LOOP1 ni
n vn cn cho n khi mt yu cu ngt mi xy ra...
Bi ging Chng 4

Nu bm T2EX, b m thi gian tm thi t li. Nt bm ny reset li timer, trong
khi nt nhn RESET resets cc vi iu khin.

;************************************************************************
;* PROGRAM NAME : Timer2.ASM
;* DESCRIPTION: Program rotates log. "0" on port P3. Timer2 determines
;* the speed of rotation and operates in auto-reload mode
;************************************************************************

;BASIC DIRECTIVES

$MOD53
$TITLE(TIMER2.ASM)
$PAGEWIDTH(132)
$DEBUG
$OBJECT
$NOPAGING

;DEFINITION OF VARIABLES

T2MOD DATA 0C9H
;STACK
DSEG AT 03FH

;RESET VECTORS
CSEG AT 0

ORG 02BH ; Timer T2 Reset vector
JMP TIM2_ISR

ORG 100H

MOV A,#0FFH
MOV P3,#0FFH
MOV RCAP2L,#0FH ; Prepare 16-bit auto-reload mode
MOV RCAP2L,#01H
CLR CAP2 ; Enable 16-bit auto-reload mod
Bi ging Chng 4

SETB EXEN2 ; Pin P1.1 reset is enabled
SETB TR2 ; Enable Timer T2
MOV IE,#0A0H ; Interrupt is enabled
CLR C

LOOP1: SJMP LOOP1 ; Remain here

TIM2_ISR: RRC A ; Rotate contents of Accumulator
;to the right through
; Carry flag
MOV P3,A ; Move the contents of
;Accumulator A to PORT3
CLR TF2 ; Clear timer T2 flag TF2
CLR EXF2 ; Clear timer T2 flag EXF2
RETI ; Return from interrupt

4.2.4 Dng ngt ngoi.
Di y l mt v d khc ca s thc thi ngt. Mt ngt ngoi c to ra khi mt
logic khng (0) l xy ra trn chn P3.2 hoc chn P3.3. Ty thuc vo l u vo hot ng
no, mt trong hai cng vic s c thc thi:

Mt logic s mc khng (0) trn P3.2 khi to s thc thi ngt Isr_Int0, v th s tng
dn trong R0 c sao chp ra cng P0. Logic s mc khng trn P3.3 khi to s thc thi
chng trnh con ngt Isr_Int1, s tng dn trong R1 c sao chp sang P1.
Trong ngn hn, mi ln bm vo cc nt nhn INT0 v INT1 s c tnh v ngay lp
tc c hin th nh dng nh phn trn cng thch hp (LED m chung dng).

;************************************************************************
;* PROGRAM NAME : Int.ASM
;* DESCRIPTION : Program counts interrupts INT0 generated by appearance of
high-to-low
;* transition signal on pin P3.2 Result appears on port P0. Interrupts INT1
are also
Bi ging Chng 4

;* counted up at the same time. They are generated byappearing high-to-low
transition
;* signal on pin P3. The result appears on port P1.
;************************************************************************

;BASIC DIRECTIVES

$MOD53
$TITLE(INT.ASM)
$PAGEWIDTH(132)
$DEBUG
$OBJECT
$NOPAGING

;RESET VECTORS

CSEG AT 0

ORG 003H ; Interrupt routine address for INT0
JMP Isr_Int0
ORG 013H ; Interrupt routine address for INT1
JMP Isr_Int1

ORG 100H
XRESET:
MOV TCON,#00000101B ; Interrupt INT0 is generated
;by appearing
; high-to-low transition signal on pin P3.2
; Interrupt INT0 is generated by appearing
; high-to-low transition signal on pin P3.3
MOV IE,#10000101B ; Interrupt enabled
MOV R0,#00H ; Counter starting value
MOV R1,#00H
MOV P0,#00H ; Reset port P0
MOV P1,#00H ; Reset port P1

LOOP: SJMP LOOP ; Remain here

Isr_Int0:
INC R0 ; Increment value of interrupt INT0 counter
MOV P0,R0
RETI

Isr_Int1:
INC R1 ; Increment value of interrupt INT1 counter
MOV P1,R1
RETI
4.2.5 Lp trnh ngt ngoi theo sn xung.
Pht hin nu c sn xung th sinh ngt, bt loa.
;Int1_Edge_Trigger
; Cha^n 1.3 no^'i vo+'i loa
; Khi co' ca.nh xuo^'ng o+? INT1 -> ba^.t
;loa 1 lu'c ro^`i ta('t
ORG 0000H
LJMP MAIN
;ISR cu?a INT1
Bi ging Chng 4

ORG 0013H ;INT1 ISR
SETB P1.3 ;ba^.t loa
MOV R3,#255
BACK: DJNZ R3,HERE ;delay 1 chu't
CLR P1.3 ;ta('t loa
RETI ;
;MAIN program for initialization
ORG 30H
MAIN: SETB TCON.2 ;INT1: ca.nh
MOV IE,#10000100B ;EN ngt ngoi 1
HERE: SJMP HERE ;cho+` nga('t
END
4.2.6 S dng LED 7 thanh
Cc v d sau y m t vic s dng n LED hin th 7 thanh. LED loi m chung.
K t khi ph bin cch t duy logic l mt (1) bt ci g ln v khng logic (0) tt
ci g , n hin th tiu th dng in nh (mc tiu th in nng thp) v cc cc
c ni vi in tr kh cao.
tit kim chn I/O, bn LED hin th c kt ni hot ng ch
multiplex. N c ngha l tt c cc on c cng tn c kt ni vi mt cng ra, v
ch c mt mn hnh LED hot ng ti mt thi im, ta gi l qut LED.
Tranzistors v segmenats trn mn hnh ny nhanh chng c kch hot, do lm
cho ta tng rng tt c cc ch s ang hot ng ng thi.

4.2.7 Vit ch s trn LED 7 thanh
Chng trnh ny l mt loi bi tp lm "nng ln" trc khi lm vic thc t. Mc
ch ca v d ny l hin th trn mn hnh bt c iu g . Ch Multiplex
khng c s dng thi gian ny. Thay vo , 3 ch s c hin th trn duy nht
mt trong s (u tin bn phi).
K t khi vi vi iu khin, "khng bit" lm th no vit s 3, mt chng trnh
con nh gi l Disp c s dng (vi iu khin vit s ny l 0000 0011). iu ny cho
php chng trnh con hin th tt c cc ch s thp phn (0-9). Nguyn tc hot ng
rt n gin. Mt s mun hin th, c cng vo a ch hin ti v lnh nhy c
thc thi, s khc mun hin th, s c nhy n a ch khc.

;************************************************************************
;* PROGRAM NAME : 7Seg1.ASM
;* DESCRIPTION: Program displays number "3" on 7-segment LED display
;************************************************************************

;BASIC DIRECTIVES

$MOD53
$TITLE(7SEG1.ASM)
$PAGEWIDTH(132)
$DEBUG
$OBJECT
$NOPAGING

;STACK
Bi ging Chng 4

DSEG AT 03FH

;RESET VECTORS
CSEG AT 0

ORG 100H

MOV P1,#0 ; Turn off all segments on displays
MOV P3,#20h ; Activate display D4

LOOP:
MOV A,#03 ; Send number 3 to display
LCALL Disp ; Perform appropriate masking for the number
MOV P1,A
SJMP LOOP

Disp: ; Subroutine for displaying digits
INC A
MOVC A,@A+PC
RET
DB 3FH ; Digit 0 mask
DB 06H ; Digit 1 mask
DB 5BH ; Digit 2 mask
Bi ging Chng 4

DB 6DH ; Digit 5 mask
DB 7DH ; Digit 6 mask

4.2.8 Thng bo bng vn bn trn mn hnh LCD
V d ny s dng loi LCD ph bin nht hin th vn bn trong hai dng vi 16
k t mi dng. tit kim chn IO ca vi iu khin, ch c 4 chn c s dng cho
giao tip d liu. Bng cch ny, mi byte c truyn i theo hai bc: u tin l 4 bit
cao sau l 4 bit thp.
LCD cn phi c khi to ti u chng trnh (trc khi s dng cc tnh nng
ghi c LCD). Bn cnh , cc phn ca chng trnh lp i lp li trong chng trnh
to ra mt chng trnh con c bit. Tt c iu ny c v rt phc tp, nhng ton b
chng trnh v c bn thc hin mt s hot ng n gin v hin th dng ch LCD
display.

*************************************************************************
;* PROGRAM NAME : Lcd.ASM
;* DESCRIPRTION : Program for testing LCD display. 4-bit communication
;* is used. Program does not check BUSY flag but uses program delay
;* between 2 commands. PORT1 is used for connection
;* to the microcontroller.
;************************************************************************

;BASIC DIRECTIVES

$MOD53
$TITLE(LCD.ASM)
$PAGEWIDTH(132)
$DEBUG
$OBJECT
$NOPAGING

;Stack
DSEG AT 0E0h
Bi ging Chng 4

Stack_Start: DS 020h

Start_address EQU 0000h

;Reset vectors
CSEG AT 0
ORG Start_address
JMP Inic

ORG Start_address+100h

MOV IE,#00 ; All interrupts are disabled
MOV SP,#Stack_Start

Inic: CALL LCD_inic ; Initialize LCD

;*************************************************
;* MAIN PROGRAM
;*************************************************

START: MOV A,#80h ; Next character will appear on the first
CALL LCD_status ; location in the first line
;of LCD display.
MOV A,#' ' ; Display character .
CALL LCD_putc ; Call subroutine for
;character transmission.
CALL LCD_putc
CALL LCD_putc
CALL LCD_putc
CALL LCD_putc
CALL LCD_putc
MOV A,#'L' ; Display character L.
CALL LCD_putc
MOV A,#'C' ; Display character C.
CALL LCD_putc
MOV A,#'D' ; Display character D.
CALL LCD_putc

MOV A,#0c0h ; Next character will appear;
; on the first
CALL LCD_status ; location in the second line
;of LCD display.
CALL LCD_putc ; Call subroutine for
;character transmission.
CALL LCD_putc
CALL LCD_putc
CALL LCD_putc
MOV A,#'D' ; Display character D.
CALL LCD_putc
MOV A,#'i' ; Display character i.
CALL LCD_putc
MOV A,#'s' ; Display character s.
Bi ging Chng 4

CALL LCD_putc
MOV A,#'p' ; Display character p.
CALL LCD_putc
MOV A,#'l' ; Display character l.
CALL LCD_putc
MOV A,#'a' ; Display character a.
CALL LCD_putc
MOV A,#'y' ; Display character y.
CALL LCD_putc

MOV R0,#20d ; Wait time (20x10ms)
CALL Delay_10ms
MOV DPTR,#LCD_DB ; Clear display
MOV A,#6d
CALL LCD_inic_status
MOV R0,#10d ; Wait time(10x10ms)
CALL Delay_10ms
JMP START

;*********************************************
;* Subroutine for wait time (T= r0 x 10ms)
;*********************************************

Delay_10ms: MOV R5,00h ; 1+(1+(1+2*r7+2)*r6+2)*r5 approximately
MOV R6,#100d ; (if r7>10)
MOV R7,#100d ; 2*r5*r6*r7
DJNZ R7,$ ; $ indicates current instruction.
DJNZ R6,$-4
DJNZ R5,$-6
RET

;*************************************************************************
;* SUBROUTINE: LCD_inic
;* DESCRIPTION: Subroutine for LCD initialization.
;*
;* (is used with 4-bit interface, under condition that pins DB4-7 on LCD
;* are connected to pins PX.4-7 on microcontrollers ports,
; i.e. four higher
;* bits on the port are used).
;*
;* NOTE: It is necessary to define port pins for controlling LCD operation:
;* LCD_enable, LCD_read_write,
; LCD_reg_select,similar to port for connection to LCD.
;* It is also necessary to define addresses for the first character in each
;* line.
;*************************************************************************

LCD_enable BIT P1.3 ; Bit for activating pin E on LCD.
LCD_read_write BIT P1.1 ; Bit for activating pin RW on LCD.
LCD_reg_select BIT P1.2 ; Bit for activating pin RS on LCD.
LCD_port SET P1 ; Port for connection to LCD.
Busy BIT P1.7 ; Port pin on which Busy flag appears.

LCD_Start_I_red EQU 00h ; Address of the first message character
; in the first line of LCD display.
LCD_Start_II_red EQU 40h ; Address of the first message character
; in the second line of LCD display.

LCD_DB: DB 00111100b ; 0 -8b, 2/1 lines, 5x10/5x7 format
DB 00101100b ; 1 -4b, 2/1 lines, 5x10/5x7 format
DB 00011000b ; 2 -Display/cursor shift, right/left
Bi ging Chng 4

DB 00001100b ; 3 -Display ON, cursor OFF,
;cursor blink off
DB 00000110b ; 4 -Increment mode, display shift off
DB 00000010b ; 5 -Display/cursor home
DB 00000001b ; 6 -Clear display
DB 00001000b ; 7 -Display OFF, cursor OFF,
; cursor blink off

LCD_inic:
;*****************************************

MOV DPTR,#LCD_DB
MOV A,#00d ; Triple initialization in 8-bit
CALL LCD_inic_status_8 ; mode is performed at the beginning
MOV A,#00d ; (in case of slow increment of
CALL LCD_inic_status_8 ; power supply when the power supply is on
MOV A,#00d
lcall LCD_inic_status_8

MOV A,#1d ; Change from 8-bit into
CALL LCD_inic_status_8 ; 4-bit mode
MOV A,#1d

MOV A,#3d ; As from this point the program executes in
;4-bit mode
MOV A,#6d
MOV A,#4d

RET

LCD_inic_status_8:
;******************************************
PUSH B

MOVC A,@A+DPTR
CLR LCD_reg_select ; RS=0 - Write command
CLR LCD_read_write ; R/W=0 - Write data on LCD

MOV B,LCD_port ; Lower 4 bits from LCD port are memorized
ORL B,#11110000b
ORL A,#00001111b
ANL A,B

MOV LCD_port,A ; Data is moved from A to LCD port
SETB LCD_enable ; high-to-low transition signal
; is generated on the LCD's EN pin
CLR LCD_enable

MOV B,#255d ; Time delay in case of improper reset
DJNZ B,$ ; during initialization
DJNZ B,$
DJNZ B,$

POP B
RET

LCD_inic_status:
Bi ging Chng 4

;*************************************************************************
MOVC A,@A+DPTR
CALL LCD_status
RET

;*************************************************************************
;* SUBROUTINE: LCD_status
;* DESCRIPTION: Subroutine for defining LCD status.
;*************************************************************************

LCD_status: PUSH B
MOV B,#255d
DJNZ B,$
DJNZ B,$
DJNZ B,$
CLR LCD_reg_select ; RS=O: Command is sent to LCD
CALL LCD_port_out

SWAP A ; Nibles are swapped in accumulator

DJNZ B,$
DJNZ B,$
DJNZ B,$
CLR LCD_reg_select ; RS=0: Command is sent to LCD
CALL LCD_port_out

POP B
RET
;************************************************************************
;* SUBROUTINE: LCD_putc
;* DESCRIPTION: Sending character to be displayed on LCD.
;************************************************************************

LCD_putc: PUSH B
MOV B,#255d
DJNZ B,$
SETB LCD_reg_select ; RS=1: Character is sent to LCD
CALL LCD_port_out

SWAP A ; Nibles are swapped in accumulator

DJNZ B,$
SETB LCD_reg_select ; RS=1: Character is sent to LCD

CALL LCD_port_out
POP B
RET

;*************************************************************************
;* SUBROUTINE: LCD_port_out
;* DESCRIPTION: Sending commands or characters on LCD display
;*************************************************************************

LCD_port_out: PUSH ACC
PUSH B
MOV B,LCD_port ; Lower 4 bits of LCD port are memorized
ORL B,#11110000b
ORL A,#00001111b
ANL A,B

MOV LCD_port,A ; Data is copied from A to LCD port
Bi ging Chng 4

SETB LCD_enable ; high-to-low transition signal
; is generated on the LCD's EN pin
CLR LCD_enable

POP B
POP ACC
RET

4.2.9 Nhn d liu qua UART
kch hot tnh nng giao tip ni tip UART thnh cng, iu cn thit p
ng cc quy nh c th ca chun RS232. N ch yu cp n cc cp in p theo
yu cu ca chun ny. Theo ,-10V n -3V l mc logic mt (1) trong thng ip,
trong khi 3V n 10 V l mc logic khng (0). Cc vi iu khin chuyn i chnh xc
d liu v nh dng ni tip, nhng ngun cung cp in p ch 5V. T , khng phi
d dng chuyn i 0V thnh 10V v 5V thnh -10V, Hot ng ny trn c ng
truyn v ng nhn d liu. y, MAX232 ca Maxim c s dng bi v n c
ph bin rng ri, r v ng tin cy.

V d ny cho thy lm th no nhn c thng ip gi t PC. Timer T1 to tc baud.
T khi thch anh 11,0592 MHz c s dng, rt d dng c c tiu chun tc truyn
m tc baud l 9600 bps. Mi d liu nhn c ngay lp tc c chuyn ra P1.

;************************************************************************
;* PROGRAM NAME : UartR.ASM
;* DESCRIPTION: Each data received from PC via UART appears on the port
;* P1.
;*
;************************************************************************
Bi ging Chng 4

;BASIC DIRECTIVES

$MOD53
$TITLE(UARTR.ASM)
$PAGEWIDTH(132)
$DEBUG
$OBJECT
$NOPAGING

;STACK
DSEG AT 03FH

;RESET VECTORS
CSEG AT 0
ORG 023H ; Starting address of
;UART interrupt routine
JMP IR_SER

ORG 100H

XRESET: MOV IE,#00 ; All interrupts are disabled
MOV SP,#STACK_START ; Initialization of Stack pointer
MOV TMOD,#20H ; Timer1 in mode2
MOV TH1,#0FDH ; 9600 baud rate at the frequency of
; 11.0592MHz
MOV SCON,#50H ; Receiving enabled, 8-bit UART
MOV IE,#10010000B ; UART interrupt enabled
CLR TI ; Clear transmit flag
CLR RI ; Clear receive flag
SETB TR1 ; Start Timer1


IR_SER: JNB RI,OUTPUT ; If any data is received,
; move it to the port
MOV A,SBUF ; P1
MOV P1,A
OUTPUT: RETI

4.2.10 Truyn d liu qua UART
Chng trnh ny m t cch s dng UART truyn d liu. Mt dy s (0-255) c truyn
n my PC tc truyn 9600 baud. MAX 232 c s dng nh l mt iu p.

;************************************************************************
;* PROGRAM NAME : UartS.ASM
;* DESCRIPTION: Sends values 0-255 to PC.
;************************************************************************

;BASIC DIRECTIVES

$MOD53
$TITLE(UARTS.ASM)
$PAGEWIDTH(132)
$DEBUG
Bi ging Chng 4

$OBJECT
$NOPAGING

;STACK
DSEG AT 03FH

;RESET VECTORS
CSEG AT 0

ORG 100H

XRESET: MOV IE,#00 ; All interrupts are disabled
MOV SP,#STACK_START ; Initialization of Stack pointer
MOV TMOD,#20H ; Timer1 in mode 2
MOV TH1,#0FDH ; 9600 baud rate at the frequency of
; 11.0592MHz
MOV SCON,#40H ; 8-bit UART
CLR TI ; Clear transmit bit
MOV R3,#00H ; Reset caunter
SETB TR1 ; Start Timer 1

START: MOV SBUF,R3 ; Move number from counter to a PC
LOOP1: JNB TI,LOOP1 ; Wait here until byte transmission is
; complete
CLR TI ; Clear transmit bit
INC R3 ; Increment the counter value by 1

CJNE R3,#00H,START ; If 255 bytes are not sent return to the
; label START



4.2.11 Chng trnh con phc v truyn thng ni tip
Serial_Init: ;Khi to:
;Set timer 1 mode to 8-bit Auto-Reload
mov TMOD,#20H
;Enable reception
;Set Serial port mode to 8-bit UART
mov SCON,#50H
;Set baudrate to 9600 at 11.0592MHz
mov TH1,#0FDH
mov TL1,#0FDH
;Start Timer
setb TR1
ret

Serial_Send: ; truyn ni dung thanh ghi A ra UART
;wait for last data to be
;sent completely
jnb TI,Serial_Send
;clear the transmit interrupt flag
Bi ging Chng 4

clr TI
;Then move the data to send in SBUF
mov SBUF,A
ret

Serial_Read: ; nhn t UART v thanh ghi A
;Wait for Receive interrupt flag
jnb RI,Serial_Read
;If falg is set then clear it
clr RI
;Then read data from SBUF
mov A,SBUF
ret

4.2.12 Truyn thng UART cho 8051 bng phn mm
thc hin thnh cng UART u tin chng ta cn phi bit giao thc truyn
thng UART.

S trn cho thy dng sng ca mt frame truyn. u tin l bit bt u .. sau
8-bit d liu v ti mt bit dng cui. C mt cng thc b mt tnh ton thi gian tr
hon l c baudrate chnh xc gia cc bit.
Di y l mt phn mm trin khai UART, trong c th c s dng chng
trnh C cng nh ASM. N c vit cho phn mm Keil. Nhng vi mt vi thay i
nh bn c th dng n trong chng trnh ca bn.

?SU?PUTC SEGMENT CODE
?SU?GETC SEGMENT CODE

PUBLIC _putc
PUBLIC getc

txd_pin EQU P3.1 ;Transmit on this pin
rxd_pin EQU P3.0 ;Receive on this pin

;Formula to calculate the bit time delay constant
;This constant is calculated as: (((crystal/baud)/12) - 5) / 2
;crystal is the frequency of crystal in Hz
;baud is required baudrate
;Please try to keep baudrate below 9600
;to get best results :)

BITTIM EQU 45; (((11059200/9600)/12) - 5) / 2

;--------------------------------------------
;To send data serially
;For C programs
Bi ging Chng 4

;Protype definition:
; void putc(unsigned char);
;Usage:
; putc(data);
;Return:
; This function returns nothing
;
;For Assembly Programs:
;
;Usage:
; data to be send has to be moved to R7
; for example:
; mov R7,#'a'
; lcall _putc
;--------------------------------------------
RSEG ?SU?PUTC
_putc:
push ACC
Push PSW
mov a,r7
CLR txd_pin ;Drop line for start bit
MOV R0,#BITTIM ;Wait full bit-time
DJNZ R0,$ ;For START bit
MOV R1,#8 ;Send 8 bits
putc1:
RRC A ;Move next bit into carry
MOV txd_pin,C ;Write next bit
DJNZ R0,$ ;For DATA bit
DJNZ R1,putc1 ;write 8 bits
SETB txd_pin ;Set line high
RRC A ;Restore ACC contents
DJNZ R0,$ ;For STOP bit
POP PSW
pop ACC
RET

;--------------------------------------------
;To receive data Serially
;If you want to use this routine in your
;C program then define function prototype
; as:
; unsigned char getc(void);
;
; Usage:
; data = getc();
; Return value:
; Returns data received
;If you are using it in assembly program
; Usage:
; lcall getc
; Return:
; data received is stored in R7
;--------------------------------------------

Bi ging Chng 4

RSEG ?SU?GETC
getc:
Push ACC
Push PSW
JB rxd_pin,$ ;Wait for start bit
MOV R0,#BITTIM/2 ;Wait 1/2 bit-time
DJNZ R0,$ ;To sample in middle
JB rxd_pin,getc ;Insure valid
MOV R1,#8 ;Read 8 bits
getc1:
DJNZ R0,$ ;For DATA bit
MOV C,rxd_pin ;Read bit
RRC A ;Shift it into ACC
DJNZ R1,getc1 ;read 8 bits
mov r7,a
POP PSW
pop ACC
RET ;go home

4.2.13 Ghp ni 8051 vi ADC0804, chuyn i ADC
rd equ P1.0 ;Read signal P1.0
wr equ P1.1 ;Write signal P1.1
cs equ P1.2 ;Chip Select P1.2
intr equ P1.3 ;INTR signal P1.3
adc_port equ P2 ;ADC data pins P2
adc_val equ 30H ;ADC read value stored here

org 0H
start: ;Start of Program
acall conv ;Start ADC conversion
acall read ;Read converted value
mov P3,adc_val ;Move the value to Port 3
sjmp start ;Do it again

conv: ;Start of Conversion
clr cs ;Make CS low
clr wr ;Make WR Low
nop
setb wr ;Make WR High
setb cs ;Make CS high
wait:
jb intr,wait ;Wait for INTR signal
ret ;Conversion done

read: ;Read ADC value
clr cs ;Make CS Low
clr rd ;Make RD Low
mov a,adc_port ;Read the converted value
mov adc_val,a ;Store it in local variable
setb rd ;Make RD High
setb cs ;Make CS High
ret ;Reading done
Bi ging Chng 4

4.2.14 Chuyn i s nh phn sang s thp phn
Khi s dng n LED v mn hnh LCD, thng cn thit phi chuyn i s t nh
phn sang s thp phn. V d, nu mt vi thanh ghi c cha s dng nh phn, cn
hin th s trn mt mn hnh LED ba ch s, cn thit phi chuyn n sang dng
thp phn. Ni cch khc, n l cn thit xc nh nhng g s c hin th trn mn
hnh hin th bn phi nht (n v), gia hin th (hng chc) v hin th tri nht
(hng trm).
Cc chng trnh con di y thc hin chuyn i mt byte. S nh phn c lu
tr trong accumulator, trong khi s nh dng thp phn c lu trong thanh ghi
R3, R2 v accumulator (n v, hng chc v hng trm, tng ng).

;************************************************************************
;* SUBROUTINE NAME : BinDec.ASM
;* DESCRIPTION : Content of accumulator is converted into
;* three decimal digits
;************************************************************************

BINDEC: MOV B,#10d ; Store decimal number 10 in B
DIV AB ; A:B. Remainder remains in B
MOV R3,B ; Move units to register R3
MOV B,#10d ; Store decimal number 10 in B
MOV R2,B ; Move tens to register R2
MOV B,#10d ; Store decimal number 10 in B
MOV A,B ; Move hundreds to accumulator
RET ; Return to the main program
4.2.15 Ghp ni vi iu khin vi bn phm

Hnh 4-1.Ma trn bn phm
Hnh 4-2.Cch ghp ni bn phm

on chng trnh gi m ASCII khi bm phm P0.1

Bi ging Chng 4

4.2.16 Ghp ni vi iu khin vi step motor
Bi ton thc hin vic iu khin ng c bc quay, thay i tc , o chiu,
dng ng c. Chng trnh s dng 4 u to xung vo ng c lm thay i trng
thi ca ng c bc.
Thng cc cun dy ca ng c bc c xc nh theo mu dy, tuy nhin i vi mt
ng c bt k, ta c th dng ng h xc nh dy nh hnh v, y trnh by cch xc
nh ng c c 5, 6 u dy.

Hnh 4-3. Cu to ng c bc

1. dng ng h xc nh u chung (common) dng ng h thang o tr, o tr gia
cc cp dy, u chung l u c tr gia n v cc u khc bng in tr cc u khc
vi nhau.
Khi bit c th t cc cun dy, ta kch xung theo th t ng c s chy.
V d mt on chng trnh sau, gi s 4 u ca ng c bc u vo 4 bit: P1.0
P1.3 ca 8051.
ORG 0000H
MOV R3, #00000011B
MOV A, R3
BACK: MOV P1,A
RL A ;Quay thanh ghi A
ACALL DELAY
SJMP BACK
DELAY:
MOV R1, #50
H1: MOV R2 , #255
H2: DJNZ R2, H2
DJNZ R1, H1
RET
END

Bi ging Chng 4

Ti liu tham kho

1. Tng Vn On, Hong c Hi, H vi iu khin 8051, NXB Lao ng x hi, nm
2001
2. Nguyn Tng Cng, Cu trc v lp trnh h vi iu khin 8051, NXB Khoa hc v
k thut, nm 2004
3. Nguyn Minh Tun, Gio trnh hp ng - Chng 1, HKHTN, 2002
4. Randal Hyde, The art of assembly language programming Chapter 1.
5. Norton Guide
6. Dan Rollins, TechHelp v.6.0
7. http://picat.dieukhien.net
8. http://wapedia.mobi/vi/Hp_ng
9. http://www.emu8086.com/
10. http://www.daniweb.com/code/
11. http://www.freewebs.com/maheshwankhede/adcdac.html

Bai Giang VXL VDK Chuan 2009 2010

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Bai Giang VXL VDK Chuan 2009 2010

Uploaded by

Copyright:

Available Formats

TRNG I HC K THUT CNG NGHIP

You might also like