1

MOS Digital Circuits

Chapter 16
In the late 70s as the era of LSI and VLSI
began, NMOS became the fabrication
technology choice.
Later the design flexibility and other
advantages of the CMOS were realized,
CMOS technology then replaced NMOS at all
level of integration.
The small transistor size and low power
dissipation of CMOS circuits, demonstration
principal advantages of CMOS over NMOS
circuits.
NMOS Inverter
For any IC technology used in digital
circuit design, the basic circuit element
is the logic inverter.
Once the operation and
characterization of an inverter circuits
are thoroughly understood, the results
can be extended to the design of the
logic gates and other more complex
circuits.
NMOS Inverter
If V
I
<V
NT
, the transistor is in
cutoff and i
D
=0, there is no
voltage drop across R
D
, and
the output voltage is
V
o
=V
DD
=V
DS
If V
I
>V
NT,
the transistor is on
and initially is biased in
saturation region, since
V
DS
>V
GS
-V
TN
.
As the input voltage increases
(V
GS
) , the drain to source
voltage (V
DS
) decreases and
the transistor inter into the
non saturation region.
+
+
V
GS
=V
R
D
=V
DD
=V
DS
NMOS Inverter Transfer Characteristics with
load resister (Saturation Region)
+
+
V
GS
=V
R
D
=V
DD
=V
DS
V
GS
=V
R
D
=V
DD
=V
DS
As the input is increased slightly above
the V
TN
, the transistor turns on and is in
the saturation region. The output
voltage is then
v
o
= V
DD
i
D
R
D
(16.6 )
where the drain current is given by
i
D
= K
n
(V
GS
- V
TN
)
2
= K
n
(V
i
- V
TN
)
2
( 16.7)
By substituting the value of I
D
from Eq.
16.7 we get ,
V
O
= V
DD
- K
n
R
D
(V
I
- V
TN
)
2
(16.8)
which relates the output and input
voltages as long as the transistor is
biased in the saturation region.
NMOS Inverter Transfer Characteristics with
load resister (transition Region)
As the input voltage is further increases
and voltage drop across the R
D
become
sufficient to reduce the drain to source
voltage such that
V
DS
V
GS
-V
TN
.
the Q-point of the transistor moves up the
load line. At the transition point, we have
v
ot
= V
It
- V
TN
16.9
where V
o
, and V
I
, are the drain-to-source
and gate-to-source voltages,
respectively, at the transition point. By
substituting Equation (16.9) into (16.8),
the input voltage at the transition point
can be determined as,
K
n
R
D
(V
It
- V
TN
)
2
+ (V
It
- V
TN
) - V
DD
= 0
+
+
V
GS
=V
R
D
=V
DD
=V
DS
V
GS
=V
R
D
=V
DD
=V
DS
NMOS Inverter Transfer Characteristics with
load resister (Nonsaturation Region)
As the input voltage becomes
greater than V
It
, the Q-point
continues to move up the load
line, and the transistor becomes
biased in the nonsaturation region.
The drain current is then
i
D
= K
n
[2(V
GS
- V
TN
)V
DS
V
DS
2
]
= K
n
[2(v
I
- V
TN
)V
O
V
o
2
] (16.11)
The output voltage is then
determined by vo = V
DD

i
D
R
D
Substitute the value of I
D
from
above equation we get the output
voltage relation when the
transistor is biased in
nonsaturation region.
V
O
= V
DD
K
n
R
D
[2(v
l
- V
TN
)vo -
v
o
2
]
+
+
V
GS
=V
R
D
=V
DD
=V
DS
V
GS
=V
R
D
=V
DD
=V
DS
2
+
+
VGS=V
RD
=VDD=VDS
VGS=V
RD
=VDD=VDS
It should be be noted that the minimum output voltage, or the logic 0 level, for a high
input decreases with increasing load resistance, and the sharpness of the transition
region between a low input and a high input increases with increasing load resistance.
Summary of NMOS inverter C-V
relationship with the resister load
Saturation region
Transition region
i
D
= Kn(V
GS
- V
TN
)
2
= K
n
(V
i
- V
TN
)
2
V
O
= V
DD
- K
n
R
D
(V
I
- V
TN
)
2
v
ot
= V
It
- V
TN
K
n
R
D
(V
It
- V
TN
)
2
+ (V
It
- V
TN
) - V
DD
Nonsaturation region
= K
n
[2(v
I
- V
TN
)V
O
V
o
2
] i
D
V
O
= V
DD
K
n
R
D
[2(v
l
- V
TN
)vo - v
o
2
]
+
+
V
GS
=V
RD
=VDD=VDS
V
GS
=V
RD
=VDD=VDS
NMOS Inverter with Enhancement
Load
This basic inverter
consist of two
enhancement-only
NMOS transistors
and is much more
practical than the
resister loaded
inverter, which is
thousand of times
larger than a
MOSFET.
n-Channel MOSFET connected as
saturated load device
An n-channel enhancement-mode
MOSFET with the gate connected to
the drain can be used as load device in
an NMOS inverter.
Since the gate and drain of the
transistor are connected, we have
V
GS
=V
DS
When V
GS
=V
DS
>V
TN,
a non zero drain
current is induced in the transistor and
thus the transistor operates in
saturation only. And following condition
is satisfied.
V
DS
>(V
GS
-V
TN
)
V
DS
(sat)= (V
DS
-V
TN
) because
V
GS
=V
DS
or V
DS
(sat)= (V
GS
-V
TN
)
In the saturation region the drain current is
i
D
=K
n
(V
GS
-V
TN
)
2
= K
n
(V
DS
-V
TN
)
2
The i
D
versus v
DS
characteristics are shown in Figure 16.7(b),
which indicates that this device acts as a nonlinear resistor.
NMOS Inverter with Enhancement
Load/Saturated
In the saturation region the load
drain current is
i
DL
=K
L
(V
GSL
-V
TNL
)
2
= K
L
(V
DSL
-V
TNL
)
2
For V
GSD
<V
TN
( driver transistor )
transistor is in cutoff mode and
does not conduct drain current
0= i
DL
=K
L
(V
GSL
-V
TNL
)
2
= K
L
(V
DSL
-
V
TNL
)
2
V
GSL
=V
TNL
or V
DSL
=V
TNL
As a result the output high voltage
V
O
is degraded by the threshold
voltage or
V
O,, max
= V
OH
=V
DD
-V
TNL
NMOS inverter with Enhancement
Load/Saturated (Cont.)
As the V
I
=>V
TND
A non zero drain current is induced in
the transistor and thus the drive
transistor operates in saturation only.
As shown in the figure the following
condition is satisfied
i
DD
=i
DL or
K
D
(V
GSD
-V
TND
)
2
= K
L
(V
GSL
-V
TNL
)
2
Substituting V
GSD
=V
I
and V
GSL
=V
DD
-V
O
yields
K
D
(V
I
- V
TND
)
2
= K
L
(V
DD
- V
O
- V
TNL
)
2
Solving for V
O
gives
V
O
= V
DD
-V
TNL
- K
D
/K
L
(V
I
-V
TND
)
3
NMOS inverter with Enhancement
Load/Saturated (driver at the transition point)
As the input voltage (V
GS
) further
increases, the drive Q-point
moves up and switch into the
transition region., we have
V
DSD
(sat)= V
GSD
-V
TND
In terms of input/output transition
voltages
or V
Ot
=V
It
-V
TND
Substituting above Equation into
following equation
V
O
= V
DD
-V
TNL
- K
D
/K
L
(V
I
-V
TND
)
we find the input voltage at the
transition point, which is
V
It
= [V
DD
V
TNL
+V
TND
(1+ K
D
/K
L
)]/(1+
K
D
/K
L
)
NMOS Inverter with Enhancement Load/Saturated
(driver at the non saturation region))
As the input voltage becomes greater than VIt the driver
transistor Q- point continues to move up the load
curve and the driver becomes biased in the
nonsaturation region. Since the driver and load drain
currents are still equal, or iDD = iDL, we now have
KD[2(VGSD - VTND)VDSD - VDSD
2
] = KL(VDSL -VTNL)
2
Substituting VGSD=VI and VDSD=VO and VDSL= VDD-VO we
get
KD[2(vl -VTND) Vo- VO
2
] = KL(VDD - VO - VTNL)
2
The ratio K
D
IK
L
is the aspect ratio and is
related to the width-to-length parameters
of the driver and load transistors.
The slope of the VTC curves in the saturation region is
known as inverter gain and is given by
dVo/dVI= - KD/KL
If the inverter gain is greater then unity, the inverter logic
gate is belonged to restoring logic family.
Limitation of NMOS
inverter
Example 16.3
Limitation of Enhancement Load inverter
VO,max= V
OH
=V
DD
-V
TNL
the output high voltage V
O
is degraded by the threshold
voltage.
NMOS Inverter with Depletion Load
This is an alternate form of
the NMOS inverter that
uses an enhancement-
depletion MOSFET load
device with gate and source
terminal connected.
This inverter has the
advantage of V
O
= V
DD
, as
well as more abrupt VTC
transition region even though
the W/L ratio for the output
MOSFET is small.
The term depletion mode
means that a channel exists
even with zero gate voltage.
4
N-Channel Depletion-Mode
MOSFET
In n- channel
depletion mode
MOSFET, an n-
channel region or
inversion layer exists
under the gate oxide
layer even at zero
gate voltage and
hence term depletion
mode.
A negative voltage
must be applied to the
gate to turn the
device off.
The threshold
voltage is always
negative for this
kind of device.
NMOS Inverter with Depletion Load
(saturation condition)
With the gate and source
are connected, V
GSL
=0.
Since the threshold voltage
of load transistor is
negative, we have
V
GSL
=0>V
TNL
= -(V
TNL
)
This implies that load
MOSFET is always active.
For an active device we can
write
V
DSL
V
GSL
V
TNL
= -V
TNL
=V
TNL
becauseV
GSL
=0.
NMOS Inverter with Depletion Load (cont.)
Case I: when V
I
<V
TND
(drive is
cutoff): No drain current conduct
in either transistor. That means
the load transistor must be in the
linear region of the operation and
the output current can be
expressed as fellows
i
DL
(linear)=K
L
[2(V
GSL
- V
TNL
)V
DSL
-
V
DSL
2
]
Since V
GSL
=0, and i
DL=0
0=-K
L
[2V
TNL
V
DSL
+ V
DSL
2
]
Which gives V
DSL
=0 thus
V
O
= V
DD
This is the advantage of the
depletion load inverter over the
enhancement load inverter.
NMOS Inverter with Depletion Load
(Cont.)
Case II: When V
I
>V
TND
(driver turns
on)
and is biased in the saturation
region; however, the load is
biased in the nonsaturation
region.
Under the condition we can write
i
DD
=I
DDL
K
D
(V
GSD
-V
TND
)
2
=K
L
[2(V
GSL
- V
TNL
)V
DSL
- V
DSL
2
]
Substituting V
GSD
=V
I
, V
GSL
=0, and
V
DSL
=V
DD
-V
O
Yields
K
D
(V
I
-V
TND
)
2
=K
L
[2(-V
TNL
)(V
DD
-
V
O
)-V
DD
V
O
)
2
]
Which relates the input and output
voltage as long as the driver is
biased in saturation region and
Two transition points for NMOS depletion
load inverter
In the Figure the point B and C are
corresponding the two transition points:
one for the load and one for the driver.
The transition point for the load is given by,
V
DSL
=V
DD
-V
Ot
Also V
DSL
=V
GSL
-V
TNL
By equating the relations we get
V
DD
-V
Ot
=V
GSL
-V
TNL
Since V
GSL
=0
V
0t
=V
DD
+V
TNL
As we know V
TNL
is negative. This implies that
V
ot
<V
DD
The transition point for the driver is given
by
V
DSD
=V
GSD
-V
TND
Or in terms of input and output voltage we can
write
V
Ot
=V
It
-V
TND
When both devices (driver and load) are in
saturation region
When both devices are biased in
saturation region the Q point lies
between point B and C on the load
curve, and
K
D
(V
GSD
-V
TND
)
2
= K
L
(V
GSL
-V
TNL
)
2
Or
K
D
/K
L
(V
I-
V
TND
)=-V
TNL
Implies that input voltage is constant as
the Q-point passes this region.
If we further increased the input voltage,
the drive is biased in the nosaturation
region while load is in saturation
region. The Q-point moves between C
and D on the load curve. For the
input/output characteristics we
equate two drain current equation
K
D
[2(V
GSD
- V
TND
)V
DSD
- V
DSD
2
] = K
L
(V
DSL
-
V
TNL
)
2
Which becomes
K
D
/K
L
[2(V
I
-V
TND
)V
O
-V
o
2
]=-(-V
TNL
)
2
Implies that input and output voltages are
not linear in this region.
5
VT Characteristics of NMOS Inverter with
Depletion Load
The Figure demonstrate in present configuration more abrupt
VTC transition region can be achieved even though the W/L
ratio for the output MOSFET is small.
Transient Analysis of NMOS inverters
The source of
capacitance C
T2
and C
T3
are the transistor input
capacitances and
parasitic capacitances
due to interconnect lines
between the inverter
stages.
The constant current
over a wide range of VDS
provided by the depletion
load implies that this
type of inverter switch a
capacitive load more
rapidly than the other
two types inverter
configurations.
The rate at
Transient Analysis of NMOS inverters (cont.)
The fall time relatively
short, because the load
capacitor discharges
through the large driver
transistor.
The raise time is longer
because the load
capacitor is charged by
the current through the
smaller load transistor.
(W/L)
L
=1
(W/L)
D
=4
F-0.5pF
6
depletion load enhancement load
1160W 825W
200W
7
16.2: NMOS Logic Circuit
NMOS logic circuits are constructed by
connecting driver transistor in parallel,
series or series-parallel combinations
to produce required output logic
function
NMOS NOR gate
NMOS NOR gate can be constructed by
connecting an additional driver transistor
in parallel with a depletion load inverter.
The output of a NOR gate is only high
when both inputs are at logic 0(low)i.e.
If A=B=logic 0,
Then both driver transistors M
DA
and M
DB
are in cut off mode and
V
0
=V
DD
(logic 1)
For all other possible inputs V
0
= 0 (logic 0).
For example,
If A=high (logic1) and B=low (logic0)
Then M
DB
is in cut off mode and remaining
circuit behave as depletion load inverter.
However, when both driver transistors
are in active mode the value of the output
voltage logic 0) is changed.
NMOS NOR gate: Special case when all
inputs are at logic 1
When A=B=logic 1
Both driver transistors are switched into nonsaturation region
and load transistor is biased in saturation region. We have
iDL=iDA+iDB
By substituting the values of current equation we can write as,
KL(VGSL-VTNL)
2
= KDA[2(VGSA - VTNA)VDSA - VDSA
2
] + KDB[2(VGSB
-VTNB)VDSB - VDSB
2
]
Suppose two driver transister are identical, which implies that,
KDA=KDB=KD
VTNA=VTNB=VTND
As we know VGSL=0
Also from figure VGSA=VGSB=VDD
VDSA=VDSB=V0
By substituting all these parameters we can write above equation as,
(-VTNL)
2
= 2(KD/KL)[2(VDD-VTND)V0-VO
2
)
Conclusion: The above equation suggested that when the both the
driver are in conducting mode, the effective aspect ratio of the
NOR gate is double. This further suggested that output voltage
becomes slightly smaller when both inputs are high. Because
higher the aspect ratio lower the output.
Concept of effective width to length ratios
For the NOR gate the effective
width of the drivers transistors
doubles. That means the effective
aspect ratio is increased.
For the NAND gate the effective
length of the driver transistors
doubles. That means the effective
aspect ratio is decreased.
.
Parallel combination
Series combination
8
At present, complementary MOS or CMOS has replaced NMOS at all
level of integration, in both analog and digital applications.
The basic reason of this replacement is that the power dissipation in
CMOS logic circuits is much less than in NMOS circuits, which makes
CMOS very attractive.
Although the processing is more complicated for CMOS circuits than
for NMOS circuits.
However, the advantages of CMOS digital circuits over NMOS circuits
justify their use.
CMOS: the most abundant devices on earth
Full rail-to-rail swing high noise margins
Logic levels not dependent upon the relative device sizes
transistors can be minimum size ratio less
Always a path to V
dd
or GND in steady state low
output impedance (output resistance in k range)
large fan-out.
Extremely high input resistance (gate of MOS transistor
is near perfect insulator) nearly zero steady-state
input current
No direct path steady-state between power and ground
no static power dissipation
Propagation delay function of load capacitance and
resistance of transistors
CMOS properties
16.3.1:p-Channel MOSFET
Revisited
In p-channel enhancement
device. A negative gate-to-
source voltage must be
applied to create the
inversion layer, or channel
region, of holes that,
connect the source and
drain regions.
The threshold voltage V
TP
for p-channel enhancement
load device is always negative
and positive for depletion-
mode PMOS.
Cross-section of p-channel enhancement mode
MOSFET
The operation of the p-channel is same as the n-channel device , except that the
hole is the charge carrier, rather than the electron, and the conventional current
direction and voltage polarities are reversed.
Simplified cross section of a CMOS
inverter
In the fabrication process, a separate p-well region is
formed within the starting n-substrate.
The n-channel MOSFET is fabricated in the p-well region
and p-channel MOSFET is fabricated in the n-substrate.
9
CMOS Inverter:
Steady State Response
V
DD
R
n
V
out
= 0
V
in
= V
DD
V
DD
R
p
V
out
= 1
V
in
= 0
V
OL
= 0
V
OH
= V
DD
Voltage Transfer Curve
CMOS Inverter Load Lines
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
I
D
n
(
A
)
V
out
(V)
X 10
-4
V
in
= 1.0V
V
in
= 1.5V
V
in
= 2.0V
V
in
= 2.5V
0.25um, W/L
n
= 1.5, W/L
p
= 4.5, V
DD
= 2.5V, V
Tn
= 0.4V, V
Tp
= -0.4V
V
in
= 0V
V
in
= 0.5V
V
in
= 1.0V
V
in
= 1.5V
V
in
= 0.5V
V
in
= 2.0V
V
in
= 2.5V V
in
= 2.5V
V
in
= 2V V
in
= 2V
V
in
= 1.5V V
in
= 1.5V
V
in
= 1V V
in
= 1V
V
in
= 0.5V V
in
= 0.5V
V
in
= 0V V
in
= 0V
PMOS NMOS
NMOS off
PMOS in non sat
NMOS in sat
PMOS in non
sat
NMOS in sat
PMOS in sat
NMOS in non
sat
PMOS in sat
NMOS in
nonsat
PMOS off
DC analysis of the CMOS inverter
The figure shows series
combination of a CMOS
inverter.
To form the input, gate
of the two MOSFET are
connected.
To form the output, the
drains are connected
together.
V
I
V
o
1 0
0 1
The transistor K
N
is also known as pull down
Device, it is pulling the output voltage down towards ground.
The transistor K
P
is known as the pull up device because it is
pulling the output voltage up towards V
DD
. This property speed
up the operation considerably.
It is to be noted that the static power dissipation during both extreme cases
(logic 1 or 0) is almost zero because i
Dp
=i
Dn
=0.
7
CMOS inverter in either high or low
state (ideal case)
Ideally, the power
dissipation of the CMOS
inverter is zero.
However, real CMOS
inverter exhibits a very
small power dissipation in
the nanowatt range
rather than in the
milliwatt rang of NMOS
inverter.
1
10
Different biasing conditions for a CMOS
inverter.
Case I: when NMOS is biased in saturation
region and PMOS is biased in nonsaturation
region.
The above condition can be achieved when
NMOS just start to conduct (V
I
=V
TN
). Under
this condition we can write,
i
DN
=i
DP
K
N
[V
GSN
-V
TN
]
2
=K
P
[2(V
GSP
+V
TP
)V
SDP
-V
SDP
2
)]
In terms of input output voltage we can write,
K
N
[V
I
-V
TN
]
2
=K
P[
2(V
DD
-V
I
+V
TP
)V
DD
-V
O
)-(V
DD
-V
O
)
2
]
Transition points for PMOS and NMOS
As we know transition point for
the PMOS can be define as,
V
SDP
(sat)=V
SGP
+V
TP
Or
V
OPt
=V
IPt
-V
TP
Or
V
OPt
=V
IPt
+|V
TP
|
Similarly, the transition point
for NMOS can be written as
V
DSN
(sat)=V
GSN
-V
TN
or
V
oNt
=V
INT
-V
TN
Biasing conditions for the CMOS
inverter (cont.)
Case II:
When both transistors are biased
in the saturation region.
i
DN
=i
DP
K
N
[V
GSN
-V
TN
]
2
=K
P
(V
GSP
+V
TP
)
2
In terms of input output voltage we
can write,
K
N
[V
I
-V
TN
]
2
=K
P
(V
DD
-V
I
+V
TP
)
2
The input voltage can be determine
by simplifying above equation as,
The above eq. can also be used to
determine input voltage at the
transition points.
P
N
TN
P
N
TP DD
It I
K
K
V
K
K
V V
V V
+
+ +
= =
1
Both are in
Saturation
region
Symmetrical properties of the
CMOS inverter
CMOS inverter design consideration
The CMOS inverter usually design to have,
(i)V
TN
=|V
TP
|
(ii) K
n
(W/L)=K
p
(W/L)
But K
n
> K
p
(because
n
>
p
)
How equation (ii) can be satisfied?
This can achieved if width of the PMOS is made two or
three times than that of the NMOS device. This is
very important in order to provide a symmetrical
VTC, results in wide noise margin.
8
11
CMOS inverter VTC
V
CC
V
CC
V
in
V
out
k
p
=k
n
k
p
=5k
n
k
p
=0.2k
n
Increase W of PMOS
k
p
increases
VTC moves to right
Increase W of NMOS
k
n
increases
VTC moves to left
For V
TH
= Vcc/2
k
n
= k
p
W
n
2W
p
Effects of V
It
adjustment
Result from changing k
p
/k
n
ratio:
Inverter threshold V
It
Vcc/2
Rise and fall delays unequal
Noise margins not equal
Reasons for changing inverter threshold
Want a faster delay for one type of transition
(rise/fall)
Remove noise from input signal: increase one
noise margin at expense of the other
12
CMOS inverter currents
When the output of a
CMOS inverter is either
at a logic 1 or 0, the
current in the circuit is
zero.
When the input voltage
is in the range
V
TN
<V
I
<V
TP
Both transistors are
conducting and a
current exists in the
inverter.
When NMOS transistor is biased in
the saturation region
When NMOS transistor is
biased in the saturation
region, the current in the
inverter is controlled by V
GSN
(why?).
Under this condition we can
write,
I
DN
=i
DP
=K
N
[V
GSN
-V
TN
]
2
By taking the square root
both sides, we can write,
i
DM
=i
DP
=K
N
(V
I
-V
TN
)
The above equation showed
that as long as NMOS
transistor is biased in the
saturation region the square
root of the CMOS inverter
current is linear function of
the input voltage.
When PMOS transistor is biased in the
saturation region
When PMOS transistor is biased in
the saturation region, the current in
the inverter is controlled by V
SGP
(why?).
Under this condition we can write,
I
DN
=i
DP
=K
P
[V
GSP
+V
TP
]
2
I
DN
=i
DP
=K
P
[V
DD
-V
I
+V
TP
]
2
By taking the square root both
sides, we can write,
i
DM
=i
DP
=K
P
(V
DD
-V
I
+V
TP
)
The above equation showed that as
long as PMOS transistor is biased in
the saturation region the square
root of the CMOS inverter current
is linear function of the input
voltage.
At the switching point, both transistors are biased in the saturation
region. It is to be noted that the actual current characteristic does not
have a sharp discontinuity.
IDt =
Power Dissipation
Although there isn't power dissipation in the
CMOS inverter when the output is either at
logic 0 or 1. However, during switching of the
CMOS inverter from low logic 0 to logic 1,
current flows and power is dissipated.
Usually CMOS inverter and logic circuit are
used to drive other MOS devices by
connecting a capacitor across the output of a
CMOS inverter.
This capacitor must be charged and
discharged during the switching cycle.
13
NMOS Transistor Capacitances: Triode
Region
C
ox
= Gate-channel
capacitance per unit
area(F/m
2
).
C
GC
= Total gate channel
capacitance.
C
GS
= Gate-source
capacitance.
C
GD
= Gate-drain
capacitance.
C
GSO
and C
GDO
= overlap
capacitances (F/m).
NMOS Transistor Capacitances:
Saturation Region
Drain no longer connected to
channel
NMOS Transistor Capacitances: Cutoff
Region
Conducting channel
region completely gone.
C
GB
= Gate-bulk
capacitance
C
GBO
= gate-bulk
capacitance per unit
width.
CMOS Inverter:
Switch Model of Dynamic Behavior
V
DD
R
n
V
out
C
L
V
in
= V
DD
V
DD
R
p
V
out
C
L
V
in
= 0
Gate response time is determined by the time to charge C
L
through R
p
(discharge C
L
through R
n
)
CMOS inverter power
Power has three components
Static power: when input isnt switching
Dynamic capacitive power: due to
charging and discharging of load
capacitance
Dynamic short-circuit power: direct
current from V
DD
to G
nd
when both
transistors are on
CMOS inverter static power
Static power consumption:
Static current: in CMOS there is no static current
as long as V
in
< V
TN
or V
in
> V
DD
+V
TP
Leakage current: determined by off transistor
Influenced by transistor width, supply voltage,
transistor threshold voltages
V
DD
V
I
<V
TN
I
leak,n
Vcc V
DD
I
leak,p
Vo(low)
V
DD
14
Dynamic Capacitive Power and energy stored in
the PMOS device
Case I: When the input is at logic 0: Under this
condition the PMOS is conducting and NMOS is in
cutoff mode and the load capacitor must be charged
through the PMOS device.
Power dissipation in the PMOS transistor is given by,
P
P
=i
L
V
SDp
= i
L
(V
DD
-V
O
)
The current and output voltages are related by,
i
L
=C
L
dv
O
/dt
Similarly the energy dissipation in the PMOS device can
be written as the output switches from low to high ,
Above equation showed the energy stored in the
capacitor C
L
when the output is high.
2
2
0
2
0
0 0 0 0
2
1
) 0
2
( ) 0 ( ,
2
, ) (
DD L P
DD
L DD DD L P
V
O
L
V
O DD L P
O
V
O L
V
O DD L P
O
O DD L P P
V C E
V
C V V C E C V C E
d C d V C E dt
dt
d
V C P E
DD
DD
DD DD
=
= =
= = =

Power Dissipation and Total Energy Stored

in the CMOS Device
Case II: when the input is high and out put is low:
During switching all the energy stored in the load
capacitor is dissipated in the NMOS device
because NMOS is conducting and PMOS is in
cutoff mode. The energy dissipated in the NMOS
inverter can be written as,
The total energy dissipated during one switching
cycle is,
The power dissipated in terms pf frquency can be
written as
2
2
1
DD L N V C E =
2 2 2
2
1
2
1
DD L DD L DD L N P T
V C V C V C E E E = + = + =
2
DD L T
T
T
V fC fE P
t
E
P t P E = = =
This implied that the power dissipation in the CMOS inverter is directly
proportional to switching frequency and V
DD
2
Dynamic capacitive power
Formula for dynamic power:
Observations
Does not (directly) depend on device sizes
Does not depend on switching delay
Applies to general CMOS gate in which:
Switched capacitances are lumped into C
L
Output swings from Gnd to V
DD
Input signal approximated as step function
Gate switches with frequency f
f V C P
DD L dyn
2
=
Dynamic short-circuit power
Short-circuit current flows from V
DD
to Gnd
when both transistors are on saturation mode
Plot on VTC curve:
V
CC
V
CC V
in
V
out
I
D
I
max
I
max
: depends on
saturation current
of devices
Inverter power consumption
Total power consumption
f V C Ptot
I V f
t t
I V f V C P
P P P P
CC L
leak CC
f r
CC CC L tot
stat sc dyn tot
2
max
2
~
2
+

+
+ =
+ + =
Power reduction
Reducing dynamic capacitive power:
Lower the voltage!
Quadratic effect on dynamic power
Reduce capacitance
Short interconnect lengths
Drive small gate load (small gates, small fan-out)
Reduce frequency
Lower clock frequency -
Lower signal activity
f V C P
DD L dyn
2
=
15
Power reduction
Reducing short-circuit current:
Fast rise/fall times on input signal
Reduce input capacitance
Insert small buffers to clean up slow input
signals before sending to large gate
Reducing leakage current:
Small transistors (leakage proportional to
width)
Lower voltage
Concept of Noise
Margins
NM
L
=V
IL
-V
OL
(noise margin for low input)
NMH=V
OH
-V
IH
(noise margin for high input)
NM
L
=V
IL
-V
OLU
(noise margin for low input)
NMH=V
OHU
- V
IH
(noise margin for high input)
VI
At point V
IL
the NMOS is biased in the saturation region and
PMOS is biased in the nonsaturation region
Taking derivative with respect to V
I
yields
At V
IL

Assume CMOS is symmetrical i. e. K

N
=K
P

(1)
(2)
(3)
(4)
(5)
Substituting (5) into (1)
(6)
Noise Margins
equations
At point V
IH
the NMOS is biased in the nonsaturation region and
PMOS is biased in the saturation region
Taking derivative with respect to V
I
yields
(6)
(9)
(8)
(7)
Assume CMOS is symmetrical i. e. K
N
=K
P
(10)
Substituting (10) into (6)
Noise Margins
equations
(cont.)
Summary of the noise margin of a symmetrical
CMOS inverter
NM
L
= V
IL
- V
OLU
(noise margin for low input)
NMH = V
OHU
- V
IH
(noise margin for high input)
16
Summary of the noise margin of asymmetrical
CMOS inverter
NM
L
= V
IL
- V
OLU
(noise margin for low input)
NMH = V
OHU
- V
IH
(noise margin for high input)
4
CMOS Logic Circuits
Large scale integrated CMOS logic
circuits such as watched, calculators,
and microprocessors are constructed by
using basic CMOS NOR and NAND
gates. Therefore, understanding of
these basic gates is very important for
the designing of very large scale
integrated (VLSI) logic circuits.
7
CMOS NOR gate
CMOS NOR gate can be
constructed by using
two parallel NMOS
devices and two series
PMOS transistors as
shown in the figure. In
the CMOS NOR gate
the output is at logic 1
when all inputs are low.
For all other possible
inputs, output is low or
at logic 0.
8
17
CMOS NAND gate
In CMOS NAND
gate the output is
at logic 0 when all
inputs are high.
For all other
possible inputs,
output is high or
at logic 1.
How can we design CMOS NOR
symmetrical gate?
In order to obtained symmetrical
switching times for the high-to-low
and low-to-high output transitions,
the effective conduction (design)
parameters of the composite
PMOS and composite NMOS
device must be equal. For the
CMOS NOR gate we can write as,
K
CN
=K
CP
By recalling effective channel width
and effective channel length
concept, the effective conduction
parameter for NMOS and PMOS
for a CMOS NOR can be written
as,
Since K
n
~2K
p
p
p
N
n
L
W K
L
W K

2 2
2
2
p N
L
W
L
W

2
2
2
N P
L
W
L
W

8
or
This implies that in order to get the
symmetrical switching properties , the
width to length ratio of PMOS transistor
must be approximately eight times that
of the NMOS device.
For asymmetrical case switching time is longer
Concept of effective width to length ratios
Parallel combination
Series combination
Fan-In and Fan-Out
The Fan-in of a gate is the number of its
inputs. Thus a four input NOR gate has a
fan-In of 4.
Similarly, Fan-Out is the maximum number
of similar gates that a gate can drive while
remaining within guaranteed
specifications.
18
t
V
out
V
in
input
waveform
output
waveform
t
p
= (t
pHL
+ t
pLH
)/2
Propagation delay
t
50%
t
pHL
50%
t
pLH
t
f
90%
10%
t
r
signal slopes
V
in
V
out
The propagation delay t
p
of a gate defines how quickly
it responds to a change at its input(s).
Propagation Delay Definitions
Switching Time and Propagation
Delay Time
The dynamic performance of a
logic circuit family is
characterized by propagation
delay of its basic inverter. The
propagation delay time is
define as the average of low-
to-high propagation delay time
and the high-to-low
propagation delay time.
The propagation delay time is
directly proportional to the
switching time and increases
as the Fan-out increases.
Therefore, the maximum Fan-
out is limited by the maximum
acceptable propagation delay
time.
Each additional load gate increases the load capacitance their must be
charge and discharge as the driver gate changes state. This place a
practical limit on the maximum allowable number of load gates.
Inverter Transient Response (input step pulse)
-0.5
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5
V
in
V
o
u
t
(
V
)
t (sec)
x 10
-10
V
DD
=2.5V
0.25m
W/L
n
= 1.5
W/L
p
= 4.5
R
eqn
= 13 k ( 1.5)
R
eqp
= 31 k ( 4.5)
t
pHL
= 36 psec
t
pLH
= 29 psec
so
t
p
= 32.5 psec
t
f
t
r
t
pHL
t
pLH
From simulation: t
pHL
= 39.9 psec and t
pLH
= 31.7 psec
Propagation Delay Estimate
The two modes of capacitive
charging/discharging that contribute to
propagation delay
Switch-level model
Delay estimation using switch-
level model (for general RC
circuit):
R
n C
L
[ ]

= =
= =
= =
= =

0
1
0 1
0 1
ln ) ln( ) ln(


1
0
V
V
RC V V RC t
dV
V
RC
t t t
dV
V
RC
dt
R
V
I
dV
I
C
dt
dt
dV
C I
p
V
V
p
Switch-level model
For fall delay t
phl
, V
0
=V
cc
, V
1
=V
cc
/2
L p plh
L n phl
p
CC
CC
p
C R t
C R t
RC t
V
V
RC
V
V
RC t
69 . 0
69 . 0
) 5 . 0 ln(
ln ln
2
1
0
1
=
=
=

=
Standard RC-delay
equations
19
Transmission Gates
Use of transistors as
switches are called
transmission gates because
switches can transmit
information from one circuit
to another.
NMOS transmission gate as an
open switch.
The figure shows NMOS
transmission gate. The
transistor in the gate can
conduct current in either
direction. The bias
applied to the
transistor determines
which terminal acts as the
drain and which terminal
acts as the source.
When gate voltage =0
The n-channel transistor is
cut off and the transistor
acts as an open switch
Characteristics of NMOS transmission gate (at high
input)
If =V
DD
, V
I
=V
DD
, and initially, the output V
0
is 0
and
capacitance C
L
is fully discharged.
Under these conditions, the terminal a acts as the
drain because its bias is VDD, and terminal b
acts as the source because its bias is 0.
The gate to source voltage can be written as
V
GS
=-V
O
or
V
GS
= V
DD
-V
O
As C
L
charges up and Vo increases, the gate to
source voltage decreases. When the gate to
source voltage V
GS
become equal to threshold
voltage V
TN
, the capacitance stop charging and
current goes to zero.
This implies that the
V
O
=V
O
(max) when V
GS
=V
TN
Or
V
O
(max) = V
DD
-V
TN
d
S
G
This implies that output voltage never will be equal to V
DD
. ; rather it will be lower by V
TN
.
This is one of the disadvantage of an NMOS transmission gate when VI=high
Characteristics of NMOS
transmission gate (at low input)
When V
I
=0 and =V
DD
and V
O
=V
DD
-V
TN
at t=o (initially).
It is to be noted that in the present case
terminal b acts as the drain and terminal
a acts as the source.
Under these conditions the gate to source
voltage is,
V
GS
=-V
I
V
GS
=V
DD
-o
v
GS=
v
DD
This implies that value of V
GS
is constant.
In this case the capacitor is fully
discharge to zero as the drain current
goes to zero.
V
O
=0
This implies that the NMOS transistor
provide a good logic 0 when V
I
=low
V
DD
-V
t
G
S
D
source
drain
gate
Why NMOS transmission gate does not remain in
a static condition?
The reverse leakage
current due to reverse
bias between terminal
b and ground begins
to discharge the
capacitor, and the
circuit does not
remain in a static
condition.
V
DD
-V
t
source
drain
gate
20
V
O
(max) = V
DD
-V
TN