Solutions to Assignment #5

Chapter 7



1 (a) From the DFG we get:

=
0
1
,
1
1
,
1
0
h y x
e e e

The two conditions to be satisfied for the scheduling and the projection vector to be
permissible are:


, 0
, 0

e S
d S
T
T

for all dependence vectors e.
Verifying these conditions we get the following for each of the cases:

(i) [ ] [ ]

= = =
1
0
0 1 0 1 p d S
T T



e p
T
e S
T

x
e 1 0
y
e 1 1
h
e 0 1

In this case

0
1

=
e S All
d S
T
T
Thus this case is permissible.
(ii) [ ] [ ]

= = =
2
1
1 2 2 1 p d S
T T

[ ] 0
1
2
2 1 =

= d S Since
T
, this case is not permissible.
(iii) [ ] [ ]

= = =
1
0
0 1 1 1 p d S
T T



e p
T
e S
T

x
e 1 1
y
e
1 2
h
e 0 1

In this case

0
1

=
e S All
d S
T
T
Thus this case is permissible.
(iv) [ ] [ ]

= = =
1
0
0 1 2 1 p d S
T T

In this case
[ ] 1
0
1
2 1 =

= d S
T
, [ ] 0 2
1
0
2 1 < =

= is e S
x
T

[ ] 0 1
1
1
2 1 < =

= is e S
y
T
, [ ] 1
0
1
2 1 =

=
h
T
e S
Since 0 < e S
T
for e=

1
0
and e=

1
1
this case is not permissible. Note that these edges
cannot be simply reversed to make 0 e S
T
since the functionality of the nodes in the
dependence graph are unknown and it is not clear if there are precedence constraints
along the edges.

(b) The systolic architectures for the permissible designs (i) and (iii) are given below.

P0 P1 P2
.........X
3
X
2
X
1
X
0
.........Y
3
Y
2
Y
1
Y
0
D
D
D D
D
h
0
h
1
h
2
D



Figure1. [ ] [ ]
T T
d S 0 1 0 1 = =

P0 P1 P2
.........X
3
X
2
X
1
X
0
.........Y
3
Y
2
Y
1
Y
0
D
2D
D D
2D
h
0
h
1
h
2
D D
2D
D


Figure2. [ ] [ ]
T T
d S 0 1 1 1 = =



9.

x0 x1 x2 x3 x4 x5
y4 y5 y6
i
j
w0
w1
w2
w3
w4



(a) We start by deriving the RIA as follows:


) 1 , ( ) , (
) , ( ) , ( ) 1 , 1 ( ) , (
) , 1 ( ) , (
=
+ + =
=
j i X j i X
j i H j i X j i Y j i Y
j i H j i H



The reduced graph is given by



The scheduling is done by applying the following formulae

H
(1 0)
Y
(1, -1)
X
(0,1)
(0,0)
(0,0)

x x y
T
T e S
s
s
S +

= ,
2
1

From the reduced graph we see that


4 :
0 :
0 :
0 :
0 :
2 1
2
1
+

+

+
Y Y
X Y
X X
H Y
H H
s s Y Y
Y X
s X X
Y H
s H H







If we use linear scheduling, (i.e. 0 = = =
Y X H
) and choose S
T
=(4 0) then it will
maximize the HUE (hardware utilization time)


(b)
If ( ) 4 / 1
1
0
0 4 ,
0
1
=

= =

= HUE p S d
T



e p
T
e S
T

x
e 1 0
y
e -1 4
h
e 0 4

The systolic architecture for the design is given below.



Figure 3. [ ] [ ]
T T
d S 0 1 0 4 = =


(c)
If ( ) 4 / 1
1
1
0 4 ,
1
1
=

= =

= HUE p S d
T


P0 P1 P2
Y :Y0 Y1 Y2 Y3........
4D
4D 4D
w1 w2
4D 4D
P3
4D
w3
4D
P4
4D
w4
4D
w0
X


e p
T
e S
T

x
e 1 0
y
e 0 4
h
e 1 4


The systolic architecture for the design is given below.

P0 P1 P2
4D
4D 4D
Y Y
4D 4D
P3
4D
Y
4D
P4
4D
Y
4D
Y
w4 w3 w2 w1 w0
X



Figure 4. [ ] [ ]
T T
d S 1 1 0 4 = =

10.
i
j


The dependence vectors are given by:

=
1
0
,
0
2
,
0
1
h y x
e e e

(a) Since there is a delay on each edge, we can choose [ ]
T
S 1 1 =
[ ] [ ]

= = =
0
1
1 0 1 1 p d S
T T
HUE=1/S
T
d =1


e p
T
e S
T
x
e 1 1
y
e 2 2
h
e 0 1


The systolic architecture for the design is given below.



Figure 5. [ ] [ ]
T T
d S 1 0 1 1 = =
(b) If ( )

= =

=
1
1
1
1
1 1 ,
1
1
p or p S d
T
choosing p=

1
1



e p
T
e S
T

x
e 1 1
y
e 2 2
h
e -1 1


The systolic architecture for the design is given below.

2D 2D 2D 2D 2D
X
Y
D
D D
D D
2D
h D
D D
D D
D
D

Figure 6. [ ] [ ]
T T
d S 1 1 1 1 = =



2D 2D 2D 2D 2D
X
Y
D D D
D D
h h h
h h
D
D D
D
15. Y(n) is defined by the following equation:

) 6 ( ) 4 ( ) 2 ( ) ( ) ( + + + = n dx n cx n bx n ax n y






In the given DG the inputs move along the j axis, the weights along the i axis, and
the outputs move along the diagonal. Note that the dependence vectors are given by:

=
0
1
,
1
2
,
1
0
h y x
e e e

(a) For such a filter the RIA is given by


) 1 , ( ) , (
) , ( ) , ( ) 1 , 2 ( ) , (
) , 1 ( ) , (
=
+ + =
=
j i X j i X
j i H j i X j i Y j i Y
j i H j i H


The reduced graph is given as

H
(1 0)
Y
(2, -1)
X
(0,0)
(0,0)
(0, 1)

x0 x1 x2 x3 x4 x5
y6
a
b
c
d
x6 x7
y7
y8
i
j

The scheduling is done by applying the following formulae


x x y
T
T e S
s
s
S +

= ,
2
1

From the reduced graph we see that


2 ) ( 2 :
0 :
0 :
0 :
0 :
2 1
2
1
+

+

+
Y Y
X Y
X X
H Y
H H
s s Y Y
Y X
s X X
Y H
s H H







If we use linear scheduling, (i.e. 0 = = =
Y X H
), some possible solutions are given
by:

=
1
2
S Or

=
2
2
S Or

=
0
1
S .

We choose S
T
=(1 0) since we need to reduce the number of delays in the systolic
architecture.

(b) If ( )

= =

=
1
0
0 1 ,
0
1
p S d
T

(c)
Then we have:


e p
T
e S
T
x
e 1 0
y
e -1 2
h
e 0 1

The systolic architecture for the design is given below.


P0 P1 P2
D
D D
b c
2D 2D
P3
D
d
2D
X
a
Y 2D


Figure 7. [ ] [ ]
T T
d S 0 1 0 1 = =

(d) For the above systolic architecture the Hardware Utilization Efficiency is

1
1
1 1
= =
d S
T


Hence the utilization is 100%