L16 Testbenches for

state machines

VHDL Language Elements

More examples

HDL coding of class examples

Testbench for example

Testing of examples testbench construction

Note trade off and difference in Mealy vs Moore

implementation from simulation results

Constructing simple testbenches general rules

Ref: text Unit 10, 17, 20

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More examples

Consider the state machine we designed earlier for

detecting an input that ends in the sequence 101.
Developed both Mealy and Moore implementations.

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Now translate these to VHDL

The ENTITY the same ports

ENTITY mealy101 IS
PORT (clk,x : IN bit; z : OUT bit);
END mealy101;
ENTITY moore101 IS
PORT (clk,x : IN bit; z : OUT bit);
END moore101;

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Start the architecture

The declarative region

ARCHITECTURE one OF mealy101 IS

TYPE state_type IS (s0,s1,s2);
SIGNAL state,next_state : state_type;
BEGIN
ARCHITECTURE one OF moore101 IS
TYPE state_type IS (s0,s1,s2,s3);
SIGNAL state,next_state : state_type;
BEGIN

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The F/F process

The state elements

--state elements mealy

PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
END PROCESS;

--state elements moore

PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
END PROCESS;

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The next state processes Mealy

--next state logic mealy

PROCESS (state,x)
BEGIN
CASE state IS
WHEN s0 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s1;
END IF;
WHEN s1 => IF (x='0') THEN next_state <= s2;
ELSE next_state <= s1;
END IF;
WHEN s2 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s1;
END IF;
END CASE;
END PROCESS;

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The next state process Moore

PROCESS (state,x)
BEGIN
CASE state IS
WHEN s0 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s1;
END IF;
WHEN s1 => IF (x='0') THEN next_state <= s2;
ELSE next_state <= s1;
END IF;
WHEN s2 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s3;
END IF;
WHEN s3 => IF (x='0') THEN next_state <= s2;
ELSE next_state <= s1;
END IF;
END CASE;
END PROCESS;

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The output logic - Mealy

-- output logic - mealy machine

PROCESS (state,x)
BEGIN
CASE state IS
WHEN s0 => z<='0';
WHEN s1 => z<='0';
WHEN s2 => IF (x='1') THEN z<='1';
ELSE z<= '0';
END IF;
END CASE;
END PROCESS;

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The output logic - Moore

--output logic - Moore machine

PROCESS (state)
BEGIN
CASE state IS
WHEN s0 => z <= '0';
WHEN s1 => z <= '0';
WHEN s2 => z <= '0';
WHEN s3 => z <= '1';
END CASE;
END PROCESS;

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Creating a testbench

Start with the ENTITY

As the testbench is the top unit there is no interface.

Process within testbench generate stimulus and possibly
check response and generate reports.
ENTITY tb101 IS
END tb101;

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Declarations

The declrative region declare DUTs

ARCHITECTURE one OF tb101 IS

--declare units to be tested
COMPONENT mealy101
PORT (clk,x : IN bit; z : OUT bit);
END COMPONENT;
FOR all : mealy101 USE ENTITY work.mealy101(one);
COMPONENT moore101
PORT (clk,x : IN bit; z : OUT bit);
END COMPONENT;
FOR all : moore101 USE ENTITY work.moore101(one);

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Declarative Region

Declare signal to connect to DUT

BOTH stimulus and response

-- delcare input signals and input stream

SIGNAL xs : BIT_VECTOR (1 to 30) :=
('0','0','0','1','0','1','0','0','0','1','0','1','0','1','0','1',
'0','0','0','1','0','1','1','0','1','1','1','0','1','0');
SIGNAL x,z1,z2 : BIT;
SIGNAL clk : BIT :='1';

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Wire in DUT

Instantiate components

BEGIN
--Instantiate units
ml : mealy101 PORT MAP (clk,x,z1);
mo : moore101 PORT MAP (clk,x,z2);

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Set up clocks

Set up a 50% duty cycle clock

--Set up clock
clk <= NOT clk AFTER 5 ns;

50% duty cycle clock is easy as above

More complex clocks can be set up

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More complex clocks

Use a process

PROCESS -- clk starts set high

BEGIN
clk <= 1;
WAIT FOR 5 ns; -- time high
clk <= 0;
WAIT FOR 15 ns; --time low
END PROCESS;

This is a 25% duty cycle clock the is high 25% of the

period. Easy to adapt for any duty cycle and clock
period.

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The stimulus process

--Stimulus process
PROCESS
BEGIN
WAIT FOR 1 ns;
FOR i IN 1 to 30 LOOP
x <= xs(i);
WAIT FOR 10 ns;
END LOOP;
WAIT FOR 10 ns;
WAIT;
END PROCESS;

Process grabs inputs from the input vector set up in the declarative region.
A good option when a simple sequence on a single signal.
More advanced techniques may be needed for complex machines.

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The simulation result

The waveform note clock edge versus X valid

time. ('0','0','0','1','0','1','0','0','0','1','0','1','0','1','0','1,'0','0','0','1','0','1','1','0','1','1','1','0','1','0');

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Simulation result 2

If timing of clock edge versus input X is

shifted output can be different

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Demo of simulation

A look at a live demonstration of Model Sim

for simulation of this machine.
Note that in Moore implementation output
seems to be delayed ~1 clock.

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Lecture summary

HDL from code to simulation

For the 101 sequence detector

Testbench for the sequence detector

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