Electrical Engg

1) Transistors:
Transisttor operation
Biploar trransistor:
A transistor is basically a Si on Ge crysttal
containing three separate
e regions. It can
n be
either NPN
N or PNP type fig.
f 1. The midd
dle
region is ca
alled the base and
a the outer two
t
regions are
e called emitterr and the collec
ctor.
The outer layers although
h they are of sa
ame
type but the
eir functions ca
annot be chang
ged.
They have different physical and electric
cal
properties.
In most transistors, emitte
er is heavily do
oped.
Its job is to emit or inject electrons
e
into the
t
base. Thes
se bases are lig
ghtly doped and
very thin, itt passes most of
o the emitterinjected ele
ectrons on to th
he collector. Th
he
doping leve
el of collector is
s intermediate
between th
he heavy doping of emitter and the
light doping
g of the base.
The collecttor is so named
d because it
collects ele
ectrons from ba
ase. The collec
ctor is
the largest of the three regions; it must
dissipate more
m
heat than the emitter or
base. The transistor
t
has two
t
junctions. One
O
between em
mitter and the base
b
and otherr
between th
he base and the
e collector.
Because off this the transiistor is similar to
t
two diodes, one emitter diode and otherr
collector ba
ase diode.
Fig .1
When trans
sistor is made, the diffusion of
o free electrons
s across the jun
nction produce
es two depletion layers. For each of
these deple
etion layers, the barrier poten
ntial is 0.7 V forr Si transistor a
and 0.3 V for G
Ge transistor.
The depletion layers do not
n have the same width, beca
ause different rregions have d
different doping
g levels. The mo
ore
heavily dop
ped a region is, the greater th
he concentration of ions near tthe junction. T his means the depletion layer
penetrates more deeply in
nto the base an
nd slightly into emitter. Simila
arly, it penetratiion more into ccollector. The
thickness of
o collector dep
pletion layer is large while the base depletion
n layer is smalll as shown in fig. 2.
Fig. 2
If both the junctions
j
are fo
orward biased using two d.c sources,
s
as sho
own in fig. 3a. free electrons (majority carrie
ers)
enter the emitter and colle
ector of the transistor, joins at the base and come out of th
he base. Becau
use both the diodes
are forward
d biased, the emitter and colle
ector currents are
a large.
Fig. 3a
Fig. 3b
If both the junction

j
are rev
verse biased as
a shown in fig. 3b, then sma ll currents flow
ws through both
h junctions onlyy due
to thermally
y produced min
nority carriers and
a surface lea
akage. Therma
ally produced ca
arriers are tem
mperature dependent
it approxim
mately doubles for
f every 10 de
egree celsius rise in ambient ttemperature. T
The surface lea
akage current
increases with
w voltage.
When the emitter
e
diode is
s forward biase
ed and collector diode is reverrse biased as sshown in fig. 4 then one expe
ect
large emitte
er current and small collectorr current but co
ollector current is almost as la
arge as emitter current.
Fig. 4
When emittter diodes forw
ward biased and
d the applied voltage
v
is more than 0.7 V (ba
arrier potential)) then larger nu
umber
of majority carriers (electrrons in n-type) diffuse across the junction.
Once the electrons
e
are injected by the emitter
e
enter intto the base, the
ey become min
nority carriers. These electron
ns do
not have se
eparate identities from those, which are therrmally generate
ed, in the base
e region itself. T
The base is ma
ade
very thin an
nd is very lightlly doped. Beca
ause of this only
y few electronss traveling from
m the emitter to
o base region
recombine with holes. This gives rise to recombination
n current. The rrest of the elecctrons exist for more time. Since the
collector diode is reverse biased, (n is connected
c
to po
ositive supply) ttherefore mostt of the electron
ns are pushed into
collector layer. These collector elections
s can then flow
w into the extern
nal collector lea
ad.
Thus, there
e is a steady sttream of electro
ons leaving the
e negative sourrce terminal an
nd entering the emitter region.. The
VEB forward
d bias forces th
hese emitter ele
ectrons to ente
er the base reg ion. The thin and lightly dope
ed base gives a
almost
all those electrons enough lifetime to difffuse into the depletion layer. The depletion layer field pushes a steady sstream
of electron into the collecttor region. The
ese electrons le
eave the collecttor and flow intto the positive tterminal of the
voltage sou
urce. In most trransistor, more
e than 95% of th
he emitter injeccted electrons flow to the collector, less than
n 5%
fall into bas
se holes and flo
ow out the exte
ernal base lead
d. But the collecctor current is less than emittter current.
Relation between
b
different currentss in a transisttor:
The total cu
urrent flowing into the transisttor must be equal to the total current flowing
g out of it. Hence, the emitterr
current IE is
s equal to the sum
s
of the colle
ector (IC ) and base
b
current (I B). That is,
IE = IC + IB
The curren
nts directions arre positive directions. The tota
al collector currrent IC is made
e up of two com
mponents.
1. The frac
ction of emitter (electron) curre
ent which reaches the collecttor ( dc IE )
2. The norm
mal reverse lea
akage current ICO
dc is know
wn as large sign
nal current gain
n or dc alpha. It is always possitive. Since co llector current is almost equa
al to
the IE there
efore dc IE varries from 0.9 to
o 0.98. Usually, the reverse le
eakage current is very small ccompared to the
e total
collector cu
urrent.
NOTE: The
e forward bias on the emitter diode controls the number off free electrons infected into th
he base. The la
arger
(VBE) forwa
ard voltage, the
e greater the nu
umber of injecte
ed electrons. T
The reverse bia
as on the collecctor diode has little
influence on
o the number of
o electrons tha
at enter the collector. Increas ing VCB does n
not change the number of free
e
electrons arriving
a
at the collector
c
junctio
on layer.
The symbo
ol of npn and pn
np transistors are
a shown in fig. 5.
Fig. 5
Breakdow
wn Voltages:
Since the tw
wo halves of a transistor are diodes, two mu
uch reverse vo
oltage on eitherr diode can cau
use breakdown
n. The
breakdown
n voltage depen
nds on the widtth of the deplettion layer and tthe doping leve
els. Because off the heavy dop
ping
level, the emitter
e
diode ha
as a low breakd
down voltage approximately
a
5 to 30 V. The collector diode
e is less heavilyy
doped so itts breakdown voltage
v
is highe
er around 20 to
o 300 V.
Configurrations: M- Bipolar juncction transisttors

Common Base Amplifiier:
The comm
mon base amplifier circuit is sh
hown
in Fig. 1. The
T VEE source
e forward biase
es the
emitter dio
ode and VCC so
ource reverse biased
b
collector diode.
d
The ac source
s
vin is
connected
d to emitter thro
ough a coupling
g
capacitor so
s that it blocks
s dc. This ac voltage
produces small fluctuatio
on in currents and
a
voltages. The
T load resisttance RL is also
o
connected
d to collector through coupling
g
capacitor so
s the fluctuation in collector base
voltage will be observed across RL.
The dc equivalent circuit is obtained by
y
reducing all
a ac sources to zero and ope
ening
all capacittors. The dc collector current is
same as IE and VCB is giv
ven by
VCB = VCC - IC RC.
Fig
g. 1
These currrent and voltage

e fix the Q poin
nt. The ac equivalent circuit iss obtained by re
educing all dc sources to zero
o and
shorting all coupling capa
acitors. r'e repre
esents the ac re
esistance of th e diode as sho
own in Fig. 2.
Fig. 2
Fig. 3, shows the diode curve
c
relating IE and VBE. In th
he absence of a
ac signal, the trransistor opera
ates at Q point (point
of intersecttion of load line
e and input cha
aracteristic). Wh
hen the ac sign
nal is applied, tthe emitter currrent and voltag
ge also
change. If the
t signal is sm
mall, the operatting point swing
gs sinusoidallyy about Q point (A to B).
Fig .3
If the ac sig
gnal is small, th
he points A and
d B are close to
o Q, and arc A B can be apprroximated by a straight line an
nd
diode appe
ears to be a res
sistance given by
If the input signal is small, input voltage and current wiill be sinusoida
al but if the inpu
ut voltage is larrge then curren
nt will
no longer be
b sinusoidal because of the non
n linearity off diode curve. T
The emitter currrent is elongatted on the positive
half cycle and
a compresse
ed on negative half cycle. The
erefore the outp
put will also be distorted.
r'e is the ratio of VBE and
d IE and its va
alue depends upon
u
the locatio
on of Q. Highe
er up the Q poin
nt small will be the
value of r' e because the same change in
i VBE produce
es large change
e in IE. The slop
pe of the curve
e at Q determin
nes the
value of r'e. From calculattion it can be proved that.
r'e = 25mV / IE
Proof
In general, the current thrrough a diode is given by
Where q is he charge on electron, V is the

t drop across
s diode, T is the
e temperature and K is a con
nstant.
On differen
ntiating w.r.t V, we get,
The value of
o (q / KT) at 25
5C is approxim
mately 40.
Therefore,
or,
To a close approximation the small chan

nges in collecto
or current equa
al the small cha
anges in emitte
er current. In th
he ac
equivalent circuit, the current iC' is show
wn upward beca
ause if ie' incre
eases, then iC' also increasess in the same
direction.
In general, the current thrrough a diode is given by
Where q is he charge on electron, V is the

t drop across
s diode, T is the
e temperature and K is a con
nstant.
On differen
ntiating w.r.t V, we get,
The value of
o (q / KT) at 25
5C is approxim
mately 40.
Therefore,
or,
To a close approximation the small chan

nges in collecto
or current equa
al the small cha
anges in emitte
er current. In th
he ac
equivalent circuit, the current iC' is show
wn upward beca
ause if ie' incre
eases, then iC' also increasess in the same
direction.
Voltage gain:
Since the ac
a input voltage
e source is con
nnected across r'e. Therefore, the ac emitterr current is give
en by
ie = Vin / r'e
or,
Vin = ie r'e
The outputt voltage is give

en by Vout = ic (RC || RL)
Under open
n circuit condition vout = ic Rc
Example--1
Find the vo
oltage gain and
d output of the amplifier
a
shown
n in fig. 4, if inp
put voltage is 1
1.5mV.
Fig. 4
Solution:
The emitter dc current I E is given by
Therefore, emitter ac resistance =

or,
AV= 56.6
and, Vout = 1.5 x 56.6 = 84

4.9 mV
Example--2
Repeat exa
ample-1 if ac so
ource has resis
stance R s = 10
00 W .
Solution:
The ac equ
uivalent circuit with
w ac source resistance is shown
s
in fig. 5 .
Fig. 5
The emitter ac current is given

g
by
or,
Therefore, voltage gain of the amplifier =
and,
Vout = 1.5 x 8.71 =13.1 mV
Common Emitter Curv

ves:
The common emitter conffiguration of BJ
JT is shown in fig. 1.
Fig. 1
In C.E. con
nfiguration the emitter
e
is made
e common to th
he input and ou
utput. It is also referred to as grounded emittter
configuratio
on. It is most co
ommonly used configuration. In this, base ccurrent and outtput voltages arre taken as
impendent parameters an
nd input voltage
e and output cu
urrent as depen
ndent parametters
VBE = f1 ( IB, VCE )
IC = f2( IB, VCE )
Input Cha
aracteristic:
The curve between IB and
d VBE for differe
ent values of VCE are shown i n fig. 2. Since the base emittter junction of a
transistor is
s a diode, there
efore the chara
acteristic is similar to diode on
ne. With higherr values of VCE collector gathe
ers
slightly more electrons an
nd therefore ba
ase current redu
uces. Normallyy this effect is n
neglected. (Earrly effect). Whe
en
collector is shorted with emitter

e
then the
e input characte
eristic is the ch
haracteristic of a forward biase
ed diode when VBE is
zero and IB is also zero.
Fig. 2
Output Characteristic:
The outputt characteristic is the curve be
etween VCE and
d IC for various values of IB. F
For fixed value of IB and is sho
own
in fig. 3. Fo
or fixed value of
o IB, IC is not va
arying much de
ependent on VCCE but slopes a
are greater than
n CE characterristic.
The outputt characteristics
s can again be divided into three parts.
Fig. 3
(1) Active Region:
In this regio
on collector jun
nction is reverse biased and emitter
e
junction
n is forward biased. It is the arrea to the right of
VCE = 0.5 V and above IB= 0. In this regiion transistor current
c
respond
ds most sensitivvely to IB. If tra
ansistor is to be
e used
as an ampllifier, it must op
perate in this re
egion.
If dc is trully constant then IC would be independent off VCE. But beca use of early eff
ffect, dc increa
ases by 0.1% (0
0.001)
e.g. from 0.995 to 0.996 as
a VCE increase
es from a few volts
v
to 10V. Th
hen dc increases from 0.995
5 / (1-0.995) = 200 to
0.996 / (1-0
0.996) = 250 orr about 25%. This
T
shows thatt small change in reflects la
arge change in . Therefore th
he
curves are subjected to la
arge variations for the same ty
ype of transisto
ors.
(2) Cut Offf:
Cut off in a transistor is given by IB = 0, IC= ICO. A trans
sistor is not at ccut off if the ba
ase current is simply reduced to
zero (open circuited) unde
er this condition,
IC = IE= ICO / ( 1-dc) = ICEO
O
The actual collector curre
ent with base op
pen is designated as ICEO. Sin
nce even in the
e neighborhood
d of cut off, ddc may
be as large
e as 0.9 for Ge,, then IC=10 ICO
ordingly in orde
er to cut off tran
nsistor
O(approximately), at zero bas e current. Acco
it is not eno
ough to reduce
e IB to zero, butt it is necessary
y to reverse bia
as the emitter junction slightlyy. It is found tha
at
reverse volltage of 0.1 V is
s sufficient for cut off a transis
stor. In Si, the dc is very nearly equal to zzero, therefore
e, IC =
ICO. Hence even with IB= 0, IC= IE= ICO so that transisto
or is very close to cut off.
In summary
y, cut off mean
ns IE = 0, IC = ICO
age whose mag
gnitude is of the
e
C , IB = -IC = -ICO
C , and VBE is a reverse volta
order of 0.1
1 V for Ge and 0 V for Si.
Reverse Collector
C
Saturration Currentt ICBO:
When in a physical transistor emitter current is reduced to zero, then the collector ccurrent is know
wn as
ICBO (appro
oximately equal to ICO). Reverrse collector sa
aturation curren
nt ICBOalso varie
es with temperrature, avalanch
he
multiplicatio
on and variability from sample
e to sample. Consider the circcuit shown in ffig. 4. VBB is the
e reverse volta
age
applied to reduce
r
the emiitter current to zero.
z
IE = 0,
IB = -ICBO
If we requirre, VBE = - 0.1 V

Then - VBBB + ICBO RB < - 0.1
0 V
Fig. 4
If RB = 100
0 K, ICBO = 100 m A, Then VBBB must be 10.1 Volts. Hence trransistor must be capable to withstand this
reverse volltage before breakdown voltage exceeds.
(3).Saturattion Region:
In this regio
on both the dio
odes are forwarrd biased by at least cut in vo
oltage. Since th
he voltage VBE a
and VBC acrosss a
forward is approximately
a
0.7 V therefore
e, VCE = VCB + VBE = - VBC+ V BE is also few ttenths of volts. Hence saturattion
region is ve
ery close to zerro voltage axis, where all the current rapidlyy reduces to ze
ero. In this regio
on the transisto
or
collector cu
urrent is approx
ximately given by VCC / R C an
nd independen t of base curre
ent. Normal tran
nsistor action iss last
and it acts like a small ohmic resistance
e.
Large Sig
gnal Current Gain
G
dc :The ratio Ic / IB is defined as transfer ratiio or large sign
nal current gain
n dc
Where IC is
s the collector current
c
and IB is the base currrent. The dc iss an indication if how well the transistor workks.
The typical value of dc va
aries from 50 to
o 300.
In terms of h parameters, dc is known as dc current gain
g
and in dessignated hfE ( dc = hfE). Kno
owing the maximum
collector cu
urrent and dc the minimum base
b
current ca
an be found wh
hich will be nee
eded to saturate
e the transistorr.
This expres
ssion of dc is defined
d
neglectting reverse lea
akage current ((ICO).
Taking reve
erse leakage current
c
(ICO) into
o account, the expression forr the dc can be
e obtained as fo
ollows:
dc in terms
s of dc is given
n by
Since, ICO = ICBO
Cut off of a transistor mea

ans IE = 0, then
n IC= ICBO and IB = - ICBO. Therrefore, the abo
ove expression dc gives the
collector cu
urrent incremen
nt to the base current
c
change
e form cut off to
o IB and hence it represents th
he large signal
current gain of all commo
on emitter trans
sistor.
Small sig
gnal analysiis of basic trransistor am
mplifier
Small Sign
nal CE Ampllifiers:
CE amplifie
ers are very po
opular to ampliffy the small signal ac. After a transistor has been biased w
with a Q point near
the middle of a dc load lin
ne, ac source can
c be coupled to the base. T
This produces ffluctuations in tthe base curren
nt and
hence in th
he collector current of the sam
me shape and frequency.
f
The
e output will be enlarged sine wave of same
frequency.
The amplifiier is called line
ear if it does no
ot change the wave
w
shape of the signal. As long as the inp
put signal is sm
mall,
the transisttor will use only
y a small part of
o the load line and the operattion will be line
ear.
On the othe
er hand, if the input signal is too
t large. The fluctuations alo
ong the load lin
ne will drive the
e transistor into
o
either saturration or cut offf. This clips the
e peaks of the input
i
and the a
amplifier is no lo
onger linear.
The CE am
mplifier configurration is shown
n in fig. 1.
Fig. 1
The couplin
ng capacitor (C
CC ) passes an ac signal from one point to a nother. At the ssame time it do
oes not allow th
he dc
to pass thro
ough it. Hence it is also called
d blocking capa
acitor.
Fig. 2
For example in fig. 2, the
e ac voltage at point
p
A is trans
smitted to pointt B. For this series reactance XC should be vvery
small comp
pared to series resistance RS. The circuit to the left of A ma
ay be a source
e and a series rresistor or mayy be
the Theven
nin equivalent of
o a complex ciircuit. Similarly RL may be the
e load resistancce or equivalen
nt resistance off a
complex ne
etwork. The current in the loop is given by
As frequency increases,
decreases, and
d current incre ases until it rea
aches to its ma
aximum value vin / R.
Therefore the
t capacitor couples the sign
nal properly fro
om A to B when
n XC<< R. The size of the cou
upling capacitor
depends up
pon the lowest frequency to be
b coupled. No
ormally, for lowe
est frequency XC 0.1R is ta
aken as design
n rule.
The couplin
ng capacitor ac
cts like a switch
h, which is ope
en to dc and sh orted for ac.
The bypass
s capacitor Cb is similar to a coupling
c
capac
citor, except tha
at it couples an
n ungrounded p
point to a groun
nded
point. The Cb capacitor lo

ooks like a shorrt to an ac signal and thereforre emitter is said ac grounded
d. A bypass
capacitor does
d
not disturb
b the dc voltage
e at emitter bec
cause it looks o
open to dc current. As a design rule
XCb 0.1RE at lowest freq
quency.
Analysis of
o CE amplifiier:
In a transis
stor amplifier, th
he dc source sets up quiesce
ent current and voltages. The ac source then
n produces
fluctuations
s in these curre
ent and voltage
es. The simples
st way to analyyze this circuit is to split the an
nalysis in two p
parts:
dc analysis
s and ac analys
sis. One can us
se superpositio
on theorem for analysis .
AC & DC
C Equivalent Circuits:
C
For dc equivalent circuit, reduce all ac voltage
v
sources
s to zero and o pen all ac curre
ent sources an
nd open all
capacitors. With this redu
uced circuit sho
own in fig. 3 dc
c current and vo
oltages can be calculated.
Fig. 3
For ac equivalent circuits reduce dc volttage sources to
o zero and ope
en current sourcces and short a
all capacitors. T
This
circuit is us
sed to calculate
e ac currents and voltage as shown
s
in fig. 4
4.
Fig. 4
The total cu
urrent in any branch is the su
um of dc and ac
c currents throu
ugh that branch
h. The total volltage across an
ny
branch is th
he sum of the dc
d voltage and ac voltage acrross that brancch.
Phase Inv
version:
Because off the fluctuation
n is base current; collector cu
urrent and colle
ector voltage also swings above and below tthe
quiescent voltage.
v
The ac
c output voltage
e is inverted with respect to th
he ac input voltage, meaning it is 180o out o
of
phase with input.
During the positive half cy
ycle base curre
ent increase, ca
ausing the colle
ector current to
o increase. Thiss produces a la
arge
voltage dro
op across the collector
c
resisto
or; therefore, the voltage outp ut decreases a
and negative ha
alf cycle of output
voltage is obtained.
o
Conv
versely, on the negative half cycle
c
of input vo
oltage less colllector current flows and the vvoltage
drop across the collector resistor decrea
ases, and henc
ce collector volttage increasess we get the po
ositive half cycle
e of
output volta
age as shown in fig. 5.
Fig. 5
Stabiliza
ation
Stability of
o Operating Point
Let us cons
sider three ope
erating points of
o transistor ope
erating in comm
mon emitter am
mplifier.
1.
2.
3.
Near cu
ut off
Near sa
aturation
In the middle
m
of active
e region
If the opera
ating point is se
elected near th
he cutoff region, the output is clipped in nega
ative half cycle
e as shown in fiig. 1.
Fig. 1
If the opera
ating point is se
elected near sa
aturation region
n, then the outp
put is clipped in
n positive cycle
e as shown in ffig. 2.
Fig.
F 2
Fig. 3
If the opera
ating point is se
elected in the middle
m
of active
e region, then tthere is no clipp
ping and the ou
utput follows in
nput
faithfully as
s shown in fig. 3. If input is large then clippin
ng at both side
es will take placce. The first circcuit for biasing the
transistor is
s CE configura
ation is fixed bia
as.
In biasing circuit
c
shown in
n fig. 4(a), two different powe
er supplies are required. To avvoid the use off two supplies tthe
base resisttance RB is con
nnected to VCC as shown in fig. 4(b).
Fig. 4(a)
Fig. 4(b)
Now VCC is
s still forward biasing emitter diode.
d
In this circuit Q point iss very unstable
e. The base ressistance RB is
selected by
y noting the req
quired base current IB for ope
erating point Q.
IB = (VCC VBE ) / RB
Voltage ac
cross base emittter junction is approximately 0.7 V. Since V CC is usually ve
ery high
i.e. IB = VCCC/ RB
Since IB is constant there
efore it is called
d fixed bias circ
cuit.
Stability of
o quiescent operating
o
poin
nt:
Let us assu
ume that the tra
ansistor is replaced by an oth
her transistor off same type. T
The dc of the tw
wo transistors o
of
same type may not be sa
ame. Therefore, if dc increas
ses then for sam
me IB, output characteristic sh
hifts upward.
eases, the outp
put characteristic shifts downw
ward. Since IB i s maintained cconstant, thereffore the operatting
If dc decre
point shifts
s from Q to Q1 as
a shown in fig
g. 5. The new operating
o
point may be complletely unsatisfa
actory.
Therefore, to maintain op
perating point stable, IB should
d be allowed to
o change so ass to maintain VCCE & IC constan
nt
nges.
as dc chan
Fig. 5
A second cause
c
for bias instability
i
is a variation
v
in tem
mperature. The reverse satura
ation current ch
hanges with
temperaturre. Specifically,, ICO doubles fo
or every 10oC rise
r
in temperatture. The collector current ICccauses the collector
junction tem
mperature to rise, which in turn increases ICO
of this growth ICO, IC will incre
ease ( dc IB +
C . As a result o
(1+ dc ) ICO
sible that this process
p
goes o
on and the ratin
ngs of the transsistors are exce
eeded.
C ) and so on. It may be poss
This increa
ase in IC changes the characte
eristic and hence the operatin
ng point.
Stability Factor:
F
The operatting point can be
b made stable
e by keeping IC and VCE consttant. There are
e two technique
es to make Q p
point
stable.
1.
2.
stabilization technique
es
compensation techniq
ques
d which allow IB to vary so as to keep IC relattively constant with variationss

In first, resistor biasing cirrcuits are used
in dc , ICO and VBE.
In second, temperature sensitive device
es such as diod
des, transistorss are used whicch provide com
mpensating voltages
and currents to maintain the
t operating point
p
constant.
To comparre different bias
sing circuits, stability factor S is defined as t he rate of chan
nge of collectorr current with
respect to the
t ICO, keeping dc and VCE constant
c
S = IC / ICO
If S is large
e, then circuit is
s thermally insttable. S cannott be less than u
unity. The othe
er stability facto
ors
are, IC / dc and IC / VBE. The bia
as circuit, which provide stabiility with ICO, also show stability even if and
es.
VBEchange
IC =
dcIB
+ (I +
dc
) ICO
C
Differentiatting with respec

ct to IC,
In fixed bia
as circuit, IB & IC are independ
dent. Therefore
e
and S = 1 + dc. If dc=100, S = 101, which me
eans
ICincreases
s 101 times as fast as ICO. Su
uch a large change definitely o
operate the tra
ansistor in saturration.
Essentia
als of a biasing network
k
Emitter Feedback
F
Biass:
Fig. 1, sho
ows the emitter feedback bias circuit. In this circuit, the volttage across ressistor RE is use
ed to offset the
changes in
n dc. If dc incrreases, the collector current in
ncreases. Thiss increases the emitter voltage
e which decrea
ase
the voltage
e across base resistor
r
and red
duces base currrent. The redu
uced base curre
ent result in lesss collector currrent,
which partiially offsets the
e original increa
ase in dc. The feedback term
m is used becau
use output currrent ( IC) producces a
change in input
i
current ( IB ). RE is comm
mon in input an
nd output circu its.
Fig. 1
In this case
e
Since IE = IC + IB
Therefore,
In this case
e, S is less com
mpared to fixed
d bias circuit. Thus the stability
ty of the Q poin
nt is better.
Further,
If IC is to be
e made insensitive to dc than
n
RE cannot be made large enough to swa

amp out the efffects of dc with
hout saturating
g the transistor..
Collector Feedback Bias:

In this case
e, the base resistor is returned back to colle
ector as shown in fig. 2. If tem
mperature incre
eases. dc incre
eases.
This produces more colle
ectors current. As
A IC increases
s, collector emiitter voltage de
ecreases. It me
eans less voltag
ge
across RB and causes a decrease
d
in base current this decreasing IC, and compenssating the effectt of dc.
Fig. 2
In this circu
uit, the voltage equation is giv
ven by
Circuit is sttiff sensitive to changes in dcc. The advantag

ge is only two rresistors are ussed.
Then,
Therefore,
It is better as compared to
o fixed bias circ
cuit.
Further,
Circuit is sttill sensitive to changes in dcc. The advantag

ge is only two rresistors are ussed.
Voltage Divider
D
Bias:
If the load resistance RC is
i very small, e.g.
e in a transfo
ormer coupled ccircuit, then the
ere is no impro
ovement in
stabilization in the collector to base bias
s circuit over fix
xed bias circuitt. A circuit whicch can be used even if there iss no
dc resistan
nce in series with the collectorr, is the voltage
e divider bias o
or self bias. fig.. 3.
The curren
nt in the resistance RE in the emitter
e
lead cau
uses a voltage drop which is in the direction
n to reverse bia
as the
emitter junction. Since thiis junction mus
st be forward biiased, the base
e voltage is obttained from the
e supply throug
gh R1,
R2 network
k. If Rb = R1 || R2 equivalent re
esistance is very very smalll, then VBE volta
age is indepen
ndent of
ICO and IC / ICO 0. For
F best stability
y R1 & R2 mustt be kept small .
Fig. 3
If IC tends to
t increase, be
ecause of ICO, th
hen the currentt in RC increase
es, hence base
e current is deccreased becau
use of
more reverrse biasing and
d it reduces IC .
To analysis
s this circuit, th
he base circuit is
i replaced by its thevenin's e
equivalent as sshown in fig. 4.
Fig. 4
Thevenin's
s voltage is
Rb is the efffective resistan

nce seen back from the base terminal.
If VBE is considered to be independent of

o IC, then
The smalle
er the value of Rb, the better is
s the stabilizatiion but S canno
ot be reduced be unity.
Hence IC always
a
increase
es more than ICO
uced, then curre
ent drawn from
m the supply inccreases. Also iff RE is
C . If Rb is redu
increased then
t
to operate
e at same Q-po
oint, the magnittude of VCC mu
ust be increase
ed. In both the ccases the powe
er loss
increased and
a reduced .
In order to avoid the loss of ac signal be
ecause of the fe
eedback cause
ed by RE, this rresistance is offten by passed by a
large capacitance (> 10 F) so that its reactance at th

he frequency u
under considera
ation is very sm
mall.
Emitter Bias:
B
Fig. 5, sho
own the emitter bias circuit. Th
he circuit gets this
t
name beca
ause the negattive supply VEE is used to forw
ward
bias the em
mitter junction through
t
resistor RE. VCC still re
everse biases collector junctiion. This also g
gives the same
e
stability as voltage divider circuit but it is
s used only if split
s
supply is avvailable.
Fig. 5
In this circu
uit, the voltage equation is giv
ven by
Lecture - 17: Biasing Tec

chniques
Example-1
Determine the Q-point forr the CE ampliffier given in fig. 1, if R1 = 1.5K
K W and Rs = 7K W . A 2N39
904 transistor iss
used with = 180, RE = 100W and RC = Rload = 1K W . Also determ

mine the Pout(a
ac) and the dc power delivere
ed to
the circuit by
b the source.
Fig. 1
Solution:
We first ob
btain the Theve
enin equivalent..
and
Note that th
his is not a des
sirable Q-point location since VBB is very clo
ose to VBE. Va
ariation in VBE
E therefore
significantly
y change IC.W
We find Rac = RC
R || Rload= 50
00 W and Rdc = RC + RE =1..1KW. The valu
ue of
VCErepres
senting the quie
escent value as
ssociated with ICQ is found a
as follows,
Then
Since the Q-point

Q
is on th
he lower half off the ac load lin
ne, the maximu
um possible sym
mmetrical output voltage swin
ng is
The ac pow
wer output can be calculated as
The powerr drawn from the dc source is given by
The powerr loss in the tran

nsistor is given
n by
The Q-poin
nt in this examp
ple is not in the
e middle of the load line so tha
at output swing
g is not as grea
at as possible.
However, if the input sign
nal is small and
d maximum outtput is not requ ired, a small IC
C can be used to reduce the p
power
dissipated in the circuit.
Moving Ground
G
Aroun
nd:
Ground is a reference point that can be moved around
d. e.g. considerr a collector fee
edback bias cirrcuit. The vario
ous
stages of moving
m
ground are shown in fig.
f 2.
Fig. 2
Biasing a pnp Transisttor:

The biasing
g of pnp transis
stor is done sim
milar to npn transistor except that supply is of opposite pollarity The vario
ous
biasing circ
cuits of pnp transistor are sho
own in fig. 3.
Fig. 3
Example 2:
For the circ
cuit shown in fiig. 4, calculate IC and VCE
Solution:
Fig. 4
Biasing methods
m
forr amplifierss:
Biasing Circuit
C
Techniiques or Loca
ating the Q - Point:
P
Fixed Bias
s or Base Bias
s:
In order forr a transistor to

o amplify, it has
s to be properly
y biased. This m
means forward
d biasing the ba
ase emitter juncction
and reverse biasing collector base juncttion. For linear amplification, tthe transistor sshould operate in active regio
on ( If
IE increase
es, IC increases
s, VCE decrease
es proportionally).
The source
e VBB, through a current limit resistor
r
RB forw
ward biases the
e emitter diode
e and VCC throu
ugh resistor RC (load
resistance)) reverse biase
es the collector junction as sho
own in fig. 1.
Fig. 1
The dc bas
se current throu
ugh RB is given
n by
IB = (VBB - VBE) / RB
or
VBE
B = VBB - IB RB
Normally VBE is taken 0.7

7V or 0.3V. If ex
xact voltage is required, then the input chara
acteristic ( IB vss VBE) of the
transistor should
s
be used
d to solve the above equation.. The load line for the input ciircuit is drawn o
on input
characteris
stic. The two po
oints of the load
d line can be obtained
o
as give
en below
For IB = 0,
0
and
Forr
VBE = VBB.
VBE = 0,
IB = VBB/ RB.
The interse
ection of this lin
ne with input ch
haracteristic giv
ves the operatiing point Q as sshown in fig. 2
2. If an ac signa
al is
connected to the base of the transistor, then variation in VBE is aboutt Q - point. Thiss gives variatio
on in IB and hen
nce IC.
Fig. 2
In the output circuit, the lo

oad equation can
c be written as
a
VCE = VCC- IC RC
This equation involves tw
wo unknown VCE and IC and th
herefore can no
ot be solved. To
o solve this equation output
characteris
stic ( ICvs VCE) is used.
The load equation is the equation
e
of a straight
s
line and
d given by two points:
IC= 0,
&
VCE = VCC
VCE = 0,
IC= VCC / RC
The interse
ection of this lin
ne which is also
o called dc load
d line and the ccharacteristic g
gives the opera
ating point Q ass
shown in fiig. 3.
Fig. 3
The point at
a which the loa
ad line intersec
cts with IB = 0 characteristic
c
iss known as cut off point. At this point base ccurrent
is zero and
d collector curre
ent is almost ne
egligibly small. At cut off the e
emitter diode ccomes out of fo
orward bias and
d
normal tran
nsistor action is
s lost. To a clos
se approximation.
VCE ( cut offf) VCC (app
proximately).
The interse
ection of the loa
ad line and IB = IB(max) charactteristic is know
wn as saturation
n point . At this point IB= IB(maxx), IC=
IC(sat). At this point collecto
or diodes come
es out of revers
se bias and ag ain transistor a
action is lost. T
To a close
approximattion,
IC(sat) VCC / RC(approxim
mately ).
The IB(sat) is
s the minimum current require
ed to operate the transistor in
n saturation reg
gion. If the IB is less than IB (saat), the
transistor will
w operate in active
a
region. Iff IB > IB (sat) it always operatess in saturation rregion.
If the transistor operates at saturation or cut off points and no where else then it is o
operating as a switch is show
wn
in fig. 4.
Fig. 4
VBB = IB RB+ VBE
IB = (VBB VBE ) / RB
If IB> IB(sat), then it operate
es at saturation
n, If IB = 0, then
n it operates at cut off.
If a transisttor is operating
g as an amplifie
er then Q point must be seleccted carefully. A
Although we ca
an select the
operating point
p
any where
e in the active region by choo
osing different vvalues of RB & RC but the varrious transistor
ratings suc
ch as maximum
m collector dissipation PC(max) maximum colle
ector voltage VC(max) and IC(maax) & VBE(max) lim
mit the
operating range.
r
Once the Q point is estab
blished an ac in
nput is connectted. Due to thiss the ac source
e the base curre
ent varies. As a
result of this collector current and collec
ctor voltage also varies and th
he amplified ou
utput is obtained.
If the Q-point is not selected properly then the output waveform
w
will n
not be exactly tthe input wavefform. i.e. It may be
clipped from
m one side or both
b
sides or itt may be distortted one.
Field efffect transisto

or:
Junction
n field effectt transistor:
Module
1
Power Semiconductor
Devices
Version 2 EE IIT, Kharagpur 1
Lesson
6
Metal Oxide
Semiconductor Field
Effect Transistor
(MOSFET)
Constructional Features, operating principle and characteristics of Power Metal Oxide

Semiconductor Field Effect Transistor (MOSFET).
Instructional Objectives
On completion the student will be able to
Differentiate between the conduction mechanism of a MOSFET and a BJT.
Explain the salient constructional features of a MOSFET.
Draw the output i-v characteristics of a MOSFET and explain it in terms of the operating
principle of the device.
Explain the difference between the safe operating area of a MOSFET and a BJT.
Draw the switching characteristics of a MOSFET and explain it.
Design the gate drive circuit of a MOSFET.
Interpret the manufacturers data sheet rating of a MOSFET.
6.1 Introduction
Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc)
have been the front runners in the quest for an ideal power electronic switch. Ever since the
invention of the transistor, the development of solid-state switches with increased power
handling capability has been of interest for expending the application of these devices. The BJT
and the GTO thyristor have been developed over the past 30 years to serve the need of the power
electronic industry. Their primary advantage over the thyristors have been the superior switching
speed and the ability to interrupt the current without reversal of the device voltage. All bipolar
devices, however, suffer from a common set of disadvantages, namely, (i) limited switching
speed due to considerable redistribution of minority charge carriers associated with every
switching operation; (ii) relatively large control power requirement which complicates the
control circuit design. Besides, bipolar devices can not be paralleled easily.
The reliance of the power electronics industry upon bipolar devices was challenged by the
introduction of a new MOS gate controlled power device technology in the 1980s. The power
MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The
new device promised extremely low input power levels and no inherent limitation to the
switching speed. Thus, it opened up the possibility of increasing the operating frequency in
power electronic systems resulting in reduction in size and weight. The initial claims of infinite
current gain for the power MOSFET were, however, diluted by the need to design the gate drive
circuit to account for the pulse currents required to charge and discharge the high input
capacitance of these devices. At high frequency of operation the required gate drive power
becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area
of the device cross section which increases with the blocking voltage rating of the device.
Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts)
applications where the ON state resistance reaches acceptable values. Inherently fast switching
speed of these devices can be effectively utilized to increase the switching frequency beyond
several hundred kHz.
From the point of view of the operating principle a MOSFET is a voltage controlled
majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is
controlled by the voltage applied on the control electrode (called gate) which is insulated by a
thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate
voltage modulate the conductivity of the semiconductor material in the region between the main
current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like
their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement
type. Both of these can be either n- channel type or p-channel type depending on the nature of
the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs
along with their drain current vs gate-source voltage characteristics (transfer characteristics).
D
ID
G
D
ID
ID
ID
G
G
ID
ID
VGS
n-channel depletion type
MOSFET
VGS
p-channel depletion type
MOSFET
ID
ID
VGS
n-channel enhancement
type MOSFET
VGS
p-channel enhancement
type MOSFET
(a)
(b)
Fig 6.1: Different types of power MOSFET.
(a) Circuit symbols and transfer characteristics
(b) Photograph of n-channel enhancement type MOSFET.
From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type
switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This
is not convenient in many power electronic applications. Therefore, the enhancement type
MOSFETs (particularly of the n-channel variety) is more popular for power electronics
applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b)
shows the photograph of some commercially available n-channel enhancement type Power
MOSFETs.
6.2
Constructional Features of a Power MOSFET
As mentioned in the introduction section, Power MOSFET is a device that evolved from
MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were
by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting
technology was called lateral double deffused MOS (DMOS). However it was soon realized that
much larger breakdown voltage and current ratings could be achieved by resorting to a vertically
oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually
all manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has
vertically oriented three layer structure of alternating p type and n type semiconductors as shown
in Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure. A large
number of such cells are connected in parallel (as shown in Fig 6.2 (b)) to form a complete
device.
Source
Gate conductor
FIELD OXIDE
n+
Gate oxide
n+
n+
n+
p(body)
p(body)
n- (drain drift)
n+
Drain
(a)
Contact to source
Source
Conductor
Gate
Oxide
Field oxide
Gate
Conductor
nn+ p n+
n+ p n+
Single
MOSFET
Cell
n+
nn+
(b)
Fig. 6.2: Schematic construction of a power MOSFET
(a) Construction of a single cell.
(b) Arrangement of cells in a device.
The two n+ end layers labeled Source and Drain are heavily doped to approximately the
same level. The p type middle layer is termed the body (or substrate) and has moderate doping
level (2 to 3 orders of magnitude lower than n+ regions on both sides). The n- drain drift region
has the lowest doping density. Thickness of this region determines the breakdown voltage of the
device. The gate terminal is placed over the n- and p type regions of the cell structure and is
insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate
oxide). The source and the drain region of all cells on a wafer are connected to the same metallic
contacts to form the Source and the Drain terminals of the complete device. Similarly all gate
terminals are also connected together. The source is constructed of many (thousands) small
polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source
regions, to same extent, influences the ON state resistance of the MOSFET.
D
G
S
+
n
p
Body spreading
resistance
MOSFET
Parasitic BJT
n
Parasitic BJT
nn+
Body diode
S
Fig. 6.3: Parasitic BJT in a MOSFET cell.

One interesting feature of the MOSFET cell is that the alternating n+ n- p n+ structure
embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into
each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base and the
emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type
substrate. In the design of the MOSFET cells special care is taken so that this resistance is
minimized and switching operation of the parasitic BJT is suppressed. With an effective
short circuit between the body and the source the BJT always remain in cut off and its
collector-base junction is represented as an anti parallel diode (called the body diode) in
the circuit symbol of a Power MOSFET.
6.3 Operating principle of a MOSFET

At first glance it would appear that there is no path for any current to flow between the
source and the drain terminals since at least one of the p n junctions (source body and
body-Drain) will be reverse biased for either polarity of the applied voltage between the
source and the drain. There is no possibility of current injection from the gate terminal
either since the gate oxide is a very good insulator. However, application of a positive
voltage at the gate terminal with respect to the source will covert the silicon surface
beneath the gate oxide into an n type layer or channel, thus connecting the Source to the
Drain as explained next.
The gate region of a MOSFET which is composed of the gate metallization, the gate
(silicon) oxide layer and the p-body silicon forms a high quality capacitor. When a small
voltage is application to this capacitor structure with gate terminal positive with respect to
the source (note that body and source are shorted) a depletion region forms at the interface
between the SiO2 and the silicon as shown in Fig 6.4 (a).
VGS1
+++ ++++++++
Source
Electrode
Gate Electrode
Si02
n+
Depletion layer
boundary.
Ionized
acceptor
p
n-
(a)
VGS2
VGS2 > VGS1
+++ ++++++++
Source
Electrode
Gate Electrode
Si02
n+
Ionized
acceptor
Free
electron
Depletion layer
boundary.
n(b)
VGS3
VGS3 > VGS2 > VGS1
+++ ++++++++
Source
Electrode
Gate Electrode
Si02
Inversion layer
with free electrons
n+
Depletion layer
boundary.
p
Ionized
acceptor
n-
(c)
Fig. 6.4: Gate control of MOSFET conduction.
(a) Depletion layer formation;
(b) Free electron accumulation;
(c) Formation of inversion layer.
The positive charge induced on the gate metallization repels the majority hole carriers from
the interface region between the gate oxide and the p type body. This exposes the
negatively charged acceptors and a depletion region is created.
Further increase in VGS causes the depletion layer to grow in thickness. At the same time
the electric field at the oxide-silicon interface gets larger and begins to attract free electrons
as shown in Fig 6.4 (b). The immediate source of electron is electron-hole generation by
thermal ionization. The holes are repelled into the semiconductor bulk ahead of the
depletion region. The extra holes are neutralized by electrons from the source.
As VGS increases further the density of free electrons at the interface becomes equal to the
free hole density in the bulk of the body region beyond the depletion layer. The layer of
free electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The
inversion layer has all the properties of an n type semiconductor and is a conductive path or
channel between the drain and the source which permits flow of current between the
drain and the source. Since current conduction in this device takes place through an n- type
channel created by the electric field due to gate source voltage it is called Enhancement
type n-channel MOSFET.
The value of VGS at which the inversion layer is considered to have formed is called the
Gate Source threshold voltage VGS (th). As VGS is increased beyond VGS(th) the
inversion layer gets some what thicker and more conductive, since the density of free
electrons increases further with increase in VGS. The inversion layer screens the depletion
layer adjacent to it from increasing VGS. The depletion layer thickness now remains
constant.
Exercise 6.1 (after section 6.3)

1.
Fill in the blank(s) with the appropriate word(s)

i.
A MOSFET is a ________________ controlled ________________ carrier device.
ii.
Enhancement type MOSFETs are normally ________________devices while depletion

type MOSFETs are normally ________________ devices.
iii.
The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of
________________.
iv.
The MOSFET cell embeds a parasitic ________________ in its structure.
v.
The gate-source voltage at which the ________________ layer in a MOSFET is formed

is called the ________________ voltage.
vi.
The thickness of the ________________ layer remains constant as gate source voltage
is increased byond the ________________ voltage.
Answer: (i) voltage, majority; (ii) off, on; (iii) SiO2, (iv) BJT, (v) inversion, threshold; (vi)
depletion, threshold.
2.
What are the main constructional differences between a MOSFET and a BJT? What
effect do they have on the current conduction mechanism of a MOSFET?
Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors.
However, unlike BJT the p type body region of a MOSFET does not have an external
electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of
SiO2. The body itself is shorted with n+ type source by the source metallization. Thus
minority carrier injection across the source-body interface is prevented. Conduction in a
MOSFET occurs due to formation of a high density n type channel in the p type body
region due to the electric field produced by the gate-source voltage. This n type channel
connects n+ type source and drain regions. Current conduction takes place between the
drain and the source through this channel due to flow of electrons only (majority carriers).
Where as in a BJT, current conduction occurs due to minority carrier injection across the
Base-Emitter junction. Thus a MOSFET is a voltage controlled majority carrier device
while a BJT is a minority carrier bipolar device.
6.4 Steady state output i-v characteristics of a MOSFET

The MOSFET, like the BJT is a three terminal device where the voltage on the gate
terminal controls the flow of current between the output terminals, Source and Drain. The
source terminal is common between the input and the output of a MOSFET. The output
characteristics of a MOSFET is then a plot of drain current (iD) as a function of the Drain
Source voltage (vDS) with gate source voltage (vGS) as a parameter. Fig 6.5 (a) shows such a
characteristics.
VGS VGS (th) = VDS

iD
ohmic
rDS(ON)
Electron Drift
Velocity
Increasing VGS
VGS6
Active
VGS5 [VGSVGS(th)]<VDS
VGS4
VGS3
VGS2
vgs1
Cut off (VGS < VGS (th))
VDSS vDS
(a)
G
(c)
Electric
Field
iD
n+
Source
region
resistance
Channel
p resistance
n-
iD
Drift
region
resistance
Drain
resistance
n+
(b)
VGS(th)
D
VGS
(d)
Fig. 6.5: Output i-v characteristics of a Power MOSFET

(a) i-v characteristics;
(b) Components of ON-state resistance;
(c) Electron drift velocity vs Electric field;
(d) Transfer
With gate-source voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET
operates in the cut-off mode. No drain current flows in this mode and the applied drain
source voltage (vDS) is supported by the body-collector p-n junction. Therefore, the
maximum applied voltage should be below the avalanche break down voltage of this
junction (VDSS) to avoid destruction of the device.
When VGS is increased beyond vGS(th) drain current starts flowing. For small values of vDS
(vDS < (vGS vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation
is called ohmic mode of operation. In power electronic applications a MOSFET is
operated either in the cut off or in the ohmic mode. The slope of the vDS iD characteristics
in this mode is called the ON state resistance of the MOSFET (rDS (ON)). Several physical
resistances as shown in Fig 6.5 (b) contribute to rDS (ON). Note that rDS (ON) reduces with
increase in vGS. This is mainly due to reduction of the channel resistance at higher value of
vGS. Hence, it is desirable in power electronic applications, to use as large a gate-source

voltage as possible subject to the dielectric break down limit of the gate-oxide layer.
At still higher value of vDS (vDS > (vGS vGS (th)) the iD vDS characteristics deviates from
the linear relationship of the ohmic region and for a given vGS, iD tends to saturate with
increase in vDS. The exact mechanism behind this is rather complex. It will suffice to state
that, at higher drain current the voltage drop across the channel resistance tends to decrease
the channel width at the drain drift layer end. In addition, at large value of the electric field,
produced by the large Drain Source voltage, the drift velocity of free electrons in the
channel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomes
independent of VDS and determined solely by the gate source voltage vGS. This is the
active mode of operation of a MOSFET. Simple, first order theory predicts that in the
active region the drain current is given approximately by
i D = K(vGS - vGS (th))2
(6.1)
Where K is a constant determined by the device geometry.

At the boundary between the ohmic and the active region
vDS = vGS - vGS (th)
(6.2)
Therefore, i D = KvDS2
(6.3)
Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1)
applies reasonably well to logic level MOSFETs. However, for power MOSFETs the
transfer characteristics (iD vs vGS) is more linear as shown in Fig 6.5 (d).
At this point the similarity of the output characteristics of a MOSFET with that of a BJT
should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off,
(ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important
differences as well.
Unlike BJT a power MOSFET does not undergo second break down.
The primary break down voltage of a MOSFET remains same in the cut off and in
the active modes. This should be contrasted with three different break down
voltages (VSUS, VCEO & VCBO) of a BJT.
The ON state resistance of a MOSFET in the ohmic region has positive temperature
coefficient which allows paralleling of MOSFET without any special arrangement
for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature
coefficient making parallel connection of BJTs more complicated.
As in the case of a BJT the operating limits of a MOSFET are compactly represented in a
Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a
BJT the SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is restricted
by the absolute maximum permissible value of the drain current (IDM) which should not be
exceeded even under pulsed operating condition. To the left, operating restriction arise due
to the non zero value of rDS(ON) corresponding to vGS = vGS(Max). To the right, the first
operating restriction is due to the limit on the maximum permissible junction temperature
rise which depends on the power dissipation inside the MOSFET. This limit is different for
DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the
pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A
MOSFET does not undergo second break down and no corresponding operating limit
appears on the SOA. The final operation limit to the extreme right of the SOA arises due to
the maximum permissible drain source voltage (VDSS) which is decided by the avalanche
break down voltage of the drain -body p-n junction. This is an instantaneous limit. There is
no distinction between the forward biased and the reverse biased SOAs for the MOSFET.
They are identical.
Log (iD)
IDM
10-5sec
rDS(ON) limit
10-4sec
(VGS = VGS(max))
Max.
10-3sec
Power
Dissipation DC
Limit (Timax)
Primary voltage breakdown
limit
VDSS
Log (vDS)
Fig. 6.6: Safe operating area of a MOSFET.
Due to the presence of the anti parallel body diode, a MOSFET can not block any reverse
voltage. The body diode, however, can carry an RMS current equal to IDM. It also has a
substantial surge current carrying capacity. When reverse biased it can block a voltage
equal to VDSS.
For safe operation of a MOSFET, the maximum limit on the gate source voltage (VGS
(Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of
the thin gate oxide layer and permanent failure of the device. It should be noted that even
static charge inadvertently put on the gate oxide by careless handling may destroy it. The
device user should ground himself before handling any MOSFET to avoid any static charge
related problem.
Exercise 6.2
i.
A MOSFET operates in the ________________ mode when vGS < vGS(th)

ii.
In the ohmic region of operation of a MOSFET vGS vGS (th) is greater than
________________.
iii.
rDS (ON) of a MOSFET ________________ with increasing vGS.
iv.
In the active region of operation the drain current iD is a function of ________________

alone and is independent of ________________.
v.
The primary break down voltage of MOSFET is ________________ of the drain

current.
vi.
Unlike BJT a MOSFET does not undergo ________________.
vii.
________________ temperature coefficient of rDS(ON) of MOSFETs facilitates easy

________________ of the devices.
viii.
In a Power MOSFET the relation ship between iD and vGS vGS(th) is almost
________________ in the active mode of operation.
ix.
The safe operating area of a MOSFET is restricted on the left hand side by the
________________ limit.
Answer: (i) Cut off; (ii) vDS; (iii) decreases; (iv) vGS, vDS; (v) independent; (vi)
break down; (vii) Positive, paralleling; (viii) linear; (ix) rDS (ON);
second
6.5 Switching characteristics of a MOSFET

6.5.1 Circuit models of a MOSFET cell
Like any other power semiconductor device a MOSFET is used as a switch in all power
electronic converters. As a switch a MOSFET operates either in the cut off mode (switch
off) or in the ohmic mode (switch on). While making transition between these two states it
traverses through the active region. Being a majority carrier device the switching process in
a MOSFET does not involve any inherent delay due to redistribution of minority charge
carriers. However, formation of the conducting channel in a MOSFET and its
disappearance require charging and discharging of the gate-source capacitance which
contributes to the switching times. There are several other capacitors in a MOSFET
structure which are also involved in the switching process. Unlike bipolar devices,
however, these switching times can be controlled completely by the gate drive circuit
design.
Gate oxide
+
CGD
CGD
CGS
Drain body
depletion
layer
CDS
n-
Actual
CGD2
n+
(b)
CGD
CGD
(cut off)
CGS
CGD
iD = f(vGS)
(Active)
CGS
S
VDS
VGS VGS (th) = VDS
(a)
idealized
CGD1
rDS(ON)
(Ohmic)
CGS
(c)
Fig. 6.7: Circuit model of a MOSFET
(a) MOSFET capacitances
(b) Variation of CGD with VDS
(c) Circuit models.
Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most
prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the
gate metallization and the n+ type source region. It has the largest value (a few nano farads)
and remains more or less constant for all values of vGS and vDS. The next largest capacitor
(a few hundred pico forwards) is formed by the drain body depletion region directly
below the gate metallization in the n- drain drift region. Being a depletion layer capacitance
its value is a strong function of the drain source voltage vDS. For low values of vDS (vDS <
(vGS vGS (th))) the value of CGD (CGD2) is considerably higher than its value for large vDS
as shown in Fig 6.7 (b). Although variation of CGD between CGD1 and CGD2 is continuous a
step change in the value of CGD at vDS = vGS vGS(th) is assumed for simplicity. The lowest
value capacitance is formed between the drain and the source terminals due to the drain
body depletion layer away form the gate metallization and below the source metallization.
Although this capacitance is important for some design considerations (such as snubber
design, zero voltage switching etc) it does not appreciably affect the hard switching
performance of a MOSFET. Consequently, it will be neglected in our discussion. From the
above discussion and the steady state characteristics of a MOSFET the circuit models of a
MOSFET in three modes of operation can be drawn as shown in Fig 6.7 (c).
6.5.2 Switching waveforms

The switching behavior of a MOSFET will be described in relation to the clamped
inductive circuit shown in Fig 6.8. For simplicity the load current is assumed to remain
constant over the small switching interval. Also the diode DF is assumed to be ideal with
no reverse recovery current. The gate is assumed to be driven by an ideal voltage source
giving a step voltage between zero and Vgg in series with an external gate resistance Rg.
VD
DF
IO
if
+
iD
CGD
VDS
Rg
Vgg
+
-
ig
CGS
Fig. 6.8: Clamped inductive switching circuit using a MOSFET.

To turn the MOSFET on, the gate drive voltage changes from zero to Vgg. The gate
source voltage which was initially zero starts rising towards Vgg with a time constant 1 =
Rg (CGS + CGD1) as shown in Fig 6.9.
Vgg
VGS
VGSI0
VGS(th)
Vgg
2
1
2 = Rg(CGS+CGD2)
ig
1 = Rg(CGS+CGD1)
R g igI0
iD, if
iD
I0
if
Vgg
igI0
Rg
if
I0
iD
VDS
I0ros (ON)
tdON tri
tfv1 tfv2
tON
td(off) trv2 trvi tfi

toff
Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET
Note that during this period the drain voltage vDS is clamped to the supply voltage VD
through the free wheeling diode DF. Therefore, CGS and CGD can be assumed to be
connected in parallel effectively. A part of the total gate current ig charges CGS while the
other part discharges CGD.
Till vGS reaches vGS (th) no drain current flows. This time period is called turn on delay
time (td(ON)). Note that td(ON) can be controlled by controlling Rg. Byond td(ON) iD
increases linearly with vGS and in a further time tri (current rise time) reaches Io. The
corresponding value of vGS and ig are marked as VGS Io and ig Io respectively in Fig 6.9.
At this point the complete load current has been transferred to the MOSFET from the free
wheeling diode DF. iD does not increase byond this point. Since in the active region iD and
vGS are linearly related, vGS also becomes clamped at the value vGSIo. The gate current ig
now discharges CGD and the drain voltage starts falling.
ig
V -V I
d
d
d
v DS = ( vGS + vGD ) = v GD =
= GG GS o
dt
dt
dt
CGD
CGD R g
( 6.4 )
The fall of vDS occurs in two distinct intervals. When the MOSFET is in the active region
(vDS > (vGS vGS (th)) CGD = CGD1.Since CGD1 << CGD2, vDS falls rapidly. This fast fall
time of vDS is marked tfv1 in Fig 6.9. However, once in the ohmic region, CGD = CGD2 >>
CGD1. Therefore, rate of fall of vDS slows down considerably (tfv2). Once vDS reaches its
on state value (rDS(ON) Io) vGS becomes unclamped and increases towards Vgg with a
time constant 2 = Rg (CGS + CGD2). Note that all switching periods can be reduced by
increasing Vgg or / and decreasing Rg. The total turn on time is tON = td(ON) + tri + tfv1 +
tfv2.
To turn the MOSFET OFF, Vgg is reduced to zero triggering the exact reverse process of
turn on to take place. The corresponding waveforms and switching intervals are show in
Fig 6.9. The total turn off time toff = td(off) + trv1 + trv2 + tfi.
6.5.3 MOSFET Gate Drive

MOSFET, being a voltage controlled device, does not require a continuous gate current
to keep it in the ON state. However, it is required to charge and discharge the gate-source and the
gate-drain capacitors in each switching operation. The switching times of a MOSFET essentially
depends on the charging and discharging rate of these capacitors. Therefore, if fast charging and
discharging of a MOSFET is desired at fast switching frequency the gate drive power
requirement may become significant. Fig 6.10 (a) shows a typical gate drive circuit of a
MOSFET.
VGG
VD
VGG
RG +
R1
(1 +1)
R1
Q1
Logic level
gate pulse
RG
RG
Q2
VGG
Q3
(b)
(a)
VD
DF
IL
R
RG
B
G
RB
(d)
S
(c)
Fig. 6.10: MOSFET gate drive circuit.

(a) Gate drive circuit; (b) Equivalent circuit during turn on and off;
(b) Effect of parasitic BJT; (d) Parallel connection of MOSFETs.
To turn the MOSFET on the logic level input to the inverting buffer is set to high state so
that transistor Q3 turns off and Q1 turns on. The top circuit of Fig 6.10 (b) shows the
equivalent circuit during turn on. Note that, during turn on Q1 remains in the active
region. The effective gate resistance is RG + R1 / (1 + 1). Where, 1 is the dc current gain
of Q1.
To turn off the MOSFET the logic level input is set to low state. Q3 and Q2 turns on
whole Q1 turns off. The corresponding equivalent circuit is given by the bottom circuit of
Fig 6.10 (b)
The switching time of the MOSFET can be adjusted by choosing a proper value of RG.
Reducing RG will incase the switching speed of the MOSFET. However, caution should
be exercised while increasing the switching speed of the MOSFET in order not to turn on
the parasitic BJT in the MOSFET structure inadvertently. The drain-source capacitance
(CDS) is actually connected to the base of the parasitic BJT at the p type body region. The
body source short has some nonzero resistance. A very fast rising drain-source voltage
will send sufficient displacement current through CDS and RB as shown in Fig 6.10 (c).
The voltage drop across RB may become sufficient to turn on the parasitic BJT. This
problem is largely avoided in a modern MOSFET design by increasing the effectiveness
of the body-source short. The devices are now capable of dvDS/dt in excess to 10,000
V/s. Of course, this problem can also be avoided by slowing down the MOSFET
switching speed.
Since MOSFET on state resistance has positive temperature coefficient they can be
paralleled without taking any special precaution for equal current sharing. To parallel two
MOSFETs the drain and source terminals are connected together as shown in Fig 6.10
(d). However, small resistances (R) are connected to individual gates before joining them
together. This is because the gate inputs are highly capacitive with almost no losses.
Some stray inductance of wiring may however be present. This stray inductance and the
MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate
voltage that can result in puncture of the gate qxide layer due to voltage increase during
oscillations. This is avoided by the damping resistance R.
Exercise 6.3
1.

i.
The Gate-Source capacitance of a MOSFET is the ________________ among all three

capacitances.
ii.
The Gate-Drain transfer capacitance of a MOSFET has large value in the

________________ region and small value in the ________________ region.
iii.
During the turn on delay time the MOSFET gate source voltage rises from zero to the
________________ voltage.
iv.
The voltage fall time of a MOSFET is ________________ proportional to the gate

charging resistance.
v.
Unlike BJT the switching delay times in a MOSFET can be controlled by proper design
of the ________________ circuit.
Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive.
2. A Power MOSFET has the following data

CGS = 800 pF ; CGD = 150 pF; gf = 4; vGS(th) = 3V;
It is used to switch a clamped inductive load (Fig 6.8) of 20 Amps with a supply voltage VD=
200V. The gate drive voltage is vgg = 15V, and gate resistance Rg = 50. Find out maximum
dv DS
did
and
during turn ON.
value of
dt
dt
Answer: During turn on
i D g f ( v gs - v gs (th) )
dv gs
di D
= gf
dt
dt
dv
V -v
But ( CGS + CGD ) gs = gg gs
dt
Rg
di D
dt
dv
di D
gf
= g f gs =
( Vgg - vgs )
dt
dt
R g ( CGS + CGD )
=
Max
gf
R g ( CGS + CGD
since for vgs < vgs (th)
di D
dt
=
Max
(V
)
iD =
gg
- vgs
Min
)=
g f ( Vgg - vgs (th) )

R g ( CGS + CGD )
di D
=0
dt
4
15 - 3) = 1.01109 A sec
-12 (
5095010
From equation (6.4)

dv DS Vgg - VGS , Io
=
dt
CGD R g
For Io = 20 A, vgs(th) = 3V, and gf = 4

I
20
VGS , Io = o + vgs (th) =
+ 3 = 8 volts
gf
4
dv DS
15 -8
=
= 933106 V sec.
dt
15010-12 50
6.6
MOSFET Ratings
Steady state operating limits of a MOSFET are usually specified compactly as a safe
operating area (SOA) diagram. The following limits are specified.
VDSS: This is the drain-source break down voltage. Exceeding this limit will destroy the
device due to avalanche break down of the body-drain p-n junction.
IDM: This is the maximum current that should not be exceeded even under pulsed current
operating condition in order to avoid permanent damage to the bonding wires.
Continuous and Pulsed power dissipation limits: They indicate the maximum
allowable value of the VDS, iD product for the pulse durations shown against each limit.
Exceeding these limits will cause the junction temperature to rise beyond the acceptable
limit.
All safe operating area limits are specified at a given case temperature.
In addition, several important parameters regarding the dynamic performance of the
device are also specified. These are
Gate threshold voltage (VGS (th)): The MOSFET remains in the cut off region when vGS
in below this voltage. VGS (th) decreases with junction temperature.
Drain Source on state resistance (rDS (ON)): This is the slope of the iD vDS
characteristics in the ohmic region. Its value decreases with increasing vGS and increases
with junction temperature. rDS (ON) determines the ON state power loss in the device.
Forward Transconductance (gfs): It is the ratio of iD and (vGS vGS(th)). In a MOSFET
switching circuit it determines the clamping voltage level of the gate source voltage and
thus influences dvDS/dt during turn on and turn off.
Gate-Source breakdown voltage: Exceeding this limit will destroy the gate structure of
the MOSFET due to dielectric break down of the gate oxide layer. It should be noted that
this limit may by exceeded even by static charge deposition. Therefore, special
precaution should be taken while handing MOSFETs.
Input, output and reverse transfer capacitances (CGS, CDS & CGD): Value of these
capacitances are specified at a given drain-source and gate-source voltage. They are
useful for designing the gate drive circuit of a MOSFET.
In addition to the main MOSFET, specifications pertaining to the body diode are also
provided. Specifications given are
Reverse break down voltage: This is same as VDSS
Continuous ON state current (IS): This is the RMS value of the continuous current that
can flow through the diode.
Pulsed ON state current (ISM): This is the maximum allowable RMS value of the ON
state current through the diode given as a function of the pulse duration.
Forward voltage drop (vF): Given as an instantaneous function of the diode forward
current.
Reverse recovery time (trr) and Reverse recovery current (Irr): These are specified as
functions of the diode forward current just before reverse recovery and its decreasing
slope (diF/dt).
Exercise 6.4

i.
The maximum voltage a MOSFET can with stand is ________________ of drain current.
ii.
The FBSOA and RBSOA of a MOSFET are ________________.
iii.
The gate source threshold voltage of a MOSFET ________________ with junction

temperature while the on state resistance ________________ with junction temperature.
iv.
The gate oxide of a MOSFET can be damaged by ________________ electricity.
v.
The reverse break down voltage of the body diode of a MOSFET is equal to
________________ while its RMS forward current rating is equal to ________________.
Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) VDSS; IDM.
Reference
[1] Evolution of MOS-Bipolar power semiconductor Technology, B. Jayant Baliga,
Proceedings of the IEEE, VOL.76, No-4, April 1988.
[2] Power Electronics ,Converters Application and Design Third Edition, Mohan,
Undeland, Robbins. John Wiley & Sons Publishers 2003.
[3] GE Power MOSFET data sheet.
Lesson Summary
MOSFET is a voltage controlled majority carrier device.
A Power MOSFET has a vertical structure of alternating p and n layers.
The main current carrying terminals of an n channel enhancement mode MOSFET are
called the Drain and the Source and are made up of n+ type semiconductor.
The control terminal is called the Gate and is isolated form the bulk semiconductor by a
thin layer of SiO2.
p type semiconductor body separates n+ type source and drain regions.
A conducting n type channel is produced in the p type body region when a positive voltage
greater than a threshold voltage is applied at the gate.
Current conduction in a MOSFET occurs by flow of electron from the source to the drain
through this channel.
When the gate source voltage is below threshold level a MOSFET remains in the Cut Off
region and does not conduct any current.
With vGS > vGS (th) and vDS < (vGS vGS (th)) the drain current in a MOSFET is
proportional to vDS. This is the Ohmic region of the MOSFET output characteristics.
For larger values of vDS the drain current is a function of vGS alone and does not depend on
vDs. This is called the active region of the MOSFET.
In power electronic applications a MOSFET is operated in the Cut Off and Ohmic
regions only.
The on state resistance of a MOSFET (VDS (ON)) has a positive temperature coefficient.
Therefore, MOSFETs can be easily paralleled.
A MOSFET does not undergo second break down.
The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does
not have a second break down limit.
Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not
depend on the drain current.
The safe operating area of a MOSFET does not change under Forward and Reverse bias
conditions.
The drain body junction in a MOSFET structure constitute an anti parallel diode
connected between the source and the drain. This is called the MOSFET body diode.
The body diode of a MOSFET has the same break down voltage and forward current rating
as the main MOSFET.
The switching delays in a MOSFET are due to finite charging and discharging time of the
input and output capacitors.
Switching times of a MOSFET can be controlled completely by external gate drive design.
The input capacitor along with the gate drive resistance determine the current rise and fall
time of a MOSFET during switching.
The transfer capacitor (Cgd) determines the drain voltage rise and fall times.
rDS (ON) of a MOSFET determines the conduction loss during ON period.
rDS (ON) reduces with higher vgs. Therefore, to minimize conduction power loss maximum
permissible vgs should be used subject to dielectric break down of the gate oxide layer.
The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be
handled only after discharging one self through proper grounding.
For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower
switching loss compared to a BJT. Therefore, MOSFETs are more popular for high
frequency (>50 kHz) low voltage (<100 V) circuits.
Practice Problems and Answers
Practice Problems
1. How do you expect the gate source capacitance of a MOSFET to varry with gate source
voltage. Explain your answer.
2. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field
strength of 5 106 V/cm and a safely factor of 50%, find out the maximum allowable
gate source voltage.
3. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is
always greater than current fall and rise times.
4. A MOSFET has the following parameters
VGS(th) = 3V, gfs = 3, CGS = 800 PF, CGD = 250 PF. The MOSFET is used to switch an
inductive load of 15 Amps from 150V supply. The switching frequency is 50 kHz. The
gate drive circuit has a driving voltage of 15V and output resistance of 50. Find out the
switching loss in the MOSFET.
Answer to practice problems

1. When the gate voltage is zero the thickness of the gate-source capacitance is
approximately equal to the thickness of the gate oxide layer. As the gate source voltage
increases the width of the depletion layer in the p body region also increases. Since the
depletion layer is a region of immobile charges it in effect increases the thickness of the
gate-source capacitance and hence the value of this capacitances decreases with
increasing vGS. However, as vGS is increased further free electrons generated by thermal
ionization get attracted towards the gate oxide-semiconductor interface. These free
electrons screen the depletion layer partially and the gate-source capacitance starts
increasing again. When vGS is above vgs (th) the inversion layer completely screens the
depletion layer and the effective thickness of the gate-source capacitance becomes once
again equal to the thickness of the oxide layer. There after the value of CGS remains more
or less constant.
2. From the given data the break down gate source voltage
v GS
BD
= E BD t gs
where EBD = Break down field strength

tgs = thickness of the oxide layer.
So v GS
Let vgs
safety.
BD
= 5106 100010-8 = 50V
Max
be the maximum allowable gate source voltage assuming 50% factor of

1.5 vgs
vgs
Max
Max
= vGS
BD
= 50 V
50
V 33 Volts.
1.5
3. We Know that for MOSFET

i D = g fs ( VGS - VGS (th) )
( Vgg - vGS )
di D
d
= g fs vGS = g fs
dt
dt
R g CGS
During current rise Vgg >> vGS
g fs
di
Vgg
D
dt R g CGS
t ri = t fi
Io
R g CGS
g fs Vgg
where Io = load current.
Now From equation (6.4)

Vgg - Vg s , Io
Vgg
d
v DS =
dt
R g CGD
R g CGD
Since Vgg >> Vgs, Io

V
t rr = t fv D R g CGD where VD = Load voltage.
Vgg
I
t ri
t
= fi = o
t rr
t fr
VD
CG S
g fs CG D
That is current rise and fall times are much shorter than voltage rise and fall times.
4. Referring to Fig 6.9 energy loss during switching occurs during intervals tri , tfv1, tfv2, trv2,trv1,
and tfi. For simplicity it will be assumed that tfv2 = trv2 = 0. Also the rise and fall of iD and vDS
will be assumed to be linear.
During tri
i D = g fs (vgs - vgs (th))
Vgg - v gs
di D
d
= g fs v gs = g fs
dt
dt
(CGS + CGD )R g
g fs Vgg
di D
sinceVgg >> v gs during current rise

dt (CGS + CGD )R g
Io
(CGS + CGD )R g
g fs Vgg
Energy loss during tri is
V I2
1
E ON1 = t ri VD Io = D o (CGS + CGD )R g
2
2g fs Vgg
During tfv
dVDS Vgg - Vgs, Io
=
dt
CGD R g
I
But Vgs , Io = o + vgs (th)
g fs
I
Vgg - v gs (th) - o
dVDS
g fs
=
dt
R g CGD
t ri =
t fv =
VD
Vgg - Vgs (th) -
Io
R g CGD
g fs
Energy loss during tfv is

E ON2 = 1 t fv Io VD
2
VD 2 Io
=
R g CGD
I
2 Vgg - vgs (th) - o
g fs
Energy loss during Turn on is


VD Io R g Io ( CGS + CGD )
VD CGD
+
2
g fs Vgg
V
V
(th)
(
)
gg
gs
From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.e. tri = tfi, tfv =
trv)
E ON = E ON1 + E ON2 =
E ON = EOFF
Total switching energy lass is Esw = EON + EOFF = 2 EON
VD Vgg
I g C
E sw = VD Io R g CGD o fs 1+ GS +
Vgg CGD Vgs (th) Io g fs
V
Vgg
gg
VD Vgg
C I g
Psw E sw = VD Io R g CGD f sw 1+ GS o fs +
v gs (th) Io g fs
CGD Vgg
1
Vgg
v gg
Substituting the values given

Psw = 32 mw,
Classificattionofpoweramplifiers
Darlingto
on Amplifier:
It consists of two emitter followers
f
in cas
scaded mode as
a shown in fig
g. 1. The overa
all gain is close to unity. The m
main
a
is very
y large increas
se in input impe
edence and an equal decreasse in output
advantage of Darlington amplifier
impedance
e.
Fig. 1
DC Analy
ysis:
nd VBE drop. T
The first tra
ansistor has on
ne VBE drop and
d second trans
sistor has secon
The voltage diviider produces VTH to
the input base. The dc em
mitter current of the second sttage is
IE2 = (VTH 2 vBE ) / (RE )
The dc emitter current of the first stage that is the base
e current of seccond stage is g
given by
IE1 IE2 / 2
If r'e(2) is ne
eglected then in
nput impedance of second sta
age is
Zin (2) = 2 RE
This is the impedance seen by the first transistor.
t
If r'e(1) is also negle
ected then the input impedancce of 1 become
es.
Zin (1) = 1 2 RE
which is ex
xtremely high because
b
of the products of two
o betas, so the
e approximate iinput impedancce of Darlington
n
amplifier is
s
Zin = R1 || R2
Output im
mpedance:
The Theve
enin impedance
e at the input is
s given by
RTH = RS || R1 || R2
Similar to single
s
stage common collecto
or amplifier, the
e output impeda
ance of the two
o stages zout(1) and zout(2) are g
given
by.
Therefore, t he output imp

pedance of the
e amplifier is ve
ery small.
Example--1
Design a single stage npn
n emitter follow
wer amplifier as
s shown in fig. 2 with =60, VBE =0.7V, Rsouurce =1 K, and
d VCC=
12V. Deterrmine the circuit element values for the stage to achieve A i = 10 with a 10
00 load.
Fig. 2
Solution:
nd RE, but we only
o
have two equations.
e
Thesse two equatio
ons are specifie
ed by the curren
nt
We must select R1, R2 an
he placement of
o the Q-point.
gain and th
As discuss
sed earlier, the best choice forr a CE amplifie
er is to make RC =R load. We ccould derive a ssimilar result fo
or
RE and Rloaad in the CC am
mplifier. We sha
all therefore be
egin by constra
aining REto be e
equal to Rload. T
This yields a th
hird
equation,
RE = Rload= 100 W
Now finding the load line slopes,
Rac = RE || Rload =50 W
Rdc = RE = 100 V
o place the Q-p
a
of the
e input is not specified, we ch
hoose the quiesscent current to
point in the cen
nter of
Since the amplitude
the ac load
d line for maxim
mum swing.
We now fin
nd the value of r'e
Since re is insignificant co
ompared to RE || Rload, it can be
b ignored. Thiis is usually the
e case for emitter follower circcuits.
e
for current gain we find
f
Using the equation
Everything in this equatio

on is known exc
cept RB. We so
olve for RB with
h the result
RB = 1500 W
nd from the bas
se loop.
VBB is foun
Continuing
g with the desig
gn as discussed
d earlier, we fin
nd
R1 = 13.8 K
R2 = 1.68 K
The voltage gain of the CC
C amplifier is approximately
a
unity.
r
is given by
The input resistance
Rin = RB || [ ( R E || Rloadd ) ] = 1 k
The outputt resistance is given
g
by
The maxim
mum peak to pe
eak symmetrica
al output swing is given by
Vout(p-p) 1.8 | ICQ| (RE || Rload ) = 7.2 V
t load, Pload, and the maxim
mum power req uired of the tra
ansistor, Ptransisttor, are
The powerr dissipated in the
Example--2 (Capacitor-Coupled CB
B Design)
Design a CB
C amplifier using an npn tran
nsistor as show
wn in fig. 3 with
h = 100, VCC= 24 V, Rload= 2
2K, RE = 400
VBE = 0.7V
V. Design this amplifier for a vo
oltage gain of 20.
2
Fig. 3
Solution:
Since there
e are fewer equ
uations than there are unknow
wns, we need a
an additional cconstraint, so w
we set
RC = Rload = 2 K
Then we have,
Rac = 1.40 K and Rdc =2

2.40 K
For maximum swing, we set ICQ to
We now fin
nd that
The curren
nt gain is given by
and inpu
ut impedan
nce is given
n by
We use the
e bias equation
n to find the parrameters of the
e input bias circcuitry.
The bias re
esistors are the
en given by
The maxim
mum peak-to-pe
eak undistorted
d output voltage
e is
Vout(peak-p
peak) = 1.8 | ICQ
Q | (Rload || RC) = 11.3 V
Push pulll power am

mplifiers:
Class A cu
urrent drain::
In a class A amplifier shown in fig.1, the
e dc source VCCC must supply direct current to the voltage divider and the
collector circuit.
Fig. 1
Assuming a stiff voltage divider
d
circuit, the
t dc current drain
d
of the volltage divider cirrcuit is
I 1 = V CC / (R 1 +R 2 )
In the colle
ector circuit, the
e dc current dra
ain is
I 2 = I CQ
In a class A amplifier, the
e sinusoidal varriations in colle
ector current avverages to zero
o. Therefore, w
whether the ac ssignal
is present or
o not, the dc source
s
must supply an averag
ge current of
I S = I 1 + I 2.
This is the total dc curren
nt drain. The dc
c source voltage multiplied byy the dc currentt drain gives the ac power sup
pplied
to an amplifier.
P S = V CC IS
Therefore, efficiency of th
he amplifier, = (P L (max) / P S ) * 100 %
Where,, P L (max) = maximum ac load line
e power. In clas
ss A amplifier, there is a wastage of power in resistor R C and
2
R E i.e. ICQ
Q * (R C + R E ).
To reduce this wastage of
o power R C an
nd R E should be
b made zero. R E cannot be made zero beccause this will g
give
rise to bias
s stability proble
em. R C can als
so not be made
e zero because
e effective load
d resistance ge
ets shorted. Thiis
results in more
m
current an
nd no power tra
ansfer to the load R L. The R C resistance ca
an, however, be replaced by a
an
inductance
e whose dc resistance is zero and there is no
o dc voltage drrop across the choke as show
wn in fig. 1.
Since in most application the load is loudspeaker, therrefore power am
mplifier drives the loudspeake
er, and the
maximum power
p
transfer takes place on
nly when load impedence is e
equal to the sou
urce impedencce. If it is not, th
he
loud speak
ker gets less po
ower. The impe
edence matchin
ng is done with
h the help of tra
ansformer, as sshown in fig. 2.
Fig. 2
The ratio of
o number of turrns is so selectted that the imp
pedence referrred to primary sside can be ma
atched with the
e
output impedence of the amplifier.
a
Class B am
mplifier:
The efficien
ncy ( ) of clas
ss A amplifier is poor. The rea
ason is that the
ese circuits dra
aw considerable
e current from the
supply eve
en in the absence of input sign
nals.
In class B operation
o
the transistor collec
ctor current flow
ws for only 180
0 of the ac cyccle. This impliess that the Q-po
oint is
located app
proximately at cutoff on both dc and ac load
d lines. The advvantages of cla
ass B operation
n are
Lo
ower transistorr power dissipa
ation
Reduced
R
current drain.
Push pull circuit:
When a tra
ansistor operate
es in class B, itt clips off a
half cycle. To avoid the re
esulting distortiion, two
transistors are used in pu
ush pull arrange
ement. This
means thatt one transistorr conducts duriing positive
half cycle and
a other trans
sistor conducts during
negative ha
alf cycle. The distortion
d
is low
w, load power
is large and
d efficiency ( ) is more. fig. 3, shows
how a npn and pnp transistor emitter folllowers are
connected in push pull arrrangement.
a equivalent ciircuit are shown in fig.
The dc & ac
4 & fig. 5. The
T biasing res
sistors are sele
ected so that
Q-point is set
s at cutoff. Th
his biases the emitter
e
diode
of each transistor betwee
en 0.6V and 0.7
7V
0
i.e. I CQ = 0.
Because th
he biasing resis
stors are equal each
emitter diode is biased with the same vo
oltage. As a
t supply volta
age is dropped
d across
result half the
each transistor.
VCEQ = VCCC / 2.
Fig. 3
Fig. 4
Fig. 5
Since there
e is no dc resis
stance in the co
ollector or emittter circuits, the
e dc saturation current is infiniite. The dc load
d line
is vertical as
a shown in fig
g. 6. The most difficult
d
thing is
s setting up a sttable Q-point a
at cut off. Any ssignificant incre
ease
in V BE with
h temperature can
c move the Q-point
Q
up the dc load line to dangerously h
high currents. A
Ac load line is g
given
by
I C(sat) = I CQ
Q + (V CEQ / r E )
V CE (cut off) = V CEQ + I CQ r E
I CQ = 0; V CEQ = V CC / 2
i.e. I C(sat) = V CC / 2RL ( i.e
e. rE = R L )
V CE (cut off) = V CC / 2.
Fig
g. 6
When eithe
er transistor is conducting, tha
at transistor's operating
o
point swings along tthe ac load line
e and the opera
ating
point of the
e other transisto
or remains at cut
c off. The volttage swing of tthe conducting transistor can go from cut offf to
saturation. In the next half cycle, the oth
her transistor does the same tthing.
Therefore, PP = VCC
Voltage ga
ain of loaded am
mplifier:
AV= R L / (R
R L + r'e )
Z in (base) (RL + r'e )
Z out = r'e + (r B ) /
A P =A V * Ai
Without sig
gnal the capacitor charges up
p to VCC / 2 rela
ative to ground.
In the posittive half cycle of
o input voltage
e, the upper tra
ansistor conduccts and the low
wer one cut off. The upper tran
nsistor
acts like an
n ordinary emitter follower, so
o that the outpu
ut voltage appro
oximately equa
als the input vo
oltage. The currrent
flow throug
gh RL is such as direct as to make
m
output po
ositive.
In the nega
ative half cycle of input voltag
ge, the upper tra
ansistor cuts o
off and the lowe
er transistor conducts. The low
wer
transistor acts
a
like an ordinary emitter fo
ollower and pro
oduces a load vvoltage approxximately equal tto the input voltage
(i.e. negativ
ve output. Sinc
ce Q, is off, no current can flo
ow from VCC thrrough Q, but ca
apacitor acts likke a battery source
and discha
arges).
During eith
her half cycle, the source sees
s a high input impedence lookking into eitherr base and the load sees a low
w
output impedence.
Cross oveer distortion:

Fig. 1 show
ws the ac equiv
valent circuit off a class B push pull amplifierr. Suppose thatt no bias is app
plied to the emitter
diodes. Then the incomin
ng voltage has to
t rise to aboutt 0.7 V to overccome the barrie
er potential. Be
ecause of this n
no
current flow
ws through Q, when
w
the signa
al is less than 0.7
0 V. The actio
on is similar on
n the other half cycle no curre
ent
flows in Q2 until ac voltag
ge is more nega
ative the 0.7 V.
V If no bias is applied the ou
utput of class B amplifier lookss like
as shown in fig. 1.
Fig. 1
alf cycles, it no longer is a sine wave. Since the
The signal output is distorted. Because of clipping action between ha
clipping oc
ccurs between the
t time one tra
ansistor cuts off and the time the other com
mes on, it is called cross over
distortion. To
T eliminate crross over distorrtion, the slightt forward bias m
must be applied
d to each emittter diode. This
means loca
ating the Q-point slightly abov
ve cut off as sh
hown in fig. 2. IIn fact, this is cclass AB opera
ation. This means
that collecttor current flow
ws for more than
n 180 degrees but less than 3
360.
Fig. 2
Class A am
mplifier introduc
ces non-linear distortion in inp
put wave mean
ns elongates on
ne half cycle an
nd compressess one
half cycle. This can be reduced by swam
mping. In this case
c
it can be ffurther reduced
d because both
h half cycles are
e
identical in shape, is given by non-linear distortion is much
m
less than class A.
Load powe
er is given by
Since the ac
a output comp
pliance equals the
t peak-to-pe
eak voltage, the
e maximum loa
ad power is
Where, I1 = current throug

gh biasing resistance. When no signal is pre
esent I2 = ICQ a
and the current drain is small. But
when a sig
gnal is present, the current dra
ain increase be
ecause the upp
per collector cu
urrent becomess large.
If the entire
e ac load line is
s used, then the upper transis
stor has a half ssine wave of current through it with a peak vvalue
of
IC(sat) = VCEEQ / RL
The averag
ge value of halff sine wave is given
g
by
The dc pow
wer is supplied to the circuit is
s PS = VCC is un
nder no signal conditions, the
e dc power is ssmall because tthe
current dra
ain is minimum.. But when a siignal uses the entire
e
ac load lline, the dc pow
wer supplied to
o the circuit rea
aches
a maximum
m.
Biasing a class B ampllifier:

In class B amplifier,
a
two complement
c
an
ny transistors are
a required. Be
ecause of the sseries connectiion, each transsistor
drops half the
t supply voltage. To avoid cross over disttortion, the Q-p
point slightly ab
bove cut off, witth the correct
VBE somew
where between 0.6 and 0.7.
If there is an
a increase in VBE by few mV it produces 10
0 times as mucch emitter curre
ent. Because off this it is difficu
ult to
find standa
ard resistors tha
at can produce
e the correct VBE
B and it needs an adjustable resistor.
The biasing
g does not solv
ve thermal insta
ability problem. Because for a given collecto
or current, VBE requirement
decreases by 2 mV per degree rise in te
emperature. Th
he voltage divid
der produces a stiff drive for e
each diode.
Therefore as
a the tempera
ature increases
s, the fixed volta
age on each em
mitter diode forces the collector current to
increase an
nd this gives ris
se to thermal run away. When the temperatture increases collector current increases, a
and
this is equivalent to Q-point moving up along
a
the vertic
cal dc load line . As the Q-poin
nt moves towarrd higher collecctor
he temperature
e of the transisttor increases fu
urther reducing
g the required V BE .
currents, th
Fig. 3
One way to
o avoid thermal run away is to
o use diode bia
as. It is based o
on the conceptt of current mirrror as shown in
n fig.
3, the base
e current is muc
ch smaller than
n the current th
hrough the resisstor and diode. For this reaso
on, I1 and I2 are
e
approximattely equal. If th
he diode curve is identical to the VBE curve o
of the transistorr (VBE , IE ). The
e diode currentt
equals the emitter and als
so collector currrent. Therefore
e I1 is nearly eq
qual to IC.
I1 = I C .
The collecttor current is se
et by controlling
g the resistor current.
c
This is called a curren
nt mirror.
Similarly, pnp
p transistor can
c be used as a current mirro
or. If the VBE cu
urve of the tran
nsistor matchess the diode currve,
the collecto
or equals the re
esistor current.
Diode bias of class B pus
sh pull emitter follower
f
relies on
o two current mirrors as sho
own in fig. 4.
Fig. 4
The upper half is an npn current mirror, and the lower half is a pnp current mirror as shown in fig. 4. For diode bias to
be immune to changes in temperature, the diode curve must match the VBE curves of the transistor over a wide
temperature range. This is easily done in ICs .
Module
3
DC to DC Converters
Lesson
17
Types of Basic DC-DC
Converters
Study of the following:
Three basic types of dc-dc converter circuits buck, boost and buck-boost
The expressions for the output voltage in the above circuits, with inductive (R-L) and battery
(or back emf = E) load
Introduction
In the last module (#2) consisting of eight lessons, the various types of circuits used in both
single-phase and three-phase ac-dc converters, were discussed in detail. This includes half-wave
and full-wave, and also half-controlled and full-controlled ones.
In this lesson the first one in this module (#3), firstly, three basic types of dc-dc converter
circuits buck, boost and buck-boost, are presented. Then, the expressions for the output voltage
in the above circuits, with inductive (R-L) and battery (or back emf = E), i.e., R-L-E, load, are
derived, assuming continuous conduction. The different control strategies employed are briefly
described.
Keywords: DC-DC converter circuits, Thyristor choppers, Buck, boost and buck-boost
converters (dc-dc), Step-down (buck) and step-up (boost) choppers, Output voltage and current.
DC-DC Converters
There are three basic types of dc-dc converter circuits, termed as buck, boost and buck-boost.
In all of these circuits, a power device is used as a switch. This device earlier used was a
thyristor, which is turned on by a pulse fed at its gate. In all these circuits, the thyristor is
connected in series with load to a dc supply, or a positive (forward) voltage is applied between
anode and cathode terminals. The thyristor turns off, when the current decreases below the
holding current, or a reverse (negative) voltage is applied between anode and cathode terminals.
So, a thyristor is to be force-commutated, for which additional circuit is to be used, where
another thyristor is often used. Later, GTOs came into the market, which can also be turned off
by a negative current fed at its gate, unlike thyristors, requiring proper control circuit. The turnon and turn-off times of GTOs are lower than those of thyristors. So, the frequency used in GTObased choppers can be increased, thus reducing the size of filters. Earlier, dc-dc converters were
called choppers, where thyristors or GTOs are used. It may be noted here that buck converter
(dc-dc) is called as step-down chopper, whereas boost converter (dc-dc) is a step-up chopper.
In the case of chopper, no buck-boost type was used.
With the advent of bipolar junction transistor (BJT), which is termed as self-commutated
device, it is used as a switch, instead of thyristor, in dc-dc converters. This device (NPN
transistor) is switched on by a positive current through the base and emitter, and then switched
off by withdrawing the above signal. The collector is connected to a positive voltage. Now-adays, MOSFETs are used as a switching device in low voltage and high current applications. It
may be noted that, as the turn-on and turn-off time of MOSFETs are lower as compared to other
switching devices, the frequency used for the dc-dc converters using it (MOSFET) is high, thus,
reducing the size of filters as stated earlier. These converters are now being used for applications,
one of the most important being Switched Mode Power Supply (SMPS). Similarly, when
application requires high voltage, Insulated Gate Bi-polar Transistors (IGBT) are preferred over
BJTs, as the turn-on and turn-off times of IGBTs are lower than those of power transistors (BJT),
thus the frequency can be increased in the converters using them. So, mostly self-commutated
devices of transistor family as described are being increasingly used in dc-dc converters.
Buck Converters (dc-dc)

A buck converter (dc-dc) is shown in Fig. 17.1a. Only a switch is shown, for which a device
as described earlier belonging to transistor family is used. Also a diode (termed as free wheeling)
is used to allow the load current to flow through it, when the switch (i.e., a device) is turned off.
The load is inductive (R-L) one. In some cases, a battery (or back emf) is connected in series
with the load (inductive). Due to the load inductance, the load current must be allowed a path,
which is provided by the diode; otherwise, i.e., in the absence of the above diode, the high
induced emf of the inductance, as the load current tends to decrease, may cause damage to the
switching device. If the switching device used is a thyristor, this circuit is called as a step-down
chopper, as the output voltage is normally lower than the input voltage. Similarly, this dc-dc
converter is termed as buck one, due to reason given later.
S
Switch
L
I0
+
Vs
L
O
A
D
V0
DF
-
Fig. 17.1(a): Buck converter (dc-dc)

v0
Vs
V0
TON
t
T
TOFF
i0
t
Fig. 17.1(b): Output voltage and current waveforms
The output voltage and current waveforms of the circuit (Fig. 17.1a) are shown in Fig. 17.1b.
The output voltage is same as the input voltage, i.e., v0 = Vs , when the switch is ON, during the
period, TON t 0 . The switch is turned on at t = 0 , and then turned off at t = TON . This is
called ON period. During the next time interval, T t TON , the output voltage is zero, i.e.,
v0 = 0 , as the diode, D F now conducts. The OFF period is TOFF = T TON , with the time period
being T = TON + TOFF . The frequency is f = 1 / T . With T kept as constant, the average value of
the output voltage is,
T
V0 =
1
1
v0 dt =
T 0
T
TON
V
0
T
dt = Vs ON = k Vs
T
The duty ratio is k = (TON / T ) = [TON / (TON + TOFF )] , its range being 1.0 k 0.0 . Normally, due
to turn-on delay of the device used, the duty ratio (k) is not zero, but has some positive value.
Similarly, due to requirement of turn-off time of the device, the duty ratio (k) is less than 1.0. So,
the range of duty ratio is reduced. It may be noted that the output voltage is lower than the input
voltage. Also, the average output voltage increases, as the duty ratio is increased. So, a variable
dc output voltage is obtained from a constant dc input voltage. The load current is assumed to be
continuous as shown in Fig. 17.1b. The load current increases in the ON period, as the input
voltage appears across the load, and it (load current) decreases in the OFF period, as it flows in
the diode, but is positive at the end of the time period, T.
Boost Converters (dc-dc)

A boost converter (dc-dc) is shown in Fig. 17.2a. Only a switch is shown, for which a device
belonging to transistor family is generally used. Also, a diode is used in series with the load. The
load is of the same type as given earlier. The inductance of the load is small. An inductance, L is
assumed in series with the input supply. The position of the switch and diode in this circuit may
be noted, as compared to their position in the buck converter (Fig. 17.1a).
+
Is
I0
Vs
L
O
A
D
V0
Switch
-
Fig. 17.2(a): Boost converter (dc-dc)
I2
I1
TON
2T
TOFF
Fig. 17.2(b): Waveforms of source current (iS)
The operation of the circuit is explained. Firstly, the switch, S (i.e., the device) is put ON
(or turned ON) during the period, TON t 0 , the ON period being TON . The output voltage is
zero ( v0 = 0 ), if no battery (back emf) is connected in series with the load, and also as stated
earlier, the load inductance is small. The current from the source ( i s ) flows in the inductance L.
The value of current increases linearly with time in this interval, with ( d i d t ) being positive. As
the current through L increases, the polarity of the induced emf is taken as say, positive, the left
hand side of L being +ve. The equation for the circuit is,
di
d i s Vs
=
Vs = L s
or,
dt
dt
L
The switch, S is put OFF during the period, T t TON , the OFF period being
TOFF = T TON . ( T = TON + TOFF ) is the time period. As the current through L decreases, with its
direction being in the same direction as shown (same as in the earlier case), the induced emf
reverses, the left hand side of L being -ve. So, the induced emf (taken as ve in the equation
given later) is added with the supply voltage, being of the same polarity, thus, keeping the
current ( is = i0 ) in the same direction. The current ( is = i0 ) decreases linearly in the time interval,
TOFF , as the output voltage is assumed to be nearly constant at v0 V0 , with ( d i s d t ) being
negative, as Vs < V0 , which is derived later.
The equation for the circuit is,
di
d i s (Vs V0 )
Vs = V0 + L s
=
or,
dt
dt
L
The source current waveform is shown in Fig. 17.2b. As stated earlier, the current varies
linearly from I 1 ( I min ) to I 2 ( I max ) during the time interval, TON .
So, using the expression for d i s d t during this time interval,
I 2 I 1 = I max I min = (Vs / L ) TON .
Similarly, the current varies linearly from I 2 ( I max ) to I 1 ( I min ) during the time interval, TOFF .
So, using the expression for d i s d t during this time interval,
I 2 I1 = I max I min = [(V0 Vs ) / L] TOFF .
Equating the two equations, (V s / L ) T ON = [(V 0 V s ) / L ] T OFF , from which the average
value of the output voltage is,
T
T
1
1
= Vs
= Vs
= Vs
V0 = Vs
1 k
TOFF
T TON
1 (TON / T )
The time period is T = TON + TOFF , and the duty ratio is,
k = (TON / T ) = [TON / (TON + TOFF )] , with its range as 1.0 k 0.0 . The ON time interval is
TON = k T . As stated in the previous case, the range of k is reduced. This is, because the
minimum value is higher than the minimum (0.0), and the maximum value is lower than the
maximum (1.0), for reasons given there, which are also valid here. As shown, the source current
is assumed to be continuous. The expression for the output voltage can be obtained by using
other procedures.
In this case, the output voltage is higher than the input voltage, as contrasted with the
previous case of buck converter (dc-dc). So, this is called boost converter (dc-dc), when a selfVersion 2 EE IIT, Kharagpur 6
commutated device is used as a switch. Instead, if thyristor is used in its place, this is termed as
step-up chopper. The variation (range) of the output voltage can be easily computed.
Buck-Boost Converters (dc-dc)

A buck-boost converter (dc-dc) is shown in Fig. 17.3. Only a switch is shown, for which a
device belonging to transistor family is generally used. Also, a diode is used in series with the
load. The connection of the diode may be noted, as compared with its connection in a boost
converter (Fig. 17.2a). The inductor, L is connected in parallel after the switch and before the
diode. The load is of the same type as given earlier. A capacitor, C is connected in parallel with
the load. The polarity of the output voltage is opposite to that of input voltage here.
When the switch, S is put ON, the supply current ( is ) flows through the path, Vs , S and L,
during the time interval, TON . The currents through both source and inductor ( i L ) increase and
are same, with ( d i L d t ) being positive. The polarity of the induced voltage is same as that of
the input voltage. The equation for the circuit is,
di
d i L Vs
=
Vs = L L
or,
dt
dt
L
Is
I0
Switch
Vs
IL
L
O
A
D
V0
+
Fig. 17.3(a): Buck-boost converter (dc-dc)
IL2
IL1
TON
2T
TOFF
Fig. 17.3(b): Inductor current (iL) waveform
Then, the switch, S is put OFF. The inductor current tends to decrease, with the polarity of
the induced emf reversing. ( d i L d t ) is negative now, the polarity of the output voltage, V0
being opposite to that of the input voltage, Vs . The path of the current is through L, parallel
combination of load & C, and diode D, during the time interval, TOFF . The output voltage
remains nearly constant, as the capacitor is connected across the load.
The equation for the circuit is,

di
d i L V0
L L = V0
=
or,
dt
dt
L
The inductor current waveform is shown in Fig. 17.3b. As stated earlier, the current varies
linearly from I L1 to I L 2 during the time interval, TON . Note that I L1 and I L 2 are the minimum
and maximum values of the inductor current respectively. So, using the expression for d i L d t
during this time interval, I L 2 I L1 = (Vs / L ) TON .
Similarly, the current varies linearly from I L 2 to I L1 during the time interval, TOFF . So, using
the expression for d i L d t during this time interval, I L 2 I L1 = (V0 / L ) TOFF .

Equating the two equations,
the output voltage is,
T
T
V0 = Vs ON = Vs ON
TOFF
T TON
The time period is T = TON
(V s
/ L ) T ON = (V 0 / L ) T OFF , from which the average value of
(TON / T )
k
= Vs
= Vs
1 k
1 (TON / T )
+ TOFF , and the duty ratio is,
k = (TON / T ) = [TON / (TON + TOFF )] . The ON time interval is TON = k T . It may be observed that,
for the range 0 k > 0.5 , the output voltage is lower than the input voltage, thus, making it a
buck converter (dc-dc). For the range 0.5 > k 1.0 , the output voltage is higher than the input
voltage, thus, making it a boost converter (dc-dc). For k = 0.5 , the output voltage is equal to the
input voltage. So, this circuit can be termed as a buck-boost converter. Also it may be called as
step-up/down chopper. It may be noted that the inductor current is assumed to be continuous.
The range of k is somewhat reduced due to the reasons given earlier. The expression for the
output voltage can be obtained by using other procedures.
Control Strategies
In all cases, it is shown that the average value of the output voltage can be varied. The two
types of control strategies (schemes) are employed in all cases. These are:
(a) Time-ratio control, and (b) Current limit control.
Time-ratio Control
In the time ratio control the value of the duty ratio, k = TON / T is varied. There are two ways,
which are constant frequency operation, and variable frequency operation.
Constant Frequency Operation

In this control strategy, the ON time, TON is varied, keeping the frequency ( f = 1 / T ), or
time period T constant. This is also called as pulse width modulation control (PWM). Two cases
with duty ratios, k as (a) 0.25 (25%), and (b) 0.75 (75%) are shown in Fig. 17.4. Hence, the
output voltage can be varied by varying ON time, TON .
Load-voltage
v0
TON
TOFF
V0
k = 0.25
V0
v0
TON
k = 0.75
TOFF
Fig. 17.4: Pulse-width modulation control (constant frequency)
Variable Frequency Operation

In this control strategy, the frequency ( f = 1 / T ), or time period T is varied, keeping either
(a) the ON time, TON constant, or (b) the OFF time, TOFF constant. This is also called as
frequency modulation control. Two cases with (a) the ON time, TON constant, and (b) the OFF
time, TOFF constant, with variable frequency or time period ( T ), are shown in Fig. 17.5. The
output voltage can be varied in both cases, with the change in duty ratio, k = TON / T .
v0
TON
k = 0.25
t
v0
TON
k = 0.75
TOFF
T
(a) Constant TON
v0
TOFF
k = 0.25
TON
T
Load voltage
v0
TOFF
TON
k = 0.75
t
T
(b) Constant TOFF
Fig. 17.5: Output voltage waveforms for variable frequency system
There are major disadvantages in this control strategy. These are:
(a) The frequency has to be varied over a wide range for the control of output voltage in
frequency modulation. Filter design for such wide frequency variation is, therefore, quite
difficult.
(b) For the control of a duty ratio, frequency variation would be wide. As such, there is a
possibly of interference with systems using certain frequencies, such as signaling and
telephone line, in frequency modulation technique.
(c) The large OFF time in frequency modulation technique, may make the load current
discontinuous, which is undesirable.
Thus, the constant frequency system using PWM is the preferred scheme for dc-dc converters
(choppers).
Current Limit Control

As can be observed from the current waveforms for the types of dc-dc converters described
earlier, the current changes between the maximum and minimum values, if it (current) is
continuous. In the current limit control strategy, the switch in dc-dc converter (chopper) is turned
ON and OFF, so that the current is maintained between two (upper and lower) limits. When the
current exceed upper (maximum) limit, the switch is turned OFF. During OFF period, the current
freewheels in say, buck converter (dc-dc) through the diode, D F , and decreases exponentially.
When it reaches lower (minimum) limit, the switch is turned ON. This type of control is
possible, either with constant frequency, or constant ON time, TON . This is used only, when the
load has energy storage elements, i.e. inductance, L. The reference values are load current or
load voltage. This is shown in Fig. 17.6. In this case, the current is continuous, varying between
I max and I min , which decides the frequency used for switching. The ripple in the load current can
be reduced, if the difference between the upper and lower limits is reduced, thereby making it
minimum. This in turn increases the frequency, thereby increasing the switching losses.
I max
i0
I min
t
v0
TON
TOFF
T
Fig. 17.6: Current limit control
In this lesson, first one in this module (#3), the three basic circuits buck, boost and buckboost, of dc-dc converters (choppers) are presented, along with the operation and the derivation
of the expressions for the output voltage in each case, assuming continuous conduction. The
different strategies employed for their control are discussed. In the next lesson second one, the
expression for the maximum and currents for continuous conduction in buck dc-dc converter will
be derived.
Operation
nal Amplifieers:
The operrational amplifier is a dirrect-coupled
d high gain am
mplifier usaable from 0 too over 1MH
H Z to
which feeedback is ad
dded to contrrol its overalll response ccharacteristicc i.e. gain annd bandwidthh.
The op-aamp exhibits the gain dow
wn to zero frequency.
fr
Such direect coupled (dc)
(
amplifieers do not usse blocking ((coupling annd by pass) ccapacitors sinnce
these would reduce th
he amplificaation to zero at zero frequuency. Largge by pass caapacitors mayy be
used but it is not possible to fabriicate large capacitors onn a IC chip. T
The capacitoors fabricatedd are
usually leess than 20 pf.
p Transisto
or, diodes and resistors ar
are also fabriicated on thee same chip.
Differential Amplifiiers:
Differenttial amplifierr is a basic building
b
blocck of an op-aamp. The funnction of a ddifferential
amplifierr is to ampliffy the differeence between
n two input signals.
How the differential amplifier is developed? Let us consiider two em
mitter-biased circuits as shhown
in fig. 1.
Fig. 1
The two transistors Q1 and Q2 haave identical characteristtics. The resiistances of thhe circuits are
equal, i.ee. RE1 = R E2, RC1 = R C2 and the mag
gnitude of +V
VCC is equall to the magnnitude of V
VEE.
These vo
oltages are measured
m
with
h respect to ground.
To make a differentiaal amplifier, the two circcuits are connnected as shhown in fig. 1. The two +
+VCC
and VEEE supply term
minals are made
m
common
n because thhey are samee. The two em
mitters are aalso
connected and the paarallel combiination of RE1
s replaced byy a resistance RE. The tw
wo
E and RE2 is
input sign
nals v1 & v2 are applied at the base of
o Q1 and at the base of Q2. The outpput voltage iis
taken bettween two co
ollectors. Th
he collector resistances
r
aare equal andd therefore ddenoted by RC =
RC1 = RC2
C .
Ideally, the
t output vo
oltage is zero
o when the tw
wo inputs arre equal. Whhen v1 is greaater then v2 tthe
output vo
oltage with the
t polarity shown
s
appeaars. When v1 is less thann v2, the outpput voltage hhas
the opposite polarity.
onfigurationss.
The diffeerential ampllifiers are off different co
The four differential amplifier co
onfigurationss are followiing:
1.
2.
3.
4.
Dual inputt, balanced output

o
differrential amplifier.
Dual inputt, unbalanced output diffferential ampplifier.
Single input balanced output diffe rential ampllifier.
Single input unbalanceed output diffferential am
mplifier.
Fig. 2
These co
onfigurationss are shown in
i fig. 2, and
d are definedd by numberr of input siggnals used annd
the way an
a output vo
oltage is meaasured. If usee two input ssignals, the cconfigurationn is said to bbe
dual inpu
ut, otherwisee it is a singlee input confi
figuration. O
On the other hhand, if the ooutput voltagge is
measured
d between tw
wo collectorss, it is referreed to as a baalanced outpuut because bboth the
collectors are at the same
s
dc poteential w.r.t. ground.
g
If thhe output is m
measured at one of the
und, the conffiguration is called an unnbalanced ouutput.
collectors w.r.t. grou
A multisttage amplifier with a dessired gain caan be obtaineed using direect connectioon between
successiv
ve stages of differential
d
amplifiers.
a
The
T advantagge of direct ccoupling is tthat it removves
the lowerr cut off freq
quency impo
osed by the coupling
c
cappacitors, and they are theerefore, capaable
of ampliffying dc as well
w as ac inp
put signals.
Differential Input Resistance:
R
Differenttial input ressistance is deefined as thee equivalent rresistance thhat would bee measured aat
either inp
put terminal with the oth
her terminal grounded.
g
T
This means thhat the inputt resistance Ri1
seen from
m the input signal
s
sourcee v1 is determ
mined with thhe signal souurce v2 set aat zero. Simillarly,
the input signal v1 is set at zero to
o determine the input ressistance Ri2 seen from thhe input signnal
source v2. Resistancee RS1 and RS2 are ignored
d because thhey are very small.
Substitutting ie1,
Similarly
y,
The facto
or of 2 arisess because thee re' of each transistor is in series.
To get veery high inpu
ut impedance with differrential ampliifier is to usee Darlingtonn transistors.
Another ways is to use FET.
Output Resistance:
R
Output reesistance is defined
d
as th
he equivalentt resistance tthat would bbe measured at output
terminal with respectt to ground. Therefore, th
he output ressistance RO11 measured bbetween colllector
C1 and grround is equ
ual to that of the collector resistance RC. Similarlly the outputt resistance RO2
measured
d at C2 with respect to grround is equ
ual to that of the collector resistor RC.
RO1 = RO2
O = RC
(E-5)
(
The curreent gain of th

he differentiial amplifier is undefinedd. Like CE aamplifier thee differentiall
amplifierr is a small signal ampliffier. It is gen
nerally used as a voltage amplifier annd not as currrent
or powerr amplifier.
Examplee - 1
The follo
owing speciffications are given for the dual input,, balanced-ooutput differeential ampliffier:
RC = 2.2 k, RB = 4.7 k, Rin 1 = Rin 2 = 50
, +VCC= 10V
V, -VEE = -110 V, dc =1000 and VBE =
0.715V.
mine the volltage gain.
a. Determ
b. Determ
mine the inp
put resistancee
c. Determ
mine the outtput resistancce.
Solution
n:
(a). The parameters
p
of
o the ampliffiers are sam
me as discusssed in exampple-1 of lectuure-1. The
operating
g point of thee two transisstors obtaineed in lecture--1 are given below
ICQ = 0.9
988 mA
VCEQ=8.5
54V
The ac em
mitter resistaance
Therefore, substitutin
ng the known
n values in voltage
v
gain equation (E
E-2), we obtaain
b). The in
nput resistan
nce seen from
m each inputt source is giiven by (E-33) and (E-4)::
(c) The output

o
resistaance seen loo
oking back into
i
the circuuit from eachh of the two output term
minals
is given by
b (E-5)
Ro1 = Ro22 = 2.2 k
Examplee - 2
For the dual
d input, baalanced outp
put differentiial amplifierr of Examplee-1:
a. Determ
mine the outtput voltage (vo) if vin 1 = 50mV peakk to peak (ppp) at 1 kHz aand
vin 2 = 20 mV pp at
a 1 kHz.
b. What is the maxim
mum peal to peak outputt voltage witthout clippinng?
Solution
n:
(a) In Example-1
E
we have deterrmined the voltage gain oof the dual innput, balancced output
differentiial amplifierr. Substitutin
ng this voltag
ge gain (Ad = 86.96) andd given valuees of input
voltages in (E-1), wee get
(b) Notee that in casee of dual inp

put, balanced
d output diffe
ference ampllifier, the outtput voltage vo is
measured
d across the collector. Th
herefore, to calculate
c
thee maximum ppeak to peakk output volttage,
we need to determinee the voltagee drop acrosss each collecctor resistor:
A, we get
Substitutting IC = ICQ = 0.988 mA
This meaans that the maximum

m
ch
hange in volttage across eeach collectoor resistor is 2.17 (ideaally)
or 4.34 VPP. In other words, the maximum
m
peeak to peak ooutput voltagge with out cclipping is (22)
(4.34) = 8.68 VPP.
Module
1
Power Semiconductor
Devices
Lesson
1
Power Electronics
Introduction
This lesson provides the reader the following:
(i)
(ii)
(iii)
(iv)
(v)
Create an awareness of the general nature of Power electronic equipment;

Brief idea about topics of study involved,
The key features of the principal Power Electronic Devices;
An idea about which device to choose for a particular application.
A few issues like base drive and protection of PE devices and equipment common to
most varieties.
Power Electronics is the art of converting electrical energy from one form to another in an
efficient, clean, compact, and robust manner for convenient utilisation.
A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speed
induction-machine drive offers a comfortable ride and stops exactly at the floor level. Behind the
scene it consumes less power with reduced stresses on the motor and corruption of the utility
mains.
Fig. 1.1 The block diagram of a typical Power Electronic converter

Power Electronics involves the study of
Power semiconductor devices - their physics, characteristics, drive requirements and their
protection for optimum utilisation of their capacities,
Power converter topologies involving them,
Control strategies of the converters,
Digital, analogue and microelectronics involved,
Capacitive and magnetic energy storage elements,
Rotating and static electrical devices,
Quality of waveforms generated,
Electro Magnetic and Radio Frequency Interference,
Thermal Management
The typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject.
How is Power electronics distinct from linear electronics?

It is not primarily in their power handling capacities.
While power management IC's in mobile sets working on Power Electronic principles are
meant to handle only a few milliwatts, large linear audio amplifiers are rated at a few thousand
watts.
The utilisation of the Bipolar junction transistor, Fig. 1.2 in the two types of amplifiers best
symbolises the difference. In Power Electronics all devices are operated in the switching mode either 'FULLY-ON' or 'FULLY-OFF' states. The linear amplifier concentrates on fidelity in
signal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3.
Saturation and cutoff zones in the VCE - IC plane are avoided. In a Power electronic switching
amplifier, only those areas in the VCE - IC plane which have been skirted above, are suitable. Onstate dissipation is minimum if the device is in saturation (or quasi-saturation for optimising
other losses). In the off-state also, losses are minimum if the BJT is reverse biased. A BJT switch
will try to traverse the active zone as fast as possible to minimise switching losses.
Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage)
amplifier stage and (b) switching (power) amplifier
Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a
switching amplifier
Linear operation
Active zone selected:
Good linearity between input/output
Switching operation
Active zone avoided :
High losses, encountered only during
transients
Saturation & cut-off zones avoided: poor Saturation & cut-off (negative bias) zones
linearity
selected: low losses
Transistor biased to operate around No concept of quiescent point
quiescent point
Common emitter, Common collector, Transistor driven directly at base - emitter
common base modes
and load either on collector or emitter
Output transistor barely protected
Switching-Aid-Network (SAN) and other
protection to main transistor
Utilisation of transistor rating of secondary Utilisation of transistor rating optimised
importance
An example illustrating the linear and switching solutions to a power supply specification will
emphasise the difference.
Spec: Input : 230 V, 50 Hz, Output:
12 V regulated DC, 20 W
Ferrite core HF transfr:
Light, efficient
Series regulator high losses

230 V
230 V
Line freq transformer:

heavy, lossy
(b)
(a)
High-freq Duty-ratio
(ON/OFF) control
- low losses
Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification
above
The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the
supply voltage to 12-0-12 V through a power frequency transformer. The output would be
rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated
using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance
of the voltage between the output of the rectifier and the output drops across the regulator device
which also carries the full load current. The power loss is therefore considerable. Also, the stepdown iron-core transformer is both heavy, and lossy. However, only twice-line-frequency ripples
appear at the output and material cost and technical know-how required is low.
In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line
voltage is rectified and then isolated, stepped-down and regulated. A ferrite-core high-frequency
(HF) transformer is used. Losses are negligible compared to the first solution and the converter is
extremely light. However significant high frequency (related to the switching frequency) noise
appear at the output which can only be minimised through the use of costly 'grass' capacitors.
Power Semiconductor device - history

Power electronics and converters utilizing them made a head start when the first device the
Silicon Controlled Rectifier was proposed by Bell Labs and commercially produced by General
Electric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and the
robust and compact SCR first started replacing it in the rectifiers and cycloconverters. The
necessity arose of extending the application of the SCR beyond the line-commutated mode of
action, which called for external measures to circumvent its turn-off incapability via its control
terminals. Various turn-off schemes were proposed and their classification was suggested but it
became increasingly obvious that a device with turn-off capability was desirable, which would
permit it a wider application. The turn-off networks and aids were impractical at higher powers.
The Bipolar transistor, which had by the sixties been developed to handle a few tens of
amperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superior
to the SCR in its turn-off capability, which could be exercised via its control terminals. This
permitted the replacement of the SCR in all forced-commutated inverters and choppers.
However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor
and the high base currents required to switch the Bipolar spawned the Darlington. Three or more
stage Darlingtons are available as a single chip complete with accessories for its convenient
drive. Higher operating frequencies were obtainable with a discrete Bipolars compared to the
'fast' inverter-grade SCRs permitting reduction of filter components. But the Darlington's
operating frequency had to be reduced to permit a sequential turn-off of the drivers and the main
transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use.
The Power MOSFET burst into the scene commercially near the end seventies. This device
also represents the first successful marriage between modern integrated circuit and discrete
power semiconductor manufacturing technologies. Its voltage drive capability giving it again a
higher gain, the ease of its paralleling and most importantly the much higher operating
frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub-10 KW range
mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the
MOSFET reduced its price vis--vis the Bipolar also. However, being a majority carrier device
its on-state voltage is dictated by the RDS(ON) of the device, which in turn is proportional to about
VDSS2.3 rating of the MOSFET. Consequently, high-voltage MOSFETS are not commercially
viable.
Improvements were being tried out on the SCR regarding its turn-off capability mostly by
reducing the turn-on gain. Different versions of the Gate-turn-off device, the Gate turn-off
Thyristor (GTO), were proposed by various manufacturers - each advocating their own symbol
for the device. The requirement for an extremely high turn-off control current via the gate and
the comparatively higher cost of the device restricted its application only to inverters rated above
a few hundred KVA.
The lookout for a more efficient, cheap, fast and robust turn-off-able device proceeded in
different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated
Gate Bipolar Transistor (IGBT) basically a MOSFET driven Bipolar from its terminal
characteristics has been a successful proposition with devices being made available at about 4
KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw
it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET
has been able to continue in the sub 10 KVA range primarily because of its high switching
frequency. The IGBT has also pushed up the GTO to applications above 2-5 MVA.
Subsequent developments in converter topologies especially the three-level inverter
permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the
GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based
converters are possible at the highest range where line-commutated or load-commutated
converters were the only solution. The surge current, the peak repetition voltage and I2t ratings
are applicable only to the thyristors making them more robust, specially thermally, than the
transistors of all varieties.
1200V Version 3 ASIPM
Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by
some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A
IEGT (injection-enhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated
Gate Commutated Thyristors) of ABB which are promising at the higher power ranges.
However these new devices must prove themselves before they are accepted by the industry at
large.
Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about
2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide
is the only wide band gap semiconductor among gallium nitride (GaN, EG = 3.4 eV), aluminum
nitride (AlN, EG = 6.2 eV), and silicon carbide that possesses a high-quality native oxide suitable
for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times
higher than in silicon. This is important for high-voltage power switching transistors. For
example, a device of a given size in SiC will have a blocking voltage 8 times higher than the
same device in silicon. More importantly, the on-resistance of the SiC device will be about two
decades lower than the silicon device. Consequently, the efficiency of the power converter is
higher. In addition, SiC-based semiconductor switches can operate at high temperatures
(~600 C) without much change in their electrical properties. Thus the converter has a higher
reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink
size. Moreover, the high frequency operating capability of SiC converters lowers the filtering
requirement and the filter size. As a result, they are compact, light, reliable, and efficient and
have a high power density. These qualities satisfy the requirements of power converters for most
applications and they are expected to be the devices of the future.
Ratings have been progressively increasing for all devices while the newer devices offer
substantially better performance. With the SCR and the pin-diodes, so called because of the
sandwiched intrinsic i-layer between the p and n layers, having mostly line-commutated
converter applications, emphasis was mostly on their static characteristics - forward and reverse
voltage blocking, current carrying and over-current ratings, on-state forward voltage etc and also
on issues like paralleling and series operation of the devices. As the operating speeds of the
devices increased, the dynamic (switching) characteristics of the devices assumed greater
importance as most of the dissipation was during these transients. Attention turned to the
development of efficient drive networks and protection techniques which were found to enhance
the performance of the devices and their peak power handling capacities. Issues related to
paralleling were resolved by the system designer within the device itself like in MOSFETS,
while the converter topology was required to take care of their series operation as in multi-level
converters.
The range of power devices thus developed over the last few decades can be represented as a
tree, Fig. 1.5, on the basis of their controllability and other dominant features.
POWER SEMICONDUCTOR
DEVICES
UNCONTROLLED
RECTIFIERS
POWER SILICON
DIODES
FREDS
SCHOTTKY
CONTROLLED
ACCESSORIES
REGENERATIVE
SCR
TRIAC
GTO
DIAC
Zenner
MOV
NON-REGENERATIVE
BJT
MOSFET
IGBT
INTEGRATED
IGCT
PIC
INTELLIGENT
POWER MODULES
Fig. 1.5 Power semiconductor device variety
Power Diodes
diF /dt
t0
t1
SNAPPY
t2
SOFT
to
Q1
Q2
IRM
VRM
Fig. 1.6 Typical turn-off dynamics of a soft and a 'snappy' diode'

Silicon Power diodes are the successors of Selenium rectifiers having significantly improved
forward characteristics and voltage ratings. They are classified mainly by their turn-off
(dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time - trr
(reverse recovery time) to recombine with opposite charges and neutralise. Large values of Qrr (=
Q1 + Q2) - the charge to be dissipated as a negative current when the and diode turns off and trr
(= t2 - t0) - the time it takes to regain its blocking features, impose strong current stresses on the
controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt
voltages on all associated power device in the converter because of load or stray inductances
present in the network. There are broadly three types of diodes used in Power electronic
applications:
Line-frequency diodes: These PIN diodes with general-purpose rectifier type applications, are
available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent overcurrent (surge rating about six times average current rating) and surge-voltage withstand
capability. They have relatively large Qrr and trr specifications.
Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's,
have significantly lower Qrr and trr (~ 1.0 sec). They are available at high powers and are
mainly used in association with fast controlled-devices as free-wheeling or DC-DC choppers and
rectifier applications. Fast recovery diodes also find application in induction heating, UPS and
traction.
Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any
Qrr.. However, they are available with voltage ratings up to a hundred volts only though current
ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom
from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no
competition in low voltage SPMS applications and in instrumentation.
Silicon Controlled Rectifier (SCR)

The Silicon Controlled Rectifier is the most popular of the thyristor family of four layer
regenerative devices. It is normally turned on by the application of a gate pulse when a forward
bias voltage is present at the main terminals. However, being regenerative or 'latching', it cannot
be turned off via the gate terminals specially at the extremely high amplification factor of the
gate. There are two main types of SCR's.
Converter grade or Phase Control thyristors These devices are the work horses of the
Power Electronics. They are turned off by natural (line) commutation and are reverse biased at
least for a few milliseconds subsequent to a conduction period. No fast switching feature is
desired of these devices. They are available at voltage ratings in excess of 5 KV starting from
about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are
built with series-parallel combination of these devices. Conduction voltages are device voltage
rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are
unsuitable for any 'forced-commutated' circuit requiring unwieldy large commutation
components.
The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years
borrowing emitter shorting and other techniques adopted for the faster variety. The requirement
for hard gate drives and di/dt limting inductors have been eliminated in the process.
Inverter grade thyristors: Turn-off times of these thyristors range from about 5 to 50 secs
when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly
used in circuits that are operated on DC supplies and no alternating voltage is available to turn
them off. Commutation networks have to be added to the basic converter only to turn-off the
SCR's. The efficiency, size and weight of these networks are directly related to the turn-off time,
tq of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite
a few commutation networks were designed and some like the McMurray-Bedford became
widely accepted.
Asymmetrical, light-activated, reverse conducting SCR's Quite a few varieties of the
basic SCR have been proposed for specific applications. The Asymmetrical thyristor is
convenient when reactive powers are involved and the light activated SCR assists in paralleling
or series operation.
MOSFET
The Power MOSFET technology has mostly reached maturity and is the most popular device
for SMPS, lighting ballast type of application where high switching frequencies are desired but
operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour)
with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared
manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency
applications, where the currents drawn by the equivalent capacitances across its terminals are
small, it can also be driven directly by integrated circuits. These capacitances are the main
hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of
its main terminals permit easy paralleling externally also. At high current low voltage
applications the MOSFET offers best conduction voltage specifications as the RDS(ON)
specification is current rating dependent. However, the inferior features of the inherent antiparallel diode and its higher conduction losses at power frequencies and voltage levels restrict its
wider application.
The IGBT
It is a voltage controlled four-layer device with the advantages of the MOSFET driver
and the Bipolar Main terminal. IGBTs can be classified as punch-through (PT) and non-punchthrough (NPT) structures. In the punch-through IGBT, a better trade-off between the forward
voltage drop and turn-off time can be achieved. Punch-through IGBTs are available up to about
1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more
robust than PT IGBTs particularly under short circuit conditions. However they have a higher
forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably
shaping the drive signal. This gives the IGBT a number of advantages: it does not require
protective circuits, it can be connected in parallel without difficulty, and series connection is
possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view
of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe
Operating Area devoid of a Second Breakdown region.
The GTO
The GTO is a power switching device that can be turned on by a short pulse of gate current and
turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode
current to be turned off. Hence there is no need for an external commutation circuit to turn it off.
Because turn-off is provided by bypassing carriers directly to the gate circuit, its turn-off time is
short, thus giving it more capability for highfrequency operation than thyristors. The GTO
symbol and turn-off characteristics are shown in Fig. 30.3. GTOs have the I2t withstand
capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs,
the critical aspects are proper design of the gate turn-off circuit and the snubber circuit.
Power Converter Topologies

A Power Electronic Converter processes the available form to another having a different
frequency and/or voltage magnitude. There can be four basic types of converters depending upon
the function performed:
CONVERSION
FROM/TO
NAME
FUNCTION
DC to DC
Chopper
Constant to variable DC or
variable to constant DC
DC to AC
Inverter
DC to AC of desired voltage and

frequency
AC to DC
AC to AC
SYMBOL
Rectifier
AC to unipolar (DC) current
Cycloconverter,
AC-PAC,
Matrix
converter
AC of desired frequency and/or

magnitude from generally line
AC
Base / gate drive circuit

All discrete controlled devices, regenerative or otherwise have three terminals. Two of these are
the Main Terminals. One of the Main Terminals and the third form the Control Terminal. The
amplification factor of all the devices (barring the now practically obsolete BJT) are quite high,
though turn-on gain is not equal to turn-off gain. The drive circuit is required to satisfy the
control terminal characteristics to efficiently tun-on each of the devices of the converter, turn
them off, if possible, again optimally and also to protect the device against faults, mostly overcurrents. Being driven by a common controller, the drives must also be isolated from each other
as the potentials of the Main Terminal which doubles as a Control terminal are different at
various locations of the converter. Gate-turn-off-able devices require precise gate drive
waveform for optimal switching. This necessitates a wave-shaping amplifier. This amplifier is
located after the isolation stage.
Thus separate isolated power supplies are also required for each Power device in the
converter (the ones having a common Control Terminal - say the Emitter in an IGBT - may
require a few less). There are functionally two types of isolators: the pulse transformer which
can transmit after isolation, in a multi-device converter, both the un-shaped signal and power and
optical isolators which transmit only the signal. The former is sufficient for a SCR without
isolated power supplies at the secondary. The latter is a must for practically all other devices.
Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR.
IGBT
Vref
COMPARATOR
TIMER
Fig. 1.7 Simple gate-drive and protection circuit for a stand-alone IGBT and a SCR
Protection of Power devices and converters

Power electronic converters often operate from the utility mains and are exposed to the
disturbances associated with it. Even otherwise, the transients associated with switching circuits
and faults that occur at the load point stress converters and devices. Consequently, several
protection schemes must be incorporated in a converter. It is necessary to protect both the Main
Terminals and the control terminals. Some of these techniques are common for all devices and
converters. However, differences in essential features of devices call for special protection
schemes particular for those devices. The IGBT must be protected against latching, and similarly
the GTO's turn-off drive is to be disabled if the Anode current exceeds the maximum permissible
turn-off-able current specification. Power semiconductor devices are commonly protected
against:
1.
2.
3.
4.
5.
6.
7.
8.
Over-current;
di/dt;
Voltage spike or over-voltage;
dv/dt ;
Gate-under voltage;
Over voltage at gate;
Excessive temperature rise;
Electro-static discharge;
Semiconductor devices of all types exhibit similar responses to most of the stresses, however
there are marked differences. The SCR is the most robust device on practically all counts. That it
has an I2t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably
selected, and in co-ordination with fast circuit breakers would mostly protect it. This sometimes
becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT
and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal
voltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further,
the transistors permit designed gate current waveforms to minimise voltage spikes as a
consequence of sharply rising Main terminal currents. Gate resistances have significant effect on
turn-on and turn-off times of these devices - permitting optimisation of switching times for the
reduction of switching losses and voltage spikes.
Protection schemes for over-voltages - the prolonged ones and those of short duration - are
guided by the energy content of the surges. Metal Oxide Varistors (MOV's), capacitive dynamic
voltage-clamps and crow-bar circuits are some of the strategies commonly used. For high dv/dt
stresses, which again have similar effect on all devices, R-C or R-C-D clamps are used
depending on the speed of the device. These 'snubbers' or 'switching-aid-networks', additionally
minimise switching losses of the device - thus reducing its temperature rise.
Gates of all devices are required to be protected against over-voltages (typically + 20 V)
specially for the voltage driven ones. This is achieved with the help of Zener clamps - the zener
being also a very fast-acting device.
Protection against issues like excessive case temperatures and ESD follow well-set practices.
Forced-cooling techniques are very important for the higher rated converters and whole
environments are air-cooled to lower the ambient.
Objective type questions

Qs#1 Which is the Power semiconductor device having
a)
b)
c)
d)
Highest switching speed;

Highest voltage / current ratings;
Easy drive features;
Can be most effectively paralleled;
e) Can be protected against over-currents with a fuse;
f) Gate-turn off capability with regenerative features;
g) Easy drive and High power handling capability
Ans:
a) MOSFET; b) SCR; c) MOSFET; d) MOSFET; e) SCR ; (f) GTO; (g) IGBT
Qs#2 An SCR requires 50 mA gate current to switch it on. It has a resistive load and is supplied
from a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if the
driver circuit supply voltage is 10 V and the gate-cathode drop is about 1 V.
Ans: The most important ratings of the Pulse transformer are its volt-secs rating, the isolation
voltage and the turns ratio.
The volt-secs is decided by the product of the primary pulse-voltage multiplied by the period for
which the pulse is applied to the winding
If the primary pulse voltage = (Supply voltage drive transistor drop)
The turn-on time of he SCR may be in the range 50 secs for an SCR of this rating.
Consequently the volt secs may be in the range of 9 x 50 = 450 volt-secs
= 2.5 KV, IM = 150 mA
The Pulse transformer may be chosen as: 1:1, 450 Vs, Visol
The circuit shown in Fig. 1.7 may be used. Diodes 1N4002
Series resistance
= (Supply voltage drive transistor drop gate-cathode drop)/100mA
= (10 1 1) / 100 E-3
= 80 Ohm
= 49 or 57 Ohm (nearest available lower value)
Module
1
Power Semiconductor
Devices
Lesson
4
Thyristors and Triacs
Instructional objects
On completion the student will be able to
Explain the operating principle of a thyristor in terms of the two transistor analogy.
Draw and explain the i-v characteristics of a thyristor.
Draw and explain the gate characteristics of a thyristor.
Interpret data sheet rating of a thyristor.
Draw and explain the switching characteristics of a thyristor.
Explain the operating principle of a Triac.
4.1 Introduction
Although the large semiconductor diode was a predecessor to thyristors, the modern power
electronics area truly began with advent of thyristors. One of the first developments was the
publication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell
Laboratories, probably for use in Bells Signal application. However, engineers at General
Electric quickly recognized its significance to power conversion and control and within nine
months announced the first commercial Silicon Controlled Rectifier in 1957. This had a
continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also
known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest
beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv
and continuous current rating in excess of 4kA are available. They have reigned supreme for two
entire decades in the history of power electronics. Along the way a large number of other devices
with broad similarity with the basic thyristor (invented originally as a phase control type device)
have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch
(SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting
Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO).
From the construction and operational point of view a thyristor is a four layer, three terminal,
minority carrier semi-controlled device. It can be turned on by a current signal but can not be
turned off without interrupting the main current. It can block voltage in both directions but can
conduct current only in one direction. During conduction it offers very low forward voltage drop
due to an internal latch-up mechanism. Thyristors have longer switching times (measured in tens
of s) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using
a control input, have all but eliminated thyristors in high frequency switching applications
involving a DC input (i.e, choppers, inverters). However in power frequency ac applications
where the current naturally goes through zero, thyristor remain popular due to its low conduction
loss its reverse voltage blocking capability and very low control power requirement. In fact, in
very high power (in excess of 50 MW) AC DC (phase controlled converters) or AC AC
(cyclo-converters) converters, thyristors still remain the device of choice.
4.2 Constructional Features of a Thyristor

Fig 4.1 shows the circuit symbol, schematic construction and the photograph of a typical
thyristor.
A
A
p
np
(a)
n+
n+
K
G
(c)
(b)
Fig. 4.1: Constructional features of a thysistor
(a) Circuit Symbol, (b) Schematic Construction, (c) Photograph
As shown in Fig 4.1 (b) the primary crystal is of lightly doped n- type on either side of
which two p type layers with doping levels higher by two orders of magnitude are grown. As in
the case of power diodes and transistors depletion layer spreads mainly into the lightly doped nregion. The thickness of this layer is therefore determined by the required blocking voltage of the
device. However, due to conductivity modulation by carriers from the heavily doped p regions
on both side during ON condition the ON state voltage drop is less. The outer n+ layers are
formed with doping levels higher then both the p type layers. The top p layer acls as the Anode
terminal while the bottom n+ layers acts as the Cathode. The Gate terminal connections are
made to the bottom p layer.
As it will be shown later, that for better switching performance it is required to maximize
the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are
finely distributed between gate contacts of the p type layer. An Involute structure for both the
gate and the cathode regions is a preferred design structure.
4.3 Basic operating principle of a thyristor

The underlying operating principle of a thyristor is best understood in terms of the two
transistor analogy as explained below.
A
IA
Q1 (1)
J1
iC2
iC1
J2
p
n+
n+
J3
n-
p
p
J2
J3
n+
IG
(2) Q2
IK
K
K
K
(a)
(b)
(c)
Fig. 4.2: Two transistor analogy of a thyristor construction.

(a) Schematic Construction, (b) Schematic division in component
transistor
(c) Equivalent circuit in terms of two transistors.
a) Schematic construction,
b) Schematic division in component transistor
c) Equivalent circuit in terms of two transistors.
Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode
positive with respect to the cathode and the gate terminal open. With this voltage polarity J1
& J3 are forward biased while J2 reverse biased.
Under this condition.
ic1 = 1 I A + I co1
ic 2 = 2 I K + I co2
( 4.1)
( 4.2 )
Where 1 & 2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse
saturation currents of the CB junctions of Q1 & Q2 respectively.
Now from Fig 4.2 (c).
i c1 + i c2 = I A
& IA = IK
Combining Eq 4.1 & 4.4
IA =
( 4.3)
( 4.4 ) ( I G = 0 )
I co1 + I co2
I co
=
1- ( 1 + 2 ) 1- ( 1 + 2 )
( 4.5 )
Where I co I co1 + I co2 is the total reverse leakage current of J2

Now as long as VAK is small Ico is very low and both 1 & 2 are much lower than unity.
Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increased
up to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanche
multiplication process. As Ico increases both 1 & 2 increase and 1 + 2 approaches unity.
Under this condition large anode current starts flowing, restricted only by the external load
resistance. However, voltage drop in the external resistance causes a collapse of voltage across
the thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltage
drop across the device settles down to approximately equivalent to a diode drop. The thyristor is
said to be in ON state.
Just after turn ON if Ia is larger than a specified current called the Latching Current IL, 1 and
2 remain high enough to keep the thyristor in ON state. The only way the thyristor can be
turned OFF is by bringing IA below a specified current called the holding current (IH) where
upon 1 & 2 starts reducing. The thyristor can regain forward blocking capacity once excess
stored charge at J2 is removed by application of a reverse voltage across A & K (ie, K positive
with respect A).
It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to
cathode) without increasing the forward voltage across the device up to the forward break-over
level. With a positive gate current equation 4.4 can be written as
IK = IA + IG
( 4.6 )
Combining with Eqns. 4.1 to 4.3 I A =
2 I G + I co
1- ( 1 + 2 )
( 4.7 )
Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence
VAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which a
thyristor is turned ON.
When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.)
junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the junction J3 has a
very low reverse break down voltage since both the n+ and p regions on either side of this
junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by
junction J1. The maximum value of the reverse voltage is restricted by
a) The maximum field strength at junction J1 (avalanche break down)
b) Punch through of the lightly doped n- layer.
Since the p layers on either side of the n- region have almost equal doping levels the avalanche
break down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break
down voltage of a thyristor are almost equal.Up to the break down voltage of J1 the reverse
current of the thyristor remains practically constant and increases sharply after this voltage.
Thus, the reverse characteristics of a thyristor is similar to that of a single diode.
If a positive gate current is applied during reverse bias condition, the junction J3 becomes
forward biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the roles
of their respective emitters and collectors interchanged. However, the reverse 1 & 2 being
significantly smaller than their forward counterparts latching of the thyristor does not occur.
However, reverse leakage current of the thyristor increases considerably increasing the OFF state
power loss of the device.
If a forward voltage is suddenly applied across a reverse biased thyristor, there will be
considerable redistribution of charges across all three junctions. The resulting current can
become large enough to satisfy the condition 1 + 2 = 1 and consequently turn on the thyristor.
This is called dv turn on of a thyristor and should be avoided.
dt
Exercise 4.1
1)

i. A thyristor is a ________________ carrier semi controlled device.
ii. A thyristor can conduct current in ________________ direction and block voltage in
________________ direction.
iii. A thyristor can be turned ON by applying a forward voltage greater than forward
________________ voltage or by injecting a positive ________________ current pulse
under forward bias condition.
iv. To turn OFF a thyristor the anode current must be brought below ________________
current and a reverse voltage must be applied for a time larger than ________________
time of the device.
v. A thyristor may turn ON due to large forward ________________.
Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off;
(v) dv
dt
2.
Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias
condition (i. e cathode positive with respect to anode)?
Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when a
reverse voltage is applied across the device the roles of the emitters and collectors of the
constituent transistors will reverse. With a positive gate pulse applied it may appear that the
device should turn ON as in the forward direction. However, the constituent transistors have very
low current gain in the reverse direction. Therefore no reasonable value of the gate current will
satisfy the turn ON condition (i.e.1 + 2 = 1). Hence the device will not turn ON.
4.4 Steady State Characteristics of a Thyristor

4.4.1 Static output i-v characteristics of a thyristor
IA
VAK
VBRF
IA
K
ig
Ig
VBRR
Is
IH
VBRF
IL
ig1 ig2 ig3 ig4
VAK
VH
ig4 > ig3 > ig2 > ig1 > ig = 0
ig4 > ig3 > ig2 > ig1 > ig = 0
Fig. 4.3: Static output characteristics of a Thyristor

The circuit symbol in the left hand side inset defines the polarity conventions of the variables
used in this figure.
With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anode
current starts flowing. However, at VBRF forward break over takes place and the voltage across
the thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK)
remains almost constant at VH (1-1.5v) while the anode current is determined by the external
load.
The magnitude of gate current has a very strong effect on the value of the break over voltage as
shown in the figure. The right hand side figure in the inset shows a typical plot of the forward
break over voltage (VBRF) as a function of the gate current (Ig)
After Turn ON the thyristor is no more affected by the gate current. Hence, any current pulse
(of required magnitude) which is longer than the minimum needed for Turn ON is sufficient to
effect control. The minimum gate pulse width is decided by the external circuit and should be
long enough to allow the anode current to rise above the latching current (IL) level.
The left hand side of Fig 4.3 shows the reverse i-v characteristics of the thyristor. Once the
thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding
current (IH). The gate terminal has no control over the turn OFF process. In ac circuits with
resistive load this happens automatically during negative zero crossing of the supply voltage.
This is called natural commutation or line commutation. However, in dc circuits some
arrangement has to be made to ensure this condition. This process is called forced
commutation.
During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse
voltage reaches reverse break down voltage (VBRR). At this point current starts rising sharply.
Large reverse voltage and current generates excessive heat and destroys the device. If ig > 0
during reverse bias condition the reverse saturation current rises as explained in the previous
section. This can be avoided by removing the gate current while the thyristor is reverse biased.
The static output i-v characteristics of a thyristor depends strongly on the junction temperature as
shown in Fig 4.4.
VBRF
IA
Tj =
150 135
25 75 125
25 75 125 150 Tj
VAK
Tj = 125 75 25
135 150
Fig. 4.4: Effect of junction temperature (Tj) on the output

i v characteristics of a thyristor.
4.4.2 Thyristor Gate Characteristics

The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop
and low reverse break down voltage. This characteristic usually is not unique even within the
same family of devices and shows considerable variation from device to device. Therefore,
manufacturers data sheet provides the upper and lower limit of this characteristic as shown in
Fig 4.5.
Vg
Vg max
d
Rg
Vg
Pgav Max
Load line
Vg min
ig
S2
Pgm
Vng
S1
Ig max
Ig
Ig min
Fig. 4.5: Gate characteristics of a thyristor.
Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximum
average gate power dissipation limit ( Pgav Max ) . These limits should not be exceeded in order to
avoid permanent damage to the gate cathode junction. There are also minimum limits of Vg
(Vgmin) and Ig (Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (Vng) is
also specified by the manufacturers of thyristors. All spurious noise signals should be less than
this voltage Vng in order to prevent unwanted turn on of the thyristor. The useful gate drive area
of a thyristor is then b c d e f g h.
Referring to the gate drive circuit in the inset the equation of the load line is given by
Vg = E - Rgig
A typical load line is shown in Fig 4.5 by the line S1 S2.
The actual operating point will be some where between S1 & S2 depending on the particular
device.
For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav
curve without violating Vg
Max
Max
or IgMax ratings. Therefore, for a dc source E c f represents the
optimum load line from which optimum values of E & Rg can be determined.
It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power
dissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turn
reduces the turn on time of the thyristor. The value of Pgm depends on the pulse width (TON) of
the gate current pulse. TON should be larger than the turn on time of the thyristor. For TON larger
than 100 s, average power dissipation curve should be used. For TON less than 100 s the
following relationship should be maintained.
Pgm Pgav
Max
( 4.9 )
Where = TON f p, f p = pulse frequency.

The magnitude of the gate voltage and current required for triggering a thyristor is inversely
proportional to the junction temperature.
The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to the
cathode) voltage specification. If there is a possibility of the reverse gate cathode voltage
exceeding this limit a reverse voltage protection using diode as shown in Fig 4.6 should be used.
A
Rg
G
E
E
K
(a)
(b)
Fig. 4.6: Gate Cathode reverse voltage protection circuit.

Exercise 4.2
1)

i.
Forward break over voltage of a thyristor decreases with increase in the

________________ current.
ii.
Reverse ________________ voltage of a thyristor is ________________ of the gate

current.
iii.
Reverse saturation current of a thyristor ________________ with gate current.
iv.
In the pulsed gate current triggering of a thyristor the gate current pulse width should be
larger than the ________________ time of the device.
v.
To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate
and the cathode must be less than the gate ________________ voltage.
Answer: (i) gate; (ii) break down, independent; (iii) increases; (iv) Turn ON; (v) nontrigger.
2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggered
with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gate
cathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude.
Answer: On period of the gate current pulse is
TON = TS =
fs
0.4
sec = 40 s < 100 s.
10 4
Therefore, pulsed gate power dissipation limit Pgm can be used. From Equation 4.9
Pgm Pgav ( Max )

0.2
watts = .5watts
.5
= 0.5Amps.
I g Max =
1
or Pgm
But Pgm = Ig Vg; Vg = 1V
4.5 Thyristor ratings

Some useful specifications of a thyristor related to its steady state characteristics as found in a
typical manufacturers data sheet will be discussed in this section.
4.5.1 Voltage ratings

Peak Working Forward OFF state voltage (VDWM): It specifics the maximum forward (i.e,
anode positive with respect to the cathode) blocking state voltage that a thyristor can withstand
during working. It is useful for calculating the maximum RMS voltage of the ac network in
which the thyristor can be used. A margin for 10% increase in the ac network voltage should be
considered during calculation.
Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transient
voltage that a thyristor can block repeatedly in the OFF state. This rating is specified at a
maximum allowable junction temperature with gate circuit open or with a specified biasing
resistance between gate and cathode. This type of repetitive transient voltage may appear across
a thyristor due to commutation of other thyristors or diodes in a converter circuit.
Peak non-repetitive off state forward voltage (VDSM): It refers to the allowable peak value of
the forward transient voltage that does not repeat. This type of over voltage may be caused due to
switching operation (i.e, circuit breaker opening or closing or lightning surge) in a supply
network. Its value is about 130% of VDRM. However, VDSM is less than the forward break over
voltage VBRF.
Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.e, anode negative
with respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the
peak negative value of the ac supply voltage.
Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may
occur repeatedly during reverse bias condition of the thyristor at the maximum junction
temperature.
Peak non-repetitive reverse voltage (VRSM): It represents the peak value of the reverse
transient voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is less
than reverse break down voltage VBRR.
Fig 4.7 shows different thyristor voltage ratings on a comparative scale.

IA
VBRR VRSM VRRM VRWM
VDWM VDRM VDSM
VBRF
VAK
Fig. 4.7: Voltage ratings of a thyristor.
4.5.2 Current ratings

Maximum RMS current (Irms): Heating of the resistive elements of a thyristor such as metallic
joints, leads and interfaces depends on the forward RMS current Irms. RMS current rating is used
as an upper limit for dc as well as pulsed current waveforms. This limit should not be exceeded
on a continuous basis.
Maximum average current (Iav): It is the maximum allowable average value of the forward
current such that
i.
Peak junction temperature is not exceeded
ii.
RMS current limit is not exceeded
Manufacturers usually provide the forward average current derating characteristics which
shows Iav as a function of the case temperature (Tc ) with the current conduction angle as a
parameter. The current wave form is assumed to be formed from a half cycle sine wave of power
frequency as shown in Fig 4.8.
Iav
Amps
= 180
120
= 120
100
80
= 60
60
= 30
40
20
0
60
80
100
120
140
TC (C)
Fig. 4.8: Average forward current derating characteristics
Maximum Surge current (ISM): It specifies the maximum allowable non repetitive current the
device can withstand. The device is assumed to be operating under rated blocking voltage,
forward current and junction temperation before the surge current occurs. Following the surge
the device should be disconnected from the circuit and allowed to cool down. Surge currents are
assumed to be sine waves of power frequency with a minimum duration of cycles.
Manufacturers provide at least three different surge current ratings for different durations.
For example
I sM = 3000 A for 1 cycle

2
I sM = 2100 A for 3 cycles
I sM = 1800 A for 5 cycles
Alternatively a plot of IsM vs. applicable cycle numbers may also be provided.
Maximum Squared Current integral (i2dt): This rating in terms of A2S is a measure of the
energy the device can absorb for a short time (less than one half cycle of power frequency). This
rating is used in the choice of the protective fuse connected in series with the device.
Latching Current (IL): After Turn ON the gate pulse must be maintained until the anode
current reaches this level. Otherwise, upon removal of gate pulse, the device will turn off.
Holding Current (IH): The anode current must be reduced below this value to turn off the
thyristor.
Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneous
forward current at a given junction temperature.
Average power dissipation Pav): Specified as a function of the average forward current (Iav) for
different conduction angles as shown in the figure 4.9. The current wave form is assumed to be
half cycle sine wave (or square wave) for power frequency.
Pav
60
30
90
= 180
iF
t
Iav
Fig. 4.9: Average power dissipation vs average forward current in a thyristor.
In the above diagram

1
i d
2 o F
1
Pav =
v i d
2 o F F
I av =
( 4.10 )
( 4.11)
4.5.3 Gate Specifications

Gate current to trigger (IGT): Minimum value of the gate current below which reliable turn on
of the thyristor can not be guaranteed. Usually specified at a given forward break over voltage.
Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage below
which reliable turn on of the thyristor can not be guaranteed. It is specified at the same break
over voltage as IGT.
Non triggering gate voltage (VGNT): Maximum value of the gate-cathode voltage below which
the thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit
must be below this level.
Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gate
and the cathode terminals without damaging the junction.
Average Gate Power dissipation (PGAR): Average power dissipated in the gate-cathode
junction should not exceed this value for gate current pulses wider than 100 s.
Peak forward gate current (IGRM): The forward gate current should not exceed this limit even
on instantaneous basis.
Exercise 4.3
1)

i. Peak non-repetitive over voltage may appear across a thyristor due to ________________
or ________________ surges in a supply network.
ii. VRSM rating of a thyristor is greater than the ________________ rating but less than the
________________ rating.
iii. Maximum average current a thristor can carry depends on the ________________ of the
thyristor and the ________________ of the current wave form.
iv. The ISM rating of a thyristor applies to current waveforms of duration ________________
than half cycle of the power frequency where as the i2dt rating applies to current durations
________________ than half cycle of the power frequency.
v. The gate non-trigger voltage specification of a thyristor is useful for avoiding unwanted
turn on of the thyristor due to ________________ voltage signals at the gate.
Answer: (i) switching, lightning; (ii) VRRM, VBRR; (iii) case temperature, conduction
angle; (iv) greater, less; (v) noise
2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180.
Find the corresponding rating for = 60. Assume the current waveforms to be half cycle sine
wave.
Answer: The form factor of half cycle sine waves for a conduction angle is given by
I
F.F = RMS =
Iav
1
2
1
2
Sin d
Sin d
o
- 1 Sin 2
2
1- Cos
For = 180, F.F =
2
RMS current rating of the thyristor = 1200
= 1885 Amps.
- 3 = 2.778
4
3
Since RMS current rating should not exceeded
For = 60, F.F = 2
1200
Maximum Iav for = 60 =

4
3
4
= 679.00 Amps.
4.6 Switching Characteristics of a Thyristor

During Turn on and Turn off process a thyristor is subjected to different voltages across it and
different currents through it. The time variations of the voltage across a thyristor and the current
through it during Turn on and Turn off constitute the switching characteristics of a thyristor.
4.6.1 Turn on Switching Characteristics

A forward biased thyristor is turned on by applying a positive gate voltage between the gate and
cathode as shown in Fig 4.10.
+
vAK
ig
iA
t
0.9 ION
iA
ig
Vi
ION
0.1 ION
vAK
vAK
0.9 VON
VON
td
iA
Expanded scale
0.1 VON
tON
tr
Firing angle
Vi
t
tp
Fig. 4.10: Turn on characteristics of a thyristor.
Fig 4.10 shows the waveforms of the gate current (ig), anode current (iA) and anode cathode
voltage (VAK) in an expanded time scale during Turn on. The reference circuit and the associated
waveforms are shown in the inset. The total switching period being much smaller compared to
the cycle time, iA and VAK before and after switching will appear flat.
As shown in Fig 4.10 there is a transition time tON from forward off state to forward on state.
This transition time is called the thyristor turn of time and can be divided into three separate
intervals namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times are
shown in Fig 4.10 for a resistive load.
Delay time (td): After switching on the gate current the thyristor will start to conduct over the
portion of the cathode which is closest to the gate. This conducting area starts spreading at a
finite speed until the entire cathode region becomes conductive. Time taken by this process
constitute the turn on delay time of a thyristor. It is measured from the instant of application of
the gate current to the instant when the anode current rises to 10% of its final value (or VAK falls
to 90% of its initial value). Typical value of td is a few micro seconds.
Rise time (tr): For a resistive load, rise time is the time taken by the anode current to rise from
10% of its final value to 90% of its final value. At the same time the voltage VAK falls from 90%
of its initial value to 10% of its initial value. However, current rise and voltage fall
characteristics are strongly influenced by the type of the load. For inductive load the voltage falls
faster than the current. While for a capacitive load VAK falls rapidly in the beginning. However,
as the current increases, rate of change of anode voltage substantially decreases.
If the anode current rises too fast it tends to remain confined in a small area. This can give rise to
local hot spots and damage the device. Therefore, it is necessary to limit the rate of rise of the
di
ON state current A by using an inductor in series with the device. Usual values of maximum
dt
allowable di A is in the range of 20-200 A/s.
dt
Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to
100%. During this time conduction spreads over the entire cross section of the cathode of the
thyristor. The spreading interval depends on the area of the cathode and on the gate structure of
the thyristor.
4.6.2 Turn off Switching Characteristics

Once the thyristor is on, and its anode current is above the latching current level the gate loses
control. It can be turned off only by reducing the anode current below holding current. The turn
off time tq of a thyristor is defined as the time between the instant anode current becomes zero
and the instant the thyristor regains forward blocking capability. If forward voltage is applied
across the device during this period the thyristor turns on again.
During turn off time, excess minority carriers from all the four layers of the thyristor must be
removed. Accordingly tq is divided in to two intervals, the reverse recovery time (trr) and the gate
recovery time (tqr). Fig 4.11 shows the variation of anode current and anode cathode voltage with
time during turn off operation on an expanded scale.
vAK
iA
iA
di A
dt
ig
Vi
t
Qrr
Irr
vi
vAK
iA
t
Expanded
scale
Vrr
trr
tq
t
vi
tgr
Fig. 4.11: Turn off characteristics of a thyristor.
The anode current becomes zero at time t1 and starts growing in the negative direction with the
same di A till time t2. This negative current removes excess carriers from junctions J1 & J3. At
dt
time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse
current and the anode current starts decreasing. The value of the anode current at time t2 is called
the reverse recovery current (Irr). The reverse anode current reduces to the level of reverse
saturation current by t3. Total charge removed from the junctions between t1 & t3 is called the
reverse recovery charge (Qrr). Fast decaying reverse current during the interval t2 t3 coupled with
the di
limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the
dt
device. This voltage must be limited below the VRRM rating of the device. Up to time t2 the
voltage across the device (VAK) does not change substantially from its on state value. However,
after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK starts
following supply voltage vi. At the end of the reverse recovery period (trr) trapped charges still
exist at the junction J2 which prevents the device from blocking forward voltage just after trr.
These trapped charges are removed only by the process of recombination. The time taken for this
recombination process to complete (between t3 & t4) is called the gate recovery time (tgr). The
time interval tq = trr + tgr is called device turn off time of the thyristor.
No forward voltage should appear across the device before the time tq to avoid its inadvertent
turn on. A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltage
is applied across the device. tc is called the circuit turn off time.
The reverse recovery charge Qrr is a function of the peak forward current before turn off and its
di
for
rate of decrease A . Manufacturers usually provide plots of Qrr as a function of di A
dt
dt
different values of peak forward current. They also provide the value of the reverse recovery
current Irr for a given IA and di A . Alternatively Irr can be evaluated from the given Qrr
dt
characteristics following similar relationships as in the case of a diode.
As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on
the construction of the thyristor. In normal recovery converter grade thyristor they are almost
equal for a specified forward current and reverse recovery current. However, in a fast recovery
inverter grade thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helps
reduce the total turn off time tq of the thyristor (and hence allow them to operate at higher
switching frequency). However, large voltage spike due to this snappy recovery will appear
across the device after the device turns off. Typical turn off times of converter and inverter
grade thyristors are in the range of 50-100 s and 5-50 s respectively.
As has been mentioned in the introduction thyristor is the device of choice at the very highest
power levels. At these power levels (several hundreds of megawatts) reliability of the thyristor
power converter is of prime importance. Therefore, suitable protection arrangement must be
made against possible overvoltage, overcurrent and unintended turn on for each thyristor. At the
highest power level (HVDC transmission system) thyristor converters operate from network
voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps
of current. They usually employ a large number of thyristors connected in series parallel
combination. For maximum utilization of the device capacity it is important that each device in
this series parallel combination share the blocking voltage and on state current equally. Special
equalizing circuits are used for this purpose.
Exercise 4.4
1)

i.
A thyristor is turned on by applying a ________________ gate current pulse when it is

________________ biased.
ii.
Total turn on time of a thyristor can be divided into ________________ time

________________ time and ________________ time.
iii.
During rise time the rate of rise of anode current should be limited to avoid creating local
________________.
iv.
A thyristor can be turned off by bringing its anode current below ________________
current and applying a reverse voltage across the device for duration larger than the
________________ time of the device.
v.
Reverse recovery charge of a thyristor depends on the ________________ of the forward

current just before turn off and its ________________.
vi.
Inverter grade thyristors have ________________ turn off time compared to a converter
grade thyristor.
Answer: (i) positive, forward; (ii) delay, rise, spread; (iii) hot spots (iv) holding, turn off; (v)
magnitude, rate of decrease (vi) faster
2. With reference to Fig 4.10 find expressions for (i) turn on power loss and (ii) conduction
power loss of the thyristor as a function of the firing angle . Neglect turn on delay time and
spread time and assume linear variation of voltage and current during turn on period. Also
assume constant on state voltage VH across the thyristor.
Answer: (i) For a firing angle the forward bias voltage across the thyristor just before turn on
is
VON = 2Vi Sin ; Vi = RMS value of supply voltage.
Current after the thyristor turns on for a resistive load is
I ON =
VON
Vi
Sin
Neglecting delay and spread time and assuming linear variation of voltage and current during
turn on
. where V has been neglected.
Vak = 2 Vi Sin 1 - t
H
t
ON
2 Vi Sin
R
Total switching energy loss
ia =
t ON
t ON
2Vi 2
1 - t
t
Sin 2
dt
t ON t ON
o
o
R
2Vi 2
t
2
Vi 2
=
Sin 2 ON 1 - =
Sin 2 t ON
R
2
3
3R
E ON =
t ON
v ak i a dt =
EON occurs once every cycle. If the supply frequency is f then average turn on power loss is
given by.
PON = E ON f =
Vi 2
Sin 2 t ON f
3R
(ii) If the firing angle is the thyristor conducts for - angle. Instantaneous current through the
device during this period is
2 Vi Sin t
ia = R
<t
R
Where tON & VH have been neglected for simplicity.
total conduction energy loss over one cycle is
E C = Vak i a dt =
1
V
H
2 Vi
Sin d =
R
Average conduction power loss = PC = E cf =
2 Vi VH
(1 + Cos )
R
2 Vi VH
(1 + Cos )
2R
Fuse
i1
Vi
if
220 V
50 HZ
3. In the ideal single phase fully controlled converter T1 & T2 are fired at a firing angle after
the positive going zero crossing of Vi while T3 & T4 are fired angle after the negative going
zero crossing of Vi, If all thyristors have a turn off time of 100 s, find out maximum allowable
value of .
Answer: As T1 & T2 are fired at an angle after positive going zero crossing of Vi, T3 & T4 are
subjected to a negative voltage of Vi. Since this voltage remain negative for a duration (-)
angle
(after
which
Vi
becomes
positive)
for
safe
commutation
0
( - Max) t off Max = 178.2 .
4.7 The Triac

The Triac is a member of the thyristor family. But unlike a thyristor which conducts only in one
direction (from anode to cathode) a triac can conduct in both directions. Thus a triac is similar to
two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case
of a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gate
terminal. The gate looses control over conduction once the triac is turned on. The triac turns off
only when the current through the main terminals become zero. Therefore, a triac can be
categorized as a minority carrier, a bidirectional semi-controlled device. They are extensively
used in residential lamp dimmers, heater control and for speed control of small single phase
series and induction motors.
4.7.1 Construction and operating principle

Fig. 4.12 (a) and (b) show the circuit symbol and schematic cross section of a triac respective. As
the Triac can conduct in both the directions the terms anode and cathode are not used for
Triacs. The three terminals are marked as MT1 (Main Terminal 1), MT2 (Main Terminal 2) and
the gate by G. As shown in Fig 4.12 (b) the gate terminal is near MT1 and is connected to both
N3 and P2 regions by metallic contact. Similarly MT1 is connected to N2 and P2 regions while
MT2 is connected to N4 and P1 regions.
MT1
N2
N2
MT2
P2
P2
N3
N3
G
P1
N1
MT1
(a)
N1
P2
N4
P1
MT2
(b)
Fig. 4.12: Circuit symbol and schematic construction of a Triac

(a) Circuit symbol (b) Schematic construction.
Since a Triac is a bidirectional device and can have its terminals at various combinations of
positive and negative voltages, there are four possible electrode potential combinations as given
below
1. MT2 positive with respect to MT1, G positive with respect to MT1
2. MT2 positive with respect to MT1, G negative with respect to MT1
3. MT2 negative with respect to MT1, G negative with respect to MT1
4. MT2 negative with respect to MT1, G positive with respect to MT1
The triggering sensitivity is highest with the combinations 1 and 3 and are generally used.
However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2
and 3 are used. Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction
mechanism of a triac in trigger modes 1 & 3 respectively.
IG
IG
IG
MT1
(-)
N2
MT1
(+)
N3
IG
P2
P2
N1
N1
P1
P1
N4
MT2
(+)
(a)
MT2
(-)
(b)
Fig. 4.13: Conduction mechanism of a triac in trigger modes 1

and 3
(a) Mode 1 , (b) Mode 3 .
In trigger mode-1 the gate current flows mainly through the P2 N2 junction like an ordinary
thyristor. When the gate current has injected sufficient charge into P2 layer the triac starts
conducting through the P1 N1 P2 N2 layers like an ordinary thyristor.
In the trigger mode-3 the gate current Ig forward biases the P2 P3 junction and a large number of
electrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns on
completely.
4.7.2 Steady State Output Characteristics and Ratings of a Triac

I
Ig3 > Ig2 > Ig1 > Ig = 0

-VBO
Ig = 0
VBO
-Ig3 < Ig2 < Ig1
Fig. 4.14: Steady state V I characteristics of a Triac
From a functional point of view a triac is similar to two thyristors connected in anti parallel.
Therefore, it is expected that the V-I characteristics of Triac in the 1st and 3rd quadrant of the V-I
plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no
signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak
value is lower than the break over voltage (VBO) of the device. However, the turning on of the
triac can be controlled by applying the gate trigger pulse at the desired instance. Mode-1
triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant.
As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current).
However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact
with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings
of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings
of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared
to a thyristor. Manufacturers usually specify characteristics curves relating rms device current
and maximum allowable case temperature as shown in Fig 4.15. Curves relating the device
dissipation and RMS on state current are also provided for different conduction angles.
Bidirectional ON state current

(RMS)
200
150
100
For all conduction angles
50
0
20
40
60
80
100
120
Maximum allowable case temperature (TC)

Fig. 4.15: RMS ON state current Vs maximum case temperature.
4.7.3 Triac Switching and gate trigger circuit

Unlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. As a result
the triacs are operated only at power frequency. Switching characteristics of a triac is similar to
that of a thyristor. However, turn off of a triac is extremely sensitive to temperature variation and
may not turn off at all if the junction temperature exceeds certain limit. Problem may arise when
a triac is used to control a lagging power factor load. At the current zero instant (when the triac
turns off) a reverse voltage will appear across the triac since the supply voltage is negative at that
instant. The rate of rise of this voltage is restricted by the triac junction capacitance only. The
resulting dv
may turn on the triac again. Similar problem occurs when a triac is used to
dt
control the power to a resistive element which has a very low resistance before normal working
condition is reached. If such a load (e.g. incandescent filament lamp) is switch on at full supply
voltage very large junction capacitance charging current will turn ON the device. To prevent
such condition an R-C snubber is generally used across a triac.
The triac should be triggered carefully to ensure safe operation. For phase control application,
the triac is switched on and off in synchronism with the mains supply so that only a part of each
half cycle is applied across the load. To ensure clean turn ON the trigger signal must rise
rapidly to provide the necessary charge. A rise time of about 1 s will be desirable. Such a triac
gate triggering circuit using a diac and an R-C timing network is shown in Fig 4.16.
LOAD
R1
R2
D1
V1
C
C1
Fig. 4.16: Triac triggering circuit using a diac.
In this circuit as Vi increases voltage across C1 increases due to current flowing through load, R1,
R2 and C1. The voltage drop across diac D1 increases until it reaches its break over point. As D1
conducts a large current pulse is injected into the gate of the triac. By varying R2 the firing can
be controlled from zero to virtually 100%.
Exercise 4.5
1)

i.
A Triac is a ________________ minority carrier device
ii.
A Triac behaves like two ________________ connected thyristors.
iii.
The gate sensitivity of a triac is maximum when the gate is ________________ with
respect to MT1 while MT2 is positive with respect to MT1 or the gate is
________________ with respect to MT1 while MT2 is negative with respect to MT1
iv.
A Triac operates either in the ________________ or the ________________ quadrant of

the i-v characteristics.
v.
In the ________________ quadrant the triac is fired with ________________ gate

current while in the ________________ quadrant the gate current should be
________________.
vi.
The maximum possible voltage and current rating of a Triac is considerably

________________ compared to thyristor due to ________________ of the two current
carrying paths inside the structure of the triac.
vii.
To avoid unwanted turn on of a triac due to large dv
dt
________________ are used
across triacs.
viii.
For clean turn ON of a triac the ________________ of the gate current pulse should be
as ________________ as possible.
Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first,
positive, third, negative (vi) lower, interaction; (vii) R-C shubbers; (viii) rise time,
small.
References
1. Dr. P.C. Sen, Power Electronics; Tata McGrow Hill Publishing Company Limited;
New Delhi.
2. Dr. P.S. Bimbhra, Power Electronics Khanna Publishers
Lesson Summary
Thyristor is a four layer, three terminal, minority carrier, semi-controlled device.
The three terminals of a thyristor are called the anode, the cathode and the gate.
A thyristor can be turned on by increasing the voltage of the anode with respect to the
cathode beyond a specified voltage called the forward break over voltage.
A thyristor can also be turned on by injecting a current pulse into the gate terminal when
the anode voltage is positive with respect to the cathode. This is called gate triggering.
A thyristor can block voltage of both polarity but conducts current only from anode to
cathode.
After a thyristor turns on the gate looses control. It can be turned off only by bringing the
anode current below holding current.
After turn on the voltage across the thyristor drops to a very low value (around 1 volt). In
the reverse direction a thyristor blocks voltage up to reverse break down voltage.
A thyristor has a very low conduction voltage drop but large switching times. For this
reason thyristors are preferred for high power, low frequency line commutated
application.
A thyristor is turned off by bringing the anode current below holding current and
simultaneously applying a negative voltage (cathode positive with respect to anode) for a
minimum time called turn off time.
A triac is functionally equivalent to two anti parallel connected thyristors. It can block
voltages in both directions and conduct current in both directions.
A triac has three terminals like a thyristor. It can be turned on in either half cycle by
either a positive on a negative current pulse at the gate terminal.
Triacs are extensively used at power frequency ac load (eg heater, light, motors) control
applications.
Practice Problems and Answers
1. Explain the effect of increasing the magnitude of the gate current and junction
temperature on (i) forward and reverse break down voltages, (ii) forward and reverse
leakage currents.
Th
15 V
N1 N2
iB
2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse
transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum
average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage
limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N1/N2 and the
value of R.
Fuse
i1
Vi
if
220 V
50 HZ
3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The
thyristors are fired at a firing angle = 0 when motor runs at rated speed. The motor has
on armature resistance of 0.2 and negligible armature inductance. Find out the peak
surge current rating of the thyristors such that they are not damaged due to sudden loss of
field excitation to the motor. The protective fuse in series with the motor is designed to
disconnect the motor within 1 cycle of fault. Find out the i 2 dt rating of the
2
thyristors.
4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode
regions? A thyristor used to control the voltage applied to a load resistance from a 220v,
50HZ single phase ac supply has a maximum

value of the
di a
dt
di a
dt
rating of 50 A / s. Find out the
limiting inductor to be connected in series with the load resistance.

THM
200V
THA
20 A
200V
5. In a voltage commutated dc dc thyristor chopper the main thyristor THM is

commutated by connecting a pre-charged capacitor directly across it through the auxiliary
thyristor THA as shown in the figure. The main thyristor THM has a turn off time off
50s and maximum dv
rating of 500v/ s. Find out a suitable value of C for safe
dt
commutation of THM.
Answers to Practice Problems
1.
i.
ii.
Forward break down voltage reduces with increasing gate current. It increases with
junction temperature up to certain value of the junction temperature and then falls rapidly
with any further increase in temperature.
Reverse break down voltage is independent of the gate current magnitude but decreases
with increasing junction temperature.
Forward leakage current is independent of the gate current magnitude but increases with
junction temperature.
Reverse leakage current increases with both the junction temperature and the magnitude
of the gate current.
THM
200V
THA
20 A
200V
2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write
E = R i g + Vg OR Vg = E - R i g
The diode D clamps the gate voltage to zero when E goes negative.
Now for ig = O,
But E =
N2
Since Vg
Vg = E.
N1
15
N2
N1
Max
= 15
= 10 v
10
E = 10 v
= 1.5
Gate pulse width = 0.4 10-4 Sec = 40s. <100s.

instantaneous gate power dissipation limit can be used.
Pav
0.2
Max
=
= 0.5 watts
0.4
For maximum utilization of the gate power dissipation limit the gate load line ie Vg = E igR =
10 igR should be tangent to the maximum power dissipation curve Vg ig = 0.5
Vg i g
Max
Let the operating Vg and ig be Vgo & igo
Vgo = 10 - i go R
Vgo i go = 0.5
i go 2 R - 10 i go + 0.5 = 0
Since Vg = 10 ig R is tangent to Vg ig = 0.5 at Vgo, igo.

Slope of the tangent of Vgig = 0.5 at (Vgo, igo) = -R
-R =
R =
i go 2
dv g
- vg
v
=
= - go
di g ( vgo,igo )
i g ( vgo,igo )
i go
v go
v i
0.5
= go 2go = 2
i go
i go
i go
0.5
- 10i go + 0.5 = 0
i go 2
R = 0.5
i go
or
10i go = 1
or i go = 0.1
0.5
= 50
.01
Back emf.
Va
t
ia
(normal)
t
ia
(with field loss)
t
3. Figure shows the armature voltage (firm line) and armature current of the motor under normal
operating condition at rated speed. If there is a sudden loss of field excitation back emf will
become zero and armature current will be limited solely by the armature resistance.
220 2
The peak magnitude of the fault current will be
= 1556(Amps) .
.2
It the thyristors have to survive this fault at least for 1 cycle (after which the fuse blows) IsM >
2
1556 Amps.
The fuse blows within 1
cycle of the fault occurring. Therefore the thyristors must withstand

2
the fault for at least 1 cycle.
2
2
Therefore, the i t rating of the thyristor should be
10-2
(1556 Sin 100 t )
2
i dt =
(1556 )
10-2
[1 -
Cos 200 t ] dt
2
= 1 10 -2 (1556 ) = 1.21 10 4 A 2 Sec
2
4. At the beginning of the turn on process the thyristor starts conducting through the area
adjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anode
current is lager than the rate of increase of the current conduction are, the current density
increases with time. This may lead to thyristor failure due to excessive local heating. However, if
the contact area between the gate and the cathode is large a thyristor will be able to handle a
di
relatively large a without being damaged.
dt
di a
The maximum
L
Since
di a
dt
Max
dt
will occur when the thyristor is triggered at = 90. Then
di a
=
dt
2 220 Sin 90 0
= 50 10 6 A Sec
min
2 220
= 6.22 10 -6 H = 6.22 H
di a
dt
Max
VC
toff
vTHM
200 V
dv / dt
iC
20 Amps.
t
5. As soon as THA is turned on the load current transfer from THM to C. the voltage across
THM is the negative of the capacitance voltage. Figure shows the waveforms of voltage across
the capacitor (vc), voltage across the main thyristor (VTHM) and the capacitor current ic. From
dv
i
= c
figure
c
dt
dv
= 500 v s
Now ic = 20 Amps &
dt Max
Min
ic
dv
dt
=
Max
20
-8
F = 0.04 F
6 = 4 10
50010
The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial
value of 200v. This time must be greater than the turn off time of the device.
dv c
= i c = 20
dt
20 t
v c =
c
Now C
v = 200 - 0 = 200
t = t off
20 50 10 -6
C
20 50 10 -6
C =
= 5 F
200
200 =
For safe commutation of THM the higher value of C must the chosen
the required value of C = 5 F.
Module
5
DC to AC Converters
Lesson
33
Introduction to Voltage
Source Inverters
After completion of this lesson the reader will be able to:

(i)
(ii)
(iii)
(iv)
Identify the essential components of a voltage source inverter.

Explain the principle behind dc to ac conversion.
Identify the basic topology of single-phase and three-phase inverters and explain
its principle of operation.
Explain the gate drive circuit requirements of inverter switches.
The word inverter in the context of power-electronics denotes a class of power conversion (or
power conditioning) circuits that operates from a dc voltage source or a dc current source and
converts it into ac voltage or current. The inverter does reverse of what ac-to-dc converter
does (refer to ac to dc converters). Even though input to an inverter circuit is a dc source, it is
not uncommon to have this dc derived from an ac source such as utility ac supply. Thus, for
example, the primary source of input power may be utility ac voltage supply that is converted
to dc by an ac to dc converter and then inverted back to ac using an inverter. Here, the final ac
output may be of a different frequency and magnitude than the input ac of the utility supply.
[The nomenclature inverter is sometimes also used for ac to dc converter circuits if the
power flow direction is from dc to ac side. However in this lesson, irrespective of power
flow direction, inverter is referred as a circuit that operates from a stiff dc source and
generates ac output. If the input dc is a voltage source, the inverter is called a voltage
source inverter (VSI). One can similarly think of a current source inverter (CSI), where the
input to the circuit is a current source. The VSI circuit has direct control over output (ac)
voltage whereas the CSI directly controls output (ac) current. Shape of voltage
waveforms output by an ideal VSI should be independent of load connected at the output.]
The simplest dc voltage source for a VSI may be a battery bank, which may consist of several
cells in series-parallel combination. Solar photovoltaic cells can be another dc voltage source.
An ac voltage supply, after rectification into dc will also qualify as a dc voltage source. A
voltage source is called stiff, if the source voltage magnitude does not depend on load connected
to it. All voltage source inverters assume stiff voltage supply at the input.
Some examples where voltage source inverters are used are: uninterruptible power supply (UPS)
units, adjustable speed drives (ASD) for ac motors, electronic frequency changer circuits etc.
Most of us are also familiar with commercially available inverter units used in homes and offices
to power some essential ac loads in case the utility ac supply gets interrupted. In such inverter
units, battery supply is used as the input dc voltage source and the inverter circuit converts the dc
into ac voltage of desired frequency. The achievable magnitude of ac voltage is limited by the
magnitude of input (dc bus) voltage. In ordinary household inverters the battery voltage may be
just 12 volts and the inverter circuit may be capable of supplying ac voltage of around 10 volts
(rms) only. In such cases the inverter output voltage is stepped up using a transformer to meet the
load requirement of, say, 230 volts.
33.1 How to Get AC Output From DC Input Supply?

Figs. 33.1(a) and 33.1(b) show two schematic circuits, using transistor-switches, for generation
of ac voltage from dc input supply. In both the circuits, the transistors work in common emitter
configuration and are interconnected in push-pull manner. In order to have a single control signal
for the transistor switches, one transistor is of n-p-n type and the other of p-n-p type and their
emitters and bases are shorted as shown in the figures. Both circuits require a symmetrical
bipolar dc supply. Collector of n-p-n transistor is connected to positive dc supply (+E) and that
of p-n-p transistor is connected to negative dc supply of same magnitude (-E). Load, which has
been assumed resistive, is connected between the emitter shorting point and the power supply
ground.
In Fig. 33.1(a), the transistors work in active (amplifier) mode and a sinusoidal control voltage of
desired frequency is applied between the base and emitter points. When applied base signal is
positive, the p-n-p transistor is reverse biased and the n-p-n transistor conducts the load current.
Similarly for negative base voltage the p-n-p transistor conducts while n-p-n transistor remains
reverse biased. A suitable resistor in series with the base signal will limit the base current and
keep it sinusoidal provided the applied (sinusoidal) base signal magnitude is much higher than
the base to emitter conduction-voltage drop. Under the assumption of constant gain (hfe) of the
transistor over its working range, the load current can be seen to follow the applied base signal.
Fig. 33.2(a) shows a typical load voltage (in blue color) and base signal (green color) waveforms.
This particular figure also shows the switch power loss for n-p-n transistor (in brown color). The
other transistor will also be dissipating identical power during its conduction. The quantities in
Fig. 33.2(a) are in per unit magnitudes where the base values are input supply voltage (E) and the
load resistance (R). Accordingly the base magnitudes of current and power are E/R and E2/R
respectively. As can be seen, the power loss in switches is a considerable portion of circuits
input power and hence such circuits are unacceptable for large output power applications.
As against the amplifier circuit of Fig. 33.1(a), the circuit of Fig. 33.1(b) works in switched
mode. The conducting switch remains fully on having negligible on-state voltage drop and the
non-conducting switch remains fully off allowing no leakage current through it. The load voltage
waveform output by switched-mode circuit of Fig. 33.1(b) is rectangular with magnitude +E
when the n-p-n transistor is on and E when p-n-p transistor is on. Fig. 33.2(b) shows one such
waveform (in pink color). The on and off durations of the two transistors are controlled so that (i)
the resulting rectangular waveform has no dc component (ii) has a fundamental (sinusoidal)
component of desired frequency and magnitude and (iii) the frequencies of unwanted harmonic
voltages are much higher than that of the fundamental component. The fundamental sine wave in
Fig. 33.2(b), shown in blue color, is identical to the sinusoidal output voltage of Fig. 33.2(a).
Both amplifier mode and switched mode circuits of Figs. 33.1(a) and 33.1(b) are capable of
producing ac voltages of controllable magnitude and frequency, however, the amplifier circuit is
not acceptable in power-electronic applications due to high switch power loss. On the other
hand, the switched mode circuit generates significant amount of unwanted harmonic voltages
along with the desired fundamental frequency voltage. As will be shown in some later lessons,
the frequency spectrum of these unwanted harmonics can be shifted towards high frequency by
adopting proper switching pattern. These high frequency voltage harmonics can easily be
blocked using small size filter and the resulting quality of load voltage can be made acceptable.
+E
+E
LOAD (R)
LOAD (R)
-E
Fig. 33.1 (a): A push-pull
active amplifier circuit
-E
Fig. 33.1 (b): A push-pull
switched mode circuit
The magnitude, phase and frequency of the fundamental voltage waveform in Fig. 33.2(b) is
solely determined by the magnitude of supply voltage and the switching pattern of the push-pull
circuit shown in Fig. 33.1(b). Thus, as long as the transistors work in the switch-mode (fully on
or fully off), the output voltage is essentially load-independent.
33.2 What If The Load Is Not Resistive?

Circuit of Fig. 33.1(b) will not be able to output proper voltage waveform for a non-resistive load
for the reasons mentioned below.
Transistors used in the circuit of Fig. 33.1(b) are meant to carry only unidirectional current (from
collector to emitter) and thus if the upper (n-p-n) transistor is on, the current must enter the star
(*) marked terminal of the load and this same terminal will get connected to the positive dc
supply (+E), other load terminal being at ground potential. When n-p-n transistor turns off and pn-p type turns on, the load voltage and current polarities reverse simultaneously (p-n-p transistor
can only carry current coming out of star marked end of load). Such one to one matching
between the instantaneous polarities of load voltage and load current can be achieved only in
purely resistive loads. For a general load the instantaneous current polarity may be different from
instantaneous load-voltage polarity. As pointed out in section 33.1, the inverter switching-pattern
fixes the output waveform irrespective of the load. Thus the magnitude, phase and frequency of
the fundamental voltage output by a VSI is independent of the nature of load. Thus it turns out
that for a non-resistive load the switches in the circuit of Fig. 33.1(b) should be able to carry bidirectional current and at the same time be controllable. [A mechanical switch realized using
an electromagnetic contactor is one example of the bi-directional current carrying
controllable switch. However electromagnetic contactors are not capable of operating at
high frequency, in the range of kilohertz, and may not be suitable for present application.]
If an anti-parallel diode is connected across each transistor switch, as shown in Fig. 33.3(a), the
combination can conduct a bi-directional current. Now the transistor in anti-parallel with the
diode may be considered as a single switch. [A major difference exists between this bidirectional electronic switch and a bi-directional current carrying mechanical switch. The
mechanical switch can be subjected to bi-directional voltage. When off, the mechanical
switch can block both positive and negative voltage across its terminals. The electronic
switch of Fig. 33.3(a) can block only one polarity of voltage, the one that keeps the diode
reverse biased. Under this polarity of voltage the switch can remain off as long as the base
(or the gate) terminal is not given the turn-on signal. When applied voltage polarity is
reversed the diode starts conducting and so the switch is not able to block the flow of
reverse current.] In spite of unidirectional voltage blocking capability, the new electronic
switch (similar to the one shown in Fig. 33.3(a)) suffices for the inverter application as pointed
out in the following paragraphs.
The push-pull circuit operation is now revisited using bi-directional current carrying switches.
The modified circuit is shown in Fig. 33.3(b). It may be noted that both IGBT and BJT type
transistors, when bypassed by anti-parallel diode, qualify as bi-directional current carrying
switches. However, IGBT switch is controlled by gate voltage whereas the BJT
+E
Input /
Output
SW1
Q1
D1
LOAD
Analogous to
Gate
(control)
Control
S
Q2
Input /
Output
Fig. 33.3(a): Bi-directional controlled

switch
D2
SW2
-E
Fig. 33.3 (b): Modified push-pull circuit
switch is controlled using base current. [IGBT switches are easier to use, are much faster and
are available in higher voltage and current ratings. As a result BJT switches are becoming
obsolete.] In the circuit of Fig. 33.3(b), n-p-n transistor (Q1) together with diode (D1) constitutes
the upper switch (SW1). Similarly lower switch (SW2) consists of p-n-p transistor (Q2) in antiparallel with diode (D2). By applying positive base-to-emitter voltage of suitable magnitude to
transistor Q1, the upper switch is turned on. Once the upper switch (diode D1or transistor
Q1) is conducting star end of load is at +E potential and diode D2 of lower switch gets
reverse biased. Transistor Q2 is also reverse biased due to application of positive base voltage
to the transistors. Thus while switch SW1is conducting current, switch SW2 is off and is
blocking voltage of magnitude 2E. Similarly when applied base voltage to the transistors is
made negative, Q1 is reverse biased and Q2 is forward biased. This results in SW1 turning
off and SW2 turning on. Now SW1 blocks a voltage of magnitude 2E.
It may be interesting to see how diodes follow the switching command given to the transistor
part of the switches. To illustrate this point some details of circuit operation with an inductive
load, consisting of a resistor and an inductor in series, is considered. As is well known, current
through such loads cannot change abruptly. The electrical inertial time constant of the load,
given by its L (inductance) / R (resistance) ratio, may in general be large compared to the chosen
switching time period of the transistor switches. Thus the transistors Q1 and Q2 may turn-on
and turn-off several times before the load current direction changes. Let us consider the time
instant when instantaneous load current is entering the star end of the load in Fig. 33.3(b). Now
with the assumed load current direction when Q1 is given turn-on signal current flows from
positive dc supply, through transistor Q1, to load. Next, when Q1 is turned-off and Q2 is
turned on (but load current direction remaining unchanged) the load current finds its path
through diode of lower switch (D2). Whether D2 or Q2 conducts, voltage drop across SW2 is
virtually zero and it can be considered as a closed or a fully-on switch. In the following
switching cycle when Q1 is turned on again (load current direction still unchanged) the load
current path reverts back from D2 to Q1. It may not be difficult to see how this happens.
While current flowed through D2 the load circuit got connected to negative emf (-E) of the
supply. When Q1 conducts the positive (+E) emf supports the load current. The natural choice
for load current is to move from D2 to Q1. In fact turning on of Q1 will make D2 reverse
biased. The reader may repeat a similar exercise when the instantaneous load current comes out
of the star end of load. Thus it will be evident that diodes do not need a separate command to
turn on and off. Irrespective of the load current direction, turning on of Q1 makes SW1 on and
similarly turning off of Q1 (with simultaneous turn-on of Q2) makes SW2on. Q1 and Q2
are turned on in a complementary manner. It may not be difficult to see that the circuit of Fig.
33.3(b) will work satisfactorily for a purely resistive load and a series connected resistorcapacitor load too.
The push-pull circuit of Fig. 33.3(b) has some technical demerits that have been discussed
below.
First, it needs a bipolar dc supply with identical magnitudes of positive and negative supply
voltages. For practical reasons it would have been simpler if only one (uni-polar) dc source was
required. In fact some circuit topologies realize a bi-polar dc supply by splitting the single dc
voltage-source through capacitive potential divider arrangement. [A resistive potential divider
will be terribly inefficient.] Two identical capacitors of large magnitude are put across the dc
supply and the junction point of the capacitors is used as the neutral (ground) point of the bipolar dc supply. Fig. 33.3(c) shows one such circuit where a single dc supply has been split in
two halves. In such circuits the voltages across the two capacitors may not remain exactly
balanced due to mismatch in the loading patterns or mismatch in leakage currents of the
individual capacitors. Also, unless the capacitors are of very large magnitude, there may be
significant ripple in the capacitor voltages, especially at low switching frequencies. The
requirement of splitting a single dc source is eliminated if a full bridge circuit, as mentioned in
the next section, is used.
The second demerit of the push-pull circuit shown in Fig. 33.3(b) is the requirement of two
different kinds of transistors, one n-p-n type and the other p-n-p type. The switching speeds of np-n and p-n-p transistors are widely different unless they are produced carefully as matched
pairs. In power electronic applications, n-p-n transistors are preferred as they can operate at
higher switching frequencies. Similarly n-channel MOSFETs and IGBTs are preferred over their
p-channel counterparts. The difficulty in using two n-p-n transistors in the above discussed pushpull circuit is that they can no longer have a common base and a common emitter point and thus
it wont be possible to have a single base drive signal for controlling both of them. The base
signals for the individual transistors will then need to be separate and isolated from each other.
The difficulty in providing isolated base signals for the two transistors is, often, more than
compensated by the improved capability of the circuit that uses both n-p-n transistors or nchannel IGBTs. The circuit in Fig. 33.3(c) shows identical transistors (n-channel IGBTs) for both
upper and lower switches. The gate drive signals of the two transistors (IGBTs) now need to be
different and isolated as the two emitter points are at different potentials. The circuit in Fig.
33.3(c) is better known as a half bridge inverter.
P
+
_
Edc
+
_
O
+
_
0.5Edc
LOAD
0.5Edc
D1
Q1
Q2
D2
N
Fig. 33.3(c): Topology of a 1-phase half bridge VSI
33.3 General Structure of Voltage Source Inverters

Figs. 33.4 (a) and 33.4(b) show the typical power-circuit topologies of a single-phase and a
three-phase voltage source inverter respectively. These topologies require only a single dc
source and for medium output power applications the preferred devices are n-channel IGBTs.
Edc is the input dc supply and a large dc link capacitor (Cdc) is put across the supply terminals.
Capacitors and switches are connected to dc bus using short leads to minimize the stray
inductance between the capacitor and the inverter switches. Needless to say that physical layout
of positive and negative bus lines is also important to limit stray inductances. Q1, Q2, Q3 etc. are
fast and controllable switches. D1, D2, D3 etc. are fast recovery diodes connected in anti-parallel
with the switches. A, B and C are output terminals of the inverter that get connected to the
ac load. A three-phase inverter has three load-phase terminals whereas a single-phase inverter
has only one pair of load terminals.
The current supplied by the dc bus to the inverter switches is referred as dc link current and has
been shown as idc in Figs 33.4(a) and 33.4(b). The magnitude of dc link current often changes
in step (and some times its direction also changes) as the inverter switches are turned on and off.
The step change in instantaneous dc link current occurs even if the ac load at the inverter output
is drawing steady power. However, average magnitude of the dc link current remains positive if
net power-flow is from dc bus to ac load. The net power-flow direction reverses if the ac load
connected to the inverter is regenerating. Under regeneration, the mean magnitude of dc link
current is negative. [The dc link current may conceptually be decomposed into its dc and ac
components. The individual roles of the dc voltage source and the dc link capacitor may
be clearly seen with respect to the dc and ac components of the dc link current. For the dc
component of current the capacitor acts like open circuit. As expected, under steady state,
the capacitor does not supply any dc current. The dc part of bus current is supplied solely
by the dc source. A practical dc voltage source may have some resistance as well as some
inductance in series with its internal emf. For dc component of bus current, the source
voltage appears in series with its internal resistance (effect of source inductance is not felt).
But for ac component of current, the internal dc emf of source appears as short and its
series impedance (resistance in series with inductance) appears in parallel with the dc-link
capacitor. Thus the ac component of current gets divided into these two parallel paths.
However, the high frequency component of ac current mainly flows through the capacitor,
as the capacitive impedance is lower at high frequencies. The step change in dc link current
is associated with significant amount of high frequency components of current that
essentially finds its path through the capacitor.]
For an ideal input (dc) supply, with no series impedance, the dc link capacitor does not have any
role. However a practical voltage supply may have considerable amount of output impedance.
The supply line impedance, if not bypassed by a sufficiently large dc link capacitor, may cause
considerable voltage spike at the dc bus during inverter operation. This may result in
deterioration of output voltage quality, it may also cause malfunction of the inverter switches as
the bus voltage appears across the non-conducting switches of the inverter. Also, in the absence
of dc link capacitor, the series inductance of the supply line will prevent quick build up or fall of
current through it and the circuit behaves differently from the ideal VSI where the dc voltage
supply is supposed to allow rise and fall in current as per the demand of the inverter circuit.
[It may not be possible to reduce supply line inductance below certain limit. Most dc
supplies will inherently have rather significant series inductance, for example a
conventional dc generator will have considerable armature inductance in series with the
armature emf. Similarly, if the dc supply is derived after rectifying ac voltage, the ac
supply line inductance will prevent quick change in rectifier output current. The effect of
ac line inductance is reflected on the dc side as well, unless this inductance is effectively
bypassed by the dc side capacitor. Even the connecting leads from the dc source to the
inverter dc bus may contribute significantly to the supply line inductance in case the lead
lengths are large and circuit lay out is poor. It may be mentioned here that an inductance,
in series with the dc supply, may at times be welcome. The reason being that for some types
of dc sources, like batteries, it is detrimental to carry high frequency ripple current. For
such cases it is advantageous if the dc source has some series inductance. Due to series
inductance of the source, the high frequency ripple will prefer to flow through the dc link
capacitor and thus relieve the dc source.]
The dc link capacitor should be put very close to the switches so that it provides a low
impedance path to the high frequency component of the switch currents. The capacitor itself
must be of good quality with very low equivalent series resistor (ESR) and equivalent series
inductor (ESL). The length of leads that interconnect switches and diodes to the dc bus must also
be minimum to avoid insertion of significant amount of stray inductances in the circuit. The
overall layout of the power circuit has a significant effect over the performance of the inverter
circuit.
idc
idc
Q1
Edc
D1
Q1
Edc
+ Cdc
_
A
Q2
D3
Q3
LOAD
D2
Q4
B
D4
Fig. 33.4(a): Topology of a 1-phase VSI
+ Cdc
_
D1
Q3
Q2
D2
D3
Q5
Q4
D4
D5
Q6
D6
Fig. 33.4(b): Topology of a 3-phase VSI
[One of the thumb rules for good circuit layout is to put the conductor pairs carrying same
magnitude but opposite direction of currents close by, the minimum distance between them
being decided only by their voltage isolation requirement. Thus the positive and negative
terminals of the dc bus should run close by. A twisted wire pair may be an example of two
closely running wires.]
The details of the inverter circuits shown in Figs. 33.4(a) and 33.4(b) are discussed in later
lessons. However it may be mentioned here that these circuits are essentially extension of the
half bridge circuit shown in Fig. 33.3(c). For example, the single-phase bridge circuit of Fig.
33.4(a) may be thought of as two half-bridge circuits sharing the same dc bus. Thus the single
phase full-bridge (often, simply called as bridge) circuit has two legs of switches, each leg
consisting of an upper switch and a lower switch. Junction point of the upper and lower switches
is the output point of that particular leg. Voltage between output point of legs and the midpotential of the dc bus is called as pole voltage referred to the mid potential of the dc bus. One
may think of pole voltage referred to negative bus or referred to positive bus too but unless
otherwise mentioned pole voltages are assumed to be referred to the mid-potential of the dc bus.
The two pole voltages of the single-phase bridge inverter generally have same magnitude and
frequency but their phases are 1800 apart. Thus the load connected between these two pole
outputs (between points A and B) will have a voltage equal to twice the magnitude of the
individual pole voltage. The pole voltages of the 3-phase inverter bridge, shown in Fig. 33.4(b),
are phase apart by 1200 each.
33.4 Need For Isolated Gate-Control Signals For The Switches

As already mentioned the switches in bridge configurations of inverters, as in Figs. 33.3(c),
33.4(a) and 33.4(b), need to be provided with isolated gate (or base) drive signals. The individual
control signal for the switches needs to be provided across the gate (base) and source (or emitter)
terminals of the particular switch. The gate control signals are low voltage signals referred to the
source (emitter) terminal of the switch. For n-channel IGBT and MOSFET switches, when gate
to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is
less than threshold voltage the switch turns off. The threshold voltage is generally of the order of
+5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts
where as turn-off gate voltage is zero or little negative (around 5 volts). It is to be remembered
that the two switches of an inverter-leg are controlled in a complementary manner. When the
upper switch of any leg is on, the corresponding lower switch remains off and vice-versa.
When a switch is on its emitter and collector terminals are virtually shorted. Thus with upper
switch on, the emitter of the upper switch is at positive dc bus potential. Similarly with lower
switch on, the emitter of upper switch of that leg is virtually at the negative dc bus potential.
Emitters of all the lower switches are solidly connected to the negative line of the dc bus. Since
gate control signals are applied with respect to the emitter terminals of the switches, the gate
voltages of all the upper switches must be floating with respect to the dc bus line potentials. This
calls for isolation between the gate control signals of upper switches and between upper and
lower switches. Only the emitters of lower switches of all the legs are at the same potential (since
all of them are solidly connected to the negative dc bus) and hence the gate control signals of
lower switches need not be isolated among themselves. As should be clear from the above
discussion, the isolation provided between upper and lower switches must withstand a peak
voltage stress equal to dc bus voltage. Gate-signal isolation for inverter switches is generally
achieved by means of optical-isolator (opto-isolator) circuits. Fig.33.5 shows a typical optoisolator circuit. The circuit makes use of a commercially available opto-coupler IC, shown within
dotted lines in the figure. Input stage of the IC is a light emitting diode (LED) that emits light
when forward biased. The light output of the LED falls on reverse biased junction of an optical
diode. The LED and the photo-diode are suitably positioned inside the opto-coupler chip to
ensure that the light emitted by the LED falls on the photo-diode junction. The gate control
pulses for the switch are applied to the input LED through a current limiting resistor of
appropriate magnitude. These gate pulses, generated by the gate logic circuit, are essentially in
the digital form. A high level of the gate signal may be taken as on command and a low level
(at ground level) may be taken as off command. Under this assumption, the cathode of the LED
is connected to the ground point of the gate-logic card and anode is fed with the logic card
output. The circuit on the output (photo-diode) side is connected to a floating dc power supply,
as shown in Fig. 33.5. The control (logic card) supply ground is isolated from the floating-supply
ground of the output. In the figure the two grounds have been shown by two different symbols.
The schematic connection shown in the figure indicates that the photo-diode is reverse biased. A
resistor in series with the diode indicates the magnitude of the reverse leakage current of the
diode. When input signal to LED is high, LED conducts and the emitted light falls on the reverse
biased p-n junction. Irradiation of light causes generation of significant number of electron-hole
pairs in the depletion region of the reverse biased diode. As a result magnitude of reverse leakage
current of the diode increases appreciably. The resistor connected in series with the photo-diode
now has higher voltage drop due to the increased leakage current. A signal comparator circuit
senses this condition and outputs a high level signal, which is amplified before being output.
Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate
terminal of the switch (often a small series resistor, as suggested by the switch manufacturer, is
put between the output signal and the gate terminal of the switch).
+VCC (floating)
Photo-diode
L
E
D
Control
Ground
Signal
comparator and
power amplifier
circuit
Output
Floating
Ground
Fig.33.5: A schematic opto-isolator circuit
33.5 Classification of Voltage Source Inverters

Voltage source inverters can be classified according to different criterions. They can be classified
according to number of phases they output. Accordingly there are single-phase or three-phase
inverters depending on whether they output single or three-phase voltages. It is also possible to
have inverters with two or five or any other number of output phases. Inverters can also be
classified according to their ability in controlling the magnitude of output parameters like,
frequency, voltage, harmonic content etc. Some inverters can output only fixed magnitude
(though variable frequency) voltages whereas some others are capable of both variable voltage,
variable frequency (VVVF) output. Output of some voltage source inverters is corrupted by
significant amount of many low order harmonics like 3rd, 5th, 7th, 11th, 13th order of the desired
(fundamental) frequency voltage. Some other inverters may be free from low order harmonics
but may still be corrupted by some high order harmonics. Inverters used for ac motor drive
applications are expected to have less of low order harmonics in the output voltage waveform,
even if it is at the cost of increased high order harmonics. Higher order harmonic voltage
distortions are, in most ac motor loads, filtered away by the inductive nature of the load itself.
Inverters may also be classified according to their topologies. Some inverter topologies are
suitable for low and medium voltage ratings whereas some others are more suitable for higher
voltage applications. The inverters shown in Figs. 33.3(c), 33.4(a) and 33.4(b) are two level
inverters as the pole voltages may acquire either positive dc bus or negative dc bus potential. For
higher voltage applications it may not be uncommon to have three level or five level inverters.
Quiz Problems
1. A large capacitor, put across dc bus of a voltage source inverter, is intended to:
(a) allow a low impedance path to the high frequency component of dc link current.
(b) to minimize high frequency current ripple through the ideal dc source.
(c) to maintain a constant dc link current.
(d) to protect against switch failure.
2. A diode in anti-parallel with the controlled switch, like IGBT, is used in VSI to:
(a) prevent reversal of dc link current.
(b) allow a non-unity power factor load at the output.

(c) protect the circuit against accidental reversal of dc bus polarity.
(d) none of the above.
3. The inverter switches work in fully-on or fully-off mode to achieve:
(a) easier gate control circuit for the switching devices.
(b) minimum distortion in the output voltage waveform.
(c) reduced losses in the switches.
(d) satisfactory operation for non-resistive load at the output.
4. Gate (base) signals to the VSI switches, using n-channel IGBTs, need to be isolated to
allow:
(a) protection of switches against short at the inverter output terminals.
(b) switches to be connected in bridge fashion.
(c) lower losses in the gate drive circuit.
(d) a dc link voltage higher than the switch voltage rating.
(Answers to the quiz problems: 1-a, 2-b, 3-c, 4-b)
Module
5
DC to AC Converters
Lesson
34
Analysis of 1-Phase,
Square - Wave Voltage
Source Inverter

(i)
(ii)
(iii)
Explain the operating principle of a single-phase square wave inverter.

Compare the performance of single-phase half-bridge and full-bridge inverters.
Do harmonic analysis of load voltage and load current output by a single-phase
inverter.
Decide on voltage and current ratings of inverter switches.
(iv)
Voltage source inverters (VSI) have been introduced in Lesson-33. A single-phase square wave
type voltage source inverter produces square shaped output voltage for a single-phase load. Such
inverters have very simple control logic and the power switches need to operate at much lower
frequencies compared to switches in some other types of inverters, discussed in later lessons. The
first generation inverters, using thyristor switches, were almost invariably square wave inverters
because thyristor switches could be switched on and off only a few hundred times in a second. In
contrast, the present day switches like IGBTs are much faster and used at switching frequencies
of several kilohertz. As pointed out in Lesson-26, single-phase inverters mostly use half bridge
or full bridge topologies. Power circuits of these topologies are redrawn in Figs. 34.1(a) and
34.1(b) for further discussions.
P idc
Sw1
+
C_
Edc
+
_
0.5Edc
Edc
O
+
C_
Sw3
Sw1
LOAD
+ Cdc
_
A
LOAD
0.5Edc
Sw2
N
Fig. 34.1(a): A 1-phase half bridge VSI
Sw2
Sw4
N
Fig. 34.1(b): A 1-phase full-bridge VSI
In this lesson, both the above topologies are analyzed under the assumption of ideal circuit
conditions. Accordingly, it is assumed that the input dc voltage (Edc) is constant and the switches
are lossless. In half bridge topology the input dc voltage is split in two equal parts through an
ideal and loss-less capacitive potential divider. The half bridge topology consists of one leg (one
pole) of switches whereas the full bridge topology has two such legs. Each leg of the inverter
consists of two series connected electronic switches shown within dotted lines in the figures.
Each of these switches consists of an IGBT type controlled switch across which an uncontrolled
diode is put in anti-parallel manner. These switches are capable of conducting bi-directional
current but they need to block only one polarity of voltage. The junction point of the switches in
each leg of the inverter serves as one output point for the load.
In half bridge topology the single-phase load is connected between the mid-point of the input dc
supply and the junction point of the two switches (in Fig. 34.1(a) these points are marked as O
and A respectively). For ease of understanding, the switches Sw1 and Sw2 may be assumed to
be controlled mechanical switches that open and close in response to the switch control signal. In
fact in lesson-33 (section 33.2) it has been shown that the actual electronic switches mimic the
function of the mechanical switches. Now, if the switches Sw1 and Sw2 are turned on alternately
with duty ratio of each switch kept equal to 0.5, the load voltage (VAO) will be square wave with
a peak-to-peak magnitude equal to input dc voltage (Edc). Fig. 34.2(a) shows a typical load
voltage waveform output by the half bridge inverter. VAO acquires a magnitude of +0.5 Edc when
Sw1 is on and the magnitude reverses to -0.5 Edc when Sw2 is turned on. Fig. 24.2 also shows
the fundamental frequency component of the square wave voltage, its peak-to-peak magnitude
being equal to 4 Edc . The two switches of the inverter leg are turned on in a complementary
manner. For a general load, the switches should neither be simultaneously on nor be
simultaneously off. Simultaneous turn-on of both the switches will amount to short circuit across
the dc bus and will cause the switch currents to rise rapidly. For an inductive load, containing an
inductance in series, one of the switches must always conduct to maintain continuity of load
current. In Lesson-33 (section 33.2) a case of inductive load has been considered and it has been
shown that the load current may not change abruptly even though the switching frequency is
very high. Such a situation, as explained in lesson-33, demands that the switches must have bidirectional current carrying capability.
34.1 Harmonic Analysis of The Load Voltage And Load Current

Waveforms
The load voltage waveform shown in Fig. 34.2(a) can be mathematically described in terms of its
Fouriers components as:
2E
VAO =
ndc sin(nwt ) (34.1)
n =1,3,5,7,...,
,where n is the harmonic order and w
is the frequency (f) of the square wave. f also

2
happens to be the switching frequency of the inverter switches. As can be seen from the
expression of Eqn. 34.1, the square wave load voltage consists of all the odd harmonics and their
magnitudes are inversely proportional to their harmonic order. Accordingly, the fundamental
frequency component has a peak magnitude of
Edc and the nth harmonic voltage (n being odd
2
Edc . The magnitudes of very high order harmonic voltages
n
become negligibly small. In most applications, only the fundamental component in load voltage
is of practical use and the other higher order harmonics are undesirable distortions. Many of the
practical loads are inductive with inherent low pass filter type characteristics. The current
waveforms in such loads have less higher order harmonic distortion than the corresponding
distortion in the square-wave voltage waveform. A simple time domain analysis of the load
current for a series connected R-L load has been presented below to corroborate this fact. Later,
for comparison, frequency domain analysis of the same load current has also been done.
integer) has a peak magnitude of
34.1.1 Time Domain Analysis

The time domain analysis of the steady state current waveform for a R-L load has been presented
here. Under steady state the load current waveform in a particular output cycle will repeat in
successive cycles and hence only one square wave period has been considered. Let t=0 be the
instant when the positive half cycle of the square wave starts and let I0 be the load current at this
instant. The negative half cycle of square wave starts at t=0.5T and extends up to T. The circuit
equation valid during the positive half cycle of voltage can be written as below:
di
Ri + L = 0.5Edc , for 0 < t < 0.5T ...(34.2)
dt
Similarly the equation for the negative half cycle can be written as
di
Ri + L = 0.5 Edc , for 0.5T < t < T .(34.3)
dt
, where T (=1/f) is the time period of the square wave.
The instantaneous current i during the first half of square wave may be obtained by solving
Eqn.(34.2) and putting the initial value of current as I0.
t
t
0.5 Edc
(1 e ) + I 0 e
for 0 < t < 0.5T ..(34.4)
Accordingly, i (t ) =
R
, where = L/R is the time constant of the R-L load.
The current at the end of the positive half cycle becomes the starting current for the negative half
cycle.
T
T
0.5 Edc
(1 e 2 ) + I 0 e 2 . The
Thus the next half cycle starts with an initial current =
R
circuit equation for the next half cycle may now be written as
i(t ) =
0.5Edc
(1 e
R
T
(t )
2
T
(t )
T
T
2
0.5E
dc
)+
(1 e 2 ) + I 0e 2 e
R
for 0.5T <t< T
Simplifying the above equation one gets:

i (t ) =
t
t
E
0.5 Edc
(1 + e ) + I 0 e + dc e
R
R
(t
T
)
2
, for 0.5T < t < T
.(34.5)
Under steady state, the instantaneous magnitude of inductive load current at the end of a periodic
cycle must equal the current at the start of the cycle. Thus putting t=T in Eqn. (34.5), one gets the
expression for I0 as,
T
T
E T
0.5Edc
(1 + e ) + I 0 e + dc e 2
I0 =
R
R
T 0.5E
T
E T
dc
(1 e ) + dc e 2 1
or, I 0 1 e =
R
R
0.5Edc Edc
0.5Edc 1 e 2
1
.(34.6)
or, I 0 =
= R
T
T
R
R
2
1 + e 2
1 + e
Substituting the above expression for I0 in Eqn. (34.4) one gets,

t
T
0.5 Edc 1 + e 2 2e
i(t ) =
T
R
2
1
e
+
, for 0 < t < 0.5T ....(34.7)
It may be noted from Eqn. (34.7) that the load current at the end of the positive half cycle of
square wave (at t=0.5T) simply turns out to be I0. This is expected from the symmetry of the
load voltage waveform. Load current expression for the negative half cycle of square wave can
similarly be calculated by substituting for I0 in Eqn. (34.5). Accordingly,
i (t ) =
0.5 Edc
R
or, i (t ) =
T
(t )
2
Edc e
+
R
T
1 + e 2
0.5 Edc
R
, for 0.5T < t < T
(t )
2
T
1 + e 2 2e
1 + e 2
, for 0.5T < t < T ............... (34.8)
The current expressions given by Eqns. (34.7) and (34.8) have been plotted in Figs. 34.2(b) to
34.2(e) for different time constants of the R-L load. The current waveforms have been
E
normalized against a base current of 0.5 dc . The square wave voltage waveform, normalized
R
against a base voltage of 0.5Edc has also been plotted together with the current waveforms. It can
be seen that the load current waveform repeats at fundamental frequency and the higher order
harmonic distortions reduce as the load becomes more inductive. For L/R ratio of 2, the 3rd order
harmonic distortion in the load current together with its fundamental component has been shown
in Fig. 34.2(e). In this case, it can be seen that the relative harmonic distortion in load current
waveform is much lower than that of the voltage waveform shown in Fig. 34.2(a). The basis for
calculating the magnitude of different harmonic components of load current waveform has been
shown in the next subsection that deals with frequency domain analysis.
34.1.2 Frequency Domain Analysis

The square shape load voltage may be taken as superposition of different harmonic voltages
described by Eqn. 34.1. The load current may similarly be taken as superposition of harmonic
currents produced by the different harmonic voltages. The load current may be expressed in
terms of these harmonic currents. To illustrate this the series connected R-L load has once again
been considered here. First the expressions for different harmonic components of load current are
calculated in terms of load parameters: R and L/R (or ) and inverter parameters: dc link voltage
(Edc) and time period of square wave (T).
For the fundamental harmonic frequency the load impedance (Z1) and load power factor angle
(1) can be calculated to be
Z1 =
2 2
R 2 + ( 4 L
2)
2 L
and 1 = tan 1
..(34.9)
TR
The load impedance and load power factor angle for the nth harmonic component (Zn and n
respectively) will similarly be given by,
Zn =
2 2 2
R 2 + (4 n L
2)
2 nL
and n = tan 1
..(34.10)
TR
The fundamental and nth harmonic component of load current, (Iload)1 and (Iload)n respectively, can
be found to be
(Iload)1 =
2 Edc
2 Edc
sin( wt 1 ) and (Iload)n =
sin(nwt n ) (34.11)
n Z n
Z1
The algebraic summation of the individual harmonic components of current will result in the
following expression for load current.
I Load =
2 Edc
sin(nwt n ) .(34.12)
n =1,3,5,7,..., n Z n
From Eqns. 34.10 and 34.12 it may be seen that the contribution to load current from very higher
order harmonics become negligible and hence the infinite series based expression for load
current may be terminated beyond certain values of harmonic order n. For L/R ratio = 2T, the
individual harmonic components of load current normalized against a base current of
0.5 Edc
have been calculated below:
R
4
sin( wt tan 1 4 ) = 0.1sin( wt 1.491)
(Iload)1,normalized =
2
1 + 16
4
sin(3wt tan 1 12 ) = 0.011sin(3wt 1.544)
2
3 1 + 144
4
sin(5wt tan 1 20 ) = 0.004sin(5wt 1.555)
2
5 1 + 400
4
sin(7 wt tan 1 28 ) = 0.002sin(7 wt 1.559)
2
7 1 + 784
4
sin(11wt tan 1 44 ) = 0.0008sin(11wt 1.564)
2
11 1 + 1936
It may be concluded that for L/R = 2T, the contribution to load current from 13th and higher
order harmonics are less than 1% of the fundamental component and hence they may be
neglected without any significant loss of accuracy.
Fig. 34.2(f) shows the load voltage and algebraic summation of the first five dominant harmonics
(fundamental, 3rd, 5th, 7th and 11th) in the load current, the expressions for which have been given
above. In Fig. 34.2(g) the load current waveforms of Fig. 34.2(e) and 34.2(f) have been
superimposed for comparison. It may be seen that the load current waveform of Fig. 34.2(f)
calculated using truncated series of the frequency domain analysis very nearly matches with the
exact waveform of Fig. 34.2(e), calculated using time domain analysis.
34.2 Analysis Of The Single-Phase Full Bridge Inverter

Single-phase half bridge inverter has already been described above. The single-phase full bridge
circuit (Fig. 34.1(b)) can be thought of as two half bridge circuits sharing the same dc bus. The
full bridge circuit will have two pole-voltages (VAO and VBO), which are similar to the pole
voltage VAO of the half bridge circuit. Both VAO and VBO of the full bridge circuit are square
waves but they will, in general, have some phase difference. Fig. 34.3 shows these pole voltages
staggered in time by t seconds. It may be more convenient to talk in terms of the phase
displacement angle defined as below:
t
= (2 ) Radians..(34.13)
T
, where t is the time by which the two pole voltages are staggered and T is the time period of
the square wave pole voltages.
The pole voltage VAO of the full bridge inverter may again be written as in Eqn. 34.1, used
earlier for the half bridge inverter. Taking the phase shift angle into account, the pole-B
voltage may be written as
2E
VBO =
ndc sin n(wt ) (34.14)
n =1,3,5,7,...,
Difference of VAO and VBO gives the line voltage VAB. In full bridge inverter the single phase
load is connected between points A and B and the voltage of interest is the load voltage VAB.
Taking difference of the voltage expressions given by Eqns. 34.1 and 34.14, one gets
2E
VAB =
ndc [sin nwt sin n(wt )] (34.15)
n =1,3,5,7,...,
The fundamental component of VAB may be written as

2 Edc
4E
VAB ,1 =
[sin wt sin( wt )] = dc cos( wt ) sin ...(34.16)
2
2
The nth harmonic component in VAB may similarly be written as

2 Edc
4E
n
.(34.17)
VAB ,n =
[sin nwt sin n( wt )] = dc cos n( wt ) sin
n
n
2
2
From Eqn. 34.16, the rms magnitude of the fundamental component of load voltage may be
written as
....(34.18)
(VAB ,1 ) rms = 0.9 Edc sin
2
The rms magnitude of load voltage can be changed from zero to a peak magnitude of 0.9 Edc .
The peak load voltage magnitude corresponds to = 180 degrees and the load voltage will be
zero for = 00. For = 180 degrees, the load voltage waveform is once again square wave of
time period T and instantaneous magnitude E.
As the phase shift angle changes from zero to 1800 the width of voltage pulse in the load voltage
waveform increases. Thus the fundamental voltage magnitude is controlled by pulse-width
modulation.
Also, from Eqns. 34.17 and 34.1 it may be seen that the line voltage distortion due to higher
order harmonics for pulse width modulated waveform (except for = 1800) is less than the
corresponding distortion in the square wave pole voltage. In fact, for some values of phase shift
angle () many of the harmonic voltage magnitudes will drastically reduce or may even get
eliminated from the load voltage. For example, for = 600 the load voltage will be free from 3rd
and multiples of third harmonic.
34.3 Voltage And Current Ratings Of Inverter Switches

Switches in each leg of the inverter operate in a complementary manner. When upper switch of a
leg is on the lower switch will need to block the entire dc bus voltage and vice versa. Thus the
switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. In
practical inverters the switch voltage ratings are taken to be somewhat higher than the worst-case
dc voltage to account for stray voltages produced across stray inductances, the turn-on transient
voltage of a power diode etc. For a well laid out circuit a 50% margin over the dc-bus voltage
may be the optimum switch voltage rating. Each switch of the inverter carries load current during
half of the current cycle. Hence the switches must be rated to withstand the peak magnitude of
instantaneous load current. The semiconductor switches have very small thermal time constant
and they cannot withstand overheating for more than a few milli seconds. Thus even though the
load current passes through the switches only in alternate half cycles, the thermal limit may be
reached during half cycle of current itself. It may be pointed out that each inverter switch
consists of a controlled switch in anti-parallel with a diode. The distribution of current between
the diode and the controlled switch will depend on the load power factor at the operating
frequency. In general both diode as well as the controlled switch should be rated to carry the
peak load current.
34.4 Applications Of Square Wave Inverter

The square wave voltage-source inverter discussed in this lesson finds application in many low
cost ac motor drives, uninterruptible power supply units and in circuits utilizing electrical
resonance between an inductor and a capacitor. Some examples of circuits utilizing resonance
phenomenon are induction heating units and electronic ballasts for fluorescent lamps.
Quiz Problems
1. A single-phase full bridge inverter with square wave pole voltages is connected to a dc
input voltage of 600 volts. What maximum rms load voltage can be output by the
inverter? How much will be the corresponding rms magnitude of 3rd harmonic voltage
(a)
(b)
(c)
(d)
Approximately 270 volts of fundamental and 30 volts of 3rd harmonic voltage

Approx. 480 volts fundamental and 160 volts of 3rd harmonic voltage
2. How does the output power handling capacity of a single-phase half bridge inverter
compare with that of a single-phase full bridge inverter when they are connected to same
dc bus voltage and the peak current capability of the inverter switches is also same. Also
compare their costs.
(a)
(b)
(c)
(d)
The half bridge inverter can output double power but cost also doubles.
The half bridge inverter can output only half the power but cost is less.
The half bridge inverter can output only half the power but cost is nearly same
The output power capability is same but half bridge inverter costs less.
3. A single-phase full bridge inverter is connected to a purely resistive load. Each inverter
switch consists of an IGBT in anti-parallel with a diode. For this load how does the diode
conduction loss compare with the IGBT conduction loss?
(a)
(b)
(c)
(d)
Diode and IGBT will have nearly same conduction loss

Diode conduction loss will be nearly half of the IGBT loss
Diode will have no conduction loss
IGBT will have no conduction loss
4. Using frequency domain analysis estimate the ratio of 5th and 7th harmonic currents in a
purely inductive load that is connected to the output of a single phase half bridge inverter
with square wave pole voltages.
(a)
(b)
(c)
(d)
5th harmonic current will be nearly double of the 7th harmonic current
5th harmonic current will be 40% more than the 7th harmonic current
5th harmonic current will be zero while 7th harmonic current will be present
Both 5th and 7th harmonic currents will be zero
(Answers to the quiz problems: 1-d, 2-b, 3-c, 4-a)
Module
5
DC to AC Converters
Lesson
35
3-Phase Voltage Source
Inverter With Square
Wave Output

(i)
(ii)
(iii)
(iv)
Explain the operating principle of a three-phase square wave inverter.

Understand the limitations and advantages of square-wave inverters.
Do harmonic analysis of load voltage and load current output by the three-phase
sq. wave inverter.
The basic configuration of a Voltage Source Inverter (VSI) has been described in Lesson 33.
Single-phase half-bridge and full-bridge configurations of VSI with square wave pole voltages
have been analyzed in Lesson 34. In this lesson a 3-phase bridge type VSI with square wave pole
voltages has been considered. The output from this inverter is to be fed to a 3-phase balanced
load. Fig. 35.1 shows the power circuit of the three-phase inverter. This circuit may be identified
as three single-phase half-bridge inverter circuits put across the same dc bus. The individual pole
voltages of the 3-phase bridge circuit are identical to the square pole voltages output by singlephase half bridge or full bridge circuits. The three pole voltages of the 3-phase square wave
inverter are shifted in time by one third of the output time period. These pole voltages along with
some other relevant waveforms have been plotted in Fig. 35.2. The horizontal axis of the
waveforms in Fig. 35.2 has been represented in terms of t, where is the angular frequency
(in radians per second) of the fundamental component of square pole voltage and t stands for
time in second. In Fig. 35.2 the phase sequence of the pole voltages is taken as VAO, VBO and
VCO. The numbering of the switches in Fig. 35.1 has some special significance vis--vis the
output phase sequence.
P idc
Edc
+ Cdc
_
A
Sw5
Sw3
Sw1
N
3-phase
balanced load
Sw4
Sw6
Sw2
Fig. 35.1: A 3-phase Voltage Source Inverter (VSI) feeding a balanced load
VAO
0.5Edc
Sw1
Sw1
Sw4
- 0.5Edc
Sw4
VBO
0.5Edc
Sw3
Sw6
Sw3
Sw6
VCO
- 0.5Edc
Sw6
0.5Edc
Sw5
Sw5
Sw2
Sw5
Sw2
- 0.5Edc
Edc
VAB
0
-Edc
2/3Edc
VAN
1/3Edc
-1/3Edc
-2/3Edc
2/3Edc
VBN
1/3Edc
-1/3Edc
0
/3 2/3
4/3 5/3 2
-2/3Edc
7/3 8/3 3 10/3 11/3 3
Fig. 35.2: Some relevant voltage waveforms output by a 3-phase square wave VSI
To appreciate the particular manner in which the switches have been numbered, the conductionpattern of the switches marked in Fig. 35.2 may be noted. It may be seen that with the chosen
numbering the switches turn on in the sequence:- Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw1, Sw2,
.and so on. Identifying the switching cycle time as 360 degrees (2 radians), it can be seen that
each switch conducts for 1800 and the turning on of the adjacent switch is staggered by 60
degrees. The upper and lower switches of each pole (leg) of the inverter conduct in a
complementary manner. To reverse the output phase sequence, the switching sequence may
simply be reversed.
Considering the symmetry in the switch conduction pattern, it may be found that at any time
three switches conduct. It could be two from the upper group of switches, which are connected to
positive dc bus, and one from lower group or vice-versa (i.e., one from upper group and two
from lower group). According to the conduction pattern indicated in Fig. 35.2 there are six
combinations of conducting switches during an output cycle:- (Sw5, Sw6, Sw1), (Sw6, Sw1,
Sw2), (Sw1, Sw2, Sw3), (Sw2, Sw3, Sw4), (Sw3, Sw4, Sw5), (Sw4, Sw5, Sw6). Each of these
combinations of switches conducts for 600 in the sequence mentioned above to produce output
phase sequence of A, B, C. As will be shown later the fundamental component of the three
output line-voltages will be balanced. The load side phase voltage waveforms turn out to be
somewhat different from the pole voltage waveforms and have been dealt with in the next
section.
35.1 Determination Of Load Phase-Voltages

Fig. 35.1 shows a star connected balanced 3-phase load. The three load terminals are connected
to the three output points (A, B, C) of the inverter. The neutral point N of the load is
deliberately left open for some good reasons mentioned later. The load side phase voltages VAN,
VBN and VCN can be determined from the conduction pattern of the inverter switches. With
reference to Fig. 35.2, it may be seen that for 0t/3, switches Sw5, Sw6 and Sw1 conduct.
Under the assumption of ideal switches Fig. 35.3(a) will represent the equivalent inverter and
load circuit during the time interval 0t/3. In the equivalent circuit representation the nonconducting switches have been omitted and a cross (X) sign is used to represent a conducting
switch. For a balanced 3-phase load the instantaneous phase voltage waveforms have been
derived below for the following two cases (i) when the 3-phase load is purely resistive and (ii)
when the load, in each phase, consists of a resistor in series with an inductor and a back e.m.f. In
both the cases the equivalent circuit of Fig. 35.3(a) has been referred to derive the expression for
load-phase voltage.
Sw1
X
Sw5
X
Sw6
X
+
Edc _
VAN = 1/3 Edc

VBN = -2/3 Edc
VCN = 1/3 Edc
Fig. 35.3(a): Schematic load circuit during conduction of Sw5, Sw6 and Sw1
For case (i), when the load is a balance resistive load, it is very easy to see that the instantaneous
phase voltages, for 0t/3, will be given by VAN = 1/3 Edc, VBN = -2/3 Edc, VCN = 1/3 Edc.
For case (ii), the following circuit relations hold good.
di
di
di A
+ E A , VBN = RiB + L B + EB , VCN = RiC + L C + EC ...(35.1)
dt
dt
dt
= Edc , VAN = VCN ....(35.2)
VAN = RiA + L
VAN VBN
where, iA , iB , iC
are the instantaneous load-phase currents entering phases A, B and C
respectively. EA , EB and EC are the instantaneous magnitudes of load phase-emfs. R and L are
the per-phase load resistance and inductance that are connected in series with the corresponding
phase-emf. Since the load is balanced (with its neutral point floating) the algebraic sum of the
instantaneous phase currents and the phase emfs will be zero. Accordingly,
iA + iB + iC = 0 and EA + EB + EC = 0(35.3)
From Eqns. 35.1 and 35.3, the following may be deduced:
d (i + i )
di
VAN + VCN = R (i A + iC ) + L A C + ( E A + EC ) = ( RiB + L B + EB ) = VBN .... (35.4)
dt
dt
Now from Eqns. 35.2 and 35.4 it can be easily found that VAN = 1/3 Edc, VBN = -2/3 Edc, VCN =
1/3 Edc.
Thus the instantaneous magnitudes of load phase voltages, in case of a more general (but
balanced) R-L-E load are same as in case of a simple balanced resistive load.
Fig. 35.3(b) shows the equivalent circuit during /3t2/3, when the switches Sw6, Sw1 and
Sw2 conduct. The instantaneous load phase voltages may be found to be VAN = 2/3 Edc, VBN =
VCN = -1/3 Edc.
+
Edc _
Sw1
X
Sw2
X
Sw6
X
VAN = 2/3 Edc

VBN = -1/3 Edc
VCN = -1/3 Edc
Fig. 35.3(b): Schematic load circuit during conduction of Sw6, Sw1 and Sw2
The load phase voltage waveforms for other switching combinations may be found in a similar
manner. Two of the phase voltages, VAN and VBN , along with line voltage VAB have been plotted
over two output cycles in Fig. 35.2. It may be seen that voltage VBN is similar to VAN but lags it
by one third of the output cycle period. Further, it can be verified that the load phase voltage VCN
also has a waveform identical to the two other phase voltages but time displaced by one third of
the output time period. VCN waveform leads VAN by 120 degrees in the time (t) frame. It
should be obvious that the fundamental component of the phase voltage waveforms will
constitute a balanced 3-phase voltage having a phase sequence A, B, C. It may also be recalled
that by suitably changing the switching sequence the output phase sequence can be changed. The
phase voltage waveforms of Fig. 35.2 show six steps per output cycle and are also referred as the
six-stepped waveform. A more detailed analysis of the load voltage waveforms is done in the
following section.
35.2 Harmonic Analysis Of Load Voltage Waveforms

The individual pole voltage waveforms output by the 3-phase square wave inverter are identical
to the output waveform of a single-phase half bridge inverter. As a consequence, the harmonic
analysis of the voltage waveform presented in section 34.1 of Lesson 34 is valid here too. The
expression for line voltage VAB is identical to the one given in Lesson 34 (Eqn.34.15), with
of Eqn. 34.15 replaced by 2/3 radians. For convenience the expressions for pole-A voltage
VAO and line voltage VAB are reproduced below in Eqns.35.5 and 35.6. The relevant
waveforms are shown in Fig.35.2.
VAO =
2 Edc
sin(nwt ) .....(35.5)
n =1,3,5,7,..., n
2 Edc
2
sin nwt sin n( wt
) ....(35.6)
n
3
n =1,3,5,7,...,
Using equations 35.5 and 35.6, the expressions for remaining pole and line voltages can be
written simply by shifting the time (t) origin by the phase shift angle shown in Fig.35.2.
Accordingly the expressions for pole voltage VBO and line voltage VBC are written below in Eqns.
35.7 and 35.8 respectively.
2E
2
VBO =
ndc sin n(wt 3 ) ...(35.7)
n =1,3,5,7,...,
VAB =
2
4
sin n( wt 3 ) sin n( wt 3 ) ....(35.8)

It may be verified that difference of VAO and VBO leads to the expression for VAB . The
expression for a particular harmonic component in the voltage waveforms is determined simply
by substituting n in above equations by the harmonic order. Accordingly the fundamental
magnitude of line voltages VAB , VBC and VCA can be written as:
VBC =
2 Edc
n=1,3,5,7,..., n
2 Edc
2 2 3Edc
sin wt sin( wt
) =
sin( wt + )
6
2 3Edc
2 3Edc
7
VBC ,1 =
sin( wt ) , VCA,1 =
sin( wt
)
2
6
The three fundamental line voltages are balanced (have identical magnitudes and are phase apart
by 1200). For most practical loads only the fundamental component of the inverter output voltage
is of interest. However the inverter output also contains significant amount of higher order
harmonic voltages that cause undesirable distortion of the output waveform. It may, though, be
noted that there are no even harmonics and the line voltages are free from 3rd and multiples of 3rd
order harmonics. Also, as the harmonic order (n) increases their magnitudes decrease inversely
with the harmonic order. When expressed as a fraction of fundamental voltage magnitude, the
line voltage distortions are mainly due to 20% of 5th harmonic, nearly 14% of 7th, nearly 9% of
VAB ,1 =
11th and nearly 8% of 13th harmonic. Since most loads are inductive in nature with a low pass
filter type characteristics the effect of very high order harmonics may be neglected.
It may be noted that though the pole voltages have 3rd and multiples of 3rd order harmonic
distortions, the line voltages are free from these distortions. Hence the load neutral point, rather
than being connected to the mid-potential point of the input dc supply (as in a single-phase half
bridge inverter), is deliberately left floating. The floating neutral point does not allow a closed
path for the 3rd and multiples of 3rd harmonic currents to flow (3rd or multiples of 3rd harmonic
current, if present in the load phases, have identical instantaneous magnitudes in all the three
phases and their algebraic sum needs to flow in or out of the load neutral point). By keeping the
load neutral point floating, not only the need for bringing out the mid-potential point of dc
supply is done away with, the triplen harmonic distortions of the load current is totally
eliminated. Since there are no triplen harmonic currents in the load, the load-phase voltages are
also free from triplen harmonic distortions. In fact the six-stepped load-phase voltages shown in
Fig. 35.2 are found to be free from triplen harmonics. It turns out that by removing all triplen
harmonics from the square-shaped pole voltage waveform one can arrive at the corresponding
load-phase (six-stepped) voltage waveform. Accordingly the load-phase voltages may be
expressed in terms of its harmonic contents as shown below.
2 Edc
VAN =
sin(nwt ) .....(35.9)
n =1,5,7,11,13..., n
VBN =
2 Edc
2
sin n( wt
) ...(35.10)
n
3
n=1,5,7,11,13...,
VCN =
2 Edc
2
sin n( wt +
) ...(35.11)
3
n=1,5,7,11,13..., n
For a balanced three-phase load, the instantaneous magnitude of any phase current can be
determined by superposition of different harmonic currents of the phase. For a simple threephase R-L load, the phase-A current ( iA ) expression in terms of resistance (R) and inductance
(L) of the load may be written as:
iA =
n=1,5,7,11,13...,
2 Edc
n R 2 + n 2 2 L2
sin[nwt tan 1 (
n L
)] .....(35.12)
R
Phase-B and phase-C current expressions can be obtained simply by replacing t in Eqn. 35.12
2
2
by ( t
) respectively. A close look at Eqn. 35.12 will reveal that for a
) and ( t +
3
3
purely inductive 3-phase load the 5th, 7th, 11th and 13th harmonic distortion in the load current (as
a percentage of fundamental component of current) will respectively be 4%, 2.04%, 0.83% and
0.59%. These distortions are much less than the corresponding distortions in the load voltage
waveforms. As a result the load current for highly inductive R-L load will have close to
sinusoidal shape.
35.3 Voltage And Current Ratings Of Inverter Switches

As in a single-phase square-wave inverter, switches in each leg of the three-phase inverter
operate in a complementary manner. When upper switch of a leg is on the lower switch will need
to block the entire dc bus voltage and vice versa. Thus the switches must be rated to block the
worst-case instantaneous magnitude of dc bus voltage. An extra safety margin over the worstcase dc voltage, as discussed in Lesson-34, section 34.3, is recommended. Each inverter-switch
carries load-phase current during half of the current cycle. Hence the switches must be rated to
withstand the peak expected magnitude of instantaneous load-phase current. For a non-unity
power factor load, the diode connected in anti-parallel with the switch will conduct part of the
switch current. The distribution of current between the diode and the controlled switch will
depend on the load power factor at the operating frequency. In general both diode as well as the
controlled switch should be rated to carry the peak load current. These diodes also need to block
a peak reverse voltage equal to worst case voltage across the switches.
35.4 Use And Limitations Of 3-Phase Square Wave Inverter

The three-phase square wave inverter as described above can be used to generate balanced threephase ac voltages of desired (fundamental) frequency. However harmonic voltages of 5th, 7th
and other non-triplen odd multiples of fundamental frequency distort the output voltage. In many
cases such distortions in output voltages may not be tolerable and it may also not be practical to
use filter circuits to filter out the harmonic voltages in a satisfactory manner. In such situations
the inverter discussed in this lesson will not be a suitable choice. Fortunately there are some
other kinds of inverters, namely pulse width modulated (PWM) inverters, discussed in the next
lesson, which can provide higher quality of output voltage.
The square wave inverter discussed in this lesson may still be used for many loads, notably ac
motor type loads. The motor loads are inductive in nature with the inherent quality to suppress
the harmonic currents in the motor. The example of a purely inductive load discussed in the
previous section illustrates the effectiveness of inductive loads in blocking higher order harmonic
currents. In spite of the inherent low-pass filtering property of the motor load, the load current
may still contain some harmonics. These harmonic currents cause extra iron and copper losses in
the motor. They also produce unwanted torque pulsations. Fortunately the torque pulsations due
to harmonic currents are of high frequencies and their effect gets subdued due to the large
mechanical inertia of the drive system. The motor speed hardly changes in response to these
torque pulsations. However in some cases torque pulsations of particular frequencies may cause
unwanted resonance in the mechanical system of the drive. A special notch filter may then be
required to remove these frequencies from the inverter output voltage.
The input dc voltage to the inverter is often derived from an ac source after rectification and
filtering. A simple diode bridge rectifier followed by a filter capacitor is often the most costeffective method to get dc voltage from ac supply. In some applications, like in un-interrupted
power supplies, the dc input may be coming from a bank of batteries. In both these examples, the
input dc magnitude is fairly constant. With fixed input dc voltage the square-wave inverter can
output only fixed magnitude of load voltage. This does not suit the requirement in many cases
where the load requires a variable voltage variable frequency (VVVF) supply. In order that ac
output voltage magnitude is controllable, the inverter input voltage will need to be varied using
an additional dc-to-dc converter. However a better solution will be to use a PWM inverter (to be
discussed in the next lesson), which can provide a VVVF output with enhanced output voltage
quality.
In spite of the limitations, discussed above, the square wave inverter may be a preferred choice
on account of its simplicity and low cost. The switch control circuit is very simple and the
switching frequency is significantly lower than in PWM inverters. This results in low switching
losses. The switch cost may also be lower as one may do away with slower switching devices
and slightly lower rated switches. Another advantage over PWM inverter is its ability to output
higher magnitude of fundamental voltage than the maximum that can be output from a PWM
inverter (under the given dc supply condition). Listed below are two applications where a 3phase square wave inverter could be used.
(i)
A low cost solid-state frequency changer circuit: This circuit converts the 3-phase ac
(input) voltages of one frequency to 3-phase ac (output) voltages of the desired
frequency. The input ac is first converted into dc and then converted back to ac of new
frequency. The square wave inverter discussed in this lesson may be used for dc to ac
conversion. Such a circuit may, for example, convert 3-phase ac voltages of 50 Hz to 3phase ac voltages of 60 Hz. The input to this circuit could as well have come from a
single-phase supply, in which case the single-phase ac is first converted into dc and
then converted back to 3-phase ac of the desired frequency.
(ii)
An uninterrupted power supply circuit: Uninterrupted power supply circuits are used to
provide uninterrupted power to some critical load. Here a critical load requiring 3phase ac supply of fixed magnitude and frequency has been considered. In case ac
mains supply fails, the 3-phase load may be electronically switched, within few
milliseconds, to the output of the 3-phase square wave inverter. Input dc supply of the
inverter often comes from a battery bank.
Problems
(1)
A 3-phase square wave inverter feeds a balanced 3-phase resistive-inductive load. The
load phase current will contain, apart from the fundamental frequency current, the
following harmonic currents:
(a)
(b)
(c)
(d)
(2)
The six-stepped load phase voltage of a 3-phase square wave inverter, with a dc link
voltage of 100 volts, will have the following rms magnitudes of 1st, 3rd and 5th harmonic
voltages:
(a)
(b)
(c)
(d)
(3)
All odd multiples of fundamental

All odd and even multiples of fundamental
All even multiples of fundamental except 6th and multiples of 6th
All odd multiples of fundamental except 3rd and multiples of 3rd
10V, 30V and 50V respectively

100V, 33.3V and 20V respectively
90V, 30V and 0 respectively
45V, 0 and 9V respectively
A 3-phase square wave inverter, fed from a fixed dc input, is capable of producing the
following type of ac (fundamental component) voltages:
(a)
(b)
(c)
(d)
(4)
Variable voltage variable frequency type

Fixed voltage variable frequency type
Variable voltage fixed frequency type
None of the above
A 3-phase square wave inverter feeds a balanced 3-phase inductance type load. The
worst-case load phase current (peak magnitude) is expected to be 100 amps and the
worst-case dc input voltage is expected to be 600 volts. The diodes of the inverter will be
subjected to the following peak voltage and current stresses:
(a)
(b)
(c)
(d)
600V, 100A
600V, 70.7A
424V, 70.7A
424V, 100A
(Answers: 1-d, 2-d, 3-b, 4-a)
Module
5
DC to AC Converters
Lesson
36
3-Phase Pulse Width
Modulated (PWM)
Inverter

(i)
(ii)
(iii)
(iv)
Explain the philosophy behind PWM inverters.

Understand the advantages and disadvantages of PWM inverters.
Compare the quality of output voltage produced by different PWM inverters
Pulse width modulated (PWM) inverters are among the most used power-electronic circuits in
practical applications. These inverters are capable of producing ac voltages of variable
magnitude as well as variable frequency. The quality of output voltage can also be greatly
enhanced, when compared with those of square wave inverters discussed in Lesson-35. The
PWM inverters are very commonly used in adjustable speed ac motor drive loads where one
needs to feed the motor with variable voltage, variable frequency supply. For wide variation in
drive speed, the frequency of the applied ac voltage needs to be varied over a wide range. The
applied voltage also needs to vary almost linearly with the frequency. PWM inverters can be of
single phase as well as three phase types. Their principle of operation remains similar and hence
in this lesson the emphasis has been put on the more general, 3-phase type PWM inverter.
There are several different PWM techniques, differing in their methods of implementation.
However in all these techniques the aim is to generate an output voltage, which after some
filtering, would result in a good quality sinusoidal voltage waveform of desired fundamental
frequency and magnitude. As will be discussed later in this chapter, for the inverter topology
considered here, it may not be possible to reduce the overall voltage distortion due to harmonics
but by proper switching control the magnitudes of lower order harmonic voltages can be
reduced, often at the cost of increasing the magnitudes of higher order harmonic voltages. Such a
situation is acceptable in most cases as the harmonic voltages of higher frequencies can be
satisfactorily filtered using lower sizes of filter chokes and capacitors. Many of the loads, like
motor loads have an inherent quality to suppress high frequency harmonic currents and hence an
external filter may not be necessary.
To judge the quality of voltage produced by a PWM inverter, a detailed harmonic analysis of the
voltage waveform needs to be done. In the following discussions some of the results of harmonic
analysis done in the previous lessons have been borrowed. In Lesson-35, while discussing the 3phase square wave inverter it was shown that the magnitudes of fundamental components of the
inverter pole voltage (voltage between the output of an inverter leg and the mid potential point of
the input dc supply) and the load phase voltage are identical provided the load is a balanced 3phase load. In fact, after removing 3rd and multiples of 3rd harmonics from the pole voltage
waveform one obtains the corresponding load phase voltage waveform. The pole voltage
waveforms of 3-phase inverter are simpler to visualize and analyze and hence in this lesson the
harmonic analysis of load phase and line voltage waveforms is done via the harmonic analysis of
the pole voltages. It is implicit that the load phase and line voltages will not be affected by the 3rd
and multiples of 3rd harmonic components that may be present in the pole voltage waveforms.
36.1 Nature Of Pole Voltage Waveforms Output By PWM

Inverters
Unlike in square wave inverters the switches of PWM inverters are turned on and off at
significantly higher frequencies than the fundamental frequency of the output voltage waveform.
The typical pole voltage waveform of a PWM inverter is shown in Fig. 36.1 over one cycle of
output voltage. In a three-phase inverter the other two pole voltages have identical shapes but
they are displaced in time by one third of an output cycle. Compared to the square pole voltage
waveform seen in Lesson-35, the pole voltage waveform of the PWM inverter changes polarity
several times during each half cycle. The time instances at which the voltage polarities reverse
have been referred here as notch angles. It may be noted that the instantaneous magnitude of pole
voltage waveform remains fixed at half the input dc voltage (Edc). When upper switch (SU),
connected to the positive dc bus is on, the pole voltage is + 0.5 Edc and when the lower switch
(SL), connected to the negative dc bus, is on the instantaneous pole voltage is - 0.5 Edc. The
switching transition time has been neglected in accordance with the assumption of ideal
switches. It is to be remembered that in voltage source inverters, meant to feed an inductive type
load, the upper and lower switches of the inverter pole conduct in a complementary manner. That
is, when upper switch is on the lower is off and vice-versa. Both upper and lower switches
Pole
Voltage
0.5Edc
SU
SU
SU
SU
SU
SU
SU
SU
SU
t
0
SL
SL
SL
SL
SL
SL
SL
SL
SL
-0.5Edc
1
0
/2
4
-3
-4
-1 +1 +3
3/2
2-3 2-1
+4
2-4
2-2 2
-2
+2
Fig.36.1: A typical pole-voltage waveform of a PWM inverter

should not remain on simultaneously as this will cause short circuit across the dc bus. On the
other hand one of these two switches in each pole (leg) must always conduct to provide
continuity of current through inductive loads. A sudden disruption in inductive load current will
cause a large voltage spike that may damage the inverter circuit and the load.
36.2 Harmonic Analysis Of Pole Voltage Waveform

The pole voltage waveform shown in Fig. 36.1 has half wave odd symmetry and quarter-wave
mirror symmetry. The half wave odd symmetry of any repetitive waveform f(t), repeating after
every 2/ duration, is defined by f(t) = - f(+t). Such a symmetry in the waveform amounts
to absence of dc and even harmonic components from the waveform. All inverter output voltages
maintain half wave odd symmetry to eliminate the unwanted dc voltage and the even harmonics.
The half wave odd symmetry followed by quarter wave mirror symmetry, defined by f(t) = f(t), results in presence of only sine components in the Fourier series representation of the
waveform. It may be verified that quarter wave symmetry may not hold good once the time
origin is shifted arbitrarily. However the half-wave odd symmetry is maintained in spite of
shifting of time origin. This is quite expected, as by just shifting the time origin new (even)
harmonic frequencies will not creep up in the voltage waveform, whereas by shifting time origin
the sine wave may become cosine or may have some other phase-shift. The quarter wave
symmetry talked above is not necessary for improvement of the output waveform quality; it
merely simplifies the Fourier analysis of the pole voltage waveform. It may also be noted that the
quarter wave symmetry is not achieved at the cost of compromising the inverters output
capability (in terms of magnitude and quality of achievable output voltage).
With the assumed quarter wave mirror symmetry and half wave odd symmetry the waveform
shown in Fig. 36.1 may be decomposed in terms of its Fourier components as below:-
VAO =
n=1,3,5,....
bn sin n t ..(36.1)
where VAO is the instantaneous magnitude of the pole voltage shown in Fig. 36.1 and
bn is the peak magnitude of its nth harmonic component. Because of the half wave and quarter
wave symmetry of the waveform, mentioned before, the pole voltage has only odd harmonics
and has only sinusoidal components in the Fourier expansion. Thus the pole voltage will have
fundamental, third, fifth, seventh, ninth, eleventh and other odd harmonics. The peak magnitude
of nth harmonic voltage is given as:
2E
bn =
(1 2 cos n1 + 2 cos n 2 2 cos n 3 + 2 cos n 4 ) ..(36.2)
n
, where 1 , 2 3 and 4 are the four notch angles in the quarter cycle ( 0 t 2 ) of
the waveform.
Now, as described in the beginning of this lesson, the third and multiples of third
harmonics do not show up in the load phase and line voltage waveforms of a balanced 3-phase
load. Most of the three phase loads of interest are of balanced type and for such loads one need
not worry about triplen (3rd and multiples of 3rd) harmonic distortion of the pole voltages. The
peak magnitudes of fundamental ( b1 ) and three other lowest order harmonic voltages that matter
most to the load can be written as:
2E
b1 =
(1 2 cos 1 + 2 cos 2 2 cos 3 + 2 cos 4 ) ...(36.3)
2E
(1 2 cos 51 + 2 cos 5 2 2 cos 5 3 + 2 cos 5 4 ) ...(36.4)
5
2E
b7 =
(1 2 cos 71 + 2 cos 7 2 2 cos 7 3 + 2 cos 7 4 ) ..(36.5)
5
2E
b11 =
(1 2 cos111 + 2 cos11 2 2 cos11 3 + 2 cos11 4 ) ...(36.6)
11
It can be seen that the 3rd and 9th harmonics have been not considered, as they will not appear in
the load side phase and line voltages. Most of the industrial loads are inductive in nature with an
b5 =
inherent quality to attenuate currents due to higher order harmonic voltages. Thus after
fundamental voltage, the other significant voltages for the load are 5th, 7th and 11th etc.
Generally, only the fundamental frequency component in the output voltage is of interest and all
other harmonic voltages are undesirable. As such one would like to eliminate as many low order
harmonics as possible. Accordingly the fundamental voltage magnitude ( b1 ) may be set at the
desired value and the magnitudes of fifth ( b5 ), seventh ( b7 ) and eleventh ( b11 ) harmonics may
be set to zero. These voltage magnitudes when substituted in the expressions given by Eqns. 36.3
to 36.6 will lead to the solutions of the notch angles. One may like to eliminate many more
unwanted harmonic frequencies from the load voltage waveform but this will require
introduction of more notch angles per quarter cycle of the pole voltage. In fact if there are k
notch angles per quarter cycle, k number of equations may be written each of which determines
the magnitude of a particular harmonic voltage. Now, each time a notch angle is encountered in
the pole voltage waveform, the top and bottom switches of that particular pole undergo a
switching transition (on to off or vice versa). The switching frequency (fsw) of the inverter
switches can be equated to
fsw = 2 k f1
...........(36.7)
, where one turn-on and one turn-off has been taken as one switching cycle, k is the number of
notches per quarter cycle and f1 is the frequency of fundamental component in the output
voltage. Thus it can be seen that a better quality output waveform (in terms of elimination of
more numbers of unwanted harmonic voltages) comes at the cost of increasing the switching
frequency of the inverter. The switching frequency is directly proportional to the switching
losses in the inverter switches. Also, the switch must be capable of being switched on and off at
the required frequency. The IGBT switches used in medium power inverters are generally
switched at a frequency of 20 kHz or more. With a switching frequency of 20 kHz and the output
(fundamental) frequency of 50 Hz there will be up to 200 notches per quarter cycle of the output
waveform. The load voltage can thus be made virtually free of low order harmonics and the load
current (for an inductive load) can be expected to have a good quality sinusoidal waveform. The
switching frequency of 20 kHz is important in another sense too. The range of audible noise for
human beings extends from few Hertz to 20 kHz. Thus if the switching frequency is 20 kHz or
beyond, the switching frequency related audible noise will not be present when the inverter
operates. The inverter operation can then be very quite. If the inverter operates at low frequency,
the connecting wires to the switches etc. also carry low frequency current producing low
frequency vibrations (due to interaction of current with the stray magnetic field produced by
other conductors etc.) and result in audible noise. Similarly low frequency current through
inductors and transformers also produce audible noise. The humming or whistling type noise due
to low switching frequency may at times be too annoying and unacceptable.
36.3 Trade Off Between Low Order And High Order Harmonics
The 3-phase inverter with six switches connected in the bridge fashion is also known as a twolevel inverter because the inverter pole-voltage alternates between the two voltage levels of +0.5
Edc and - 0.5 Edc (the switching transition time has been neglected). The root mean square (rms)
of the pole voltage equals 0.5 Edc. Now a periodic function f ( t ) when expressed in terms of
its Fourier components satisfies the following mathematical identity.
[ f ( t )rms ]2 = f ( t )1,rms
n = 2,3,4,....,
f ( t ) n ,rms ..(36.8)
In Eqn. (36.8), f ( t )rms is the rms magnitude of the given periodic waveform where as
f ( t )1,rms and f ( t )n,rms are the rms magnitudes of the fundamental component and nth
harmonic component of the waveform respectively.
Also, if the waveform f ( t ) has half wave odd symmetry and quarter wave mirror symmetry,
its fundamental voltage can be expressed as
f ( t )1,rms =
{ f ( t ) sin t}d t ....(36.9)
t =0
Now let f ( t ) in the above equations (36.8 and 36.9) be replaced by the two-level pole voltage
waveform of the PWM inverter. The term on the left hand side of Eqn. (36.8) equals (0.5Edc)2.
The first term on the right hand side of Eqn. (36.8) is the square-of-rms (i.e., mean of square)
magnitude of the fundamental component of pole voltage whereas the second term on the right
hand side denotes the mean-of-square magnitude of the unwanted ripple in the pole voltage. As
can be seen, the rms magnitude of the fundamental pole voltage is always going to be less than
0.5Edc. Further, as given by Eqn. (36.9), the fundamental magnitude (rms) of PWM inverters
output pole-voltage will be less than 0.45Edc, which is the rms magnitude of fundamental pole
voltage of a 3-phase square wave inverter. [In case of square wave output, both f ( t ) and
sin t are positive during 0 t but the sign of f ( t ) in PWM waveform alternates
between positive and negative values.]
In case of PWM inverter the magnitude of fundamental output voltage is fixed by suitable pulse
width modulation (by selection of suitable notch angles for the waveform in Fig. 36.1). However,
as can be seen from Eqn. (36.8), the reduction in fundamental magnitude leads to increase in the
rms magnitude of the unwanted ripple voltage. Also, after fixing the fundamental voltage
magnitude if it is desired to eliminate some of the low order harmonics, it will be at the cost of
increasing the magnitudes of higher order harmonics. Thus, as far as the quality of inverter pole
voltage alone is concerned the PWM technique is not helping. However considering the fact that
most of the loads are inductive in nature with low pass filter type characteristics the load current
quality effectively improves by eliminating lower order harmonics from the pole voltage
waveform (even if the higher order harmonic magnitudes increase). In case the load, on its own,
is not able to filter out the harmonic voltages satisfactorily the inverter output may be passed
through some external filter before being applied to load. The required size of the external filter
will be small if the inverter output is free from low frequency harmonics.
36.4 Brief Description Of Some Popular PWM Techniques

The schematic PWM waveform shown in Fig. 36.1, is only representative in nature. The logic
described to select notch angles is also specific to one particular PWM technique that is known
as selective harmonic elimination technique. There are several other PWM techniques, the
important ones are:- SINE-PWM technique, Space Vector based PWM technique, Hysteresis
current controller based PWM technique etc. A few of these techniques have been dealt with, in
detail in the next few lessons.
Some of the PWM techniques can be realized using analog circuits alone; some others are more
easily realized with the help of digital processors like microprocessor, Digital signal processor
(DSP) or Personal Computer (PC), whereas some other PWM controllers could be a hybrid
between analog and digital circuits. For example, the selective harmonic elimination technique
described above requires numerical solutions of the transcendental equations for arriving at the
required notch angles. These transcendental equations are solved off-line and the information
regarding notch angles (switching instances) is stored in digital memory, like EPROM. It may be
realized that the notch instances may not occur at regular time intervals. Similarly fundamental
output voltage requirement may not remain fixed for all output frequencies and hence the
transcendental equations (similar to Eqns. 36.3 to 36.6) will be different for different output
frequencies. Also, as per Eqn. 36.7, if the switching frequency is kept constant, there will be
more notch angles (per quarter cycle) at low output frequencies and less number of notches at
higher frequencies. Thus the set of notch angles for one frequency may be different from the
notch angles at some other frequency. For satisfactory implementation of this technique,
generally the desired output frequency range is divided in few discrete frequencies. For example,
it may be desired to output a 3-phase balanced voltage in the frequency range of 5 Hz to 50 Hz
with the constraint that the ratio between output voltage magnitude and output frequency should
remain fixed to some predetermined value. Under this situation the output voltage range may be
discretized in steps of, say, 1Hz. Thus the available output may vary from 5 Hz to 50 Hz through
the following discrete values of intermediate frequencies: 6 Hz, 7 Hz, 8 Hz, , 49 Hz. The
desired magnitudes of output voltage for all these discrete frequencies is found out and
accordingly the notch angles are calculated to eliminate as many unwanted harmonics as possible
(keeping in mind the constraint on switching frequency). Now switching information for
successive output frequencies may be stored in successive memory blocks. For each of these
output frequencies, it may be convenient to discretize one complete output cycle time interval in
small steps (say, in steps of 10 microseconds) and the inverter switching word (as described
below) at these successive time intervals are then stored in the successive memory locations. The
switching word combines the switching information for all three legs (all six switches) of the
inverter and may be obtained in the form of a six bit binary word, each bit corresponding to one
particular switch. When a particular bit value is 1 that particular switch may require being
turned-on. Similarly 0 bit value may correspond to turn-off command of the switch. Now if the
memory block, containing switching information is addressed sequentially after every 10
microsecond (this being the time step, chosen above, to discretize the output cycle time period)
the desired switching pattern for the inverter switches may be obtained. The notch angles can
thus be realized with a maximum time error of 10 microseconds (which for 50 Hz output
corresponds to an error of 0.180 only). After completion of one output cycle the next cycle is
simply repeated like the previous one. One may move from one memory block to another
memory block (by suitably multiplexing the memory address-word) to obtain the inverterswitching pattern for some other output frequency. The selective harmonic elimination technique
described above is also known as stored-PWM technique. The overall memory requirement may
be large but since the memory cost has been reducing over the years the stored-PWM technique
remains one of the most attractive techniques.
In contrast to the selective harmonic elimination technique discussed above, some other PWM
techniques, notably SINE-PWM and Space Vector-PWM techniques, try to match the mean
value of load voltage under the rectangular PWM waveform with the mean voltage of the desired
output waveform over every small time interval of the output cycle. If, for example, the desired
output voltage is a sinusoidal waveform of a given magnitude and of frequency f1, then for
every small time interval t of the output cycle period (such that t << 1/ f1) the mean (dc)
magnitude under desired sine wave and the mean dc voltage under the PWM pulses are made
equal. Now barring the mismatch in the instantaneous magnitudes of the sine wave and the PWM
wave within the small time period t, the two waveforms are matching. Thus the PWM
waveform may be considered to be the superposition of the desired output waveform and ripple
voltages of time period t. The ripple voltage waveform in each t time interval may not be
identical and hence ripple voltage may consist of a band of harmonics of high frequency. In the
frequency axis the high frequency harmonic voltages are far away from the desired voltage of
fundamental frequency f1 and hence suitable low pass filter circuits may be used to block the
unwanted harmonic currents without affecting the magnitude of the fundamental frequency
current. Further details of these techniques may be found in later lessons.
P
+
_
Edc
+
_
+
_
0.5Edc
LOAD
0.5Edc
SU
IL
A
SL
N
Fig. 36.2: 1-phase half bridge VSI for CCPWM control
Another popular PWM technique is current controlled PWM (CCPWM) technique. Here the
instantaneous magnitude of load current is directly controlled, within some tolerable error band,
to match the desired current shape. This technique is described below for a single-phase half
bridge inverter shown in Fig.36.2. The positive sense for the load current (IL) is taken along the
direction of arrow in Fig. 36.2. The actual load current is sensed with the help of a current sensor
and compared with its reference magnitude. The error in load current can be controlled, as
described below, by proper switching of the inverter switches. The load could be a R-L load or a
R-L-E load. In case of R-L-E load, it is assumed that the back emf (E) of the load has a peak
magnitude lower than the magnitude of instantaneous pole voltage (0.5Edc). To increase the
actual current along the direction of arrow (or to reduce the current flowing in a direction
opposite to the arrow) upper switch SU needs to be turned on, whereas turning on of lower
switch SL will produce the reverse effect. This can be verified simply by writing and analyzing
the loop voltage equation.
36.5 Two-Level Versus Three-Level PWM Inverters

As described in section 36.3, the three-phase bridge inverter consisting of six switches (shown in
Lesson-35) can output pole voltages of only two levels +0.5Edc and -0.5Edc. In contrast to a twolevel inverter, a three-level inverter is capable of producing three different pole-voltage levels,
namely, +0.5Edc, zero and -0.5Edc. The circuit details of three-level inverter will not be discussed
in this course but it can easily be shown that the three-level inverter will have better harmonic
spectrum in comparison to the two-level inverter. As described by Eqn. (36.8) in section 36.3,
any reduction in the fundamental output voltage magnitude of a two level inverter results in
increased rms magnitude of unwanted ripple in the output waveform. Now, let Eqn. (36.8) be
considered in relation to a three-level inverter. Since the pole voltage can now have zero level
too, the rms magnitude of the pole voltage can be brought below 0.5Edc. For lower magnitude of
fundamental pole-voltage, as given by Eqn. (36.9), suitable intervals of zero voltage level may be
introduced such that with lowering of fundamental voltage the rms of the overall pole voltage
also reduces. Thus the rms of the ripple voltage, in case of three-level inverter, can be made
lower than that of the two-level inverter.
P idc
Sw1
Edc
+ Cdc
_
A
LOAD
Sw3
Sw2
Sw4
N
Fig. 36.3: A 1-phase full-bridge VSI
The three-level versus two-level comparison can be applicable to a single-phase PWM inverter
too. Consider the single-phase full bridge circuit shown in Fig.36.3. For this circuit if all the time
one of the two diagonal pair of switches, (Sw1 and Sw4) or (Sw2 and Sw3), conduct the load
voltage will have two levels; +E or E. By suitably switching between one diagonal pair to
another diagonal pair one can obtain a PWM waveform similar to the pole voltage waveform of a
three-phase PWM inverter (only change is in the voltage magnitude). Now if the allowed
switching combination includes conduction of Sw1 along with Sw3 (or Sw2 along with Sw4) the
load voltage may have three-levels, i.e., +E, zero and E. As with a three-phase inverter, the
single phase PWM inverter too will have lower voltage distortion in case of three-level load
voltage (than the corresponding distortion in two level output).
36.6 Considerations On Switch Voltage And Current Ratings

As in square wave inverter the switches of PWM inverter must also be rated for the maximum dc
link voltage. There will, however, be a significant difference in the switch current ratings of the
square wave and PWM inverter for comparable magnitudes of inverters output current. This is
due to the increased switching losses in the PWM inverter. Since the switches in PWM inverter
operate at much higher frequencies than in square wave inverter, the switching losses in the
former are comparable to the conduction losses. This calls for suitable de-rating of the switch
current rating. For medium power rated inverters mostly IGBT switches (with fast acting antiparallel diodes) are used. Generally molded blocks of six switches and six diodes, connected in
bridge fashion with their power and control terminals brought out, are commercially available.
These molded blocks come with isolated metallic case that need to be mounted on suitably sized
heat sinks for dissipation of thermal losses in the switch. The switch manufacturers provide the
turn-on and turn-off loss data for the switches for different magnitudes of dc link voltage, switch
current and gate-to-emitter voltages. Similarly conduction loss data for the switches and the
diodes are also provided. The thermal resistance data (thermal resistance between case and
semiconductor-junction) for the switches and diodes are also provided. The heat-sink
manufacturers provide data / guide lines for calculating the thermal resistance between heat sink
and ambient. The inverter designer needs to do a detailed analysis of the worst-case thermal
losses and temperature rise and need to limit the switch current accordingly. In PWM inverters,
because of large number of switching per output cycle, the load current frequently jumps from
controlled switch (say, IGBT) to diode and hence the diodes of the switches must also be rated to
carry the peak magnitude of load current. It is to be kept in mind that in PWM inverters the load
current polarity changes only according to the output frequency and not according to the
switching frequency. For load power factor close to one, as the PWM inverters output voltage
decreases the diode conduction duration increases. The worst-case diode losses also need to be
determined for deciding on the de-rating factor for diode currents.
Quiz Problems
(1) A PWM inverter is operated from a dc link voltage of 600 volts. The maximum rms line
voltage (fundamental component) will be less than or equal to:
(a) 600 volts
(b) 300 volts
(c) 467 volts
(d) 582 volts
(2) In the harmonic analysis of the pole-voltage waveform (produced by a three-phase PWM
inverter feeding a balanced three-phase load) the 3rd and multiples of 3rd harmonics are
ignored because:
(a) They will not appear in pole voltage
(b) They will not appear in load phase voltage
(c) They will not appear in load phase and line voltage
(d) They will appear in line voltage but not in phase voltage
(3) An IGBT based PWM inverter, with very large number of (nearly) evenly distributed
notches per output cycle, is used to feed a three-phase balanced R-L load with a load
power factor of 0.9. The peak magnitude of diode current and the IGBT current will have
the following relation:
(a) They will be equal
(b) Peak diode current will be less than half of the peak IGBT current
(c) Diode current will nearly be zero
(d) Peak diode current will be less than one third of the peak IGBT current
(4) A PWM inverter is capable of producing the following type of output voltage:
(a) Variable in magnitude and frequency
(b) Variable voltage, fixed frequency
(c) Fixed voltage, variable frequency
(d) Fixed voltage, fixed frequency
Answers to Quiz problems: 1-c, 2-c, 3-a, 4-a
Module
5
DC to AC Converters
Lesson
39
Current Source Inverter
Study of the following:
The circuit for single-phase Current Source Inverter (CSI) using thyristors
Auto-Sequential Commutated mode of operation for 1-ph. Inverter (ASCI), with waveforms
Three-phase Current Source Inverter (CSI) circuit and operation, with waveforms
Introduction
In the previous six (5.1-5.6) lessons in this module, the circuit and operation of single-phase
and three-phase Voltage Source Inverters (VSI), with waveforms, were described in detail. Also,
the presence of harmonics in voltage waveforms, along with its reduction mainly by Pulse Width
Modulation (PWM) techniques, was presented. Presently, mainly self-commutated switching
devices, like say transistors, are used in the above circuits, replacing thyristors, with bulky
commutation circuits needed to turn them OFF, these being force-commutated ones. In the last
two (5.7-5.8) lessons in this module, the circuit and operation of different types of single-phase
and three-phase Current Source Inverters (CSI), with waveforms, will be described in detail. The
device used here is thyristor. In this lesson (5.7), initially, the circuit of single-phase CSI will be
presented. The Auto-Sequential Commutated mode of operation for this Inverter (ASCI), using
thyristors, will be discussed in detail, with waveforms. Then, the circuit and operation of threephase CSI, along with relevant waveforms, will be presented. Finally, the advantages and
disadvantages of CSI over VSI, in brief, are described
For the VSI, as the full form denotes, the output voltage is constant, with the output current
changing with the load type, and/or the values of the components. But in the CSI, the current is
nearly constant. The voltage changes here, as the load is changed. In an Induction motor, the
developed torque changes with the change in the load torque, the speed being constant, with no
acceleration/deceleration. The input current in the motor also changes, with the input voltage
being constant. So, the CSI, where current, but not the voltage, is the main point of interest, is
used to drive such motors, with the load torque changing.
Keywords: Single-phase and Three-phase Current Source Inverter (CSI), ASCI mode of
operation, CSI using thyristors
Single-phase Current Source Inverter

a
Th1
a
D1
L'
+
VS
D4
b
C1 = C/2
+ -
Th2
I
D2
Load (L)
D3
+
I
Th4
C2 = C/2
Th3
b
Fig. 39.1: Single phase current source inverter (CSI) of ASCI type.
The circuit of a Single-phase Current Source Inverter (CSI) is shown in Fig. 39.1. The type
of operation is termed as Auto-Sequential Commutated Inverter (ASCI). A constant current
source is assumed here, which may be realized by using an inductance of suitable value, which
must be high, in series with the current limited dc voltage source. The thyristor pairs, Th1 & Th3,
and Th2 & Th4, are alternatively turned ON to obtain a nearly square wave current waveform.
Two commutating capacitors C1 in the upper half, and C2 in the lower half, are used. Four
diodes, D1D4 are connected in series with each thyristor to prevent the commutating capacitors
from discharging into the load. The output frequency of the inverter is controlled in the usual
way, i.e., by varying the half time period, (T/2), at which the thyristors in pair are triggered by
pulses being fed to the respective gates by the control circuit, to turn them ON, as can be
observed from the waveforms (Fig. 39.2). The inductance (L) is taken as the load in this case, the
reason(s) for which need not be stated, being well known. The operation is explained by two
modes.
ig1,
ig3
0
ig2,
ig4
0
T/2
T/2
VCo
vC
0
t
T/2
T/2
-VCo
t2
t1
I
i0
0
-I
i01,
iD
iC1
iD1
iD2
T/2
-I
Th1 & Th3

triggered
Th2 & Th4

triggered
Th1 & Th3

triggered
Fig. 39.2: Voltage and current waveforms

Mode I: The circuit for this mode is shown in Fig. 39.3. The following are the assumptions.
Starting from the instant, t = 0 , the thyristor pair, Th2 & Th4, is conducting (ON), and the
current (I) flows through the path, Th2, D2, load (L), D4, Th4, and source, I. The commutating
capacitors are initially charged equally with the polarity as given, i.e., vC1 = vC 2 = VC 0 . This
mans that both capacitors have right hand plate positive and left hand plate negative. If two
capacitors are not charged initially, they have to pre-charged.
a
I
I
Th1
+
e
D1
I
Th2
f
C1=C/2 I
D2
d
L
D4
I
Th4
D3
C2=C/2
Th3
b
Fig. 39.3: Mode I (1 phase CSI)
At time, t = 0, thyristor pair, Th1 & Th3, is triggered by pulses at the gates. The conducting
thyristor pair, Th2 & Th4, is turned OFF by application of reverse capacitor voltages. Now,
thyristor pair, Th1 & Th3, conducts current (I). The current path is through Th1, C1, D2, L, D4,
C2, Th3, and source, I. Both capacitors will now begin charging linearly from ( VC 0 ) by the
constant current, I. The diodes, D2 & D4, remain reverse biased initially. The voltage, v D1 across
D1, when it is forward biased, is obtained by going through the closed path, abcda
as v D1 + Vco (1 /(C / 2) ) I dt = 0 It may be noted the voltage across load inductance, L is zero
(0), as the current, I is constant. So, v D1 = Vco + (2 / C ) I dt
As the capacitor gets charged, the voltage v D1 across D1, increases linearly. At some time,
say t1, the reverse bias across D1 becomes zero (0), the diode, D1.starts conducting. An identical
equation can be formed for diode, D3 also. Actually, both diodes, D1 & D3, start conducting at the
same instant, t1. The time t1 for which the diodes, D1 & D3, remain reverse biased is obtained by
equating, v D1 = Vco + ((2 I t1 ) / C ) = 0 . The time is given by, t1 = (C /(2 I ) ) VC 0 . The
capacitor voltages vC1 = vC 2 = vC , appear as reverse voltage across the thyristors, Th2 & Th4,
when
the
thyristors,
Th1
&
Th3,
are
triggered.
The
value
of
vC
is
vC1 = vC 2 = vC = Vco + (2 / C ) I dt ,
which,
if
computed
at
t = t1 ,
comes
out
as,
vC1 = vC 2 = vC (t1 ) = Vco + ((2 I t1 ) / C ) = Vco + ((2 I ) / C ) (C /(2 I ) ) VC 0 = 0 ,

using the value of t1 obtained earlier. This means that the voltages across C1 & C2, varies linearly
from VC 0 to zero in time, t1. Mode I ends, when t = t1 , and vC = 0 . Note that t1 is the circuit
turn-off time for the thyristors.
a
Th1
iC1
Th2
f
C1=C/2
D1
D2
L
d
i0
D4
D3
C2=C/2
iC2
Th4
Th3
b
Fig. 39.4(a): Mode II (1-phase CSI)
a
I
I
e (g)
ie
i0
c
L
f (h)
d
I
b
Fig. 39.4(b): Equivalent circuit for mode II
Mode II: The circuit for this mode is shown in Fig. 39.4a. Diodes, D2 & D4, are already
conducting, but at t = t1 , diodes, D1 & D3, get forward biased, and start conducting. Thus, at the
end of time t1, all four diodes, D1D4 conduct. As a result, the commutating capacitors now get
connected in parallel with the load (L). For simplicity in analysis, the circuit is redrawn as
Version 2 EE IIT, Kharagpur
shown in Fig. 39.4b, where the equivalent capacitor is C / 2 , as C1 = C 2 = C . The equation for
the current at the node is, I + i0 = iC (= iC1 + iC 2 ) , where, iC1 = iC 2 = iC / 2 The voltage balance
equation is,
di
L 0 = (1 / C ) iC dt = = (1 / C ) ( I + i0 ) dt
dt
d 2 i0 i0
d 2 i0
i
I
I
+
=
+ 0 =
or,
2
2
C
C
(L C)
(L C)
dt
dt
2
d i
or, ( L C ) 20 + i0 = I
dt
The solution of the equation is, i0 = A cos ( 0 t ) + B sin ( 0 t ) + K ,
where, A, B & K are constants, natural frequency,
f 0 = 1 / (2 ) ( L C ) , 0 = (2 ) f 0 = 1 / ( L C ) , and time period,
or, L
T = 1 / f 0 = (2 ) / 0 = (2 ) ( L C ) .
The initial conditions at t = 0 are, i0 = I and d i0 / dt = 0 . It should be noted that the time, t is
measured from the instant, the diodes, D1 & D3, start coducting, i.e., from the instant, mode I is
over. Using the initial conditions stated earlier, the current is, i0 = I (2 cos ( 0 t ) 1) . The
capacitor current is iC = I + i0 = 2 I cos ( 0 t ) .
2 I
1
sin ( 0 t ) .
iC dt =
C
0 C
This expression can also be obtained as,
vC = v L = L (d i0 / dt ) = ((2 I ) ( 0 L) ) sin ( 0 t ) , where, 0 L = 1 /( 0 C ) , as can be
The voltage across capacitor is, vC =
derived using 0 = 1 / ( L C ) . So, the above expressions are same, and can be written as,
vC = (2 I ) ( L / C ) sin ( 0 t ) , substituting the expression for 0 in any of the above

expressions. So, iC1 = iC 2 = I cos ( 0 t ) , and
i D1 = I iC1 = I (cos ( 0 t ) 1) , in the interval 0 < t < t 2 .

As the current, iC1 tends to reverse, diode, D3 prevents its reversal. Similarly, the diode, D4
prevents the reversal of the current, iC 2 . From the initiation of mode II, a time, t2 must elapse for
the current, iC1 to become zero (0). The time, t 2 is,
t 2 = ( / 2) / 0 = ( / 2) ( L C ) = (1 /(4 f 0 ) ) = T / 4 , as ( 0 t 2 ) = ( / 2) , using,
iC1 = I cos ( 0 t 2 ) = 0 . The capacitor voltage at time, t 2 is, vC = ((2 I ) /( 0 C ) ) = VC 0 . Note

that this is also the maximum value. Now, the load current is, i0 = I (2 1) = I . This shows that
the load current has reversed from +I to I during mode II, after time, t2. It is also seen that the
capacitor voltage changes by 2 VC 0 (from VC 0 to VC 0 ) during each commutation interval. The
time t1 , after substituting VC 0 , comes out as,
t1 = (C /(2 I ) VC 0 = (C /(2 I ) ((2 I ) /( 0 C ) ) = 1 / 0 = ( L C ) .
The total commutation interval is, t c = t1 + t 2 = (1 + ( / 2) ) / 0 = (1 + ( / 2) ) ( L C ) .
Version 2 EE IIT, Kharagpur
At the end of the process, constant current flows in the path, Th1, D1, load (L), D3, Th3, and
source, I. This continues till the next commutation process is initiated by the triggering of the
thyristor pair, Th2 & Th4.
The complete commutation process is summarized here. The process (mode I) starts with the
triggering of the thyristor pair, Th1 & Th3. Earlier, the thyristor pair, Th2 & Th4 were conducting.
With the two commutating capacitors charged earlier with the polarity as shown (Fig. 39.3), the
conducting thyristor pair, Th2 & Th4 turns off by the application of reverse voltage. Then, the
voltages across the capacitors decrease to zero at time, t1 (end of mode I), as constant (source)
current, I flows in the opposite direction. Mode II now starts (Fig. 39.4a), as the diodes, D1 & D3,
get forward biased, and start conducting. So, all four diodes D1-D4, conduct, and the load
inductance, L is now connected in parallel with the two commutating capacitors. The current in
the load reverses to the value I, after time, t 2 (end of mode II), and the two capacitors also are
charged to the same voltage in the reverse direction, the magnitude remaining same, as it was
before the start of the process of commutation (t = 0). It may be noted that the constant current, I
flows in the direction as shown, a part of which flows in the two capacitors.
In the above discussion, one form of load, i.e. inductance L only, has been considered. The
procedure remains nearly same, if the load consists of resistance, R only. The procedure in mode
I, is same, but in mode II, the load resistance, R is connected in parallel with the two
commutating capacitors. The direction of the current, I remains same, a part of which flows in
the two capacitors, charging them in the reverse direction, as shown earlier. The derivation,
being simple, is not included here. It is available in books on this subject.
Three-phase Current Source Inverter

X
+
Th1
D1
Th5
Th3
C1
C3
D5
D3
C5
iA
iB
iC
A
B
Vdc
C
D4
D6
C4
C2
Th4
Th6
C6
L
L
R
N
D2
Th2
Fig. 39.5(a): Three-phase current source inverter (CSI)

The circuit of a Three-phase Current Source Inverter (CSI) is shown in Fig. 39.5a. The type
of operation in this case is also same here, i.e. Auto-Sequential Commutated Inverter (ASCI). As
in the circuit of a single-phase CSI, the input is also a constant current source. The output current
(phase) waveforms are shown in Fig. 39.5b. In this circuit, six thyristors, two in each of three
arms, are used, as in a three-phase VSI. Also, six diodes, each one in series with the respective
thyristor, are needed here, as used for single-phase CSI. Six capacitors, three each in two (top
and bottom) halves, are used for commutation. It may be noted that six capacitors are equal, i.e.
C1 = C 2 = " = C6 = C . The diodes are needed in CSI, so as to prevent the capacitors from
discharging into the load. The numbering scheme for the thyristors and diodes are same, as used
in a three-phase VSI, with the thyristors being triggered in sequence as per number assigned
(Fig. 39.5b).
I
180
iA
300
120
360
-I
I
120
IB
300
360
240
60
-I
IC
60
180
240
360
-I
on
off
Th1
Th2
Th3
Th4
Th5
Th6
Th1
Th5
Th6
Th1
Th2
Th3
Th4
Th5
Th1
Th1
Th3
Th3
Th5
Th5
Th1
Th6
Th2
Th2
Th4
Th4
Th6
Th6
60
120
180
240
300
360
Thyristors conducting
Fig. 39.5(b): Phase current waveforms
The commutation process in a three-phase CSI is described in brief. The circuit, when two
thyristors, Th1 & Th2, and the respective diodes, are conducting, is shown in Fig. 39.6a. The
current is flowing in two phases, A & C. The three capacitors in the top half, are charged
previously, or have to pre-charged as shown. But the capacitors in the bottom half are not shown.
I
L
Th1
Th3
C1
Th5
C3
+
I
-
D1
C5
D5
D3
I (iA)
A
B
C
I (iC)
D2
I
Th2
Fig. 39.6(a): Three-phase CSI with two thyristors, Th1 & Th2 conducting
Mode I: The commutation process starts, when the thyristor, Th3 in the top half, is triggered, i.e.
pulse is fed at its gate. Immediately after this, the conducting thyristor, Th1 turns off by the
application of reverse voltage of the equivalent capacitor. Mode I (Fig. 39.6b) now starts. As the
diode D1 is still conducting, the current path is via Th3, the equivalent capacitor, D1, and the load
in phase A (only in the top half). The other part, i.e. the bottom half and the source, is not
considered here, as the path there remains same. The current, I from the source now flows in the
reverse direction, thus the voltage in the capacitor, C1 (and also the other two) decreases. It may
be noted the equivalent capacitor is the parallel combination of the capacitor, C1 and the other
part, being the series combination of the capacitors, C3 & C5 ( C = C / 2 ). It may be shown the its
value is C eq = C / 3 , parallel combination of C & C / 2 , as C1 = C3 = C5 = C . Also, the current
in the capacitor, C1 is ( 2 / 3) I , and the current in other two capacitors, C3 & C5 is I / 3 . When
the voltage across the capacitor, C1 (and also the other two) decreases to zero, the mode I ends.
L
Th1
2I/3 C1
+
-
Th3
Th5
C3
-
I/3
+
I
+
D1
C5
D3
D5
I/3
I (iA)
A
B
C
I (iC)
D2
I
Th2
Fig. 39.6(b): Mode I (3-phase CSI)

Mode II: After the end of mode I, the voltage across the diode, D3 goes positive, as the voltage
across the equivalent capacitor goes negative, assuming that initially (start of mode I) the voltage
was positive. It may be noted that the current through the equivalent capacitor continues to flow
in the same direction. Mode II (Fig. 39.6c) starts. Earlier, the diode, D1 was conducting. The
diode, D3 now starts conducting, with the voltage across it being positive as given earlier. A
circulating current path now exists between the equivalent capacitor, two conducting diodes, D1
& D3 and the load (assumed to be inductive R & L, per phase) of the two phases, A & B, the
two loads and also the two diodes being now connected in series across the equivalent capacitor.
The current in this path is oscillatory, and goes to zero after some time, when the mode II ends.
The diode, D1 turns off, as the current goes to zero. So, at the end of mode II, the thyristor, Th3 &
the diode, D3 conduct. This process has been described in detail in the earlier section on singlephase CSI (see mode II). It may be noted that the polarity of the voltage across the equivalent
capacitor (at the end of mode II) has reversed from the initial voltage (at the beginning of mode
I). This is needed to turn off the outgoing (conducting) thyristor, Th3, when the incoming
thyristor, Th5 is triggered. The complete commutation process as described will be repeated. The
diodes in the circuit prevent the voltage across the capacitors discharging through the load.
+
L
I
Th1
-
C3
C1
D1
Th5
Th3
+
C5
D5
D3
iA
A
B
C
I (iC)
iB
D2
I
Th2
Y
Fig. 39.6(c): Mode II (3-phase CSI)
The circuit is shown in Fig. 39.6d, with two thyristors, Th3 & Th2, and the respective diodes
conducting. The current now flows in two phases, B & C, at the end of the commutation process,
instead of phase A at the beginning (Fig. 39.6a). It may be noted the current in the bottom half
(phase C) continues to flow, and also the thyristor, Th2 & the diode, D2 remain in conduction
mode. This, in brief, is the commutation process, when the thyristor, Th3 is triggered and the
current is transferred to the thyristor, Th3 & the diode, D3 (phase B), from the thyristor, Th1 & the
diode, D1 (phase A).
I
+
L
I
Th1
Th3
-
C1
Th5
-
C3
D1
+
C5
I
D3
D5
I (iB)
B
C
I (iC)
C
D2
I
Th2
Fig. 39.6(d): Three-phase CSI with two thyristors, Th3 & Th2 conducting
Comments
In the introductory remarks, one merit of CSI has been stated, i.e. it can be used for the speed
control of ac, specially induction, motors subject to variation in load torque. In recent years,
self-commutated power switching devices, such as power transistors etc., are being used in VSI,
but not costly inverter-grade thyristors (having low turn-off time), along with bulky commutation
circuits. These circuits also need additional diodes for feeding the reactive power back to the
supply, when used with heavily inductive loads. The advantages and disadvantages of CSI vis-vis VSI are given.
Advantages
1. The circuit for CSI, using only converter grade thyristor, which should have reverse blocking
capability, and also able to withstand high voltage spikes during commutation, is simple.
2. An output short circuit or simultaneous conduction in an inverter arm is controlled by the
controlled current source used here, i.e., a current limited voltage source in series with a
large inductance.
3. The converter-inverter combined configuration has inherent four-quadrant operation
capability without any extra power component.
Disadvantages
1. A minimum load at the output is required, and the commutation capability is dependant upon
load current. This limits the operating frequency, and also puts a limitation on its use for UPS
systems.
2. At light loads, and high frequency, these inverters have sluggish performance and stability
problems.
In this lesson the seventh one of this module, the current source inverter (CSI) vis--vis
VSI, is introduced. The commutation process for Auto-Sequential Commutated Inverter (ASCI)
mode of operation in single-phase CSI, is mainly described, along with circuit diagram and
relevant waveforms, in detail. Then, the commutation process for the same mode of operation,
i.e. ASCI, in three-phase CSI, is described, along with various circuit diagrams, in brief. Finally,
the advantages and disadvantages of CSI over VSI, are presented. In the next lesson, eighth and
last one, of this module, the load-commutated CSI, and also the Pulse Width Modulation (PWM)
techniques used in CSI, will be discussed.
Module
5
DC to AC Converters
Lesson
40
Load-commutated
Current Source Inverter
(CSI)
Study of the circuit and operation for Load-commutated Current Source Inverter (CSI)
Introduction
In the last lesson (5.7) seventh one in this module, the circuit and operation of single-phase
and three-phase Current Source Inverters (CSI), with relevant waveforms, have been described in
detail. The device used is thyristor. The type is the Auto-Sequential Commutated Inverter
(ASCI). In this lesson (5.8) eighth and final one in this module, the circuit and operation of
load-commuted CSI, including waveforms, will be presented in detail.
Keywords: Load-commutated current source inverter (CSI)
Load-Commutated CSI
In the last lesson, ASCI mode of operation for a single-phase Current Source Inverter (CSI)
was presented. Two commutating capacitors, along with four diodes, are used in the above
circuit for commutation from one pair of thyristors to the second pair. Earlier, also in VSI, if the
load is capacitive, it was shown that forced commutation may not be needed. The operation of a
single-phase CSI with capacitive load (Fig. 40.1) is discussed here. It may be noted that the
capacitor, C is assumed to be in parallel with resistive load (R). The capacitor, C is used for
storing the charge, or voltage, to be used to force-commutate the conducting thyristor pair as will
be shown. As was the case in the last lesson, a constant current source, or a voltage source with
large inductance, is used as the input to the circuit.
+ a
i
Th1
Th2
i
iC
C
+ -
Vin
v0
= vC
Load (R)
Th4
Th3
Fig. 40.1: Load-commuted CSI

The power switching devices used here is the same, i.e. four thyristors only in a full- bridge
configuration. The positive direction for load current and voltage, is shown in Fig. 40.1. Before t
= 0, the capacitor voltage is vC = V1 , i.e. the capacitor has left plate negative and right plate
positive. At that time, the thyristor pair, Th2 & Th4 was conducting. When (at t = 0), the thyristor
pair, Th1 & Th3 is triggered by the pulses fed at the gates, the conducting thyristor pair, Th2 &
Th4 is reverse biased by the capacitor voltage vC = V1 , and turns off immediately. The current
path is through Th1, load (parallel combination of R & C), Th3, and the source. The current in the
thyristors is iTh1 = iTh3 = I , the output current is iac = I ; the capacitor voltage, vC changes from
V1 to V1 , as the capacitor gets charged by the current iC during the time, (T / 2) > t > 0 . The
load voltage is v0 = vC . Thus, the waveform of the current, i0 = (v0 / R) = (vC / R) through load
resistance, R has the same nature as that of vC (Fig. 40.2). Similarly, when (at t = T / 2 ), the
thyristor pair, Th2 & Th4 is triggered by the pulses fed at the gates, the conducting thyristor pair,
Th1 & Th3 is reverse biased by the capacitor voltage vC = V1 , and turns off immediately. The
current path is through Th2, load (parallel combination of R & C), Th4, and the source. The
current in the thyristors is iTh 2 = iTh 4 = I , but the output current is iac = I ; the capacitor
voltage, vC changes from V1 to V1 , as the capacitor gets charged by the current iC during the
time, T > t > (T / 2) .
ig1,
ig3
0
T/2
T/2
ig2,
ig4
0
v0,
i0
I1,
V1
iTh1, I
iTh3
0
iTh2,
iTh4
T/2
0
T/2
T/2
-I1,
-V1,
I+I1
I
iac
I-I1
iC 0
T/2
-(I-I1)
T/2
-I
Th1, Th3
Th2, Th4
-(I+I1)
Th1, Th3
triggered
V1
vin
T/2
Th2, Th4
triggered
Th1, Th3
triggered
-V1
V1
vTh1,
vTh3
0
T/2
-V1
Fig. 40.2: Voltage and current waveforms.
Various current and voltage waveforms during one cycle T > t > 0 , are shown in Fig. 40.2.
At t = 0, the capacitor voltage is vC = V1 , then v0 = vC = V1 , and the load current through R is
i0 = (V1 / R) = I1 . As stated earlier, during the time (T / 2) > t > 0 , the capacitor gets charged,
with its voltage changing from V1 to V1 .
So, At t = T / 2 , the load current is
i0 = (vC / R) = (v0 / R) = (V1 / R) = I1 . The input voltage is vin = v0 , during (T / 2) > t > 0 , and
vin = v0 , during T > t > (T / 2) .

It may be observed that, when the thyristor pair, Th1 & Th3 is conducting for (T / 2) > t > 0 ,
the currents iC , i0 are leaving node A (Fig. 40.1), and the current, I is entering node A.
Therefore, the equivalent circuit for (T / 2) > t > 0 , is shown in Fig. 40.3a. The current in node
A, is iC + i0 = I or, iC = I i0 . At t = 0, i0 = I 1 , and iC = I + I 1 . The mathematical steps for a
steady solution of the output current, and other parameters, such as input voltage etc., are given
later. Just after (T/2), when the thyristor pair, Th2 & Th4 is conducting, the currents iC , i0 are
entering node B (Fig. 40.1), and so also the current, I. The equivalent circuit for T > t > (T / 2) ,
is shown in Fig. 40.3b. The current in node B is iC + i0 + I = 0 or, iC = ( I + i0 ) . At t = (T/2),
i0 = I 1 , and iC = ( I + I1 ) . The cycle repeats itself.
I
i0
c (a)
iC
c (a)
iC
i0
I
R
v0 = vC
V1
v0 = vC
C
C
+
d (b)
V1
d (b)
(b)
(a)
Fig. 40.3: (a) Equivalent circuit for 0 < t < T/2

(b) Equivalent circuit for T/2 < t < T
The steps to be followed to find the expression of the output current, and other parameters
are described. The voltage balance equation for the equivalent circuit (Fig. 40.3a) is,
R i0 (1 / C ) ( I i0 ) dt + v1 = 0
d i0 i0
I
+ =
dt C C
Solving it, with the initial condition for i0 as given earlier,
Differentiating it, we get R
i0 = I 1 e t /( RC ) I 1 e t /( RC )
To arrive at a steady solution only, the following steps are followed. At t = (T/2), the current is
i0 = I 1 , as shown later. So, I1 = I 1 e T /( 2RC ) I1 e T /( 2RC )
1 e T /( 2RC )
or, I1 = I
= I , if (T /( 2 R C ) ) >> 1 or, T >> ( R C )
T /( 2RC )
1 + e
So, using the above expression, the output current, or the current in resistance, R comes out as,
2 (e t /( RC ) )
i0 = I 1
T /( 2 R C )
1+ e
The output voltage v0 , or the capacitor voltage vC is,
2 e t /( RC )
v 0 = vC = i0 R = ( R I ) 1
T /( 2 RC )
1+ e
The turn-off time provided by the circuit for each thyristor is obtained from the condition that,
when t = tOFF , v0 = vC = i0 R = 0 . So,
2 e tOFF /( RC )
v0 = vC = i0 R = ( R I ) 1
1 + e T /(2RC )
or, e tOFF /( RC ) = (1 + e T /(2RC ) ) / 2
) = 0
= ( R C ) log e (1 + eT /(2RC ) ) / 2
or, tOFF = ( R C ) log e
T /(2 RC )
1+ e
The average value of the input voltage, Vin is,
2 e t /( RC )
1
0 1 + e T /( 2RC ) dt
4 R C 1 e T /( 2RC )
or, Vin = ( I R ) 1

T /( 2 RC )
T
1
e
+
When the input power ( Vin I ) is positive, power is delivered to the load.
1
Vin =
T /2
2I R
0 (i0 R) dt = T
T /2
T /2
The following points may be noted.

1. It may be observed from the equation given earlier that, as the inverter frequency ( f = 1 / T )
is increased, the turn-off time provided by the circuit decreases. But, the circuit commutation
time, t off , should be more than the turn-off time of the thyristor, t q , for reliable operation.
This means that there is an upper limit to the inverter frequency, beyond which the thyristors
in the inverter circuit will fail to commutate.
2. When the inverter frequency ( f = 1 / T ) is low, or time period, T is high, the graph of i0 (t )
or v0 (t ) as given in Fig. 40.2, becomes flatter as shown by dotted line in Fig. 40.4. As this
graph is nearer to a square wave, it can be inferred that, for low inverter frequencies, the
inverter has square wave output for load current or load voltage ( i0 / v0 ).
When the inverter frequency ( f = 1 / T ) is high, or time period, T is low, the waveform
of v0 or i0 is shown by full line in Fig. 40.4. As this graph is closer to a sine wave, it can be
noted that, for higher frequency, the CSI has sinusoidal wave shape for load (output) current
or voltage.
v0, i0
Small T
Large T
T
T/2
Fig. 40.4: Waveforms for CSI with resistive (R) load
(a) Square wave output: It has been found that, for obtaining square wave of the load current,
T /( 2 R C ) > 5.0 . If t q is the turn-off time for the thyristors used in CSI, then form the
equation given earlier,
t q = ( R C ) log e 2 /(1 + e 5 ) ( R C ) log e 2 = 0.69 ( R C )
or, C = t q /(0.69 R)
For T /( 2 R C ) = 5.0 or T = 10 R C , the maximum frequency is,
f max = 1 / T = 1 /(10 R C )
Substituting the value of C obtained earlier, f max = 0.069 / t q
(b) Sinusoidal wave output: For obtaining sinusoidal wave of the load current, the capacitive
reactance, X C at three times the minimum frequency, f min , should be lower than R / 2 , i.e.,
1
R
,
at 3 f min , X C =
2 3 f min C 2
or C 0.106 /( R f min)
The inverter should therefore be operated at frequencies higher than f min in order to obtain
the sinusoidal wave shape.
In this lesson (5.8) eighth and final one in this (last) module (5), the circuit and operation,
of load-commuted CSI, including waveforms, are discussed in detail. In this module (5), mainly
two types of dc-ac converters, termed as inverters Voltage Source (VSI) and Current Source
(CSI), have been presented. Both single-phase and three-phase inverters have been described,
with relevant waveforms. Starting with the use of Pulse Width Modulation (PWM) techniques,
used for voltage control in VSI, other variations, such as Sine PWM, have been taken up.
Incidentally, this is the last lesson for the course on Power Electronics.

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1) Transistors:

If both the junction

Configurrations: M- Bipolar juncction transisttors

These currrent and voltage

Where q is he charge on electron, V is the

To a close approximation the small chan

Where q is he charge on electron, V is the

To a close approximation the small chan

The outputt voltage is give

The emitter dc current I E is given by

Therefore, emitter ac resistance =

and, Vout = 1.5 x 56.6 = 84

The emitter ac current is given

Therefore, voltage gain of the amplifier =

Vout = 1.5 x 8.71 =13.1 mV

Common Emitter Curv

collector is shorted with emitter

If we requirre, VBE = - 0.1 V

Since, ICO = ICBO

Cut off of a transistor mea

point. The Cb capacitor lo

d which allow IB to vary so as to keep IC relattively constant with variationss

Differentiatting with respec

RE cannot be made large enough to swa

Collector Feedback Bias:

Circuit is sttiff sensitive to changes in dcc. The advantag

Circuit is sttill sensitive to changes in dcc. The advantag

Rb is the efffective resistan

If VBE is considered to be independent of

large capacitance (> 10 F) so that its reactance at th

Lecture - 17: Biasing Tec

used with = 180, RE = 100W and RC = Rload = 1K W . Also determ

Since the Q-point

The powerr drawn from the dc source is given by

The powerr loss in the tran

Biasing a pnp Transisttor:

In order forr a transistor to

Normally VBE is taken 0.7

In the output circuit, the lo

Field efffect transisto

Constructional Features, operating principle and characteristics of Power Metal Oxide

Differentiate between the conduction mechanism of a MOSFET and a BJT.

Explain the salient constructional features of a MOSFET.

Draw the switching characteristics of a MOSFET and explain it.

Design the gate drive circuit of a MOSFET.

Interpret the manufacturers data sheet rating of a MOSFET.

Version 2 EE IIT, Kharagpur 3

Version 2 EE IIT, Kharagpur 4

Constructional Features of a Power MOSFET

Fig. 6.3: Parasitic BJT in a MOSFET cell.

6.3 Operating principle of a MOSFET

VGS2 > VGS1

Version 2 EE IIT, Kharagpur 8

VGS3 > VGS2 > VGS1

Version 2 EE IIT, Kharagpur 9

Exercise 6.1 (after section 6.3)

Fill in the blank(s) with the appropriate word(s)

A MOSFET is a ________________ controlled ________________ carrier device.

Enhancement type MOSFETs are normally ________________devices while depletion

The MOSFET cell embeds a parasitic ________________ in its structure.

The gate-source voltage at which the ________________ layer in a MOSFET is formed

6.4 Steady state output i-v characteristics of a MOSFET

Version 2 EE IIT, Kharagpur 10

VGS VGS (th) = VDS

A MOSFET is a controlled carrier device.