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A0601-Digital System Design1
A0601-Digital System Design1
Tech I Semester Supplementary Examinations September 2009 DIGITAL SYSTEM DESIGN (Common To Digital Systems & Computer Electronics, Digital Electronics& Communication Systems, VLSI System Design ) Time : 3hours Max.Marks:60 Answer any FIVE questions All questions carry equal marks --1.a) Draw an ASM chart to design a control logic of a binary multiplier. Realize the same using MUX, decoder and D-type flip flops. b) Obtain the Reduced dimension maps for the following for variable maps and also generate the minimized expression. CD AB 00 01 11 10 00 1 1 01 1 X 11 1 1 X 10 1 Reduce variable D. 2. CD AB 00 00 1 01 11 10 1
01 11 10 1 X X 1 1 1 X 1
Reduce variable B.
The typical cell in an interactive network has one binary input xi and one binary out put Zi. The output Zi=1 if and only if xi x i-2. for the first two cells (i.e; i =1,2) assume X-1= X0 = 0. Write a cell table in standard form. Make a gray code state assignment and write the output and carry functions. For the circuit shown below find tests to detect the faults h SAO and hSA1, K SAO and K SA1. Find tests to distinguish between the above faults.
3.a)
b)
Derive
Cont2
::2::
Apply D-algorithm to detect h SAO fault in the given circuit and derive the test vectors.
b)
Apply signature analysis to the above circuit and generate the signatures using 4 bit LFSR with a feed back from 3rd flip flop.
5.a)
b)
It is necessary to synchronize the machine of table shown below to a state A with a minimum number of input symbols. Devise such a procedure which may be adaptive NS,2 PS X= 0 X=1 A C,1 E,1 B A,0 D,1 C E,0 D,1 D F,1 A,1 E B,1 F,0 F B,1 C,1 Determine whether a distinguishing sequences exist for the given machine below NS,2 PS X= 0 X=1 A C,1 A,0 B D,0 D,0 C A,0 D,0 D B,0 C,0 Apply PLA maximization procedure and obtain the minimized expression to be implemented on PLA. F = 2021+0022+1200 Obtain the minimum test vector set for the above function f in 6(a) Explain the COMPACT algorithm and apply it to the following PLA whose column set and SSR is given as follows. Column A B C D E F G SSR 12 1,3,6 2,3,7,8,10 1,2,5,6,9,11 2,4,6,8,10,12 1,2,4,7,11 4,5,6,7,12
6.a) b) 7.