Lab 3: CMOS NOR Gate:

Circuit Design and Layout

Developed by: Basawaraj
Last Modified Apr., 2011

Requirements:
Before starting this lab you should have successfully completed lab 1 and 2.

INTRODUCTION:
NAND and NOR are the two basic gates. Since all other logic gates can be designed using either one of
them, they are also referred to as Universal Gates. In the first two labs we designed both the circuit
and the layout of the CMOS NAND gate. In this lab we will design a CMOS NOR gate. Like the
NAND gate the NOR gate also has 2 PMOS and 2 NMOS transistors. They only differ in their
placement, in case of the NAND gates the PMOS were in parallel and the NMOS were in series where
as in case of the NOR gates the PMOS are in series and the NMOS in parallel.
In the first part of this lab you will design a CMOS NOR gate using XCircuit and do a digital
simulation using IRSIM. In the second part of this lab you will layout the CMOS NOR gate using
Magic, generate the .sim file and simulate using IRSIM.
1. CMOS NOR gate using XCircuit
2. CMOS NOR gate using Magic

NOR Circuit:
Design a CMOS NOR gate using XCircuit, circuit diagram shown in figure 1 below.

Figure 1: Circuit of CMOS NOR gate

Refer to the steps followed in lab 1, when you designed a CMOS NAND gate. First design the NOR
gate, with the two PMOS devices in series in the pull up part of the circuit and the two NMOS devices
in parallel in the pull down section. Connect the vdd, gnd, input and output ports. Label the input and
output ports and create a symbol for the NOR gate.
Save the circuit, create a .sim file and simulate it using IRSIM.

NOR Layout:
Now layout the CMOS NOR gate following the steps from lab 2. The layout is shown in figure 2
below.

Figure 2: Layout of CMOS NOR gate

Note that the NOR gate layout is similar to the NAND gate layout, with the following two differences.
1. The PMOS devices / transistors are in series in case of the NOR gate where as they were
in parallel in the NAND gate; and
2. The NMOS devices are in parallel in the NOR gate, while they were in series in the
NAND gate.
Layout PMOS and NMOS devices, make input and out ports and label the ports and the power lines
(Vdd and GND). Save the layout, extract the layout into a .ext file and convert it into a .sim file for use
with IRSIM.
Simulate this .sim file using IRSIM and make sure that the layout behaves exactly as required, i.e. it is
the layout for the NOR gate.