You are on page 1of 42

A

Compal Confidential

ICW50 Schematics Document


AMD Turion/Sempron + Nvidia MCP67-MV
2007 / 04 / 20

Rev:1.0

FOR Pre-MP

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Issued Date

Deciphered Date

2007/8/18

Cover Sheet

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P

Friday, April 20, 2007

Sheet
E

of

42

Compal confidential
Project Code: ICW50
File Name : LA-3581P

Thermal Sensor
ADM1032ARM

DDRII

AMD Turion/Sempron CPU


Socket S1 638P

DDRII-SO-DIMM X2
page 08,09

page 4,5,6,7

page 6

533/667/800

Dual Channel

HT LINK

200-800MHz

DVI-D Conn.

LCD Conn.

page 20

CRT & TV-out

page 20

page 19

LVDS
DVI

USB conn x4

Nvidia
MCP67-MV

page 25,26

836 BGA

LVDS

MXM II VGA/B

HD Audio

3.3V 24.576MHz/48Mhz

IDE BUS

3.3V ATA-100

PCI-Express

CDROM
Conn.
page 21

port 1

PCI BUS
MINI Card x2

PHY(GbE)

WLAN, TV-Tuner

RTL8211B

IDSEL:AD20
(PIRQE#,
GNT#0,
REQ#0)

page 22

29

20

SATA BUS

page 18

New Card
Socket

CMOS
Camera
page

USB 2.0 BUS

PCI-Express

Bluetooth
Conn page

S-ATA HDD
Conn. page 21

3.3V 33 MHz

HDA Codec
ALC268

page 31

Audio AMP

page 10,11,12,13,14,15,16,17

page 32

Card Reader
RICOH R5C833

Phone Jack x3

LPC BUS

page 23

RJ45

MDC 1.5
Conn
page 29

page 32

page 22

1394
Conn.

page 23

6 in 1
socket

ENE KB926

page 24

page 27,28

Power On/Off CKT / LID switch / Power OK CKT


page 30

Int.KBD

Touch Pad

page 29

DC/DC Interface CKT.


page 33

CIR/LED
page 29

page 29

RTC CKT.
page 16

EC I/O Buffer

BIOS

page 29

Power Circuit DC/DC

page 29

page 35~41

CIR
page 30
A

Compal Secret Data

Security Classification

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

BLOCK DIAGRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

of

42

SIGNAL

STATE

Voltage Rails

+VALW

+V

+VS

Clock

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

ON

OFF

OFF

OFF

Power Plane

Description

S1

S3

S5

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+0.9V

0.9V switched power rail for DDR terminator

ON

ON

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.2VALW

1.2V always on power rail

ON

ON

ON*

+1.2VS

1.2V switched power rail

ON

OFF

OFF

+1.2V_HT

1.2V switched power rail

ON

OFF

OFF

+1.8V

1.8V power rail for DDR

ON

ON

OFF

Vcc
Ra/Rc/Re

+1.8VS

1.8V switched power rail

ON

OFF

OFF

Board ID

+2.5VS

2.5V switched power rail

ON

OFF

OFF

0
1
2
3
4
5
6
7

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Board ID / SKU ID Table for AD channel

Board ID
0
1
2
3
4
5
6
7

External PCI Devices


IDSEL#

1394

AD20

REQ#/GNT#
0

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

Interrupts
PIRQE

Device

Address

Smart Battery

0001 011X b

EC SM Bus2 address
Device
ADM1032

PCB Revision
UMA (0V)
DISCRETE (3.3V)

SKU ID Table
SKU ID
0
1
2
3
4
5
6
7

Address
1001 100X b

MCP67 SM Bus address


Device

Address

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 001Xb

BTO Option Table

EC SM Bus1 address

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BOARD ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Device

SLP_S1# SLP_S3# SLP_S5#


HIGH

Full ON

VIN

+3VALW/+3V/+3VAUX

SKU
B - PHASE
C - PHASE

BTO Item
BOM Structure
DIP CAP & RTC
45@
UMA
UMA@
VGA
VGA@
UMA & TV-OUT
UMA&TV@
2 SATA HDD
SATA2@
CAMERA
CMOS@
BLUETOOTH
BT@
MINI CARD 1(TV)
MINI1@
MINI CARD 2(WLAN)
MINI2@
NEW CARD
EXPRESS@
TV-OUT
TV@
DVI
DVI@
1394
1394@
CARD READER
5IN1@
HT Debug Port
HT@

Compal Secret Data

Security Classification

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

TABLE OF CONTENTS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

of

42

PROCESSOR HYPERTRANSPORT INTERFACE


VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

FAN Conn

+1.2V_HT
JP22A

+1.2V_HT

(10)
(10)
(10)
(10)

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

J5
K5
J3
J2

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

Y4
Y3
Y1
W1

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

1
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)

W=40mils

2 51_0402_1%
2 51_0402_1%
(10) H_CTLIP0
(10) H_CTLIN0

H_CTLIP1
H_CTLIN1

P3
P4

H_CTLIP0
H_CTLIN0

N1
P1

L0_CTLOUT_H1
L0_CTLOUT_L1

T5
R5

L0_CTLIN_H0
L0_CTLOUT_H0
L0_CTLIN_L0
L0_CTLOUT_L0
FOX_PZ63823-284S-41F

R2
R3

L0_CTLIN_H1
L0_CTLIN_L1

H_CTLOP0
H_CTLON0

+VCC_FAN1
FAN1

+3VS

R88
10K_0402_5%

1
C510

2
10U_0805_10V4Z

1
C509

2
1000P_0402_50V7K

D21
BAS16_SOT23-3

Update Footprint

JP16
1
2
3

(27,28) FAN_SPEED1

ACES_85205-03001

1
C52
1000P_0402_50V7K

U11
+5VS
+VCC_FAN1
(27,28) EN_DFAN1

(10)
(10)
(10)
(10)

1
2
3
4

EN_DFAN1
1

2
R1431
R1421

D20
1SS355_SOD323-2

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2

+5VS

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0

2 C533
4.7U_0805_10V4Z

AE5
AE4
AE3
AE2

HTT Interface

(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)

D4
D3
D2
D1

VEN
VIN
VO
VSET

GND
GND
GND
GND

8
7
6
5

G993P1UF_SOP8
C310
10U_0805_10V4Z

FAN1 Conn

H_CTLOP0 (10)
H_CTLON0 (10)

Athlon 64 S1
Processor Socket

+1.2V_HT

2
C542
4.7U_0805_10V4Z

C541
4.7U_0805_10V4Z

C536
0.22U_0402_10V4Z

C539
180P_0402_50V8J

2
C540
0.22U_0402_10V4Z

2
2
C538
180P_0402_50V8J

LAYOUT: Place bypass cap on topside of board


NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS

Compal Secret Data

Security Classification

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

AMD CPU HT I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

of

42

Processor DDR2 Memory Interface


JP22C

+1.8V
+0.9VREF_CPU
4

+0.9V

JP22B

10:8:10:8:10

R388
39.2_0402_1%~D

PLACE THEM CLOSE TO


CPU WITHIN 1"

Y10
AE10
AF10

(8)
(8)
(8)
(8)

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

(9)
(9)
(9)
(9)

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

(9) DDR_CKE1_DIMMB
(9) DDR_CKE0_DIMMB
(8) DDR_CKE1_DIMMA
(8) DDR_CKE0_DIMMA
(8) DDR_A_MA[15..0]

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

Y26
J24
W24
U23

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

H26
J23
J20
J21

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

K22
R20
T22

MA_BANK2
MA_BANK1
MA_BANK0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

T20
U20
U21

(8) DDR_A_RAS#
(8) DDR_A_CAS#
(8) DDR_A_WE#

Y16
AA16
E16
F16

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

AF18 DDR_B_CLK2
AF17 DDR_B_CLK#2
A17 DDR_B_CLK1
A18 DDR_B_CLK#1

M_ZN
M_ZP

V19
J22
V22
T19

(8) DDR_A_BS#2
(8) DDR_A_BS#1
(8) DDR_A_BS#0

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

VTT_SENSE

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

MA_RAS_L
MA_CAS_L
MA_WE_L
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor
Socket

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

(8)
(8)
(8)
(8)

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

(9)
(9)
(9)
(9)

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

W23
W26
V20
U19

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

MB_BANK2
MB_BANK1
MB_BANK0

K26 DDR_B_BS#2
T26 DDR_B_BS#1
U26 DDR_B_BS#0

DDR_B_BS#2 (9)
DDR_B_BS#1 (9)
DDR_B_BS#0 (9)

MB_RAS_L
MB_CAS_L
MB_WE_L

U24 DDR_B_RAS#
V26 DDR_B_CAS#
U22 DDR_B_WE#

DDR_B_RAS# (9)
DDR_B_CAS# (9)
DDR_B_WE# (9)

DDR_B_ODT1 (9)
DDR_B_ODT0 (9)
DDR_A_ODT1 (8)
DDR_A_ODT0 (8)
DDR_B_MA[15..0]

(9)

(9) DDR_B_DM[7..0]

DDR_A_CLK2

DDR_B_CLK2
1

DDR_A_CLK#2

1
C336
1.5P_0402_50V8C

DDR_B_CLK#2

DDR_A_CLK1

C349
1.5P_0402_50V8C

DDR_B_CLK1
1

DDR_A_CLK#1

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

To reverse SODIMM socket

VTT_SENSE

TP2
M_ZN
M_ZP

PAD

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

M_VREF

DDRII Cmd/Ctrl//Clk

W17
R386
39.2_0402_1%~D

1
C344
1.5P_0402_50V8C

DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR


WITHIN 1.2 INCH

C348
1.5P_0402_50V8C

PLACE CLOSE TO PROCESSOR


WITHIN 1.2 INCH

(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

AD12
AC16
AE22
AB26
E25
A22
B16
A12

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12
B12

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

Y13
AB16
Y19
AC24
F24
E19
C15
E12

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0]

(8)

To normal SODIMM socket

(9) DDR_B_D[63..0]

DDRII Data

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER


SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

DDR_A_DM[7..0]

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

(8)

(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)

FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket

+1.8V

R228
+0.9VREF_CPU
2

1K_0402_1%

CPU_VREF_REF
1

C358

C363

A1
C345

C357

A26

C350

R222
2

1000P_0402_50V7K

0.1U_0402_16V4Z

1U_0402_6.3V4Z

Athlon 64 S1g1

1K_0402_1%

1000P_0402_50V7K

1000P_0402_50V7K

uPGA638
Top View

VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU

AF1

Compal Secret Data

Security Classification

Issued Date

2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

AMD CPU DDRII MEMORY I/F


Size Document Number
Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P

Friday, April 20, 2007

Sheet
E

of

42

ATHLON Control and Debug

LAYOUT: ROUTE VDDA TRACE APPROX.


50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

R155
300_0402_5%

+2.5VS

FCM2012C-800_0805

22U_0805_6.3V6M

C276

2
4.7U_0805_10V4Z

C271

2
0.22U_0603_16V7K

C277
3300P_0402_50V7K

R370
R371

+1.8V

(15) CPU_SIC
(15) CPU_SID

R369 1
R368 1

+3VS

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#

300_0402_5%
300_0402_5%

2
2

CPU_SIC_R
CPU_SID_R

0_0402_5%
0_0402_5%

2
2
R378 1
R376 1

+1.2V_HT
+1.8V

1
1

2 44.2_0603_1%
2 44.2_0603_1%

CPU_HTREF1
CPU_HTREF0

+1.8V

5
A

place them to CPU within 1"

PAD
PAD

B7
A7
F10

RESET_L
PWROK
LDTSTOP_L
SIC
SID

TP3
TP1

1
R383

C5451

(10) CPUCLK

CPU_ALL_PWROK

2
0_0402_5%
@

HTREF1
HTREF0

F6
E6

VDD_FB_H
VDD_FB_L

CPU_PRESENT_L

W9
Y9

NC7SZ08P5X_NL_SC70-5
@

1
R380

2
0_0402_5%

C5441

(10) CPUCLK#

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

3900P_0402_50V7K
R382
169_0402_1%

A9
A8

R184
300_0402_5%

G10

DBRDY

CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

AA9
AC9
AD9
AF9

TMS
TCK
TRST_L
TDI

E9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8

TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12

C3
AA6
W7
W8
Y6
AB6

TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2

P20
P19
N20
N19

RSVD0
RSVD1
RSVD2
RSVD3

U9

2
2

1
R189

CPU_LDTSTOP#

2
0_0402_5%
@

NC7SZ08P5X_NL_SC70-5
@

1
R183

Y
3

(10) HTCPU_STOP#

2
0_0402_5%

CPU_THERMDC
CPU_THERMDA

+1.8V

10:10

R373
300_0402_5%

MCP_PWRGD_R

(10) HTCPU_RST#

U25

(15,18,27,28) MCP_PWRGD

+1.8V

+1.8V

R375
0_0402_5%

1
R377

CPU_HT_RESET#

2
0_0402_5%
@

NC7SZ08P5X_NL_SC70-5
@

1
R374

CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H

R199 1
R198 1
R188 1

2 300_0402_5%
2 1K_0402_5%
2 510_0402_5%

CPU_TEST21_SCANEN
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

R197
R387
R385
R215

2
2
2
2

1
1
1
1

300_0402_5%
510_0402_5%
300_0402_5%
300_0402_5%

R26
R25
P22
R22

2
0_0402_5%

A5
C6
A6
A4
C5
B5

VID5
VID4
VID3
VID2
VID1
VID0

AC6

CPU_PRESENT#

A3

PSI#

R156
300_0402_5%

VID5
VID4
VID3
VID2
VID1
VID0

(41)
(41)
(41)
(41)
(41)
(41)

PSI# (41)

CLKIN_H
CLKIN_L

CPU_DBRDY

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

+1.8V

PSI_L

AF6 H_THERMTRIP_S#
AC7 CPU_PROCHOT#_1.8

VDDIO_FB_H
VDDIO_FB_L

3900P_0402_50V7K
+1.8V

VID5
VID4
VID3
VID2
VID1
VID0

P6
R6

U26

2
2
(10) HTCPU_PWRGD

CPU_VCC_SENSE
CPU_VSS_SENSE

(41) CPU_VCC_SENSE
(41) CPU_VSS_SENSE

THERMTRIP_L
PROCHOT_L

AF4
AF5

5:10

R381
C543 0.1U_0402_16V4Z
4.7K_0402_5%
@
1
2

R379
300_0402_5%

VDDA2
VDDA1

DBREQ_L
TDO

TEST29_H
TEST29_L

MISC

C266

F8
F9

+2.5VS_VDDA

JP22D

W=50mils

2 L28

+1.8V

E10

CPU_DBREQ#

AE9 CPU_TDO

C9
C8

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

5:5:5

TEST24
TEST23
TEST22
TEST21
TEST20

AE7
AD7
AE8
AB8 CPU_TEST21_SCANEN
AF7

TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8

J7
H8
AF8
AE6 CPU_TEST26_BURNIN#
K8
C4

RSVD4
RSVD5
RSVD6
RSVD7

R384
1
2
80.6_0402_1%

RSVD8
RSVD9

H16
B18

RSVD10
RSVD11

B3
C1

RSVD12
RSVD13
RSVD14

H6
G6
D5

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

R24
W18
R23
AA8
H18
H19

ROUTE AS 80 Ohm DIFFERENTIAL PAIR


PLACE IT CLOSE TO CPU WITHIN 1"

FOX_PZ63823-284S-41F

+3V

NOTE: HDT TERMINATION IS REQUIRED


FOR REV. Ax SILICON ONLY.

R116
10K_0402_5%

3V_LDT_RST#

R113
220_0402_5%
HT@

Q16
H_THERMTRIP_S#

1
R535

2
1
0_0402_5%
@

3
1H_THERMTRIP#
MMBT3904_SOT23
1
R115

R117
@ 1K_0402_5%

R127
1K_0402_5%

2 2

+3V

+3VS

2
4
6
8
10
12
14
16
18
20
22
24
26

1
3
5
7
9
11
13
15
17
19
21
23

2
G

R159 1
2

+3V

Q15
MMBT3904_SOT23
1 @
MAINPWON (35,36,37)

2
0_0402_5%
@

CPU_HT_RESET#

H_THERMTRIP# (10)

220_0402_5%HT@

R160 1
2

+1.8V

R114
300_0402_5%

JP7

220_0402_5%HT@

R161 1
2

+1.8V

+1.8V

220_0402_5%HT@

R162 1

HDT Connector

220_0402_5%

R163 1
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

220_0402_5%HT@

HT@

AMD NPT S1 SOCKET


Processor Socket

+1.8V

Q14

SAMTEC_ASP-68200-07
@

2N7002_SOT23
HT@
+1.8V

+3VS

(27,28) EC_SMB_DA2

CPU_THERMDA

D+

VDD1

CPU_THERMDC

D-

ALERT#

THERM#

GND

EC_SMB_CK2

SCLK

EC_SMB_DA2

SDATA

Q19
(10) PROCHOT#

1
R141

CPU_PROCHOT#_1.8
2
0_0402_5%
@

3
1
MMBT3904_SOT23
C

(27,28) EC_SMB_CK2

U4
2200P_0402_50V7K
A

R186
@ 10K_0402_5%

0.1U_0402_16V4Z
2

C269

C275

R130
4.7K_0402_5%
2CPU_PH_G 2

R133
10K_0402_5%

+3VS

PVT Modify 2007/03/22

EC_THERM# (15,27,28)

Connect to MCP67

ADM1032ARM_RM8

Compal Secret Data

Security Classification

U2 CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PLACE
CLOSE TO PROCESSOR WITHIN 1" INCH

Issued Date

2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

AMD CPU CTRL & DEBUG


Size
C
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Sheet

Friday, April 20, 2007


1

of

42

+CPU_CORE

+ C548
2

+ C550

470U_D2E_2VM_R9

+ C546

470U_D2E_2VM_R9

+ C547

470U_D2E_2VM_R9

330U_D2E_2.5VM_R9

+CPU_CORE

+CPU_CORE
C287
10U_0805_10V6M
1
1

PROCESSOR POWER AND GROUND

C288
10U_0805_10V6M
1
1

C289
10U_0805_10V6M
1
1

1
+

2
2
C279
10U_0805_10V6M

2
2
C280
10U_0805_10V6M

2
2
C282
10U_0805_10V6M

C551
820U_E9_2.5V_M_R7
45@

2
2

C281
10U_0805_10V6M

JP22F

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

+1.8V

FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket

A1

A26

Athlon 64 S1g1
uPGA638

VSS1
VSS66
VSS2
VSS67
VSS3
VSS68
VSS4
VSS69
VSS5
VSS70
VSS6
VSS71
VSS7
VSS72
VSS8
VSS73
VSS9
VSS74
VSS10
VSS75
VSS11
VSS76
VSS12
VSS77
VSS13
VSS78
VSS14
VSS79
VSS15
VSS80
VSS16
VSS81
VSS17
VSS82
VSS18
VSS83
VSS19
VSS84
VSS20
VSS85
VSS21
VSS86
VSS22
VSS87
VSS23
VSS88
VSS24
VSS89
VSS25
VSS90
VSS26
VSS91
VSS27
VSS92
VSS28
VSS93
VSS29
VSS94
VSS30
VSS95
VSS31
VSS96
VSS32
VSS97
VSS33
VSS98
VSS34
VSS99
VSS35
VSS100
VSS36
VSS101
VSS37
VSS102
VSS38
VSS103
VSS39
VSS104
VSS40
VSS105
VSS41
VSS106
VSS42
VSS107
VSS43
VSS108
VSS44
VSS109
VSS45
VSS110
VSS46
VSS111
VSS47
VSS112
VSS48
VSS113
VSS49
VSS114
VSS50
VSS115
VSS51
VSS116
VSS52
VSS117
VSS53
VSS118
VSS54
VSS119
VSS55
VSS120
VSS56
VSS121
VSS57
VSS122
VSS58
VSS123
VSS59
VSS124
VSS60
VSS125
VSS61
VSS126
VSS62
VSS127
VSS63
VSS128
VSS64
VSS129
VSS65
FOX_PZ63823-284S-41F

Ground

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+CPU_CORE

Power

+CPU_CORE
JP22E
AC4 VDD1
AD2 VDD2
G4 VDD3
H2 VDD4
J9 VDD5
J11 VDD6
J13 VDD7
K6 VDD8
K10 VDD9
K12 VDD10
K14 VDD11
L4 VDD12
L7 VDD13
L9 VDD14
L11 VDD15
L13 VDD16
M2 VDD17
M6 VDD18
M8 VDD19
M10 VDD20
N7 VDD21
N9 VDD22
N11 VDD23
P8 VDD24
P10 VDD25
R4 VDD26
R7 VDD27
R9 VDD28
R11 VDD29
T2 VDD30
T6 VDD31
T8 VDD32
T10 VDD33
T12 VDD34
T14 VDD35
U7 VDD36
U9 VDD37
U11 VDD38
U13 VDD39
V6 VDD40
V8 VDD41
V10 VDD42

10/2 Modify

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

CPU SOCKET S1 DECOUPLING


+CPU_CORE

C315
22U_0805_6.3V6M

C326
22U_0805_6.3V6M

C332
10U_0805_10V6M

C333
22U_0805_6.3V6M

C327
10U_0805_10V6M

+CPU_CORE

C318
0.22U_0402_10V4Z

C328
10U_0805_10V6M

C324
10U_0805_10V6M

C316
10U_0805_10V6M

C334
22U_0805_6.3V6M

+1.8V

C308
0.22U_0402_10V4Z

C319
180P_0402_50V8J

C309
0.01U_0402_16V7K

C353
10U_0805_10V6M

C343
10U_0805_10V6M

C361
0.22U_0402_10V4Z

C356
0.22U_0402_10V4Z

DECOUPLING BETWEEN PROCESSOR AND DIMMs


PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8V

C352
4.7U_0805_10V4Z

C342
4.7U_0805_10V4Z

C351
4.7U_0805_10V4Z

C388
4.7U_0805_10V4Z

C362
0.22U_0402_10V4Z

C386
0.22U_0402_10V4Z

C383
0.22U_0402_10V4Z

C381
0.22U_0402_10V4Z

C385
0.01U_0402_16V7K

C382
0.01U_0402_16V7K

C340

C360

180P_0402_50V8J
2

180P_0402_50V8J

Athlon 64 S1
Processor Socket

Top View

+0.9V

AF1
2

C304
4.7U_0805_10V4Z

C299
1000P_0402_50V7K

C320
4.7U_0805_10V4Z

C303
4.7U_0805_10V4Z

C300
1000P_0402_50V7K

C302
4.7U_0805_10V4Z

C307
1000P_0402_50V7K

C313
0.22U_0402_10V4Z

C306
1000P_0402_50V7K

C305

C312
0.22U_0402_10V4Z

180P_0402_50V8J
2

0.22U_0402_10V4Z

C297

C314

180P_0402_50V8J
2

C296

C298
0.22U_0402_10V4Z

180P_0402_50V8J
2

C295
180P_0402_50V8J

Compal Secret Data

Security Classification

Issued Date

2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

AMD CPU PWR & GND


Size
C
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
1

of

42

+1.8V

+1.8V

+DIMM_VREF

+1.8V

C428

C579

+1.8V

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1

4.7U_0805_10V4Z

C417

C418

4.7U_0805_10V4Z

C415

C416

4.7U_0805_10V4Z

1
1

C422

150U_D2_6.3VM

C447

C448

C449

C450

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C451

2
1

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
2 47_0402_1%
2 47_0402_1%

DDR_A_MA14
4
DDR_A_MA15
3
47_0404_4P2R_5%
DDR_A_MA7
4
DDR_CKE1_DIMMA
3
47_0404_4P2R_5%
DDR_A_MA6
4
DDR_A_MA11
3
47_0404_4P2R_5%
DDR_A_MA2
4
DDR_A_MA4
3
47_0404_4P2R_5%
DDR_A_BS#1
4
DDR_A_MA0
3
47_0404_4P2R_5%
DDR_CS0_DIMMA#
4
DDR_A_RAS#
3
47_0404_4P2R_5%
DDR_A_MA13
4
DDR_A_ODT0
3
47_0404_4P2R_5%

1
2
RP15
1
2
RP16
1
2
RP17
1
2
RP20
1
2
RP18
1
2
RP19
1
2
RP21

+1.8V

2
C444

C442

C441

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C440

DDR_A_DQS#7
DDR_A_DQS7

C446

DDR_A_D60
DDR_A_D61

0.1U_0402_16V4Z

DDR_A_D54
DDR_A_D55

0.1U_0402_16V4Z

DDR_A_CLK2 (5)
DDR_A_CLK#2 (5)

DDR_A_DM6

+0.9V

Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V

DDR_A_D62
DDR_A_D63

Compal Secret Data

Security Classification
Issued Date

DIMM1 REV H:5.2mm (BOT)

0.1U_0402_16V4Z

DDR_CS3_DIMMA# (5)

DDR_A_D44
DDR_A_D45

2 10K_0402_5%
2 10K_0402_5%

0.1U_0402_16V4Z

1
2
RP10
1
2
RP11
DDR_A_MA9
1
DDR_A_MA8
2
RP12
DDR_A_MA5
1
DDR_A_MA3
2
RP13
DDR_A_MA1
1
DDR_A_MA10
2
RP14
DDR_A_BS#0
1
DDR_A_WE#
2
RP9
DDR_A_CAS#
1
DDR_CS1_DIMMA#
2
RP8
DDR_A_ODT1
R277
1
DDR_CS3_DIMMA# R280
1
DDR_A_BS#2
DDR_A_MA12

DDR_A_D38
DDR_A_D39

1
1

C452

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_ODT0 (5)

DDR_A_DM4

R281
R282

+0.9V

DDR_A_BS#1 (5)
DDR_A_RAS# (5)
DDR_CS0_DIMMA# (5)

DDR_A_D36
DDR_A_D37

DDR_A_CLK2
DDR_A_CLK#2

0.1U_0402_16V4Z

DDR_CS3_DIMMA#

C453

DDR_A_ODT0
DDR_A_MA13

FOX_AS0A426-M2RN-7F
<BOM Structure>

+ C628
220U_D2_4VM_R15

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

0.1U_0402_16V4Z

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

C429
0.1U_0402_16V4Z

C412

C445

0.1U_0402_16V4Z

MEM_SMBDATA
MEM_SMBCLK
+3VS

C439

(9,15) MEM_SMBDATA
(9,15) MEM_SMBCLK

DDR_A_MA15
DDR_A_MA14

0.1U_0402_16V4Z

DDR_A_D58
DDR_A_D59

DDR_CKE1_DIMMA (5)

C438

DDR_CKE1_DIMMA

0.1U_0402_16V4Z

DDR_A_DM7

DDR_A_D30
DDR_A_D31

C443

DDR_A_D56
DDR_A_D57

1
1

0.1U_0402_16V4Z

DDR_A_D50
DDR_A_D51

+0.9V

0.1U_0402_16V4Z

DDR_A_DQS#6
DDR_A_DQS6

4.7U_0805_10V4Z

DDR_A_D48
DDR_A_D49

DDR_A_DQS#3
DDR_A_DQS3

C432

DDR_A_D42
DDR_A_D43

DDR_A_DQS#[0..7]

C431

DDR_A_DM5

DDR_A_MA[0..15]

0.1U_0402_16V4Z

DDR_A_D40
DDR_A_D41

C411

DDR_A_D34
DDR_A_D35

4.7U_0805_10V4Z

DDR_A_DQS#4
DDR_A_DQS4

(5) DDR_A_DQS#[0..7]

0.1U_0402_16V4Z

4.7U_0805_10V4Z

DDR_A_D32
DDR_A_D33

DDR_A_D28
DDR_A_D29

C433

DDR_A_ODT1

(5) DDR_A_ODT1

DDR_A_DQS[0..7]

(5) DDR_A_DQS[0..7]
(5) DDR_A_MA[0..15]

C434

DDR_A_CAS#
DDR_CS1_DIMMA#

0.1U_0402_16V4Z

(5) DDR_A_CAS#
(5) DDR_CS1_DIMMA#

C435

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

(5) DDR_A_BS#0
(5) DDR_A_WE#

0.1U_0402_16V4Z

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

(5) DDR_A_DM[0..7]

DDR_A_D22
DDR_A_D23

C436

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

0.1U_0402_16V4Z

DDR_CS2_DIMMA#
DDR_A_BS#2

DDR_A_DM[0..7]

C437

(5) DDR_CS2_DIMMA#
(5) DDR_A_BS#2

0.1U_0402_16V4Z

(5) DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

DDR_A_D[0..63]

(5) DDR_A_D[0..63]

0.1U_0402_16V4Z

DDR_A_D26
DDR_A_D27

+1.8V

DDR_A_CLK1 (5)
DDR_A_CLK#1 (5)

C410

DDR_A_DM3

1K_0402_1%

4.7U_0805_10V4Z

DDR_A_DM2

R274

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

C573
0.22U_0603_16V7K
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C413
C398
C424
C426
C578
C576
C574
4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K0.22U_0603_16V7K

C409

DDR_A_D24
DDR_A_D25

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_A_CLK1
DDR_A_CLK#1

1K_0402_1%

4.7U_0805_10V4Z

DDR_A_D18
DDR_A_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_A_DM1

C408

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D12
DDR_A_D13

4.7U_0805_10V4Z

DDR_A_D16
DDR_A_D17

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D6
DDR_A_D7

C407

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_DM0

4.7U_0805_10V4Z

DDR_A_D10
DDR_A_D11

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

4.7U_0805_10V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C399
C414
C427
C425
C577
C575
4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K
1
1
1
1
1
1
1
1
1
1
1
1
1

R275

JP28
DDR_A_D0
DDR_A_D1

2006/08/18

2007/8/18

Deciphered Date

Title

DDR2 SO-DIMM I

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

of

42

+1.8V

+1.8V

DDR_B_D[0..63]

(5) DDR_B_D[0..63]

+DIMM_VREF

+1.8V
DDR_B_DM[0..7]

(5) DDR_B_DM[0..7]

DDR_B_D8
DDR_B_D9

C655
1000P_0402_50V7K

1
1

+ C629
220U_D2_4VM_R15

C631

C630

4.7U_0805_10V4Z

1
C633

C632

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1
C

2
C461

C462

C463

C465

DDR_CS3_DIMMB#

2
C464

C466

DDR_B_ODT0
DDR_B_MA13

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CKE1_DIMMB (5)

0.1U_0402_16V4Z

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V
DDR_CS2_DIMMB#
DDR_CKE0_DIMMB

DDR_B_BS#1 (5)
DDR_B_RAS# (5)
DDR_CS0_DIMMB# (5)

DDR_B_MA12
DDR_B_BS#2

DDR_B_ODT0 (5)

DDR_B_MA8
DDR_B_MA9

DDR_CS3_DIMMB# (5)

DDR_B_MA3
DDR_B_MA5

DDR_B_D36
DDR_B_D37
DDR_B_DM4

DDR_B_MA10
DDR_B_MA1

DDR_B_D38
DDR_B_D39

DDR_B_WE#
DDR_B_BS#0

DDR_B_D44
DDR_B_D45

DDR_CS0_DIMMB#
DDR_B_RAS#

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_ODT1
DDR_CS3_DIMMB#

1
2
RP22
1
2
RP23
1
2
RP24
1
2
RP25
1
2
RP26
1
2
RP27
1
2
RP29
R286
1
R287
1

4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
4
3
47_0404_4P2R_5%
2 47_0402_1%
2 47_0402_1%

DDR_CKE1_DIMMB
4
DDR_B_MA15
3
47_0404_4P2R_5%
DDR_B_MA14
4
DDR_B_MA11
3
47_0404_4P2R_5%
DDR_B_MA7
4
DDR_B_MA6
3
47_0404_4P2R_5%
DDR_B_MA4
4
DDR_B_MA2
3
47_0404_4P2R_5%
DDR_B_MA0
4
DDR_B_BS#1
3
47_0404_4P2R_5%
DDR_B_CAS#
4
DDR_CS1_DIMMB#
3
47_0404_4P2R_5%
DDR_B_ODT0
4
DDR_B_MA13
3
47_0404_4P2R_5%

1
2
RP30
1
2
RP31
1
2
RP32
1
2
RP33
1
2
RP34
1
2
RP28
1
2
RP35

DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
+1.8V

2
C484

C485

C486

C477

C458

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V

DDR_B_D62
DDR_B_D63
2 10K_0402_5%
2 10K_0402_5%

+0.9V

DDR_B_DQS#7
DDR_B_DQS7

R289 1
R288 1

C470

DDR_B_D60
DDR_B_D61

0.1U_0402_16V4Z

DDR_B_D54
DDR_B_D55

0.1U_0402_16V4Z

DDR_B_DM6

0.1U_0402_16V4Z
C457

DDR_B_CLK2 (5)
DDR_B_CLK#2 (5)

0.1U_0402_16V4Z
C469

DDR_B_CLK2
DDR_B_CLK#2

Change PCB Footprint

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DIMM0 REV H:9.2mm (BOT)


5

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

C456
0.1U_0402_16V4Z

DDR_B_MA15
DDR_B_MA14

FOX_AS0A426-MARG-7F
2

0.1U_0402_16V4Z

DDR_CKE1_DIMMB

C471

+3VS

DDR_B_D30
DDR_B_D31

0.1U_0402_16V4Z

MEM_SMBDATA
MEM_SMBCLK

(8,15) MEM_SMBDATA
(8,15) MEM_SMBCLK

DDR_B_DQS#3
DDR_B_DQS3

C472

DDR_B_D58
DDR_B_D59

DDR_B_D28
DDR_B_D29

0.1U_0402_16V4Z

DDR_B_DM7
A

DDR_B_D22
DDR_B_D23

C476

DDR_B_D56
DDR_B_D57

+0.9V

0.1U_0402_16V4Z

DDR_B_D50
DDR_B_D51

DDR_B_DM2

0.1U_0402_16V4Z

DDR_B_DQS#6
DDR_B_DQS6

C626

DDR_B_D48
DDR_B_D49

4.7U_0805_10V4Z

DDR_B_D42
DDR_B_D43

C478

DDR_B_DM5

4.7U_0805_10V4Z

DDR_B_D40
DDR_B_D41

DDR_B_D20
DDR_B_D21

0.1U_0402_16V4Z

DDR_B_D34
DDR_B_D35

C627

DDR_B_DQS#4
DDR_B_DQS4

4.7U_0805_10V4Z

DDR_B_D32
DDR_B_D33
B

C479

DDR_B_ODT1

(5) DDR_B_ODT1

1
C622

DDR_B_CAS#
DDR_CS1_DIMMB#

C480

(5) DDR_B_CAS#
(5) DDR_CS1_DIMMB#

0.1U_0402_16V4Z

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

(5) DDR_B_BS#0
(5) DDR_B_WE#

4.7U_0805_10V4Z

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

C623

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_D14
DDR_B_D15

C481

DDR_CS2_DIMMB#
DDR_B_BS#2

DDR_B_CLK1 (5)
DDR_B_CLK#1 (5)

0.1U_0402_16V4Z

(5) DDR_CS2_DIMMB#
(5) DDR_B_BS#2

DDR_B_CLK1
DDR_B_CLK#1

C482

(5) DDR_CKE0_DIMMB

DDR_CKE0_DIMMB

DDR_B_DM1

C483

DDR_B_D26
DDR_B_D27

+1.8V

4.7U_0805_10V4Z

DDR_B_DM3

DDR_B_D12
DDR_B_D13

0.1U_0402_16V4Z

C656
1000P_0402_50V7K

C653
1000P_0402_50V7K

C624

DDR_B_D24
DDR_B_D25

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

(5) DDR_B_DQS#[0..7]

0.1U_0402_16V4Z

DDR_B_D18
DDR_B_D19

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_B_DQS#[0..7]

4.7U_0805_10V4Z

DDR_B_DQS#2
DDR_B_DQS2

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_MA[0..15]

(5) DDR_B_MA[0..15]

0.1U_0402_16V4Z

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D16
DDR_B_D17

DDR_B_D6
DDR_B_D7

C625

DDR_B_D10
DDR_B_D11

DDR_B_DM0

4.7U_0805_10V4Z

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D4
DDR_B_D5

(5) DDR_B_DQS[0..7]
C459

DDR_B_D2
DDR_B_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C455

DDR_B_DQS#0
DDR_B_DQS0

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1
D

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

4.7U_0805_10V4Z

JP29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C654
1000P_0402_50V7K

DDR_B_DQS[0..7]

+3VS

Compal Secret Data

Security Classification
Issued Date

2006/08/18

2007/8/18

Deciphered Date

Title

DDR2 SO-DIMM II

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

of

42

U23A

(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

(4)
(4)
(4)
(4)

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

MCP67
PART 1 OF 8

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

AF16
AG16
AH16
AJ16
AJ15
AK15
AK16
AL16
AG17
AF17
AL17
AK17
AL18
AK18
AJ19
AK19

HT_MCP_RXD0_P
HT_MCP_RXD0_N
HT_MCP_RXD1_P
HT_MCP_RXD1_N
HT_MCP_RXD2_P
HT_MCP_RXD2_N
HT_MCP_RXD3_P
HT_MCP_RXD3_N
HT_MCP_RXD4_P
HT_MCP_RXD4_N
HT_MCP_RXD5_P
HT_MCP_RXD5_N
HT_MCP_RXD6_P
HT_MCP_RXD6_N
HT_MCP_RXD7_P
HT_MCP_RXD7_N

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

AD14
AE14
AF14
AG14
AH14
AJ14
AL13
AK13
AC15
AD15
AD16
AE16
AE17
AD17
AB17
AC17

HT_MCP_RXD8_P
HT_MCP_RXD8_N
HT_MCP_RXD9_P
HT_MCP_RXD9_N
HT_MCP_RXD10_P
HT_MCP_RXD10_N
HT_MCP_RXD11_P
HT_MCP_RXD11_N
HT_MCP_RXD12_P
HT_MCP_RXD12_N
HT_MCP_RXD13_P
HT_MCP_RXD13_N
HT_MCP_RXD14_P
HT_MCP_RXD14_N
HT_MCP_RXD15_P
HT_MCP_RXD15_N

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

AJ17
AH17
AL14
AK14

HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N

H_CTLOP0
H_CTLON0

AH19
AG19
AC18
AD18

HT_MCP_RXCTL0_P
HT_MCP_RXCTL0_N
HT_MCP_RXCTL1_P/RESERVED
HT_MCP_RXCTL1_N/RESERVED

AC13
AB13

THERMTRIP#/GPIO_58
PROCHOT#/GPIO_20

+3.3V_PLL_CPU

AB16

+3.3V_PLL_CPU

+1.2V_PLL_CPU_HT

AB15

+1.2V_PLL_CPU_HT

HT_MCP_TXD0_P
HT_MCP_TXD0_N
HT_MCP_TXD1_P
HT_MCP_TXD1_N
HT_MCP_TXD2_P
HT_MCP_TXD2_N
HT_MCP_TXD3_P
HT_MCP_TXD3_N
HT_MCP_TXD4_P
HT_MCP_TXD4_N
HT_MCP_TXD5_P
HT_MCP_TXD5_N
HT_MCP_TXD6_P
HT_MCP_TXD6_N
HT_MCP_TXD7_P
HT_MCP_TXD7_N

AK27
AJ27
AK26
AL26
AK25
AL25
AL24
AK24
AK22
AL22
AK21
AL21
AH21
AJ21
AL20
AM20

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

HT_MCP_TXD8_P
HT_MCP_TXD8_N
HT_MCP_TXD9_P
HT_MCP_TXD9_N
HT_MCP_TXD10_P
HT_MCP_TXD10_N
HT_MCP_TXD11_P
HT_MCP_TXD11_N
HT_MCP_TXD12_P
HT_MCP_TXD12_N
HT_MCP_TXD13_P
HT_MCP_TXD13_N
HT_MCP_TXD14_P
HT_MCP_TXD14_N
HT_MCP_TXD15_P
HT_MCP_TXD15_N

AG27
AH27
AF25
AG25
AH25
AJ25
AE23
AF23
AD21
AE21
AF21
AG21
AC20
AD20
AE19
AF19

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N

AK23
AJ23
AG23
AH23

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

HT_MCP_TXCTL0_P
HT_MCP_TXCTL0_N
RESERVED/HT_MCP_TXCTL1_P
RESERVED/HT_MCP_TXCTL1_N

AK20
AJ20
AD19
AC19

H_CTLIP0
H_CTLIN0

HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_RST#
HT_MCP_PWRGD

AD23
AB20
AC21
AD22

CLKOUT_200MHZ_P
CLKOUT_200MHZ_N

AL28
AM28

CLKOUT_25MHZ

AK28

HT

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

(4)
(4)
(4)
(4)

(6) H_THERMTRIP#
(6) PROCHOT#

+3VS

L7 1
2
MBK1608121YZF_0603

C46
4.7U_0805_10V4Z
1

C43
0.1U_0402_16V4Z
1

HTCPU_REQ#
HTCPU_STOP#
HTCPU_RST#
HTCPU_PWRGD

CPUCLK (6)
CPUCLK# (6)

1
R366

HT_MCP_COMP_VDD

AL12
150_0402_1% HT_MCP_COMP_GND

CPU_SBVREF

AG28

CLK200_TERM_GND

AJ28

TP4

MCP67-MV_PBGA836

PAD

R123
2.37K_0402_1%
2

L13 1
2
MBK1608121YZF_0603

C141
10U_0805_10V4Z
C101
1
1 0.1U_0402_16V4Z

AM12
2
150_0402_1%

+1.2V_HT

+1.2V_HT

2
1
R364

R164
22K_0402_5%

HTCPU_STOP# (6)
HTCPU_RST# (6)
HTCPU_PWRGD (6)

+1.2V_HT
2

H_CTLIP0 (4)
H_CTLIN0 (4)

+3VS

(4) H_CTLOP0
(4) H_CTLON0

9/25 Modify TO +3VS

C136
0.1U_0402_16V4Z

Compal Secret Data

Security Classification

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

MCP67 HT LINK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

10

of

42

PCIE_GTX_C_MRX_P[0..15]

(18) PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_P[0..15]

(18) PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

(18) PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_N[0..15]

(18) PCIE_MTX_C_GRX_N[0..15]
U23B

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

R45
10K_0402_5%
@
(25,26,27) MCP_PCIE_WAKE#

R365 2
R367 2
R149 2

MCP_PCIE_WAKE#
1 10K_0402_5% @
1 10K_0402_5% @
1 10K_0402_5% @

H17
U31
U30
U29
U28

PE_WAKE#/GPIO_21
PE0_PRSNTX1#/DDC_CLK1
PE0_PRSNTX4#/DDC_DATA1
PE0_PRSNTX8#/EXP_EN
PE0_PRSNTX16#

PE0_REFCLK_P
PE0_REFCLK_N

R29 CLK_PCIE_VGA
R30 CLK_PCIE_VGA#

PCIE_MRX_PTX_P1_R
PCIE_MRX_PTX_N1_R

L29
L30
W27
W28

PE1_RX_P
PE1_RX_N
PEA_CLKREQ#
PEA_PRSNT#

PE1_TX_P
PE1_TX_N
PE1_REFCLK_P
PE1_REFCLK_N

M28 PCIE_MTX_PRX_P1
M29 PCIE_MTX_PRX_N1
T32
T31

M26
M27
U26
U27

PE2_RX_P
PE2_RX_N
PEB_CLKREQ#
PEB_PRSNT#

PE2_TX_P
PE2_TX_N
PE2_REFCLK_P
PE2_REFCLK_N

M24 PCIE_MTX_PRX_P2
M25 PCIE_MTX_PRX_N2
T29
T30

(18) PE_PRSNTX16#
(26) PCIE_MRX_PTX_P1
(26) PCIE_MRX_PTX_N1
(26) EXP_CLKREQ#

R146 1
R147 1
+3VS

(25) PCIE_MRX_PTX_P2
(25) PCIE_MRX_PTX_N2
(25) MINI2_CLKREQ#

R139 1
R140 1
+3VS

(25) PCIE_MRX_PTX_P3
(25) PCIE_MRX_PTX_N3
(25) MINI1_CLKREQ#

EXPRESS@
2 0_0402_5%
2 0_0402_5%
EXPRESS@
R152 2
PEA_PRSNT#

R134 1
R135 1
+3VS

1 10K_0402_5%
EXPRESS@

2 0_0402_5% MINI2@
2 0_0402_5% MINI2@
R118 2
PEB_PRSNT#
MINI1@
0_0402_5%
2
2 0_0402_5%
MINI1@
R148 2
PEC_PRSNT#

PCIE_MRX_PTX_P2_R
PCIE_MRX_PTX_N2_R
1 10K_0402_5%
MINI2@
PCIE_MRX_PTX_P3_R
PCIE_MRX_PTX_N3_R
1 10K_0402_5%
MINI1@

C115
4.7U_0805_10V4Z

L19 1
2
MBK1608121YZF_0603

C105
0.1U_0402_16V4Z

+1.2V_PLL_PE_SS1

N23
N22
U25
U24

PE3_RX_P
PE3_RX_N
PEC_CLKREQ#
PEC_PRSNT#

PE3_TX_P
PE3_TX_N
PE3_REFCLK_P
PE3_REFCLK_N

N30
N31
R22
U23

PE4_RX_P
PE4_RX_N
PED_CLKREQ#/GPIO_16
PED_PRSNT#

PE4_TX_P
PE4_TX_N
PE4_REFCLK_P
PE4_REFCLK_N

M30
M31
T25
T26

P31
P30
T22
V31

PE5_RX_P
PE5_RX_N
PEE_CLKREQ#/GPIO_17
PEE_PRSNT#

PE5_TX_P
PE5_TX_N
PE5_REFCLK_P
PE5_REFCLK_N

P29
P28
T23
T24

P26
P27
U22
V30

PE6_RX_P
PE6_RX_N
PEF_CLKREQ#/GPIO_18
PEF_PRSNT#

PE6_TX_P
PE6_TX_N
PE6_REFCLK_P
PE6_REFCLK_N

P24
P25
P23
R23

+1.2V_PLL_PE_SS1
+1.2V_PLL_PE_SS2

R20
R19

+1.2V_PLL_PE1
+1.2V_PLL_PE2

P19
P20

+3.3V_PLL_PE_SS1
+3.3V_PLL_PE_SS2

C167 1

2 0.1U_0402_16V7K

C196 1

2 0.1U_0402_16V7K

C169 1

2 0.1U_0402_16V7K

C198 1

2 0.1U_0402_16V7K

C171 1

2 0.1U_0402_16V7K

C200 1

2 0.1U_0402_16V7K

C173 1

2 0.1U_0402_16V7K

C202 1

2 0.1U_0402_16V7K

C175 1

2 0.1U_0402_16V7K

C204 1

2 0.1U_0402_16V7K

C177 1

2 0.1U_0402_16V7K

C229 1

2 0.1U_0402_16V7K

C238 1

2 0.1U_0402_16V7K

C231 1

2 0.1U_0402_16V7K

C240 1

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

+3VS

MP 2007/4/12 Added
R550
R551

+1.2V_PLL_PE1

L5 1
2
MBK1608121YZF_0603
C18
C104
L6 1
2 4.7U_0805_10V4Z 0.1U_0402_16V4Z
MBK1608121YZF_0603
1
1
1

1 @
1K_0402_1%

PEA_PRSNT#

1 MINI2@
1K_0402_1%

PEB_PRSNT#

EXPRESS@
C249 1
2 0.1U_0402_16V7K
C248
1
2 0.1U_0402_16V7K
EXPRESS@
MINI2@
C220 1
2 0.1U_0402_16V7K
C219
1
2 0.1U_0402_16V7K
MINI2@
MINI1@
C235 1
2 0.1U_0402_16V7K
C234
1
2 0.1U_0402_16V7K
MINI1@

PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1
CLK_PCIE_CARD
CLK_PCIE_CARD#

PCIE_MTX_C_PRX_P1 (26)
PCIE_MTX_C_PRX_N1 (26)
CLK_PCIE_CARD (26)
CLK_PCIE_CARD# (26)

PCIE_MTX_C_PRX_P2
PCIE_MTX_C_PRX_N2
CLK_PCIE_MINI2
CLK_PCIE_MINI2#

PCIE_MTX_C_PRX_P2 (25)
PCIE_MTX_C_PRX_N2 (25)
CLK_PCIE_MINI2 (25)
CLK_PCIE_MINI2# (25)

PCIE_MTX_C_PRX_P3
PCIE_MTX_C_PRX_N3
CLK_PCIE_MINI1
CLK_PCIE_MINI1#

PCIE_MTX_C_PRX_P3 (25)
PCIE_MTX_C_PRX_N3 (25)
CLK_PCIE_MINI1 (25)
CLK_PCIE_MINI1# (25)

1 MINI1@
1K_0402_1%

V24

C25
4.7U_0805_10V4Z

PEC_PRSNT#

C26
0.1U_0402_16V4Z

MINI_CARD(TV)

C267
0.1U_0402_16V4Z

2
(15,31) HT_VLD

U5

HT_VLD

PE_RST0#

PCIE_RST#

PCIE_RST# (18,26)

FOR VGA,LAN,NEW CARD

PE_RST0#

W30

W29

MINI_CARD(WLAN)

R170 1

PEX_RST1#

NEW CARD

+3V

NC7SZ08P5X_NL_SC70-5
@

PEX_RST#

R165 1

2 0_0402_5% PCIE_RST1#

2 0_0402_5%

PCIE_RST1# (25)

FOR MINI CARD

PE_CLK_COMP
@ R169
PCIE_RST1# 1

MCP67-MV_PBGA836
R145
2.37K_0402_1%
@

0_0402_5%
2 PCIE_RST#

R552

+3.3V_PLL_PE_SS1
1

+1.2VS

CLK_PCIE_VGA (18)
CLK_PCIE_VGA# (18)

M22 PCIE_MTX_PRX_P3
M23 PCIE_MTX_PRX_N3
T27
T28

U19
U20

2 0.1U_0402_16V7K

+1.2VS

C194 1

VGA@ C193
VGA@
VGA@ C166
VGA@
VGA@ C195
VGA@
VGA@ C168
VGA@
VGA@ C197
VGA@
VGA@ C170
VGA@
VGA@ C199
VGA@
VGA@ C172
VGA@
VGA@ C201
VGA@
VGA@ C174
VGA@
VGA@ C203
VGA@
VGA@ C176
VGA@
VGA@ C228
VGA@
VGA@ C237
VGA@
VGA@ C230
VGA@
VGA@ C239
VGA@

+3V

PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N

PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

D24
C24
A24
B24
B25
C25
B26
C26
C27
D27
A28
B28
A29
B29
A30
B30
B31
B32
C31
C32
D31
D32
E31
E30
F31
F30
G29
G30
H29
H30
H32
H31

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

F23
G23
F24
F25
D25
D26
C28
D28
C29
C30
D29
D30
F26
F27
F28
F29
H23
H24
H25
H26
H27
H28
K24
K25
K27
K26
K28
K29
J31
J30
K31
K30

PCIE GFX I/F

CLOSE TO CONNECT

MVP67
PART 2 OF 8

PEA_PRSNT#
R553
PEB_PRSNT#
R554
PEC_PRSNT#
R555

EXP_CLKREQ#
0_0402_5% @
MINI2_CLKREQ#
0_0402_5% @
MINI1_CLKREQ#
2
0_0402_5% @

Compal Secret Data

Security Classification
(14,26) CP_PE#

R563

PEA_PRSNT#
0_0402_5% EXPRESS@

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

MCP67 PCIE LINK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

11

of

42

+3V

+3VMAC
+3VMAC

+1.2VALW

+3VMAC

2 C53
0.1U_0402_16V4Z

+3V

2
2

SS%

NC

GND

VDD

SSON CLKOUT

R527
10K_0402_5%

(20,27,28) DPST_PWM
(18,27,28) ENBKL
(20) UMA_ENVDD
0.1U_0402_16V4Z
2

TXCLK_PHY
22_0402_5%

TXCLK_PHY (22)

PVT Modify 2007/03/12

L20
MBK1608121YZF_0603
L22
MBK1608121YZF_0603

2 LCD_BKLT_EN
0_0402_5% UMA@

1
R121

+3VS

C190
1U_0402_6.3V4Z

L24
MBK1608121YZF_0603
@
C210
4.7U_0805_10V4Z

DACS

TV_DAC_RSET
TV_DAC_VREF

+3VS

AD24
AE25
AE27

LCD_BKL_CTL
LCD_BKL_ON
LCD_PANEL_PWR

AL29
AM29

HDMI_TXC_P
HDMI_TXC_N

AK29
AJ29
AM30
AL30
AK30
AJ30

HDMI_TXD0_P
HDMI_TXD0_N
HDMI_TXD1_P
HDMI_TXD1_N
HDMI_TXD2_P
HDMI_TXD2_N

2
2

22K_0402_5%
6.2K_0402_5%

AE26
AL32

HPLUG_DET3
HPLUG_DET2

R136 1

10K_0402_5%

AD25
AC26

HDCP_ROM_SCLK
HDCP_ROM_SDATA

AC24
AC25

+1.8V_IFPA
+1.8V_IFPB

AC23
AC22

+3.3V_IFPAB_HVDD
+3.3V_HDMI_PLL_HVDD

+3.3V_PLL_IFPP

C221
0.1U_0402_16V4Z
1

RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
RGB_DAC_HSYNC
RGB_DAC_VSYNC

G21
H21

UMA_CRT_HSYNC
UMA_CRT_VSYNC

G8
H8

UMA_CRT_CLK (19)
UMA_CRT_DATA (19)

FLAT PANEL

+3.3V_HDMI

2 C212
0.01U_0402_16V7K

AH29

+3.3V_HDMI

AK31
AK32

HDMI_RSET
HDMI_VPROBE

UMA_CRT_R
UMA_CRT_G
UMA_CRT_B

C36
1 4.7U_0805_10V4Z

F21

TV_DAC_RED
TV_DAC_GREEN
TV_DAC_BLUE

C23
C22
D23

UMA_TV_CRMA
UMA_TV_LUMA
UMA_TV_COMPS

IFPA_TXC_P
IFPA_TXC_N

AE30
AE31

UMA_TXCLK+
UMA_TXCLK-

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

AC30
AC29
AC27
AC28
AD30
AD29
AD31
AD32

UMA_TXOUT0+
UMA_TXOUT0UMA_TXOUT1+
UMA_TXOUT1UMA_TXOUT2+
UMA_TXOUT2-

IFPB_TXC_P
IFPB_TXC_N

AJ31
AJ32

UMA_TZCLK+
UMA_TZCLK-

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N

AE28
AE29
AF30
AF31
AG30
AG29
AH31
AH30

UMA_TZOUT0+
UMA_TZOUT0UMA_TZOUT1+
UMA_TZOUT1UMA_TZOUT2+
UMA_TZOUT2-

DDC_CLK2
DDC_DATA2

L21
J22

UMA_LCD_CLK
UMA_LCD_DATA

DDC_CLK3
DDC_DATA3

L22
K22

DDC_DATA3

MP Modify 2007/04/13

AB31
AB30

2
1

TXCLK_R

(19)
(19)

C658
33P_0402_50V8K
@

+3VS

L8
1
2
MBK2012121YZF_0805

TXCLK

C38
1 C58
1
0.1U_0402_16V4Z 4.7U_0805_10V4Z

C
C681
33P_0402_50V8K
@

UMA_TV_CRMA (19)
UMA_TV_LUMA (19)
UMA_TV_COMPS (19)

UMA_CRT_R

R63 1

UMA_CRT_G

R62 1

UMA_CRT_B

R64 1

UMA_TV_CRMA

R3321

UMA_TV_LUMA

R3241

UMA@
2 150_0402_1%
UMA@
2 150_0402_1%
UMA@
150_0402_1%
2

UMA_TXCLK+ (20)
UMA_TXCLK- (20)
UMA_TXOUT0+
UMA_TXOUT0UMA_TXOUT1+
UMA_TXOUT1UMA_TXOUT2+
UMA_TXOUT2-

(20)
(20)
(20)
(20)
(20)
(20)

UMA&TV@
2 150_0402_1%
UMA&TV@
2 150_0402_1%
UMA&TV@
150_0402_1%
2

UMA_TV_COMPS R3251

UMA_TZCLK+ (20)
UMA_TZCLK- (20)
UMA_TZOUT0+
UMA_TZOUT0UMA_TZOUT1+
UMA_TZOUT1UMA_TZOUT2+
UMA_TZOUT2-

(20)
(20)
(20)
(20)
(20)
(20)

+3VS
UMA@
R361 1

2 2.7K_0402_5%

R359 1

2 2.7K_0402_5% UMA_LCD_DATA

UMA_LCD_CLK

UMA_LCD_CLK (20)
UMA_LCD_DATA (20)

R57

DDC_DATA3

2
10K_0402_5%

IFPAB_RSET
IFPAB_PROBE

1
MCP67-MV_PBGA836
R144
C160
1K_0402_1%
0.1U_0402_16V4Z
2 @
@

1
R372
1K_0402_1%
2 C528
@
0.01U_0402_16V7K
@

+1.2VALW

R61
1.47K_0402_1%

C178
4.7U_0805_10V4Z
+3V

UMA_CRT_R (19)
UMA_CRT_G (19)
UMA_CRT_B (19)

C42
0.1U_0402_16V4Z

E21

+3.3V_TV_DAC

IFPAB_RSET
IFPAB_VPROBE

MII_RST (22) C40


0.1U_0402_16V4Z

2
2
C211
4.7U_0805_10V4Z

+3V

R69
1.47K_0402_1%

B21
C21
B22

R478
10K_0402_5%

+3VMAC

10K_0402_5%

C18
H20

2
GPIO_6/FERR//SYS_SERR/IGPU_GPIO_6*
GPIO_7/NFERR//SYS_PERR/IGPU_GPIO_7*

TXCTL (22)

MII_RESET#
MII_VREF

DDC_CLK0
DDC_DATA0

RGMII_PWRDWN#
2

D17 RGMII_PWRDWN#
R94

R472
10K_0402_5%
@

1 C44
0.1U_0402_16V4Z

TXD0 (22)
TXD1 (22)
TXD2 (22)
TXD3 (22)
TXCLK

G17

+3.3V_RGB_DAC

R24 1
R138 1

+1.8V_IFP_MCP

C148
0.1U_0402_16V4Z

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%
33_0402_5%
22_0402_5%

2
2
2
2
2
2

BUF_25MHZ

+3.3V_PLL_DISP
TV_XTALIN
TV_XTALOUT

+3VS

0_0603_5%
2

1
1
1
1
1
1

RGMII_MDC (22)
RGMII_MDIO (22)

2 C61
C507
C66 2
22P_0402_50V8J 4.7U_0805_10V4Z
0.1U_0402_16V4Z
UMA&TV@

2 TXCLK_PHY_R
0_0402_5% @

+3VS

RGB_DAC_RSET
RGB_DAC_VREF

C682

1
R529

RGMII/MII_PWRDWN#/GPIO_37

U11
T11

L25
MBK1608121YZF_0603

+1.8VS

27MHZ_20P_7A27000010 1
UMA&TV@
C508
22P_0402_50V8J
2
UMA&TV@

S IC PCS3P23Z01DG-08-TR TSSOP 8P
TXCLK_PHY_R 1
R528

TXCLK

K20
L20

R79
1
R473
R471
R474
R475
R476
R477

2
U40

NC

N15
E17
F17

Y3
1

CLKIN

2 C103
R66
E23
124_0402_1% 0.01U_0402_16V7K H22

NB_XTALIN
NB_XTALOUT

R525
10K_0402_5%

RGMII/MII_MDC
RGMII/MII_MDIO

TXD0_R
TXD1_R
TXD2_R
TXD3_R
TXCLK_R
TXCTL_R

2
C55
0.01U_0402_16V7K

R67
124_0402_1%

+3.3V_PLL

MII_COMP_3P3V
MII_COMP_GND

K21
D21

R68
49.9_0402_1%

R526
10K_0402_5%
@
TXCLK

+3.3V_PLL_MAC_DUAL

B17
C17

RGMII_TXD0/MII_TXD0
RGMII_TXD1/MII_TXD1
RGMII_TXD2/MII_TXD2
RGMII_TXD3/MII_TXD3
RGMII_TXCLK/MII_TXCLK
RGMII_TXCTL/MII_TXEN

+1.2VALW_MAC

+3V

RGMII/MII_INTR/GPIO35

N18
J19
K19
L19
L18
H19
K18

MP Modify 2007/04/19

B18
N13

+1.2V_DUAL_RMGT

2 RGMII_INTR_R
0_0402_5%

L14

RGMII_INTR
1
R514

(22) RGMII_INTR
R349
49.9_0402_1%

C51
4.7U_0805_10V4Z

MII_RXER/GPIO_36
MII_COL/MI2C_DATA
MII_CRS/MI2C_CLK

+3.3V_DUAL_RMGT

L9
MBK1608121YZF_0603

MP Modify 2007/04/13

1 10K_0402_5% @
10K_0402_5% @
RGMII_INTR_R
1

C19
J18
D19

LAN

R479 2
R321
2

RGMII_RXD0/MII_RXD0
RGMII_RXD1/MII_RXD1
RGMII_RXD2/MII_RXD2
RGMII_RXD3/MII_RXD3
RGMII_RXC/MII_RXCLK
RGMII_RXCTL/MII_RXDV

40 mil

B20
C20
E19
F19
G19
J20

+3VMAC

RXD0
RXD1
RXD2
RXD3
RXCLK
RXCTL

RXD0
RXD1
RXD2
RXD3
RXCLK
RXCTL

0_0603_5%
2

2
0_0805_5%

1
R557

(22)
(22)
(22)
(22)
(22)
(22)

+3VMAC

R52
1

+3VMAC

+3VAUX

+3V

MCP67
PART 3 OF 8

2
@ 0_0805_5%

U23C
1
R556

2
2 C163
0.1U_0402_16V4Z

R558
10K_0402_5%

R559
20K_0402_1%

Q62
AO3413_SOT23-3

1
3

(15,22) SLP_RMGT#

R560
0_0402_5%

Q63
2N7002_SOT23 +1.2VALW_MAC

2
G

1 C691
0.1U_0402_16V4Z

6 mil
2

Compal Secret Data

Security Classification

2
D

PVT Modify 2007/03/12

PVT Modify 2007/03/12


S

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

MCP67 LAN/ CRT/ LVDS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

12

of

42

+3V
SBPWR_EN# (34)

E10
G10
J10
M11
E8

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#

MCP67
PART 4 OF 8

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

(23) PCI_REQ#0

8.2K_1206_8P4R_5%

U23D

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#

F10
H10
K10
L10
F8

PCI_GNT#0

PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

K12
K13
F14
K16

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#

L13
J14
H14
B14
J13
C13
B13

PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_STOP#

PCI_PME#/GPIO_30

C16

PCI_PME#

PCI_CBE#[3..0]
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_AD[31..0]

(23) PCI_AD[31..0]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

D10
B10
C10
L12
K11
J11
D11
C11
J12
H12
G12
F12
E12
D12
C12
B12
G14
E14
D14
J15
C14
D15
K15
C15
L16
G16
J16
E16
H16
D16
F16
A16

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

(23) PCI_PIRQE#
(23) PCI_PIRQF#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

L17
J17
B16
K17

PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#

(23) PCI_TRDY#

PCI_TRDY#

K14

8.2K_1206_8P4R_5%

RP5
+3VS

1
2
3
4

8
7
6
5

PCI_SERR#
PCI_TRDY#
PCI_FRAME#
PCI_STOP#

8.2K_1206_8P4R_5%

RP4
+3VS

1
2
3
4

8
7
6
5

PCI_IRDY#
PCI_PERR#
PCI_DEVSEL#

8.2K_1206_8P4R_5%
C

RP1
+3VS

1
2
3
4

8
7
6
5

PCI_REQ#4
PM_CLKRUN#

8.2K_1206_8P4R_5%

LPC_DRQ#0
(23,27,28) SERIRQ
(23,27,28) PM_CLKRUN#

LPC_DRQ#1
LPC_DRQ#0

C6
B6

SERIRQ
PM_CLKRUN#

D6
D5

IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15

(21) IDE_D[15..0]
(21) IDE_DREQ
(21) IDE_IRQ
(21) IDE_IORDY
(21) IDE_IOR#

IDE_D[15..0]

IDE_IOR#
1
R362 2
R43

AF10
AL9
AK8
AK7
AK6
AJ6
AL5
AL4
AJ5
AK5
AL6
AJ7
AJ8
AL8
AK9
AG10

IDE_DREQ AK11
IDE_IRQ
AH10
IDE_IORDY AK10
2
AL10
1 33_0402_5%AF12
15K_0402_5%

PCI

PCI_CBE#[3..0]

IDE_DREQ_P
IDE_INTR_P
IDE_RDY_P
IDE_IOR_P#
CABLE_DET_P/GPIO_63

EC_PME#

EC_PME# (27,28)

+3VS

RP2

PCI_DEVSEL# (23)
PCI_FRAME# (23)
PCI_IRDY# (23)
PCI_PAR (23)
PCI_PERR# (23)
PCI_SERR# (23)
PCI_STOP# (23)

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

PCI_RESET0#

J9

R30

2 33_0402_5%

PCI_RST1394# (23)

PCI_RESET1#

K9

R33

2 33_0402_5%

PCIRST_IDE# (21)

PCI_RESET2#

K8

PAD

T4

PCI_RESET3#

L9

PAD

T5

PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN

C9
B9
B8
A8
C8
D8

1
2
3
4

LPC_DRQ#0 R38
LPC_DRQ#1 R72
SERIRQ
R36

8
7
6
5
8.2K_1206_8P4R_5%
@
2 8.2K_0402_5% @
2 8.2K_0402_5% @
2 10K_0402_5% @

1
1
1

CLK_PCI_LPC_R

1 C37
10P_0402_50V8J
@

CLK_PCI_1394_R

R40

2 22_0402_5%

PCI_CLK4
PCI_CLKIN

R46

2 22_0402_5%

JP35

1
3

9/20 Added

LPC

IDE

LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#

D7
B3

LPC_RESET#

C7

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_CLK0

A4
B4
C4
A3
B5

LPC_CLK1

C5

CLK_PCI_1394 (23)

1 C31
1
10P_0402_50V8J
C30
10P_0402_50V8J
2
2

LPC_DRQ1#/GPIO19/FANRPM1
LPC_DRQ0#/GPIO_50

IDE_DATA_P0
IDE_DATA_P1
IDE_DATA_P2
IDE_DATA_P3
IDE_DATA_P4
IDE_DATA_P5
IDE_DATA_P6
IDE_DATA_P7
IDE_DATA_P8
IDE_DATA_P9
IDE_DATA_P10
IDE_DATA_P11
IDE_DATA_P12
IDE_DATA_P13
IDE_DATA_P14
IDE_DATA_P15

SN74AHCT1G125DCKR_SC70-5
@

(23)

PCI_TRDY#

LPC_SERIRQ
LPC_CLKRUN/GPIO_42

PAD

R329 1

2 22_0402_5%LPC_FRAME#

LPC_FRAME# (14,27,28)

R54

2 33_0402_5%

PLT_RST# (27,28)

1
1
1
1
1

2
2
2
2
2

T6

R333
R328
R335
R311
CLK_PCI_LPC_R R59

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%

IDE_ADDR_P0
IDE_ADDR_P1
IDE_ADDR_P2

AG12
AE12
AH12

IDE_A0
IDE_A1
IDE_A2

IDE_CS1_P#
IDE_CS3_P#
IDE_DACK_P#

AJ12
AK12
AJ11

IDE_CS1#
IDE_CS3#
IDE_DACK#

IDE_CS1# (21)
IDE_CS3# (21)
IDE_DACK# (21)

IDE_IOW_P#

AJ10

IDE_IOW#

IDE_IOW# (21)

IDE_COMP_3P3V
IDE_COMP_GND

AM4
AK4

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_AD0 (27,28)
LPC_AD1 (27,28)
LPC_AD2 (27,28)
LPC_AD3 (27,28)
CLK_PCI_LPC (27,28)

IDE_A0 (21)
IDE_A1 (21)
IDE_A2 (21)

NC
NC

NC
NC

Debug Port

2
4

PCI_CBE#0

CLK0

CLK1

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

7
9
11
13
15
17
19
21

A3<7>
A3<6>
A3<5>
A3<4>
A3<3>
A3<2>
A3<1>
A3<0>

A1<7>
A1<6>
A1<5>
A1<4>
A1<3>
A1<2>
A1<1>
A1<0>

8
10
12
14
16
18
20
22

PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8

PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16

23
25
27
29
31
33
35
37

A2<7>
A2<6>
A2<5>
A2<4>
A2<3>
A2<2>
A2<1>
A2<0>

A0<7>
A0<6>
A0<5>
A0<4>
A0<3>
A0<2>
A0<1>
A0<0>

24
26
28
30
32
34
36
38

PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

39
40
41
42
43

GND
GND
GND
GND
GND

+3VS

R29
121_0402_1%

S W-CONN AMP 2-767004-2 38P


@

8
7
6
5

U32

1
2
3
4

Internal PU

RP6
+3VS

PCI_PME#

PCI_GNT#0 (23)

OE#

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

8
7
6
5

1
2
3
4

+3VS

RP3

MCP67-MV_PBGA836

R51
121_0402_1%

9/21 Add 33ohm for IDE_IOR#

Compal Secret Data

Security Classification
Issued Date

2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

MCP67 PCI/ LPC/ IDE


Size Document Number
Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

13

of

42

PLACE SATA AC COUPLING


CAPS CLOSE TO MCP67
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0

(21) SATA_STX_C_DRX_P0
(21) SATA_STX_C_DRX_N0

2 C512
C511
2

MCP67
PAR 5 OF 8

SATA_STX_DRX_P0
SATA_STX_DRX_N0

AE4
AE5
AG5
AG6

SATA2@
0.01U_0402_16V7K
1
2 C514
0.01U_0402_16V7K 1
C513
2

SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1

(21) SATA_STX_C_DRX_P1
(21) SATA_STX_C_DRX_N1

SATA_DTX_C_SRX_N1
SATA_DTX_C_SRX_P1

(21) SATA_DTX_C_SRX_N1
(21) SATA_DTX_C_SRX_P1

SATA_A0_TX_P
SATA_A0_TX_N
SATA_A0_RX_N
SATA_A0_RX_P

AD1
AD2

SATA_A1_TX_P
SATA_A1_TX_N

AE2
AE3

SATA_A1_RX_N
SATA_A1_RX_P

SATA
SATA_STX_DRX_P1
SATA_STX_DRX_N1

SATA2@

AG4
AG3

SATA_B0_TX_P
SATA_B0_TX_N

AH3
AH2

SATA_B0_RX_N
SATA_B0_RX_P

USB

+3VS

JUMPER
@

10K_0402_5%
HDA_SDOUT_ICH
2
10K_0402_5% @
2
10K_0402_5%
LPC_FRAME#
2

LPC_FRAME# (13,27,28)

AG7
AG8

SATA_B1_TX_P
SATA_B1_TX_N

AF2
AF3

SATA_B1_RX_N
SATA_B1_RX_P

LPC_FRAME

10K_0402_5%
2

HDA_SDOUT

R320
1
R319
1
R44
1
R41
1

"0"

"0"

LPC BIOS*

"0"

"1"

PCI BIOS

"1"

"0"

SPI BIOS

AJ1
AJ2

RESERVED/SATA_C1_TX_P
RESERVED/SATA_C1_TX_N

"1"

"1"

RESERVED

AK1
AK2

RESERVED/SATA_C1_RX_N
RESERVED/SATA_C1_RX_P

FUNCTION
AL1
AL2

RESERVED/SATA_C0_TX_P
RESERVED/SATA_C0_TX_N

AK3
AL3

RESERVED/SATA_C0_RX_N
RESERVED/SATA_C0_RX_P

+3VS

R35
10K_0402_5%
2

*DEFAULT
AJ4

2
2.49K_0402_1%
SATA_LED#

(27,28) SATA_LED#

+3VS

USB0_P
USB0_N

U3
U2

USB1_P
USB1_N

U4
U5

USB2_P
USB2_N

U6
U7

USB3_P
USB3_N

V3
V2

USB4_P
USB4_N

W4
W3

USB5_P
USB5_N

W5
W6

USB6_P
USB6_N

W7
W8

USB7_P
USB7_N

Y2
Y3

USB8_P
USB8_N

AA3
AA2

USB9_P
USB9_N

AA5
AA4

RESERVED/USB10_P
RESERVED/USB10_N

AA7
AA6

RESERVED/USB11_P
RESERVED/USB11_N

AB3
AB2

RESERVED
RESERVED

AC3
AC4

USB_RBIAS_GND

1
R108

SATA_LED#

U23E

SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0

(21) SATA_DTX_C_SRX_N0
(21) SATA_DTX_C_SRX_P0

0.01U_0402_16V7K
1
0.01U_0402_16V7K 1

D4

T1

SATA_TERMP
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27
USB_OC3#/GPIO_28/MGPIO_1
USB_OC4#/GPIO_29/MGPIO_3

SATA_LED#/GPIO_57

USB20_P0
USB20_N0
1
R343

2
15K_0402_5%

1
R346

2
15K_0402_5%

1
R342

2
15K_0402_5%

1
R341

2
15K_0402_5%

1
R84

2
15K_0402_5%

1
R80

2
15K_0402_5%

1
R345

2
15K_0402_5%

1
R348

2
15K_0402_5%

USB20_P1
USB20_N1

USB20_P3
USB20_N3
USB20_P4
USB20_N4
USB20_P5
USB20_N5

1
2
R344
15K_0402_5%
CMOS@

1
R353

2
15K_0402_5%

1
R357

1
2
R360
15K_0402_5%
MINI1@

1
R358

1
2
R352
15K_0402_5%
MINI2@

1
2
R355
15K_0402_5%
MINI2@

1
2
R350
15K_0402_5%
EXPRESS@

1
2
R356
15K_0402_5%
EXPRESS@

1
R351

1
R354
@

USB20_P6
USB20_N6
USB20_P7
USB20_N7
USB20_P8
USB20_N8
USB20_P9
USB20_N9

HDA_BITCLK_ICH_R

CLKIN

NC

VDD

CLKOUT

NC

SSON

SS

GND

R459
10K_0402_5%
@

W13
V13

+1.2V_PLL_SP_VDD
+1.2VS
HDA_BITCLK_ICH
1
C640
0.1U_0402_16V4Z
2

+3.3V_USB_DUAL1
+3.3V_USB_DUAL2

2 C140
0.1U_0402_16V4Z

R13

+3.3V_PLL_SP_SS

P13

+3.3V_PLL_LEG

ASM3P623S00CF-08TR_TSSOP8
@

HDA_BITCLK_ICH_R 1
R461

+1.2VS

+3VS

C149
0.1U_0402_16V4Z

2 C50
0.1U_0402_16V4Z

L14 1
2
MBK1608121YZF_0603

C54
10U_0805_10V4Z

C143
0.1U_0402_16V4Z

NEW CARD
C

NON-USE

R87
1
R338
1.1K_0402_1%

T2
T3
T4
T5
T6

USB_OC#4
10K_0402_5%
USB_OC#3
10K_0402_5%
2 HDA_RST_ICH#
10K_0402_5%

1
R316

2
+3V

1
R313

USB_OC#0 (26)
USB_OC#1 (25)
CP_PE# (11,26)
USB_OC#3
USB_OC#4

C57
0.1U_0402_16V4Z

HDA_SYNC_ICH
10K_0402_5%

C63
0.1U_0402_16V4Z

Y8
Y9

HDA_BITCLK

D2

HDA_SDATA_OUT/GPIO_45

B1

HDA_SDOUT_ICH
1
22_0402_5%

HDA_SDATA_IN0/GPIO_22
HDA_SDATA_IN1/GPIO_23/MGPIO_0
HDA_SDATA_IN2/GPIO_24/MGPIO_2

B2
A2
D1

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2

HDA_RESET#

C2

HDA_RST_ICH#
1
22_0402_5%

2
R315

HDA_SYNC/GPIO_44

C1

HDA_SYNC_ICH
1
22_0402_5%

2
R312

HDA_DOCK_EN#/GPIO_51
HDA_DOCK_RST#/GPIO_46

D3
C3

HDA

HDA_BITCLK_ICH
1
33_0402_5%

2
R318

2
R314

HDA_SDOUT_MDC
HDA_SDIN0
HDA_SDIN1

HDA_BITCLK_MDC

(30)

HDA_BITCLK_ICH
HDA_SYNC_ICH
HDA_RST_ICH#
HDA_SDOUT_ICH

(30)

(32)
(30)

C23
C17
10P_0402_50V8J 10P_0402_50V8J
1 @
1 @
1 C22
1

HDA_RST_MDC# (30)
2
HDA_SYNC_MDC

(30)

HDA_BITCLK_ICH
1
33_0402_5%
HDA_SYNC_ICH
1
22_0402_5%
HDA_RST_ICH#
1
22_0402_5%
HDA_SDOUT_ICH
1
22_0402_5%

MCP67-MV_PBGA836

C145
4.7U_0805_10V4Z

L10 1
2
MBK1608121YZF_0603
1

+3.3V_PLL

MINI2

USB20_P9
USB20_N9

R86

HDA_BITCLK_ICH_R

HDA_BITCLK_ICH
0_0402_5%

+1.2V_PLL_SP_VDD

MINI1

USB20_P8 (26)
USB20_N8 (26)

R460
10K_0402_5%
@

BLUETOOTH

+1.2V_PLL_SP_VDD
+1.2V_PLL_SP_SS

1
+3.3V_PLL

USB CAMERA

USB20_P7 (25)
USB20_N7 (25)

2
15K_0402_5%

U36

USB/B
Connector

+3V

+3VS

USB20_P3 (25)
USB20_N3 (25)

USB20_P6 (25)
USB20_N6 (25)

2
15K_0402_5%
MINI1@

2
15K_0402_5%

USB/B
Connector

USB20_P5 (30)
USB20_N5 (30)

BT@

USB20_P2 (25)
USB20_N2 (25)

USB20_P4 (20)
USB20_N4 (20)

2
15K_0402_5%

BT@

USB PORT_1

USB20_P1 (26)
USB20_N1 (26)

USB20_P2
USB20_N2

1
2
R347
15K_0402_5%
CMOS@

USB PORT_1

USB20_P0 (26)
USB20_N0 (26)

2
R25
2
R23
2
R26
2
R27

2
2 C20
10P_0402_50V8J 10P_0402_50V8J

HDA_BITCLK_AUDIO

(32)

HDA_SYNC_AUDIO

(32)

HDA_RST_AUDIO#

(32)

HDA_SDOUT_AUDIO

(32)

2
C153
0.1U_0402_16V4Z

Compal Secret Data

Security Classification

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

MCP67 SATA/ USB/ HDAUDIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

14

of

42

+3V

R469

+3V

R470

2 CRT_DET
10K_0402_5%

CRT_DET
R445

+3VS

U23F

RI#
@

M4
R283
470K_0402_5%
@

GPIO_12/SUS_STAT#

MSIC

+RTCVCC

MP Modify 2007/04/12

R340
1M_0402_5%
(27,28) EC_GA20
(27,28) EC_KBRST#
(27,28) EC_SCI#
(27,28) EC_SMI#

2 0_0402_5%
2 0_0402_5%

1
1

R93
49.9K_0402_1%

R463
CRT_DET
1

(19) CRT_DET

R91
R96

0_0402_5%
LID#
2
LLB#
C29
1U_0603_10V4Z
1
2

K7
K6
M6
P4
P8
L3

P5
N10

A20GATE/GPIO_55
KBRDRSTIN#/GPIO_56
SIO_PME#/GPIO_31
EXT_SMI#/GPIO_32
RI#/GPIO33
INTRUDER#

(27,28) PBTN_OUT#
+3V

Close To RAM Door


J1

R90

1
@ JOPEN
(27,28)
(6,18,27,28)
(31,40)
(11,31)
(41)

C60
1U_0603_10V4Z
1
2

EC_RSMRST#

EC_RSMRST#
MCP_PWRGD
MEM_VLD
HT_VLD
VGATE

MEM_VLD
HT_VLD

2
10K_0402_5%2
10K_0402_5%

1
1

XTALIN
XTALOUT

R81
R95

MCP_SPKR

SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT#/GPIO_64

E3
G3
E2
F2
F3

SMBCLK1
SMBDATA1
M_SMBCLK
M_SMBDATA
SMB_ALERT#

THERM#/GPIO_59

K5

RTC_RST#

2
10K_0402_5%
2
10K_0402_5%

PM_SLP_S5# (27,28)

MCP_SPKR (32)

Q10
2N7002_SOT23
M_SMBCLK

SMBCLK1 (25,26)
SMBDATA1 (25,26)

MEM_SMBCLK

MEM_SMBCLK (8,9)

+3VS

M_SMBDATA

EC_THERM# (6,27,28)

PWRGD_SB
PWRGD
MEM_VLD
MCP_VLD/HT_VLD
CPU_VLD

AC14
AB14
AD12

FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANCTL1/GPIO_62

F6
F5
F4

MCPVDD_EN/HTVDD_EN
CPUVDD_EN

N3
M2

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9

K2
K3
M7
J2

SUS_CLK/GPIO_34

P2

BUF_SIO_CLK

J3

+3V

2
15K_0402_5%

R65
R70
R34

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
JTAG_TCK

ACIN_L

D29
RB751V_SOD323
2
1
R74
R56

VLDT_EN (34)
VR_ON (41)

R73
R60

R339

XTALIN
XTALOUT

+3VS

SMBCLK1
2.7K_0402_5%
SMBDATA1
2.7K_0402_5%
2 SMB_ALERT#
2.7K_0402_5%

1
1

M_SMBCLK
2.7K_0402_5%
M_SMBDATA
2.7K_0402_5%

ACIN (18,27,28,37)
2
10K_0402_5%
2
10K_0402_5%

MEM_SMBDATA (8,9)

2N7002_SOT23
Q9

CPU_SIC (6)
CPU_SID (6)

1
R438

MEM_SMBDATA

@
+3V

2
10K_0402_5%

1
R543

ACIN_L
2
470K_0402_5%

MP Modify 2007/04/12

25MHZ_20P
C34
27P_0402_50V8J

C35
27P_0402_50V8J

C503
18P_0402_50V8J
2
1

XTALIN_RTC
@

X2
2
3

NC

IN

NC

OUT

32.768KHZ_12.5P_MC-306
2
1

R334
10M_0402_5%
1
2

M5

H4
H3

X1
1

PWRBTN#
RSTBTN#

U9
T8
T7
U8
T9

K4

THERM_SIC/GPIO_48
THERM_SID0/GPIO_49
THERM_SID1/GPIO_47/PWR_LED#

R10
P9

L4
T10
M8
P7
M3

SPKR

R104

SLP_RMGT# (12,22)

LID#
LLB#

PVT Modify 2007/03/12


PBTN_OUT#
1 RSTBTN#
10K_0402_5%

H5
H6
H7

H2
H1

1 C16
10P_0402_50V8J
@

XTALIN_RTC
XTALOUT_RTC

TEST_MODE_EN

P11

PKG_TEST

P10

MCP67-MV_PBGA836

XTAOUT_RTC

R71
0_0402_5%
2

18P_0402_50V8J
C504

+3VS

R540
1
R541
1

2.2K_0402_5%
2 MEM_SMBCLK
2.2K_0402_5%
2 MEM_SMBDATA

9/25 Added for EMI


1

EC_GA20
EC_KBRST#
SIO_PME#
EXT_SMI#
RI#
SM_INTRUDER#

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15

PM_SLP_S3# (27,28)

0_0402_5%

R3
P3
R4

R101
PM_SLP_S3#
SLP_RMGT#
PM_SLP_S5#

SLP_S3#
SLP_RMGT#
SLP_S5#

R464

GPIO_1/PWRDN_OK/SPI_CS1
GPIO_2/NMI/PS2_CLK0
GPIO_3/SMI#/PS2_DATA0
GPIO_4/SCI/INTR/PS2_CLK1
GPIO_5/INIT#/PS2_DATA1

2
G

EC_LID_OUT#

(27,28) EC_LID_OUT#

1
1

P6
N11
R11
M9
M10

2
G

2
R542
@

R92
R97

IDE_HRESET#
2 0_0402_5%
2 0_0402_5%

(21) IDE_HRESET#
@
(27,28) EC_SWI#
D24
(27,28) EC_SMI#
RB751V_SOD323
ACIN_R
1
2
1
20K_0402_1%

MCP_SPKR

MCP67
PAR 6 OF 8

(18,27,28,37) ACIN

+3V

1
@ 100K_0402_5%

LID#
2
100K_0402_5%
LLB#
2
10K_0402_5% @

R53

2 EC_LID_OUT#
10K_0402_5% @

PVT Modify 2007/03/23

R100
1K_0402_1%
2

R78

Compal Secret Data

Security Classification

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

MCP67 MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

15

of

42

C152
10U_0805_10V4Z

C527
4.7U_0805_10V4Z

C73
0.1U_0402_16V4Z

C100
0.1U_0402_16V4Z

C114
0.1U_0402_16V4Z

U23G

MCP67
PART 7 OF 8

C39
0.01U_0402_16V7K

R77
0_0603_5%
2

2
2
C102
0.1U_0402_16V4Z

2
2
C110
0.1U_0402_16V4Z

2
2
C47
0.1U_0402_16V4Z

C45
0.1U_0402_16V4Z

C506
0.1U_0402_16V4Z

L6
L8

+3.3V_DUAL1
+3.3V_DUAL2

N2

+3.3V_VBAT

RTC Battery

BATT1
2

+RTCBATT

+RTCBATT

Update Footprint
1

ML1220T13RE
45@

R539
1K_0402_1%

PVT Modify 2007/03/22


D22
BAS40-04_SOT23-3
2

+RTCVCC

+CHGRTC
B

MCP67-MV POWER STATES

+3.3V1
+3.3V2
+3.3V3
+3.3V4

2
2
C41
0.1U_0402_16V4Z

Power Signal

AJ9
AG9
F11
H11

S4/S5

POWER

+3.3V_DUAL1
+RTCVCC

+1.2V_RBB1
+1.2V_RBB2
+1.2V_RBB3
+1.2V_RBB4

1
C519
4.7U_0805_10V4Z

C520
0.1U_0402_16V4Z

AD9
AH6
AE32
Y32
AD8
M32
AE18
AB25
AB27
U15
AE11
V27
R27
N27
G27
Y14
F15
V29
AC12
AB19
AM9
AB12
AM8
AF8
AH4
E27
AM31
F22
AF4
AM32
AG11
L15
AD27
P22
AD11
V11
L23
P15

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+1.2V1
+1.2V10
+1.2V11
+1.2V12
+1.2V13
+1.2V14
+1.2V15
+1.2V16
+1.2V17
+1.2V18
+1.2V19
+1.2V2
+1.2V20
+1.2V21
+1.2V22
+1.2V23
+1.2V24
+1.2V25
+1.2V26
+1.2V27
+1.2V28
+1.2V29
+1.2V3
+1.2V4
+1.2V5
+1.2V6
+1.2V7
+1.2V8
+1.2V9

AA22
V19
W20
Y20
Y19
V17
AB21
AA23
Y30
U17
U18
Y31
W17
Y18
U16
AA24
V18
AA25
AA26
AB22
W18
AB23
AA27
AA28
AA29
W19
AA30
AA31
V20

+1.2V_HT1
+1.2V_HT2
+1.2V_HT3

Y15
Y17
Y16

+1.2V_PED1
+1.2V_PED2
+1.2V_PED3
+1.2V_PED4
+1.2V_PED5

V23
W25
W24
V22
W26

+1.2V_PEA1
+1.2V_PEA2
+1.2V_PEA3
+1.2V_PEA4
+1.2V_PEA5
+1.2V_PEA6
+1.2V_PEA7
+1.2V_PEA8

Y22
Y23
Y27
Y29
Y25
W22
W23
Y24

+1.2V_SP_D1
+1.2V_SP_D2
+1.2V_SP_D3
+1.2V_SP_D4

AE8
AE7
AE9
AE6

+1.2V_SP_A1
+1.2V_SP_A2
+1.2V_SP_A3
+1.2V_SP_A4
+1.2V_SP_A5

AB11
AB10
AD10
AC10
AE10

+1.2V_DUAL1
+1.2V_DUAL2

N16
N17

C526
150U_D2_6.3VM
1
1
+
2

C151
22U_0805_6.3V6M

C159
4.7U_0805_10V4Z

C130
0.1U_0402_16V4Z

C135
0.1U_0402_16V4Z

+1.2VS

R102
0_0603_5%

C106
0.1U_0402_16V4Z
+1.2V_HT1

C139
0.1U_0402_16V4Z

C144
0.1U_0402_16V4Z

+1.2VS

1 C529
150U_D2_6.3VM
+@

1 C67
1U_0402_6.3V4Z

C121
0.1U_0402_16V4Z

C124
0.1U_0402_16V4Z

2
2
C112
0.1U_0402_16V4Z

2
C

+1.2VS
L17
KC FBM-L11-201209-221LMAT_0805

+1.2V_PED
+1.2V_PEA

C117
0.1U_0402_16V4Z

C128
0.1U_0402_16V4Z

C156
4.7U_0805_10V4Z

2
2
C123
0.1U_0402_16V4Z

+1.2V_SP_D
C68
1
1
0.01U_0402_16V7K
2

C111
1
1
10U_0805_10V4Z

2
2
C62
0.1U_0402_16V4Z

2
2
C157
22U_0805_6.3V6M

2
C162
10U_0805_10V4Z

C71
1
1
0.1U_0402_16V4Z

+1.2VS

2
C116
10U_0805_10V4Z

R110
0_0805_5%

C189
10U_0805_10V4Z
1
1

2
2
C126
1U_0402_6.3V4Z

C119
1
1
10U_0805_10V4Z

2
2
C72
0.1U_0402_16V4Z

2
C118
4.7U_0805_10V4Z
B

+1.2V_SP_A
C75
1
1
0.1U_0402_16V4Z

L12 1
C518
1
1
4.7U_0805_10V4Z

2
2
C64
0.1U_0402_16V4Z

2 MBK2012121YZF_0805

2
C516
4.7U_0805_10V4Z

S0

S1

S3

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

C59

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

0.1U_0402_16V4Z
1

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

ON

ON

OFF OFF

OFF

+1.2VALW

C56
0.1U_0402_16V4Z

Compal Secret Data

Security Classification

2006/08/18

Issued Date

2007/8/18

Deciphered Date

Title

MCP67 POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

+1.2V_HT

2
MCP67-MV_PBGA836

G3

C48
0.1U_0402_16V4Z

C107
0.1U_0402_16V4Z

V15
V16
W16
W15

+3VS

C525
C74
C108
C109
C120
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C147
C125
C132
C131
C134
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+3V

+1.2VS

Size Document Number


Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P
Sheet

Friday, April 20, 2007


1

16

of

42

U23H

MCP67
PAR 8 OF 8
AB9
AC6
AC8
AA8
AD3
AD4
AA9
AC5
AC9

L11
V8
H13
N6
AA1
AD13
K23
AM16
AH1
U13
R6
R8
M1
N1
U1
J1
J4
J6
Y13
AE1
Y6
A5
A12
N8
E6
AC11
H15
T17
J21
D18
A20
N4
G6
AG22
P16
T19
AE24
AJ26
AJ24
U32
T20
AM24
AF29
AJ13
AA32
AG13
AE15
F13
AF6
AB4
AG15
E25
AM17
R15
A17
AG24
N20
N24
AM1
AM21
A21
V25
AJ3
L25
P17
H18
L24
AM5
U14
AC16
U10
N29
AM2
AM3

WUSB_VREF
WUSB_CCA_STATUS
WUSB_SERIAL_DATA
WUSB_PHY_RESET*
WUSB_TX_EN
WUSB_RX_EN
WUSB_PHY_ACTIVE
WUSB_STOPC
WUSB_VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

WUSB_PCLK
WUSB_DATA_EN
WUSB_DATA7
WUSB_DATA6
WUSB_DATA5
WUSB_DATA4
WUSB_DATA3
WUSB_DATA2
WUSB_DATA1
WUSB_DATA0

AC7
AB8
V9
W11
W10
W9
Y11
Y10
AA11
AA10

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

R18
H9
R17
A1
D9
AG26
G4
AB6
J25
R25
T16
T15
J29
W14
AD6
AB24
AM13
R16
V6
A13
N32
AM25
F9
N9
AL31
G25
AB18
AH32
D13
N25
A25
R9
R14
AF27
AH8
A32
P14
E29
E32
V10
J23
N14
AB29
E4
AE13
L27
J27
A9
J32
AE20
AJ22
AG18
AG20
V14
F18
F20
D20
E1
V4
J8
F7
T18
J24
A31
Y1
T13
D22
Y4
P18
AJ18
AE22
R24
N19
T14

GROUND

MCP67-MV_PBGA836

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

MCP67 GROUND
Size Document Number
Custom

Rev
1.0

ICW50 / ICY70 LA-3581P

Date:

Sheet

Friday, April 20, 2007


1

17

of

42

1
2
R125
0_0402_5%
2 VGA@
C182
0.1U_0402_16V4Z
VGA@
1

PCIE_MTX_C_GRX_N[0..15]

(11) PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

(11) PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

(11) PCIE_GTX_C_MRX_N[0..15]
D

MCP_PWRGD (6,15,27,28)

PCIE_GTX_C_MRX_P[0..15]

(11) PCIE_GTX_C_MRX_P[0..15]

1
R122
0_0402_5%

L18
JP19A
KC FBM-L11-201209-221LMAT_0805
VGA@
1
2
1 PWR_SRC
B+
VGA@
3 PWR_SRC
1
2
5 PWR_SRC
7 PWR_SRC
9 PWR_SRC
9/25 Added for EMI
11 PWR_SRC
13 PWR_SRC
L21
15
KC FBM-L11-201209-221LMAT_0805 17 PWR_SRC
GND
19 GND
21 GND
23 GND

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
RUNPWROK
5VRUN
GND
GND
GND

2
4
6
8
10
12
14
16
18
20
22
24

25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107

PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5

PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2

PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
PEX_RX2#
PEX_RX2
GND

PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2

VGA_ON (27)
JP19B

+1.8VS

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
CLK_PCIE_VGA#
CLK_PCIE_VGA

(11) CLK_PCIE_VGA#
(11) CLK_PCIE_VGA
+5VS
(11,26) PCIE_RST#

1
@

PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15

2
@

PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1

(27,28) MXM_THERM#

26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108

D_EC_SMB_DA1
D_EC_SMB_CK1
MXM_THERM_R
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA

R515
0_0402_5%

PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15

(19) VGA_CRT_HSYNC
(19) VGA_CRT_VSYNC
(19) VGA_DDC_CLK
(19) VGA_DDC_DATA

PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14

1
R516
0_0402_5%
@

(15,27,28,37) ACIN

PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
(20) DVI_DET
(20) VGA_DVI_TXC(20) VGA_DVI_TXC+

DVI_DET
VGA_DVI_TXCVGA_DVI_TXC+

PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4

(20) VGA_DVI_TXD2(20) VGA_DVI_TXD2+

VGA_DVI_TXD2VGA_DVI_TXD2+

PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3

(20) VGA_DVI_TXD1(20) VGA_DVI_TXD1+

VGA_DVI_TXD1VGA_DVI_TXD1+

PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2

(20) VGA_DVI_TXD0(20) VGA_DVI_TXD0+

VGA_DVI_TXD0VGA_DVI_TXD0+

PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5

109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229

PEX_RX1#
GND
PEX_RX1
PEX_TX1#
GND
PEX_TX1
PEX_RX0#
GND
PEX_RX0
PEX_TX0#
GND
PEX_TX0
PEX_REFCLK#
PRSNT1#
PEX_REFCLK
TV_C/HDTV_Pr
CLK_REQ#
GND
PEX_RST#
TV_Y/HDTV_Y
RSVD
GND
RSVD
TV_CVBS/HDTV_Pb
SMB_DAT
GND
SMB_CLK
VGA_RED
THERM#
GND
VGA_HSYNC
VGA_GRN
VGA_VSYNC
GND
DDCA_CLK
VGA_BLU
DDCA_DAT
GND
IGP_UCLK#
LVDS_UCLK#
IGP_UCLK
LVDS_UCLK
GND
GND
RSVD
LVDS_UTX3#
RSVD
LVDS_UTX3
RSVD
GND
IGP_UTX2#
LVDS_UTX2#
IGP_UTX2
LVDS_UTX2
GND
GND
IGP_UTX1#
LVDS_UTX1#
IGP_UTX1
LVDS_UTX1
GND
GND
IGP_UTX0#
LVDS_UTX0#
IGP_UTX0
LVDS_UTX0
GND
GND
IGP_LCLK#/DVI_B_CLK#
LVDS_LCLK#
IGP_LCLK/DVI_B_CLK
LVDS_LCLK
DVI_B_HPD/GND
GND
RSVD
LVDS_LTX3#
RSVD
LVDS_LTX3
GND
GND
IGP_LTX2#/DVI_B_TX2#
LVDS_LTX2#
IGP_LTX2/DVI_B_TX2
LVDS_LTX2
GND
GND
IGP_LTX1#/DVI_B_TX1#
LVDS_LTX1#
IGP_LTX1/DVI_B_TX1
LVDS_LTX1
GND
GND
IGP_LTX0#/DVI_B_TX0#
LVDS_LTX0#
IGP_LTX0/DVI_B_TX0
LVDS_LTX0
DVI_A_HPD
GND
DVI_A_CLK#
DDCC_DAT
DVI_A_CLK
DDCC_CLK
GND
LVDS_PPEN
DVI_A_TX2#
LVDS_BL_BRGHT
DVI_A_TX2
LVDS_BLEN
GND
DDCB_DAT
DVI_A_TX1#
DDCB_CLK
DVI_A_TX1
2V5RUN
GND
GND
DVI_A_TX0#
3V3RUN
DVI_A_TX0
3V3RUN
GND
3V3RUN

110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230

PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
PE_PRSNTX16#
VGA_TV_CRMA

PE_PRSNTX16# (11)
VGA_TV_CRMA (19)

VGA_TV_LUMA

VGA_TV_LUMA (19)

VGA_TV_COMPS

VGA_TV_COMPS (19)

VGA_CRT_R

VGA_CRT_R (19)

VGA_CRT_G

VGA_CRT_G (19)

VGA_CRT_B

VGA_CRT_B (19)

VGA_TZCLKVGA_TZCLK+

VGA_TZCLK- (20)
VGA_TZCLK+ (20)

VGA_TZOUT2VGA_TZOUT2+

VGA_TZOUT2- (20)
VGA_TZOUT2+ (20)

VGA_TZOUT1VGA_TZOUT1+

VGA_TZOUT1- (20)
VGA_TZOUT1+ (20)

VGA_TZOUT0VGA_TZOUT0+

VGA_TZOUT0- (20)
VGA_TZOUT0+ (20)

VGA_TXCLKVGA_TXCLK+

VGA_TXCLK- (20)
VGA_TXCLK+ (20)

VGA_TXOUT2VGA_TXOUT2+

VGA_TXOUT2- (20)
VGA_TXOUT2+ (20)

VGA_TXOUT1VGA_TXOUT1+

VGA_TXOUT1- (20)
VGA_TXOUT1+ (20)

VGA_TXOUT0VGA_TXOUT0+

VGA_TXOUT0- (20)
VGA_TXOUT0+ (20)

I2CC_SDA
I2CC_SCL
ENVDD

I2CC_SDA (20)
I2CC_SCL (20)
ENVDD (20)

ENBKL
VGA_DVI_SDATA
VGA_DVI_SCLK

ENBKL (12,27,28)
VGA_DVI_SDATA (20)
VGA_DVI_SCLK (20)

+2.5VS
+3VS

ACES_88990-2D08
ACES_88990-2D08

VGA@

+3VS

+2.5VS

+5VS

4.7U_0805_10V4Z
VGA@ 2

1
C142

C522

0.1U_0402_16V4Z
2 VGA@

4.7U_0805_10V4Z
VGA@ 2

1
C524

0.1U_0402_16V4Z
2 VGA@

0.1U_0402_16V4Z
2 VGA@

C523

D_EC_SMB_DA1

Q54
VGA@ 2N7002_SOT23

C146

2
G

C206
0.1U_0603_25V7K
VGA@

(27,28,29,37) EC_SMB_DA1
C150

0.1U_0402_16V4Z
2 VGA@
(27,28,29,37) EC_SMB_CK1

3
S

C651
10U_1206_25V6M
VGA@

+3VS

+1.8VS

C652
10U_1206_25V6M
@

B+

B+

B+

2
G

VGA@

VGA@

PVT Modify 2007/03/22

D_EC_SMB_CK1
A

Q55
2N7002_SOT23

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Issued Date

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

MXM Connector
Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
1

18

of

42

CRT Connector

D15

D14

W=40mils

D13

+5VS

+R_CRT_VCC

+CRT_VCC

D1

DAN217_SC59 DAN217_SC59 DAN217_SC59


F1

R8
R6

(18) VGA_CRT_B
(12) UMA_CRT_B

R5

1
1
1
1

2 VGA@ 0_0402_5%
2
UMA@ 0_0402_5%
2 VGA@ 0_0402_5%
2
UMA@ 0_0402_5%
2 VGA@ 0_0402_5%
2
UMA@ 0_0402_5%

CRT_R
L42
CRT_G
L41
CRT_B
R304

C499
10P_0402_50V8J
1
1

(18) VGA_CRT_G
(12) UMA_CRT_G

1
1

R10
R9

R14

R303
R302

C3
0.1U_0402_16V4Z
2

L40

CRT_R_1
2
FCM2012C-800_0805

1
1

CRT_G_1
2
FCM2012C-800_0805

CRT_B_1
2
FCM2012C-800_0805

JP14

C498
C496
C495
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J
2
2
2

150_0402_1%
C497
10P_0402_50V8J

1
+CRT_VCC

2
R297

CRT_HSYNC_2
2
FCM1608C-121T_0603

C2
470P_0402_50V7K

1
L38

CRT_VSYNC_2
2
FCM1608C-121T_0603
1

CRT_HSYNC_1

C493
10P_0402_50V8K

SN74AHCT1G125DCKR_SC70-5

C491

DSUB_15

10P_0402_50V8K

2
0.1U_0402_16V4Z

CRT_VSYNC

CRT_VSYNC_1
+3VS
+CRT_VCC

SN74AHCT1G125DCKR_SC70-5

2
VGA@ 0_0402_5%
2
UMA@ 39_0402_5%

U21

1
R298
1
R299

Place closed to chipset


R11
4.7K_0402_5%
UMA@

R7
4.7K_0402_5%

R1

(18) VGA_TV_COMPS
(12) UMA_TV_COMPS

UMA@ 0_0402_5%
1

UMA_CRT_DATA (12)

2
1
R2
UMA@ 0_0402_5%

UMA_CRT_CLK (12)
3

2 R3
VGA@ 0_0402_5%

VGA_DDC_CLK (18)

2
FCM1608C-121T_0603

1
L31 TV@

2
FCM1608C-121T_0603

TV_CRMA_1
TV_COMPS_1
TV_LUMA_1

TV_COMPS

R202
TV@

R214
TV@

R220
TV@

150_0402_1%

2
FCM1608C-121T_0603

C346
1 82P_0402_50V8J
TV@

C301
1 82P_0402_50V8J
1
TV@

C337
1 82P_0402_50V8J
TV@

R4
4.7K_0402_5%
UMA@

+3VS
SUYIN_030107FR007SX08FU
TV@

150_0402_1%

1
L29 TV@

C317
1 82P_0402_50V8J
1
TV@
TV@

3
6
7
5
2
4
1
8
9

1
L33 TV@

TV_CRMA

(12) UMA_TV_CRMA

(18) VGA_TV_CRMA

VGA_DDC_DATA (18)

JP24
TV_LUMA

(12) UMA_TV_LUMA

Q1
2N7002_SOT23

+3VS
1
2
R76
VGA@ 0_0402_5%
1
2
R391 UMA&TV@ 0_0402_5%
1
2
R75
VGA@ 0_0402_5%
1
2
R393 UMA&TV@ 0_0402_5%
1
2
R83
VGA@ 0_0402_5%
1
2
R392 UMA&TV@ 0_0402_5%

1
D

DSUB_15

(18) VGA_TV_LUMA

R13
2

3
S

4.7K_0402_5%
1

Q2
2N7002_SOT23

Place closed to chipset

2 R12
VGA@ 0_0402_5%

2
G

2
DSUB_12

D6
D9
D10
@
@
@
DAN217_SC59 DAN217_SC59 DAN217_SC59

2
G

TV-OUT Conn.

+3VS

C1
470P_0402_50V7K

(12) UMA_CRT_VSYNC

(18) VGA_CRT_VSYNC

OE#

1
C490

CRT_DET (15)

C4
470P_0402_50V7K

+CRT_VCC

Place closed to chipset

SUYIN_070549FR015S208CR

U22
Y

16
17

DSUB_12

1
10K_0402_5%

CRT_HSYNC

OE#

P
(12) UMA_CRT_HSYNC

2
VGA@ 0_0402_5%
2
UMA@ 39_0402_5%

1
R301
1
R300

1
L39

2
0.1U_0402_16V4Z
5

1
C492

(18) VGA_CRT_HSYNC

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

150_0402_1%

150_0402_1%

C494
10P_0402_50V8J

2
1.1A_6VDC_FUSE
1

+3VS

Place closed to chipset


(18) VGA_CRT_R
(12) UMA_CRT_R

RB411D_SOT23

W=40mils

150_0402_1%
C335
82P_0402_50V8J

C323
82P_0402_50V8J
TV@

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CRT & TV-OUT Connector


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
E

19

of

42

LCD POWER CIRCUIT

TXOUT0TXOUT0+
TXOUT1TXOUT1+

+3VALW

+3VS

+LCDVDD

R19
100K_0402_5%

3
G

TZOUT2TZOUT2+

+LCDVDD
TZCLKTZCLK+

C500

4.7U_0805_10V4Z
2

R310
100K_0402_5%

I2CC_SCL
I2CC_SDA

0.1U_0402_16V4Z

+3VS

TXOUT1+
TXOUT1-

TXOUT0+
TXOUT0-

TXOUT2+
TXOUT2TXCLK+
TXCLK-

D16
2 RB751V_SOD323

DISPOFF#
TZOUT0+
TZOUT0-

Update Footprint

VGA_TZOUT0- (18)
VGA_TZOUT0+ (18)

TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZCLK+
TZCLK-

LCD/PANEL BD. Conn.

VGA_TZOUT1- (18)
VGA_TZOUT1+ (18)
VGA_TZOUT2- (18)
VGA_TZOUT2+ (18)
VGA_TZCLK- (18)
VGA_TZCLK+ (18)

UMA_LCD_CLK
UMA_LCD_DATA

UMA_LCD_CLK (12)
UMA_LCD_DATA (12)

UMA_TXOUT0+
UMA_TXOUT0-

UMA_TXOUT0+ (12)
UMA_TXOUT0- (12)

UMA_TXOUT1+
UMA_TXOUT1-

UMA_TXOUT1+ (12)
UMA_TXOUT1- (12)

UMA_TXOUT2+
UMA_TXOUT2-

UMA_TXOUT2+ (12)
UMA_TXOUT2- (12)

UMA_TXCLK+
UMA_TXCLK-

UMA_TXCLK+ (12)
UMA_TXCLK- (12)

UMA_TZOUT0+
UMA_TZOUT0-

UMA_TZOUT0+ (12)
UMA_TZOUT0- (12)

UMA_TZOUT1+
UMA_TZOUT1-

UMA_TZOUT2+ (12)
UMA_TZOUT2- (12)

UMA_TZCLK+
UMA_TZCLK-

UMA_TZCLK+ (12)
UMA_TZCLK- (12)

10/2 SWAP PIN

USB20_CMOS_N4
USB20_CMOS_P4

+DVI_VCC F2
1.1A_6VDC_FUSE
DVI@
2
1

L4
2
1
+LCDVDD
KC FBM-L11-201209-221LMAT_0805

TXOUT0TXOUT0+

9/25 Added for EMI

TXOUT2+
TXOUT2-

L3
4

USB20_CMOS_P4

USB20_N4

USB20_CMOS_N4

TXCLKTXCLK+
+3VS

1
2
RP37

(18) VGA_DVI_TXD1+
(18) VGA_DVI_TXD1-

(18) VGA_DVI_TXD2(18) VGA_DVI_TXD2+

DAC_BRIG
C7
INVTPWM

WCM2012F2S-900T04_0805
CMOS@

C11
DISPOFF#
C8

9/25 Added for EMI

+INVPWR_B+

DVI_TXD017
1
4
DVI_TXD0+
18
2
3
RP36
DVI@ 0_0404_4P2R_5%
DVI_TXD1+
DVI_TXD19
4
DVI_TXD1DVI_TXD1+
10
3
DVI@
0_0404_4P2R_5%
DVI_TXD21
1
4
DVI_TXD2+
2
2
3
RP38
DVI@ 0_0404_4P2R_5%
12
13

1
1
1

2
@ 220P_0402_50V7K
2
@ 220P_0402_50V7K
2
@ 220P_0402_50V7K

(18) VGA_DVI_TXC+
(18) VGA_DVI_TXC-

1
2
RP39

L2
2
1
KC FBM-L11-201209-221LMAT_0805
A

C6

C5

B+
1

C9
0.1U_0402_16V4Z

C12
10U_0805_10V4Z

0.1U_0402_16V4Z

TMDS_DATA2TMDS_DATA2+

DDC_CLOCK

TMDS_DATA3TMDS_DATA3+

DDC_DATA

20
21

TMDS_DATA5TMDS_DATA5+

C13

+5V

+5VS

R327
4.7K_0402_5%
DVI@

R331
4.7K_0402_5%
DVI@

Q44
2N7002_SOT23
DVI@
1

VGA_DVI_SCLK (18)

Q45
2N7002_SOT23
DVI@
Hot Plug Detect

16

R337
1

R336
@
100K_0402_5%

TMDS_DATA2/4 shield
TMDS_DATA1/3 shield
TMDS_DATA0/5 shield
TMDS_Clock shield

3
11
19
22

GND

15

Analog VSYNC

VGA_DVI_SDATA (18)

DVI_DET

0_0402_5%
DVI@

TMDS_Clock+
TMDS_Clock-

Shield
Shield
Shield
Shield
Shield
Shield

+3VS

DVI_DET (18)

D19
SKS10-04AT_TSMA@

SUYIN_070939FR024S531PL
DVI@

(HDQ70)

680P_0603_50V7K 68P_0402_50V8K
2
2

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

14

TMDS_DATA1TMDS_DATA1+

TMDS_DATA4TMDS_DATA4+

25
26
27
28
31
32

+LCDVDD

TMDS_DATA0TMDS_DATA0+

4
5

DVI_TXC+
23
4
DVI_TXC24
3
DVI@ 0_0404_4P2R_5%

+3VS
L1
2
1
KC FBM-L11-201209-221LMAT_0805

+DVI_VCC

JP15
(18) VGA_DVI_TXD0(18) VGA_DVI_TXD0+

Fro CMOS Cemera

DVI-D Connector

ACES_88242-4001

USB20_P4

C502
0.1U_0402_16V4Z
DVI@

TXOUT1TXOUT1+

D18
DVI@ RB411D_SOT23

2
G

2
2

W=40mils
INVT_PWM (27,28)
DPST_PWM (12,27,28)

@
0_0402_5%
R305
1
R306
1
0_0402_5%
@

(14) USB20_N4
(14) USB20_P4

INVT_PWM
0_0402_5%
0_0402_5%

2
G

TZCLKTZCLK+

2
2

TZOUT2+
TZOUT2-

(60 MIL)

DAC_BRIG (27,28)
1
R15 1
R16

TZOUT1+
TZOUT1-

DAC_BRIG
INVTPWM
DISPOFF#

TZOUT0TZOUT0+

41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

(18) I2CC_SCL
(18) I2CC_SDA

I2CC_SCL
I2CC_SDA

GND
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

+3VS

GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

UMA_TZOUT1+ (12)
UMA_TZOUT1- (12)

UMA_TZOUT2+
UMA_TZOUT2-

JP1
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

+INVPWR_B+

VGA_TXCLK- (18)
VGA_TXCLK+ (18)

4.7K_0402_5%
BKOFF#

4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%
4
3
UMA@ 0_0404_4P2R_5%

VGA_TXOUT2- (18)
VGA_TXOUT2+ (18)

C501

R307

(27,28) BKOFF#

1
2
RP56
1
2
RP41
1
2
RP53
1
2
RP43
1
2
RP45
1
2
RP55
1
2
RP47
1
2
RP49
1
2
RP51

VGA_TXOUT1- (18)
VGA_TXOUT1+ (18)

W=60mils

VGA_TXOUT0- (18)
VGA_TXOUT0+ (18)

2
G

Q3
AO3413_SOT23-3

VGA_TXOUT04
VGA_TXOUT0+
3
VGA@ 0_0404_4P2R_5%
VGA_TXOUT14
VGA_TXOUT1+
3
VGA@ 0_0404_4P2R_5%
VGA_TXOUT24
VGA_TXOUT2+
3
VGA@ 0_0404_4P2R_5%
VGA_TXCLK4
VGA_TXCLK+
3
VGA@ 0_0404_4P2R_5%
VGA_TZOUT04
VGA_TZOUT0+
3
VGA@ 0_0404_4P2R_5%
VGA_TZOUT14
VGA_TZOUT1+
3
VGA@ 0_0404_4P2R_5%
VGA_TZOUT24
VGA_TZOUT2+
3
VGA@ 0_0404_4P2R_5%
VGA_TZCLK4
VGA_TZCLK+
3
VGA@ 0_0404_4P2R_5%

R18

1
2
RP40
1
2
RP52
1
2
RP42
1
2
RP44
1
2
RP54
1
2
RP46
1
2
RP48
1
2
RP50

1
2
1K_0402_5%
1
R513
C14
1K_0402_5%
0.047U_0402_16V7K
@
2
Q39
2N7002_SOT23
1

UMA@
2 0_0402_5%
VGA@
0_0402_5%
2

R309 1

4.7U_0805_10V4Z

TZOUT1TZOUT1+

2
G
S

(18) ENVDD

TZOUT0TZOUT0+

R308 1

C10

1 2

Q4
2N7002_SOT23

(12) UMA_ENVDD

TXCLKTXCLK+

W=60mils

R17
300_0402_5%

TXOUT2TXOUT2+

Title

LVDS & DVI Connector


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
1

20

of

42

+3VS

IDE_D[0..15]

(13) IDE_D[0..15]

+3VS

C311
2 0.1U_0402_16V4Z

R216
1
4.7K_0402_5%
@
U12
2 B

IDE_A[0..2]

JP25

+5VS

R187
100K_0402_5%

IDE_IOW#
IDE_IORDY
IDE_IRQ
IDE_A1
IDE_A0
IDE_CS1#
IDE_LED#

(13) IDE_IOW#
(13) IDE_IORDY
(13) IDE_IRQ

2
(27,28) IDE_LED#

(13) IDE_CS1#

IDE_LED#

+5VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

IDE_RESET#
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0

R172 2

2
R171

+5VS
1 10K_0402_5% @
SD_CSEL
1
470_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
OCTEK_CDR-50JD1

IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_DREQ
IDE_IOR#

4.7K_0402_5%

IDE_D7

R217 1

2 10K_0402_5%

IDE_IRQ

R190 1

2 10K_0402_5%

IDE_DREQ

R209 1

2 5.6K_0402_5%

IDE_PDIAG# R219 1

2 10K_0402_5%

PCIRST_IDE#

(13) PCIRST_IDE#

@
33_0402_5%

IDE_DREQ (13)
IDE_IOR# (13)

NC7SZ08P5X_NL_SC70-5
@

R389

IDE_DACK#

IDE_RESET#

R203
IDE_IORDY

CDROM CONN

IDE_HRESET#

(15) IDE_HRESET#

(13) IDE_A[0..2]

+5VS

IDE_DACK# (13)
0.1U_0402_16V4Z

IDE_PDIAG#
IDE_A2
IDE_CS3#

IDE_CS3# (13)
+5VS

C274

10U_0805_10V4Z

1
C273

C268

80mils

2
1U_0402_6.3V4Z

C272

2
1000P_0402_50V7K

1
2
R173
100K_0402_5%
@

+5VS

80mils

If CDROM is Slave
then SD_CSEL= Floating
else SD_CSEL= Low

SATA HDD Conn.(SAS Connector)


JP27
(14) SATA_STX_C_DRX_P0
(14) SATA_STX_C_DRX_N0

1
2
3
4
5
6
7

SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

(14) SATA_STX_C_DRX_P1
(14) SATA_STX_C_DRX_N1
B

SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1

GND
HTX0+
HTX0GND
HRX0HRX0+
GND

23
24
25
26
27
28
29

GND
HTX1+
HTX1GND
HRX1HRX1+
GND

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

30
31

GND1
GND2

+3VS

0.1U_0402_16V4Z

C572
10U_0805_10V4Z

C568

C569

C571

0.1U_0402_16V4Z

2
1000P_0402_50V7K
B

+5VS
+3VS

+5VS

C567
10U_0805_10V4Z

C566
0.1U_0402_16V4Z

1
1

2
C570
150U_D2_6.3VM

C565
0.1U_0402_16V4Z

2
C564
1000P_0402_50V7K

Close to SATA HDD

OCTEK_SAS-22CA1G
SATA@

C581
(14) SATA_DTX_C_SRX_N0
(14) SATA_DTX_C_SRX_P0

SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0

1
C580
C561

(14) SATA_DTX_C_SRX_N1
(14) SATA_DTX_C_SRX_P1

2
1

SATA2@
SATA_DTX_C_SRX_N1
1
2
SATA_DTX_C_SRX_P1
1
2
C560
SATA2@

0.01U_0402_16V7K
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
0.01U_0402_16V7K
0.01U_0402_16V7K
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
0.01U_0402_16V7K

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Issued Date

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

SATA HDD & IDE ODD Connector


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
1

21

of

42

@
@
RXCLK_R

4.7K_0402_5% @
R506 4.7K_0402_5% @
LINK1000
1
2
1
2

CONFIG_0
CONFIG_1
CONFIG_2
CONFIG_3
CONFIG_4
CONFIG_5
CONFIG_6
CONFIG_7
CONFIG_8
CONFIG_9

C683
33P_0402_50V8K
@

Config 9 : Interface Mode Select


C

(12) RGMII_INTR

9
64

LAN_CTRL18
LAN_CTRL15

MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-

3
4
6
7
11
12
14
15

LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1LAN_MIDI2+
LAN_MIDI2LAN_MIDI3+
LAN_MIDI3-

RSET
PHYRSTB

1
38

RSET
2
2.49K_0402_1%

X1
X2

61
62

CLK125

41

RTL8211B-GR_QFN64_9x9

+3VAUX

R411
5.1K_0402_1%
@
1
R128

2 0.01U_0402_16V7K

C129 1

2 0.01U_0402_16V7K

C133 1

2 0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C213

place 0.1u cap close to IC power pin


1
D
2

C635
0.1U_0603_25V7K
+3VALW

+3VAUX
L43
1
2
FBMA-L11-322513-201LMA40T_1210
@

D
Q50
2N7002_SOT23

2
1
C236
27P_0402_50V8J

1
R561
1
R562

2
0_0402_5%
2
0_0402_5%

SBPWR_EN (27,28,34,40)

SLP_RMGT# (12,15)

R450
100K_0402_5%

C191
0.1U_0402_16V4Z

MP Modify 2007/04/13

1
1

25MHZ_20P
C243
27P_0402_50V8J

2
G

S
MII_RST (12)

MP Modify 2007/04/19

+3VAUX
LAN_LINK#

2
D26

LINK10
1
CH751H-40PT _SOD323

LAN_LINK#

2
D27

LINK100
1
CH751H-40PT _SOD323

LED_RX
L67
LED_TX
L68

2
1
2
FBM-11-160808-700T_0603 B
1
1
2
FBM-11-160808-700T_0603 A
U39

LAN_ACTIVITY#

Update Footprint

NC7SZ08P5X_NL_SC70-5

V_DAC1
LAN_MIDI3LAN_MIDI3+
V_DAC2
LAN_MIDI2LAN_MIDI2+
V_DAC3
LAN_MIDI1LAN_MIDI1+
V_DAC4
LAN_MIDI0LAN_MIDI0+

1
2
3
4
5
6
7
8
9
10
11
12

place 0.1u cap close to IC power pin

RP7

TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-

24
23
22
21
20
19
18
17
16
15
14
13

MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-

1
2
3
4

RJ45_MDI3RJ45_MDI3+
RJ45_MDI2RJ45_MDI2+

MP Modify 2007/04/19
Q18
2SB1188T100R_SC62-3

LAN_CTRL18 1

C122 1

2
2
C532
0.1U_0402_16V4Z

8
7
6
5

RJ45_GND

L70
2
1
MBK1608301YZF_0603

LAN_AVDD18_R

C161
0.1U_0402_16V4Z

75_1206_8P4R_5%

LAN_AVDD18

103mA

C185
10U_0805_10V4Z

RJ45_MDI1RJ45_MDI1+
RJ45_MDI0RJ45_MDI0+

0.1U_0402_16V4Z

2
2
C534
0.1U_0402_16V4Z

C531
0.1U_0402_16V4Z
1

+3VAUX

T1
2 0.01U_0402_16V7K

C535
0.1U_0402_16V4Z
1
1

+3VAUX_GATE

2
1
R441
200K_0402_5%

1
2
R566 0_0402_5%

EMI 2007/4/12 Added


C113 1

C530
10U_0805_10V4Z
1
1

1
2
3
4

2
1WOL_EN# 2
R449
G
100K_0402_5%
S
Q46
2N7002_SOT23

+5VALW

Y1

R32
470_0402_5%
@

V_DAC3
0_0402_5% @
V_DAC2
2
0_0402_5% @
V_DAC1
2
0_0402_5% @

S
S
S
G

SI4800BDY_SO8

+VSB

LAN_XTAL1
LAN_XTAL2

D
D
D
D

0.1U_0402_16V4Z
C205

R511

CTRL18
CTRL15

6 Via to GND

8
7
6
5

0.1U_0402_16V4Z
C224

R510
V_DAC2

V_DAC1

C227
1U_0603_10V4Z

0.1U_0402_16V4Z
C223

V_DAC3

GND

LAN_AVDD18

MBK1608121YZF_0603
1 LAN_DVDD15

R509

65

C179

1
R120
0_0805_5%
@

V_DAC4

CONFIG_0
CONFIG_1
CONFIG_2
CONFIG_3
CONFIG_4
CRS/CONFIG_5
COL/CONFIG_6
INTB/CONFIG_7
RXER/CONFIG_8
CONFIG_9

LINK1000
1
CH751H-40PT _SOD323

2
D25

LAN_AVDD18

58
57
56
54
53
47
46
37
35
33

LAN_AVDD15

LAN_LINK#

LED_RX
LED_TX
0_0402_5%
0_0402_5%

+3VAUX
U34

0.1U_0402_16V4Z
C222

4.7K_0402_5% @
R498 4.7K_0402_5%
RXDLY
1
2
1
2

2
2

2
5
10
13

+3VALW

1
1
R493
R496

AVDD18
AVDD18
AVDD18
AVDD18

0.1U_0402_16V4Z
C261

LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX

C242

50
48
44
43
40
39

63

60mil

L60

PHY Config

R507

LAN_ACTIVITY#

R497

LINK10
LINK100
LINK1000

AVDD15

4.7K_0402_5% @
R495 4.7K_0402_5%
TXDLY
1
2
1
2

MDC
MDIO

LAN_DVDD15

4.7K_0402_5%
R491 4.7K_0402_5% @
1
2 CONFIG_9
1
2

R494

30
31

LED

R490

RGMII_MDC
RGMII_MDIO

4.7K_0402_5%
R489 4.7K_0402_5% @
1
2 CONFIG_8
1
2

(12) RGMII_MDC
(12) RGMII_MDIO

DVDD15
DVDD15
DVDD15
DVDD15

1
2
C164 0.1U_0402_16V4Z
1
2
C188 0.1U_0402_16V4Z

R488

TXDLY
RXDLY

32
36
45
59

LAN_AVDD33

MBK1608121YZF_0603
1
+3VAUX

4.7K_0402_5%
R487 4.7K_0402_5% @
1
2 CONFIG_7
1
2

51
52

8
60

L59

R486

TXDLY
RXDLY

C659
33P_0402_50V8K
@

AVDD33
AVDD33

1.5v & 1.8v output power trace


width=40mil

4.7K_0402_5%
R485 4.7K_0402_5% @
1
2 CONFIG_6
1
2

RXCTL
RXC
RXD0
RXD1
RXD2
RXD3

+3VAUX

R484

16
22
17
19
20
21

18
23
34
42
49
55

4.7K_0402_5%
R483 4.7K_0402_5% @
1
2 CONFIG_5
1
2

R482

RXCTL
RXCLK_R
RXD0
RXD1
RXD2
RXD3

33_0402_5%

DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33

C253

(12) RXCTL
R481 1
(12) RXD0
(12) RXD1
(12) RXD2
(12) RXD3

(12) RXCLK

+3VAUX

TXCTL
TXC
TXD0
TXD1
TXD2
TXD3

RGMII

(RTL8211B:Config for all capability,


prefer slave mode)

29
24
25
26
27
28

Config 5~8 : Auto-Negotiation(NWay)


Configuration

PVT 2007/3/12

+3VAUX

TXCTL
TXCLK
TXD0
TXD1
TXD2
TXD3

TXCTL
TXCLK_PHY
TXD0
TXD1
TXD2
TXD3

0.1U_0402_16V4Z
C225

U3
(12)
(12)
(12)
(12)
(12)
(12)

RGMII_MDIO
10K_0402_5%

PWR

R181

CLK LAN I/F

+3VAUX

0.1U_0402_16V4Z

+3VAUX

350uH_GSL5009LF

Update Footprint

C686
10P_0402_50V8J
2 @

LAN_LINK#

PR3-

RJ45_MDI2+

PR3+

RJ45_MDI1+

PR2+

RJ45_MDI0-

PR1-

RJ45_MDI0+

PR1+

L62
+3VAUX

LAN_LINK#_R
2
FBM-11-160808-700T_0603
R129
2
1 300_0603_5%

10
9

15

R500
R501

PR2-

RJ45_MDI2-

SHLD1

R502
R503

SHLD2

14

SHLD1

13

MP Modify 2007/04/19

Q21
2SB1188T100R_SC62-3

C254
0.1U_0402_16V4Z

place 0.1u cap close to IC power pin

L71
2
1
MBK1608301YZF_0603

LAN_DVDD15_R
1

LAN_DVDD15

241mA

C257
10U_0805_10V4Z

0.1U_0402_16V4Z

4.7K_0402_5%
1
2 CONFIG_0
4.7K_0402_5%
1
2 CONFIG_1
4.7K_0402_5%
1
2 CONFIG_2
4.7K_0402_5%
1
2 CONFIG_3
4.7K_0402_5%
1
2 CONFIG_4

0.1U_0402_16V4Z
C260

RJ45_MDI1-

LAN_CTRL15
R499

0.1U_0402_16V4Z
C262

RJ45_MDI3+

C685
10P_0402_50V8J
2 @

16

0.1U_0402_16V4Z
C263

PR4+

SHLD2

0.1U_0402_16V4Z
C264

PR4-

0.1U_0402_16V4Z
C265

LAN_LINK#_R

Amber LED-

0.1U_0402_16V4Z
C256

LAN_ACTIVITY#_R

11

+3VAUX

0.1U_0402_16V4Z
C251

LAN_ACTIVITY#_R
2
FBM-11-160808-700T_0603
RJ45_MDI3-

Amber LED+

C247

LAN_ACTIVITY#
L61

12

+3VAUX

1 300_0603_5%

JP18
R126

Config 0~4 : PHY Address

Green LEDGreen LED+


FOX_JM36113-L2R8-7F

L69

PVT 2007/3/12

RJ45_GND

MBK1608301YZF_0603
1
1
2

EMI 2007/4/12 Added


5

C127
1000P_1206_2KV7K

LANGND
1

C138
C165
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2
2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

PHY RTL8211B
Size Document Number
Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P

Monday, April 23, 2007

Sheet
1

22

of

42

+3VS

R5C833

PCI_AD20

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

1
2
R226 100_0402_5%
(13) PCI_PERR#
5IN1@
(13) PCI_SERR#

PCI_REQ#0
PCI_GNT#0

(13) PCI_REQ#0
(13) PCI_GNT#0

124
123

CLK_PCI_1394

(13) CLK_PCI_1394
(13) PCI_RST1394#

121
119
71
117
70

CBS_GRST#
2 10K_0402_5%
2 0_0402_5%
5IN1@

@ R240 1
R242 1

(13,27,28) PM_CLKRUN#

33
23
25
24
29
26
8
30
31

115
116

(13) PCI_PIRQE#
(13) PCI_PIRQF#

1
R211

+3VS
(26,27,28,34,38)

1
R212

SUSP#

69
66

2
10K_0402_5%
5IN1@

2
0_0402_5% @

111
107
103
102
99

97

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#
PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#

AGND
AGND
AGND
AGND
AGND

C290
10U_0805_10V4Z

105
104

IEEE1394_TPBP0
IEEE1394_TPBN0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83

SDCD#_XDCD0#
MSCD#_XDCD1
XD_CE#
SDWP#_XDRB#
MC_PWREN
XDWP#
5IN1_LED#
TP_MSEXTCK
SDCMD_MSBS
SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
XDD4
XDD5
XDD6
XDD7
XDCLE
XDALE

MSEN
XDEN

58
55

MSEN
XDEN

XI
XO

94
95

R5C832XI
R5C832XO

SERIRQ
TP_UDIO1
TP_UDIO2
UDIO3
UDIO4
UDIO5

72
60
56
65
59
57

C359
0.01U_0402_16V7K

C338
0.1U_0402_16V4Z

C331
0.01U_0402_16V7K

5IN1@

5IN1@

L34 1
2
KC FBM-L11-201209-221LMAT_0805
5IN1@

SDCD#_XDCD0# (24)
MSCD#_XDCD1 (24)
XD_CE# (24)
SDWP#_XDRB# (24)

5IN1@

XDWP# (24)
5IN1_LED# (27,28)

5IN1@

5IN1@

5IN1@

SDWP#
SDPWR0

MDIO05

SDPWR1

MDIO06

XDR/B#

SDLED#

MMCLED#

MSLED#

5IN1@

MDIO08

SDCCMD

MMCCMD

MSBS

XDWE#

MDIO09

SDCCLK

MMCCLK

MSCCLK

XDRE#

MDIO10

SDCDAT0

MMCDAT

MSCDAT0

XDCDAT0

MDIO11

SDCDAT1

MSCDAT1

XDCDAT1

MDIO12

SDCDAT2

MSCDAT2

XDCDAT2

MDIO13

SDCDAT3

MSCDAT3

XDCDAT3

5IN1@

SDCMD_MSBS (24)
SDCLK_MSCLK (24)
SDDATA0_MSDATA0 (24)
SDDATA1_MSDATA1 (24)
SDDATA2_MSDATA2 (24)
SDDATA3_MSDATA3 (24)
XDD4 (24)
XDD5 (24)
XDD6 (24)
XDD7 (24)
XDCLE (24)
XDALE (24)

XDPWR
D

XDWP#

MDIO07

5IN1@

XDLED#

MSEXTCK

MDIO14

XDCDAT4

MDIO15

XDCDAT5

MDIO16

XDCDAT6

MDIO17

XDCDAT7

MDIO18

XDCLE

MDIO19

XDALE

Function set pin define

UDIO3

UDIO4

MSEN

XDEN

Pull-up

Pull-up

Pull-up

Pull-up

Function
Enable
SD,XD,MS,MMC Card
+3VS

Layout Note: Place close to R5C832


and Shield GND for SDCLK_MSCLK

5IN1@
2

Layout Note: Place close to R5C832


and Shield GND for SD_CLK

MSEN
UDIO3
UDIO4
UDIO5

5IN1@ R194
5IN1@ R191
5IN1@ R204
5IN1@ R193

XDEN

5IN1@ R205 1

1
1
1
1

2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%

2 10K_0402_5%

C366

SERIRQ (13,27,28)
PAD
T2
PAD
T3

1
5IN1@

4
13
22
28
54
62
63
68
118
122

5IN1@

+3V_PHY

0.01U_0402_16V7K

96
101
100

XDCE#

MDIO03

MSWR

5IN1@

+3VS

1
C369

XDCD1#

C367
10U_0805_10V4Z

TPBP0
TPBN0

MSCD#

MMCPWR

C372
1000P_0402_50V7K

IEEE1394_TPAP0
IEEE1394_TPAN0

XD Card
PIN Name
XDCD0#

MDIO04

C373
1000P_0402_50V7K

109
108

5IN1@

C374
0.1U_0402_16V4Z

TPAP0
TPAN0

5IN1@

5IN1@

C375
0.1U_0402_16V4Z

IEEE1394_TPBIAS0

5IN1@

C371
10U_0805_10V4Z

113

C378
0.47U_0603_16V4Z

TPBIAS0

C347
0.47U_0603_16V4Z

98
106
110
112

C294
0.01U_0402_16V7K

+3VS

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

RSV

+3V_PHY

UDIO0/SRIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

HWSPND#
TEST

1
C285
0.01U_0402_16V7K

67
86

MS Card
PIN Name

MDIO02

C354
10U_0805_10V4Z

VCC_3V

MMC Card
PIN Name
MMCCD#

MDIO01

+3VS

16
34
64
114
120

VCC_MD3V

FIL0
REXT
VREF

INTA#
INTB#

61

SD Card
PIN Name
SDCD#

MDIO
PIN Name
MDIO00

1
5IN1@

R5C832XI

2
22P_0402_50V8J

(13)
(13)
(13)
(13)
(13)
(13)

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
CBS_IDSEL
PCI_PERR#
PCI_SERR#

C370

C/BE3#
C/BE2#
C/BE1#
C/BE0#

1 @

5IN1@

C322
0.01U_0402_16V7K

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

R241
10K_0402_1%

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

7
21
35
45

VCC_RIN

10
20
27
32
41
128

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

R5C833

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C377
0.01U_0402_16V7K

C379
R237
4.7P_0402_50V8C10_0402_5%

CLK_PCI_1394

125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53

C284
0.01U_0402_16V7K

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

(13)
(13)
(13)
(13)

5IN1@

U14

(13) PCI_AD[0..31]

SD,MMC,MS,XD muti-function pin define

5IN1@

1
5IN1@

Y2
5IN1@
24.576MHZ_16P_X8A024576FG1H

SDDATA1_MSDATA1

R231 2

SDDATA2_MSDATA2

R243 2

R5C832XO
+VCC_4IN1

1 0_0402_5%
5IN1@
1 0_0402_5%
5IN1@
2 0_0805_5%
5IN1@

R229 1

22P_0402_50V8J

SD_MSDATA1

SD_MSDATA1 (24)

SD_MSDATA2

SD_MSDATA2 (24)
+VCC_4IN1_XD

D11

Layout Note: Shield GND for


CBS_CCLK_INTERNAL and CBS_CCLK

MSCD#_XDCD1

SDCD#_XDCD0#

XDCD#

XDCD# (24)

DAN202UT106_SC70-3
5IN1@

R5C833-TQFP128P_TQFP128_14x14

2N7002_SOT23
Q27
5IN1@

IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0

IEEE1394_TPBIAS0

1394@

4
3
2
1

6
5

6
5

40mil

8
7
6
5

MC_PWREN#

1
2

5IN1@

R239
300_0603_5%
5IN1@

R218
150K_0402_5%

C329
1U_0402_6.3V4Z

R451

G528_SO8
5IN1@

SDCMD_MSBS

5IN1@

SDDATA0_MSDATA0
R452
SDDATA1_MSDATA1
R453
SDDATA2_MSDATA2
R454
SDDATA3_MSDATA3
R455
SDWP#_XDRB#

R456

2N7002_SOT23
Q30
5IN1@

2
G
S

2.7K_0402_5%

2.7K_0402_5%

2.7K_0402_5%

2.7K_0402_5%

2.7K_0402_5%

2.7K_0402_5%

FOX_UV31413-4R1-TR
1394@

C554
0.33U_0603_10V7K

C553
0.01U_0402_16V7K

1394@

1394@

4
3
2
1

1U_0402_6.3V4Z
5IN1@

R397
56.2_0603_1%

C321

OUT
OUT
OUT
FLG

1 2

2
G

GND
IN
IN
EN#

MC_PWREN

5IN1@

C339

1
2

2
1

1
1

2
1

U13

MC_PWREN#

1394@

+VCC_4IN1

1
2
3
4

MC_PWREN#

1 @

R394
56.2_0603_1%

R396
56.2_0603_1%

R238
10K_0402_5%
5IN1@

+3VS

JP26

R398
56.2_0603_1%

R210
100K_0402_5%

1394@

CBS_GRST#

Z3008

5IN1@

1394@

1394@

+VCC_4IN1
+3VS

C355
R225
4.7P_0402_50V8C10_0402_5%

1
R395
5.1K_0402_1%

C552
270P_0402_50V7K

+3VS

Update Footprint

Memory Card Power Switch

SDCLK_MSCLK

0.1U_0402_16V4Z

5IN1@

Layout Note: Place close to R5C832

Layout Note: Shield GND for


IEEE1394_TPA and TPB

Compal Secret Data

Security Classification
Issued Date

2005/10/06

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1394@

Title

Compal Electronics, Inc.


R5C833_1394+Card reader

Size Document Number


Custom

Rev
1.0

ICW50 / ICY70 LA-3581P

Date:

Friday, April 20, 2007

Sheet
1

23

of

42

H29
H_S354D138

H20
H_S354D138

H3
H_S354D138

H18
H_S354D138

H2
H_S354D138

H11
H_S354D138

H10
H_S354D138

H30
H_S354D138

H4
H_S354D138

H6
H_C236D165

H28
H_C335BC140D138

H24
H_S354BC140D138

H16
H_C236D165

H1
H_C236BC315D138

H7
H_C236D165

H19
H_C315BC236D138

H15
H_S354D138

H17
H_C236D165

SD-WP-SW

35

SDWP#_XDRB#

15
19
20
18
16
17
21

5IN1@ R429
MSCLK 1
2
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
MSCD#_XDCD1
SDCMD_MSBS

13
22

4IN1 GND
4IN1 GND

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

H26
H_C236D98

SDCLK_MSCLK (23)
SDDATA0_MSDATA0 (23)
SDDATA1_MSDATA1 (23)
SDDATA2_MSDATA2 (23)
SDDATA3_MSDATA3 (23)
MSCD#_XDCD1 (23)
SDCMD_MSBS (23)

FD1

H23
H_O89X58D59X28

FD2
@

FD3
@

FD4
@

FD5
@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD7

FD8

FD9

FD10

FD17

FD18

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD15

FD16

@
B

FIDUCIAL_C40M80

FIDUCIAL_C40M80

+3V

C650
0.1U_0402_16V4Z

+3V

C649
0.1U_0402_16V4Z

+3VS

C648
0.1U_0402_16V4Z

+3VS

C647
0.1U_0402_16V4Z

+3VALW

C646
0.1U_0402_16V4Z

+5VS

C645
0.1U_0402_16V4Z

+5VS

C644
0.1U_0402_16V4Z

C643
0.1U_0402_16V4Z

C642
0.1U_0402_16V4Z

C641
0.1U_0402_16V4Z

+5VALW

FIDUCIAL_C40M80

FIDUCIAL_C40M80

4IN1 GND
4IN1 GND

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD6
@

FIDUCIAL_C40M80

+5VALW

For DDR Metal Cage

SDWP#_XDRB# (23)

TAITW_R015-312-LM

+5VALW

H1
: H_C236BC315D138
H6,H7,H16,H17 : H_C315BC168D165
H25,H26
: H_C236D98
H31,H32,H33 :H_C236BC131D128

22_0402_5%
SDCLK_MSCLK

37
38

H22
H_O89X58D59X28

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

H25
H_C236D98

H27
H_O197X158D197X158N

6
7
5
34
1
2
3
4

H5
H_C158D158N

SDCMD_MSBS
XDWP#
XDALE
XDCD#
SDWP#_XDRB#
SDCLK_MSCLK
XD_CE#
XDCLE

24
25
29
10
11
12
36

4 IN 1 CONN

H31
H_C236BC131D128

For MDC

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

8
9
26
27
28
30
31
32

H33
H_C236BC131D128

H8
H_C236BC131D128

SDDATA0_MSDATA0
SD_MSDATA1
SD_MSDATA2
SDDATA3_MSDATA3
XDD4
XDD5
XDD6
XDD7

(23) XD_CE#
(23) XDCLE

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-CMD
SD-CD-SW

5IN1@
R430
22_0402_5%
SDCLK 1
2 SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA0_MSDATA0 (23)
SD_MSDATA1
SD_MSDATA1 (23)
SD_MSDATA2
SD_MSDATA2 (23)
SDDATA3_MSDATA3
SDDATA3_MSDATA3 (23)
SDCMD_MSBS
SDCMD_MSBS (23)
SDCD#_XDCD0#
SDCD#_XDCD0# (23)

(23) SDCMD_MSBS
(23) XDWP#
(23) XDALE
(23) XDCD#
(23) SDWP#_XDRB#

23
14

(23) SDDATA0_MSDATA0
(23) SD_MSDATA1
(23) SD_MSDATA2
(23) SDDATA3_MSDATA3
(23) XDD4
(23) XDD5
(23) XDD6
(23) XDD7

H14
H_C236BC131D128

SD-VCC
MS-VCC

XD-VCC

33

H32
H_C236BC131D128

+VCC_4IN1

JP30
C

For FAN and MXM

PVT Modify 2007/3/12

H21
H_C276BC131D128

(New)

+VCC_4IN1_XD

4 IN 1 Socket Push Type

H13
H_C276BC131D128

5IN1@

C619
0.1U_0402_16V4Z

For CPU Support Breket


+VCC_4IN1
5IN1@
C618
10U_0805_10V6M

Compal Secret Data

Security Classification
Issued Date

2005/10/06

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Card Reader Conn / Screw

Size Document Number


Custom

Rev
1.0

ICW50 / ICY70 LA-3581P

Date:

Friday, April 20, 2007

Sheet
1

24

of

42

+3VS

+3VS

C218
10U_0805_10V4Z
MINI1@

C216

C214

C233
4.7U_0805_10V4Z
2

C217
0.1U_0402_16V4Z

2
1

MINI1@

C183
10U_0805_10V4Z
MINI2@

MINI1@

MINI1@

+5VS
(11) MINI1_CLKREQ#

(11) CLK_PCIE_MINI1#
(11) CLK_PCIE_MINI1

TV_S_CIN
TV_S_YIN
PCIE_MRX_PTX_N3
PCIE_MRX_PTX_P3

(11) PCIE_MRX_PTX_N3
(11) PCIE_MRX_PTX_P3

(11) PCIE_MTX_C_PRX_N3
(11) PCIE_MTX_C_PRX_P3
2

+3VS
AUDIO_INL
AUDIO_INR
TV_CVBSIN

0.1U_0402_16V4Z
2 MINI2@

C184

C180

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 MINI2@
2 MINI2@

C181

0.1U_0402_16V4Z
2 MINI2@

PVT2 Modify 2007/04/12

JP20
1
3
5
7
9
11
13
15

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

@
0_0402_5%
2 MCP_PCIE_WAKE#_LAN
WLAN_BT_DATA
WLAN_BT_CLK

R544
1
(30) WLAN_BT_DATA
(30) WLAN_BT_CLK
(11) MINI2_CLKREQ#

MCP_PCIE_WAKE#

(11,26,27) MCP_PCIE_WAKE#
+3VS
+1.5VS

(11) CLK_PCIE_MINI2#
(11) CLK_PCIE_MINI2

PCIE_RST1#

PCIE_RST1# (11)

PCIE_MRX_PTX_N2
PCIE_MRX_PTX_P2

(11) PCIE_MRX_PTX_N2
(11) PCIE_MRX_PTX_P2

SMBCLK1_R
SMBDATA1_R

(11) PCIE_MTX_C_PRX_N2
(11) PCIE_MTX_C_PRX_P2
USB20_N6 (14)
USB20_P6 (14)

+3VS

(MINI2_LED#)
MINI2@
(27,28) E51TXD_P80DATA
(27,28) E51RXD_P80CLK

E51TXD_P80DATA
E51RXD_P80CLK

R177 1
1
R176

2 0_0402_5%
2
0_0402_5%

JP21
1
3
5
7
9
11
13
15

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

MINI2@

+5VALW

+5VALW

C420

USB20_N3
USB20_P3

USB20_N2 (14)
USB20_P2 (14)

WL_OFF# (27,28)
PCIE_RST1# (11)
2
2 0_0402_5% MINI2@
0_0402_5% @

+3VS
+3V

USB20_N7 (14)
USB20_P7 (14)
MINI1_LED#

MINI1_LED#

MINI1_LED# (30)

PVT Modify 2007/03/12(+3V,+3VS)

Auxiliary Power (mA)

Primary Power (mA)

Normal

Peak

Normal

+3VS

1000

750

+3VALW

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)


3

4.7U_0805_10V4Z
2

USB20_N3 (14)
USB20_P3 (14)

1
R545
1
R546

+3VS

AUDIO_INR
AUDIO_INL
TV_S_YIN_R
TV_S_CIN_R
TV_CVBSIN_R
+3VALW
RCIRRX

WL_OFF#
PCIE_RST1#
1
R531 1
R532
SMBCLK1_R
SMBDATA1_R

+3V

RCIRRX (27)
USB_EN# (26,27,28)

ACES_87213-2000

2
2

SMBDATA1_R
2.7K_0402_5%
SMBCLK1_R
2.7K_0402_5%

+3VS

PVT2 Modify 2007/04/12

R265
100K_0402_5%

2
G

USB20_N2
USB20_P2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+1.5VS

Mini Card Power Rating


Power

JP11

R263 1

2 10K_0402_5%

USB_OC#1 (14)
(15,26) SMBDATA1

C389

SMBDATA1_R

Q56
2N7002_SOT23

2
G

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+3VS

FOX_AS0B226-S99N-7F
MINI2@

53
54
55
56

53
54
55
56

FOX_AS0B226-S99N-7F
MINI1@

USB/B Connector

C186
10U_0805_10V4Z
MINI2@

G1
G2
G3
G3

(27,28) TV_THERM#

C187

MINI1@

TV TUNNER
(11,26,27) MCP_PCIE_WAKE#

+3VS

0.1U_0402_16V4Z
MINI1@

L52
MBK2012121YZF_0805
MCP_PCIE_WAKE#

+1.5VS

0.1U_0402_16V4Z
2

AV-IN Connector
CIR

(15,26) SMBCLK1

3
S

C215

+5VS

0.1U_0402_16V4Z

G1
G2
G3
G3

+1.5VS

0.1U_0402_16V4Z

SMBCLK1_R

Q57
2N7002_SOT23

TV_S_YIN_R
L54
4

TV_S_CIN_R
L55
TV_CVBSIN_R
L56

1
1
1

TV_S_YIN
2
MBK1608121YZF_0603
TV_S_CIN
2
MBK1608121YZF_0603
TV_CVBSIN
2
MBK1608121YZF_0603

EMI PVT Modify 2007/03/12 Close JP11

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

MINI CARD / USB-B Conn.


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
E

25

of

42

New Card Power Switch

New Card Socket (Left/TOP)

U18

20

14
15
4
3
2

1.5Vout1
1.5Vout2

CPUSB#
CPPE#
STBY#
SHDN#
SYSRST#

C406

40mil
+3VALW_CARD1

40mil
+1.5VS_CARD1

10U_0805_10V4Z
2
EXPRESS@

Imax = 1.35A

C403

C397

RCLKEN
PERST#

+3VS
+3VS

TPS2231PWPR_PWP24
EXPRESS@

C393

2
CLKREQ1#

NC7SZ32P5X_NL_SC70-5

+1.5VS

C396

(14) USB20_N8
(14) USB20_P8

C405

CP_USB#
SMBCLK1_NEW
SMBDATA1_NEW

Q33
2N7002_SOT23
EXPRESS@

PERST1#

C421

0.1U_0402_16V4Z
2 EXPRESS@

(11) PCIE_MRX_PTX_N1
(11) PCIE_MRX_PTX_P1

U20
4

CLKREQ1#
CP_PE#

(11,14) CP_PE#
(11) CLK_PCIE_CARD#
(11) CLK_PCIE_CARD

(11) PCIE_MTX_C_PRX_N1
(11) PCIE_MTX_C_PRX_P1

EXP_CLKREQ# (11)

EXPRESS@

27
28

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND

GND
GND

29
30

FOX_1CH4110C_LT
EXPRESS@
SMBDATA1
SMBCLK1

1
+3VS

2 0_0402_5% SMBDATA1_NEW
2 0_0402_5% SMBCLK1_NEW

R536 1
R537 1

10U_0805_10V4Z
2
EXPRESS@

3
S

SMBDATA1

(15,25) SMBDATA1

1
R547
1
R548

+3VS

2
G

10U_0805_10V4Z
2
EXPRESS@

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

+3VS_CARD1

R270
10K_0402_5%
EXPRESS@

2
C394

C402

+3VS

10U_0805_10V4Z
EXPRESS@ 2

C404

(11,25,27) MCP_PCIE_WAKE#
+3VALW_CARD1

RCLKEN1 2
G
+3V

JP9

0928 Modify

Imax = 0.75A

10U_0805_10V4Z
10U_0805_10V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
EXPRESS@
EXPRESS@
EXPRESS@
EXPRESS@
EXPRESS@

RCLKEN1
PERST1#

NC1
NC2
NC3
NC4
NC5

23
22
9

R271
10K_0402_5%
EXPRESS@

+3VS

+1.5VS_CARD1

+1.5VS_CARD1

OC#

1
10
12
13
24

11

16
17

Imax = 0.275A

+3VS_CARD1

1.5Vin1
1.5Vin2

GND

EXPRESS@
R269EXPRESS@
1
2 100K_0402_5% CP_USB#
+3V
R268 1
2 100K_0402_5% CP_PE#
SUSP#
(23,27,28,34,38) SUSP#
SYSON
(27,28,34,40) SYSON
PCIE_RST#
(11,18) PCIE_RST#

Aux_out

3.3Vaux_in

18
19

+1.5VS

7
8

G Vcc

21

+3V

3.3Vout1
3.3Vout2

+3VS_CARD1

3.3Vin1
3.3Vin2

5
6

+3VS

+3VALW_CARD1

60mils

SMBDATA1_NEW

Q58
2N7002_SOT23
@

USB CONN. 1(Stack-up Type)

SMBDATA1_NEW
2
2.7K_0402_5% @
SMBCLK1_NEW
2
2.7K_0402_5% @

2
G

PVT2 Modify 2007/04/11

SMBCLK1

3
S

(15,25) SMBCLK1

+USB_VCCA

+USB_VCCA

C270

2
OUT
OUT
OUT
FLG

8
7
6
5

R158
100K_0402_5%
2

GND
IN
IN
EN#

R154 1

PVT Modify 2007/03/22


2 10K_0402_5%

USB_OC#0 (14)

(14) USB20_N0
(14) USB20_P0

G528_SO8
4.7U_0805_10V4Z
2
C241
3

1 C245
1
470P_0402_50V7K

U6
1
2
3
4

W=80mils

+USB_VCCA
1

+5VALW

SMBCLK1_NEW

Q59
2N7002_SOT23
@

+3V

1
(14) USB20_N1
(14) USB20_P1

0.1U_0402_16V4Z
2

(25,27,28) USB_EN#

2
C537
150U_D2_6.3VM

2 C244
470P_0402_50V7K
JP23

USB20_N0
USB20_P0

@
@

R168 1
R174 1

2 0_0402_5%
2 0_0402_5%

USB20_N0_R
USB20_P0_R

1
2
3
4

VCC
D0D0+
GND

USB20_N1
USB20_P1

@
@

R137 1
R132 1

2 0_0402_5%
2 0_0402_5%

USB20_N1_R
USB20_P1_R

5
6
7
8

VCC
D1D1+
GND

9
10

GND1
GND2

SUYIN_020122MR008S505ZL
L26
USB20_N0

USB20_P0

USB20_N0_R

USB20_P0_R

WCM2012F2S-900T04_0805

L23
USB20_N1

USB20_P1

4
1

USB20_N1_R

USB20_P1_R

WCM2012F2S900T04_0805
D5
1
USB20_P0_R

GND
I/O

D4
VCC

+USB_VCCA

I/O

USB20_N0_R

1
USB20_P1_R

@ PRTR5V0U2X_SOT143

GND
I/O

VCC

+USB_VCCA

I/O

USB20_N1_R

@ PRTR5V0U2X_SOT143

SUYIN_020173MR004G533ZR_4P

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Issued Date

SUYIN_020173MR004G533ZR_4P

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

NEW CARD & USB Connector


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
E

26

of

42

+3VALW

KSI[0..7]

0.1U_0402_16V4Z
1 C341
1

C293

0.1U_0402_16V4Z
1
2
C368

2
2
0.1U_0402_16V4Z

C380

2
2
0.1U_0402_16V4Z

1
2+EC_VCCA
2 FBM-L11-160808-800LMT_0603
1
C376
C384
1000P_0402_50V7K
1000P_0402_50V7K
1
1
2

BATT_TEMP
0.1U_0402_16V4Z
BATT_OVP
ACIN

C660
2
C661
2
C662
2

1
2
3
4

1
2
3
4

100P_0402_50V8J
1
100P_0402_50V8J
1
100P_0402_50V8J
1

E51RXD_P80CLK
E51TXD_P80DATA

+3VALW
D

65W/90W#
R519

(15,28) PM_SLP_S3#
(15,28) PM_SLP_S5#
(15,28) EC_SMI#
(28,30,33) LID_SW#
(23,26,28,34,38) SUSP#
(15,28) PBTN_OUT#
(13,28) EC_PME#
(6,15,28) EC_THERM#
(4,28) FAN_SPEED1
(28,30) BT_ON#

+5VALW
RP57

1
2
3
4

8
7
6
5

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

(28,31) ON/OFF
(28,30) PWR_SUSP_LED
(28,30) NUM_LED#

4.7K_1206_8P4R_5%

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
SUSP#
PBTN_OUT#
EC_PME#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED
NUM_LED#

EC_CRY2
EC_CRY1

97
98
99
109

3S/4S#
65W/90W#
SBPWR_EN

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

EC_SI_SPI_SO/FRD#
EC_SO_SPI_SI/FWR#
EC_SPICLK
EC_SPICS#/FSEL#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RCIRRX

122
123

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

SPI Device Interface


SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

XCLK1
XCLK0

11
24
35
94
113
A

@ R224
(11,25,26) MCP_PCIE_WAKE#

R221

1
1

EC_PME#
10K_0402_5%
EC_PME#
2
0_0402_5% @

KB926QFB1_LQFP128_14X14

20mil

FSTCHG
BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED
SYSON
MCP_PWRGD

EC_LID_OUT#
EC_ON
VGA_ON
BKOFF#
WL_OFF#
MEDIA_LED#

SKU_ID
ENBKL
EAPD
SATA_LED#
MXM_THERM#
IDE_5IN1_LED#

H
L

SKU_ID

AD_BID0 (28)

C291

R200
0_0402_5%
@

Rd

8.2K_0402_5%
2
UMA@ 0.1U_0402_16V4Z

C278
0.1U_0402_16V4Z

EC_SI_SPI_SO/FRD# (28,29)
EC_SO_SPI_SI/FWR# (28,29)
EC_SPICLK (28,29)
EC_SPICS#/FSEL# (28,29)

ENCODER_PULSE (28,33)
FSTCHG (28,38)
BATT_GRN_LED# (28,30,33)
CAPS_LED# (28,30)
BATT_AMB_LED# (28,30,33)
PWR_LED (28,30)
SYSON (26,28,34,40)
MCP_PWRGD (6,15,18,28)
ACIN (15,18,28,37)

3S/4S#

1
R462

ENBKL

1
R466

2.7K_0402_5%
10K_0402_5%

EC_RSMRST# (15,28)
EC_LID_OUT# (15,28)
EC_ON (28,31)
EC_SWI# (15,28)
VGA_ON (18)
BKOFF# (20,28)
WL_OFF# (25,28)
MEDIA_LED# (28,30)
CALIBRATE (28,38)

EC_CRY1

(28) EC_CRY1
C556

EC_CRY2

10P_0402_50V8K
2

SKU_ID (28)
ENBKL (12,18,28)
EAPD (28,32)
SATA_LED# (14,28)
MXM_THERM# (18,28)

EC_CRY2

(28)

C555

10P_0402_50V8K
2

ARCADE# (28,30) +3VS

X3
32.768KHZ_12.5P_1TJS125DJ2A073

IDE_5IN1_LED#
@
2 C692
0.1U_0402_16V4Z

5IN1_LED#

IDE_LED#

5IN1_LED# (23,28)
IDE_LED# (21,28)

U38
NC7SZ08P5X_NL_SC70-5

For KB926 C0 reversion

Issued Date

Compal Electronics, Inc.

Compal Secret Data


2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Rc

AD_BID0
R192

Rb

C-PASE
B-PASE

R207
100K_0402_5%

3S/4S# (28,38)
65W/90W# (28,38)
SBPWR_EN (22,28,34,40)
TV_THERM# (25,28)

2
R206
100K_0402_5%
VGA@

Ra

L32
ECAGND 2
1
FBM-L11-160808-800LMT_0603

Security Classification

+3VALW

PS2 Interface

GND
GND
GND
GND
GND

+3VALW

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

+3VALW
EC_MUTE (28,33)
USB_EN# (25,26,28)
WL_LED# (28,30)
BT_LED# (28,30)
TP_CLK (28,29)
TP_DATA (28,29)

2 TP_CLK
4.7K_0402_5%
2 TP_DATA
4.7K_0402_5%

1
R235
1
R236

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_MUTE
USB_EN#
WL_LED#
BT_LED#
TP_CLK
TP_DATA

SKU ID definition,
Please see page 3.

(18,28,29,37)
(18,28,29,37)
(6,28)
(6,28)

+5VS

83
84
85
86
87
88

Analog Board ID definition,


Please see page 3.

IN

RB751V_SOD323

Update Footprint

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

OUT

EC_RCIRRX (28)

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

DAC_BRIG (20,28)
EN_DFAN1 (4,28)
IREF (28,38)
CHGSEL (28,38)

NC

EC_RCIRRX

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

DPST_PWM (12,20,28)

C549
0.1U_0402_16V4Z

NC

D12

(25) RCIRRX

DAC_BRIG
EN_DFAN1
IREF

1
100K_0402_5%

R232
10K_0402_5%

68
70
71
72

POUT (28,41)

+3VALW

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output

1
100K_0402_5%

TV_THERM#
2
R443

R390
10K_0402_5%
2
1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP (28,37)

BATT_OVP (28,38)
ADP_I (28,38)

AD_BID0

C292
0.1U_0402_16V4Z

EC_SCI#

BATT_TEMP
BATT_OVP

(15,28) EC_SCI#
(13,23,28) PM_CLKRUN#

63
64
65
66
75
76

1
47K_0402_5%
1

AD

+3VS

2
R201

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

PWM Output

(13,28) PLT_RST#
(28) EC_RST#
+3VALW

12
13
37
20
38

1
100K_0402_5%
+5VALW

R444

INVT_PWM (20,28)
BEEP# (28,32)
ENCODER_DIR (28,33)
ACOFF (28,35,38)
ECAGND
2
1
C283 0.01U_0402_16V7K

(13,28) CLK_PCI_LPC

21
23
26
27

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

AGND

R233 2

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

INVT_PWM
BEEP#

69

C364
@ 22P_0402_50V8J
2
1

1
2
3
4
5
7
8
10

PVT Modify 2007/03/12


USB_EN#

(15,28) EC_GA20
(15,28) EC_KBRST#
(13,23,28) SERIRQ
(13,14,28) LPC_FRAME#
(13,28) LPC_AD3
(13,28) LPC_AD2
1 @ 33_0402_5%
(13,28) LPC_AD1
(13,28) LPC_AD0

E51RXD_P80CLK (25,28)
E51TXD_P80DATA (25,28)

@ ACES_85205-0400

ECAGND (28)

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

U15

+3VALW
JP10

C330

67

9
22
33
96
111
125

KSO[0..17] (28,29,30)

+EC_VCCA (28)

ECAGND

For EC Tools

KSI[0..7] (28,29,30)

KSO[0..17]

L30

Title

EC ENE KB926
Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
1

27

of

42

+3VALW

KSI[0..7] (27,29,30)

+EC_VCCA (27)

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

(15,27) PM_SLP_S3#
(15,27) PM_SLP_S5#
(15,27) EC_SMI#
(27,30,33) LID_SW#
(23,26,27,34,38) SUSP#
(15,27) PBTN_OUT#
(13,27) EC_PME#

KSI0/GPIO30
KSI1/GPIO31
KSI0/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
89
90

KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

E51TXD_P80DATA
E51RXD_P80CLK
NUM_LED#
BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED
SYSON
0_0402_5%
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
SUSP#
PBTN_OUT#
EC_PME#
EC_CRY2
EC_CRY1

(27) EC_CRY2
(27) EC_CRY1

88
87
86
85

34
35
40
99
100
101
102
104
4
7
8
16
17
18
19
20
21
22
23
138
139

75
DA0/GPO3C
DA1/GPO3D
DA2/GPO3E
DA3/GPO3F
DA output or GPO

76
78
79
80

DAC_BRIG
EN_DFAN1
IREF

PWM1/GPIO0F
PWM2/GPIO10
PWM3/GPIO11
PWM4/GPIO19
FANPWM1/GPIO12
FANPWM2/GPIO13
FANFB1/GPIO14
FANFB2/GPIO15

25
27
29
38
30
31
32
33

INVT_PWM
BEEP#

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
PSCLK3/GPIO4E
PSDAT3/GPIO4F

91
92
93
94
95
96

EC_MUTE
USB_EN#
WL_LED#
BT_LED#
TP_CLK
TP_DATA

ADB0/GPXID0/SDIDI
ADB1/GPXID1
ADB2/GPXID2
ADB3/GPXID3
ADB4/GPXID4
ADB5/GPXID5
ADB6/GPXID6
ADB7/GPXID7
KBA0/GPXOA00/SDICS#
KBA1/GPXOA01/SDICLK
KBA2/GPXOA02/SDIDO
KBA3/GPXOA03
KBA4/GPXOA04
KBA5/GPXOA05
KBA6/GPXOA06
KBA7/GPXOA07
KBA8/GPXOA08
KBA9/GPXOA09
KBA10/GPXOA10
KBA11/GPXOA11
KBA12/GPXOA12
KBA13/GPXOA13
KBA14/GPXOA14
KBA15/GPXOA15
KBA16/GPXOA16
KBA17/GPXOA17
KBA18/GPXOA18
KBA19/GPIO51/A19

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

ADB0 @ R250 1
ADB1 @ R439 1
ADB2 @ R257 1
ADB3 @ R251 1
ADB4 @ R258 1
ADB5 @ R252 1
ADB6 @ R259 1
ADB7 @ R253 1
KBA0 @ R244 1
KBA1 @ R260 1
KBA2 @ R256 1
KBA3 @ R448 1
KBA4 @ R261 1
KBA5 @ R246 1
KBA6 @ R262 1
KBA7
KBA8 @ R248 1
KBA9 @ R254 1
KBA10 @ R249 1
KBA11 @ R255 1
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
MXM_THERM#

GPIO58/SPICLK
RD#/SPIDI
WR#/SPIDO
SPICS#

142
135
136
144

EC_SI_SPI_SO/FRD#
EC_SO_SPI_SI/FWR#
EC_SPICS#/FSEL#

GPIO18
GPIO1B
GPIO1C
GPIO1E
GPIO1F
GPIO42
SELIO2#/GPIO43
SELIO#/GPIO50
XCLK32K/GPIO57
GPIO59

36
41
43
45
46
83
84
97
137
143

ON/OFF
@ R433 1
@ R440 1

81
82

EC_RCIRRX

FAN/PWM

ps2
interface

key Matrix
scan

Data
BUS

Address
BUS
SM BUS

GPIO16/E51TXD
GPIO17/E51CLK/E51RXD
GPIO1A/NUMLED#
GPIO52/E51CS#
GPIO53/CAPSLED#
GPIO54
GPIO55/SCORLED#
GPIO56
GPIO02
GPIO03
GPIO04
GPIO06
GPIO07
GPIO08
GPIO09
GPIO0A
GPIO0B/ESB_CLK
GPIO0C/ESB_DAT
GPIO0D
XCLKI
XCLKO
V18R

129
103
13
28
39

140

SDA2/GPIO47
SCL2/GPIO46
SDA1/GPIO45
SCL1/GPIO44

BATT_TEMP
BATT_OVP

AGND

R245

63
64
65
66
67
68
69
70

71
72
73
74

Host
INTERFACE

77

@
(15,27) EC_RSMRST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

(25,27) E51TXD_P80DATA
(25,27) E51RXD_P80CLK
(27,30) NUM_LED#
(27,30,33) BATT_GRN_LED#
(27,30) CAPS_LED#
(27,30,33) BATT_AMB_LED#
(27,30) PWR_LED
(26,27,34,40) SYSON
B

EC_SCI#

AD0/GPI38
AD1/GPI39
AD2/GPI3A
AD3/GPI3B
AD INtput or GPI

PWR

GND
GND
GND
GND
GND

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

GA20/ GPIO00
KBRST#/GPIO01
SERIRQ
LFRAME#
LAD3
LAD2
LAD1
LAD0
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

VCC
VCC
VCC
VCC
VCC
VCC

U16

1
2
3
5
6
9
10
12
14
15
42
24
44

AVCC

11
26
37
105
127
141

KSO[0..17] (27,29,30)

(15,27) EC_GA20
(15,27) EC_KBRST#
(13,23,27) SERIRQ
(13,14,27) LPC_FRAME#
(13,27) LPC_AD3
(13,27) LPC_AD2
(13,27) LPC_AD1
(13,27) LPC_AD0
(13,27) CLK_PCI_LPC
(13,27) PLT_RST#
(27) EC_RST#
(15,27) EC_SCI#
(13,23,27) PM_CLKRUN#

(6,27)
(6,27)
(18,27,29,37)
(18,27,29,37)

ADB[0..7]

ADB[0..7]

KSO[0..17]

KBA[0..19]

KBA[0..19]

KSI[0..7]

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41

AD_BID0

BATT_TEMP (27,37)
BATT_OVP (27,38)
ADP_I (27,38)
AD_BID0 (27)
DAC_BRIG (20,27)
EN_DFAN1 (4,27)
IREF (27,38)
CHGSEL (27,38)

INVT_PWM (20,27)
BEEP# (27,32)
EC_THERM# (6,15,27)
PWR_SUSP_LED (27,30)
ENCODER_DIR (27,33)
ACOFF (27,35,38)
FAN_SPEED1 (4,27)
BT_ON# (27,30)

PWR_SUSP_LED
FAN_SPEED1
BT_ON#

FSTCHG
MCP_PWRGD

EC_MUTE (27,33)
USB_EN# (25,26,27)
WL_LED# (27,30)
BT_LED# (27,30)
TP_CLK (27,29)
TP_DATA (27,29)

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

TV_THERM# (25,27)
SKU_ID (27)
ENBKL (12,18,27)
IDE_LED# (21,27)
SATA_LED# (14,27)
5IN1_LED# (23,27)
EAPD (27,32)
ARCADE# (27,30)
3S/4S# (27,38)
65W/90W# (27,38)
SBPWR_EN (22,27,34,40)
EC_RSMRST# (15,27)
EC_LID_OUT# (15,27)
EC_ON (27,31)
EC_SWI# (15,27)

SKU_ID
ENBKL
IDE_LED#
SATA_LED#
EAPD

SBPWR_EN
EC_LID_OUT#
EC_ON
BKOFF#
WL_OFF#
MEDIA_LED#

BKOFF# (20,27)
WL_OFF# (25,27)
MEDIA_LED# (27,30)
CALIBRATE (27,38)

MXM_THERM# (18,27)

EC_SPICLK (27,29)
EC_SI_SPI_SO/FRD# (27,29)
EC_SO_SPI_SI/FWR# (27,29)
EC_SPICS#/FSEL# (27,29)

ON/OFF (27,31)

2 0_0402_5% EC_ON
2 0_0402_5% SBPWR_EN

EC_ON (27,31)
SBPWR_EN (22,27,34,40)

DPST_PWM (12,20,27)
POUT (27,41)
FSTCHG (27,38)
MCP_PWRGD (6,15,18,27)
ACIN (15,18,27,37)
EC_RCIRRX (27)
ENCODER_PULSE

(27,33)

KB925QFA0_LQFP144_22x22
@ 20mil
ECAGND

ECAGND (27)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Issued Date

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

EC ENE KB910L/925(Reserved)
Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
1

28

of

42

+5VALW

2 0.1U_0402_16V4Z

R182
100K_0402_5%
2

A0
A1
A2
GND

JP6

1
2
3
4

+5VS
(27,28) TP_DATA
(27,28) TP_CLK

AT24C16AN-10SI-2.7_SO8

6
5
4
3
2
1

TP_DATA
TP_CLK

TP_DATA
TP_CLK
3

VCC
WP
SCL
SDA

@
U8
8
7
6
5

C259 1

(18,27,28,37) EC_SMB_CK1
(18,27,28,37) EC_SMB_DA1

To TP/B Conn.

+5VALW

ACES_85201-0605
R196
100K_0402_5%

D3
@
PSOT24C_SOT23

+5VS
TP_DATA C208 1

2 @ 100P_0402_50V8J

TP_CLK

2 @ 100P_0402_50V8J

C207 1

Update Footprint

C209

Update Footprint

0.1U_0402_16V4Z

9/25 Added for EMI


+3VALW
C258 1

2 0.1U_0402_16V4Z

CE#
WP#
HOLD#
VSS

VDD
SCK
SI
SO

8
6
5
2

R166 1
R167 1
R208 1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

EC_SPICLK (27,28)
EC_SO_SPI_SI/FWR# (27,28)
EC_SI_SPI_SO/FRD# (27,28)

(Left)

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

PVT Net Name Modify 2007/3/12

U37
1
3
7
4

CE#
WP#
HOLD#
VSS

VDD
SCK
SI
SO

8
6
5
2

KSI[0..7] (27,28,30)

KSO[0..17]

KSO[0..17] (27,28,30)

JP5

MX25L8005M2C-15G_SOP8
+3VALW

(27,28) EC_SPICS#/FSEL#

KSI[0..7]

INT_KBD Conn.

U10
1
3
7
4

(27,28) EC_SPICS#/FSEL#

EC_SPICLK (27,28)
EC_SO_SPI_SI/FWR# (27,28)
EC_SI_SPI_SO/FRD# (27,28)

MX25L8005M2C-15G_SOP8
@

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

(Right)

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

G2
G1

28
27

ACES_85201-26051

C91

100P_0402_50V8J

KSO7

C83

100P_0402_50V8J

KSO14

C90

100P_0402_50V8J

KSO6

C82

100P_0402_50V8J

KSO13

C89

100P_0402_50V8J

KSO5

C81

100P_0402_50V8J

KSO12

C88

100P_0402_50V8J

KSO4

C80

100P_0402_50V8J

KSI0

C92

100P_0402_50V8J

KSO3

C79

100P_0402_50V8J

KSO11

C87

100P_0402_50V8J

KSI4

C96

100P_0402_50V8J

KSO10

C86

100P_0402_50V8J

KSO2

C78

100P_0402_50V8J

KSI1

C93

100P_0402_50V8J

KSO1

C77

100P_0402_50V8J

KSI2

C94

100P_0402_50V8J

KSO0

C76

100P_0402_50V8J

KSO9

C85

100P_0402_50V8J

KSI5

C97

100P_0402_50V8J

KSI3

C95

100P_0402_50V8J

KSI6

C98

100P_0402_50V8J

KSO8

C84

100P_0402_50V8J

KSI7

C99

100P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

KSO15

2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

BIOS, I/O Port & K/B Connector


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Monday, April 23, 2007

Sheet

29

of

42

+3VS

+5VS

+5VALW

PVT2 Modify 2007/4/10

JP2

BT_BTN#

KSI3

EMAIL_BTN#

KSI4

IE_BTN#

KSI5

E-KEY_BTN#
17
18

Check 15.4" K/B Matrix

G17
G18

+5VS
1 C28
1U_0402_6.3V4Z

PWR_LED#
WL_R_LED#
BT_LED#
PWR_SUSP_LED#
KSO0
KSI1
KSI2
KSI3
KSI4

+3V

MDC Conn.

ON/OFFBTN# (31)
2

BT_LED# (27,28)
KSO0 (27,28,29)
KSI1 (27,28,29)
KSI2 (27,28,29)
KSI3 (27,28,29)
KSI4 (27,28,29)

+5VALW
1

ACES_85201-16051

HDA_SDOUT_MDC

(14) HDA_SDOUT_MDC
(14) HDA_SYNC_MDC
(14) HDA_SDIN1
(14) HDA_RST_MDC#

C657
100P_0402_50V8J

R112 1

2 33_0402_5%

1
3
5
7
9
11

2
+3VALW
100K_0402_5%

D17
2

ARCADE_BTN# 1

ARCADE# (27,28)
51ON#

51ON# (31,35)

DAN202UT106_SC70-3

+3VALW

R111
0_0402_5%
@

1 C27
1U_0402_6.3V4Z

KSO0 (27,28,29)
KSI5 (27,28,29)
LID_SW# (27,28,33)
+3VALW
+5VS

13
14
15
16
17
18

1
ARCADE_BTN#
KSO0
KSI5

2 0_0402_5%

C154
1U_0603_10V4Z

+3V
HDA_BITCLK_MDC (14)
R538
0_0402_5%

ACES_88018-124G

C155

Connector for MDC Rev1.5

1
R317

MEDIA_LED# (27,28)
CAPS_LED# (27,28)
NUM_LED# (27,28)

R467 1

2
4
6
8
10
12

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

HDA_SDOUT_MDC
JP36
12
11
10
9
8
7
6
5
4
3
2
1

20mil

JP17

KSI2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

WL_BTN#

GND
GND
GND
GND
GND
GND

KSO0
KSI1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

22P_0402_50V8J

1 C137
10P_0402_50V8J
@

ACES_85201-1205

Update Footprint

PWR_LED#

C663 1

2 @ 100P_0402_50V8J

ON/OFFBTN#

C664 1

2 @ 100P_0402_50V8J

LID_SW#

C665 1

100P_0402_50V8J

WL_R_LED#

C666 1

2 @ 100P_0402_50V8J

KSI5

C667 1

100P_0402_50V8J

BT_LED#

C668 1

2 @ 100P_0402_50V8J

PWR_SUSP_LED#C669 1

2 @ 100P_0402_50V8J

ARCADE_BTN# C670 1

100P_0402_50V8J

NUM_LED#

C672 1

100P_0402_50V8J

2 @ 100P_0402_50V8J

CAPS_LED#

C674 1

100P_0402_50V8J

C675 1

2 @ 100P_0402_50V8J

MEDIA_LED#

C676 1

100P_0402_50V8J

C677 1

2 @ 100P_0402_50V8J

C678 1

2 @ 100P_0402_50V8J

KSO0

C671 1

KSI1

C673 1

KSI2
KSI3

WL_LED# (27,28)

@
MINI1_LED#

MINI1_LED# (25)

0_0402_5%

Bluetooth Conn.
+3VALW

+3VS
+BT_VCC

R295
100K_0402_5%
@

C473
BT@
0.1U_0402_16V4Z

KSI4

100P_0402_50V8J

WL_LED#
0_0402_5%

1
R292

(27,28) BT_ON#

2
10K_0402_5%

PWR_SUSP_LED#

PWR_LED#

BT@

1
R520
1
R521

WL_R_LED#

EMI PVT Modify 2007/3/12

C474

JP12
C475
BT@
1U_0603_10V4Z

Q37
AO3413_SOT23-3
BT@

1
2
G
3

S Q47
2N7002_SOT23

10

ACES_87213-0800G
BT@

R296
300_0603_5%
BT@

L37
USB20_N5

USB20_P5

USB20_N5_R

USB20_P5_R

(27,28) PWR_LED

1 GND
2
3
4
5
6
7
8 GND

1
C487
BT@
BT@
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z

S Q40
2N7002_SOT23

1
2
G
3

(27,28) PWR_SUSP_LED

(25) WLAN_BT_DATA
(25) WLAN_BT_CLK
+BT_VCC

C489
D

(14) USB20_P5
(14) USB20_N5

1
2
3
4
5
6
7
8

BT@
2 USB20_P5_R
2 USB20_N5_R
BT@

W=40mils

BT@
0.1U_0402_16V4Z

0_0402_5%
R290 1
R291 1
0_0402_5%

2
G
S

Q38
2N7002_SOT23
BT@

WCM2012F2S-900T04_0805
@

9/25 Added for EMI

PWR_LED#

PWR_LED# (33)

PWR_SUSP_LED#

PWR_SUSP_LED# (33)

HT-297DQ/GQ_AMB/YG_0603

2
G

Q52
2N7002_SOT23
@

LED2
3
4

BATT_GRN_LED#

BATT_GRN_LED# (27,28,33)

+5VALW

R294
300_0402_5%
1
2
R435
453_0402_1%
1
2

YG

+5VALW

+BT_VCC

@
R522
10K_0402_5%
1
2

BT_LED# (27,28)
4

+5VALW

LED1
YG

+5VS

R293
300_0402_5%
1
2
R436
453_0402_1%
1
2

BATT_AMB_LED#

BATT_AMB_LED# (27,28,33)

PVT Modify 2007/3/12

HT-297DQ/GQ_AMB/YG_0603

PVT Value Modify to 453E 2007/3/12

Compal Footprint
4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

MDC / BT / CIR / LED


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet

30

of

42

TOP Side

+3VALW

2
@ 10K_0603_5%

2
@ 10K_0603_5%

Power Button
2

R533

R534

R213

Bottom Side
1

100K_0402_5%
D7

ON/OFFBTN#

(30) ON/OFFBTN#

ON/OFF (27,28)

51ON#

51ON# (30,35)

DAN202UT106_SC70-3

Update Footprint
2

2
G
R195
10K_0402_5%

C325
1000P_0402_50V7K

D8
RLZ20A_LL34

1
EC_ON

(27,28) EC_ON

1
D
2N7002_SOT23
Q24

Power ON Circuit

+5VALW

+3V

+1.8V

+5VALW

+3V

3
2

C70
0.1U_0402_16V4Z

2
1

Q36
MMBT3904_SOT23
1

2
1

MEM_VLD
D

1
2

Q35
BSS138_SOT23
2
G

HT_VLD (11,15)

R278
47K_0402_5%

R279
47K_0402_5%

R276
47K_0402_5%

C430
0.1U_0402_16V4Z

Q12
MMBT3904_SOT23
1

HT_VLD

Q11
BSS138_SOT23
2
G

R107
47K_0402_5%

R105
47K_0402_5%

C69
0.1U_0402_16V4Z

R98
47K_0402_5%

+1.2V_HT

MEM_VLD (15,40)

C454
0.1U_0402_16V4Z

NEAR PU10

Compal Secret Data

Security Classification
Issued Date

2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR_OK CIRCUIT/ BTN


Size Document Number
Custom ICW50 / ICY70
Date:

Rev
1.0

LA-3581P

Friday, April 20, 2007

Sheet

31

of

42

28.7K for Module Design (VDDA = 4.702)

+VDDA
+5VAMP

2
1

1
C612

2
1U_0603_10V4Z

U29

L45 1
2
KC FBM-L11-201209-221LMAT_0805

VIN

1
1
L46 1
C605
C602
2
KC FBM-L11-201209-221LMAT_0805
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z

DELAY

ERROR

SD

R434

C
2

R431

D23
RB751V_SOD323

R432
10K_0402_5%

HD Audio Codec

C594
LINE_L

(33) LINE_L

C583
LINE_R

(33) LINE_R

C582

MIC1_L

(33) MIC1_L

C587
MIC1_R

(33) MIC1_R

C584

(33) HP_PLUG#

R415 2

1 5.1K_0402_1%

(33) LINEIN_PLUG#
(33) MIC_PLUG#

R419 1
R413 2

2 10K_0402_1%
1 20K_0402_1% (27,28) EAPD
(33) SPDIF

EAPD
1
2SPDIF_R
FBM-L11-160808-800LMT_0603
L53
1

Codec Signals
2

PORT-A (PIN 39, 41)

20K

PORT-B (PIN 21, 22)

10K

PORT-C (PIN 23, 24)

5.1K

PORT-D (PIN 35, 36)

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-G (PIN 43, 44)

5.1K

PORT-H (PIN 45, 46)

1
DVDD

25

38
AVDD2

LINE_OUT_L

35

HP_LEFT

LINE_OUT_R

36

HP_RIGHT

MIC2_L

HP_OUT_L

39

AMP_LEFT

MIC2_R

HP_OUT_R

41

AMP_RIGHT

LINE1_L

NC

45

LINE1_R

DMIC_CLK

46

CD_L

NC

43

20

CD_R

NC

44

19

CD_GND

SENSE_A

NC

10

BIT_CLK

SDATA_IN

R424

MIC1_R

10U_0805_10V4Z
2

HP_LEFT (33)
HP_RIGHT (33)
AMP_LEFT (33)
AMP_RIGHT (33)

C608
2 0_0402_5%
1

22P_0402_50V8J
2
HDA_BITCLK_AUDIO

PCBEEP

MONO_OUT

29

GPIO1

31

MIC1_VREFO_L

28

SYNC
SDATA_OUT
GPIO0
GPIO3
SENSE A
SENSE B

47

EAPD

48

SPDIFO

2 33_0402_5%

37

LINE1_VREFO
RESET#

R421 1

(14)

MIC1_VREFO_R

32

MIC2_VREFO

30

VREF

27

JDREF

40

DVSS1
DVSS2

DGND

+3VS

10mil
MIC1_VREFO_L
MIC1_VREFO_R

10mil
1

NC

33

AVSS1
AVSS2

26
42

C585
10U_0805_10V4Z
2
R409
20K_0402_1%

AGND

1000P_0402_50V7K
2

C688
1

1000P_0402_50V7K
2

C689
1

1000P_0402_50V7K
2

C690
1

1000P_0402_50V7K
2

1
R404

2
0_0805_5%

1
R406

2
0_0805_5%

1
R405

Issued Date

2
0_0805_5%

GND

GNDA

Compal Electronics, Inc.

Compal Secret Data


2006/08/18

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C687
1

+5VS

MIC2_VREFO
CODEC_VREF

Security Classification

EMI Added 2007/4/12

HDA_SDIN0 (14)
WOOFER_MONO (33)

ALC268-GR_LQFP48_9X9

C387
22P_0402_50V8J

+3VS

C610

MIC1_L

2
3
13
34

4
7

C609

L47
MBK1608301YZF_0603
2
1

0.1U_0402_16V4Z

NC

11

(14) HDA_SDOUT_AUDIO

15

MIC1_C_L
21
4.7U_0805_6.3V6K
MIC1_C_R
22
4.7U_0805_6.3V6K
MONO_IN
12

(14) HDA_SYNC_AUDIO

C607

14

MIC2_C_L
16
4.7U_0805_6.3V6K
MIC2_C_R
17
4.7U_0805_6.3V6K
LINE_C_L
23
4.7U_0805_6.3V6K
LINE_C_R
24
4.7U_0805_6.3V6K
18

(14) HDA_RST_AUDIO#

U30

+3VS_DVDD

0.1U_0402_16V4Z

(33) INT_MIC_R

39.2K

20mil

40mil

0.1U_0402_16V4Z
L44 1
2
FBM-L11-160808-800LMT_0603 1
1
1
<BOM Structure>
C590
C586
C589
10U_0805_10V4Z
2
2
2
0.1U_0402_16V4Z

C597

SENSE B

R407
10K_0402_1%

PVT Modify 2007/3/12

1U_0603_10V4Z
1
2
R427
2SC2411K_SOT23 2.4K_0402_5%

AVDD1

SENSE A

C588
10U_0805_10V4Z

47K_0402_5%

+VDDA

Impedance

C601

MONO_IN

+AVDD_AC97

Sense Pin

R518

0.1U_0402_16V4Z

C611
1
2

DVDD_IO

560_0402_5%
1

C617 1
1U_0603_10V4Z

(15) MCP_SPKR

GND

4.85V

47K_0402_5%

CNOISE

+VDDA

R408
30K_0402_1%

Q42

2
B

560_0402_5%
R517

SENSE or ADJ

40mil

2
1

C634 1
1U_0603_10V4Z

SI9182DH-AD_MSOP8

R428
10K_0402_5%

(27,28) BEEP#

VOUT

+5VS

(output = 250 mA)

60mil

1
R418
10K_0402_5%

Title

HD Audio Codec ALC268


Size
B

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P

Date:

Friday, April 20, 2007


G

Sheet

32
H

of

42

PVT Modify 2007/3/12

Speaker
Conn.
FBM-11-160808-700T_0603

L63
+3VS

R523 1

2 0_0603_5%

+5VAMP

R524 1

2 0_0603_5%
@
1
C679
0.1U_0402_16V4Z

HPF Fc = 604Hz

+5VAMP

W=40mil
1

1
2

3
4

G1
G2

ACES_88266-02001

L66

VDD

19

20
10
PVDD
PVDD

11

U31

HVDD

AMP_LEFT_C-1
1
2
C599
0.47U_0603_16V4Z
R414
R416

(32) AMP_LEFT

1
2

SPKR+
SPKR-

2 AMP_RIGHT_C
1U_0603_10V4Z
2 AMP_LEFT_C
1U_0603_10V4Z

1
C604
1
C600

JP3

SPK_L+
2
SPK_L2
FBM-11-160808-700T_0603

1
1

L65
AMP_RIGHT_C-1

CVDD

(32) AMP_RIGHT

L64

C606
C595
0.1U_0402_16V4Z
2
2
4.7U_0805_10V4Z

2
C603
0.47U_0603_16V4Z
1
2

SPKL+
SPKL-

FBM-11-160808-700T_0603
SPK_R+
2
SPK_R2
FBM-11-160808-700T_0603

1
1

JP34

20mil

1
2

1
2

3
4

G1
G2

ACES_88266-02001

VOL_AMP

26

17
18

CVSS

15

VSS

16

GND
PGND
PGND
CGND
GND

2
23
7
13
29

/SD

R422
30K_0402_5%

C592
1U_0603_10V4Z
2

VOL_AMP

2
2

C598

R420
100K_0402_1%

C680
0.01U_0402_16V7K
D
1

28

BEEP

12
14

CP+
CP-

25

BIAS

SPDIF_PLUG#

C591
1U_0603_10V4Z

Q43
AO3413_SOT23-3

2.2U_0805_10V6K
2

2
G
Q53
2N7002_SOT23

S/PDIF Out JACK


LINE Out/Headphone Out
C468

(27,28) EC_MUTE
+3VALW

EC_MUTE

31
3

51_0402_1%
HPOUT_L_1
51_0402_1%
HPOUT_R_1

JP4
0.1U_0402_16V4Z

BATT_GRN_LED# (27,28,30)
BATT_AMB_LED# (27,28,30)
PWR_LED# (30)
PWR_SUSP_LED# (30)
+3VALW
LID_SW# (27,28,30)
+5VALW

1
2

1
2

G1
G2

3
4

MIC_R 1
L57 1
L58

2 INT_MIC_R
2MBK1608121YZF_0603
MBK1608121YZF_0603
1

C460

C65

SINGA_2SJ-E373-T01

JP33

15mil

8
7
LINEIN_PLUG#

(32) LINEIN_PLUG#

LINE_R
LINE_L

(32) LINE_L

L51
1

FBM-11-160808-700T_0603
LINE_R_R
2

1
L48

LINE_L_R
2
FBM-11-160808-700T_0603
1
1

MIC_R
2

220P_0402_50V7K

(32) LINE_R

C613
220P_0402_50V7K
2

@
PSOT24C-LF-T7_SOT23-3
D28

5
4
3
6
2
1

SINGA_2SJ-E351-S03

C614
220P_0402_50V7K

LINE-IN JACK
(HDA Jack)

5
4

SW1
XRE094PHDINB1-2-12-E-7016_3P

U28

1
2
3
4
5
6
7

1
C562
2

(32) MIC1_R

U27
CD1#
D1
CP1
SD1#
Q1
Q1#
GND

VCC
CD2#
D2
CP2
SD2#
Q2
Q2#

14
13
12
11
10
09
08

(32) MIC1_L

TC74LCX74FT_TSSOP14

1
2

2 FBM-11-160808-700T_0603

C616
220P_0402_50V7K

5
4

MIC2_R_1

3
6
2
1

1
C615
220P_0402_50V7K

SINGA_2SJ-E351-S01

MIC JACK

(HDA Jack)

ENCODER_DIR (27,28)
ENCODER_PULSE (27,28)

Volume Control Circuit

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Issued Date

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

MIC_PLUG#

MIC2_L_1

2 FBM-11-160808-700T_0603
<BOM Structure>

C558
1

1
L49
1
L50

8
7

(32) MIC_PLUG#
R425
2.2K_0402_5%

R426
2.2K_0402_5%

2
NC7SZ14P5X_NL_SC70-5

1
2
R399 10K_0402_5%
1
C559

+3VS
0.1U_0402_16V4Z
C563

JP32

MIC1_VREFO_R

5
P

NC

0.1U_0402_16V4Z

MIC1_VREFO_L

1
2
R402 10K_0402_5%

0.1U_0402_16V4Z

GND

+3VS

COM

C557
1

0.01U_0402_16V7K

R403
100K_0402_5%
R401
10K_0402_5%

GND

R400
10K_0402_5%

0.01U_0402_16V7K

+3VS

1
2
6
3

INT_MIC_R (32)

15mil

+3VS

JP31

2
100P_0402_50V8J

ACES_88266-02001

0.1U_0402_16V4Z

HP_PLUG# (32)

20_0402_5%

4
7
8
10

C620

S/PDIF Jack
LINE-IN Jack
MIC-IN Jack
Sub-Woofer
Lid Switch

1
L36
1
L35

R106
2.2K_0402_5%

C621

R565 1

(32) SPDIF
+5VSPDIF

+5VAMP

BATT_GRN_LED#
BATT_AMB_LED#
PWR_LED#
PWR_SUSP_LED#

ACES_88107-30001

GNDGND

32

MIC2_VREFO

+5VSPDIF

SPDIF_PLUG#
HPP_PLUG#
LINEIN_PLUG#
MIC_PLUG#

@
2 0_0402_5%

R5641

330P_0402_50V7K
1
1 330P_0402_50V7K
HPP_PLUG#
2 HPOUT_L_2
FBM-11-160808-700T_0603
2 HPOUT_R_2
FBM-11-160808-700T_0603
SPDIF_PLUG#

MIC2_R_1
MIC2_L_1

HPOUT_R

PVT Modify 2007/3/12


FOR EMI

0.1U_0402_16V4Z

+5VAMP
(32) WOOFER_MONO

R284

Int MIC Conn.

C488

SPDIF

C467

JP13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2N7002_SOT23

To AUDIO/B Connector
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2N7002_SOT23
S

PVT Modify 2007/3/12

R285

LINE_R_R
LINE_L_R

20mil

HPOUT_L

HPOUT_L_2
HPOUT_R_2

APA2057A_TSSOP28
EC_MUTE

+5VSPDIF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

2
G
Q61

2
G
Q60

+5VSPDIF

PVT Modify 2007/3/12

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

R549
100K_0402_5%

R468
100K_0402_5%

39K_0402_5%

HP_R
HP_L

HP_RIGHT_R
39K_0402_5% HP_LEFT_R

MP Modify 2007/4/12
HP_PLUG#

INR_H
INL_H

HPOUT_R
HPOUT_L

+5VAMP
+5VAMP

1 1

4
6

SPKL+
SPKL-

HP EN

+5VAMP
2.2U_0805_10V6K
HP_RIGHT_C 1
1
2.2U_0805_10V6K
R412
HP_LEFT_C
1
1
R410

LOUT+
LOUT-

24

SPKR+
SPKR-

8
9

2 100K_0402_5%

22
21

/AMP EN

R417 1

ROUT+
ROUT-

(32) HP_LEFT

27

(32) HP_RIGHT
+5VAMP

2
C596
HP_RIGHT
C593
HP_LEFT

INR_A
INL_A

2 100K_0402_5%

Gain= 14dB

3
5
R423 1

560_0402_5%

560_0402_5%

Title

Amplifier & Audio Jack


Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
E

33

of

42

+5VALW

+1.2VALW TO +1.2V_HT
2

+3VALW TO +3VS

+1.2V_HT

R39
10K_0402_5%

+3VS

SUSP
2
G
Q5
2N7002_SOT23

Q6
2N7002_SOT23

+VSB

10U_0805_10V4Z

R330
@ 1M_0402_1%

C505
0.1U_0603_25V7K

2VLDT_EN#
G
Q7
2N7002_SOT23

R31
100K_0402_5%

2N7002_SOT23

2 VLDT_EN#
G
Q41
2N7002_SOT23

1
R326
100K_0402_5%
1
2

1.2VHT_GATE

SI4800BDY_SO8
C49

2
G
Q8

(15) VLDT_EN

+5VALW

SUSP

1
2
3
4

R20
@ 1M_0402_1%

C24
0.1U_0603_25V7K

10U_0805_10V4Z

C19

2
G

SI4800BDY_SO8

S
S
S
G

+VSB

D
D
D
D

5VS_GATE
20K_0402_1%

U2

8
7
6
5

VLDT_EN#
R42
470_0402_5%

10U_0805_10V4Z

C32

R22
470_0402_5%

R21
100K_0402_5%
1
2

1U_0603_10V4Z

R28

+1.2VALW

1
2
3
4

S
S
S
G

1U_0603_10V4Z

C33

D
D
D
D

8
7
6
5

10U_0805_10V4Z

+3VS
C21

U1

C15

+3VALW

+1.2V_HT

+1.2VALW TO +1.2VS

+5VALW TO +5VS

5VS_GATE

2 SUSP
G
Q32
2N7002_SOT23

C158

10U_0805_10V4Z

1U_0603_10V4Z

2 SUSP
G
Q13
2N7002_SOT23

2 R363
60.4K_0402_1%

1
2

R227
10K_0402_5%

2
G
Q25

+3VALW TO +3V_SB(MCP67 AUX Power)


+3VALW
+1.8VS

4.7U_0805_10V4Z

1U_0603_10V4Z

C638

C636

10U_0805_10V4Z
2
2
1U_0603_10V4Z

2
10U_0805_10V4Z

5VS_GATE

C392
0.1U_0603_25V7K

1
D

SBPWR_EN#

2
Q49G
2N7002_SOT23

2 SBPWR_EN#
G
Q48
2N7002_SOT23

R457
10K_0402_5%

C639
0.1U_0603_25V7K

SBPWR_EN#

(13) SBPWR_EN#

+5VALW

2 R266
60.4K_0402_1%

3V_GATE

2
1
R447
200K_0402_5%

+VSB

2 SUSP
G
Q31
2N7002_SOT23

R446
470_0603_5%

C395
4.7U_0805_10V4Z

1
2
3
4

S
S
S
G

SI4800BDY_SO8

C390

SI4856ADY-T1-E3_SO8

C637

D
D
D
D

C391

R264
470_0402_5%

8
7
6
5

+1.8VS

1
2
3
4

2N7002_SOT23

U35

U17

S
S
S
G

+1.8V

D
D
D
D

R223
100K_0402_5%

+3V

1
SYSON

SYSON#

+1.8V TO +1.8VS

C515
0.1U_0603_25V7K

(26,27,28,40) SYSON

8
7
6
5

1
A

2 SUSP
G
Q17
2N7002_SOT23

2 SYSON#
G
Q20
2N7002_SOT23 @

Compal Secret Data

Security Classification

R185
470_0402_5%

2 SUSP
G
Q22
2N7002_SOT23

R153
470_0402_5% @

R458
100K_0402_5%

2
1

R131
470_0402_5%

R180
470_0402_5%

+1.8V

2
4

+0.9V

+1.5VS

2
G
Q51
S
2N7002_SOT23

(22,27,28,40) SBPWR_EN

+2.5VS

+5VALW

5VS_GATE

(39) SYSON#

2N7002_SOT23

C423
0.1U_0603_25V7K

R272
100K_0402_5%

1
R109
470_0402_5%

C517

22U_0805_6.3V6M

C521

+1.2VS

SI4856ADY-T1-E3_SO8

C419
4.7U_0805_10V4Z

S
S
S
G

1U_0603_10V4Z

D
D
D
D

4.7U_0805_10V4Z

R267
470_0402_5%

C400

C401

2
G
Q34

(23,26,27,28,38) SUSP#

1
2
3
4

2
1

SI4800BDY_SO8

U24

8
7
6
5

1
2
3
4

S
S
S
G

D
D
D
D

+1.2VS

U19

8
7
6
5

SUSP

(39) SUSP

+1.2VALW

+5VS

+5VS

+5VALW

R273
10K_0402_5%

2 SYSON#
G
Q23
2N7002_SOT23

2006/08/18

Issued Date

Deciphered Date

2007/8/18

Title

DC INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

Size
B
Date:

Document Number

Rev
1.0

ICW50 / ICY70 LA-3581P


Friday, April 20, 2007

Sheet
E

34

of

42

PJP1

1
1 2

PR2
1K_1206_5%
1
2

PD1
RLZ24B_LL34

B+

100K_0402_5%

PR7
1K_1206_5%
1
2

PR6

E&T_4510-E04C-01R

PR4
1K_1206_5%
1
2

RLS4148_LLDS2

PQ1
TP0610K-T1-E3_SOT23-3
1

PR5
1

100K_0402_5%

PR3
1K_1206_5%
1
2

PD2

VIN
2

560P_0402_50V7K

PR1
10_1206_5%
PC4
2
1

PC3
2
1

12P_0402_50V8J

PC2
2
1

VIN

FBMA-L18-453215-900LMA90T_1812
1
2

12P_0402_50V8J

PL1

ADPIN

PC1
1

G1

560P_0402_50V7K

G2

1
PR8
100K_0402_5%

(27,28,38) ACOFF

PR9
33_1206_5%

VS

PQ3
DTC115EUA_SC70-3

PQ2
DTC115EUA_SC70-3

RLS4148_LLDS2

1 2

1 1

PD4
RB751V-40TE17_SOD323-2
2
1

BATT+

PD3

VIN

(30,31) 51ON#

PQ4
TP0610K-T1-E3_SOT23-3
1

PC6
0.1U_0603_25V7K

PR11
22K_0402_5%
1
2

PR10
100K_0402_5%

0.22U_1206_25V7K

PC5
2
1

CHGRTCP

B+

PR12
2.2M_0402_5%
1

VL

PR13
499K_0402_1%

ACIN

2006/09/01

PACIN (37,38)

PQ6
DTC115EUA_SC70-3

@ PR22
66.5K_0402_1%

+5VALW

Deciphered Date

Compal Electronics, Inc.


2007/09/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

PR21
47K_0402_5%
2PQ5
2
1
G RHU002N06_SOT323-3

Compal Secret Data

Security Classification
Issued Date

RTCVREF

PR20
34K_0402_1%
2
1

BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

PR19
499K_0402_1%

Precharge detector
Min.
typ.
Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

PR18
191K_0402_1%

PC9
0.01U_0402_25V7K

PC10
0.1U_0603_25V7K

PRG++ 2

32.4

RB715F_SOT323-3

PC7
1U_0805_25V4Z

8
1

PC11
1000P_0402_50V7K

(38) ACON

P
1

GND
1

PU2A
LM393DR_SO8

IN

OUT

560_0603_5% 560_0603_5%

PD5

PR17

2 1

PC8
1

4.7U_0805_6.3V6K

PR16
+CHGRTC

(6,36,37) MAINPWON

PU1 G920AT24U_SOT89-3
3

PR14
100K_0402_1%

PR15
200_0805_5%

RTCVREF

3.3V

VS

Title

DCIN/DECTOR
Size
B
Date:

Document Number

Rev
1.0

ICW50/ICY70
Sheet

Friday, April 20, 2007


D

35

of

42

MAX8744_B+

B+

MAX8744_B+

PL2

5
6
7
8

PC16
2200P_0402_50V7K
2
1

D
D
D
D

PQ8
SI4800BDY-T1-E3_SO8

4
3
2
1

G
S
S
S

PC15
4.7U_1206_25V6K
2
1

PC14
4.7U_1206_25V6K
2
1

8
7
6
5
S
S
S
G

D
D
D
D

1
2
3
4

PQ7
SI4800BDY-T1-E3_SO8

PC13
4.7U_1206_25V6K
2
1

PC12
2200P_0402_50V7K
2
1

FBMA-L18-453215-900LMA90T_1812
1
2

MAX8744ETJ+_TQFN32_5X5

PGND

19

29

CSH3
CSH5

12

CSH5

CSL5

13

CSL5

FB5

11

FB5

LDO5

20

SKIP

10

CSL3

30

FB3

PGOOD3

27

PGOOD5

14

ON5

ON3

1
2

1
2

PC29
1U_0603_6.3V6M

GND

ILIM

ILM

FSEL
9

2VREF_8744

<BOM Structure>

ONA

1
2
PR40

PR41
@ 47K_0402_5%

2
1
1

2VREF_8744 1

(6,35,37) MAINPWON

SPOK (37,40)

PR36

0.22U_0603_10V7K

1
+

PR70 0_0402_5%

SHDN

1000P_0402_50V7K

2VREF_8744

@ PR32 0_0402_5%
1
2

FBA

0_0402_5%

PC28

PGOODA

4.7U_0805_6.3V6K
2
1

31

22

PC26
2

OUTA

PC25

PR33
10K_0402_1%
1
2

32

VL

+5VALWP

DRVA

REF

A3 modify

PR35
200K_0402_5%
1
2

PR34
100K_0402_5%
21
2

499K_0402_1%

PR37

2VREF_8744
PC24 0.22U_0603_16V7K
2

@ PC97
0.1U_0603_25V7K

CSL3

28

PL4
S COIL 8.2UH +-20% MPL73-8R2 4A

CSH3

A2 modify
2

18

DL5

PC27
150U_D2_6.3VM

DL3

PR31
15.4K_0402_1%

23

PR29
825_0402_1%

17

LX5

PR27
2.21K_0402_1%
2
1

LX3

PC22
0.22U_0603_16V7K
1
2

24

DL3

0.1U_0603_25V7K
LX5

LX3

12VREF_8744

0_0402_5%
3

+5VALWP Ipeak = 7.49A ; Imax = 5.3A


DCR = 68m ohm(max) ; Rcs = 16.04m ohm
DCR = 64m ohm(typical) ; Rcs = 15.06m ohm
Ilimit = 185mV/16.04m ~ 215mV/15.06m
= 11.53A ~ 14.28A

@
PC30
0.047U_0402_16V7K

Iocp(mean) = Ilimit -Delta I/2


=10.032A~12.782A

Delta I=((Vin-Vo)*D)/(F*L)
=((19-3.3)*(3.3/19))/(300K*8.2U)
=1.108A

Delta I=((Vin-Vo)*D)/(F*L)
=((19-5)*(5/19))/(300K*8.2U)
=1.498A

Notes :
4

PR177
4.7_1206_5%

PR25
BST5A 2
2.2_0402_5%

15

2
1

BST5

PC20

DCR = 68m ohm(max) ; Rcs = 16.04m ohm

Ilimit = 185mV/16.04m ~ 215mV/15.06m


= 11.53A ~ 14.28A
Iocp(mean) = Ilimit -Delta I/2 =10.442A~13.172A

BST3

26

DH5

PC138
680P_0402_50V7K

1 BST3A
2.2_0402_5%

@ PR38
0_0402_5%

DCR = 64m ohm(typical) ; Rcs = 15.06m ohm

16

PR39
0_0402_5%

+3VALWP Ipeak = 8.57A; Imax = 6A

DH5

0.1U_0603_25V7K

2
PZD1
RLZ5.1B_LL34

DH3

PQ9
5
6
7
8

25

SI4810BDY-T1-E3_SO8
4 G
D
3 S
D
2 S
D
1 S
D

DH3

FB3

21

PC19

0.1U_0603_25V7K

PC23
1000P_0402_50V7K

IN

EP

PQ10
SI4810BDY-T1-E3_SO8
1 S
D 8
2 S
D 7
3 S
D 6
4 G
D 5

33
PR24

@ PC93

VS

PC17
1U_1206_25V7K
1
2

PU3

PC21
0.22U_0603_16V7K

680P_0402_50V7K

PC137

PR176
1
4.7_1206_5%
1
2

PR28
825_0402_1%
2
1

A2 modify

PR30
10K_0402_1%

PR26
6.81K_0402_1%
1
2

PC18
330U_D3L_6.3VM_R25M

+3VALWP

PR23
2.21K_0402_1%
1
2

PL3
S COIL 8.2UH +-20% MPL73-8R2 4A
1
2

fESR<=fOSC/ ; fESR=1/(2**RESR*COUT)

ON3 = REF --->3.3V starts up delay 2ms after 5V starts up


Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/09/01

Deciphered Date

2007/09/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

+5VALWP/+3VALWP
Size Document Number
Custom
ICW50/ICY70
Date:

Rev
1.0
Sheet

Friday, April 20, 2007


D

36

of

42

BATT++

BATT+

PH1 under CPU botten side :


CPU thermal protection at 90 degree C
Recovery at 70 degree C

PL7
HCB4532KF-800T90_1812
1
2

PC56
0.01U_0402_25V7K

PC57
1000P_0603_50V7K

VL

SUYIN_200275MR007G161ZL

PC59
1000P_0402_50V7K

+3VALWP

PR73
150K_0402_1%

TM_REF1

MAINPWON (6,35,36)

PU2B
LM393DR_SO8

PR81
150K_0402_1%
2
1
VL

PR82
1K_0603_1%

PR77
82.5K_0603_1%
1
2

2
2

6.49K_0603_1%

PR80

PR76
442K_0603_1%
2

PC60
1U_0805_16V7K
2
1

PH1
100K_0603_1%_TH11-4H104FT
2
1

100_0603_1%

1
PR78

1
2

PR79

SMART
Battery:
1.BATT+
2.BATT+
3.TS
4.SMC
5.SMD
6.GND
7.GND

100_0603_1%

PJP2 battery connector

PC58
0.1U_0603_25V7K

PR75
9.76K_0402_1%

TSA
EC_SMC1
EC_SMD1

1
2
3
4
5
6
7

PR83
150K_0402_1%

VL

VS

PJP2

BATT_TEMP (27,28)
EC_SMB_CK1 (18,27,28,29)
EC_SMB_DA1 (18,27,28,29)

PR84
1M_0402_1%
1
2
VIN

VIN

1
3

8
P

PACIN (35,38)

G
LM393DR_SO8

PR90
10K_0402_5%

PZD2
RLZ4.3B_LL34

RTCVREF

PQ26
RHU002N06_SOT323-3

2
G
1

(36,40) SPOK

ACIN (15,18,27,28)

PACIN

PU6B

O
4

Vin Detector
Min.
typ.
Max.
H-->L 16.976V 17.257V 17.728V
L-->H 17.430V 17.901V 18.384V

PR94
100K_0402_5%
PR95
0_0402_5%
1
2

ACIN

PC64
0.1U_0603_25V7K

PR87
10K_0402_5%
1
2

PR92
10K_0402_5%
2
1

1
2

PU6A

PR93
22K_0402_5%
1
2

VL

PC63
0.22U_1206_25V7K

PC62
0.1U_0603_25V7K

1
PR91
100K_0402_5%

1
2

2
3

B+

PR89
20K_0402_1%
2
1

PQ25
TP0610K-T1-E3_SOT23-3
+VSBP
1

PC61
1000P_0402_50V7K

PR88
22K_0402_5%
1
2

PR86
10K_0402_5%

VS

PR85
84.5K_0402_1%

LM393DR_SO8

PC65
0.1U_0603_25V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/09/01

Deciphered Date

2007/09/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

BATTERY CONN. / OTP


Size
B
Date:

Document Number

Rev
1.0

ICW50/ICY70
Sheet

Friday, April 20, 2007


D

37

of

42

CP = 85%*Iada ; CP = 4.07A
B+

PL5

CSIN

1
1

ACSET ACPRN

23

EN

22

CSIN

VCOMP

CSIP

19

PC44
1
0.1U_0603_25V7K
LX_CHG
DH_CHG

PQ20
SI4800BDY-T1-E3_SO8

PR64
274K_0402_1%
1
2

PQ24
SI2301BDS-T1-E3_SOT23-3

ACLIM

VDDP

15

VADJ

LGATE

14

GND

PGND

13

G
S
S
S

Normal 4S LI-ON Cells

16800mV

LOW

HIGH

16.80V

Normal 3S LI-ON Cells

12600mV

HIGH

HIGH

12.60V

HIGH

HIGH

12.60V

2
1

Issued Date

2006/09/01

(27,28) 65W/90W#

Deciphered Date

UMA@
2
G
PQ47
RHU002N06_SOT323-3

Compal Electronics, Inc.


2007/09/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

PC55
0.01U_0402_25V7K

PR69
200K_0402_1%

LM358ADR_SO8

PR174
20K_0402_1%
2

Compal Secret Data

Security Classification

6251aclim

11.5K_0402_1%

PR60
6251VREF 1

PR67
300K_0603_0.1%

2
8
P
G

PU5A
3

BATT-OVP=0.1487*BATT+

Wake up charge while


no communication

4
3
2
1
1

LI-3S :13.50V--BATT-OVP=2.007V
PR66
845K_0603_1%

LM358ADR_SO8

BATT-OVP=0.1487*BATT+

LI-4S :18.0V--BATT-OVP=2.677V

BATT+

P
4

12.90V

PU5B
5

0
G

17.20V

PC54
0.01U_0402_25V7K

LOW

(27,28) BATT_OVP

PR68
10K_0402_5%
2

PC53
0.01U_0402_25V7K

LOW

@
PQ46
2SC2411K_SOT23-3

@
PR171
20K_0402_1%

1
8

CV mode

VS

6251_EN

2
1

S
PC133
0.01U_0402_25V7K

A3 modify
PR170
100K_0402_1%
@
C
2
B
E

VS

CHGSEL

LOW

5
6
7
8

PQ45
RHU002N06_SOT323-3

2
G

(27,28) Calibrate

3S/4S#

HIGH

OVP voltage :

PR63 UMA@
2.37K_0402_1%

13050mV

PC136
680P_0402_50V7K
@

PC52
4.7U_0805_6.3V6K

2
1

CSON

2800mAH 3S pack

PR56
0.02_2512_1%

IREF=0.43V~3.24V

17400mV

ISL6251AHAZ-T_QSOP24

IREF=0.7224*Icharge

2800mAH 4S pack

1
26251VDD
4.7_0603_5%
PR62

6251VREF

CC=0.6~4.48A

Charging Voltage
(0x15)

6251VDDP
DL_CHG

PR169
274K_0402_1%

2
(27,28) CHGSEL

BATT Type

BST_CHG 1
2
2.2_0603_5%

BATT+
4

10

PR175
4.7_1206_5%
@

16

BOOT

CHLIM

PC48
BST_CHGA 2
1
0.1U_0603_25V7K
PD9
RB751V-40TE17_SOD323-2

PL6
10UH_PCMB104T-100MS_6A_20%
CHG
1
2

D
D
D
D

17

2.2_0603_5%

G
S
S
S

UGATE

2
PR173

PQ22
SI4800BDY-T1-E3_SO8

VREF

12

CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.502V, Iinput=4.07A

PHASE

11

PR65
100K_0402_1%

6251aclim

6251VREF

ICM

18

2 PACIN
G PQ18
RHU002N06_SOT323-3

(27,28,35) ACOFF

0.01U_0402_25V7K

PR61
100K_0402_1%

PR58

0.1U_0603_25V7K

PQ23
DTC115EUA_SC70-3

4
3
2
1

6251VREF
PC47
1
2

PR59
80.6K_0402_1%
2
1
1

(27,28) IREF

1 PR55
2
100_0402_1%

3
5
6
7
8

CSOP

1
PR53 20_0603_5%

PQ21
RHU002N06_SOT323-3
(27,28) ADP_I

PC51
1

ACON

1 PR54
2
10K_0402_1%
1
2
PC46
100P_0402_50V8J

ICOMP

20

21

CSOP

CELLS

CSON

1SS355_SOD323-2
PR172 20_0603_5%
1
2
PC41
0.047U_0603_16V7K
1
2
PR52 20_0603_5%

CSON

PC37
0.1U_0603_25V7K

DCIN

PC50
10U_1206_25V6M

24

DCIN

VIN

200K_0402_1%

PQ15
DTC115EUA_SC70-3
PD8
2
1
2

PC49
10U_1206_25V6M

VDD

2.2U_0603_6.3V6K

2
1

PR47

2
1

2
G

(35) ACON

(35,37) PACIN

PR57
22K_0402_5%
PACIN 1
2

ACOFF (27,28,35)

PU4

PC45
1
2

SUSP# (23,26,27,28,34)

0.01U_0402_25V7K

1SS355_SOD323-2

3
RB715F_SOT323-3

6251_EN 3

1
2
PC43 6800P_0402_25V7K

VIN

PD6

PR46
10K_0402_1%

100K_0402_1%

2
1
PR50

@ PC42
@PC42
680P_0402_50V7K
CSON 1
2

PR45
47K_0402_1%
1
2

2FSTCHG

PR51
150K_0402_1%

(27,28) 3S/4S#

PQ17
DTC115EUA_SC70-3

D
3

2
1

6251VDD 1
PR49
47K_0402_5%

PQ19
RHU002N06_SOT323-3
3

2 PR48
1
10K_0402_5%
1
2
PC132
0.1U_0402_16V7K

(27,28) FSTCHG

2
G

100K_0402_1%

A3 modify

PD15

PD14 1SS355TE-17_SOD323-2 6251VDD


1
2

PQ44
DTC115EUA_SC70-3

PR168

PC38

PQ14
DTA144EUA_SC70-3

A3 modify

DCIN

8
7
6
5

P3
PR167
100K_0402_1%
2
1

PR44
200K_0402_1%

PQ16
DTC115EUA_SC70-3

PC31
10U_1206_25V6M
2
1

PQ43 TP0610K-T1-E3_SOT23-3

PC36
5600P_0402_25V7K
1
2

CSIP

1
2
3

PC35
0.1U_0603_25V7K

PR43
47K_0402_1%

1
2
3

PC40
0.1U_0603_25V7K

PQ13
AO4407_SO8

CHG_B+

FBMA-L18-453215-900LMA90T_1812
1
2

PR42
0.02_2512_1%

P3
8
7
6
5

PQ12
AO4407_SO8
1
2
3

PC34
2200P_0402_25V7K
2
1

1
2
3

D
D
D
D

P2

8
7
6
5

PC33
0.1U_0603_25V7K
2
1

ADP_I = 19.9*Iadapter*Rsense
PQ11
AO4407_SO8

VIN

PC32
10U_1206_25V6M
2
1

Iada=0~4.74A(90W)

Title

CHARGER
Size

Document Number

Rev
1.0

ICW50/ICY70
Date:

Friday, April 20, 2007

Sheet
D

38

of

42

+3VALW

PJP3
JUMP_43X118

PJP4
JUMP_43X118

GND

+2.5VSP

VFB

AGND

VTT

VCCA

VTT

REFEN

PC74
0.1U_0603_25V7K

1
PC72
22U_1206_10V6M

PR98
60.4K_0402_1%
PC73
0.047U_0402_16V7K

RHU002N06_SOT323-3

PC70
22U_1206_10V6M

+0.9VP
2

2
G

PQ27

PC71
0.1U_0603_25V7K
2
1

PR100
1K_0402_1%
1

(34) SYSON#

RT9173DPSP_SO8
PR99
0_0402_5%
1
2

PGND

PC69
1U_0603_16V6K
1
2

NC

VIN

VOUT

PR96
1K_0402_1%

NC

PC68
1U_0603_6.3V6M

REFEN

PU8

CM8562IS_PSOP8

PR101
200K_0402_1%

NC

+3VALW

PR97
10_0603_1%

GND

RTCVREF

VCNTL

PC67
10U_0805_6.3V6M

VIN

PU7
1

AGND

+1.8V

+5VALW

PC66
10U_0805_6.3V6M
1
2

+1.8V

2PQ28
1
2
G RHU002N06_SOT323-3
PR102
0_0402_5%

SUSP (34)

+1.8V

+3VALW

+1.8VP

+1.8V

PJP6

PJP7
JUMP_43X118

PJP5

+3VALWP

JUMP_43X118
1

JUMP_43X118

JUMP_43X118

+1.5VS

VIN

PGND

VFB

AGND

VTT

VCCA

VTT

REFEN

PJP11

+VSBP

PJP12

+VSB

PJP13

PR104
60.4K_0402_1%
PC78
0.047U_0402_16V7K

PC77
22U_1206_10V6M

+0.9V

+1.5VSP

JUMP_43X118

PC79
0.1U_0603_25V7K

RTCVREF

PC76
1U_0603_16V6K
1
2

+1.5VSP

+1.2VALW

+5VALW
PU9

CM8562IS_PSOP8

PR105
51K_0402_1%

PR103
10_0603_1%

+2.5VS

JUMP_43X118

JUMP_43X118

+0.9VP

JUMP_43X118

PJP10

1
PJP9

AGND

+2.5VSP

PJP8

PC75
10U_0805_6.3V6M
1
2

+5VALW

+1.2VALWP

+5VALWP

JUMP_43X118
1

2PQ29
1
2
G RHU002N06_SOT323-3
PR106
0_0402_5%

SUSP (34)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/09/01

2007/09/01

Deciphered Date

+0.9VSP/+1.5VSP/+2.5VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size Document Number


Custom ICW50/ICY70
Date:

Rev
1.0

Friday, April 20, 2007

Sheet
1

39

of

42

+5VALW

+3VALW
BST_1.8V-1

LX_1.2V

11

VCCA2

FB_1.2V

12

FB2

13

PGD2

ILIM2

18

VDDP2

17

ILIM_1.2V
1 PR119 2
30.1K_0402_1%
+5VALW

DL2

16

DL_1.2V

PGND2

15

SC413TSTRT_TSSOP28

+3VALW

2
1

G
S
S
S

1
+

PC98
1U_0603_10V6K

PR121
10K_0402_1%

PC99
0.1U_0603_25V7K

@
PR123
100K_0402_5%

(26,27,28,34) SYSON

to VSSA1 and VOUT1 PIN

FB_1.2V

VFB=0.5V

Close to IC Side
Differential routing of feedback

VSSA2

PC95
33P_0402_50V8K

(22,27,28,34) SBPWR_EN

14

PQ33
SI4810BDY-T1-E3_SO8

+1.2VALWP

Vout_1.2VALWP

PC96

19

330U_D2_2.5VY_R15M

LX2

Maximum continuous current=>6A


PL10
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

1
PR120
15K_0402_1%

VOUT2

VCCA_1.2

PR117
0_0402_5%
1
2DH_1.2V-1

0.1U_0603_25V7K

20

4
3
2
1

21

DH2

(36,37) SPOK

PR165
0_0402_5%
1
2
PR122
0_0402_5%
1
2

BST_1.2V
1 PR115 2
2.2_0402_5%
DH_1.2V

BST2

TON2

EN/PSV2

PC91
1
2

22

PQ31
SI4800BDY-T1-E3_SO8

EN/PSV1

BST1

PR112
2
1
820K_0402_5%

Vout_1.8V

23

SC413_B+

PC88
4.7U_1206_25V6K

24

TON1

4.7U_1206_25V6K

VOUT1

DH1

PC87
1

LX1

SC413_B+

VCCA_1.8

5
6
7
8

25

D
D
D
D

VCCA1

1
2
3

ILIM1

MEM_VLD (15,31)

PC86
1000P_0402_50V7K
1
2

S
S
S

PC94
1000P_0402_50V7K

Vout_1.2VALWP 10

FB_1.8V

26

5
6
7
8

PR116
1M_0402_5%

PR118
10K_0402_1%

SC413_B+ 2

FB1

VDDP1

D
D
D
D

0.1U_0603_25V7K
PQ32
FDS6670AS_NL_SO8

27

G
S
S
S

8
7
6
5
D
D
D
D

FB_1.8V

DH_1.8V
6
PR114
2 BST_1.8V 7
2.2_0402_5%
8

28

PGD1

DL1

4
3
2
1

0_0402_5%

@ PR166
0_0402_5%
1
2

VSSA1

PGND1

Close to IC Side

Differential routing of feedback to VSSA2 and VOUT2 PIN

PC100
0.1U_0603_25V7K

PR124
0_0402_5%
1

DH_1.8V-1
1

1
2

1
2

PC90
33P_0402_50V8K

@
PR109
100K_0402_5%

S
S
S
G

DL_1.8V
2
PC85
1
2 +5VALW 3
1U_0603_10V6K
1
2 ILIM_1.8V
4
PR111 30.1K_0402_1%
LX_1.8V
5

PC89
1
2

PC92
330U_D2_2.5VY_R15M

PR113
26.1K_0402_1%

Vout_1.8V

1
2
3
4

PL9
1UH_SIL104-1R0-R_11A_30%
1
2

+1.8VP

BST_1.2V-1

PQ30
SI4800BDY-T1-E3_SO8

PR110

Maximum continuous current=>6A

VCCA_1.2

2
8
7
6
5

VCCA_1.8

PU10

D
D
D
D

1
2

PC84
4.7U_1206_25V6K

PC83
2
1

4.7U_1206_25V6K

1
2
FBMA-L11-322513-151LMA50T_1210

SC413_B+

PL8

PD13
CHP202UPT_SOT323-3

B+

PR108
10_0603_5%

PR107
10_0603_5%

PC82
1U_0603_10V6K
2
1

PC80
2.2U_0603_6.3V6K

PC81
1U_0603_10V6K

@ PR164
0_0402_5%

VFB=0.5V
VFB=0.5V
Vo=VFB*(1+PR120/PR121)=1.25V
Vo=VFB*(1+PR122/PR127)=1.805V
Ipeak=8.54A, Imax=6A
Ipeak=13.82A, Imax=9.68A
Ton=(3.3E-12*(PR116+37K)*(Vout/VBat))+50ns
Ton=(3.3E-12*(PR112+37K)*(Vout/VBat))+50ns
=0.2661us
=3.3E-12*(820K+37K)*(1.805/19)+50ns=0.319us
SI4810BDY:Rds(on)=>Typ:16 mOhm
FDS6670AS:Rds(on)=>Typ:9 mOhm
Max:20 mOhm
Max:11.5 mOhm
Ivalleymin=9E-6*(PR119/Rds(ON)max*1.3)=10.419A
Iocp=Ivalley+Iripple/2
Ivalleymax=11E-6*(PR119/Rds(ON)typ*1.1)=18.8125A
Iripple=(vin-vout)*(Ton/L)=5.485A
Iripple=(vin-vout)*(Ton/L)=2.631A
A

Ivalleymin=9E-6*(PR106/Rds(ON)max*1.4)=16.826A

Iocp=Ivalley+Iripple/2
Ivalleymax=11E-6*(PR106/Rds(ON)typ*1.2)=30.657A

OCP==>11.7345A~20.128A

OCP==>19.5685A~33.3995A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/09/01

Issued Date

Deciphered Date

2007/09/01

+1.8VALWP/+1.2VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size Document Number


Custom
ICW50/ICY70
Date:

Friday, April 20, 2007

Rev
1.0
Sheet
1

40

of

42

B+
CPU_B+

+5VS

DH2

21

DH2

TON

LX2

22

LX2

OFS

DL2

24

DL2

VRHOT#

PGND2

23

CSP2

13

CSN2

14

39

SKIP#

PC121
220P_0402_50V8J

1
3

PQ40
FDV301N_NL_SOT23-3

PC105
100U_25V_M

1
2

1
PR137
4.22K_0402_1%
2

4
3
2
1

PQ38
SI7686DP-T1-E3_SO8

PR158
0_0402_5%
2

3
2

CPU_B+

PR161
10_0402_5%

(6)

PC115
0.22U_0603_16V7K
PR149
0_0402_5%
1
2

2
2

(6) PSI#

0_0402_5%
2

PQ41
FDS6676AS_SO8
G
D 5
S
D 6
S
D 7
S
D 8

PQ39
RHU002N06_SOT323-3

2
G

PR147
1

220P_0402_50V8J

PR156
100_0402_1%

PC126
4700P_0603_50V7K

PC120
1

PR155
200K_0402_1%

20

@ PC129
@PC129
4700P_0402_25V7K
1

CPU_VSS_SENSE

(6) CPU_VCC_SENSE

REF

1
PC117

BST2

10_0402_5%

POUT

PR140
2

PC125
0.01U_0402_25V7K

CCI

PL13
P_0.36H_ETQP4LR36WFC_24A_20%
1
2

CCV

@PC131
@
PC131
1U_0805_16V7K

PR160
4.22K_0402_1%
PH3
PR162
10KB_0603_5%_ERTJ1VR103J
2.1K_0402_1%
1
2
1
2

FB

PC128
680P_0603_50V7K

TIME

11

PC114
4700P_0402_25V7K
1
PR146 20K_0402_1%
2
1
2
470P_0603_50V8J

PC113
680P_0603_50V7K

PR144
2K_0603_1%
FB 1
2

PC122
2
1

40

PR139
PH2
2.1K_0402_1%
10KB_0603_5%_ERTJ1VR103J
1
2
1
2

2200P_0402_50V7K
2
1
PC123
4.7U_1206_25V6K
2
1
PC124
4.7U_1206_25V6K
2
1

IC

PR159
4.7_1206_5%
2

SHDN#

@
AGND

38

1
1
PR157
200K_0402_1%

2
1
PC101
4.7U_1206_25V6K
2
1
PC102
4.7U_1206_25V6K
2
1
PC103
0.01U_0402_25V7K
2
1
PC104
2200P_0402_50V7K
2
1
PC134
330P_0402_50V7K
2
1
PC135
330P_0402_50V7K

18

PR134
4.7_1206_5%
1 1
2

15

GND

PC110
220P_0402_50V8J
PC111
220P_0402_50V8J

FDS6676AS_SO8

CSN1

TWO-PH

FDS6676AS_SO8
PQ36
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

PHASEGD

37

3
2
1

17

5
6
7
8

16

D
D
D
D

CSP1

PQ35

PWRGD

G
S
S
S

27

PC112
4700P_0402_25V7K
2
1

PGND1

PC109
0.22U_0603_16V7K
2
1

D5

4
3
2
1

PQ37
+3VS
RHU002N06_SOT323-3

2
G

PC108
0.01U_0402_25V7K
2
1

DL1

36

PQ42
FDS6676AS_SO8
G
D 5
S
D 6
S
D 7
S
D 8

26

EP

1 2

LX1

DL1

MAX8774_REF 10
2
0.1U_0603_25V7K
7

PR153
0_0402_5%
2
1

PR152
169K_0603_1%

28

D4

1
2
200K_0402_1%

D3 MAX8774GTL+_TQFN40
LX1

35

PL12
P_0.36H_ETQP4LR36WFC_24A_20%
1
2

3
2
1

MAX8774_REF
1
2
PR151
31.6K_0402_1%

1
PC119

PR150
CPU_B+

71.5K_0402_1%
1
PC116
2
1
150P_0402_50V8J

1
2
PC118
0.1U_0603_25V7K

34

+CPU_CORE

4
3
2
1

100K_0402_5%
PR148 10K_0402_1%
1
2

(27,28) POUT

DH1

PR145
100_0402_1%

PR143
2

29

MAX8774_VCC
@ PR142
@PR142
1

DH1

PU11

12

(15) VR_ON

D2

41

33

+
2

4
PR131
0_0402_5%
1
2

0.22U_0603_16V7K

+3VS
PR141
0_0402_5%
1
2

30

PQ34
SI7686DP-T1-E3_SO8

PR154
1
2
2.2_0402_5%

(15) VGATE

BST1

PC127
2
1

(6) VID5

THRM

D1

(6) VID4

D0

32

(6) VID3

PR129
2.2_0402_5%
1
2

31

(6) VID2

25

(6) VID1

VDD

GNDS

2
1
PR127 0_0402_5%
2
1
PR128 0_0402_5%
2
1
PR130 0_0402_5%
2
1
PR132 0_0402_5%
2
1
PR133 0_0402_5%
2
1
PR135
0_0402_5%
1
2
PR136
0_0402_5%
1
2
PR138 100K_0402_1%

(6) VID0

VCC

MAX8774_VCC
19

PC107
2.2U_0603_10V6K

PC106
2.2U_0603_6.3V6K
1
2

PR125 10_0402_5%
2
1

+3VS

PR126
10K_0402_5%
2
1

PL11
FBMA-L18-453215-900LMA90T_1812
1
2

PC130
0.22U_0603_16V7K
1
2
CSP2

PR163
1

0_0402_5%

2006/09/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2007/09/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

+CPU_CORE
Size Document Number
Custom
ICW50/ICY70
Date:

Rev
1.0

Friday, April 20, 2007

Sheet
1

41

of

42

Version change list (P.I.R. List)


Item

Fixed Issue

Rev.

PG#

Page 1 of 1
for HW

Modify List

Date

Phase

BOM Change.

0.4

12

Remove R144, R372, C160, C528.

PVT

Added SSC for Lan TXCLK. (EMI Request)

0.4

12

Added U40, R525, R526, R527, R528, C682.

PVT

Improve Samsung Memory Module compatibility.

0.4

15

Added R540,R541 2.2K pull up +3VS.

PVT

Design Modify.(SCH Change)

0.4

15

Change CRT_DET form GPIO_5 to LID#, Add R78 10K. (Bios Request)

PVT

BCIC0172 : When Reset or Cold Boot MCP67 ACIN EC.

0.4

15

D24 , 47K Pull High.Added R283 200K Pull Down.

PVT

RTC Battery .

0.4

16

Added R539 1K.

PVT

Design Modify.(SCH Change)

0.4

22

Change Q50.G Pin Net Name to SBPWR_EN.

PVT

Added R-C for BUF_25Mhz (EMI Request).

0.4

22

Added R530,C684.

PVT

Design Modify for EMI.

0.4

22

Added L59, L60, L61, L62, C685, C686.

PVT

10

+3VS when enter S3 Mode.

0.4

25,26

Added Q56, Q57, Q58, Q59, R536, R537.

PVT

11

Design Modify for Acer WLAN LED.

0.4

25

JP21.44 Pin Added MINI1_LED# Net, Added R520, R521.

PVT

12

BATT_TEMP, BATT_OVP, ACIN .

0.4

27

Added C660, C661, C662.

PVT

13

Design Modify for Power. (65W/95W Detect Function)

0.4

27

U15.98 Pin Added 65W/95W# Net, Added R519 100K to +3VALW.

PVT

14

Design Modify for EMI.

0.4

30

Added C663~C678.

PVT

15

For AUDIO EA Test.

0.4

32

Change C582, C583, C584, C587,C594, C597 to 4.7uF.

PVT

16

bo bo .

0.4

33

Added Q53,C680.

PVT

17

Design Modify for EMI.

0.4

33

Added L57, L58 for Mic. L63, L64, L65, L66 for SPK. D28 for ESD.

PVT

18

Change Codec Amp to APA2057RI-TRL_TSSOP28.

0.4

33

Change U31 to SA00001QD00, added R523,R524.

PVT

19

Remove PJP14.

0.4

34

Remove PJP14.

PVT

20

Change MCP67-MV form A01 to A02.

0.4

10~17

Change MCP67-MV form A01 to A02.

PVT

21

0.4

15

Change C503, C504 form 18pF to 6.8pF.

PVT

22

Improve WLAN Module compatibility.

0.3

11,25

Change WLAN Port form PCIE4 to PCIE2.

DVT2

23

Fixed LAN LED work abnormal.

0.3

22

Added D25,D27,D27, U39.

DVT2

24

Change LAN to RTL8211B.

0.2

22

Change Page 22 all compnent.

DVT1

Compal Electronics, Inc.


Title

PIR (HW)

Size

Document Number

Date:

Friday, April 20, 2007

LA-3581P

ICW50

Sheet
1

42

of

42

Rev
1.0

You might also like