Practical Instruction Manual EC233 Electroncs Design Automation Lab

HDL Realization of Basic and

EXP NO. Date:-
Universal Gates
OBJECTIVE

To write the Verilog code to realise and simulate the following circuits (AND, OR, NOT, XOR,
XNOR, NAND & NOR gates)
THEORY
AND Gate
The AND gate produces HIGH output when all its inputs are HIGH
Logic Symbol Truth Table
A B Y = AB
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate
The OR gate produces HIGH output when one or more inputs are HIGH
Logic Symbol Truth Table
A B Y = A+B
0 0 0
0 1 1
1 0 1
1 1 1
NOT Gate
The NOT gate produces the complement of its input.
Logic Symbol Truth Table
A Y= A
0 1
1 0

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Practical Instruction Manual EC233 Electroncs Design Automation Lab

NAND Gate
The NAND gate produces LOW output when all the inputs are HIGH
Logic Symbol Truth Table
A B Y= AB
0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate
The NOR gate produces LOW output when one or more inputs are HIGH
Logic Symbol Truth Table
A B Y= A +B
0 0 1
0 1 0
1 0 0
1 1 0

XOR Gate
The XOR gate produces HIGH output when one input is LOW and other input is high.
Logic Symbol Truth Table
A B Y=A B
0 0 0
0 1 1
1 0 1
1 1 0

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Practical Instruction Manual EC233 Electroncs Design Automation Lab

XNOR Gate
The XOR gate produces HIGH output when one input is LOW and other input is high.
Logic Symbol Truth Table
A B Y= A B
0 0 1
0 1 0
1 0 0
1 1 1

VERILOG CODES
AND GATE

//module Module_Name(Ports);
module BasGatAND(y,a,b);
//output port Declaration
output y;
//input port Declaration
input a,b;
// dataflow modelling
assign y=a&b;
endmodule

OR GATE

//module Module_Name(Ports);
module BasGatOR(y,a,b);
//output port Declaration
output y;
//input port Declaration
input a,b;
// dataflow modelling
assign y=a|b;
endmodule

NOT GATE

//module Module_Name(Ports);
module BasGatNOT(y,a);
//output port Declaration
output y;
//input port Declaration
input a;
// dataflow modelling
assign y=~a;
endmodule

MESCET, Kunnukara Dept. Of ECE

Practical Instruction Manual EC233 Electroncs Design Automation Lab

NAND GATE

//module Module_Name(Ports);
module UniGatNAND(y,a,b);
//output port Declaration
output y;
//input port Declaration
input a,b;
// dataflow modelling
assign y=~(a&b);
endmodule

NOR GATE

//module Module_Name(Ports);
module UnivGatNOR(y,a,b);
//output port Declaration
output y;
//input port Declaration
input a,b;
// dataflow modelling
assign y=~(a|b);
endmodule

XOR GATE

//module Module_Name(Ports);
module SpGatXOR(y,a,b);
//output port Declaration
output y;
//input port Declaration
input a,b;
// dataflow modelling
assign y=a^b;
endmodule

XNOR GATE

//module Module_Name(Ports);
module SpGatXNOR(y,a,b);
//output port Declaration
output y;
//input port Declaration
input a,b;
// dataflow modelling
assign y=a~^b;
endmodule

MESCET, Kunnukara Dept. Of ECE

Practical Instruction Manual EC233 Electroncs Design Automation Lab

SIMULATION WAVEFORMS

AND GATE

OR GATE

NOT GATE

NAND GATE

MESCET, Kunnukara Dept. Of ECE

Practical Instruction Manual EC233 Electroncs Design Automation Lab

NOR GATE

XOR GATE

XNOR GATE

MESCET, Kunnukara Dept. Of ECE