Elektricni Pretvaraci ALL PDF

NET VIER 2016/2017, Elektrini Pretvarai Snage - AC/AC pretvarai, profesor: Dr eljko Despotovi, dipl.el.
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ENERGETSKI PRETVARAI NAIZMENINOG NAPONA

Naizmenini pretvarai su elektronski ureaji koji povezuju naizmenine elektrine mree
razliitih parametara, odnosno pretvaraju naizmenini napon jednog nivoa u naizmenini napon
drugog nivoa ili naizmenini napon jedne frekvencije u naizmenini napon druge frekvencije i sl.
Naizmenini pretvarai se dele na:
pretvarae napona
pretvarae frekvencije
Pretvarai frekvencije mogu biti:
direktni AC/AC
indirektni AC/DC/AC (imaju jednosmerno meu kolo)
Direktni pretvarai frekvencije se dele prema odnosu ulazne i izlazne frekvencije, nainu
iskljuenja tiristora i prema nainu upravljanja.
Prema odnosu ulazne i izlazne frekvencije naizmeninog napona ili struje, direktni
pretvarai frekvencije mogu imati:
niu izlaznu frekvenciju i
viu ili niu izlaznu frekvenciju.
Za iskljuenje tiristora kod direktnih pretvaraa frekvencije mogu se koristiti posebni
komutacioni krugovi, a mogu raditi i bez posebnih komutacionih krugova.
Prema nainu upravljanja, direktni pretvarai frekvencije mogu biti:
anvelopni ili ciklokonvertori (izlazni napon je anvelopa mrenog napona)
fazno upravljani
Fazno upravljani mogu biti:
sa krunom strujom i
bez krune struje
METODE PRETVARANJA NAIZMENIINOG NAPONA

Ako se dva tiristora meusobno spoje antiparalelno, a zatim na red sa potroaem, kao to je
prikazano na Slici 1, na potroau se moe regulisati efektivna vrednost naizmeninog napona.
Za pretvaranje naizmeninog napona koriste se:
Fazne metode,
Stepenaste i fazno-stepenaste metode,
irinsko-impulsna metoda i dr.
Fazne metode pretvaranja naizmeninog napona zasnivaju se na upravljanju efektivne
vrednosti naizmeninog napona na optereenju, i to tako da se menja trajanje voenja jednog od
antiparalelno spojenih tiristora za vreme poluperioda frekvencije mree (Slika 1)
Fazno upravljanje je mogue ostvariti pri kanjenju ugla upravljanja (Slika 2(a)), pri
prethoenju ugla upravljanja (Slika 2(b)), i pri kombinaciji oba naina upravljanja.
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NET VIER 2016/2017, Elektrini Pretvarai Snage - AC/AC pretvarai, profesor: Dr eljko Despotovi, dipl.el.in
Slika 1. eme pretvaraa naizmeninog napona; (a) sa antiparalelno spojenim tiristorima, (b) sa
tiristorima i nepropusno polarizovanim diodama, (c) sa diodama i zajednikim tiristorom
PRETVARAI NAIZMENINOG NAPONA SA ISTIM OTPORNIM

OPTEREENJEM
Dijagrami napona i struja prikazani na Slici 2. odnose se na monofazne pretvarae
naizmeninog napona sa istim otpornim optereenjem. Vrednost ugla odgovara vremenu,
odnosno =t, gde je kruna uestanost mree (=2f; f=50(60)Hz).
Slika 2. Vremenski dijagrami napona i struja koji ilustruju fazne metode pretvaranja naizmeninog
napona; (a) napona i struje na optereenju, (b) napona na tiristoru pri zaostajanju ugla , (c) napona i
struje optereenja pri prethoenju ugla upravljanja , (d) napona i struje optereenja pri dvostranom
faznom regulisanju
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Pri upravljanju koji odgovara Slici 2(a), prestanak voenja tiristora se ostvaruje u
vremenskim trenutcima koji odgovaraju uglovima , 2, 3 zbog promene polariteta
naizmeninog napona napajanja po zavretku svake poluperiode (prirodna komutacija).
Pri nainu upravljanja koji odgovara slikama 2(c) i 2(d) prestanak voenja tiristora mora se
ostvariti do zavretka tekueg polutalasa napona napajanja. To je mogue postii jedino
prinudnom komutacijom tiristora. Zadatak se reava tako to se u emu uvode kola za prinudnu
komutaciju tiristora ili se jednosmerni tiristori zamenjuju dvosmernim.
Zavisnost efektivne vrednosti napona na optereenju od ugla upravljanja (upravljaka
karakteristika) za fazno upravljanje s uglom kanjenja i uglom prethoenja na Slici 2(a) i Slici
2(c), data je izrazom:

1 1
U opt =
( 2 U) 2 sin 2 d ; U opt =
( 2 U) 2 sin 2 d , (1.1)
0
ili u relativnim jedinicama, za isto omsko optereenje ova zavisnost je data kao:
U opt 1 1
= ( + sin 2) , (1.2)
U 2
gde je U efektivna vrednost naizmeninog napona na ulazu pretvaraa (U=U1 pri nepostojanju i
U=U2 pri postojanju ulaznog transformatora) jednaka izlaznom naponu pri =0.
Na analogan nain dobiju se izrazi za dvostrano fazno upravljanje:

1
U opt =
( 2 U) 2 sin 2 d , (1.3)

odakle je:
U opt 1 1
= ( 2 + sin 2) , (1.4.)
U 2
Na Slici 3. prikazane su upravljake karakteristike pretvaraa naizmeninog napona

odreene na osnovi izraza (1.2) i (1.4).
3
Slika 3. Upravljake karakteristike pretvaraa pri faznim metodama pretvaranja naizmeninog napona :
1,2 pri kanjenju i prethoenju ugla upravljanja , 3 pri dvostranoj faznoj regulaciji
Pri istom aktivnom optereenju i pri razliitim nainima upravljanja krive struje mree i
struje optereenja iopt podudaraju se po obliku sa krivom napona uopt i pri >0 razlikuju se od
sinusoide. Drugim reima, za ove pretvarae i za ispravljae, znaajne je procena efikasnosti
potronje snage iz mree = k cos . Faktor izoblienja k je mera odstupanja krive struje od
sinusoide. Parametar karakterie ugao faznog pomeraja prvog harmonika struje optereenja i
krive napona mree.
U regulacionom smislu, u sklopu na Slici 2 (a) prvi harmonik struje zaostaje za naponom ,
dok prema Slici 2(c) prethodi naponu.
Za oba naina upravljanja faktor pomeraja i faktor izoblienja odreuju se pomou izraza:
+ 0.5 sin 2
cos = (1.5)
2 2
( ) + ( ) sin 2 + sin
( ) 2 + ( ) sin 2 + sin 2
k= (1.6)
( + 0.5 sin 2)
Pri dvostranom faznom upravljanju, kao to pokazuje Slika 2(d), fazni ugao =0 i cos=1, pa je
faktor izoblienja:
2 + sin 2
k= (1.7)

Pomou izraza (1.5)- (1.7) moemo odrediti faktor snage:
4
U opt
= , (1.8.)
U
Ova vrednost nam govori, da u jednostranim pretvaraima naizmeninog napona, nezavisno od
metode faznog upravljanja, je faktor snage jednak relativnom naponu na optereenju i stoji s njim
u linearnom odnosu, kriva 1 na slici 4.
Isti faktor snage za posmatrane metode faznog upravljanja dobija se na raun veih
izoblienja krive struje iopt prema Slici 2 (d), a u odnosu na Sl. 2(a) i 2.(c), odnosno na raun
manjeg faktora k.
Slika 4. Dijagram zavisnosti faktora snage pretvaraa naizmeninog napona od relativne vrednosti
napona na optereenju: 1 - za jednostrane pretvarae, 2 - za grupno upravljanje
Da bi se poveao faktor , upravljanje snage potroaa, npr. grejaa elektrinih pei, ostvaruje se
tako da se grupa pretvaraa napaja iz zajednike mree. Poveanje faktora snage objanjava se
time to se struje osnovnih i viih harmonika, koji su nastali u mrei za napajanje pri odvojenom
radu pretvaraa, sumiraju geometrijski pa fazni pomeraj ukupnog osnovnog harmonika u odnosu
na napon napajanja i ukupne amplitude viih harmonika postaje manji od onoga u jednom
pretvarau koji radi punom snagom. Sutinski, postignuti efekat je posledica kombinacije
razmotrenih naina upravljanja. Ovo je ilustrovano krivom 2 na Slici 4, i to za dva tipa
pretvaraa kojima se upravlja po zakonima koji odgovaraju slikama 2(a) i 2 (c).
PRETVARAI NAIZMENINOG NAPONA SA INDUKTIVNIM

OPTEREENJEM
Induktivnost u kolu optereenja unosi promene u karakter struje i napona na optereenju.
Taj uticaj e biti razmotren za faznu metodu upravljanja sa uglom kanjenja ukljuenja tiristora,
kao to je prikazano na Slici 2(a).
Na slici 5. prikazana je ema pretvaraa sa preteno induktivnim optereenjem i vremenski
dijagrami napona i struje.
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Slika 5. Pretvara naizmeninog napona sa preteno induktivnim optereenjem; (a) ema, (b) vremenski
dijagram napona na optereenju, (c) vremenski dijagram struje optereenja, d) vremenski dijagram
napona na tiristoru Th1
Pri istom omskom optereenju struja iopt postaje jednaka nuli pri prolasku napona napajanja kroz
nulu, kao to pokazuje Slika 2 (a). Interval voenja tiristora je = + . Oblik krive iopt
podudara se sa oblikom krive uopt. Induktivnost Lopt usporava porast struje iopt pri ukljuenju
tiristora i spreava njeno smanjenje pri smanjenju napona U, kao to pokazuje Slika 5(c). Struja
iopt tee kroz optereenje i odgovarajui tiristor i posle prolaska napona mree kroz nulu dostie
vrednost nula nakon pomaka u predelu narednog polutalasa napona U. Period voenja tiristora
poveava se za ugao delta, tj. = + . Na raun poveanja perioda voenja tiristora u krivoj
uopt, kao i kod upravljakih ispravljaa, nastaju delovi napona U, (Slika 5(b)), kojih nema pri
istom omskom optereenju. Period pauze u krivoj izlaznog napona smanjuje se do vrednosti -.
To dovodi i do promene oblika krive napona na tiristoru, kao to pokazuje Slika 5(d). Efektivna
vrednost napona na optereenju odreuje se pomou izraza:
+
1
U opt =
( 2 U) 2 sin 2 d , (1.9.)

tako da je relativna vrednost napona na optereenju jednaka:
U opt 1 1 1
= ( ( ) + sin 2 sin 2) . (1.10)
U 2 2
Struja optereenja u periodu voenja svakog tiristora se dobija iz analize prelaznog
procesa koji nastaje nakon ulaska tiristora u rad. Ta struja se sastoji iz dve komponente: prinudne
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L opt
i slobodne. Prinudna komponenta struje optereenja zaostaje za ugao = arctg za
R opt

naponom napajanja u = 2 U sin .
Ona je jednaka odnosu:
2U
ioptpr = sin( ) (1.11)
R 2 opt + 2 L2 opt
Slobodna komponenta opada po eksponencijalnom zakonu:

i optsl = A e t (1.12)
L opt tg
sa vremenskom konstantom = =
R opt
U trenutku = suma prinudne i slobodne komponente jednaka je nuli:
2U
sin( ) + A = 0 (1.13)
R 2 opt + 2 L2 opt
odakle dolazimo do koeficijenta A:
2U
A= sin( ) (1.14)
R 2 opt + 2 L2 opt
Pomou izraza (1.11) i (1.12) dobijamo da je:

2U sin( ) sin( )e tg
i opt = (1.15)

R 2 opt + 2 L2 opt
Pri istom aktivnom optereenju (Lopt=0, =0, tg=0), jednaina (1.15) prelazi u oblik:
2U
i opt = sin , (1.16)
R opt
tj. kriva struje iopt u periodu voenja tiristora odreena je sinusnim naponom napajanja (Slika
2(a)).
Posle ubacivanja vrednosti = + u relaciju (1.15) koja odgovara struji iopt=0 (Slika 5
(b), (c)), dolazimo do transcendentne jednaine:
+

tg
sin( ) + sin( )e =0 (1.17)
koja se moe koristiti za odreivanje ugla .
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Pri preteno induktivnom optereenju pretvaraa znaajno je pitanje i odreivanje kritinog

ugla = kr , pri kome interval voenja struje potpuno prekriva interval .
U tom sluaju, prema Slici 6, struja iopt se smanjuje do nule u trenutku = + (tj.
trenutak prestanka voenja jednog tiristora podudara se sa vremenom poetka voenja drugog
tiristora). U krivoj napona uopt i struje iopt nema pauza, a trajanje voenja svakog tiristora
jednako je 180. Iz jednaine (1.17) sledi da takav reim nastaje pri
( )
= kr = = = arctg Lopt / Ropt . Efektivna vrednost napona na optereenju ima najveu
vrednost i njena relativna jedinica, prema jednaini (1.10), je jednaka jedinici. Kriva struje iopt je
neprekidna i sinusna. U skladu sa izrazom (1.15) pri = kr , bie:
2U
i opt = sin ( ) (1.18)
2 2 2
R opt + L opt
Oigledno je da e analogan reim rada biti i pri uglovima kr>>0. Podruje uglova od
nule do kr je neupravljiva zona pretvaraa u kojoj promena ugla ne utie na promenu efektivne
vrednosti napona na optereenju i njegove struje.
Slika 6. Vremenski dijagrami napona i struje pretvaraa naizmeninog napona pri kritinoj
vrednosti ugla upravljanja
Izvrena analiza rada sklopa prikazanog na Slici 1(a), moe se primeniti i na njegove
varijante na slikama 1(b) i 1(c).
U emi prikazanoj na Slici 1(b), koriste se dopunske diode D1 i D2 spojene antiparalelno
tiristorima tako da je inverzni napon na tiristorima za vreme rada blizak nuli. Zbog toga su
naponski zahtevi koji se postavljaju na tiristore jednostavniji, jer e tiristor voditi samo iznad
maksimalne vrednosti propusnog napona. Struja optereenja odgovarajueg smera tee u datom
spoju kroz rednu vezu diode i tiristora. Kriva inverznog napona na diodi pri regulisanju ima isti
izgled kao i kriva inverznog napona jednog tiristora u spoju na Slici 1(a).
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U spoju prikazanom na Slici 1(c) koristi se samo jedan tiristor. Struja optereenja tee kroz
tri redno spojena elementa (tiristor Th i dve unakrsno spojene diode). Zbog postojanja dioda D1-
D4 , na tiristor Th deluje propusni napon nezavisno od polariteta napona U tako da je prestanak
voenja tiristora mogu samo pri istom aktivnom optereenju. Prestanak voenja tiristora se
ostvaruje na raun smanjenja struje iopt do nule, u trenutku prolaska napona U kroz nulu. Ako u
kolu optereenja postoji induktivnost, spoj gubi sposobnost faznog regulisanja, jer trenutcima
prolaska struje kroz nulu odgovara propusni napon na tiristoru pa bi se tiristor nalazio u stanju
neprekidnog voenja struje, nezavisno od ugla upravljanja . Struja iopt bi u tom sluaju imala
sinusni oblik u skladu sa izrazom (1.18).
Spojevi trofaznih pretvaraa naizmeninog napona sa faznom regulacijom realizuju se po
analogiji sa jednofaznim spojevima. U ovom sluaju celokupna analiza se izvodi sa svaku fazu
ponaosob. Na osnovu izraunatih faznih struja i napona, se jednostavno mogu izraunati linijski
naponi i struje zavisno od sprege trofaznog pretvaraa ( zvezda ili trougao).
STEPENASTA METODA PRETVARANJA NAIZMENINOG NAPONA

Osobina stepenaste metode upravljanja je stepenasta promena amplitude (efektivne
vrednosti) naizmeninog napona na optereenju bez promene njihovog oblika. Ova metoda se
ostvaruje pomou transformatora na kome se izvodi sekundarnog namotaja spajaju na optereenje
preko anti-paralelnih tiristora, kao to pokazuje Slika 7.
Slika 7. Pretvara naizmeninog napona sa stepenastim upravljanjem: a)ema, b) i c) vremenski

dijagrami napona
Poetak voenja tiristora nastaje pri prolasku naizmeninog napona kroz nulu, kao to
pokazuju Slike 7(b), (c). Regulisanje snage na potroau ostvaruje se pomou upravljakog
sistema koji selektivno alje impulse na odgovarajui par anti-paralelnih tiristora i ukljuuje ih.
Prednosti ove metode su nepostojanje izoblienja oblika struje mree i faznog pomeraja struje u
odnosu na napon mree (pri istom aktivnom optereenju).
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FAZNO STEPENASTA METODA PRETVARANJA NAIZMENINOG

NAPONA
Ova metoda se zasniva na zajednikom korienju stepenaste i fazne metode regulisanja.
Ona se realizuje prema emi sa transformatorom na ulazu, kao to pokazuje Slika 7 (a). U
zavisnosti od broja stepeni sekundarnog napona transformatora u2, postoji dvostepeno,
trostepeno, etvorostepeno i viestepeno regulisanje.
Sutina fazno stepenaste metode svodi se na korienje faznog upravljanja pri kontinualnoj
promeni efektivne vrednosti napona na potroau u svakom delu stepena izlaznog napona. Zbog
irokog raspona kontinualnog upravljanja napona, fazno stepenasta metoda daje visoku vrednost
faktora snage u odnosu na fazne metode.
Princip fazno stepenaste metode upravljanja razmotrimo detaljnije na primeru dvostepenog
pretvaraa prikazanog na Slici 8.
Slika 8. Dvostepeni pretvara naizmeninog napona; (a) ema, (b) ( e) vremenski dijagrami
napona za razliite uglove upravljanja
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Upravljaki impulsi za ukljuenje tiristora Th1 i Th2 nieg stepena dovode se u trenutku
prolaza napona napajanja kroz nulu. Ukljuenje tiristora Th3 i Th4 nastaje pri uglu zaostajanja
u odnosu na pomenuti trenutak.
Pri uglu = 0 trenutci nailaska impulsa za ukljuenje za obe grupe tiristora (Th1, Th2, Th3 i
Th4) se podudaraju. Isto tako, upravljaki impulsi uslovljavaju naizmenino ukljuenje samo
tiristora Th3 i Th4 iz vie grupe. Tiristori Th1 i Th2 ostaju iskljueni pod uticajem razlike napona
(u2-2 u2-1). Zbog toga je pri = 0 napon na optereenju odreen naponom u2-2 vieg stepena, kao
to pokazuje Slika 8(b). Polutalas napona uopt pozitivnog polariteta formira se pri iskljuenom
tiristoru Th3, a polutalas napona negativnog polariteta pri iskljuenom tiristoru Th4.
Pri uglovima > > 0 (Slike 8(c) i 8(d)), upravljaki impulsi za ukljuenje tiristora Th3 i
Th4 nailaze s vremenskim zaostajanjem u odnosu na upravljake impulse za ukljuenje tiristora
Th1 i Th2. U periodu provodi ili tiristor Th1 (pri pozitivnom polaritetu napona u2-1) ili tiristor
Th2 (pri negativnom polaritetu napona u2-1) tako da se u vezi s tim periodi krive napona uopt
odreuju odsecima sinusoide u2-1. Upravljaki impuls koji dolazi na tiristor Th3 (ili Th4) nakon
intervala izaziva ukljuenje ili iskljuenje pod delovanjem napona (u2-2 u2-1) ranije ukljuenog
tiristora nieg stepena. Napon na optereenju do zavretka tekueg polutalasa napona napajanja
odreen je naponom u2-2 sekundarnog namotaja transformatora (Slike 8(c), (d).
Dovoenje upravljakog impulsa na tiristore vieg stepena sa uglom = (Slika 8(d)), ne
dovodi do njihovog ukljuenja tako da je napon na optereenju odreen sinusoidalnom napona u2-
1 nieg stepena u uslovima naizmeninog voenja tiristora Th1 i Th2.
Na taj nain, pri kontinualnom upravljanju ugla (trenutkom ukljuenja tiristora Th3 i Th4),
pretvara ostvaruje promenu efektivne vrednosti napona na optereenju u oblasti napona od u2-1
do u2-2.
Upravljaku karakteristiku uopt = f() nalazimo iz izraza za efektivnu vrednost napona
dvostepene krive (Slika 8(c)):

U opt =
1
0
( 2 U 21 )2 sin 2 d + 1 ( 2U 2 2 )2 sin 2 d (1.19)

ili posle pojednostavljenja:
U 2 21 1 2
U 2 2 1
U opt = sin 2 + + sin 2 (1.20)
2 2
Na Slici 9. prikazani su vremenski dijagrami napona i struja koji ilustruju procese u sklopu
pretvaraa sa Slike 8(a), pri fazno stepenastoj metodi upravljanja.
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Slika 9. Vremenski dijagrami napona i struja pretvaraa naizmeninog napona sa dvostepenim

faznim upravljanjem
IRINSKO IMPULSNA METODA PRETVARANJA NAIZMENINOG

NAPONA
Regulisanje po ovoj metodi zasniva se na promeni broja perioda naizmeninog napona koji
se proputa na optereenje. Ovaj nain upravljanja naizmeninog napona moe se ostvariti
pomou sklopova prikazanih na Slici 1.
Reim irinsko-impulsnog upravljanja moe se ostvariti npr. pomou sklopa sa Slike 1(a),
tako da se ukljuenje i iskljuenje tiristora odvija u vremenu duem od perioda frekvencije
napona mree. Ako nema upravljakog impulsa, tiristori ne proputaju struju i optereenje je
odvojeno od mree. Ako se na upravljake elektrode dovede upravljaki impuls, tiristori se
ukljuuju na poetku svakog poluperioda (rade kao diode) i optereenje je spojeno na mreu.
Pri kratkom ukljuivanju i iskljuivanju optereenja antiparalelno spojene tiristore moemo
smatrati beskontaktnim prekidaima za ukljuenje i iskljuenje potroaa, kao to su motori,
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grejai i sl. Ako se ukljuivanje i iskljuivanje potroaa odvija sa regulisanim trajanjem

ukljuenog t i iskljuenog t1 stanja, pri relativnoj promeni trajanja:
t t
= = (1.21)
t + t1 T
ostvaruje se regulacija srednje snage na potroau:

Poptsr = PMAX (1.22)
gde je PMAX snaga potroaa bez prisustva regulacije (t1=0).
Na slici 10. prikazani su vremenski dijagrami napona koji ilustruju princip rada pretvaraa
naizmeninog napona za datu metodu regulisanja.
Slika 10. Vremenski dijagrami napona koji ilustruju princip irinsko-impulsne metode upravljanja
na snienoj frekvenciji
U2
Ova metoda omoguuje regulisanje snage na optereenju u rasponu od do nule.
Ropt
Nedostatak ove metode je prisustvo harmonika u struji mree pri radnim frekvencijama niim od
50Hz, to je posledica impulsnog karaktera troenja energije iz mree. Ovaj nedostatak se u
znatnoj meri moe umanjiti ako se napajanje vri iz zajednike naizmenine mree za grupu od
nekoliko pretvaraa tako da se vri kompenzovanje smanjene potronje jednog pretvaraa
potronjom drugog pretvaraa.
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operska regulacija vune sile
KV
Lm
GP A
oper M
B
Filter
I KV IM
1 (zanemarujemo gubitke u
U KV oper UM operu) Pm = Pkv
pri tome je kluna osobina opera
podeavanje napona bez gubitaka
snage: U m [0,U kv ]
Predavanja iz VUCE
OPER L
Sputa napona "BUCK" + +
+
Poto je L struju E UX UI
moemo
smatrati konstantnom!
m - indeks modulacije UX
t on t on T 2T
m= Ui = m E E
T I
L- struja prigunice
I ulsr = m I L
I ul I L IL IL
kontinualno podeavanje
od 0 do E snaga:
P = E m IL ~ E IL
I izl
Veliina prekidaa:
V A ~ I L E
Predavanja iz VUCE
Podiza napona "BOOST" +
+ +
Poto je L struju
moemo E UX UI
smatrati konstantnom!
Srednja vrednost U x mora U

X
biti jednaka E t on UI T 2T
Kontinualno podeavanje
od E do
I ul
Snaga: P ~ E IL
Veliina prekidaa:
I izl
V A ~ U i I L (U i > E )
Predavanja iz VUCE
I ul I izl
Obrtai napona
"BUCK - BOOST" +
+
Poto je L struju E UX UI
moemo
smatrati konstantnom! +
Srednja vrednost napona UX

t on T 2T
na prigunici U x = 0 E
mE
Ui =
1 m
UI
Moe davati manji ili I ul IL IL
vei napon od ulaznog
E IL
Snaga: P ~
2 I izl
Veliina
prekidaa:
Predavanja iz VUCE V A ~ 2 E I L
Veliina prekidaa se definie kao V A .
U vui se koristi samo prva vrsta opera (BUCK).

Motor je okarakterisan nominalnim
naponom i on je jednak maksimalnom
trajnom naponu za koji je pravljena izolacija.
Bitno:
Dimenzije, teina, grejanje opera ( vezano za naponski i
strujni kapacitet upotrebljenih prekidaa)
Po pitanju dimenzija najpovoljniji je sputa napona.
Obrta se jedino koristi u prekidakim izvorima napajanja.
operi sputai napona se dele na:
opere sputae napona sa rekuperacijom
opere sputae napona bez rekuperacije
Predavanja iz VUCE
oper sputa napona sa rekuperacijom
dioda za
I B1 rekuperaciju
T1 D2 I B1
t on
+
LM Ia
E U KV
A
Ip
T2 D1 U i = m U KV M T t
I B2 B Impulsi na bazi tranzistora
ton = m T
m U kv Ra I a
U i = m U kv = K e + Ra I a =
Ke
Predavanja iz VUCE
m U kv K e
Fv ~ M em ~ Ia = *
Ra
Promenom t on moe se podeavati

Ra = Ra + RL
*
kontinualno brzina i vuna sila.

Omski otpor
prigunice
Ukoliko bi postojali samo T1 i D1

ne bi mogli vriti rekuperaciju energije.
Stoga su neophodni T2 i D2.
Predavanja iz VUCE
Kod manipulativnih vozila mora se
ostvariti mogunost promene polariteta.
Ovo je omogueno tzv. H mostom.
On ima dvostruko vie elemenata.
Ovakav oper se primenjuje za manje
vune snage, do 100kW.
Predavanja iz VUCE
Tiristorski nerekuperativni oper sa tiristorima
za automatsko slabljenje polja
+
Motor ima pobudni
T1 napon iz dva dela
NP
LM 2 IM
U KV Struja kroz D1 ima
D1 impulsni karakter a
NP
M da bi se izbegla
naizmenina
C 2
komponenta vezuje
se C.
Ui = m E Um E
[0, nom ] m [0,1]
Predavanja iz VUCE
I D1
IM
t on
t off
T
sr
I D1 = (1 m ) I m srednja vrednost struje
Np Np m
Fp = F1 + F2 = Im + (1 m ) I m = N p I m 1
2 2 2
Predavanja iz VUCE
Praktina realizacija eksploatacione karakteristike
tranzistorskog vunog opera
Kod vozila za masovni transport snaga motora

P 100 200 kW
a motornih kola ~ 800kW . U upotrebi su operi
P ~ 200kW U ~ 700 1200V I max = 300 1000 A
Najee se koriste IGBT tranzistori

(INSULATED GATE BIPOLAR TRANSISTOR)
K
Tumaenje IGBT-a K
G
G
Predavanja iz VUCE E E
Za VG>VT (VT - napon praga) prekida vodi.
VC
Prelazni procesi:
IC
tf
W1
p = u i
tf - odreuje komutacionu uestanost

IGBT ~ 1s

f kom 5kHz = f PWM W1
Snaga gubitaka pri komutaciji:
nom
P = f PWM W1
Predavanja iz VUCE
U KV
LF I
GP
LM IM
CF Ui
LA M
etkice
Merenje armaturne
Iu struje
IM
I
1
I ~
Predavanja iz VUCE
f PWM L
LF i CF slue kao filtar za eliminaciju visoko frekventnih
komponenti
LA nije dovoljno da smanji "ripl" struje motora ispod granice
5 - 10% Inom pa se dodaje Lm
Armaturna struja se meri iz razloga zatite i regulacije
vune sile
Pobuda obino nezavisna i napaja se iz posebnog izvora
RKV
Ups - napon podstanice
RF Rkv - otpor kontaktnog voda
+
U PS RF - otpor prigunice iz filtra
UM IR
U M = U PS + ( R ) I R
Podstanice vrlo esto nisu receptivne (tj. ne mogu da prime

energiju koenja). U tom sluaju ona se mora utroiti na neko vozilo
koje se trenutno nalazi u motornom reimu
Predavanja iz VUCE
R KV
Na motoru napon ne sme
RF prei UM (Unom +10%).
Ako se to desi mora se
UM IR prei na mehaniko
koenje.
0m 2500 m
+ +
PS1 PS2
Rekuperacija Motorni reim

Predavanja iz VUCE
Ukoliko mrea nije u stanju da prihvati rekuperiranu energiju:
za desetak millisekundi
U KV napon e biti vei od UMAX
LF
to moe da oteti tranzistore
I
GP
LM IM
CF Ui
LA M
etkice
Struja rekuperacije preko gornje diode uveava napon na CF
dVCF I R
=
Predavanja iz VUCE
dt CF
DK RK
M
QK
QK se ukljuuje i rastereuje CF,

viak energije se "spaljuje" na RK
Predavanja iz VUCE
Elektromagnetne smetnje vunog opera
Ui
E
Ui IM
A
~ 3V
t1 t t2 t
do t1 prekida vodi. U t1 prekida se otvara i dolazi do

debalansa struja. Dioda jo nije provela.
Da bi zakljuili ta se dogaa moramo posmatrati

parazitne kapacitivnosti CP.
dU i I M V
= 20
Predavanja iz VUCE
dt CP n sec
U trenutku t2 provede dioda. Najkritiniji je deo od t1
do t2, javlja se problem elektromagnetne kompatibilnosti
(velika strmina). Naroito opasno za komunikacione veze
I CG CCG
IC UG VT = 100mV
RG
+ 4,1 B
+
UC VT~ 4 - 7V
+ 4 A
Ex UG
u A prekida poinje da se ukljuuje

dok je u B ve ukljuen
CCG - parazitna kapacitivnost kolektor-gejt

Predavanja iz VUCE
VG dU C Balans struja u gejtu
I CG = C CG bie zadovoljen od t2 do t3
Ex dt
jer je IRG ide kroz
VT CCG odnosno IRG= ICG
E X VT
I = dU C E X VT
UC t RG RG =
dt RG C CG
dU C tK= t2- t1 - kanjenje
dt tR= t3- t2 - vreme uspona IC
IC t
tk tr Na strminu utiemo izborom RG
( vee RG manja strmina a
isklj. prekida samim tim i manje smetnje)
t1 t 2 t3 t
Predavanja iz VUCE
Gubici usled komutacije imaju pik u tR
pa stoga RG ne sme biti preveliko
Predavanja iz VUCE
UC Gubici snage i hlaenje vunog opera
IC t P = PKON + PKOM
PKON kondukcija
PKOM komutacija
PKON t tON
PKON = VCE I C
VCE ( ON ) I C T
VCE ( ON ) 3V
t on
PKOM t Ako usvojimo tRtF i da se

talasni oblici UC i IC
linearno menjaju
tr tf t 1 max
PKOM = U C I C f PWM
Predavanja iz VUCE 2
Dimenzije prekidaa su 100x50x25 mm (za stotinak volti i
1500A) pa sledi da su gubici oko 1500W. Problem koji se
javlja je kako odvesti toplotu da ne bi dolo do oteenja.
Mali prekidai imaju mali toplotni kapacitet pa se stoga

montiraju na aluminijumski hladnjak. Hlaenje ventilatorom
nije mogue vriti jer, u vui, pretvara mora biti izolovan
Za hlaenje se koriste toplotni ili freonske pumpe.

Kao rashladno sredstvo koristi se freon
Predavanja iz VUCE
Sanduk za smetaj pretvaraa
Bakarna cev
Zid vozila
(ee krov)
Freon
Sistem cevi
(kondenzator)
Potpuno zatvoren
(veliki napon, velika struja, jako
elektro magnetno polje)
Predavanja iz VUCE
2 3 l freona
odvode oko 3kW
15 m Cu cevi
Freon ugroava ivotnu sredinu, koristi se samo u

zatvorenim i bezbednnim sistemima !
Regulacioni blok dijagram tranzistiorskog vunog

opera sa IGBT
meri se: Ia - armaturna struja
- temperatura
Uul - ulazni napon opera
Procenjuje se: m - ugaona brzina obrtanja
UM
m
Predavanja iz VUCE Ke
Zadaci regulacije: - odreivanje ton
- odreivanje napona napajanja
pobudnog namota
t on
m= sr
T oper i Um PI regulator
mo dulator Fv
U M E MS
Ia =
Ra + ( LM + La ) S
U a = f (m ) ~ f (t on )
Predavanja iz VUCE
Up napajanje Up p
pobudnog
Lp
namotaja R p + Lp S
* greka
zadata vrednost I a + e PI regulator
Fv

merena vrednost I a
diskriminator greke
U M E MS
Ia =
Ra + ( LM + La ) S
U a = f (m ) ~ f (t on )
Predavanja iz VUCE
Kako se odreuje Ia* (eljena armaturna struja):
regulacija brzine ovek
diskriminator greke brzine ovek
pomeraj pedale gasa - zadata vuna sila (zadaje - ovek)
Veoma esto poloaj pedale direktno odreuje Ia*.

Ovaj regulator ima zadatak da se obezbedi i ogranienje
napona kojim se oper napaja.
U MAX +
RK
QK

E
mereno
Predavanja iz VUCE Postoji jo i zatita od pregrevanja.

Runo postoji mogunost da se
pusti u rad bez obzira na pregrevanje!
95C
IGBT

Ia * Ia * +
RK

Ia
180C
Predavanja iz VUCE
Bilans utroene elektrine energije
100%
Energija predata
motornim kolima
9%Pomoni potroa
U 4% U operu
napojnom
vodu
24% U motoru
81%
Gubitak u 10% trenje
podstanici 2,5%
Na otporniku
9% 18,5% za koenje
15,5%
19%
34,5%
rekuperacija
Predavanja iz VUCE
Tiristorski vuni oper
Komutaciona kola iskljuuju tiristor.

On sam to ne moe. (Tr1, Tr2, LK, CK)
LF
Tr 1
LK CK
CF
LM
A
Tr 2 M
etkice B
Predavanja iz VUCE
K ~ LK C K
CK mora svaku narednu komutaciju da doeka
na odreenom potencijalu
U toku ton mora da se zavri cela komutacija.
min
= (Ra + RLm )
t on min t on
U SR = E ; U SR = E
T T
Problem je kada USRmin>UM pol

T , fPWM ; fPWMnom ~ 200 - 800 Hz
Pri polasku f [0, f nom ] javljaju se

karakteristini zvuci pri polasku
Predavanja iz VUCE
Pomona oprema vozila za masovni prevoz putnika
signalizacija i detekcija voza

grejanje i klimatizacija
"glavno" i "deurno" svetlo
Detekcija voza - ureaj je lociran
u inama.
Jedna od ina je sekcionisana.
U0 - detekcioni signal.
Mnogo je manji kada Bakarna pletenica
tokovi kratko spoje ine.
400 Hz
U0
Predavanja iz VUCE VF trafo

Grejanje Osvetljenje
DC
DC
U KV
DC AC
Frekvencija je stalna (ista) za jednu podsekciju.

Osvetljenje: Posv 2, 2kW
Greja: 50 kW / koli ma
Predavanja iz VUCE
kondenzator
Vagonski Vuni
Aku baterija oper
pretvara
U svakim kolima mora da postoji:

vagonski pretvara
akumulatorska baterija
Predavanja iz VUCE
STOJAN RISTI
ELEKTRONSKE
KOMPONENTE
PREDAVANJA
Godina: I
Semestar: II
Elektronski fakultet Ni
2010.
2
SADRAJ
1. UVOD 7
2. KOMPONENTE SA IZVODIMA I KOMPONENTE ZA

POVRINSKO MONTIRANJE (SMD) 9
2.1. KOMPONENTE SA IZVODIMA 9
2.2. KOMPONENTE ZA POVRINSKO MONTIRANJE SMD 10
2.3. KUITA 13
2.4. LEMLJENJE KOMPONENATA 18
3. OTPORNICI 25
3.1. OPTE O OTPONICIMA 25
3.1.1. Vrste otpornika 25
3.1.2. Osnovne karakteristike otpornika 26
3.1.3. Nizovi nazivnih vrednosti otpornosti i klase tanosti 28
3.1.4. Oznaavanje otpornika 29
3.1.5. Stabilnost karakteristika otpornika 31
3.1.6. Frekventna svojstva otpornika 33
3.2. NENAMOTANI OTPORNICI STALNE OTPORNOSTI 35
3.2.1. Ugljenini otpornici 37
3.2.2. Metalslojni otpornici 38
3.2.3. Slojni kompozitni otpornici 39
3.2.4. Maseni kompozitni otpornici 40
3.2.5. ip otpornici 40
3.2.6. Otporniki moduli (otpornike mree) 41
3.3. NAMOTANI OTPORNICI STALNE OTPORNOSTI 42
3.3.1. Temperaturna kompenzacija 43
3.4. OTPORNICI PROMENLJIVE OTPORNOSTI (POTENCIOMETRI) 44
3.4.1. Osnovne karakteristike potenciometara 44
3.4.2. Vrste potenciometara 46
3.4.3. Regulacioni otpornici (trimeri) 47
3.5. OTPORNICI SA NELINEARNOM PROMENOM OTPORNOSTI 48
3.5.1. NTC otpornici 48
3.5.2. PTC otpornici (pozistori) 52
3.5.3. Varistori 53
3.5.4. Fotootpornici 55
4. KONDENZATORI 58
4.1. OPTE O KONDENZATORIMA 58

4.1.1. Kapacitivnost kondenzatora 58
4.1.2. Klase tanosti; oznaavanje kondenzatora 60
4.1.3. Dielektrici i dielektrina konstanta 61
4.1.4. Otpornost izolacije i vremenska konstanta kondenzatora 61
3
4.1.5. Frekventna svojstva kondenzatora 63
4.1.6. Gubici u kondenzatoru 64
4.1.7. Stabilnost kondenzatora 66
4.2. KONDENZATORI STALNE KAPACITIVNOSTI 67
4.2.1. Papirni kondenzatori 68
4.2.2. Kondenzatori sa plastinim i metaliziranim plastinim folijama 68
4.2.3. Liskunski kondenzatori 71
4.2.4. Stakleni kondenzatori 72
4.2.5. Keramiki kondenzatori 72
4.2.6. Elektrolitski kondenzatori 75
4.2.7. UltraCap kondenzatori 80
4.3. KONDENZATORI PROMENLJIVE KAPACITIVNOSTI 82
4.3.1. Obrtni kondenzatori 82
4.3.2. Polupromenljivi kondenzatori trimeri 82
4.3.3. Varikap diode 83
5. KALEMOVI 85
5.1. OPTE O KALEMOVIMA 85

5.1.1. Induktivnost kalemova 85
5.1.2. Kalemska tela i vrste namotaja 86
5.1.3. Frekventna svojstva kalemova 89
5.1.4. Faktor dobrote kalemova 90
5.2. KALEMOVI BEZ JEZGRA 92
5.3. KALEMOVI SA JEZGROM 93
6. TRANSFORMATORI I PRIGUNICE 98
6.1. KONSTRUKCIJA I PRORAUN 98

6.1.1. Materijali za magnetna jezgra 98
6.1.2. Oblici magnetnih jezgara 100
6.1.3. Osnovne relacije kod transformatora 102
6.2. MRENI TRANSFORMATORI 104
6.2.1. Dimenzionisanje jezgra 105
6.2.2. Namotaji 106
6.3. PRIGUNICE 107
7. OSNOVNE OSOBINE POLUPROVODNIKA 108
7.1. ELEMENTARNI POLUPROVODNICI I POLUPROVODNIKA JEDINJENJA 108

7.2. SLOBODNI ELEKTRONI I UPLJINE U POLUPROVODNICIMA 111
7.3. PRIMESNI POLUPROVODNICI 114
7.3.1. Poluprovodnici n-tipa 115
7.3.2. Poluprovodnici p-tipa 116
7.4. ENERGETSKE ZONE 117
7.5. TRANSPORT NOSILACA NAELEKTRISANJA 121
7.5.1. Drift nosilaca naelektrisanja 121
7.5.2. Specifina otpornost i provodnost homogenih poluprovodnika; driftovska struja 124
7.5.3. Difuzija u poluprovodnicima; difuziona struja 125
7.5.4. Ukupna struja 126
4
8. DIODE 127
8.1. p-n I n-p SPOJEVI 127

8.1.1. Ravnoteno stanje na p-n spoju 131
8.1.2. Kapacitivnost prostornog naelektrisanja 135
8.2. STRUJA DIODE 136
8.2.1. Testiranje ispravnosti dioda 139
8.3. PROBOJ p-n SPOJA 141
8.3.1. Zenerov proboj 141
8.3.2. Lavinski proboj 142
8.4. KONTAKT METAL-POLUPROVODNIK 143
8.5. PRIMENA DIODA U IZVORIMA NAPAJANJA 144
9. BIPOLARNI TRANZISTORI 150
9.1. VRSTE TRANZISTORA 150

9.1.1. Nain rada tranzistora 153
9.2. KOEFICIJENT STRUJNOG POJAANJA 156
9.3. STATIKE STRUJNO-NAPONSKE KARAKTERISTIKE 157
9.3.1. Statike strujno-naponske karakteristike tranzistora sa uzemljenom bazom 157
9.3.2. Statike strujno-naponske karakteristike tranzistora sa uzemljenim emitorom 157
9.4. PRIMENA TRANZISTORA 161
9.5. ELEKTRINI MODEL TRANZISTORA 163
9.6. TESTIRANJE ISPRAVNOSTI TRANZISTORA 164
10. MOS TRANZISTORI 165
10.1. VRSTE MOS TRANZISTORA 166

10.1.1. Osnovni principi rada MOS tranzistora 167
10.2. IZLAZNE KARAKTERISTIKE MOS TRANZISTORA 169
10.3. PRENOSNE KARAKTERISTIKE MOS TRANZISTORA 174
11. OSNOVI FOTOELEKTRONSKIH KOMPONENATA 176
11.1. FOTODIODA 177

11.2. FOTOGENERATOR (SOLARNA ELIJA) 178
11.3. FOTOTRANZISTOR 181
11.4. SVETLEE DIODE (LED) 181
11.6. KOMPONENTE SA SVETLOSNOM SPREGOM 183
11.6. POLUPROVODNIKE LASERSKE DIODE 184
12. OSNOVI INTEGRISANIH KOLA 188
12.1. VRSTE INTEGRACIJE 188

12.2. VRSTE INTEGRISANIH KOLA 193
12.2.1. Monolitna inetgrisana kola 193
12.2.2. Tankoslojna i debeloslojna integrisana kola 197
12.2.3. Hibridna integrisana kola 198
5
13. TAMPANE PLOE 201
13.1. JEDNOSLOJNE TAMPANE PLOE 202
13.1.1. Izrada crtea tampanog kola 203
13.1.2. Prenoenje crtea na ploicu 206
13.1.3. Nagrizanje ploice 210
13.1.4. Dvostrano tampana ploa 211
13.2. VIESLOJNE TAMPANE PLOE 212
13.3. TAMPANE PLOE ZA POVRINSKU MONTAU 214
6
1. UVOD
Danas se ve pouzdano moe tvrditi da smo savremenici elektronske revolucije. Uvoe-

nje pojma elektronska revolucija ima i stvarni smisao, s obzirom da se kod nje mogu izdvojiti
nekoliko faktora bitnih za svaku revoluciju. Prvi od njih je veliina i raspon promene: elek-
tronska revolucija je iz osnova promenila drutvo, zahvatajui pojedinca, njegov dom i radno
mesto, obrazovanje, ivotni vek, pa ak i nain raanja i smrti. Druga osobina elektronske revo-
lucije je brzina kojom je osvojen svet, iako vreme njenog najjaeg uticaja traje svega tridesetak
godina. Najzad, posle pokretanja, elektronsku revoluciju nita vie nije moglo zaustaviti.
Svake godine u elektronici nas impresionira sve ve}i broj tehnolo{kih inovacija, koje su,
prvenstveno, posledica intenzivnog razvoja elektronskih komponenata. Ipak, s pravom se moè
re}i da su ta teholo{ka ~uda veoma skromna u odnosu na ono {to tek dolazi. Pogled na samo
deo budu}nosti tehnologije izrade elektronskih komponenata i elektronskih naprava fascinira da
je, prakti~no, nezahvalno prognozirati {ta }e se sve i kako u budu}nosti proizvoditi.
Kada je re~ o elektronskim komponentama, osnovni cilj }e i dalje biti smanjivanje di-
menzija istih, sve do nivoa molekula, pa, ~ak, i atoma. Elektronika bazirana na takvim kom-
ponentama ve} sada se zove molekularna elektronika. Pored znatno ve}eg stepena integracije,
odnosno izuzetno ve}eg broja komponenata po ~ipu, smanjivanje dimenzija komponenata do-
ve{}e do daljeg pove}anja brzine njihovog rada. Naravno, postoje}i materijali bi}e zamenjeni
drugim, tako da }e i principi rada sada{njih komponenata biti druga~iji. Na sl. 1.1 prikazano je
kako su se tokom godina smanjivale dimenzije (konkretno duìna) komponenata.
Sl. 1.1. Smanjivanje dimenzija komponenata tokom godina i predvi|anje do 2020. godine.
Elektronske komponente se mogu podeliti u dve osnovne grupe: pasivne i aktivne. Pod
pasivnim komponentama se podrazumevaju one komponente koje nisu u stanju da pojaavaju
neki elektrini signal; suprotno njima, komponente koje pojaavaju elektrini signal jesu aktivne
7
komponente. Treba napomenuti da se, pored toga to osnovu savremene elektronike ine polu-
provodnike komponente i integrisana kola, pasivne elektronske komponente i dalje masovno
proizvode i ugrauju u elektronske ureaje, ali da je, zbog velikog broja i raznovrsnosti, prak-
tino nemogue opisati sve postojee komponente. Na sl. 1.2 su prikazane osnovne pasivne i
aktivne elektronske komponente kojima e biti posveena panja u okviru ovoga predmeta, sa
naznakom glave u kojoj e biti razmatrane.
Sl. 1.2. Osnovne pasivne i aktivne elektronske komponente kojima e biti posveena panja
u okviru kursa koji sledi, sa naznakom glave u kojoj e biti razmatrane.
8
2. KOMPONENTE SA IZVODIMA I KOMPO-
NENTE ZA POVRINSKO MONTIRANJE (SMD)
Svaka elektronska komponenta mora da poseduje elektrini prikljuak kojim se povezuje

sa drugim komponentama u elektrinom kolu. Prema izgledu tih elektrinih prikljuaka elektron-
ske komponente se dele na komponente sa izvodima (to su tkzv. klasine komponente) i na
komponente za povrinsko montiranje, ili SMD (od Surface Mounted Devices). Vizuelna raz-
lika izmeu ovih dveju vrsta komponenata moe se uoiti sa sl. 2.1, na kojoj je predstavljen vie-
slojni keramiki kondenzator u obe verzije.
Sl. 2.1. Vieslojni keramiki kondenzator sa ianim izvodima i u SMD izvedbi.
2.1. KOMPONENTE SA IZVODIMA

Da bi se, u cilju oformljenja unapred definisanih elektronskih kola, komponente sa izvo-
dima (sl. 2.2) nanosile na tampane ploe neophodno je da te ploe poseduju otvore (sl. 2.3)
kroz koje se uvlae izvodi komponenata, koji se sa suprotne strane ploe leme (sl. 2.3 i sl. 2.4 a).
Sl. 2.2. Komponente sa izvodima (tkzv. klasine komponente).
9
Sl. 2.3. tampana ploa sa otvorima (rupama) za montiranje komponenata sa izvodima.
Sl. 2.4. a Montiranje komponenata sa izvodima; b, c povrinsko montiranje komponenata.
2.2. KOMPONENTE ZA POVRINSKO MONTIRANJE SMD

Odmah treba rei da SMD (sl. 2.5) nisu bezizvodne komponente, ve su kod njih izvo-
di takvog oblika (nekada su to samo kontaktni zavreci) da omoguuju povrinsko montiranje
komponenata. Dakle, povrinski montirane komponente, za koje se odmah naglaava da su
veoma malih dimenzija (sl. 2.6 i sl. 2.7), jesu komponente koje se direktno leme za tampanu
plou, a ne ubacuju se u nju ili neku drugu podlogu (sl. 2.4 b, sl. 2.4c i sl. 2.8).
SMD tehnologija ima nekoliko prednosti u odnosu na montiranje komponenata sa izvo-
dima. Prva i najoiglednija prednost jeste drastino poveanje raspoloivog prostora na tam-
panoj ploi, s obzirom da su komponente za povrinsko montiranje izuzetno malih dimenzija. Na
taj nain SMD tehnologija prua mogunost da se prevaziu ogranienja u pogledu veliine i te-
ine i daje dopunski stepen slobode pri projektovanju novih minijaturnih elektronskih kola.
10
Otpornik Keramiki kondenzator Elektrolitski Al Otporniki modul
kondenzator
Svetlee diode (LED) Tranzistor (SOT 23) Diode (SOD 80C)
Integrisana kola
Sl. 2.5. Komponente za povrinsko montiranje SMD.
Sl. 2.6. Jedno integrisano kolo u SMD izvedbi u poreenju sa vrhom prsta.
11
Druga velika prednost je ekonomska. Naime, povrinskim montiranjem komponenata
moe da se utedi do 50% ukupnih trokova sklapanja tampanih ploa, a to se postie automat-
skim ureajima za montau. Istina, i kod komponenata sa izvodima se koristi automatsko ubaci-
vanje izvoda u otvore na tampanoj ploi, ali ta tehnika, iako je brza i pouzdana, zahteva pribli-
no 30% vie prostora na ploi u poreenju sa runom montaom.
Trea prednost je u brzini nanoenja, s obzirom da se u SMD tehnologiji mogu da kori-
ste najsavremenije metode lemljenja, kao to su talasno lemljenje i lemljenje razlivanjem, uz na-
pomenu da je lake smetati komponente na supstrat nego ubacivati njihove izvode u otvore na
tampanoj ploi. Na taj nain su SMD sistemi bri od ma kojeg ureaja za montau.
Sl. 2.7. Uz prikaz veliine SMD-a.
12
Sl. 2.8. SMD na tampanoj ploi.
etvrta prednost je u poveanju nivoa pouzdanosti gotovih ploa, uz istovremeno nji-

hovo krae testiranje i znaajno smanjeni kart. Izuzetno mali kart kod SMD tehnologije posle-
dica je nepostojanja otvora u tampanoj ploi, odnosno eliminacije otkaza koji nastaju prilikom
formiranja i korienja tih otvora, a takoe i nemogunosti pogrenog smetanja komponenata, s
obzirom da je montaa kontrolisana raunarom.
Peta dobra osobina SMD tehnologije jeste to su, zbog nepostojanja izvoda, odnosno
veoma kratkih izvoda, parametri parazitnih elemenata svedeni na minimalne vrednosti. To,
pak, znai da su takva kola sa boljim elektrinim karakteristikama i sa veom brzinom rada.
Bolje mehanike karakteristike, odnosno vea izdrljivost na udarce i vibracije jeste
esta prednost kola u SMD tehnologiji.
I konano, SMD mogu da imaju vei broj izvoda i kontaktnih zavretaka od klasinih
komponenata sa izvodima.
Nedostaci SMD tehnologije ogledaju se u sloenijim tehnolokim postupcima lemljenja
(posebno kada je re o runom lemljenju), teem ispitivanju usled slabije pristupanosti kontakti-
ma, odnosno kontaktnim zavrecima komponenata, kao i u nepostojanju nekih (posebno pasivnih
komponenata) sa izrazito visokim nazivnim vrednostima (otpornika veoma velikih otpornosti,
kondenzatora sa velikim vrednostima kapacitivnosti).
2.3. KUITA
Velika veina komponenata, o kojima e nadalje biti rei, inkapsulirana je u odreena
kuita. Kuita su, prvenstveno, neophodna da bi se sama komponenta, odnosno njen funkci-
onalni deo pelet (ip) (sl. 2.9), zatitio od spoljanjih uticaja (vlage, temperature, mehanikih
oteenja). Pored toga, sama kuita su tako izvedena da se preko njih komponenta vezuje (lemi)
u odreeno elektronsko kolo; drugim reima, kuita omoguuju da se preko njih (sl. 2.9) pri-
vrste elektrini izvodi kojima se ostvaruje elektrina veza izmeu peleta i ostalog dela elektron-
skog kola, odnosno drugih komponenata. Elektrina veza izmeu peleta i izvoda ostvaruje se i-
com koja se sa jedne strane bondira za pelet, a sa druge strane na izvod (sl. 2.9).
esto se prema vizuelnom izgledu kuita moe prepoznati vrsta elektronske kompo-
nente; to se posebno moe rei za komponente sa izvodima, sl. 2.10. Meutim, kod SMD-a, kada
su komponente paralelopipednog (sl. 2.1a), odnosno cilindrinog oblika (sl. 2.11b), vrlo je teko
vizuelno razlikovati otpornik od kondenzatora, odnosno otpornik ili kondenzator od diode.
13
Sl. 2.9. Poloaj peleta unutar kuita.
Na sl. 2.10 prikazana su najee koriena kuita za standardne (klasine) diskretne

poluprovodnike komponente sa izvodima, konkretno za bipolarne tranzistore. Napominje se da
kuita za komponente sa poveanom disipacijom (komponente snage) TO-3, TO-220 i TO-
247, imaju otvore kroz koje se zavrtnjima privruju za hladnjake, ime se poboljavaju uslovi
hlaenja tih komponenata.
Sl. 2.10. Najee koriena kuita bipolarnih tranzistora sa izvodima;

diode su u slinim kuitima (samo sa dva izvoda), i tada nose oznake DO.
Najee korieni tipovi i kuita SMD-a prikazani su na sl. 2.11. Paralelopipedni oblik,
tkzv. ip-komponente (sl. 2.11a), imaju otpornici, kondenzatori, pa ak i neki kalemovi. Otpor-
nici, takoe, mogu biti i cilindrinog oblika (sl. 2.11b). Cilindrini oblik kuita se koristi i za
diode, a oznaava se sa SOD (skraenica od Small Outline Diodes niskoprofilne diode). Kui-
ta diskretnih poluprovodnikih komponenata, prvenstveno se misli na tranzistore (i bipolarne i
unipolarne), oznaavaju se sa SOT (od Small Outline Transistors niskoprofilni tranzistori), sl.
2.11c.
14
Integrisana kola u SMD izvedbi se pakuju na vie naina. Kuita SOIC (od Small Inte-
grated Circuits niskoprofilna integrisana kola), sl. 2.11d, koriste se za integrisana kola sa rela-
tivno malo izvoda (od 6 do 28). Najea integrisana kola tipa CHIP CARRIER (nosa ipa),
sl. 2.11e, jesu PLLC (Plastic Leaded Chip Carrier, sl. 2.12); napominje se da je kod njih izvod sa
donje strane savijen ka unutranjosti kuita (u obliku slova J), sl. 2.13. Na sl. 2.11f VSO
oznaava kuita za veoma niskoprofilna integrisana kola (od Very Small Outline). U kuita
FLATPACK (ravna) sa sl. 2.11g spadaju veoma esto koriena kvadratna QFP (Quad Flat Pack,
sl. 2.12 i sl. 2.14a) i bezizvodna kvadratna QFN (Quad Flat Pack Non-lead, sl. 2.12 i 2.14b) ku-
ita. MICROPACK (sl. 2.11h) ili TAB (od Tape Automated Bonding) interisana kola se koriste
za automatsko bondiranje sa trake.
Sl. 2.11. Najee korieni tipovi i kuita komponenata za povrinsku montau.
Sl. 2.12. Podtipovi i kuita integrisanih kola za povrinsku montau.
Sl. 2.13. Izvodi (u obliku slova J) kod integrisanih kola sa kuitima tipa Chip carrier.
15
Sl. 2.14. a. Kvadratna QFP (Quad Flat Pack) kuita; (TQFP: Thin Quad Flat Pack;
PQFP: Plastic Quad Flat Pack; cifra iza QFP oznaava broj izvoda);
b bezizvodna kvadratna QFN (Quad Flat Pack Non-lead) kuita.
Na sl. 2.15 prikazana je tampana ploa jednog elektronskog ureaja sa povrinski mon-
tiranim komponentama, na kojoj se vide komponente u SOIC, SOT i QFP kuitima.
Sl. 2.15. Deo jednog elektronskog ureaja sa naznakom komponenata sa SOIC, SOT i QFP kuitima.
16
Za integrisana kola sa veoma velikim brojem izvoda (bolje rei kontaktnih zavretaka)
pokazalo se da su najpogodnija tkzv. BGA (od Ball Grid Array) kuita, sl. 2.12 i sl. 2.16. Pred-
nosti BGA kuita ogledaju se u sledeem: imaju svojstvo samocentriranja, imaju krae elektri-
ne veze (a to znai manje parazitne kapacitivnosti i induktivnosti, pa samim tim veu brzinu
rada), imaju manju mehaniku osetljivost izvoda, imaju vei razmak izmeu lemnih taaka i
imaju bolja termika svojstva u odnosu na ostala SMD kuita.
Sl. 2.16. Integrisana kola u BGA kuitima.
Sl. 2.17. Vieipna MCP (Multi Chip Package) kuita.
17
Na ovom mestu interesantno je pomenuti da postoje, kao na sl. 2.17, vieipna kuita
koja u sebi sadre vie meusobno razdvojenih i naslaganih ipova, kao i dvojna kuita (sl.
2.18), gde se, praktino, jedno kuite nalazi u drugom.
Sl. 2.18. Dvojna POP (Package on Package) kuita.
2.4. LEMLJENJE KOMPONENATA

Pod lemljenjem se podrazumeva postupak kojim se, pomou rastopljenog dodatnog mate-
rijala (lema), izvodi komponenata spajaju sa provodnim vezama na tampanoj ploi (ili sa izvo-
dima drugih komponenata) u nerazdvojnu celinu. Pri lemljenju se izvodi i metal na tampanoj
ploi samo zagrevaju, ali ne tope, a topi se samo materijal za lemljenje, s obzirom da ima nisku
taku topljenja (reda 180oC).
Sl. 2.19. Koturovi ice za lemljenje (tinol ice).
18
Za runo lemljenje elektronskih komponenata materijal za lemljenje je najee tinol
ica, sl. 2.19, prenika ne veeg od 1 mm (optimalni prenik ovakve ice je 0,7 mm). Dosadanje
tinol ice, koje su se pokazale izuzetno efikasne u praksi, najee su sadrale 60% kalaja i 40%
olova (taka topljenja 178oC). Meutim, svi elektronski ureaji koji e se proizvoditi u zemljama
evropske unije ili koji e se u te drave uvoziti moraju da, u skladu sa direktivama RoHS (Re-
striction of Hazardous Substances), eliminiu iz proizvodnje tih ureaja olovo (Pb), kadmijum
(Cd), ivu (Hg), hrom (Cr) i brom (Br). Stoga se proces lemljenja u proizvodnji elektronskih
ureaja preusmerava na ice za lemljenje koje ne koriste olovo. U praksi to znai vie tem-
perature topljenja (to ima za posledicu i poveanje radne temperature opreme), slabiji, tj. sporiji
temperaturni odziv potrebno je dodatno vreme za rad bez olova, pojavljivanje mostova koji
ne obezbeuju dobar kontakt, a takoe povrina lema je hrapava, to oteava pregled spojeva.
Sl. 2.20. Runo lemljenje komponenata.
Kod runog lemljenja komponenata sa izvodima (sl. 2.20), neophodno je prvo dobro oi-
stiti sve delove koji e se lemiti, a zatim vrh lemilice nasloniti na lemno mesto tako da dodiruje i
provodni sloj na tampanoj ploi i metalni izvod komponente koji se lemi. Odmah potom treba
prisloniti tinol icu na taku koja predstavlja tromeu vrha lemilice, metalnog sloja ploice i
lemnog vrha komponente, sl. 2.21a. Ako je lemilica dobro zagrejana (na oko 300oC) i ako su
lemne povrine iste, vrh tinola e se trenutno istopiti i, zahvaljujui adheziji, poeti da obuhvata
sve metalne povrine. Bez prekida treba nastaviti da se uvodi tinol i, kad se proceni da ga je
dovoljno, skloniti tinol icu i nastaviti sa dranjem lemilice na istom mestu jo oko jedne sekun-
de, odnosno lem se ne sme dugo grejati moe doi do unitenja komponente ili odvajanja ba-
karne folije sa ploice. Posle toga se ukloni lemilica i procenjuje kvalitet uraenog lema. Ohla-
eni i oformljeni tinol treba da ima oblik kupe kao na noici koja je na sl. 2.21b.
Sl. 2.21. Runo lemljenje komponenata sa izvodima.
19
Treba napomenuti da, iako postoji posebna pasta za lemljenje, nju ne treba koristiti, s
obzirom da se u samoj tinol ici nalazi sredstvo koje pospeuje proces lemljenja. Meutim, to
sredstvo deluje samo u prvom trenutku, kad se tinol rastapa, a posle hlaenja postaje potpuno
neaktivno. Ovo sredstvo je neophodno, odnosno lemljenje je bez njega nemogue, ali ako
lemljenje nije uspelo iz prvog pokuaja (npr. ako tinol nije u celosti obuhvatio lemne povrine),
nita se nee popraviti samo lemilicom, bez novog tinola. Pored toga, kada delovi koji se leme
(bakarna folija na tampanoj ploi i izvodi komponente) nisu isti, ili je sam proces lemljenja
loe izveden, spojevi mogu da dobiju jedan od oblika kao na sl. 2.21c. U tom sluaju nije
preporuljivo dalje dodavanje tinola, iako se njegovim upornim nanoenjem mogu ostvariti spo-
jevi koji lie na one sa sl. 2.21b to su tkzv. hladni spojevi, tj. spojevi koji vizuelno izgledaju
kao dobri, a u stvari su neispravni, jer ne obezbeuju elektrinu vezu na mestima lemljenja.
Tada, kao i u sluaju da tinola ima previe na lemnom mestu, bolje ga je ukloniti pomou
vakuum pumpice (sl. 2.22), ponovo dobro oistiti lemne povrine, pa ponoviti proces lemljenja
od poetka. Vrh lemilice potrebno je s vremena na vreme obrisati vlanim suneriem, da bi se
odrao uvek istim, ali se ne sme koristiti sintetiki suner (onaj koji se obino koristi u do-
mainstvu za pranje), jer e se istopiti.
Sl. 2.22. Vakuum pumpica za uklanjanje vika tinola sa lemnog mesta.
Runo lemljenje komponenata za povrinsku montau (SMD-a) se obavlja lemilicama

male snage (12 W do 18 W) sa izuzetno uzanim vrhom. U tu svrhu se na mesto lemljenja na
tampanoj ploi prvo lemilicom nanese malo lemnog materijala iz tinola (sl. 2.23a), a zatim se na
ta ostrvca postavi SMD (sl. 2.23b). Potom se vrh lemilice zajedno sa tinol icom prisloni na to
ostrvce (sl. 2.23c), tako da se lemni materijal rastopi, a SMD lagano pritiska na dole sve dok ne
legne na svoje mesto, a lem dobije oblik kao na sl. 2.23c (desno).
Sl. 2.23. Runo lemljenje komponenata za povrinsko montiranje (SMD-a).
20
Za runo lemljenje SMD-a, uz izuzetnu spretnost izvrioca lemljenja, pored opisanog
lemljenja lemilicom, koriste se i duvaljke toplog vazduha, koje u principu izgledaju kao na sl.
2.24.
Sl. 2.24. Duvaljke toplog vazduha za lemljenje SMD-a.
Pored opisanog naina lemljenja SMD-a, postoji i lemljenje selektivnim grejaem. Na-
ime, posebno oblikovani zagrejani greja se postavlja samo na izvode komponenata, tako da se
svi izvodi (samo jedne komponente) istovremeno leme; ovaj nain lemljenja je posebno pogodan
za lemljenje integrisanih kola sa ravnim kuitima. Izvodi (ili kontaktni zavreci) ostaju pritisnuti
grejaem sve dok se mesto lemljenja ne ohladi. Nedostaci ovog lemljenja jesu to se na taj nain
ne mogu lemiti svi tipovi komponenata (npr. integrisana kola sa keramikim kuitima) i to se
istovremeno ne moe lemiti vie komponenata, ve samo jedna po jedna.
Pored tampanih ploa samo sa komponentama sa izvodima i iskljuivo sa komponenta-
ma za povrinsku montau, postoje i tampane ploe meovitog tipa, sl. 2.25a. Osnovni koraci
sklapanja (montae) tampanih ploa meovitog tipa prikazani su na sl. 2.25b. Prvo se ubacuju
komponente sa izvodima u otvore na ploi i krajevi privrste; zatim se ploa okree i nanosi
lepak (adheziv) na plou ili na komponentu. Posle nanoenja adheziva postavljaju se SMD i, da
bi adheziv formirao dobru vezu pri lemljenju, ploa se sui. Nakon toga se komponente leme.
Napominje se da je, takoe, mogue montiranje na istoj strani tampane ploe i SMD-a i kompo-
nenata sa izvodima.
Metode koje su nale iroku primenu pri lemljenju SMD komponenata, posebno pri
automatskoj montai SMD-a, jesu lemljenje razlivanjem i talasno lemljenje, sl. 2.26.
Za lemljenje razlivanjem neophodno je korienje paste za lemljenje. Pasta za lemljenje
je meavina osnovnog sredstva za lemljenje (obino srebro-paladijuma), vezivnog sredstva i
tenog materijala. Ova pasta se nanosi na tampanu plou, a zatim se komponente postavljaju
tako da se izvodi, odnosno kontaktni zavreci, praktino urone u pastu. Nakon toga se i tampana
ploa i komponente zagrevaju, pri emu se lem razliva i ostvaruje istovremeno lemljenje svih
komponenata; tipine temperature pri ovom nainu lemljenja su (215230)0C.
Kod talasnog lemljenja komponente se privruju za tampanu plou lepkom, odnosno
adhezivom i, nakon suenja, alje se velika koliina lema u obliku talasa preko ploe i kompo-
nenata. Za razliku od klasinog talasnog lemljenja koje se iroko primenjuje u konvencionalnoj
tehnici montae tampanih ploa sa komponentama sa izvodima, kod SMD talasnog lemljenja
se, najee, koristi dvostruki talas: najpre se turbulentnim talasom nanosi lem na sve kritine
21
take tampane ploe, a potom se laminarnim talasom sa tih mesta uklanja suvini lem. Nedo-
statak ovog naina lemljenja je potrebno relativno veliko rastojanje izmeu komponenata.
Sl. 2.25. a Meoviti tipovi tampanih ploa; b nain montae ploa meovitog tipa:
1. formiranje otvora (rupa) u ploi; 2. ubacivanje komponenata sa izvodima;
3. okretanje ploe i nanoenje adheziva; 4. nanoenje komponenta za povrinsko
montiranje; 5. gotove ploe, sa talasno zalemljenim komponentama.
Za ureaje automatske montae (sl. 2.27) komponente za povrinsko montiranje su naj-

ee pakovane u reljefne trake sa udubljenjima za smetaj komponenata, sl. 2.28. Reljefne trake
su od papira ili kartona i namotavaju se u koture, slino filmskim trakama (sl. 2.29). Sa ovih tra-
ka komponente se uzimaju pomou pipetnih jedinica. Pipetne jedinice za podizanje (uzimanje)
i postavljanje komponente predstavljaju osnovni deo ureaja za montau SMD-a na tampanu
plou. Njihova izvoenja mogu biti razliita, ali kod svih njih same pipete imaju par mehanikih
vilica i njima hvataju komponente iz leita u traci, a zatim ih kompjuterom upravljano sputaju
na odreena mesta na tanpanoj ploi.
22
Sl. 2.26. Prikaz osnovnih koraka pri lemljenju razlivanjem i talasnom lemljenju.
Sl. 2.27. Laboratorijski ureaji za montau SMD-a.
23
Sl. 2.28. Reljefne trake sa udubljenjima za smeta SMD-a.
Sl. 2.29. Trake sa komponentama za povrinsko montiranje (na slici levo su prikazani
elektrolitski kondenzatori).
24
3. OTPORNICI
Pod otpornikom se podrazumeva komponenta koja poseduje tano odreenu vrednost
otpornosti, a koja se koristi za regulaciju raspodele elektrine energije izmeu komponenata
elektronskog kola.
Na sl. 3.1 su prikazani simboli kojima se oznaavaju otpornici u emama elektronskih
kola.
Sl. 3.1. Simboli kojima se oznaavaju otpornici u emama elektronskih kola.
3.1. OPTE O OTPORNICIMA
3.1.1. Vrste otpornika

Sa aspekta otpornosti postoje tri osnovne grupe otpornika; to su: otpornici stalne otpor-
nosti, otpornici promenljive otpornosti (potenciometri) i nelinearni otpornici. Ako se dele po
konstrukciji, otpornici mogu biti slojni, od mase i iani. U zavisnosti od namene dele se na ot-
pornike opte i posebne namene.
U otpornike opte namene spadaju otpornici od kojih se ne trae povieni zahtevi u
odnosu na tanost njihove proizvodnje i stabilnost njihovih karakteristika pri eksploataciji. Oni
se koriste u razliitim oblastima elektronike (najvie u ureajima iroke potronje).
U otpornike posebne namene spadaju visokoomski, visokofrekventni, otpornici poviene
stabilnosti (precizni i poluprecizni) i neki drugi tipovi otpornika sa posebnim zahtevima.
Konstruktivni izgled otpornika stalne otpornosti prikazan je na sl. 3.2.
Sl. 3.2. Konstruktivni izgled otpornika stalne otpornosti: a otpornik od mase

(cilintrini); b slojni; c slojni sa prorezima; d slojni sa spiralnim narescima.
25
3.1.2. Osnovne karakteristike otpornika
1. Nazivna otpornost. Pod nazivnom otpornou, koja se jo zove i nominalna otpor-
nost, podrazumeva se otpornost otpornika pri normalnim radnim uslovima. Nazivna otpornost i
doputeno odstupanje otpornosti od nazivne vrednosti (tolerancija) najee su oznaeni na sa-
mom otporniku.
Otpornost otpornika konstantnog preseka povrine S i duine l data je izrazom:
l
R= , (3.1)
S
pri emu je specifina otpornost otpornog materijala, koja se izraava u mm2/m, m ili cm.
Otpornost cilindrinog otpornika ija je zapremina od otporne mase prenika D, prikaza-
nog na sl. 3.2a, iznosi:
4l
R= . (3.2)
D 2
S obzirom da kod slojnih otpornika (o kojima e vie biti rei u delu 3.2.2) debljina ot-
pornog sloja moe biti veoma mala, esto znatno ispod 1 m, to je kod njih u velikoj meri pore-
meena idealna atomska struktura, usled ega je specifina otpornost h takvih slojeva vea od
zapreminske specifine otpornosti v . Stoga se za karakterizaciju tankog otpornog sloja ko-
risti slojna otpornost RS jednaka odnosu specifine otpornosti tankog sloja h i njegove debljine
h:
h
RS = (3.3)
h
i izraava se u / (ita se oma po kvadratu).
Sl. 3.3. Zavisnost slojne otpornosti od debljine filma, uz specifinu otpornost filma h kao parametar.
26
Dakle, slojna otpornost RS zavisi od debljine filma i njegove specifine povrinske otpor-
nosti. To znai, a to se i vidi sa sl. 3.3, da bi se, na primer, dobila slojna otpornost RS = 100 / ,
mogue je koristiti materijale specifinih otpornosti h = 0,1 mm2/m, h = 1 mm2/m, h = 10
mm2/m ili h = 100 mm2/m sa debljinama filma h = 0,001 m, h = 0,01 m, h = 0,1 m ili h
= 1 m, respektivno. Treba napomenuti da se vea stabilnost karakteristika osigurava debljim
otpornim slojevima, pa je bolje za istu vrednost slojne otpornosti koristiti materijal vee specifi-
ne otpornosti h.
Otpornost slojnih otpornika cilindrinog oblika (jedan od takvih je prikazan na sl. 3.2b),
kod kojih je debljina otpornog sloja h znatno manja od prenika tela otpornika (h << D), data je
izrazom:
l l l
R = h = h = RS . (3.4)
Dh h D D
Da bi se poveala otpornost tankoslojnog otpornika, otporni sloj je ponekad prorezan ni-

zom neprovodnih crta (pruga) irine a, sl. 3.2c. Otpornost takvog otpornika odreena je irinom
neprovodne trake i njihovim brojem N i iznosi:
Ro
R= , (3.5)
Na
1
D
gde je Ro otpornost nenarezanog slojnog otpornika, data sa (3.4).

Poveanje otpornosti tankoslojnih otpornika cilindrinog oblika jo vie se postie spi-
ralnim narezivanjem neprovodnih traka, sl. 3.2d. Na ovaj nain moe se postii poveanje otpor-
nosti i nekoliko hiljada puta u odnosu na otpornost otpornika kada nema ovih traka. Otpornost
takvih otpornika je:
t 2 + 2 D 2
R = Ro , (3.6)
t (t a )
pri emu su: t korak narezane spirale (sl. 3.2d); a irina neprovodne trake; Ro otpornost
otpornika pre nego to su narezane neprovodne trake.
2. Nazivna (nominalna) snaga Pn. To je maksimalna dopustiva snaga koja se razvija na

otporniku u toku relativno dugog vremenskog perioda pri neprekidnom optereenju i odreenoj
temperaturi okolne sredine, pri emu parametri otpornika ostaju u odreenim granicama.
Pri optereenju otpornika snagama koje su iznad nazivne dolazi do razaranja otpornog
materijala, ime se smanjuje vek otpornika, ili, ak, do pregorevanja istog. Ova snaga se zasniva
na maksimalnoj temperaturi koju ne sme da pree nijedno mesto na otporniku. Nazivna snaga
zavisi od dimenzija otpornika i uslova hlaenja, kao i od uslova eksploatacije. Ovom snagom
odreena je i maksimalna vrednost struje kroz otpornik:
Pn
I max = . (3.7)
R
Vrednosti nazivnih snaga odreene su standardom. Na sl. 3.4 prikazani su, ako se to eli
posebno da naznai, nain obeleavanja nazivnih snaga otpornika snage od 0,25 W do 2 W i
dimenzije pojedinih otpornika zavisno od njihove nazivne snage.
27
Sl. 3.4. Obeleavanje nazivnih snaga otpornika (tamo gde se to eli da istakne)
i dimenzije pojedinih otpornika odgovarajue nazivne snage.
3.1.3. Nizovi nazivnih vrednosti otpornosti i klase tanosti

U cilju svrstavanja otpornika stalne otpornosti i kondenzatora nepromenljive kapacitivno-
sti u grupe sa tano utvrenim vrednostima otpornosti, odnosno kapacitivnosti, kao i zbog uni-
formnosti u proizvodnji i korienju otpornika i kondenzatora, koriste se nizovi nazivnih (nomi-
nalnih) vrednosti otpornosti i kapacitivnosti, koje je ustanovila Meunarodna elektrotehnika
komisija. Ovi nizovi se oznaavaju slovom E. Tako, postoje nizovi E6, E12, E24...E192 i kazuju
da u navedenim nizovima respektivno ima u jednom redu veliine 6, 12, 24...192 nazivnih
vrednosti otpornosti, odnosno kapacitivnosti. Nizovi su dobijeni zaokrugljivanjem vrednosti koje
slede iz 10n/q, pri emu je n ceo pozitivan ili negativan broj, a q = 6, 12, 24. ...192 (npr. niz E12
se dobija iz 10n/12), to se najbolje vidi iz T3.1. Numerike vrednosti navedene u T3.1
pomnoene sa 10m (m = 0, 1, 2, 3...) ine nizove otpornika i kondenzatora ije su otpornosti
izraene u , a kapacitivnosti u pF (zakljuno sa 106pF).
T3.1. E nizovi nazivnih vrednosti otpornosti nepromenljivih

otpornika i kapacitivnosti nepromenljivih kondenzatora
Oznaka Tole-
niza Nazivne vrednosti rancija
E6 1,0 1,5 2,2 3,3 4,7 6,8 20%
1,0 1,5 2,2 3,3 4,7 6,8
E12 10%
1,2 1,8 2,7 3,9 5,6 8,2
1,0 1,5 2,2 3,3 4,7 6,8
1,1 1,6 2,4 3,6 5,1 7,5
E24 5%
1,2 1,8 2,7 3,9 5,6 8,2
1,3 2,0 3,0 4,3 6,2 9,1
Klase tanosti. U procesu proizvodnje komponenata dobijaju se i komponente kod kojih

postoji odstupanje otpornosti, kapacitivnosti, induktivnosti, itd. od nazivne vrednosti. Maksimal-
no dozvoljeno odstupanje otpornosti, kapacitivnosti ili induktivnosti od nazivne vrednosti, tj. =
Nimax/Ni odreeno je klasom tanosti, odnosno tolerancijom. Tolerancija se obino izraava u
procentima. Za otpornike i kondenzatore opte namene propisane su tolerancije: 0,1%, 0,25%,
0,5%, 1%, 2%, 5%, 10% i 20%.
28
Nazivne vrednosti veliina i tolerancija meusobno su povezane tako da se maksimalna
stvarna vrednost veliine Nimax pri nazivnoj vrednosti Ni poklopi sa minimalnom stvarnom
vrednou parametra N(i+1)min sledee nazivne vrednosti N(i+1), tj. Nimax N(i+1)min. Na primer, za
niz E6 je tolerancija = 0,2. Pri nazivnoj vrednosti otpornosti Ri = 2,2 k je Rimax = 2,2(1 + 0,2)
= 2,64 k. Za sledeu nazivnu vrednost (T3.1) je R(i+1) = 3,3 k i R(i+1)min = 3,3(1 0,2) = 2,64
k. Kao to se vidi, dobija se potpuno poklapanje vrednosti otpornosti. Zbog toga, dakle, nema
smisla proizvoditi otpornike sa nazivnim vrednostima otpornosti veim od 2,2 k i manjim od
3,3 k sa tolerancijom 20%.
3.1.4. Oznaavanje otpornika

Otpornik mora sadrati sledee podatke: nazivnu otpornost (u , k ili M), toleranciju
nazivne otpornosti, nazivnu snagu (u W), granini napon (u V), itd. Ovi podaci se na otporniku
naznauju datim redosledom, a ako na telu otpornika nema mesta za sve podatke, onda prvenstvo
imaju oznake po nabrojanom redosledu.
Vrednosti nazivnih otpornosti, kao i tolerancija te otpornosti, nanose se na telo otpornika
ispisivanjem cifara i slova, ili boja. Otpornost ip otpornika obino se oznaava pomou tri cifre;
trea cifra kazuje koliko nula ima iza prve i druge cifre. Na primer: 220 221; 47 470;
5600 562. Kada se oznaavanje vri ciframa i slovima koristi se skraena notacija kao u
T3.2.
T3.2. Skraeno oznaavanje otpornika ciframa i slovima

Oznaavanje Primer
Jedinica jedinice me- skraenog Odgovarajue
merenja renja oznaavanja znaenje
E47 ili R47 0,47
Omi () E ili R 4E7 ili 4R7 4,7
47E ili 47R 47
Kiloomi K47 0,47 k 470
K 4K7 4,7 k
(k)
47K 47 k
Megaomi M47 0,47 M 470 k
M 4M7 4,7 M
(M)
47M 47 M
Gigaomi G47 0,47 G 470 M
G 4G7 4,7 G
(G)
47G 47 G
Teraomi
T
T47 0,47 T 470 G
(T) 1T0 1,0 T
Oznaavanje bojama vri se prema T3.3, sa napomenom da oznaavanje poinje prvom

bojom (odnosno trakom) koja je blia jednom (levom) kraju otpornika. Oznakom sa etiri trake
oznaavaju se otpornici sa dvocifrenom osnovnom vrednou otpornosti i sledeim vrednostima
tolerancije otpornosti: 1%, 2%, 5%, 10% i 20%. Sa pet traka oznaavaju se otpornici
koji imaju trocifrenu osnovnu vrednost otpornosti, sa tolerancijom otpornosti 0,1%, 0,25%,
0,5%, 1% i 2%. Znai, oznaavanje otpornika sa tolerancijama otpornosti 1% i 2% moe
biti i sa etiri boje i sa pet boja. Na sl. 3.5a dat je primer oznaavanja otpornika sa etiri boje, a
na sl. 3.5b sa pet boja.
29
Pored ovoga, prema publikaciji IEC 115-1 (klauzula 4.5), za otpornike kod kojih je bitna
mala temperaturna promena otpornosti, pri oznaavanju bojama mogu se koristiti i est traka; u
tom sluaju, esta traka, koja je dvostruko ira od ostalih, oznaava vrednost temperaturnog
koeficijenta otpornosti, T3.3.
T3.3. Oznaavanje otpornika bojama
Napomena: umesto 10-6 esto se koristi oznaka ppm, tako da je 10-6/ oC ppm/ oC.
Sl. 3.5a. Primer oznaavanja otpornika sa dvocifrenim osnovnim brojem: otpornik

otpornosti 1200 sa dozvoljenim odstupanjem otpornosti 5% i jedan takav otpornik.
Sl. 3.5b. Primer oznaavanja otpornika sa trocifrenim osnovnim brojem:

otpornik otpornosti 86,4 sa dozvoljenim odstupanjem otpornosti 0,1%
i nekoliko takvih otpornika; napomena: da ne bi dolo do zabune,
peta traka moe biti ira od ostalih 1,5 do 2 puta.
30
3.1.5. Stabilnost karakteristika otpornika
Pod dejstvom razliitih spoljanjih uticaja, kao to su toplota (hladnoa), vlanost, priti-
sak, potresi, radijacija, itd., parametri otpornika su podloni promenama, pri emu te promene
mogu biti povratne ili nepovratne, tj. posle ukidanja dejstva spoljanjih faktora nazivne vrednosti
mogu imati ili nemati prvobitnu vrednost.
1. Temperaturna stabilnost otpornosti. Povratne promene otpornosti otpornika pri

porastu temperature karakteriu se temperaturnim koeficijentom otpornosti R, koji je jednak
relativnoj promeni otpornosti pri promeni temperature:
1 dR 1
R = . (3.8)
R dT o C
Temperaturni koeficijent otpornosti, koji zavisi i od same vrednosti otpornosti, kod nena-
motanih otpornika ima vrednosti R = (110)10-41/oC, a kod namotanih otpornika R = (0
2)10-4/oC.
Treba napomenuti da vrednost temperaturnog koeficijenata otpornosti h tankih slojeva
zavisi od debljine sloja, sastava legure, naina nanoenja filma, vrste podloge i temperature.
Jedna tipina zavisnost temperaturnog koeficijenata otpornosti h nihromskog (nihrom legura
nikla i hroma) tankog filma od debljine filma prikazana je na sl. 3.6. Sa slike se vidi da vrlo tanki
filmovi nihroma imaju h < 0, a da je kod odreene debljine sloja h = 0.
Sl. 3.6. Temperaturni koeficijent otpornosti h nihromskog tankog

filma naparenog na staklenu podlogu kao funkcija debljine filma h.
Za opseg radnih temperatura T otpornost otpornika stalne otpornosti na nekoj tempera-

turi T vrlo priblino jednaka je:
R = Ro (1 + R T ) , (3.9)
pri emu je Ro otpornost otpornika pri temperaturi To, a T = T To.

Dugotrajno dejstvo poviene temperature moe dovesti do nepovratnih promena otpor-
nosti ili oteenja otpornika, a ove promene posebno su izraene kod nenamotanih otpornika.
31
Zbog toga, za svaki tip otpornika postoji maksimalna temperatura okolne sredine pri kojoj se
sme otpornik da optereti nazivnom snagom. Kada otpornik treba da radi pri viim temperatu-
rama, onda se mora opteretiti snagom koja je manja od nazivne, sl. 3.7.
Sl. 3.7. Zavisnost dopustive snage otpornika od temperature okolne sredine.
Kada se otpornik zagreje iznad temperature okoline To za vrednost T=TTo, to se ova

toplota mora preneti na okolinu. Ovo prenoenje toplote se, uglavnom, odvija preko spoljanje
povrine otpornika. U tom sluaju, snaga koju otpornik odaje spoljanjoj sredini iznosi:
P = ST , (3.10)
pri emu je S spoljanja povrina otpornika (povrina hlaenja), a koeficijent prenoenja to-
plote, ija je vrednost = (12)10-3 W/oCcm2.
2. Vlanost. Otpornost otpornika moe biti izmenjena u sluaju da je on pod uticajem

vlage. Ova promena otpornosti nastupa zbog toga to se usled vlane povrine otpornika stvara
provodni most, te se antira otpornik (ova pojava je izraenija kod otpornika velike otporno-
sti), ili se usled oksidacije i elektrohemijskih procesa razara otporni sloj otpornika. Zbog toga se
vri zatita povrine otpornika kvalitetnim lakovima, emajlima ili, pak, ulaganjem u plastine
mase. Na taj nain se, pored zatite od vlage, otporni sloj titi i od mehanikih povreda. Savre-
meni otpornici mogu raditi u sredinama sa relativnom vlanou i do 98%.
3. Elektrino optereenje. Za razliku od metalnih provodnika, otpornost nenamotanih

otpornika se ne potinjava u potpunosti Omovom zakonu. Naime, kod otpornika, ak i pri nezna-
tno malom porastu napona na njemu, otpornost toga otpornika poinje da opada, a sama pojava
ima nelinearan karakter. Nelinearnost otpornosti otpornika sa zrnastom strukturom uslovljena je
promenom provodnosti kontakata izmeu estica, to je posledica neravnomernog zagrevanja
istih. Kod kompozitnih otpornika sa vrlo grubom krupnozrnastom strukturom moe doi do
lokalnog stapanja zrnaca, usled ega se menja otpornost otpornika; kod isto metalnih slojeva se
ne primeuje nelinearnost otpornosti.
Kao mera nelinearnosti otpornosti moe posluiti naponski koeficijent otpornosti. Ovaj
koeficijent, ija je vrednost negativna, oznaava promenu otpornosti otpornika kada se na njega
prikljui napon V i jednak je:
1 R
V = 100 (%/V). (3.11)
V R
Kod ianih i metalslojnih otpornika vrednost koeficijenta U je zanemarljiva, dok se kod

otpornika od mase i slojnih kompozitnih otpornika o ovom koeficijentu mora voditi rauna.
32
4. umovi. U otpornicima su od znaaja dve vrste umova: termiki i strujni. Termiki
ili Donsonov um je posledica termike fluktuacije nosilaca naelektrisanja i nezavisan je od
vrste materijala od koga je izraen otpornik. Napon ovoga uma Vter se rauna na osnovu:
Vter = 4kTRf (V), (3.12)
pri emu su: k = 1,3810-23 J/K Bolcmanova konstanta, T (K) apsolutna temperatura, R ()
otpornost otpornika, f (Hz) irina frekventnog podruja u kome se meri um.
Strujni um, koji je posebno izraen kod nenamotanih otpornika, javlja se samo kada
protie struja kroz otpornik. On je posledica promene povrine kontakata izmeu zrna otpornog
materijala pri proticanju struje kroz otpornik. Usled toga ovaj um zavisi od fizikih osobina ma-
terijala i naina izrade otpornika, te se ak menja od jednog do drugog uzorka iste vrste otporni-
ka. Intenzitet strujnog uma, kao i termikog, izraen preko napona Vstr proporcionalan je kvad-
ratnom korenu iz otpornosti otpornika, ali, za razliku od termikog uma, zavisi od struje koja
protie kroz otpornik i slabo zavisi od temperature. Nivo ovoga uma se smanjuje sa poveanjem
duine otpornika i sa smanjenjem veliine zrna otpornog materijala. Na sl. 3.8 prikazan je strujni
um (kao odnos Vstr/V) u funkciji vrednosti otpornosti tri tipa otpornika (videti odeljak 3.2). Vidi
se da slojni kompozitni otpornici imaju nivo uma priblino za dva reda veliine vei nego to ga
imaju metalslojni otpornici.
Ukupan napon uma (V = Vter + Vstr) definie nivo sopstvenih umova, izraen preko
V/V. Po nivou sopstvenih umova standardni otpornici se dele na dve grupe. Prvu grupu ine ot-
pornici kod kojih nivo umova nije vei od 1 V/V, a drugu otpornici sa nivoom uma ne
veim od 5 V/V u frekventnom opsegu od (606000) Hz.
Sl. 3.8. Zavisnost strujnog uma od otpornosti tri tipa otpornika.
3.1.6. Frekventna svojstva otpornika

Otpornik, kao i svaka druga komponenta, poseduje reaktivne parazitne elemente LP i CP.
Na uestanostima na kojima se uticaj reaktivnih elemenata moe zanemariti, a to su niske ue-
stanosti, otpornost otpornika se moe smatrati aktivnom. Meutim, na visokim uestanostima,
pored aktivne komponente otpornosti postoji i reaktivni deo, tj. otpornik se ponaa kao impe-
dansa. Uzimajui aktivne i reaktivne elemente, uticaj uestanosti na karakteristike otpornika mo-
e se razmatrati na osnovu uproenih ekvivalentnih ema prikazanih na sl. 3.9.
33
Sl. 3.9. Uproene ekvivalentne eme otpornika: a velike otpornosti
(visokoomskog); b male otpornosti (niskoomskog).
Kod otpornika velike otpornosti, kod kojih je R2 > Lp/Cp, moe se zanemariti induktiv-
nost otpornika i ekvivalentna ema je predstavljena paralelnom vezom Rn i Cp, sl. 3.9a, tako da je
aktivna komponenta kompleksne otpornosti jednaka:
Rn
Ra = , (3.13)
1 + ( C p R n ) 2
pri emu je Rn nazivna otpornost otpornika. Iz (3.13) se vidi da se pri malim vrednostima CpRn
aktivna komponenta Ra malo razlikuje od Rn.
Smanjenje aktivne otpornosti otpornika na visokim uestanostima zavisi, takoe, i od
povrinskih efekata, skin efekta i dielektrinih gubitaka (u telu otpornika, keramici, zatitnom
sloju, itd.). Uzimanje svih ovih efekata pri proraunu uticaja uestanosti na karakteristike otpor-
nika je veoma kompleksno. Zbog toga se u praksi najee koriste zavisnosti promene otpornosti
od uestanosti dobijene eksperimentalnim putem, sl. 3.10. Iz ovih zavisnosti je evidentno da se
na visokim uestanostima aktivna komponenta otpornika velike otpornosti moe da smanji i ne-
koliko puta, o emu se mora voditi rauna pri upotrebi odreenog otpornika.
Sl. 3.10. Promena aktivne otpornosti visokoomskih ugljeninih otpornika sa uestanou.
S obzirom da otpornost otpornika zavisi od uestanosti, to e i dozvoljeni napon, takoe,

zavisiti od uestanosti. Naime, pri odravanju stalne vrednosti napona, usled postojanja parazitne
kapacitivnosti, na viim uestanostima struja kroz prethodno kolo bila bi uveana. Da do toga ne
bi dolo, na visokim uestanostima se napon ograniava na vrednost (Vmax = Vn kada tei nuli):
34
1
Vdoz = Vmax . (3.14)
1 + (C p R p )
2
Za razliku od visokoomskih otpornika, koji obino imaju spiralni narezak, niskoomski

otpornici se izrauju od glatkih povrina. Uproena ekvivalentna ema otpornika male otpor-
nosti prikazana je na sl. 3.9b. Kod ovih otpornika, sa nazivnim otpornostima manjim od 300 ,
uticaj parazitne kapacitivnosti je znatno manji od parazitne induktivnosti. Sa porastom uesta-
nosti impedansa raste i na nekoj uestanosti moe nastupiti rezonansa. Zavisnost modula impe-
danse otpornika od uestanosti ima oblik kao na sl. 3.11. Pri vrlo malim vrednostima nazivne
otpornosti otpornika (pri R2 < 5Lp/Cp) moduo impedanse otpornika moe imati maksimum (obi-
no na uestanostima iznad 100 MHz).
Sl. 3.11. Zavisnost modula impedanse niskoomskog otpornika od uestanosti.
3.2. NENAMOTANI OTPORNICI STALNE OTPORNOSTI

Konstrukcija otpornika je uslovljena njegovom primenom, tipom otpornog materijala i za
veinu otpornika je relativno prosta. Na sl. 3.12 su prikazani nenamotani otpornici sa izvodima, a
na sl. 3.13 otpornici za povrinsku montau (SMD) i razliite kombinacije otpornika konstantne
otpornosti, poznate pod nazivom otporniki moduli (otpornike mree).
Sl. 3.12. Spoljanji izgled nenamotanih otpornika sa izvodima konstantne otpornosti.
35
SMD
Otporniki moduli (otpornike mree)
Sl. 3.13. Otpornici za povrinsku montau (SMD) i otporniki moduli.
Nenamotani otpornici stalne otpornosti se mogu podeliti na nain prikazan na sl. 3.14.
Sl. 3.14. Podela nenamotanoh otpornika stalne otpornosti.
Nadalje e ukratko biti date osnovne osobenosti razliitih tipova otpornika konstantne
otpornosti. Pre svega bie rei o slojnim otpornicima, koji se sastoje od otpornog sloja (filma)
nanetog na izolacionu podlogu, na primer na keramiki tapi ili cevicu na ijim su krajevima
uvreni kontakti. Ovi otpornici su stabilnih elektrinih karakteristika, malih dimenzija, dugog
veka eksploatacije, itd.
Za nanoenje otpornih materijala u obliku tankih slojeva (filmova) koristi se ili vakuum-
sko naparavanje ili katodno raspravanje. Vakuumsko naparavanje je metoda kod koje se, u
uslovima pritiska reda (10-710-4) Pa, otporni materijal zagreva do temperature isparenja i koji
se, zatim, naparava na izolatorsku podlogu. Sa druge strane, metoda katodnog raspravanja ne
zahteva vakuum, ve se to raspravanje odvija u uslovima niskog pritiska, reda (0,020,1) Pa i u
prisustvu nekog inertnog gasa, npr. argona. Kod ove metode egzistira jako elektrino polje izme-
u katode i anode, ostvareno potencijalnom razlikom od (35) kV. Katoda je od materijala koji
treba da se nanese u tankom sloju na podlogu, dok je sama podloga u blizini anode. Pozitivni
joni, koji se generiu izmeu katode i anode, dobijaju dovoljnu kinetiku energiju da, udarivi u
katodu, izbacuju iz nje atome, odnosno jone materijala koji se naparava i koji se potom, pod
uticajem elektrinog polja, taloe na izolacionu podlogu.
36
Svaka od ovih metoda ima prednosti i nedostatke. Tako, katodnim raspravanjem se dobija-
ju homogeniji slojevi tekotopljivih, i po hemijskom sastavu, sloenijih materijala na veoj povr-
ini. Istovrermeno, pri procesu katodnog raspravanja, nastaje reakcija rasprenog materijala sa
ostacima gasova u komori, to ozbiljno pogorava osnovna svojstva tako dobijenih slojeva. Va-
kuumskim naparavanjem se dobijaju najistiji slojevi. Stepen zagaenja slojeva se kontrolie
pritiskom zaostalih gasova; za snienje pritiska praktino nema ogranienja. Sa druge strane,
pak, vakuumskim naparavanjem se mogu dobiti samo otporni slojevi relativno prostog hemij-
skog sastava.
3.2.1. Ugljenini otpornici

Ugljenini otpornici kao otporni materijal imaju sloj pirolitikog ugljenika na keramikoj
cevici ili tapiu. Debljina ovakvih slojeva, ija je otpornost znatno vea od otpornosti legura
metala, iznosi od 0,001 m do 1 m. Popreni presek slojnog ugljeninog otpornika prikazan je
na sl. 3.15, a na sl. 3.16 spoljanji izgled takvih otpornika.
Ove otpornike odlikuju jednostavnost proizvodnje, relativno mali negativni temperaturni
koeficijent otpornosti, mali nivo uma, mala zavisnost otpornosti od uestanosti i dovedenog
napona, poviena stabilnost. Stabilnost se poveava primenom debljih slojeva, posebnih zatitnih
prekrivaa, smanjenjem optereenja i radnih napona i dodavanjem male koliine bora.
Sl. 3.15. Presek slojnog ugljeninog otpornika.
Sl. 3.16. Spoljanji izgled nekih slojnih ugljeninih otpornika.
Otpornici sa dodatkom bora predstavljaju posebnu grupu ugljeninih otpornika i esto

se zovu otpornici od sloja karbida bora. Oni su veoma stabilnih karakteristika, ija je stabilnost
istog reda veliine kao i stabilnost ianih otpornika.
37
3.2.2. Metalslojni otpornici
Otporni sloj ovih otpornika, ija je debljina reda (0,10,5) m, a kao to se vidi sa sl.
3.14, moe biti sastavljen od legura metala (metalizirani), od oksida metala i od meavine metala
i dielektrika. Popreni presek jednog metalslojnog otpornika prikazan je na sl. 3.17.
Sl. 3.17. Presek metalslojnog otpornika.
Metalslojni otpornici su 23 puta manjih dimenzija od odgovarajuih ugljeninih otpor-

nika opte namene pri istoj nazivnoj snazi, sl. 3.18.
Ugljenini Metalslojni
Sl. 3.18. Uporedni prikaz dimenzija ugleninih i metalslojnih otpornika.
Pored otpornika sa klasinim aksijalnim izvodima, danas metalslojni otpornici poprimaju

i drugaije oblike, posebno kada je re o otpornicima koji omoguavaju njihov mehaniki kon-
takt sa hladnjacima. Tako, na sl. 3.19 su prikazani otpornici sa jednostranim izvodima i mogu-
nou vezavinja za hladnjake.
Sl. 3.19. Metalslojni otpornici pogodni za hladnjake sa jednostranim izvodima.
38
Metalizirani otpornici
Kod metalslojnih otpornika sa otpornim slojem od legura metala (metalizirani) legure su
obino sastavljene od vie metala; one mogu biti veome velike specifine otpornosti. Jedan od
esto upotrebljavanih otpornih materijala za metalizirane otpornike jeste legura hroma i nikla,
poznata i kao nihrom. Povrinska otpornost slojeva nihroma se regulie promenom odnosa hro-
ma i nikla u leguri, a kada im se dodaju male koliine bakra i alumunijuma, dobija se materijal
koji ima vrednost temperaturnog koeficijenta otpornosti priblino jednak nuli na sobnoj tempera-
turi (videti sl. 3.6).
Uopte, metalizirani otpornici imaju neke bolje, a neke loije karakteristike od odgovara-
juih ugljeninih otpornika opte namene pri istoj nazivnoj snazi. Naime, oni imaju bolje
temperaturne karakteristike i stabilniji su i otporniji na klimatske uslove (posebno vlagu), to se
postie dugotrajnom termikom i elektrinom stabilizacijom otpornog sloja. Nedostatak meta-
liziranih otpornika jeste manja pouzdanost pri veim disipacijama, posebno pri impulsnom radu,
to je posledica lokalnog pregrevanja nehomogenog otpornog sloja. Takoe, ovi otpornici imaju
loije frekventne osobine od ugljeninih otpornika.
Metaloksidni otpornici
Metaloksidni otpornici imaju otporni sloj od toplotnootpornih oksida metala, najee
dioksida kalaja ili oksida rutenijuma naneenih obino na staklenu podlogu (a ne na keramiku
kao kod metaliziranih otpornika). U poreenju sa metaliziranim otpornicima, proizvodnja metal-
oksidnih otpornika je prostija, karakteristike su im sline, dimenzije identine, imaju izrazito
nizak nivo uma, imaju vei temperaturni koeficijent otpornosti, ali su stabilniji pri impulsnim
optereenjima i mehanikim dejstvima.
Kermetni otpornici
Otpornici sa mikrokompozitnim filmovima od dielektrika i metala zovu se kermetni ot-
pornici (naziv kermet potie od KERamika i METal). Kermetni slojevi se odlikuju vrlo velikom
slojnom otpornou. Za tankoslojne otpornike najbolje karakteristike od kermetnih materijala po-
kazuje smesa hroma i silicijum monoksida. Taj kermet je homogen, ima visoko atheziono svoj-
stvo, visoku temperaturnu stabilnost i dobre mehanike osobine.
3.2.3. Slojni kompozitni otpornici

Ovo su, praktino, debeloslojni otpornici. Kod njih se otporni materijal, koji je sastavljen
od mehanikih smesa prahova provodnih materijala i organskih ili neorganskih dielektrika (kao
vezivnih sredstava), u relativno debelom sloju od 7 m do 20 m, nanosi na keramiku podlogu.
Jedan od takvih tipova otpornika jeste onaj kod koga se otporni sloj sastoji od smese stakla i
meavine provodnih materijala.
Zato to je otporni sloj kompozitnih otpornika vei nego kod tankoslojnih ugljeninih i
metalslojnih otpornika, to su ovi otpornici vrlo visoke pouzdanosti. Ostale dobre osobine su, po-
red pomenutog, jednostavnost izrade i, uprkos retkim i skupim metalima (koji se dodaju u ma-
lom procentu), niska cena. Nedostaci su niska stabilnost, visoki nivo umova, znatna zavisnost
otpornosti od prikljuenog napona i relativno loa frekventna karakteristika.
39
3.2.4. Maseni kompozitni otpornici
Otpornici od mase izrauju se od smese otpornih materijala i vezivnih sredstava. Ove
smese se na povienoj temperaturi najee presuju u obliku tapia. Proizvodnja je jevtina, ali
su veoma nestabilni, imaju relativno veliki um, otpornost im znatno zavisi od snage optereenja
i temperature okoline. Otpornost i snaga im je priblino ista kao kod slojnih otpornika.
Ovi otpornici se proizvode kao kompozitni i to na keramikoj bazi i na bazi laka. Otporni
materijal na keramikoj bazi je od smese ugljenika i peska (zato se ovi otpornici esto i zovu
ugljenini kompozitni otpornici).
Otporni materijali na bazi laka su smese grafita ili ai sa vezivnim sredstvima, kao to
su ugljovodonici i razliite vrste vetakih smola, sa dodatkom neorganskih materijala za ispunu
(azbestno brano ili liskunsko brano). Pri presovanju otpornog materijala na povienoj tempera-
turi, najee u obliku tapia, umeu se sa obe strane iani izvodi za prikljuke.
3.2.5. ip otpornici
ip otpornici, koji se koriste za povrinsko montiranje, mogu biti sa tankim (tankoslojni
SMD) i debelim (debeloslojni SMD) otpornim slojem. Na sl. 3.20 su prikazani osnovni delovi
jednog tankoslojnog ip otpornika za povrinsku montau: na supstrat, koji je od alumine, kera-
mike ili stakla, naneen je tanak sloj otpornog materijala. Tipini otporni materijali su: nihrom,
legura hroma i kobalta i tantalnitrid. Otporni sloj i kontaktna elektroda (kontaktni zavretak) spo-
jeni su metalnim filmom, odnosno spojnom elektrodom.
Pored ve klasinih ip otpornika za povrinski montirane tampane ploe, danas me-
talslojni otpornici poprimaju i drugaije oblike, posebno kada je re o veoma preciznim otpor-
nicima (sl. 3.21).
Sl. 3.20. Tankoslojni ip otpornik za povrinsku montau.
40
Sl. 3.21. Precizni metalslojni otpornici za povrinsku montau.
3.2.6. Otporniki moduli (otpornike mree)

Otporniki moduli se sastoje od vie otpornika smeenih u jedno kuite sa vie izvoda. Iz-
vodi mogu biti samo sa jedne strane (sl. 3.22) i tada se zovu SIL moduli (od single-in-line), i sa
obe strane (sl. 3.23), tzv. DIL moduli (od dual-in-line), u kuitima slinim onim koja se koriste
za integrisana kola. Moduli se mogu sastojati iz vie individualnih otpornika, ili su otpornici u
njima tako povezani da ine otpornike mree (stoga se ovi moduli zovu i otpornike mree).
Sl. 3.22. SIL (single-in-line) otporniki moduli (otpornike mree).
Sl. 3.23. DIL (dual-in-line) otporniki modul.
Na sl. 3.24 prikazan je presek otpornikog modula sa jednostranim izvodima i zajedni-

kim izvodom (tipa prvog modula na sl. 3.22). Sami otpornici u otpornikim modulima najee
su dobijeni ili tankoslojnom ili debeloslojnom tehnologijom.
41
Sl. 3.24. Presek otpornikog modula sa zajednikim izvodom.
3.3. NAMOTANI OTPORNICI STALNE OTPORNOSTI

Namotani ili iani otpornici se koriste svuda gde je neophodna velika snaga otpornika.
Ako se porede sa nenamotanim otpornicima, oni su od njih skuplji, proizvodnja je sloenija,
imaju vee dimenzije (sl. 3.25) i nisu pogodni za rad na viim uestanostima. Ipak, za posebne
primene ovi otpornici imaju bolje karakteristike od nenamotanih otpornika, jer se mogu koristiti
pri viim temperaturama, imaju veoma nizak nivo uma, veoma su stabilni i mogu se izraivati
za vee nazivne snage sa malim odstupanjem otpornosti od nazivne vrednosti. Neki tipovi i-
anih otpornika su standardizovani, ali se mnogi od njih rade van standarda za konkretne prime-
ne u elektronskim ureajima.
Sl. 3.25. Spoljanji izgled ianih otpornika sa i bez hladnjaka.
Ovi otpornici se dobijaju namotavanjem na izolacionu podlogu izolovane ili neizolovane

ice od legura velike specifine otpornosti (hromnikal, hromaluminijum, manganin, konstantan
42
ima negativan temperaturni koeficijent otpornosti R, kazma, evanom, itd). ice su razliitih
prenika. Izborom duine, prenika i legure od koje je otporna ica nainjena mogu se dobiti
otpornici od 0,1 do 1 M i snaga znatno iznad 10 W.
Sl. 3.26. Oklopljavanje ianih otpornika keramikim kuitima,

postavljanje hladnjaka na iste i vezivanje hladnjaka za asije.
S obzirom da iani otpornici rade sa velikim snagama, razvijajui, pri tom, visoke tem-
perature, neki od njih se ugrauju u keramika kuita sa ljebovima, koja omoguavaju da se na
njih relativno lako postave metalni hladanjaci, koji su ili slobodni, ili se, u cilju efikasnijeg
hlaenja, vezuju za same asije (sl. 3. 26). Na sl. 3.27 prikazan je spoljanji izgled ianih otpor-
nika sa hladnjacima.
Sl. 3.27. Spoljanji izgled ianih otpornika sa hladnjacima.
3.3.1. Temperaturna kompenzacija

Pogodna osobina ianih otpornika jeste mogunost temperaturne kompenzacije, koja se
postie namotavanjem osnovnog i kompenzacionog namotaja suprotnih znakova temperaturnih
43
koeficijenata otpornosti. Neka su R1o i R2o otpornosti osnovnog i kompenzacionog namotaja pri
temperaturi To, a 1 i 2 odgovarajui temperaturni koeficijenti otpornosti. Otpornost ovakve
redne veze, pri promeni temperature za T, na osnovu (3.9) je:
R + 2 R2 o
R = Ro (1 + u T ) = ( R1o + R2o )1 + 1 1o T . (3.15)
R1o + R2 o
Potpuna temperaturna kompenzacija bie kada je dR/dT = 0, odnosno kada je ukupni

temperaturni koeficijent otpornosti ove veze jednak nuli, odakle sledi uslov temperaturne kom-
penzacije:
R1o
= 2 . (3.16)
R2 o 1
3.4. OTPORNICI PROMENLJIVE OTPORNOSTI

(POTENCIOMETRI)
Potenciometri se primenjuju za runu regulaciju struja i napona u elektronskim kolima.
Na sl. 3.28 prikazani su simboli kojima se oni oznaavaju u emama elektronskih kola. Po
obliku, potenciometri mogu biti kruni i pravolinijski. Na sl. 3.29a prikazan je slojni kruni
potenciometar sa osnovnim delovima, a na sl. 3.29b pravolinijski (iber) potenciometar.
Sl. 3.28. Simboli kojima se oznaavaju potenciometri u emama elektronskih kola.
3.4.1. Osnovne karakteristike potenciometara

Pored osnovnih parametara koji definiu otpornike konstantne otpornosti, potenciometre
karakteriu jo i sledee osobine: nazivna vrednost ukupne otpornosti, minimalna otpornost,
poetni skok otpornosti, postojanost na habanje, dopunski kontaktni um i zakon promene otpor-
nosti.
Nazivna vrednost ukupne otpornosti potenciometra jeste otpornost izmeu nepokret-
nog (11) i pokretnog (12) izvoda (sl. 3.29a), pri maksimalnom uglu obrtanja m pokretnog siste-
ma ( = 270o300o) obrtnih potenciometara, odnosno pri maksimalnom poloaju klizaa kod
iber potenciometara.
Poetni skok otpornosti predstavlja minimalnu vrednost otpornosti od koje poinje rav-
nomerna promena otpornosti potenciometra. Ova vrednost obino iznosi (12)% ukupne otpor-
nosti za potenciometre sa logaritamskom promenom, odnosno (510)% za potenciometre sa li-
nearnom promenom otpornosti.
44
b.
a.
Sl. 3.29. a Slojni kruni potenciometar: 1 otporni sloj; 2 zakivka; 3, 11, 12 izvodi;
4 osnova od plastine mase ili pertinaksa; 5 izvod struje; 6 kontaktna etkica; 7 dra etkice;
8 osovina; 9 nosa zavrtnja; 10 metalni poklopac. b Pravolinijski (iber) potenciometar.
Postojanost na habanje je okarakterisana sposobnou potenciometra da sauva nepro-

menjene karakteristike pri viestrukom korienju pokretnih delova potenciometra. Ona se oce-
njuje brojem korienja tih pokretnih delova, a da pri tom karakteristike potenciometra ostanu u
dozvoljenim granicama. Ovaj broj korienja iznosi kod potenciometara opte namene do 50000,
a kod potenciometara za profesionalnu upotrebu 105107.
Dopunski kontaktni um nastaje izmeu otpornog elementa i pokretnog kontakta kako
pri pomeranju pokretnog sistema (um pomeranja), tako i pri fiksiranom poloaju istog. Nivo
uma pomeranja je znatno vei od nivoa termikog i strujnog uma.
Funkcionalna karakteristika otpornosti predstavlja zakon promene otpornosti izmeu
nepokretnog (12) i pokretnog (11) kontakta potenciometra (sl. 3.29a) pri pomeranju pokretnog
sistema, a zavisi od naina konstrukcije potenciometra. Najee se primenjuju potenciometri sa
linearnom (kriva 1 na sl. 3.30), logaritamskom (kriva 2) i inverzno-logaritamskom (kriva 3)
promenom otpornosti. Pored njih, postoje potenciometri i sa drugaijom promenom otpornosti,
na primer sa sinusnom, kosinusnom i drugim funkcionalnim zavisnostima.
Sl. 3.30. Funkcionalne karakteristike potenciometara:

1 linearna; 2 logaritamska; 3 inverzno-logaritamska.
45
Otpornost krunih potenciometara sa linearnom promenom otpornosti (linearnih potenci-
ometara) zavisi od ugla obrtanja pokretnog sistema, tako da je:

R = Rmin + ( Rmax Rmin ) , (3.17)
m
gde je Rmin poetna otpornost potenciometra, a Rmax njegova ukupna otpornost.

Kod potenciometra sa logaritamskom promenom otpornosti (logaritamskih potencio-
metara) logaritam relativne promene otpornosti je proporcionalan relativnom pomeranju pokret-
nog kontakta:
R
log =k . (3.18)
Rmin m
Logaritamski potenciometri se primenjuju za regulaciju jaine zvuka, s obzirom da se sa

njima moe postii proporcionalnost ugla obrtanja sa jainom zvuka (u decibelima). Inverzno-
logaritamska promena otpornosti (kriva 3 na sl. 3.30) koristi se kod potenciometara od kojih se
zahteva ravnomernija promena otpornosti pri veim uglovima obrtanja; obino se primenjuju za
regulaciju boje tona kod prijemnih i pojaavakih audio ureaja.
3.4.2. Vrste potenciometara

Kao i otpornici konstantne otpornosti, i potenciometri mogu biti nenamotani i namo-
tani. Nenamotani potenciometri najee imaju otporni materijal u obliku sloja (slojni potencio-
metri). Namotani ili iani potenciometri se najee proizvode za vee snage i reostate.
Slojni potenciometri imaju otporni sloj od ugljenika, oksida metala, razliitih kompozi-
cija, kermeta i provodnih plastinih masa. Nedostatak ugljeninih i kompozitnih potenciometara
je to imaju relativno slabu temperaturnu stabilnost. Boljom temperaturnom stabilnou odlikuju
se potenciometri sa otpornim slojem od oksida metala; oni su veoma stabilni, ali imaju nazivne
vrednosti otpornosti najvie do 100 k. Korienjem kermeta i provodnih plastinih masa kao
otpornih materijala, poslednjih godina su dobijeni potenciometri sa izuzetno dobrim eksploata-
cionim karakteristikama, dobrom regulacijom otpornosti, niskim nivoom strujnih umova i rela-
tivno malim dimenzijama.
Motani potenciometri se dobijaju motanjem ice od otpornih legura na bazi nikla, hroma,
bakra, mangana, a takoe i od ica prevuenih provodnom plastikom (hibritron potenciometri).
Ovi potenciometri imaju ogranienu oblast nazivnih otpornosti, poveanu parazitnu kapacitiv-
nost i induktivnost, vrlo visoku stabilnost, imaju nizak nivo strujnih umova i mali temperaturni
koeficijent otpornosti. Pri manjim snagama se motani potenciometri ree koriste od nenamota-
nih; obino se primenjuju za obezbeenje poveanih zahteva u pogledu tanosti i stabilnosti
elektrinih i eksploatacionih karakteristika elektronskih ureaja. Naprotiv, pri velikim snagama,
iskljuivo se koriste motani, i to iani, potenciometri.
a b. c.
Sl. 3.31. Spoljanji izgled nekih vieokretnih (helikoidalnih) potenciometara.
46
Posebnu grupu motanih potenciometara ine vrlo precizni vieokretni (helikoidalni) po-
tenciometri (sa tolerancijom otpornosti do 1%), sl. 3.31; kod njih, da bi se dobila maksimalna
vrednost otpornosti, kliza treba okrenuti (po 360o) 2-, 3-, 5- ili 10-puta. Mogu biti za direktnu ili
servo ugradnju (preko kainika, sl. 3.31c).
3.4.3. Regulacioni otpornici (trimeri)

Trimeri se koriste u kolima kada otpornost treba tano odrediti u toku njihovog podea-
vanja i koju ne treba esto menjati u toku eksploatacije. Po konstrukciji se ne razlikuju mnogo od
standardnih potenciometara, sem to su manjih dimenzija i, kao i oni, mogu biti jednookretni i
vieokretni, sa nenamotanim (ugljeninim, kermetnim) ili namotanim otpornim elementom. Na
sl. 3.32 prikazano je nekoliko razliitih oblika regulacionih otpornika, a na sl. 3.33 dva proiz-
vodnje BOURNS.
Sl. 3.32. Regulacioni otpornici (trimeri).
a.
b.
Sl. 3.33. Regulacioni otpornici (trimeri) proizvodnje BOURNS: a jednoobrtni
trimer; b trimer sa puastim zupanikom za pomeranje klizaa (kruna putanja klizaa).
47
3.5. OTPORNICI SA NELINEARNOM
PROMENOM OTPORNOSTI
Poslednjih godina sve veu primenu u elektronskim ureajima imaju otpornici ija otpor-
nost zavisi od spoljanjih uticaja, kao to su temperatura, svetlost, elektrino polje, mehanika
sila, itd. S obzirom da karakteristike ovih otpornika nisu linearne funkcije promene otpornosti sa
uzrokom promene otpornosti, to se ovi otpornici zajednikim imenom zovu nelinearni otpor-
nici. Na sl. 3.34 su prikazani osnovni tipovi nelinearnih otpornika.
Sl. 3.34. Osnovni tipovi nelinearnih otpornika.
Kada se otpornost otpornika menja sa temperaturom, takvi otpornici se zovu termistori i u

zavisnosti od naina zagrevanja (sl. 3.35), ovi otpornici se dele na termistore sa direktnim i indi-
rektnim zagrevanjem. Razlikuju se dve osnovne vrste termistora: sa negativnim temperaturnim
koeficijentom otpornosti (NTC otpornici) i sa pozitivnim temperaturnim koeficijentom otpor-
nosti (PTC otpornici, ili kako se jo zovu, pozistori). Otpornici kod kojih se otpornost nelinearno
menja pod uticajem elektrinog polja zovu se varistori ili VDR otpornici, a oni koji menjaju
otpornost pod uticajem svetlosti jesu fotootpornici (sl. 3.34).
Direktno zagrevanje Indirektno zagrevanje

Sl. 3.35. Naini zagrevanja termistora (NTC i PTC otpornika).
3.5.1. NTC otpornici

NTC otpornici su termistori sa relativno velikim negativnim temperaturnim koeficijen-
tom otpornosti. Najee se izrauju od polikristalnih oksidnih poluprovodnikih materijala
48
oksida prelaznih metala (od titana do cinka u Mendeljejevom sistemu). Veliku primenu su nali
oksidi kobalta (Co2O3), titana (TiO2), aluminijuma (Al2O3), nikla (NiO), mangana (Mn2O3),
cinka (ZnO), bakra (CuO i Cu2O), hroma (Cr2O3), kalaja (SnO), itd. Obino se upotrebljavaju
smese nekoliko oksida, od kojih se, metodom keramike tehnologije, dobijaju NTC otpornici
razliitog oblika, sl. 3.36.
SMD
3.36. Razliiti tipovi NTC otpornika (napomena: 2, 3, 4. i 5.

termistor su sa znatno duim izvodima nego to je prikazano na slici).
Radno telo NTC otpornika se pravi u obliku tapia, diska (tablete) i perlice (bisera).
Ponekad se minijaturni NTC otpornici oblika perlice smetaju u staklene ampule (sl. 3.36). NTC
otpornici oblika tapia imaju maksimalnu snagu od vie vati, snaga NTC otpornika u obliku
diska (tablete, ploice) dostie jedva 1 W, a minijaturni NTC otpornici oblika perlice su snaga od
nekoliko mW.
Nadalje e se razmatrati samo NTC otpornici sa direktnim zagrevanjem. Kod takvih NTC
otpornika promena otpornosti nastaje pod dejstvom toplote koja se razvija u telu termistora usled
struje koja protie kroz njega, ili kao rezultat promene temperature NTC otpornika usled prome-
ne toplotnog reima termistora (npr. pri izmeni temperature okolne sredine). Njihove najznaaj-
nije karakteristike su:
1. Temperaturna karakteristika NTC otpornika to je zavisnost otpornosti NTC ot-
pornika od temperature. Primer temperaturnih karakteristika razliitih NTC otpornika dat je na
sl. 3.37. U opsegu radnih temperatura zavisnost otpornosti NTC otpornika od temperature moe
se predstaviti sledeim izrazom:
B
R = R exp , (3.19)
T
gde je B koeficijent temperaturne osetljivosti, ili kratko, temperaturna osetljivost i izraava

se u Kelvinovim stepenima (K), T apsolutna temperatura (K) i R konstanta koja zavisi od
materijala i dimenzija NTC otpornika (to je uslovna otpornost termistora na beskonano visokoj
temperaturi).
2. Nazivna otpornost NTC otpornika to je njegova otpornost pri odreenoj
temperaturi (obino 20oC). Nazivne otpornosti razliitih tipova NTC otpornika kreu se od
nekoliko do nekoliko k.
49
Sl. 3.37. Temperaturne karakteristike razliitih NTC otpornika;
RT0 je nazivna otpornost NTC otpornika pri T = 20oC.
3. Koeficijent temperaturne osetljivosti B to je konstanta koja se nalazi u eksponentu

izraza kojim je definisana temperaturna karakteristika NTC otpornika, jedn. (3.19). Vrednost
ovog koeficijenta, koji zavisi od svojstava materijala od kojeg je NTC otpornik nainjen, prak-
tino je konstantna za dati termistor u opsegu radnih temperatura i za razliite tipove NTC ot-
pornika iznosi od B = 700 K do B = 15000 K.
4. Koeficijent disipacije NTC otpornika H brojno je jednak snazi koju treba dovesti
NTC otporniku da bi se on zagrejao za 1oC = 1K. Ovaj koeficijent se izraava u (mW/K) ili,
kada se rauna po jedinici povrine, u (mW/m2K). Vrednost koeficijenta disipacije zavisi od tipa
NTC otpornika i iznosi H = (0,530) mW/K.
5. Statika strujno-naponska karakteristika NTC otpornika to je zavisnost pada
napona na NTC otporniku od struje koja protie kroz njega u uslovima termike ravnotee
izmeu termistora i okolne sredine.
Na sl. 3.38 prikazana je statika strujno-naponska karakteristika NTC otpornika u dvo-
strukoj logaritamskoj razmeri, ija nazivna otpornost iznosi 10 k pri 20oC; za druge vrednosti
nazivnih otpornosti dobijaju se sline krive. Ova karakteristika se eksperimentalno snima pri
konstantnoj temperaturi okolne sredine.
Za svaku taku statike strujno-naponske karakteristike NTC otpornika postoji toplotna
ravnotea. Naime, u ustaljenom reimu zagravanja NTC otpornika strujom koja protie kroz
njega, sva snaga koja se razvija u termistoru predaje se okolnoj sredini, tako da je:
V2 U2
P= = I 2 R = H (T Tos ) , (3.20)
R R
gde je T temperatura NTC otpornika, a Tos temperatura okolne sredine.
50
Sl. 3.38. Statika strujno-naponska karakteristika NTC otpornika.
Iz (3.19) i (3.20) mogue je dobiti jednainu strujno-naponske karakteristike NTC otpor-

nika u parametarskom obliku:
B
V U = HR (T Tos ) exp ; (3.21)
T
I=
H
(T Tos ) exp B . (3.22)
R T
Dakle, oblik statike strujno-naponske karakteristike NTC otpornika odreen je samo ko-
eficijentom disipacije H, njegovom otpornou na temperaturi T i temperaturom okolne sredine.
Iz jedn. (3.21) i (3.22) mogue je odrediti ekstremume statike strujno-naponske karakteristike
uz uslov da su konstantni koeficijent temperaturne osetljivosti i koeficijent disipacije:
B B(B 4Tos )
Teks = , (3.23)
2
pri emu je Teks temperatura pri ekstremnoj vrednosti strujno-naponske karakteristike, tj. pri
dU/d I = 0. Iz jedn. (3.23) sledi:
statika strujno-naponska karakteristika NTC otpornika imae ekstremnu vrednost napona
samo ako je ispunjen uslov B > 4Tos;
temperatura, a to znai i otpornost NTC otpornika, pri ekstremnim vrednostima napona od-
reeni su samo vrednostima B i Tos. Temperatura NTC otpornika pri ekstremnim vrednostima
napona ne zavisi, na primer, od koeficijenta disipacije, a to znai da e maksimumi (i minimumi)
statikih strujno-naponskih karakteristika NTC otpornika biti tano pri jednoj te istoj vrednosti
otpornosti NTC otpornika, nezavisno od njegovog oblika i dimenzija.
51
3.5.2. PTC otpornici (pozistori)
Termistori sa velikom pozitivnom vrednou temperaturnog koeficijenta otpornosti se
drugim imenom zovu pozistori. Koriste se kao ograniavai struje (za prekostrujnu zatitu, sl.
3.39) i kao limitatori temperature (sl. 3.40), zatim za demagnetizaciju kolor-katodnih cevi, za
zatitu motora, za regulaciju struja u telefoniji (sl. 3.40), za zatitu telefonskih linija, itd.
SMD
SMD
3.39. PTC za prekostrujnu zatitu.
Sl. 3.40. PTC za prekostrujnu zatitu u telefonskoj aplikaciji (prva etiri)

i kao senzorski limitatori temperature (poslednja etiri).
Osnovne karakteristike PTC otpornika su:

1. Temperaturni koeficijent otpornosti pozistora ima pozitivnu vrednost (T > 0) samo u
odreenom intervalu temperature, a van tog opsega je T < 0 (sl. 3.41);
2. najee je vrednost temperaturnog koeficijenta otpornosti pozistora znatno vea od
apsolutne vrednosti T NTC otpornika;
3. promena otpornosti termistora sa temperaturom znatno zavisi od uestanosti; ova
promena je najvea pri jednosmernoj polarizaciji i opada sa porastom uestanosti signala koji se
prikljuuje na pozistor, sl. 3.41.
52
Sl. 3.41. Promena otpornosti pozistora sa temperaturom i uestanou.
U najveem broju sluajeva pozistori se izrauju na bazi keramike od barijum titanata sa

polikristalnom strukturom, ija se otpornost znatno smanjuje ako se doda izvesna koliina pri-
mesa. Naime, barijum titanat (BaTiO3) je dielektrik sa specifinom otpornou pri sobnoj tem-
peraturi od (10101012) cm. Ako se u barijum titanat unese mala koliina ((0,10,3)%) primesa,
kao to su lantan, niobijum, itrijum, specifina otpornost se smanjuje na vrednost (10102) cm.
U delu karakteristine promene otpornosti sa temperaturom, u kome je pozitivna vrednost
temperaturnog koeficijenta otpornosti, a za sluaj jednosmerne polarizacije (kriva 0 Hz na sl.
3.41), otpornost se moe aproksimirati izrazom:
R PTC = A + C exp(BT ) , (3.24)
gde su A, B i C konstante.
3.5.3. Varistori
Varistori ili VDR otpornici (sl. 3.42) su otpornici kod kojih se otpornost nelinearno me-
nja sa promenom jaine elektrinog polja, odnosno napona na njima (sl. 3.43). Koriste se za na-
ponsku stabilizaciju, posebno veih vrednosti napona.
Varistori se najee izrauju od cink oksida. Nelinearnost otpornosti od elektrinog po-
lja uslovljava nelinearnost i naponsko-strujne karakteristike varistora, sl. 3.44. Strujno-naponska
karakteristika varistora data je izrazom:
I = K V K U , (3.25)
gde je K konstanta, a koeficijent nelinearnosti varistora, ija vrednost (npr. proizvodnje SIE-
MENS) iznosi = 3055.
53
Sl. 3.42. Razliiti tipovi varistora.
Sl. 3.43. Promena otpornosti varistora u lin-lin i log-log razmeri.
Sl. 3.44. Naponsko-strujna karakteristika varistora u lin-lin i log-log razmeri.
Iako je izrazom (3.25) definisana strujno-naponska karakteristika, proizvoai merene

vrednosti struja i napona predstavljaju u obliku naponsko-strujne karakteristike; na sl. 3.45 je pri-
kazana jedna takva realna zavisnost. Sa slike se vidi da je u radnoj oblasti koeficijent nelinear-
nosti 38 (U-I karakteristika u log-log razmeri na sl. 3.44 je data za radnu oblast), a dobija se
na osnovu (3.25):
log I 2 log I 1 log1 log10 3 0 (3) 3

= = = = 38 .
log U 2 log U 1 log 470 log 390 2.67 2.59 0.08
54
Sl. 3.45. Realna naponsko-strujna karakteristika varistora.
3.5.4. Fotootpornici
Jedan tip fotootpornika prikazan je na sl. 3.46. Fotootpornici su poluprovodniki otpor-
nici kod kojih se otpornost smanjuje pod uticajm svetlosti. Rad poluprovodnikih fotootpornika
zasnovan je na efektu fotoprovodnosti (unutranjem fotoelektrinom efektu). Izrauju se od kad-
mijum sulfida (CdS), kadmijum selenida (CdSe), kadmijum sulfoselenida (CdSSe), cink sulfida
(ZnS), a za oblast infracrvenog zraenja od olovo sulfida (PbS), indijum antimonida (InSb), kad-
mijum telurida (CdTe), itd. U najveem broju sluajeva otporni materijal se nanosi na izolacionu
podlogu, a preko toga se prekriva providnim materijalom, sl. 3.47.
Sl. 3.46. Jedan od moguih spoljanjih izgleda fotootpornika (uveliano).
Osnovne karakteristike i svojstva fotootpornika su:

1. Statika strujno-naponska karakteristika predstavlja zavisnost jednosmerne struje
koja protie kroz fotootpornik od napona na njemu pri konstantnom osvetljaju, sl. 3.48a. Razlika
izmeu struje koja protie kroz fotootpornik kada je on osvetljen i struje neosvetljenog fotoot-
pornika (struje tame) zove se fotostruja. Strujno-naponska karakteristika fotootpornika je u ve-
ini sluajeva linearna ili bliska linearnoj, sl. 3.48a.
55
Sl. 3.47. Konstruktivni izgled fotootpornika: aploica od steatita; bfotoosetljivi otporni sloj (CdS);
celektrode za kontakt (ovde su u obliku elja); dprovidno kuite od epoksidne smole; eizvodi.
2. Promena otpornosti sa osvetljajem, sl. 3.48b, meri se pri razliitom osvetljenju ot-
pornika svetlou sloenog spektralnog sastava. Ova promena otpornosti iznosi 104105 puta.
3. Svetlosna karakteristika predstavlja zavisnost fotostruje IF od osvetljenosti E, pri
konstantnom naponu, sl. 3.49. U nekoj oblasti promene osvetljenosti za svetlosnu karakteristiku
se koristi zavisnost:
IF = A E , (3.26)
gde su: A konstanta koja zavisi od tipa fotootpornika; konstanta koja zavisi od talasne du-
ine svetlosti i tipa fotootpornika; E osvetljenost.
Sl. 3.48. a Strujno-naponska karakteristika fotootpornika; b promena otpornosti

dva fotootpornika sa osvetljajem.
56
Sl. 3.49. Svetlosna karakteristika fotootpornika.
4. Spektralna karakteristika (sl. 3.50) izraava relativnu promenu fotostruje u zavisno-

sti od talasne duine svetlosti koja pada na fotootpornik. Karakteristino je za sve fotootpornike
da postoji talasna duina opt, zavisno od materijala od koga je sainjen fotootpornik, pri kojoj je
najvea promena fotostruje. To je tzv. maksimalna spektralna osetljivost.
Sl. 3.50. Spektralna karakteristika fotootpornika.
57
4. KONDENZATORI
Kondenzator predstavlja sistem od najmanje dva provodna tela (ploe, folije, metalizi-
rane folije) razdvojena dielektrikom, a koji ima sposobnost akumulacije elektrine energije.
Na sl. 4.1 su prikazani simboli kojima se oznaavaju kondenzatori u emama elektron-
skih kola.
Sl. 4.1. Simboli kojima se oznaavaju kondenzatori u emama elektronskih kola.
4.1. OPTE O KONDENZATORIMA
4.1.1. Kapacitivnost kondenzatora

Osnovna veliina kondenzatora je njegova elektrina kapacitivnost C, koja je odreena
odnosom koliine naelektrisanja Q i napona V na oblogama kondenzatora:
Q
C= . (4.1)
V
Nazivna kapacitivnost jeste kapacitivnost pri normalnim radnim uslovima i oznaena je

na samom kondenzatoru. Nazivne kapacitivnosti kondenzatora sa dozvoljenim tolerancijama bi-
raju se iz nizova E6, E12... datih u T3.1. Kapacitivnost se izraava u faradima (F). Meutim, s
obzirom da je farad vrlo velika jedinica, kapacitivnost se obino izraava u mikrofaradima (F),
nanofaradima (nF) i pikofaradima (pF).
Kapacitivnost kondenzatora zavisi od vrste dielektrika, geometrijskog oblika, dimenzija,
itd. Uticaj dielektrika na kapacitivnost je uslovljen intenzitetom polarizacije samog dielektrika.
Kao to je poznato, sposobnost dielektrika da se polarizuje u elektrinom polju karakterie se
dielektrinom propustljivou, koja se jo zove i dielektrina konstanta:
= r o , (4.2)
gde je r relativna dielektrina konstanta dielektrika, a o dielektrina konstanta vakuuma i

ona iznosi o = 8,8510-12 F/m.
Kapacitivnost kondenzatora razliitih konstrukcija (sl. 4.2) izraunava se sledeim izrazi-
ma, u kojima je kapacitivnost u pF, a dimenzije u cm:
kapacitivnost ploastog kondenzatora sa N obloga (sl. 4.2a):
58
a. b.
Sl. 4.2. Kondenzatori razliitih konstrukcija: a ploasti sa vie obloga; b tubasti.
S (N 1) S ( N 1)
C = or = 0,0885 r , (4.3)
d d
pri emu je S povrina obloga, a d debljina dielektrika (rastojanje izmeu obloga);

kapacitivnost tubastog kondenzatora, dobijenog namotavanjem trake (sl. 4.2b):
bL
C = 0,177 r , (4.5)
d
gde je b irina, a L ukupna duina trake.

Kada je vie kondenzatora vezano paralelno (na sl. 4.3 su, kao primer, prikazana dva
paralelno vezana kondenzatora), ukupna kapacitivnost Cekv takve veze je:
n
C ekv = C i , (4.6)
i =1
a kada je njih vie vezano na red, ukupna kapacitvnost se izraunava na osnovu izraza:
1 n
1
= . (4.5)
C ekv i =1 C i
Sl. 4.3. Paralelno i redno vezivanje dva kondenzatora.
59
4.1.2. Klase tanosti; oznaavanje kondenzatora
Kada je to mogue, vrednosti kapacitivnosti kondenzatora (ako nije posebno naglaeno, u
pF), kao i dozvoljena odstupanja kapacitivnosti od nazivne vrednosti, nazivni napon, itd. ispisuju
se na samom telu kondenzatora. Dozvoljena odstupanja kapacitivnosti od nazivne vrednosti, koja
se izraavaju u procentima, definisana su klasama tanosti. Ta odstupanja mogu biti simetrina
(10%, 20%) i nesimetrina (10%, +30%). S obzirom da veoma esto, zbog malih dimenzija
kondenazatora, na njima nema mesta za ispisivanje tolerancije kapacitivnosti, to je za iste uveden
sistem slovnog oznaavanja (isti standard vai i za oznaavanje tolerancije otpornosti otpornika);
na primer, oznaka F se odnosi na toleranciju 1% (100 F 100 pF 1%), a J na toleranciju 5%
(47 J 47 pF 5%)1.
Pored toga, za oznaavanje kondenzatora koriste se i boje koje se nanose u obliku trake ili
take (videti fusnotu br. 2). Naalost, nain oznaavanja kondenzatora bojama, kao i slovima i
ciframa, nije jedinstven za sve vrste kondenzatora i esto odstupa od standarda. Kada se
kapacitivnost u pF oznaava pomou tri cifre, trea cifra kazuje koliko nula ima iza prve i druge
cifre. Na primer: 220 pF 221; 47 pF 470; 56 nF 563. Meutim, kada se kapacitivnost
oznaava takom iza koje je neka cifra, onda je C u F; na primer: .0047 0,0047 F. Na sl. 4.3
je prikazano nekoliko naina oznaavanja kondenzatora (uz korienje T2.1 i T2.2 u knjizi nave-
denoj u fusnoti br. 2).
0,22 F 10%, 250 VDC 4,7 nF, 400VDC

1000 pF = 1 nF 10%, 50
VDC
47 pF 20%, 0,47 F,
100VDC
0,15 F 20%, 100 VDC C = 2200 ppm/oC
20 pF 20%,
10 nF 20%, 250 VDC 330 nF 5%, 160 VDC 50 VAC, 400VDC
Sl. 4.3. Razliiti naini obeleavanja kondenzatora; naalost, mnogi proizvoai
imaju svoja interna obeleavanja, tako da je za konkretnu primenu kondenzatora
neophodno korienje kataloga dotinog proizvoaa.
1
O detaljnijem ozna~avanju kondenzatora, kako slovima tako i bojama, videti u knjizi: Stojan Risti}, "RLC kom-
ponente", Prosveta, Ni{, 2005.
60
4.1.3. Dielektrici i dielektrina konstanta
Kapacitivnost i karakteristike kondenzatora znatno zavise od toga koji je dielektrik upo-
trebljen u kondenzatoru. Pored podele na polarne i nepolarne, dielektrici se mogu podeliti i u
sledee grupe:
Liskun, staklo, keramika sa malim gubicima (keramika tipa I) i njima slini; koriste se
za kondenzatore ije su kapacitivnosti od nekoliko pF do nekoliko stotina pF.
Keramika sa velikom vrednou dielektrine konstante (keramika tipa II i tipa III); ko-
risti se za kondenzatore kapacitivnosti od nekoliko stotina do nekoliko desetina hiljada pF.
Papir i metalizirani papir; koristi se za kondenzatore kapacitivnosti od nekoliko hiljada
pF do nekoliko F.
Oksidni slojevi; koriste se za elektrolitske kondenzatore kapacitivnosti reda F i vee.
Dielektrici u obliku folija, kao to su stirofleks, poliester, polikarbonat, itd.; koriste se
za kondenzatore kapacitivnosti od stotinu pF do nekoliko F.
Dielektrina konstanta dielektrika zavisi, u optem sluaju, od temperature, napona i ue-
stanosti promene elektrinog polja izmeu obloga kondenzatora, a takoe i od niza drugih spo-
ljanjih faktora, to znai da je i kapacitivnost kondenzatora funkcija pomenutih veliina.
4.1.4. Otpornost izolacije i vremenska konstanta kondenzatora

Realni dielektrici poseduju neku elektroprovodnost, uslovljenu postojanjem slobodnih
jona i elektrona u njima. Ta provodnost je mala, ali ipak konana. Konstantna struja Icu koja
protie kroz dielektrik pod uticajem napona na oblogama kondenzatora i koja je, praktino, struja
gubitaka, zove se struja curenja. Prema tome, otpornost dielektrika, odnosno otpornost izola-
cije kondenzatora, a to je otpornost izmeu obloga kondenzatora, jednaka je:
V
R= . (4.6)
I cu
Struja curenja Icu je vrlo mala, reda stotog ili hiljaditog dela mikroampera (izuzev kod
elektorlitskih kondenzatora) i raste sa temperaturom priblino po eksponencijalnom zakonu, tako
da otpornost izolacije jako zavisi od temperature i veoma je velika (izraava se u megaomima,
gigaomima, a takoe i u teraomima). Otpornost izolacije prvenstveno zavisi od specifine zapre-
minske otpornosti dielektrika i od njegovih dimenzija (debljine d i povrine S):
d
R= . (4.7)
S
Otpornost izolacije se meri pri normalnim klimatskim uslovima. Sa poveanjem tempera-

ture ova otpornost se eksponencijalno smanjuje (sl. 4.4).
Za N = 2, iz (4.3) i (4.7) sledi:
RC = o r = C . (4.8)
Veliina C = RC se zove vremenska konstanta kondenzatora i izraava se u sekun-

dama. Kao to se iz (4.8) vidi, vremenska konstanta ne zavisi od dimenzija kondenzatora, ve
samo od fizikih osobina dielektrika. Praktino, vremenska konstanta kondenzatora predstavlja
61
vreme za koje koliina elektriciteta opadne na 1/e deo (ili 36.8%) poetne vrednosti. Ona, tako-
e, odreuje vremensko punjenje i pranjenje kondenzatora. Naime, neka je na kondenzator prik-
ljuen jednosmerni napon E. Napon na kondenzatoru nee trenutno dostii tu vrednost, ve e se
poveavati po zakonu:
t
VC = E 1 exp( ) . (4.9)
C
Sl. 4.4. Otpornost izolacije razliitih vrsta dielektrika u funkciji temperature pri 500 V
jednosmernog napona na oblogama kondenzatora: 1 liskun zatopljen epoksidnom
smolom; 2 izolovana keramika; 3 neizolovana keramika; 4 namotan impregnisan papir;
5 liskun zatpoljen bakelitom; 6 metalizirani papir; 7 impregnisani papir.
Ako je, pak, kondenzator bio napunjen i na njegovim oblogama je bio napon E, pri
njegovom slobodnom pranjennju napon na kondenzatoru e se smanjivati po zakonu:
t
VC = E exp( ). (4.10)
C
Treba naglasiti da su vremenske konstante kondenzatora ije su kapacitivnosti manje od 100

nF vie uslovljene konstrukcijom i spoljanjim izgledom kondenzatora, nego samim osobinama
dielektrika. Za razliite tipove kondenzatora vrednost vremenske konstante iznosi od nekoliko
sekundi do nekoliko dana (T4.1).
T4.1. Vrednosti vremenskih konstanti razliitih tipova kondenzatora

Tip kondenzatora Vremenska konstanta
Kond. sa plastinim folijama (polistirolni, stirofleksni) Nekoliko dana
Papirni Nekoliko sati
Tantalni elektrolitski Jedan do dva sata
Keramiki sa velikom vrednopu dielektrine konstante Nekoliko minuta
Aluminijumski elektrolitski sa nenagrienom anodom Nekoliko sekundi
62
4.1.5. Frekventna svojstva kondenzatora
Kapacitivnost kondenzatora zavisi od uestanosti i to zbog toga to se sa uestanou
menja dielektrina konstanta i, znatno ee, zbog toga to kondenzator poseduje i parazitne veli-
ine, kao to su parazitna otpornost i parazitna induktivnost LC. Na visokim uestanostima svaki
kondenzator se moe predstaviti ekvivalentnom emom kao na sl. 4.5. Ovom ekvivalentnom e-
mom obuhvaeni su ne samo osnovna kapacitivnost i otpornost kondenzatora, nego i induktiv-
nost i aktivne otpornosti izvoda.
Sl. 4.5. Ekvivalentna ema kondenzatora.
Induktivnost kondenzatora obino je mala i ima vrednost reda nanohenrija. Otpornost gu-
bitaka r, koja se sastoji od aktivnih otpornosti obloga kondenzatora i izvoda, za obine konden-
zatore (ne elektrolitske), iznosi desetine delova oma. Otpornost R >> r u naznaenoj ekvivalent-
noj emi jednaka je otpornosti izolacije kondenzatora (ova otpornost se obeleava i sa Rp pa-
ralelna otpornost).
Postojanje sopstvene induktivnosti uslovljava pojavu rezonance koja nastaje pri rezonant-
noj uestanosti:
1
fr = . (4.11)
2 LC C
To znai da e se kondenzator pri uestanostima f > fr ponaati kao impedansa koja ima
induktivni karakter. Drugim reima, kondenzator treba koristiti pri uestanostima f < fr, pri
kojima impedansa kondenzatora ima kapacitivni karakter. Najee se radni opseg uestanosti
bira tako da je najvia uestanost 23 puta nia od rezonantne uestanosti kondenzatora. Na sl.
4.6 prikazane su tipine zavisnosti impedanse aluminijumskih elektrolitskih kondenzatora i kon-
denzatora sa plastinim metaliziranim folijama od uestanosti.
Poveanje rezonantne uestanosti fr postie se smanjenjem parazitne kapacitivnosti LC.
Jedan od naina dobijanja malih vrednosti induktivnosti LC jeste primena kratkih izvodnica, ili
upotreba kondenzatora za povrinsko montiranje (SMD). Smanjenje induktivnosti LC kod namo-
tanih tubastih kondenzatora postie se postavljanjem kontakata izvodnica to je mogue blie
jedan drugome.
Gubici u parazitnim kapacitivnostima, do kojih neminovno dolazi usled konstruktivnih
izvoenja kondenzatora (inkapsulacija, zalivanje ili presovanje u plastine mase, itd.), kao i
gubici na otpornosti izolacije (otpornosti R = Rp na ekvivalentnoj emi na sl. 4.5) odreuju donju
graninu uestanost kondenzatora. Slika 4.7 prikazuje opseg uestanosti pri kojima se konden-
zatori sa razliitim dielektricima mogu koristiti. S obzirom da se konstrukcijom i tehnologijom
proizvodnje kondenzatora moe unekoliko da utie na frekventni opseg, to je dijagram na sl. 4.7
samo orijentacionog karaktera.
63
Sl. 4.6. Frekventna zavisnost modula impedanse: a aluminijumskih elek-
trolitiskih kondenzatora; b kondenzatora sa metaliziranim plastinim folijama.
Sl. 4.7. Frekventni opseg primene kondenzatora sa razliitim dielektricima.
4.1.6. Gubici u kondenzatoru

U realnom kondenzatoru, koji je prikljuen u elektrino kolo, jedan deo energije se uvek
bespovratno izgubi. Ovaj gubitak energije je posledica zagrevanja kondenzatora i rasejavanja to-
plote u okolnu sredinu. Pri tom, izdvojena toplota moe u kondenzatoru da dovede do nedopu-
stivog poveanja njegove temperature. Poveanje temperature iznad temperature okolne sredine
direktno je proporcionalno snazi gubitaka Pa. Kondenzatori velikih reaktivnih snaga, kod kojih
gubici energije imaju i ekonomski smisao, karakteriu se dopustivim gubicima snage Pa,dop.
Ukupna snaga gubitaka Pa u kondenzatoru iznosi:
64
Pa = P + Pm , (4.12)
gde je P snaga gubitaka u dielektriku, a Pm snaga gubitaka u metalnim delovima kondenzatora.

Gubici u dielektriku su, u osnovi, povezani sa procesom polarizacije dielektrika i njegovom
provodnou. Gubici u metalnim delovima uslovljeni su zagrevanjem obloga, izvoda i kontakata.
Sl. 4.8. a Redna ekvivalentna ema kondenzatora; b fazorski dijagram napona i struja.
Snaga gubitaka u kondenzatoru moe se izraziti preko gubitaka na ekvivalentnoj rednoj

otpornosti kondenzatora Re, sl. 4.8 (sl. 4.8 je redna ekvivalentna ema kondenzatora sa sl. 4.5).
Ekvivalentna redna otpornost Re i ekvivalentna kapacitivnost Ce iznose (zanemaruje se Lc):
Rp 1
Re = r + ; C e = C 1 + C za (R p C ) 2 >> 1. (4.13)
1 + (R p C ) 2 ( R p C ) 2

Ugao , koji dopunjuje ugao izmeu vektora struje I i napona U (sl. 4.8b) do 90o zove se
ugao gubitaka. Tangens tog ugla, ija je vrednost pri zadatoj kapacitivnosti kondenzatora C i
uestanosti direktno proporcionalna otpornosti gubitaka Re, zove se tangens ugla gubitaka
kondenzatora:
V Re R I 1
tg = e = r C + = tg m + tg , (4.14)
VCe 1 R p C
I
C
gde je tgm = rC tangens ugla gubitaka u metalnim delovima, a gubici u dielektriku su dati
uglom gubitaka i tangensom ugla gubitaka tg 1/(RpC).
Veliina inverzno proporcionalna tangensu ugla gubitaka (Q = 1/tg) jeste faktor dobro-
te kondenzatora (Q-faktor).
Kao to se iz jedn. (4.14) vidi, tangens ugla gubitaka jednak je zbiru tangensa ugla gu-
bitaka u metalu (tgm) i dielektriku (tg). Treba naglasiti da je tg dominantan pri vrlo niskim
uestanostima i da sa porastom uestanosti naglo opada. Sa druge strane, kao to je evidentno iz
jedn. (4.14), tgm raste sa uestanou, tako da se moe smatrati da je na visokim uestanostima
tg tgm, sl. 4.9a,b. Tangens ugla gubitaka, meren za razliite tipove kondenzatora u njihovom
radnom opsegu uestanosti, iznosi a10-4, pri emu koeficijent a ima vrednosti od jedinice za
vazdune do a = 1000 3000 za elektrolitske kondenzatore.
65
Sl. 4.9. Zavisnost tg: a od uesatnosti za kondenzatore sa nepolarnim dielektrikom;
b od uesatnosti za kondenzatore sa polarnim dielektrikom; c od temperature za
kondenzatore sa nepolarnim dielektrikom; d od temperature za kondenzatore sa
polarnim dielektrikom; e od napona.
4.1.7. Stabilnost kondenzatora

Elektrina svojstva i radni vek kondenzatora zavise od dejstva spoljanjih klimatskih i
mehanikih uticaja (temperature, pritiska, vlanosti, radijacije, vibracija, itd.).
Uticaj temperature ogleda se u promeni kapacitivnosti i ugla gubitaka (faktora dobrote
kondenzatora), a takoe i elektrine vrstoe. Naime, promena temperature utie na metalne
delove kondenzatora u vidu skupljanja ili irenja, usled ega se menja kapacitivnost. Isto tako,
promena temperature moe da utie i na dielektrik, koji moe ili da omeka (staklo), ili da se
rastopi (parafin), ili da ovrsne (kao ulje na niskim temperaturama), ili da u dielektriku nastanu
naprsline i pukotine. Pored pomenutih promena u dielektriku, sa promenom temperature menja
se i dielektrina konstanta dielektrrika.
Linearna promena kapacitivnosti kondenzatora sa temperaturom moe se predstaviti
izrazom:
C = C o (1 + C T ) , (4.15)
gde je Co kapacitivnost pri temperaturi To u odnosu na koju se meri promena kapacitivnosti, a C

je temperaturni koeficijent kapacitivnosti:
1 dC
C = . (4.16)
C dT
Ako promena kapacitivnosti sa temperaturom C(T) ima nelinearni karakter, to je za ocenu

temperaturne stabilnosti kapacitivnosti kondenzatora bolje koristiti relativnu promenu kapacitiv-
nosti C:
66
C (T ) C (To )
C = 100 (%). (4.17)
C (To )
Uticaj vlage na karakteristike kondenzatora moe biti znatan u sluaju da vlaga prodre u
dielektrik, ime se menja dielektrina konstanta dielektrika (dielektrina konstanta vode iznosi r
= 80), a to znai da se menja i kapacitivnost kondenzatora. Pored toga, prisustvo vlage znatno
smanjuje otpornost izolacije. Kao rezultat smanjenja otpornosti izolacije rastu gubici, posebno
pri povienim temperaturama, a takoe se smanjuje i elektrina vrstoa usled porasta verovat-
noe nastajanja toplotnog proboja. Pri konstantnom dejstvu vlage postoji mogunost nastajanja
elektrohemijskih pojava u dielektriku. Katastrofalne promene vrednosti parametara kondenzatora
najee se javljaju kod kondenzatora koji due vreme nezatieni rade pri visokoj vlanosti,
posebno u tropskim krajevima. Kondenzatori koji su zatopljeni u plastine mase mogu pouzdano
da rade pri relativnoj vlanosti vazduha do 90%, a hermetizovani do iznad 98%.
4.2. KONDENZATORI STALNE KAPACITIVNOSTI
Sl. 4.10. Razliite vrste kondenzatora stalne kapacitivnosti.
Kondenzatori stalne (konstantne) kapacitivnosti najee se dele prema vrsti upotreblje-

nog dielektrika, tako da se razlikuju: papirni kondenzatori, kondenzatori sa metaliziranim papi-
rom, kondenzatori sa plastinim i metaliziranim plastinim folijama, liskunski kondenzatori, sta-
kleni kondenzatori, keramiki kondenzatori, elektrolitski kondenzatori, itd. Vie informacija o
njima u odnosu na ono to e nadalje biti dato mogu se nai u knjizi navedenoj u fusnoti br. 2.
67
4.2.1. Papirni kondenzatori
Papir je jedan od najstarijih dielektrika koji se koristi pri proizvodnji kondenzatora. Pri
tom, papir mora biti posebno izraen (tkzv. kondenzatorski papir). Treba napomenuti da se
papir nikada ne koristi sam, ve se uvek impregnie sintetikim tenostima, mineralnim uljima,
votanim materijalima ili vazelinom. To se ini zbog toga da bi se smanjila higroskopnost kon-
denzatorskog papira. Istovremeno, na taj nain se poveava dielektrina vrstoa papira, ali po-
veava i koeficijent dielektrinih gubitaka.
Papirni kondenzatori se najee rade tubastog oblika namotavanjem papirnih traka iz-
meu kojih su, kao kondenzatorske obloge, metalne folije. Kao kondenzatorske obloge obino se
koriste aluminijumske folije, sl. 4.2b. U elektronici se papirni kondenzatori sve manje koriste i
zamenjuju se kondenzatorima sa plastinim folijama. Meutim, jo se koriste u telefoniji (npr. u
aluminijumskom kuitu), u energetskoj elektronici, za korekciju faktora snage, itd.
Nedostaci papirnih kondenzatora su postojanje vazdunih mehuria u papiru i velike
dimenzije samoga kondenzatora. Ovi nedostaci su, donekle, izbegnuti kod kondenzatora sa
metaliziranim papirom, kod kojih je jedna strana papirne trake metalizirana. Druga dobra
osobina ovih kondenzatora je autoregeneracija, koja se sastoji u sledeem: ako pod dejstvom
napona nastane proboj ili kratak spoj izmeu obloga, usled velike lokalne temperature isparie
veoma tanak sloj metala u okolini mesta proboja i spreie obrazovanje stalnog kratkog spoja.
Trea prednost u odnosu na papirne kondenzatore jeste manja dimenzija kondenzatora sa metali-
ziranim papirom, s obzirom da se umesto aluminijumskih folija (debljine oko 6 m) koristi sloj
metalizacije debljine (0,020,06) m.
Postoji vie razliitih tipova i modela kondenzatora sa metaliziranim papirom, od kojih se
izdvajaju: cilindrini kondenzatori za iroku potronju u plastinim kuitima, kondenzatori za
kompenzaciju faktora snage kod fluoroscentnih svetiljki, kondenzatori za kompenzaciju faktora
snage kod motora, itd.
4.2.2. Kondenzatori sa plastinim

i metaliziranim plastinim folijama
Kondenzatori sa plastinim folijama (filmovima) i metaliziranim plastinim folijama su
skoro u potpunosti potisnuli papirne kondenzatore, s obzirom da od njih imaju znatno veu
otpornost izolacije i istovremeno znatno manji tangens ugla gubitaka. Kao dielektrik koriste se
nemetalizirane i metalizirane folije od razliitih materijala, kao to su stirofleks (zove se jo i
polistiren i polistirol), poliester, polikarbonat, polipropilen, itd.
Konstrukcija kondenzatora sa plastinim folijama i metaliziranim plastinim folijama je
slina konstrukciji papirnih kondenzatora. Kada su folije nemetalizirane, one i metalne folije se
slau kao na sl. 4.11a (kod blok kondenzatora), ili se metalne folije, izmeu kojih se smetaju
dva ili tri sloja folija od pomenutih materijala, namotavaju (sl. 4.2b). Na sl. 4.11b je prikazan deo
blok kondenzatora sa metaliziranim plastinim folijama, a na sl. 4.12 spoljanji izgled tih kon-
denzatora (zovu se jo i metal-film kondenzatori). Kao to se sa sl. 4.11b vidi, kontaktiranje me-
talizacije sa izvodnicama ostvareno je posredstvom metalnog draa, za razliku od kondenzatora
sa folijama bez metalizacije (sl. 4.11a), u kome su metalne folije u direktnom kontaktu sa izvod-
nicama.
Pored izrazito boljih karakteristika u odnosu na papirne kondenzatore i kondenzatore sa
metaliziranim papirom u pogledu otpornosti izolacije, gubitaka, vremenske konstante, faktora
dobrote, frekventnog opsega, itd., nedostatak kondenzatora sa plastinim i metaliziranim plasti-
nim folijama je to imaju relativno malu zapreminsku kapacitivnost.
68
a. b.
Sl. 4.11. Detalji konstrukcije blok kondenzatora sa plastinim folijama (a)
i metaliziranim plastinim folijama (b).
Sl. 4.12. Spoljanji izgled kondenzatora sa metaliziranim folijama (metal-film kondenzatora).
Sl. 4.13. Spoljanji izgled stirofleksnih kondenzatora.
69
Od kondenzatora sa plastinim folijama u ureajuma iroke potronje najee se koriste
stirofleksni (polistirenski, polistirolski) i poliesterski (polietilenski) kondenzatori. Spoljnji iz-
gled nekih stirofleksnih kondenzatora prikazan je na sl. 4.13, a poliesterskih na sl. 4.14.
Osovne razlike izmeu stirofleksnih i poliesterskih kondnezatora prikazane su na sl. 4.15.
Sa sl. 4.15 se vidi da poliesterski kondenzatori imaju neto loije karakteristike od stirofleksnih,
ali treba naglasiti da se, za razliku od stirofleksnih foilija, poliesterske folije mogu metalizirati,
te postoje (oni se vie i koriste) i kondenzatori sa metaliziranim poliesterskim folijama.
Sl. 4.14. Spoljanji izgled razliitih vrsta poliesterskih kondenzatora.
a. b.
d. c.
Sl. 4.15. Uporedne zavisnosti promene kapacitivnosti sa temperaturom (a),
tg sa temperaturom (b) i uestanou (c) i otpornosti izolacije sa tempera-
turom (d) za stirofleksne i poliesterske kondenzatore.
Pored pomenutih, veliku primenu su nali i polikarbonatski (sl. 4.16) i polipropilenski

kondenzatori (sl. 4.17) koji su izraeni od metalizirane polikarbonatske, odnosno polipropilenske
70
folije, respektivno. Po elektrinim karakteristikama i polikarbonatski i polipropilenski konden-
zatori su veoma slini stirofleksnim kondenzatorima, ali za razliku od njih imaju 1015 puta ma-
nju zapreminu (manjih su dimenzija) i mogu se koristiti u irem temperaturnom opsegu.
Sl. 4.16. Spoljanji izgled razliitih vrsta polikarbonatskih kondenzatora.
Sl. 4.17. Spoljanji izgled razliitih vrsta polipropilenskih kondenzatora.
4.2.3. Liskunski kondenzatori

Liskunski kondenzatori, ili kako se jo zovu mika kondenzatori spadaju u red preciznih i
stabilnih kondenzatora primenljivih na visokim uestanostima. Ovi kondenzatori imaju izuzetno
malu rednu otpornost, maksimalni odnos kapacitivnosti i zapremine, mali i jako stabilan tempe-
raturni koeficijent kapacitivnosti i uske tolerancije.
Liskun je mineral sloenog hemijskog sastava i u prirodi se sree u vie razliitih varijan-
ti. Jedna od osobina liskuna, koja je iskoriena za proizvodnju kondenzatora, jeste mogunost
njegovog cepanja na tanke listie (zato se od njih mogu dobiti samo blok kondenzatori, sl. 4.18).
71
Sl. 4.18. Spoljanji izgled nekih liskunskih kondenzatora.
4.2.4. Stakleni kondenzatori

Stakleni kondenzatori su namenjeni za visoke uestanosti i dopunjuju nazivne vrednosti
kapacitivnosti liskunskih kondenzatora iz E-nizova. Kao dielektrik se koristi borsilikatno staklo.
To su blok kondenzatori (sl. 4.19) sa naslaganim listiima stakla i aluminijumske folije. Sami
kondenzatori su monolitni, izvanredno hermetiki zatvoreni.
Ono to staklene kondenzatore izdvaja od ostalih jeste to oni zadravaju stabilne karak-
teristike ak od 180oC do +200 oC i to su od svih ostalih kondenzatora najotporniji na ko-
smika i nuklearna zraenja, sl. 4.20 (u svemirskim letilicama upravo zato ima najvie ovih kon-
denzatora).
Sl. 4.19. Spoljanji izgled nekih staklenih kondenzatora.
4.2.5. Keramiki kondenzatori

Postoji veliki broj razliitih vrsta keramikih kondenzatora (njihov spoljanji izgled je
prikazan na sl. 4.21), a svi se primenjuju pri srednjim i visokim uestanostima. Iako su to, mo-
da, kondenzatori koji se brojano najvie koriste (zbog niske cene), u principu to nisu kvalitetne
komponente. Najee se dele u tri osnovne grupe: tipa I, tipa II i tipa III.
Keramiki kondenzatori tipa I (keramike tipa I su titanati magnezijuma ili kalcijuma,
sa r = 5 470) su temperaturno stabilni kondenzatori, sa kapacitivnou (10 30) pF/mm3. Ono
72
po emu se kondenzatori razlikuju od keramikih kondenzatora tipa II i tipa III jeste to je kod
njih promena kapacitivnosti sa temperaturom linearna, sl. 4.21.
Sl. 4.20. Uporedni prikaz otpornosti na promene kapacitivnosti razliitih

tipova kondenzatora usled kosmikog i nuklearnog zraenja.
Sl. 4.21. Spoljanji izgled razliitih vrsta keramikih kondenzatora.
Sl. 4.22. Temperaturne zavisnosti kapacitivnosti keramikih kondenzatora tipa I; oznaka, npr.
N1500, znai da je temperaturni koeficijent kapacitivnosti negativan i da iznosi C = 150010-6 1/oC.
73
Keramiki kondenzatori tipa II su temperaturno nestabilni kondenzatori sa velikom
vrednou dielektrine konstante (r = 700 15000), pogodni za upotrebu u kolima za spregu i
odvoenje ili odvajanje uestanosti, gde nisu bitni mali tangens ugla gubitaka ili velika stabil-
nost kapacitivnosti. Iako su kondenzatori malih dimenzija, kapacitivnosti su relativno velike, s
obzirom da se koriste keramike sa velikim vrednostima dielektrinih konstanti; kapacitivnost je
oko 500 pF/mm3.
Za razliku od keramikih kondenzatora tipa I, koji imaju definisan i stabilan temperaturni
koeficijent kapacitivnosti, keramiki kondenzatori tipa II imaju nestabilnu kapacitivnost, koja je
sloena funkcija temperature (sl. 4.23), uestanosti, prikljuenog napona i vremena rada konden-
zatora. Kod njih temperaturni koeficijent kapacitivnosti nije definisan, te se i ne normira.
Za keramike tipa II se koristi i naziv senjetokeramike. To su titanati i cirkonati barijuma
ili stroncijuma. Nju karakterie Kirijeva temperatura, tj. temperatura pri kojoj jedan tip kri-
stalne reetke prelazi u drugi tip. Tako, keramika na bazi titanata barijuma ima tetragonalnu kri-
stalnu strukturu na 25oC; poveanjem temperature do (120125)oC tetragonalna kristalna struk-
tura transformie u kubinu. Ovaj fenomen nije poeljan, s obzirom da poveava kapacitivnost, a
vraanje na prvobitnu kristalnu strukturu u toku vremena se odvija priblino po eksponenci-
janom zakonu. Proizvodnja keramike, njena metalizacija i zatopljavanje kondenzatora su iznad
Kirijeve temperature. Stoga se, tokom vremena, smanjuje kapacitivnost kondenzatora.
Sl. 4.23. Temperaturne promene kapacitivnosti keramikih kondenzatora tipa II.
Keramiki kondenzatori tipa III su veoma temperaturno nestabilni kondenzatori (sl.

4.24) sa izuzetno velikom vrednou dielektrine konstante (r = 50000100000), pogodni za
sprena kola, kola za blokiranje i slino, u kojima mali tangens ugla gubitaka, velika otpornost
izolacije i velika stabilnost kapacitivnosti nisu bitni. U poreenju sa keramikim kndenzatorima
tipa II, ovi kondenzatori imaju manju otpornost izolacije ili manji proizvod RC i vei tg (znai,
jo su loiji). Sa druge strane, usled vrlo velike vrednosti dielektrine konstante, ovi konden-
zatori imaju najveu zapreminsku kapacitivnost, iznad 1 nF/mm3.
74
Sl. 4.24. Temperaturna zavisnost kapacitivnosti keramikih kondenzatora tipa III.
4.2.6. Elektrolitski kondenzatori

Osnovna osobina elektrolitskih kondenzatora je velika zapreminska kapacitivnost, pose-
bno izraena pri malim radnim naponima. Velika kapacitivnost se postie upotrebom veoma tan-
kih oksidnih slojeva nekih metala (Al, Ta) kao dielektrika; naime, iz
S
C = or , (4.18)
d
vidi se da e, pri istim vrednostima povrine S i relativne dielektrine konstante dielektrika r,

kapacitivnost utoliko biti vea ukoliko je debljina dielektrika d manja. Stoga, da bi se obezbedio
dobar (ravnomeran) elektrian kontakt izmeu povrine tako tankog dielektrika (tj. oksida meta-
la) i druge elektrode (jedna elektroda je metalna folija ili tapi na kojoj je oksid, a druga obino
neoksidisana metalna folija, sl. 4.24a) neophodno je da se upotrebi provodna tenost zato se
koristi tean elektrolit (kod kondenzatora sa tenim elektrolitom, sl. 4.24a), ili mangan dioksid
koji ima poluprovodnike osobine (kod kondenzatora sa vrstim elektrolitom, sl. 4.24b). Drugim
reima, elektrolit ima ulogu produetka druge elektrode.
Aluminijumski kondenzatori sa tenim elektrolitom

Aluminijumski kondenzatori sa tenim elektrolitom (sl. 4.25) dele se na polarizovane i
nepolarizovane (bipolarne).
U osnovi je svaki polarizovani aluminijumski elektrolitski kondenzator izraen kao i
svaki drugi kondenzator: izmeu provodnih elektroda je izolator (sl. 4.25a). Kao jedna elekroda
(anoda) koristi se aluminijumska folija, koja je posebnim tehnolokim postupkom oksidisana.
Taj oksidni sloj predstavlja dielektrik, a njegova debljina zavisi od nazivnog napona konden-
zatora. Druga elektroda (katoda) je izvedena preko provodnog elektrolita (npr. rastvora glikola,
75
borne kiseline i amonijaka), a za dovod elektrine struje i kontakt sa elektrolitom koristi se druga
aluminijumska folija. Izmeu oksidisane aluminijumske folije i folije za dovod struje (katode)
nalazi se u elektrolitu uvijen (slino kao kod papirnih kondenzatora) papir. Papir ima ulogu
razdvajaa izmeu pozitivne folije (anode) i negativne folije (katode).
Sl. 4.24. Principijelna predstava konstrukcije polarizovanog elektrolitskog kondenzatora

sa tenim (a) i vrstim (b) elektrolitom.
Sl. 4.25. Spoljanji izgled razliitih vrsta aluminijumskih elektrolitskih kondenzatora.
Ono o emu mora da se vodi rauna jeste da pri inverznoj polarizaciji polarizovanog
elektrolitskog kondenzatora, ve pri naponu od 2V, nastaje proces oksidacije katodne alumini-
jumske folije, to se oituje poveanjem struje, a sve to dovodi do pogoravanja karakteristika
kondenzatora (pri veim inverznim naponima nastupa proboj uz jako ujan prasak). Zbog toga su
polarizovani alumijumski elektrolitski kondenzatori namenjeni za rad pri jednosmernoj polari-
zaciji, a kada se jednosmernoj polarizaciji superponira naizmenini napon, mora se voditi rauna
da pri negativnoj poluperiodi naizmeninog napona inverzni napon ne bude vei od 2V.
Kod nepolarizovanih (bipolarnih) elektrolitskih kondenzatora katodna neoksidisana fo-
lija je zamenjena oksidisanom folijom. Zbog toga ovi kondenzatori mogu raditi i pri jednosmer-
noj i pri naizmeninoj polarizaciji. Svaki od slojeva dielektrika moe se u takvom kondenzatoru
76
nalaziti pod punim radnim naponom. Meutim, s obzirom da se debljina dielektrika udvostruila,
pri istom nazivnom naponu kapacitivnost nepolarizovanih kondenzatora je dva puta manja u
odnosu na kapacitivnost polarizovanih kondenzatora.
Ve je ranije napomenuto (sl. 4.6a) da impedansa aluminijumsih elektrolitskih kondenza-
tora jako zavisi od uestanosti i temperature (u cilju kompletnosti, na sl. 4.26 ponovo su prika-
zane zavisnosti modula impedanse od uestanosti i temperature za dva razliita kondenzatora).
Naime, pri viim uestanostima ekvivalentna ema kondenzatora sa sl. 4.5, kada se zanemari
otpornost izolacije, koja je Ri > 100 M, svodi se na ekvivalentnu emu kao na sl. 4.27.
Niskonaponski Visokonaponski
Sl. 4.26. Moduo impedanse aluminijumsih elektrolitskih kondenzatora u
funkciji uestanosti i temperature.
Sl. 4.27. Ekvivalentna ema aluminijumsih elektrolitskih kondenzatora.
U tom sluaju moduo impedanse kondenzatora iznosi:
2
1
Z = r +2
Lc . (4.19)
C
U poslednjem izrazu r je, praktino, ekvivalentna redna ili serijska otpornost elektrolit-
skog kondenzatora, koja se esto obeleava sa ESR, i koja, za odreenu temperaturu, odgovara
minimalnoj vrednosti |Z| = f(f) sa sl. 4.26.
Pored modula impedanse, i tangens ugla gubitaka (sl. 4.28) jako zavisi od uestanosti i
temperature. Osim toga, vrednosti tg aluminijumskih elektrolitiskih kondenzatora nisu male.
Naprotiv. Upravo zbog tako velikih vrednosti tg, posebno na niskim temperaturama i relativno
niskim uestanostima (sl. 4.28), preporuljivo je ove kondenzatore koristiti samo pri jednosmer-
nim reimima, a ako je to neophodno, pri naizmeninim strujama vrlo niske uestanosti.
77
Sl. 4.28. Tangens ugla gubitaka aluminijumsih elektrolitskih kondenzatorau funkciji
uestanosti i temperature: a niskonaponski (100 F/63V); b visokonaponski (47 F/350V).
Kao to je u taki 4.1.4 napomenuto, kod elektrolitskih kondenzatora struja curenja nije ma-
la i ovde se ona ee zove struja gubitaka, a predstavlja struju koja pri prikljuenju jedno-
smernog napona protie kroz kondenzator. Struja gubitaka raste sa temperaturom (sl. 4.29a).
Kada je re o zavisnosti ove struje od vremena, treba rei da je odmah po ukljuenju napona ona
velika i zatim opada, tako da posle izvesnog vremena dostie konstantnu vrednost, sl. 4.29b.
Sl. 4.29. Zavisnost struje gubitaka od: a temperature, b vremena.
Ukoliko je aluminijumski elektrolitiski kondenzator due bio uskladiten, ili u samom

ureaju nije bio pod naponom, neophodno ga je ponovo formirati. Formiranje se vri pod na-
zivnim naponom i pri tome je dozvoljeno da struja gubitaka u prvom minutu bude vea i do 100
puta (sl. 4.29b) od dozvoljene; ukoliko taj uslov nije ispunjen (struja gubitaka u trenutku uklju-
enja je znatno vea od strostruke dozvoljene vrednosti), ili ne opadne posle (1020) min kao na
sl. 4.29b, takav kondenzator treba odbaciti.
78
Tantalni elektrolitski kondenzatori
Sa tenim elektrolitom
Sa vrstim elektrolitom
SMD (sa vrstim elektrolitom)

Sl. 4.30. Spoljanji izgled razliitih vrsta tantalnih elektrolitskih kondenzatora.
Princip rada tantalnih kondenzatora je slian radu aluminijumskih elektrolitskih konden-

zatora. Sami kondenzatori su manjih dimenzija, ali skuplji od aluminijumskih elektrolitskih kon-
denzatora. U poreenju sa aluminijumskim elektrolitskim kondenzatorima, pored vee zapremin-
ske kapacitivnosti, imaju i sledea preimustva: poveano vreme uskladitenja (od 5 do 10 godi-
na), s obzirom da je oksidni sloj na tantalu stabilniji nego na aluminijumu; manju struju gubita-
ka; manji tangens ugla gubitaka; due vreme ivota; mogunost rada pri znatno viim uestano-
stima (do 100 kHz). Dobra osobina tantala je i to to ne reaguje sa drugim materijalima sa ko-
jima je u dodiru, to doputa upotrebu elektrolita visoke provodnosti, ime se obezbeuje niska
redna otpornost.
Na osnovu vrste elektrolita, tantalni kondenzatori se dele na kondenzatore sa tenim i sa
vrstim elektrolitom (sl. 4.30). Kod kondenzatora sa tenim elektrolitom anode su obino u ob-
liku folija od tantala, koje se namotavaju slino kao kod aluminijumskih elektrolitiskih kon-
denzatorima.
Mnogo eu primenu imaju tantalni kondenzatori sa vrstim elektrolitom. Anoda moe
biti u vidu sinterovanog otpreska tantalnog praha, ili od ice tantala (za kondenzatore manje ka-
pacitivnosti), kao i u vidu tapia od tantala. Dielektrik sainjava tantal-oksidni sloj, a za elek-
trolit vrstih tantalnih elektrolitskih kondenzatora koristi se mangandioksid (MnO2, sl. 4.24b).
Provodnik za katodu je grafitna i srebrna prevlaka, koja se nanosi na sloj mangandioksida i na
nju lemi katodni izvod. S obzirom da MnO2 ima poluprovodnike osobine, ovi kondenzatori se
zovu i oksidno-poluprovodniki tantalni kondenzatori. Nedostatak im je to se, u sluaju pro-
boja, ponaaju kao kratak spoj, a zamena pola dovodi do ekspolozije samoga kondenzatora.
79
Kao i kod aluminijumskih elektrolitskih kondenzatora, i kod tantalnih elektrolitskih kon-
denzatora impedansa jaki zavisi od uestanosti. Meutim, kao to se vidi sa sl. 4.31, tantalni kon-
denzatori zadravaju kapacitivne osobine do znatno viih uestanosti. anodu.
Sl. 4.31. Zavisnost impedanse tantalnih elektrolitskih kondenzatora od uestanosti i temperature za

kondenzatore: a sa vrstim elektrolitom (8,2 F/35 V); b sa tenim elektrolitom (20 F/60 V).
4.2.7. UltraCap kondenzatori
Sl. 4.32. Spoljanji izgled ultraCap kondenzatora.
UltraCap kondenzatori su komponente koje su namenjene za uvanje energije, s obzirom

da imaju izuzetno velike vrednosti kapacitivnosti, iznad farada: 5 F, 10 F, 110 F, ak do 5000 F.
Stoga se one i tretiraju kao komponente koje, u energetskom smislu, popunjuju jaz izmeu elek-
trolitskih kondenzatora i punjivih baterija. Meutim, radni naponi ultraCap kondenzatora su niski
(Un 2,5 V), i njihov vek jako zavisi od temperature i vrednosti napona sa kojima su radili Za
80
postizanje veih vrednosti napona oformljuju se moduli sa vie redno i paralelno vezanih ultra-
Cap kondenzatora (sl. 4.33), ali se istovremno mora obezbediti hlaenje tih modula, da bi se
temperatura odravala to niom, jer se jedino u tom sluaju, moe garantovati njihov dug radni
vek.
Modul 300 F/14 V Modul 150 F/42 V

Sl. 4.33. Moduli od ultraCap kondenzatora.
U osnovi, ultraCap kondenzator je elektrohemijski dvoslojni kondenzator kojeg ine dve

elektrode uronjene u elektrolit. Ovi kondenzatori nemaju klasian dielektrik, ve je tu ulogu pre-
uzela elektrohemijski ostvarena (zato su to elektrohemijski kondenzatori) suprotstavljena ko-
liina naelektrisanja na oblogama od aktivnog ugljenika, sl. 4.34. Rastojanje izmeu pozitivnog i
negativnog naelektrisanja (kvazidielektrik) iznosi samo d = (25) nm, to uslovljava izuzetno ve-
like vrednosti kapacitivnosti (zbog C = orS/d).
Sl. 4.34. Konstrukcija ultraCap kondenzatora.
Treba naglasiti da su, zbog specifinosti izrade, kao i zbog toga to to nisu kondenzatori u
klasinom smislu rei (nemaju fiziki dielektrik), ultraCap kondenzatori poznati i pod drugim
imenima: elektrohemijski dvoslojni kondenzator, pseudokondenzator, superkondenzator, itd.
81
4.3. KONDENZATORI PROMENLJIVE KAPACITIVNOSTI
Kondenzatori promenljive kapacitivnosti, koji se obino koriste u oscilatorniim kolima za
promenu rezonantne uestanosti tih kola, dele se na obrtne kondenzatore (vazdune i sa vrstim
dielektrikom izmeu obloga), polupromenljive kondenzatore (trimere) i varikap diode. Na sl.
4.35 su prikazani simboli kojima se oznaavaju kondenzatori promenljive kapacitivnosti u
emama elektronskih kola.
Obrtni kondenzator Trimer kondenzator Varikap dioda

Sl. 4.35. Simboli kondenzatora promenljive kapacitivnosti u emama elektronskih kola.
4.3.1. Obrtni kondenzatori
Sl. 4.36. Izgled nekih kondenzatora promenljive kapacitivnosti.
Obrtni kondenzatori promenljive kapacitivnosti (sl. 4.36) se sastoje od grupe nepokretnih

paralelnih ploa statora i grupe pokretnih paralelnih ploa rotora. Rotorske ploe su tako
smetene da se izmeu svake dve statorske ploe nalazi po jedna rotorska ploa. Pri obrtanju
rotorskih ploa menja se aktivna povrina izmeu ploa, tj. menja se kapacitivnost kondenzatora.
Od oblika kondenzatorskih ploa jako zavisi promena kapacitivnosti u funkciji ugla obr-
tanja, odnosno, drugim reima, izborom oblika ploa kondenzatora moe se menjati uestanost
oscilatornog kola po eljenom zakonu pri obrtanju rotorskih ploa. Na primer, za kondenzatore
sa pravolinijiskom promenom uestanosti, koji se koriste u oscilatornim kolima u kojima se sa
obrtanjem rotorskih ploa uestanost menja linearno sa uglom obrtanja, rotorske ploe su srpa-
stog oblika, dok su za linearnu promenu talasne duine te ploe bubreastog oblika.
4.3.2. Polupromenljivi kondenzatori trimeri

Kod polupromenljivih kondenzatora (trimera), sl. 4.37, kapacitivnost se menja samo u
toku podeavanja elektronskih kola, a u toku eksploatacije ostaje stalna. Proizvode se vazduni
polupromenljivi kondenzatori i kondenzatori sa vrstim dielektrikom. Svi polupromenljivi kon-
denzatori imaju izolacionu podlogu (npr. keramiku) za koju se privruje stator, leite za ro-
torsku osovinu i izvode pomou kojih se kondenzator lemi za tampanu plou. Kapacitivnost je
odreena povrinom i debljinom rotora i dielektrinom konstantom materijala izmeu rotora.
82
Sl. 4.37. Vieslojni keramiki trimer kondenzatori.
4.3.3. Varikap diode
Sl. 4.38. Varikap diode u razliitim kuitima.
Varikap diode su poluprovodnike diode (o diodama i p-n spoju videti glavu 8) sa kon-
trolisanim kapacitivnim osobinama. Kod njih se koristi kapacitivnost inverzno polarisanog p-n
spoja, pri emu se promenom inverznog napona menja irina prelazne oblasti p-n spoja, a time i
kapacitivnost varikap diode. Zbog toga se varikap diode mogu koristiti umesto klasinih promen-
ljivih kondenzatora (npr. za podeavanje oscilatornih kola).
Prednosti varikap dioda u odnosu na vazdune promenljive kondenzatore su:
neuporedivo su manjih dimenzija i mogu da se oklope zajedno sa kalemom, ime se izbe-
gavaju parazitne sprege;
otpornije su na mehanika dejstva (udare, potrese, itd.) i atmosferski uticaj;
ne postoji osovina kao kod vazdunih promenljivih kondenzatora, ve se promena kapaci-
tivnosti vri promenom napona na diodi, to se moe ostvariti promenom otpornosti poten-
ciometra, koji moe biti daleko od same diode, sl. 4.39.
Sl. 4.39. Uz ilustraciju promene napona na varikap diodi.
83
Nedostaci varikap dioda kao kondenzatora su:
gubici su vei nego kod vazdunih promenljivih kondenzatora;
kapacitivnost je nelinarna funkcija napona, usled ega nastaju izoblienja, to dovodi do
pojave viih harmonika.
Od posebnog znaaja su varikap diode sa superstrmim p-n spojem kod kojih je promena
kapacitivnosti sa inverznim naponom Vinv data izrazom:
Co
C= 2
, (4.20)
V
1 + inv
Vk

gde je Vk tkzv. kontaktna razlika potencijala koja za silicijumske diode iznosi oko 0,9 V (videti
glavu 8), a C0 je kapacitivnost nepolarisane varikap diode.
Kada se varikap dioda sa promenom kapacitivnosti po (4.20) iskoristi za oscilatorno LC
kolo, onda je rezonantna uestanost
C 1 / 2 ((Vk + Vinv ) 2 )
1
(V k + Vinv ),
1 / 2
fr =
2 LC
tj. uestanost oscilatornog kola se linearno menja sa naponom.
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5. KALEMOVI
Kalem (sl. 5.1) je elektronska komponenta koja poseduje reaktivnu otpornost direktno
proporcionalnu uestanosti dovedenog signala na tu komponentu; koeficiejent proporcionalnosti
izmeu otpornosti i uestanosti predstavlja induktivnost tog kalema. Na sl. 5.2 su prikazani sim-
boli kojima se oznaavaju kalemovi u emama elektronskih kola.
Sl. 5.1. Razliite vrste kalemova.
Kalem se jezgrom Kalem sa jezgrom Kalem bez jezgra

induktivnosti L induktivnosti L
Sl. 5.2. Simboli kojima se oznaavaju kalemovi u emama elektronskih kola.
5.1. OPTE O KALEMOVIMA
5.1.1. Induktivnost kalemova

Pri promeni magnetne indukcije B u toku kratkog vremenskog intervala (dt), u provodniku
se indukuje elektromotorna sila e:
dB
e = S , (5.1)
dt
gde je S povrina dejstva magnetne indukcije.
85
Dakle, ako se na provodnik prikljui jednosmerni napon, to se jednosmerna struja u nje-
mu odmah ne uspostavlja, s obzirom da se neposredno nakon prikljuenja napona stvara mag-
netno polje (sl. 5.3) koje ne dozvoljava trenutno uspostavljanje struje (zbog nastanka elektromo-
torne sile suprotnog znaka). Kada se magnento polje ustali (postane konstantno), to ono prestaje
da utie na proticanje jednosmerne struje.
Sl. 5.3. Nastanak magnetnog polja pri proticanju struje kroz provodnik.
U sluaju da se na provodnik prikljui naizmenini napon, to se struja i uspostavljeno

magnetno polje naizmenino menjaju. Pri tom, indukovana elektromotorna sila dovodi do pojave
otpornosti proticanju struje. Ova otpornost nije povezana sa gubicima energije, tj. to je reaktivna
otpornost i proporcionalna je uestanosti primenjenog naizmeninog napona, a koeficijent pro-
porcionalnosti L nazvan je induktivnou i izraava se u henrijima (H). Drugim reima, ako je XL
reaktivna otpornost, a kruna uestanost, to je:
X L = L . (5.2)
Za poveanje induktivnosti provodnik se mota spiralno (sl. 5.3), tako da se svaki zavojak
ne nalazi samo u svom magnetnom polju, ve i u magnetnom polju susednog zavojka. Induk-
tivnost takvog namotanog provodnika je mnogo vea od induktivnosti nenamotanog provodnika
iste duine.
5.1.2. Kalemska tela i vrste namotaja

Od kalemskog tela unekoliko zavise i karakteristike kalema. Kalemska tela su obino
cilindrinog oblika sa glatkom ili rebrastom povrinom od lakoobradivih materijala (sl 5.4), ali
mogu biti i u obliku prizme, posebno za kalemove za povrinsko montiranje (SMD).
Namotaji mogu biti jednoslojni i vieslojni. Kod jednoslojnih kalemova zavojci su jedan
do drugoga bez koraka (sl. 5.5) ili su razmaknuti sa korakom (sl. 5.6). Korak zavojaka (p
na sl. 5.6) bira se na osnovu razliitih konstruktivnih zahteva; sa jedne strane, pri poveanju
koraka smanjuje se magnetna veza izmeu zavojaka, usled ega se smanjuje induktivnost, a sa
druge strane to smanjuje sopstvenu (parazitnu) kapacitivnost kalema. U jednoslojne kalemove
spadaju i tampani kalemovi (sl. 5.7), koji mogu biti krunog, pravougaonog, estouagaonog ili
kvadratnog oblika u vidu rama.
Za dobijanje veih vrednosti induktivnosti proizvode se vieslojni kalemovi (sl. 5.8).
Meutim, vieslojni kalemovi sa zavojcima motanim po pravilnom redu (sl. 5.9) imaju mali Q-
faktor, malu stabilnost i veliku sopstvenu kapacitivnost, tako da su primenljivi samo kao prigu-
nice i u opsegu dugih talasa u radiodifuziji. Zbog toga se za motanje vieslojnih kalemova kori-
86
sti unakrsno (sl. 5.9) i nasumino motanje (sl. 5.10), ime se postie da takvi kalemovi imaju
relativno veliki Q-faktor (Q = 80100) i neznatnu sopstvenu kapacitivnost. Pored toga, ovakav
nain motanja obezbeuje veliku mehaniku vrstou ak i bez kalemskog tela.
SMD
Sl. 5.4. Kalemska tela i presek jednog kalema za povrinsko montiranje (SMD).
Sl. 5.5. Jednoslojni kalemovi bez koraka.
Sl. 5.6. Jednoslojni kalem sa korakom.
87
Sl. 5.7. Neki od tampanih kalemova.
Sl. 5.8. Vieslojni kalem sa osnovnim veliinama koje

su neophodne za njihov proraun.
Jedan od naina da se obrazuju zavojci jeste motanjem ice. Mogu se ostvariti motanjem
hladne zategnute ice (kalemovi sa stegnutim zavojcima) ili sa neznatno zategnutom icom koja
je zagrejana do (80120)oC i koja nakon hlaenja vrsto prijanja za kalemsko telo (kalemovi sa
vruim zavojcima). Drigi nain je taloenjem sloja metala na neko izolatorsko kalemsko telo.
Ovakvi kalemovi imaju neto nii Q-faktor od odgovarajuih kalemova dobijenih namotavanjem
ice, ali su zato znatno stabilniji.
Sl. 5.9. Dvoslojni (vieslojni) kalem sa unakrsnim motanjem.
88
Sl. 5.10. Dvoslojni (vieslojni) kalem sa nasuminim motanjem.
Za namotaje se najee koriste lakom izolovane bakarne ice. Pored masivne ice,
koriste se i visokofrekventni (VF) gajtani. VF gajtan se sastoji od upredenih tankih, lakom izo-
lovanih bakarnih ilica, debljine (0,05 0,1) mm. Upredanjem ilica se znatno smanjuje uticaj
skin efekta, s obzirom da je svaka ilica aktivna pri provoenju struje. Zbog toga je Q-faktor
kalema sa VF gajtanom pri visokim uestanostima vei nekoliko puta od Q-faktora odgovaraju-
eg kalema motanog masivnom icom.
5.1.3. Frekventna svojstva kalemova

Ekvivalentna ema kalema izgleda kao na sl. 5.11a, na kojoj je L induktivnost kalema, C0
parazitna (sopstvena) kapacitivnost, a R = R0 + Rf je otpornost gubitaka, koja, pored omske ot-
pornosti R0, sadri i frekventno zavisne otpornosti usled skin efekta i efekta blizine Rf. Kod kale-
mova se jezgrom otpornost R sadri i gubitke u jezgru Rj; dakle, R = R0 + Rf + Rj.
Sl. 5.11. Ekvivalentna ema kalema (a), redna ekvivalentna ema (b)
i odgovarajui fazorski dijagram (c).
Iz ekvivalentnosti ema sa sl. 5.11a i sl. 5.11b dobijaju se sledei izrazi za ekvivalentnu
otpornost Re i ekvivalentnu induktivnost Le:
1
Re = R (5.3)
(1 LC ) + (C R )
2
o
2
o
2
Co R 2
1 LC o
2
Le = L L . (5.4)
( 2 2
)
1 LC o + (C o R )
2
89
Iz (5.4) je evidentno da se induktivnost smanjuje sa poveanjem uestanosti i da je Le
uvek manje od L. Moduo impedanse kalema, na osnovu sl. 5.11a, iznosi:
R 2 + (L )
2
Z = . (5.5)
(1 LC ) + (C R )
2
o
2
o
2
a. b.
Sl. 5.12 Frekventna zavisnost modula impedanse kalemova razliitih induktivnosti.
Dakle, ako su gubici relativno mali, moduo umpedanse e se sa uestanou linearno po-
veavati samo do neke uestanosti, a zatim, kada se uticaj parazitne kapacitivnosti Co vie ne
moe da zanemari, poveanje modula impendanse je sa znatno veim nagibom (sl. 5.12). Para-
zitna kapacitivnost uslovljava nastanak rezonanse na nekoj uestanosti, i tada moduo impedanse
dobija maksimalnu vrednost (sl. 5.12); iznad te uestanosti kalem gubi induktivne osobine, odno-
sno tada dominantnu ulogu preuzima parazitna kapacitivnost, i kalem se ponaa kao konden-
zator. Ve je napomenuto da parazitna kapacitivnost zavisi od naina motanja kalema, to ima
posledice na vrednost modula impedanse, a to se najbolje vidi na sl. 5.12b.
5.1.4. Faktor dobrote kalemova

Faktor dobrote kalemova (Q-faktor) definisan je izrazom:
Le 1
Q= = , (5.6)
Re tg
gde je ugao gubitaka izmeu pada napona na induktivnoj otpornosti VLe = LeI i napona na
kalemu, sl. 5.11c.
Kako i ekvivalentna otpornost kalema Re i ekvivalentna induktivnost Le zavise od ue-
stanosti, to se Q-faktor nee u celom frekventnom opsegu linearno poveavati sa uestanou,
to na prvi pogled proizilazi iz jedn. (5.6), ve e, naprotiv, pri visokim uestanostima opadati sa
poveanjem frekvencije. Naime, pri viim uestanostima ekvivalentna otpornost Re, jedn. (5.3),
90
bre raste sa uestanou od induktivne otpornosti Le (Le po (5.4)), te Q-faktor dostie mak-
simum i sa daljim poveanjem frekvencije isti opada, sl. 5.13. Radni frekventni opseg kalema se
bira tako da Q-faktor ima maksimalnu vrednost u sredini tog opsega.
Sl. 5.13. Merene vrednosti Q-faktora kalemova razliitih induktivnosti.
Treba napomenuti da kod kalemova se jezgrom otpornost Re sadri i gubitke u jezgru Rj

(usled histerezisnih, remanentnih i gubitaka usled vihornih struja u magnentom materijalu). Sto-
ga kod kalemova sa jezgrom nije Qj = rQ0 (Qo faktor dobrote kalema bez jezgra); na primer,
usled gubitaka, kod kalemova sa otvorenim jezgrom je
Q Qo i , (5.7)
gde je i poetna relativna magnetna permeabilnost na krivoj magneenja (u taki P1 na sl. 5.14):
1 B
i = lim . (5.8)
o H 0 H
Sl. 5.14. Kriva magneenja magnetnih materijala za jezgra kalemova.
91
Kod kalema sa jezgrom zatvorenog tipa, Q-faktor se moe poveati 23 puta ubaciva-
njem nemagnetnog procepa meugvoa. To je zbog toga to se uvoenjem meugvoa
smanjuje magnetna permeabilnost, a to znai da su i manji gubici. Naime, ako su e i tge
magnetna permeabilnost jezgra sa meugvoem i tangens ugla gubitaka kalema sa tim jezgrom,
a tg tangens ugla gubitaka kalema sa jezgrom bez procepa, vai:
tg e tg
, (5.9)
e i
tako da je Q-faktor kalema sa jezgrom i meugvoem (Qe):
1 1 i
Qe = =Q i . (5.10)
tg e tg e e
S obzirom da je e < i, iz (5.10) se vidi da se Q-faktor poveava uvoenjem meu-

gvoa.
5.2. KALEMOVI BEZ JEZGRA

U ovom delu bie dati izrazi kojima se mogu izraunati induktivnosti pojedinih kalemova
bez jezgra i bez koraka, u zavisnosti od njihove veliine i oblika.
Induktivnost dugakih jednoslojnih cilindrinih kalemova. Pod dugakim kalemom

podrazumeva se kalem kod kojeg je duina l najmanje 10 puta vea od njegovog prenika do (l i
do prema sl. 5.6). Induktivnost takvog kalema (l 10 do) sa dosta dobrom tanou moe se
izraunati prema obrascu:
d o2 N 2
L = 2 10 3 (H), (5.11)
l
u kojem su do i l u cm, a N je broj zavojaka.
Induktivnost kratkih jednoslojnih cilindrinih kalemova. Ova induktivnost se sa do-

sta dobrom tanou moe aproksimirati izrazom, u kojem su do i l u cm:
do N 2
L = 2,26 10 2 (H). (5.12)
l
1 + 2,25
do
Induktivnost kratkih vieslojnih cilindrinih kalemova. Za izraunavanje induktivno-

sti kratkih vieslojnih cilindrinih kalemova, koji se najee motaju unakrsno ili nasumino,
koristi se Vilerov (Wheeler) obrazac (sve dimenzije su, prema sl. 5.8, ucm):
d o2 N 2
L = 78,7 10 3 (H). (5.13)
3d o + 9l + 10h
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Induktivnost ploastih kalemova. Ploasti kalem je onaj kod kojeg je duina kalema l
veoma mala i manja od visine namotaja h i srednjeg prenika do; kod njih se, sa dimenzijama u
cm, induktivnost rauna po:
d o2 N 2
L = 2 10 3 (H). (5.14)
h
5.3. KALEMOVI SA JEZGROM
Sl. 5.15. Razliite vrste kalemova sa jezgrom.
Sl. 5.16. Razliite vrste feritnih jezgara za kalemove.
93
Za poveanje induktivnosti kalemova koriste se magnetna jezgra. Iako jezgra za kalemo-
ve mogu biti i od magnetodielektrika (metalnog magnetnog praha), znatno ee se prave od fe-
rita, sl. 5.16. To je stoga to pri vrlo visokim uestanostima jezgra od magnetodielektrika imaju
prevelike gubitke usled vihornih struja, te je u tom sluaju neophodno koristiti feritna jezgra, kod
kojih su ti gubici znatno manji.
Feriti su jedinjenja oksida gvoa (Fe2O3) i dvovalentnih oksida metala (ZnO, MnO,
NiO, BaO, CuO i dr.) koji poseduju ferimagnetne osobine; to su tkzv. meki feriti. Dobijaju se
sinterovanjem u inertnoj atmosferi i strogo kontrolisanim temperaturnim ciklusima, a dobijena
jezgra su vrlo tvrda i otporna na vodu, slino kao keramike sinterovane mase.
S obzirom da se jezgra razlikuju po konstrukciji, to se ona mogu podeliti na otvorena,
poluzatvorena i zatvorena. Najmanje iskorienje magnetnih osobina je kod jezgara otvorenog
tipa u obliku tapia ili cevica (sl. 5.17), s obzirom da kod njih magnetni fluks dobrim delom
protie kroz vazduh.
Sl. 5.17. Jezgra otvorenog tipa i kalemovi sa takvim jezgrima.
Sl. 5.18. Prividna permeabilnost app u funkciji odnosa duine l i prenika d

feritnih tapia za razliite vrednosti poetne permeabilnosti i
Induktivnost kalemova sa otvorenim jezgrom se izraunava na osnovu:
L = app Lo , (5.15)
94
pri emu je Lo induktivnost kalema bez jezgra, a app prividna permeabilnost. Prividna permea-
bilnost zavisi od oblika jezgra i kalema, poloaja kalema na jezgru, itd. Na sl. 5.18 je prikazana
zavisnost prividne permeabilnosti od odnosa duine l i prenika d feritnih tapia za razliite
vrednosti poetne permeabilnosti i (definicija poetne permeabilnosti je data sa (5.8)).
Najbolje iskorienje magnetnih osobina pruaju torusna jezgra, sl. 5.19. Kalemovi sa
torusnim jezgrima praktino nemaju rasipanje magnetnog fluksa i imaju relativno velike vred-
nosti Q-faktora i magnetne permeabilnosti koja se obeleava sa tor (tor je torusna permeabilnost
snima se na torusnom jezgru na poetku krive magneenja). Ovi kalemovi se ne moraju da
oklopljavaju. Jezgra su kompaktna, tako da se induktivnost kalemova sa torusnim jezgrima ne
moe da menja.
Sl. 5.19. Torusno jezgro i torusni kalemovi.
Ako su L0, Q0 i R0 induktivnost, Q-faktor i gubici torusnog kalema bez jezgra, a Rj gubici
u jezgru, onda je induktivnost i Q-faktor torusnog kalema sa jezgrom, respektivno:
L j ( tor ) = tor L0 (5.16)

i
tor Q0
Q j ( tor ) = . (5.17)
Rj
1+
R0
I kod kalermova sa jezgrima zatvorenog tipa (sl. 5.20) se osigurava veoma dobro is-
korienje magnetnih osobina materijala. To su tzv. lonasta jezgra, RM i PM jezgra (sl. 5.21).
Kod njih je magnetno kolo zatvoreno, usled ega kalemovi imaju vei Q-faktor, manju zavisnost
parametara od uestanosti i spoljanjeg magnetnog polja, te mogu raditi na viim uestanostima.
Induktivnost kalema sa jezgrom zatvorenog tipa moe da se izrauna na osnovu sledeeg
izraza:
Se 2
L = oe N , (5.18)
le
u kojem su e, le i Se efektivna magnetna permeabilnost, efektivna duina magnetnih linija sila i

efektivna povrina magnetnog jezgra, respektivno, a N broj zavojaka.
95
Sl. 5.20. Kalemovi sa zatvorenim feritnim jezgrima za povrinsku montau (SMD).
Kalem sa lonastim jezgrom i njegovi sastavni delovi
Kalem sa RM jezgrom i njegovi sastavni delovi
Kalem sa PM jezgrom i njegovi sastavni delovi
Sastavni delovi dva razliita kalema sa E jezgrima

Sl. 5.21. Zatvorena feritna jezgra i odgovarajui kalemovi sa njima.
96
Kao to se iz (5.18) vidi, induktivnost kalemova sa jezgrom direktno zavisi od vrednosti
efektivne magnetne permeabilnosti e, koja umnogome zavisi od oblika i dimenzija jezgra, vrste
materijala, a pogotovo od vrednosti vazdunog procepa u magnetnom materijalu. Analitiko
odreivanje vrednosti efektivne permeabilnosti i induktivnosti kalema sa vazdunim procepom
ponekad je veoma zametno. Stoga se definie faktor induktivnosti AL, koji se eksperimentalno
odreuje. Naime, faktor induktivnosti AL praktino predstavlja induktivnost kalema sa jezgrom
koji ima samo jedan zavojak. Induktivnost kalema sa N zavojaka je onda:
L = AL N 2 . (5.19)
Faktor induktivnosti (ili, prosto, AL vrednost) predstavlja konstantu jezgra koju daje
proizvoa za svaki tip jezgra i za odgovarajui materijal i izraava se u nH. Iako je AL u nH,
uobiajeno je da se ta vrednost daje samo brojano, npr. AL = 1340 (to znai da AL = 1340 nH).
Uporeujui (5.18) i (5.19), sledi da je efektivna magnetna permeabilnost:
le
e = AL . (5.20)
o Se
Iz (5.20) je evidentno da kako AL vrednost zavisi od vazdunog procepa, tako e zavisiti i

efektivna magnetna permeabilnost e, te i induktivnost kalema. Veza izmeu efektivne magnetne
permeabilnosti e, poetne permeabilnosti i (definisane sa (5.8)), efektivne duine magnetnih
linija le i debljine vazdunog procepa dobija se primenom zakona o cirkulaciji magnetnog
polja, odakle, ali samo za male vrednosti , sledi:
1 1
+ . (5.21)
e i le
Smenjujui (5.21) u (5.18) dobija se za induktivnost kalema sa vazdunim procepom

(meugvoem):
Se
L = oi N 2 . (5.22)
le + i
97
6. TRANSFORMATORI I PRIGUNICE
Transformatori se sastoje od najmanje dva induktivno spregnuta kalema, primara i se-
kundara. U sekundaru se indukuje napon koji moe biti jednak, manji ili vei od napona dove-
denog na primarni namotaj. Za bolji prenos snage, sa to manjim gubicima, potrebno je da je
induktivna sprega izmeu namotaja to jaa; zbog toga se kod transformatora koriste magnetna
jezgra.
Na sl. 6.1 su prikazani simboli kojima se oznaavaju transformatori u emama elektron-
skih kola, a na sl. 6.2 spoljanji izgled nekih transformatora.
Sl. 6.1. Simboli kojima se oznaavaju transformatori u emama elektronskih kola.
Sl. 6.2. Spoljanji izgled nekih transformatora.
6.1. KONSTRUKCIJA I PRORAUN
6.1.1. Materijali za magnetna jezgra

Kada se jezgro od magnetnog materijala nalazi u naizmeninom magnetnom polju, to se
deo energije tog polja izgubi. Ti gubici se pri veim magnetnim indukcijama B sastoje od gubi-
taka usled vihornih struja i gubitaka usled histerezisa. Histerezisni gubici su srazmerni povrini
histerezisnog ciklusa i zbog toga su oni, kao i zagrevanje jezgra, utoliko vei ukoliko je vea
povrina histerezisne petlje. Zbog toga se nastoji da materijali koji se upotrebljavaju za magnetna
jezgra transformatora (i prigunica) imaju to je mogue uu histerezisnu petlju. Ova petlja je
najvea kada se materijal magnetie do zasienja; ako se, pak, sa magneenjem prestane kod
manjih indukcija, dobija se sve manja i ua petlja, te i manji gubici.
98
Gubici usled vihornih struja zavise od specifine otpornosti materijala jezgra i od uesta-
nosti magnetnog polja. Zato se, za smanjenje ovih gubitaka, za jezgra klasinih transformatora
koriste limovi (ili trake) koji moraju biti meusobno izolovani, a s obzirom da se sa kvadratom
uestanosti poveavaju gubici usled vihornih struja, to se za jezgra transformatora koji rade na
viim uestanostima koriste tanji limovi. Upravo iz tog razloga se, na visokim uestanostima, a
posebno pri visokofrekventnim impulsnim signalima, umesto limova za transformatore koriste
feritna jezgra.
Od limova se koriste silicijumom legirani gvozdeni lim (Fe-Si) i niklom legirani gvoz-
deni lim (Fe-Ni). Silicijumom legirani gvozdeni lim iskljuivo se koristi pri mrenoj uestanosti
(50Hz ili 60Hz), a ponekad i za transformatore za 400Hz; niklom legirani gvozdeni lim je naao
primenu u podruju audio frekvencija.
1. Vrue valjani silicijumom legirani gvozdeni lim. Silicijum se dodaje gvou da bi se
poveala njegova omska otpornost, odnosno da bi se smanjili gubici, s obzirom da se oni sma-
njuju sa poveavanjem procenta silicijuma; meutim, istovremeno se smanjuje vrednost mag-
netne indukcije u zasienju i poveava krtost materijala. Kako je, s druge strane, magnetna in-
dukcija merilo za optereenost namotaja i jainu struje u praznom hodu transformatora (vee
vrednosti indukcije omoguavaju manji broj zavojaka i vee optereenje transformatora i pri-
gunica), to se silicijum ne moe dodavati u veim koliinama (najvie do 4%), tako da se dobiju
indukcije u zasienju Bm izmeu 1 T i 1,2 T. Pri proraunu transformatora i prigunica sa vrue
valjanim silicijumom legiranim gvozdenim limovima uzima se Bm = 1,2 T.
2. Hladno valjani silicijumom legirani gvozdeni lim. Ovi limovi, u poreenju sa vrue
valjanim Fe-Si limovima, ali samo ako je smer indukcije u isrom smeru sa smerom valjanja lima,
maju sledee osnovne prednosti: manje gubitke, veu vrednost magnetne indukcije i veu mag-
netnu propustljivost; meutim, ako je indukcija sa smerom normalnim na smer valjanja, gubici
mogu biti i do tri puta vei. Stoga se prednosti orijentisanog lima mogu iskoristiti jedino kod
transformatora kod kojih je indukcija u magnetnom jezgru uvek u smeru valjanja lima (trake).
Taj neophodan uslov se obezbeuje kada se od traka oforme torusna i prereza C-jezgra. Zbog
toga transformatori sa ovakvim jezgrima imaju znatno manje gubitke i veu vrednost magnetne
indukcije (do Bm = 1,85 T), a samim tim i manje dimenzije i manju teinu od odgovarajuih
transformatora od vrue valjanih limova.
3. Niklom legirani gvozdeni lim. Iako se kod silicijumom legiranih gvozdenih limova
gubici pri uestanostima viim od 50 Hz donekle mogu smanjiti izborom tankih limova, ipak su
ti gubici nedopustivo veliki, tako da su takvi limovi praktino neupotrebljivi u oblasti viih ue-
stanosti. Pored toga, pomenuti limovi imaju relativno male vrednosti i poetne i maksimalne
magnetne permeabilnosti, koje su nedovoljne za precizne merne transformatore ili transforma-
tore koji e raditi u podruju audio uestanosti (20Hz 20kHz). Zbog toga se, u sluajevima
kada su dozvoljeni samo mali gubici i kada se trai velika relativna magnetna propustljivost,
upotrebljavaju niklom legirani gvozdeni limovi.
4. Feritna jezgra. Pored namene za transformisanje visokofrekventnih sinusoidalnih signa-
la, feritna jezgra se najvie koriste za transformatore u visokofrekventnim prekidakim izvorima
napajanja (SMPS Switched-Mode Power Supply), koji rade na uestanostima viim od 15 kHz,
a ponekad i iznad 100 kHz. Naime, za napajanje elektronskih ureaja, kao to su TV prijemnici,
raunari, avionski ureaji, itd., gde svaki milivat utede znai mnogo u ukupnom energetskom
bilansu, i svuda tamo gde se tolerie malo vei napon brujanja (oko 1% od ulaznog napona),
SMPS sa transformatorima sa feritnim jezgrima imaju nekoliko prednosti u odnosu na klasine
izvore napajanja, a to su prvenstveno vrlo visok stepen iskorienja i to nisu vie potrebni
klasini mreni transformatori, tako da se postie uteda u teini i zapremini ureaja. Obino se
pri proraunu za magnentnu indukciju u zasienju uzima Bm = (0,2 0,3) T.
99
6.1.2. Oblici magnetnih jezgara
Sl. 6.3. Transformatori sa razliitim oblicima jezgara.
Jezgra od Fe-Si i Fe-Ni se mogu dobiti od profilisanih odvojenih (izolovanih) ploica

standardizovanih oblika i dimenzija (npr. EI i UI profila), koje se slau jedna na drugu, ili od
traka, koje se koncentrino motaju i zatim seku (trakasta i prerezana trakasta jezgra npr. C-
jezgra).
1. Jezgra od limova EI profila. Kod ovih jezgara (sl. 6.4 i sl. 6.5) namotani kalem, sa
kalemskim telima kao na sl. 6.4, postavlja se na srednji stub jezgra. Primena jednog kalema
pojednostavljuje konstrukciju i omoguuje maksimalnu ispunu bakrom raspoloivog prostora
(prozora).
Sl. 6.4. Kalemska tela i odgovarajui transformatori sa jezgrima EI profila.
2. Jezgra od limova UI profila. Kao i kod jezgara od limova EI profila, i kod jezgara UI
profila se u ve namotane kalemove umeu listovi magnetnih jezgara, sl. 6.6. Meutim, u ovom
sluaju se koriste (najee) dva odvojena kalema, ime se poveava povrina preko koje se zrai
toplota i poboljava toplotni reim namotaja, te se transformatori sa jezgrima od limova UI
profila obino koriste za vee snage.
100
Sl. 6.5. Limovi EI profila (sa oznakama koje se koriste pri
proraunu transformatora) i izgled transformatora.
Sl. 6.6. Limovi UI profila (sa oznakama koje se koriste pri

3. Trakasta torusna jezgra. Da bi se iskoristile dobre osobine hladno valjanog silici-

jumom legiranog lima, od traka tog lima se namotavaju torusna, kompaktna, jezgra. Najvie se
koriste za mrene transformatore (sl. 6.7) sa i bez kalemskog tela, a u poreenju sa odgovara-
juim transformatorima sa jezgrima EI profila (za istu snagu) su oko 50% manje mase.
Sl. 6.7. Torusni mreni transformatori.
4. Prerezana trakasta jezgra (C-jezgra). Od traka orijentisanog lima izrauju se goto-

va, kompaktna jezgra, sl. 6.8, tako da pri gradnji transformatora nema dugotrajnog slaganja
limova jezgra. Naime, montaa takvih jezgara je vrlo jednostavna: dve polovine jezgra umetnu
se sa jedne i druge strane u kalemsko telo, a onda se stisnu (stegnu) trakom, sl. 6.9.
101
Sl. 6.8. Prerezana trakasta C-jezgra (sa oznakama koje se koriste pri
Sl. 6.9. Mreni transformatori sa C-jezgrima.
5. Feritna jezgra. Od feritnih jezgara za transformatore u visokofrekventnim prekida-

kim izvorima napajanja koriste se jezgra prikazana na sl. 5.21 (lonasta, PM, RM) i na sl. 5.19
(torusna jezgra).
6.1.3. Osnovne relacije kod transformatora

1. Odnos transformacije n. Pod uticajem magnetnog fluksa, prouzrokovanog naponom
U1 V1, u primarnom i sekundarnom namotaju se, respektivno, indukuju elektromotorne sile e1 i
e2 (sl. 6.10):
e1 = 4,44 10 4 fN 1 Bm S e (6.1)
e2 = 4,44 10 4 fN 2 Bm S e , (6.2)
pri emu su: f uestanost primarnog napona u Hz; N1 i N2 broj zavojaka primarnog i sekun-
darnog sekundarnog namotaja, respektivno; magnetna indukcija u zasienju u T; Se efektivni
presek jezgra (sl. 6.11) u cm2.
Naponi na krajevima transformatora se razlikuju od indukovanih elektromotornih sila
zbog pada napona na namotajima (U1 > e1 i U2 < e2). Ako se, u prvoj aproksimaciji, ovi padovi
napona zanemare, moe se smatrati da je e1 U1 i e2 U2, tako da iz (4.1) i (4.2) sledi odnos
transformacije napona n:
102
a.
b.
Sl. 6.10. Uz indukovanje elektromotornih sila u transformatoru:
a sekundar otvoren (u praznom hodu); b sekudar opereen impedansom Z.
Sl. 6.11. Uz definiciju efektivne povrine magnetnog jezgra.
U2 N2
n = . (6.3)
U 1 N1
Kada se na sekundarni namotaj prikljui potroa (sl. 6.11b), to e kroz njega proticati
struja I2, koja ima tendenciju da promeni prvobitni magnetni fluks. Na taj nain bi se poremetila
naponska ravnotea u primarnom namotaju; meutim, to nije sluaj, s obzirom da primarni na-
motaj povue dodatnu struju iz izvora pobude, koja u svakom trenutku dri magnetnu ravno-
teu struji u sekundaru, tako da prvobitni magnetni fluks ostaje nepromenjen. Ovo je ispunjeno
samo kada je I1N1 = I2N2, odakle sledi:
I 2 N1 1
= = . (6.4)
I1 N 2 n
Da li e naponi na primarnom i sekundarnom namotaju biti u fazi ili protivfazi zavisi od

toga kako su primar i sekundar motani. Naime, kada su i primarni i sekundarni namotaj motani u
istom smeru, naponi U1 i U2 e biti u fazi i, ako se to eli posebno da naglasi, na oznaci za
103
transformator, pored oznaka za primar i sekundar, stavljaju se dve take sa iste strane (sl. 6.12a);
meutim, kada je sekundarni namotaj motan suprotno od primarnog, naponi U1 i U2 e biti u
protivfazi i to se naznaava takama sa razliitih strana primara i sekundara, sl. 6.11b.
a. b.
Sl. 6.12. Naponi U1 i U2 u fazi (a) i protivfazi (b).
2. Gubici u transformatoru. U transformatorima gubici nastaju u namotajima (gubici u

bakru) i u magnetnom jezgru (gubici u gvou usled vihornih struja i histerezisa).
Gubici u bakru PCu su posledica omske otpornosti namotaja primara R1 i sekundara R2,
tako da je (za transformator koji ima n sekundarnih namotaja):
n
PCu = R1 I 12 + Ri 2 I i22 , (6.5)
i =1
pri emu su I1 i Ii2 struje primarnog i i-tog sekundarnog namotaja.

Kada je re o gvozdenim jezgrima, ukupni gubici u jezgru PFe (gubici u gvou) za
indukcije Bm > 0,7 T mogu se predstaviti izrazom:
PFe = ABm2 m Fe , (6.6)
u kojem su A konstanta koja zavisi od vrste i debljine lima, a mFe masa magnetnog jezgra.
3. Koeficijent korisnog dejstva. Koeficijent korisnog dejstva transformatora je definisan

odnosom izlazne Pi(=P2) i ulazne Pu snage:
Pi P2
= = 100 (%). (6.7)
Pu P2 + PFe + PCu
Vrednost koeficijenta korisnog dejstva kod transformatora koji se koriste u elektronici je

relativno velik, i iznosi od = 85% do = 95%.
6.2. MRENI TRANSFORMATORI

Mreni transformatori se u najveem broju sluajeva koriste za obezbeenje potrebnih
napona u ispravljakim stepenima elektronskih ureaja. Za njihov proraun potrebni su sledei
podaci: vrednost ulaznog napona U1, uestanost mrenog napona f i vrednosti napona i struja
sekundarnih namotaja U2 i I2 (odnosno izlazna snaga transformatora P2). Odmah treba naglasiti
da su jezgra mrenih transformatora bez vazdunog procepa.
Za mrene transformatore primenljive u elektronici skoro iskljuivo se koriste standardizo-
vani EI (ree UI) limovi ili trakasta prerezana jezgra (C-jezgra). Kako je broj zavojaka i primar-
nog i sekundarnog namotaja, prema (4.1) i (4.2), obrnuto proporcionalan vrednosti magnetne
104
indukcije u zasienju Bm, tj. N 1/Bm, to e za istu nazivnu snagu broj zavojaka svih namotaja, a
samim tim i masa transformatora, biti manji ukoliko je vrednost indukcije Bm vea. S obzirom da
hladno valjani silicijumom legirani gvozdeni limovi (tj. trake koje se od njih prave, a potom
prerezana C-jezgra) imaju indukciju Bm reda 1,8 T, to e mreni transformatori od ovih limova
(traka) imati manju masu od odgovarajuih transformatora sa vrue valjanim silicijumom legira-
nim limovima, kod kojih je Bm = 1,2 T.
Ovde e, ukratko, biti opisan postupak prorauna mrenog transformatora sa EI jezgri-
ma2, koristei oznaavanje sa sl. 6.5.
6.2.1. Dimenzionisanje jezgra
Izmeu standardizovanih dimenzija EI limova (videti fusnotu br. 3) treba izabrati najpo-
desniji profil sa gledita potronje, magnetnog materijala i bakra (ice za namotavanje). U tu
svrhu, osnovni koraci pri proraunu mrenih transformatora su:
1. Odreivanje efektivnog preseka jezgra: Veliina efektivnog preseka jezgra se pribli-

no moe izraunati iz izraza:
S e P2 (cm2), (6.8)
u kojem je P2 snaga sekundara (izlazna snaga) u W (mnogo ee se izraava u VA).
2. Izbor profila (veliine jezgra) i odreivanje debljine limenog paketa. Za mrene

transformatore, sa gledita najmanje upotrebe ice za namotavanje, a istovremeno i najmanje
otpornosti namotaja, najpodesnije bi bilo da je povrina poprenog preseka jezgra Se kvadratnog
oblika, odakle sledi da treba izabrati lim irine stuba:
max = Se . (6.9)
Kako je od standardizovanih veliina limova mogue izabrati samo ogranien broj onih
sa kvadratnim presekom, to se mora pribei i pravougaonim presecima jezgra. Minimalna irina
stuba lima odreena je uslovom da je visina limenog paketa h 1,5, odakle je:
min = 0,82 S e = 0,82 max . (6.10)
Dakle, bira se veliina lima kod kojeg irina stuba odgovara uslovu:
min < < max . (6.11)
Znajui efektivni presek jezgra Se, irinu stuba i debljinu lima , potreban broj limova
je:
Se
nL = . (6.12)

2
Prora~un mre`nog transformatora sa C-jezgrima, kao i svi podaci za EI jezgra, mogu se na}i u knjizi: Stojan Ri-
sti}, "RLC komponente", Prosveta, Ni{, 2005
105
4.2.2. Namotaji
Namotaji se uvek motaju na kalemsko telo (sem kod torusnih transformatora). Kalemska
tela se izrauju na vie naina i od razliitih izolacionih materijala, to zavisi od toga da li je re
o individualnoj ili serijskoj proizvodnji transformatora. Najvie se koriste kalemska tela od pre-
pana i vetakih smola (bakelita), sa takvim dimenzijama da se u njih normalno mogu da umeu
limovi.
1. Odreivanje broja zavojaka. Pri odreivanju broja zavojaka namotaja transformatora
polazi se od jedn. (6.1), uz pretpostavku da se pad napona na primaru moe da zanemari i da e
se njegov uticaj uzeti sa sekundarne strane, tako da je e1 U1, odakle sledi (jedinice su kao u
(6.1)):
U1
N1 = 10 4 . (6.13)
4,44 fS e Bm
Na slian nain, tj. na osnovu (6.2) mogao bi da se odredi i broj zavojaka sekundarnog
namotaja kod neoptereenih transformatora. Meutim, pri optereenju se mora uzeti u obzir
omski i induktivni pad napona u primarnom i sekundarnom namotaju, zbog ega broj zavojaka u
sekundaru treba poveati; to poveanje je izraeno preko koeficijenta sekundarnih gubitaka 2,
sl. 6.13. Stoga se broj zavojaka sekundarnog namotaja N2 ne rauna iz odnosa transformacije n
U2/U1 N2/N1, ve iz izraza:
U2
N 2 = 2 N1 . (6.14)
U1
Na isti nain se izraunava broj zavojaka i kada transformator ima vie sekundarnih na-
motaja, s tim da se koeficijent gubitaka 2 odreuje u odnosu na ukupno optereenje, tj. pri isto-
vremenom optereenju svih namotaja.
Sl. 6.13. Koeficijent sekundarnih gubitaka 2 u funkciji

snage za transformatore sa jezgrima EI profila.
2. Odreivanje prenika ica. Prenici ica za namotaje izraunavaju se na osnovu

vrednosti struja primara i sekundara. Struje u sekundarnim namotajima su unapred zadate, dok se
struja primara odreuje iz:
106
P2
I1 = , (6.15)
U 1
pri emu se za koeficijent korisnog dejstva uzima pretpostavljena vrednost (npr. = 0,9).
Dakle, znajui struje I1 i I2 i koristei
d 2
I = S J = J, (6.16)
4
gde je S popreni presek ice, a J gustina struje, dobija se za prenik ice d:
4I
d = . (6.17)
J
Iz poslednjeg izraza sledi da prenik ice namotaja zavisi od gustine struje. Za mrene
transformatore snaga do 150 W sa EI jezgrima esto se uzima da je J = 2,55 A/mm2, tako da je iz
poslednjeg izraza, ako je struja I u amperima,
d = 0,5I (mm). (6.18)
6.3. PRIGUNICE
Prigunice se koriste u sluajevima kada je potrebno imati to vee induktivno opteree-
nje, a to znai da one treba da imaju to veu induktivnost (da bi L bilo to vee). Prigunice sa
jezgrima od silicijumom legiranih gvozdenih limova za 50 Hz koriste ista jezgra kao mreni
transformatori (na primer, EI jezgra kao na sl. 6.14) i proraunavaju se na isti nain kao i mreni
transformatori. Kako one najee imaju veliki broj zavojaka, a napon na njima je relativno mali,
to je i indukcija u magnetnim jezgrima mala, reda Bm = (0,40,5) T. Zbog toga su gubici u
prigunicama mali, te se pri proraunu o njima ne mora mnogo voditi rauna.
Sl. 6.14. EI jezgra za prigunice (ista kao i za mrene transformatore).
107
7. OSNOVNE OSOBINE POLUPROVODNIKA
Pre izlaganja o poluprovodnikim komponentama ovde e biti izloene neke osnovne
karakteristike poluprovodnika, i to u prvom redu silicijuma. To i jeste osnovni cilj ovog poglav-
lja, koje obuhvata izlaganja o strukturi poluprovodnika, o mehanizmu provoenja struje i efek-
tima dopiranja poluprovodnika.
7.1. ELEMENTARNI POLUPROVODNICI I

POLUPROVODNIKA JEDINJENJA
U kolonama na levoj strani tablice periodnog sistema elemenata nalaze se metali. Atomi
metala mogu lako izgubiti jedan ili dva elektrona i postati pozitivni joni. Oni su, kao to je
poznato, dobri provodnici elektrine struje, s obzirom da je kod njih veza izmeu atoma i
elektrona u spoljanjoj orbiti slaba, tako da se elektroni mogu relativno lako osloboditi i postati
slobodni. Elementi u kolonama na desnoj strani tablice periodnog sistema imaju elektrone u
spoljanjim opnama vrsto vezane; oni su, prema tome, izolatori. U srednjim kolonama tablice
nalaze se elementi kod kojih je provodnost znatno manja nego kod dobrih provodnika, a znatno
vea nego kod izolatora. Oni ine klasu poluprovodnika. Tu spadaju 12 elementarnih polupro-
vodnika: bor (B), ug1enik (C), silicijum (Si), fosfor (P), sumpor (S), germanijum (Ge), arsen
(As), selen (Se), kalaj (Sn), antimon (Sb), telur (Te) i jod (J). U tabl. 7.1 prikazani su poloaji
pomenutih elemenata u periodnom Mendeljejevom sistemu. Danas se od elementarnih polupro-
vodnika skoro iskljuivo koristi silicijum, dok se drugi, kao sto su arsen, fosfor i bor upotreblja-
vaju za dopiranje silicijuma, ime se menja njegova provodnost.
Tabl. 7.1. Poloaj elementarnih poluprovodnika u periodnom sistemu elemenata

Grupa II III IV V VI VII
Perioda
II Be B C N O
III Al Si P S Cl
IV Ga Ge As Se Br
V In Sn Sb Te J Xe
VI Pb Bi Po At
I neka jedinjenja elemenata III i V grupe periodnog sistema imaju poluprovodnike oso-
bine. Zahvaljujui svojim osobinama, posebnu panju privlai galijum-arsenid (GaAs), koji se
koristi za visokofrekventne i mikrotalasne komponente (na primer kod MESFET-a). Istraivanja
poluprovodnikih jedinjenja su vrlo aktuelna, s obzirom da komponente na bazi ovih jedinjenja
mogu biti efikasni izvori, ili, pak, detektori kako infracrvenih radijacija, tako i radijacija u
vidljivom spektru. U tabl. 7.2 prikazana su poluprovodnika III-V jedinjenja koja se danas
najvie koriste, sa naznakom vrste prelaza elektrona iz valentne u provodnu zonu.
108
Tabl. 7.2. Poluprovodnika III-V jedinjenja
Elementi V grupe
Elementi III grupe Fosfor (P) Arsen (As) Antimon (Sb)
Aluminijum (Al) AlP AlAs AlSb
indirektan indirektan indirektan
Galijum (Ga) GaP GaAs GaSb
indirektan direktan direktan
Indijum (In) InP InAs InSb
direktan direktan direktan
a. Dijamantska (C, Si, Ge)
b. Sfaleritna (GaAs, GaP)

Sl. 7.1. Kristalna struktura elementarnih poluprovodnika (a) i poluprovodnikih jedinjenja (b).
Svi poluprovodnici, i elementarni i poluprovodnika jedinjenja, imaju kristalnu struk-

turu. Elementarni poluprovodnici imaju kristalnu reetku dijamantskog tipa, dok je reetka
poluprovodnikih jedinjenja modifikovana dijamantska struktura, tkzv. struktura sfalerita, sl.
7.1. Reetke dijamantskog tipa ine kovalentne veze, tj. atomi u teitu tetraedra povezani su sa
etiri atoma na vrhovima tetraedra, sl. 7.1a. Struktura sfalerita je ista kao dijamantska, ali atomi
u reetki nisu isti, sl. 7.1b. Dakle, kod reetki sa dijamantskom strukturom svaki atom je vezan sa
109
etiri oblinja atoma, tako da su ovi od njega podjednako udaljeni i meusobno se nalaze na
jednakim rastojanjima, poznatim pod nazivom tetraedralni radijus. Tetraedralni radijus se
kod dijamantske strukture izraunava na osnovu ( 3 / 8)a , pri emu je a konstanta reetke. Na
primer, kod silicijuma je a = 0,543072 nm, tako da je tetraedralni radijus 0,118 nm.
Poluprovodniki materijal od koga se proizvode komponente treba da ima pravilnu kri-
stalnu strukturu po celoj zapremini; to je, takozvani, monokristal. Meutim, monokristal nije
izotropan, s obzirom da njegove osobine zavise od pravca. To uslovljava da i karakteristike po-
luprovodnikih komponenata u znatnoj meri zavise od orijentacije povrine monokristala. Zbog
toga se kristali seku po odreenoj ravni. Naime, poloaj svake ravni kristalne reetke moe se
odrediti sa tri cela uzajamno prosta broja, ako se kao koordinatne ose izaberu pravci koje imaju
tri ivice kristalne reetke. Jedinice merenja su odseci na izabranim koordinatnim osama koje
odseca jedna od kristalografskih ravni u kristalnoj reetki. Obino se u kristalografiji koristi de-
sni koordinatni sistem, a merna jedinica na x-osi se oznaava sa a, na y-osi sa b i na z-osi sa c.
Jedinina duina za svaku osu se odreuje izborom jedinine kristalografske ravni u kristalnoj
reetki. Svaka ravan u kristalnoj reetki se smatra moguom kristalografskom ravni ako joj
pripadaju tri srazmerno postavijene take na koordinatnim osama u odnosu na koordinatni po-
etak. Ravan u kristalnoj reetki kojoj ne pripadaju srazmerno postavljene take na koordinatnim
osama moe se premestiti translacijom u poloaj da joj pripadaju srazmerno postavljene take na
koordinatnim osama. Shodno tome, odnos odseaka OA, OB i OC koje ravan ABC odseca na
koordinatnim osama x, y i z pravouglog koordinatnog sistema, moe se napisati u sledeem obli-
ku:
OA:OB:OC = ma:nb:pc,
gde su a, b i c odseci jedininih duina na odgovarajuim koordinatnim osama, a m, n i p celi

brojevi. Ovako izabrana ravan predstavlja jedininu ravan.
(020) (110) (111)

Sl. 7.2. Prikaz orijentacije tri karakteristine ravni sa Milerovim indeksima (020), (110) i (111).
Za oznaavanje orijentacije ravni kristala koriste se Milerovi indeksi. Naime, prema

osnovnoj eliji povuku se ortogonalne koordinatne ose x, y i z i proizvoljne ravni koje seku ove
ose u takama OA = x1, OB = y1 i OC = z1. Kada se reciprone vrednosti ovih koordinata pom-
noe najmanjim zajednikim imeniocem, dobijaju se Milerovi indeksi. Na primer, ako ravan see
koordinatne ose u takama x1 = 3, y1 = 2 i z1= 1, reciprone vrednosti su: 1/x1 = 1/3, 1/ y1 = 1/2 i
1/ z1 =1/1. Najmanji zajedniki imenilac je 6, tako da su Milerovi indeksi: (1/3)6 = 2, (1/2)6 = 3
i (1/1)6 = 6. Milerovi indeksi se belee u srednjoj ili maloj zagradi, te je orijentacija kristala za
pomenuti primer (236). Na sl. 7.2 prikazane su tri karakteristine ravni ije su orijentacije (020),
(110) i (111).
110
7.2. SLOBODNI ELEKTRONI I UPLJINE U
POLUPROVODNICIMA
Atomski broj silicijuma je 14 i njegova 14 elektrona su rasporeena po orbitama oko jez-
gra. Prve dve orbite su popunjene, jer sadre dva, odnosno osam elektrona, respektivno, dok je
poslednja, trea orbita nepopunjena i sadri etiri elektrona, sl. 7.3a. Elektroni u unutranjim,
popunjenim orbitama, nazivaju se stabilnim elektronima, s obzirom da se nalaze na niim ener-
getskim stanjima od elektrona u spoljanjoj, nepopunjenoj orbiti. Oni ne uestvuju u mehanizmu
provoenja struje u poluprovodnicima, kao to je, uostalom, to sluaj i kod metala, te se nee
pominjati u daljim izlaganjima.
a.
b.
Sl. 7.3. ematski prikaz atoma silicijuma u prostoru (a) i u ravni (b).
Zbog toga se silicijumov atom moe ematski da predstavi jezgrom sa pozitivnim naelek-
trisanjem od etiri elektronske jedinice (+4) koje je okrueno sa etiri elektrona iz spoljanje or-
bite, sl. 7.3b. etiri elektrona iz spoljanje orbite, zbog toga to ulaze u hemijske veze, nazivaju
se valentnim elektronima. U savrenom kristalu silicijuma, odnosno germanijuma, koji su,
dakle, etvorovalentni, svaki od ova etiri elektrona obrazuje po jednu valentnu vezu sa po
jednim elektronom iz spoljanje orbite oblinjeg atoma.
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Prema tome, potpuno ist kristal poluprovodnika, kod koga su svi elektroni povezani
valentnim vezama, ponaao bi se kao izolator, s obzirom da kod njega nema slobodnih nosilaca
naelektrisanja. Meutim, pri normalnoj sobnoj temperaturi, usled termikih vibracija kristalne
reetke, izvesni valentni elektroni poveavaju svoju energiju do te mere da mogu da se oslobode
valentnih veza i postaju slobodni elektroni, sl. 7.4a. Oslobaanjem svakog elektrona po jedna va-
lentna veza ostala je nepopunjena. Atom, koji je izgubio elektron, postaje elektrino pozitivan sa
naelektrisanjem jednakim naelektrisanju elektrona po apsolutnom iznosu (pre gubitka valentnog
elektrona atom je bio elektrino neutralan). Na taj nain se stvara pozitivno opterereenje ija se
prava priroda moe protumaiti tek pomou kvantne fizike, ali koje se po mnogim svojstvima
ponaa kao estica sa pozitivnim naelektrisanjem jednakim naelektrisanju elektrona. Njemu se
moe pripisati odreena efektivna masa, brzina u kretanju i energija, to znai da se moe tretira-
ti kao estica. Ova estica se, zbog naina postanka, naziva upljinom. Eksperimentalnim rezul-
tatima pokazana je opravdanost ovako uproene koncepcije upljina.
a. b.
Sl. 7.4. Prikaz generacije para elektron-upljina (a) i rekombinacije elektrona sa upljinom (b).
Kretanje upljina u poluprovodniku moe se predstaviti na sledei nain. Atom, koji je

izgubio jedan elektron, tei da upotpuni pekinutu valentnu vezu. On izvlai elektron iz neke
oblinje valentne veze u kojoj je elektron na relativno viem energetskom nivou. Usled toga, po-
smatrani atom postaje elektrino neutralan, ali se upljina pojavijuje na mestu sa koga je privu-
en elektron za neutralizaciju. Drugim reima, praktino se kreu elektroni, ali izgleda kao da se
kreu prazna mesta (upljine) u suprotnom smeru od kretanja elektrona. Na sl. 7.5 prikazano je
kretanje elektrona i upljina u silicijumu kada je na njega prikljuen spoljanji nspon V.
Slobodni elektroni i upljine u kristalu poluprovodnika predstavljaju energetske nesavr-
enosti kristala i imaju ogranieno vreme ivota, jer se u kretanju kroz kristal susreu i rekom-
binuju uspostavljajui ponovo valentne veze, sl. 7.4b. Termiko raskidanje valentnih veza raste
sa temperaturom, dok je brzina ponovnog uspostavljanja valentnih veza srazmerna koncentraciji
slobodnih nosilaca naelektrisanja. Zbog toga, koncentracije slobodnih elekrona i upljina pri sva-
koj temperaturi imaju onu vrednost pri kojoj se uspostavlja ravnotea izmeu brzine raskidanja i
brzine ponovnog uspostavljanja valentnih veza. Koncentracije slobodnih elektrona (n0) i upljina
(p0) meusobno su jednake (n0 = p0). Ova koncentracija se zove koncetracija sopstvenih nosi-
laca naelektrisanja ili sopstvena koncentracija i obeleava se sa ni = pi. Na sobnoj temperaturi
(300K) sopstvena koncentracija nosilaca naelektrisanja za silicijum iznosi ni =1,131010 slobod-
nih elektrona ili upljina po cm3. Na sl. 7.6 su prikazane vrednosti sopstvenih koncentracija
nosilaca naelektrisanja germanijuma, silicijuma i galijum-arsenida u funkciji temperature.
112
Sl. 7.5. Kretanje elektrona i upljina u istom (sopstvenom) silicijumu pod
uticajem spoljanjeg napona V.
Proces raskidanja valentnih veza, kao i obrnuti proces ponovnog vezivanja slobodnih
elektrona i upljina u valentne veze, zavisi u znatnoj meri i od postojanja izvesnih strukturnih
nesavrenosti kristala (defekata). Ove nesavrenosti postoje, na primer, kod kristala kod kojih se
poneki atomi nalaze u kristalnoj reetki na mestima koja bi zauzimali kada bi kristal bio savren.
I povrinski sloj kristala moe imati slian uticaj kao i strukturne nesavrenosti, to je posliedica
nepotpunosti valentnih veza u povrinskom sloju. Prisustvo strukturnih nesavrenosti, meutim,
ne menja koncentraciju sopstvenih nosilaca naelektrisanja, jer strukturne nesavrenosti u istoj
meri potpomau razbijanje valentnih veza i njihovo ponovno uspostavljanje. Ove nesavrenosti,
dakle, samo smanjuju vreme ivota slobodnih elektrona, odnosno upljina.
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Sl. 7.6. Sopstvene koncentracije nosilaca naelektrisanja u funkciji temperature.
7.3. PRIMESNI POLUPROVODNICI

Kada elektrina svojstva poluprovodnika, a tu se pre svega misli na provodnost, zavise od
prisustva nekog stranog elementa, onda je takav poluprovodnik primesni poluprovodnik. Treba
primetiti da se atomi stranih elemenata (neistoe), koje se obino nazivaju primesama, ne mo-
gu nikada u potpunosti da odstrane. Meutim, ukoliko je njihova koncentracija vrlo mala, onda
primese ne utiu u veoj meri na elektrina svojstva poluprovodnika. Naprotiv, ako je koncen-
tracija primesnih atoma relativno velika, njihov uticaj na elektrina svojstva poluprovodnika je
dominantan unutar irokog intervala temperature.
Primese mogu biti veoma razliite. U poluprovodnikim komponentama su od preva-
shodnog znaaja one primese koje se namerno i kontrolisano, pomou odgovarajuih tehnolokih
postupaka, dodaju poluprovodniku. Koncentracije primesa kreu se obino izmeu 1014 cm-3 i
1020 cm-3. To su, redovno, primese iji su atomi petovalentni ili trovalentni. Ukoliko se dodaju
petovalentne primese, onda nastaju poluprovodnici n-tipa, a dodavanjem trovalentnih primesa se
dobijaju poluprovodnici p-tipa. Atomi primesa zauzimaju u kristalnoj reetki mesta gde bi se u
istom poluprovodniku nalazili atomi samoga poluprovodnika oni se, dakle, ukljuuju u kri-
stalnu reetku supstitucijom. Karakteristino je da pojedine primese pokazuju vei afinitet prema
114
mestima u kristalnoj reetki poluprovodnika, na kojima se kod istog kristala nalaze atomi polu-
provodnika, nego sami atomi poluprovodnika. Zbog toga e, dodavanjem primesa poluprovod-
niku u istopljenom stanju, posle ovravanja primesni atomi zameniti na pojedinim mestima
atome poluprovodnika.
7.3.1. Poluprovodnici n-tipa

Kao to je napomenuto, n-tip poluprovodnika nastaje kada se poluprovodnik dopira pe-
tovalentnim primesama, na primer fosforom (P), arsenom (As) ili antimonom (Sb). ematski
prikaz kristalne reetke poluprovodnika n-tipa dat je na sl. 7.7.
Sl. 7.7. ematski prikaz kristalne reetke poluprovodnika n-tipa.
S obzirom da je broj primesnih atoma u jedinici zapremine vrlo mali u poreenju sa

brojem atoma poluprovodnika, svaki atom primese normalno je okruen atomima poluprovod-
nika. Kako samo etiri valentna elektrona primese ulaze u valentne veze, peti valentni elektron je
samo slabo vezan za atom, te se lako moe osloboditi veze i postati slobodan elektron. Energija
potrebna za oslobaanje ovog elektrona je vrlo mala, reda 0,01 eV do 0,02 eV kod germanijuma
i 0,04 eV do 0,07 eV kod silicijuma, tako da su ve na vrlo niskim temperaturama, a posebno na
sobnoj temperaturi, svi elektroni koji potiu od atoma primesa u provodnoj zoni i slobodno se
mogu kretati kroz kristal. Petovalentne primese, dakle, daju slobodne elektrone, te se, stoga,
zovu donorske primese, ili kratko donori i njihova koncentracija se oznaava sa ND. Donorski
atomi gubitkom elektrona postaju pozitivni joni i ostaju vezani u strukturi kristalne reetke, ali
treba napomenuti da je dodavanjem donora poluprovodnik ostao elektrino neutralan.
Usled toga to se dodavanjem donorskih primesa razbijaju valentne veze, u polupro-
vodniku n-tipa postojae i odreena koncentracija upljina. Naravno, koncentracija upljina bie
znatno manja od koncentracije slobodnih elektrona. Zbog toga, osnovni nosioci naelektrisanja u
n-tipu poluprovodnika bie elektroni, iji je broj (no) veoma blizak broju donorskih primesa, tj.
no ND. Elektroni se u n-tipu poluprovodnika esto zovu veinski, a upljine manjinski no-
sioci naelektrisanja.
115
U dijagramu energetskih nivoa prisustvo donorskih primesa ima za posledicu postojanje
dodatnog energetskog nivoa unutar zabranjene zone, i to u blizini dna provodne zone. Taj nivo se
zove donorski nivo ED. To to se donorski nivo nalazi u zabranjenoj zoni u blizini provodne zone
lei u injenici da je za prebacivanje elektrona (koji potiu od donorskih atoma) u provodnu
zonu potreban vrlo mali iznos energije.
7.3.2. Poluprovodnici p-tipa

Ovaj tip poluprovodnika nastaje kada se poluprovodnik dopira trovalentnim primesama,
meu koje spadaju bor (B), aluminijum (Al), galijum (Ga) i indijum (In). Kristalna reetka koja
sadri trovalentne primese prikazana je ematski na sl. 7.8. Trovalentnoj primesi nedostaje jedan
elektron da dopuni valentnu vezu. Ona se kompletira na taj nain to je dopuni valentni elektron
iz susedne veze, ili, drugim reima, da bi se obrazovala i etvrta valentna veza, privlai se jedan
elektron iz neke oblinje veze. Tako se stvara upljina na mestu odakle je valentni elektron
privuen. Kako trovalentne primese kompletiraju valentne veze primajui elektrone iz valentne
zone, zovu se akceptorske primese, ili kratko akceptori, a njihova koncentracija obeleava se
sa NA. Akceptorski atom postaje negativan jon vrsto vezan za kristalnu reetku. Energije joni-
zacije akceptorskih primesa su vrlo male i lee u istom intervalu energija kao i za donorske
primese, tako da je broj upljina po na sobnoj tempertauri veoma blizak broju akceptorskih pri-
mesa (p0 NA). Ove upljine se mogu slobodno kretati po unutranjosti kristala na nain opisan
ranije (taka 7.2).
Sl. 7.8. ematski prikaz kristalne reetke poluprovodnika p-tipa.
Kao i u poluprovodniku n-tipa, i u poluprovodniku p-tipa postoji raskidanje valentnih

veza, tako da ovde postoji i odreena koncentracija elektrona no, iji je broj znatno manji od
broja upljina; drugim reima: no << po. Prema tome, u poluprovodniku p-tipa upljine su ve-
inski, a elektroni manjinski nosioci naelektrisanja.
116
Akceptorske primese uvode u dijagram energetskih nivoa dodatni akceptorski nivo EA,
koji lei unutar zabranjene zone i to u blizini vrha valentne zone.
7.4. ENERGETSKE ZONE

Teorija energetskih zona, koja obuhvata prouavanje promena energetskih stanja elek-
trona u atomima kristalne resetke, predstavlja veoma podesan put za analizu pojava u polupro-
vodnicima i to ne samo u kvalitativnom, ve i u kvantitativnom pogledu. Iz fizike je poznato da
se elektroni u izolovanom atomu nalaze na razliitim energetskim nivoima, koji su jednaki celim
umnocima kvanta energije. Napominje se da su ovi energetski nivoi, koji odgovaraju energija-
ma elektrona na pojedinim orbitama, meusobno razdvojeni energetskim procepima (zabranje-
nim zonama), sl. 7.9a, ime se ukazuje na injenicu da ne postoji nijedan elektron koji bi imao
energiju unutar zabranjene zone. Ako se dva atoma sa jednakim energetskim nivoima elektrona
priblie jedan drugome, doi e do cepanja svakog pojedinog energetskog nivoa u dva nova ni-
voa koji su jedan prema drugome malo pomereni, sl. 7.9b. S obzirom da se u kristalnoj reetki
veliki broj atoma (reda 1022 cm-3) nalazi u meusobnoj sprezi, svaki energetski nivo se cepa u
vei broj novih, meusobno malo pomerenih nivoa, koji obrazuju energetske zone, sl. 7.9c.
Za utvrivanje elektrinih svojstava poluprovodnika od vanog interesa je da se poznaju
energetska stanja u dva najvia energetska opsega. Kod idealnog kristala poluprovodnika najvia
energetska zona je skoro prazna, s obzirom da sadri veoma mali broj elektrona (jednak koncen-
traciji sopstvenih nosilaca naelektrisanja ni, dok je prva nia energetska zona potpuno popunjena.
Ova druga energetska zona popunjena je elektronima iz spoljanje orbite atoma poluprovodnika,
tj. valentnim elektronima. Zbog toga se ona naziva valentnom zonom, za razliku od prve zone
(najvie zone), koja predstavlja provodnu zonu, sl. 7.10.
Sl. 7.9. Energetski nivoi atoma (a), dva atoma (b) i kristala (c) silicijuma.
117
Sl. 7.10. Energetske zone du jednog pravca u istom (sopstvenom) kristalu silicijuma pri T = 0 K.
Provodna zona je od valentne zone razdvojena nizom energetskih nivoa koje elektroni ne
mogu da zauzimaju i koji se zbog toga naziva zabranjenom zonom. irina zabranjene zone Eg
kod poluprovodnika relativno je mala i na sobnoj temperaturi (300K) iznosi Eg = 0,66 eV za ger-
manijum, Eg = 1,1 eV za silicijum i Eg = 1,42 eV za galijum-arsenid. Ove vrednosti predstavljaju
najmanje iznose energije koje je potrebno dovesti elektronu u valentnoj zoni da bi mogao da
pree u provodnu zonu i uestvuje u provoenju elektrine struje kroz poluprovodnik (ovo ne
znai da elektron, u fizikom smislu, prelazi iz valentne u provodnu zonu, ve da je elektron na
energetskim nivoima koji odgovaraju pomenutim zonama). Treba naglasiti da se irina zabranje-
ne zone poluprovodnika smanjuje sa poveanjem temperature, sl. 7.11.
Usled toga to kod poluprovodnika irine zabranjenih zona nisu velike, izvestan broj va-
lentnih elektrona ak i na relativno niskim temperaturama raspolae dovoljnom energijom da se
oslobodi valentnih veza i iz valentne zone pree u provodnu zonu, ostavljajui za sobom upljine
u valentnoj zoni. Treba napomenuti da je valentna zona prelaskom izvesnog broja valentnih
elektrona u provodnu zonu ostala nepopunjena, tako da i u njoj moe da doe do kretanja nae-
lektrisanja pod dejstvom stranog elektrinog polja.
Prema irini zabranjene zone, materijali se dele na provodnike, poluprovodnike i izo1ato-
re, sl. 7.12. Kod metala, sa napomenom da oni nemaju zabranjenu zonu (provodna i valentna zo-
na se dodiruju ili preklapaju), najvia energetska zona, koja sadri valentne elektrone, nije popu-
njena, sl. 7.12a. Zbog toga kod metala elektroni mogu lako prelaziti u energetske nivoe iznad
Fermijevog i slobodno se kretati pod uticajem elektrinog polja (Fermijev nivo kod metala se
definie kao onaj energetski nivo ispod koga su na temperaturi apsolutne nule svi nivoi popu-
njeni, a iznad njega svi nivoi prazni, pri emu verovatnoa da e taj nivo biti popunjen na tempe-
raturi T>0 iznosi 50%). Kod izolatora je zabranjena zona iroka, sl. 7.12c, obino nekoliko elek-
tronvolti, ili vie. Zbog toga pri normalnim uslovima samo zanemarljivo mali broj elektrona mo-
118
e da pree u provodni opseg, to objanjava izolaciona svojstva ovakvih materijala. Bitne raz-
like izmeu izolatora i poluprovodnika nema, niti je granica izmeu njih otra. Ako je irina za-
branjene zone do oko 3 eV, smatra se da je to poluprovodnik, a ako je vea od 3 eV moe se
govoriti o izolatoru. I dok su metali dobri provodnici sa otpornou oko 10-4 cm, a izolatori
izuzetno loi provodnici elektrine struje, jer imaju otpornost reda 1012 cm, dotle poluprovod-
nici mogu imati otpornost u vrlo velikom opsegu, od male, kada se ponaaju kao provodnici, do
velike, koja se pribliava otpornosti izolatora. Bitna razlika izmeu provodnika i poluprovodnika
ogleda se u tome to je provodnost kod provodnika ostvarena uglavnom pomou elektrona, a kod
poluprovodnika jo i pomou upljina.
SI. 7.11. irina zabranjene zone germanijuma, silicijuma i galijum-arsenida u funkciji temperature.
Sl. 7.12. Energetske zone provodnika (a), poluprovodnika (b) i izolatora (c)
(EV vrh valentne zone; EC dno provodne zone).
119
Unutar zabranjene zone se nalazi jo jedan energetski nivo tkzv. Fermijev nivo EF,
koji je konstanta u Fermi-Dirakovoj funkciji raspodele, a prema kojoj po energetskim nivoima
podlee raspodela elektrona i upljina. Pokazuje se da se kod sopstvenog poluprovodnika Fermi-
jev nivo nalazi na sredini zabranjene zone (sl. 7.13a), a kod n-tipa poluprovodnika u gornjoj
polovoni zabranjene zone (sl. 7.13b), i to to je koncentracija donorskih primesa vea, to je Fer-
mijev nivo blii dnu provodne zone; kod p-tipa poluprovodnika (sl. 7.13c) je obrnuto: Fermijev
nivo je u donjoj polovini zabranjene zone i to je utoliko blii vrhu valentne zone ukoliko je
koncentracija akceptorskih primesa vea.
Sl. 7.13. Poloaj Fermijevog nivoa.
Treba napomenuti da je Fermijev nivo energetski nivo sa odreenim fizikim znaenjem

samo kod metala, kada predstavlja maksimalni nivo elektrona na temperaturi apsolutne nule.
Iako se Fermijev nivo kod poluprovodnika ne moe tano da definie, odnosno ne moe mu se
dati odreena fizika interpretacija, ipak je njegovo uvoenje od izuzetne koristi pri prouavanju
provoenja struje u poluprovodnicima i poluprovodnikim komponentama. Po analogiji sa meta-
lima, gde Fermijev nivo odraava termodinamiku energiju sistema, i kod poluprovodnika Fer-
mijev nivo mora biti kontinualan na mestu spoja dva poluprovodnika, odnosno poluprovodnika
i metala.
Uvoenjem Fermijevog nivoa moe se pokazati da je u termodinamikoj ravnotei (kada
kroz poluprovodnik ne protie struja) proizvod koncentracija elektrona n0 i upljina p0 jednak
kvadratu sopstvene koncentracije nosilaca naelektrisanja:
p 0 n0 = ni2 . (7.1)
Ovaj izraz je veoma bitan, s obzirom da prua mogunost izraunavanja koncentracije

manjinskih nosilaca. Na primer, ako je na sobnoj temperaturi koncentracija donorskih primesa u
n-tipu poluprovodnika ND = 51016 cm-3, prema (7.1) koncenracija upljina kao manjinskih nosi-
laca n-tipu poluprovodnika iznosi p0 = ni2/ND = (1,131010)2/51016 2,5103 cm-3.
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7.5. TRANSPORT NOSILACA NAELEKTRISANJA
Kada na poluprovodnik nije prikljueno spoljanje elektrino polje, elektroni i upljine se
nalaze u stalnom kretanju usled termike energije kristala. Ovo kretanje nosilaca naelektrisanja
je haotino, tj. svi smerovi kretanja su podjednako verovatni. Ukoliko bi jedan smer kretanja bio
favorizovan, to bi znailo da kroz poluprovodnik protie elektrina struja i bez prikljuenja na-
pona, to je, oigledno, nemogue. Putanje po kojima se kreu nosioci naelektrisanja u odsustvu
spoljanjeg elektrinog polja imaju oblik izlomljenih linija. Ovakav oblik putanja nastaje prven-
stveno usled uticaja termikih vibracija kristalne resetke. Naime, ove vibracije se sastoje od lon-
gitudinalnih ili transverzalnih talasa odreene talasne duine i brzine prostiranja, a kao rezultat
javljaju se fononi koji imaju dvojni karakter estice i talasa. Pri sudarima sa fononima, nosioci
naelektrisanja skreu sa prvobitne putanje, usled ega putanja ima oblik izlomljene linije. U po-
luprovodnicima jak uticaj na haotino kretanje elektrona i upljina imaju, takoe, jonizovane pri-
mese usled dejstva Kulonove sile zbog pozitivno, odnosno negativno naelektrisanih donorskih i
akceptorskih jona. Treba napomenuti da i atomi drugih stranih nejonizovanih hemijskih eleme-
nata, koji se mogu nai u kristalu, kao i defekti kristalne reetke, mogu imati udela na kretanje i
putanje pokretnih nosilaca naelektrisanja.
Sl. 7.14. (a) Ilustracija haotinog kretanja elektrona u poluprovodnicima;

(b) kretanje elektrona u prisustvu spoljanjeg elektrinog polja.
Kretanje elektrona moe se, u odsustvu spoljanjeg elektrinog polja, prikazati kao na sl.
7.14a, na kojoj je prikazano sedam uzastopnih sudara elektrona sa fononima ili drugim uzroni-
cima. Rastojanja izmeu sudara su razliita, ali se moe definisati srednji slobodan put l, koji se
kree u granicama od 10-5 cm do 10-4 cm, to je je oko 2 do 3 reda veliine puta vee od rastoja-
nja izmeu atoma poluprovodnika. Brzine kojima se nosioci kreu izmeu sudara su statistiki
rasporeene, a u proseku pri sobnoj temperaturi iznose oko 107 cm/s. Srednje vreme izmeu dva
sudara iznosi oko 10-12 s do 10-11 s.
7.5.1. Drift nosilaca naelektrisanja

Kada se poluprovodnik podvrgne spoljanjem elektrinom polju, opisanom termikom
kretanju nosilaca naelektrisanja superponira se usmereno kretanje pod dejstvom toga polja. Kre-
tanje elektrona u prisustvu elektrinog polja prikazano je na sl. 7.14b. Vidi se da u pravcu de-
lovanja elektrinog polja elektron izmeu dva sudara dobija dodatnu, usmerenu brzinu, tkzv.
driftovsku brzinu. Ova brzina, usled estih sudara i promena pravca kretanja nosilaca, nee se
121
stalno poveavati, ve e postii jednu srednju vrednost, koja se za elektrina polja K koja nisu
suvie velika, moe izraziti u obliku:
vn = n K , (7.2)
gde koeficijent proporcionalnosti n izmeu brzine i elektrinog polja predstavlja pokretljivost

elektrona i izraava se u cm2/Vs.
I upljine se vladaju na slian nain, ali zbog razliite mase i drugaijeg naina postanka,
pokretljivost upljina p je manja od pokretljivosti elektrona (sl. 7.15). Slino (7.2), srednja
driftovska brzina upljina vp iznosi:
vp = pK . (7.3)
Sl. 7.15 Eksperimentalno dobijene zavisnosti brzine nosilaca

naelektrisanja od elekrinog polja za ist Ge, Si i GaAs.
Za velike vrednosti elektrinog polja prestaje da vai linearna zavisnost izmeu brzine
kretanja nosilaca i elektrinog polja data jedn. (7.2) i (7.3). Pri tim poljima se poveava broj
sudara nosilaca, te brzina usmerenog kretanja sve manje zavisi od polja. Postoji granina brzina
kojom se nosioci mogu kretati kroz kristal, sl. 7.15. Kada nosioci dostignu graninu brzinu, dalje
poveanje elektrinog polja ne poveava brzinu usmerenog kretanja nosilaca, ve samo njihovu
kinetiku energiju. Na sl. 7.15 su prikazane eksperimentaine zavisnosti driftovske brzine od
elektrinog polja za Ge, Si i GaAs. Kao to se vidi sa slike, granina brzina za sva tri polupro-
vodnika iznosi oko 107 cm/s.
Pokretljivost nosilaca naelektrisanja jako zavisi od temperature i koncentracije primesa.
Zbog toga su na sl. 7.16 prikazane eksperimentalne zavisnosti pokretljivosti elektrona i upljina
u Ge, Si i GaAs od koncentracije primesa na sobnoj temperaturi, a na sl. 7.17 zavisnosti pokret-
ljivosti u Si od temperature pri razliitim vrednostima koncentracije primesa. Sa slika 7.16 i 7.17
moe se videti da je pri sobnoj temperaturi pokretljivost elektrona priblino dva puta vea od
pokretljivosti upljina.
122
Sl. 7.16. Zavisnost pokretljivosti elektrona i upljina od koncentracije primesa u Ge, Si i GaAs.
Sl. 7.17. Zavisnost pokretljivosti elektrona (a) i upljina (b) od temperature

pri razliitim vrednostima koncentracije primesa u silicijumu.
123
7.5.2. Specifina otpornost i provodnost
homogenih poluprovodnika; driftovska struja
Specifina otpornost poluprovodnika predstavlja koeficijent proporcionalnosti izmeu
elektrinog polja K i gustine struje J:
K = J . (7.4)
Ova veliina je inverzno proporcionalna specifinoj provodnosti, tj. = 1/, tako da je:
J = K . (7.5)
Kada su poznate pokretljivosti upljina p i slobodnih elektrona n, kao i njihova koncen-

tracija u poluprovodniku (uz napomenu da se, kada kroz poluprovodnik protie struja, koncen-
tracija upljina oznaava sa p, a koncentracja elektrona sa n), specifina otpornost se izraunava
prema izrazu:
1 1
= = . (7.6)
q( n n + p p)
U istom (sopstvenom) poluprovodniku koncentracija slobodnih elektrona je jednaka

koncentraciji upljina (ni = pi), te jedn. (7.6) za specifinu otpornost postaje:
1 1
i = = . (7.7)
i qni ( n + p )
Specifina otpornost, odnosno provodnost istog poluprovodnika zove se sopstvena ili

unutranja otpornost (provodnost) poluprovodnika.
Ako je n ND >> p (n-tip poluprovodnika), onda je:
1 1
n . (7.8)
q n n q n N D
Ako je, pak, p NA >> n (p-tip poluprovodnika), sledi:
1 1
p . (7.9)
q p p q p N A
Izmerene vrednosti specifine otpornosti (pri T = 300K) za silicijum dopiran borom (p-
tip) i fosforom (n-tip) u zavisnosti od koncentracije primesa prikazane su na sl. 7.18.
Driftovska struja. Struja koja nastaje kretanjem elektrona i upljina pod uticajem elek-
trinog polja predstavlja driftovsku struju. Gustina struje usled kretanja elektrona (gustina struje
elektrona) jeste:
J ndrift = qnv n = qn n K = n K , (7.10)
gde je vn brzina elektrona prema jedn. (7.2), a n provodnost poluprovodnika usled posto-
janja pokretnih elektrona.
124
Sl. 7.18. Specifina otpornost silicijuma pri T = 300K u zavisnosti od koncentracije primesa.
Gustina struje nastala kretanjem upljina pod uticajem elektrinog polja (gustina struje
upljina) je:
J pdrift = qpv p = qp p K = p K , (7.11)
gde je p provodnost poluprovodnika usled postojanja pokretnih upljina.

Prema tome, za poluprovodnik kod koga u procesu proticanja struje uestvuju i elektroni
i upljine, driftovska gustina struje je:
J drift = J ndrift + J pdrift = ( n + p ) K = q (n n + p p ) K . (7.12)
7.5.3. Difuzija u poluprovodnicima; difuziona struja

Difuziono kretanje estica nastaje, uopte, kada u prostoru postoji razlika njihove gustine.
To vai i za poluprovodnike. Naime, kada postoji razlika u gustini slobodnih nosilaca naelektri-
sanja, nastae njihovo kretanje sa mesta vie koncentracije ka mestu nie koncentracije, sa
tendencijom da se koncentracije nosilaca izjednae. Ovo kretanje nosilaca prouzrokuje elektrinu
struju, tkzv. difuzionu struju.
Ako se posmatraju, na primer, upljine ija se koncentracija menja samo du koordinate
x, a u smerovima y i z je konstantna, difuziona struja e biti proporcionalna gradijentu kon-
centracije upljina u smeru ose x. Kada promena koncentracije postoji samo du jedne koordina-
te, gradijent je jednak dp/dx i treba ga uzeti sa negativnim predznakom, jer se kretanje upljina
obavlja sa mesta vie koncentracije prema mestu sa niom koncentracijom, sl. 7.19a. Difuziona
struja e, takoe, biti proporcionalna sposobnosti estice da difunduje, tj. difuzionoj konstanti
D. U sluaju upljina, difuziona konstanta se oznaava sa Dp. Prema tome, za gustinu difuzione
struje upljina moe se napisati:
125
Sl. 7.19. Difuziono kretanje upljina (a) i elektrona (b).
dp
J pdiff J pd = qD p . (7.13)
dx
U sluaju difuzije elektrona, za difuzionu gustinu struje elektrona vai sledee:
dn
J ndiff J nd = qDn . (7.14)
dx
U poslednjoj jednaini je pozitivan predznak zbog toga to je naelektrisanje elektrona negativno,

tako da je q(dn/dx) = qdn/dx.
Ovde se ukazuje da difuziona komponenta struje ima odluujuu ulogu u radu bipolarnih
poluprovodnikih komponenata na bazi p-n spojeva (pod bipolarnom komponentom podrazu-
meva se komponenta kod koje u procesu provoenja elektrine struje uestvuju obe vrste nosila-
ca naelektrisanja i elektroni i upljine).
7.5.4. Ukupna struja

Kada u uzorku poluprovodnika postoji i elektrino polje i gradijent koncentracije nosilaca
i kada je elektrino polje relativno malo (tako da pokretljivost ne zavisi od polja), gustine struje
elektrona i upljina u jednodimenzionalnoj predstavi su:
dn
J n = qn n K + qDn (7.15)
dx
i
dp
J p = qp p K qD p . (7.16)
dx
Poslednje dve jednaine poznate su pod nazivom transportne jednaine.

Ukupna struja u poluprovodniku jednaka je zbiru struje elektrona i struje upljina, tj.:
J = Jn + J p . (7.17)
126
8. DIODE
Rad poluprovodnikih dioda zasniva se na usmerakim osobinama p-n spojeva. Zbog to-
ga e prvi deo ove glave biti posveen karakteristikama p-n spojeva. U praksi je skoro iskljuivo
jedna oblast p-n spoja male specifine otpornosti, to znai da je u njoj velika koncentracija pri-
mesa; drugim reima, jedna oblast p-n (ili n-p) spoja je najee jako dopirana (NA,D > 1017 cm-
3
). Prema tome, re je o p+-n ili n+-p spojevima, ali, da se ta injenica ne bi stalno isticala, nadalje
e se umesto oznaka spojeva p+-n i n+-p koristiti oznake p-n i n-p, respektivno.
8.1. p-n I n-p SPOJEVI

Danas se iskljuivo proizvode planarne diode, sl. 8.1. Planarne diode, koje treba da imaju
malu direktnu otpornost, prave se u epitaksijalnom sloju silicijuma. Naime, da bi redna otpor-
nost diode bila to manja, silicijumska ploica na kojoj se planarnim postupkom istovremeno
oformljuje veliki broj dioda, trebalo bi da je to tanja. Meutim, ukoliko je ploica tanja, utoliko
se lake lomi. Minimalna debljina ploice sa kojom se uopte moe raditi je (120150) m, dok
je za dobar rad diode neophodna znatno manja debljina (vea debljina ploice samo poveava
rednu otpornost). Zbog toga se smanjenje redne otpornosti postie epitaksijalno naraslim slojem,
sl. 8.1. Kako je supstrat male otpornosti, to je otpornost tog dela zanemarljivo mala, te je i redna
otpornost diode mala. Mala otpornost osnove ima prednost i zbog toga to je sa njom mogue
lako ostvariti dobar neusmeraki spoj, te i to smanjuje rednu otpornost.
Sl. 8.1. Planarna epitaksijalna dioda.
127
Iako diode sa epitaksijalnim slojem imaju bolje karakteristike od dioda bez takvog sloja
(prvenstveno manju rednu otpornost i vei probojni napon), nadalje e se, u cilju jednostavnosti,
razmatrati samo diode koje ne sadre epitaksijalni sloj, sl. 8.2, kao i diode sa tkz. skokovitim p-n
spojem kada sa p-tipa na n-tip postoji nagla promena koncentracije primesa, sl. 8.6.
Sl. 8.2. Ilustracija diode bez epitaksijalnog sloja; velikim krugovima u prelaznoj
oblasti p-n spoja oznaene su jonizovane primese (pozitivni donorski i negativni
akceptorski joni), a kruii sa znakom + oznaavaju upljine kao veinske nosio-
ce u p-oblasti, dok je za veinske elektrone u n-oblasti iskoriena oznaka .
Dakle, p-n spoj se sastoji od intimnog spoja poluprovodnika p-tipa i poluprovodnika n-ti-
pa. Mesto na kome se prelazi sa jednog na drugi tip poluprovodnika zove se metalurki spoj, sl.
8.3a; to je, praktino, povrina dodira poluprovodnika p- i n-tipa. Kao to je u sedmoj glavi
reeno, moe se smatrati da su na sobnoj temperaturi skoro sve primese jonizovane. Zbog toga
e u p-oblasti veinski nosioci biti upljine, ija je koncentracija ppo NA, a u n-tipu elektroni,
sa koncentracijom nno ND. Manjinski nosioci u p-oblasti su elektroni (sa koncentracijom npo), a
u n-oblasti upljine, sa koncentracijom pno. S obzirom da je u p-oblasti koncentracija upljina
za nekoliko redova veliine vea nego u n-oblasti, to e iz p-oblasti ka n-oblasti nastati difuzija
upljina. Na mestu uz metalurski spoj, odakle su difuzijom otile upljine, ostaju nekompenzo-
vani akceptorski joni (sl. 8.2 i sl. 8.3a) i, kako su oni negativno naelektrisani, u p-oblasti ostaje
negativna koliina naelektrisanja (Q). Isto tako, sa strane n-oblasti difuzijom kroz metalurki
spoj odlaze elektroni u p-oblast, te u n-oblasti ostaju nekompenzovani donorski joni (sl. 8.2 i sl.
8.3a), odnosno pozitivna koliina naelektrisanja (+Q). Ta oblast sa nekompenzovanim prime-
sama, tj. sa prostornim naelektrisanjem vrsto vezanim za kristalnu reetku, zove se prelazna
oblast p-n spoja (sl. 8.2 i sl. 8.3a). U njoj, usled prostornog naelektrisanja postoji elektrino
polje K (sl. 8.3a), odnosno tolika potencijalna razlika Vbi da u ravnotei zaustavlja dalje difu-
ziono kretanje nosilaca naelektrisanja. Zbog postojanja naelektrisanja, prelazna oblast p-n spoja
zove se i barijerna oblast ili oblast prostornog naelektrisanja.
128
Sl. 8.3. p-n spoj sa izvodima bez polarizacije (a), pri direktnoj (b) i inverznoj polarizaciji (c).
129
Sl. 8.4. Uz objanjenje proticanja struje kroz direktno polarisan p-n spoj.
irina prelazne oblasti, ili barijera, moe se menjati prikljuenjem spoljanjeg napona.
Smanjenje irine barijere postie se kada se na p-oblast prikljui pozitivan, a na n-oblast nega-
tivan pol spoljanjeg napona, sl. 8.3b; takav napon V zove se direktan napon. U suprotnom
sluaju, tj. prikljuenjem inverznog napona VR, irina prelazne oblasti se poveava, sl. 8.3c.
Neka se na p-n spoj dovede napon tako da se barijera smanji, sl. 8.3b. Usled smanjenja
barijere difuziona struja kroz p-n spoj postaje vea od driftovske i kroz p-n spoj e proticati
struja. Na sl. 8.4 simbolino je prikazano kretanje elektrona i upljina koje ine struju kroz p-n
spoj, odnosno kroz diodu. U n-oblasti veinski nosioci su elektroni i oni se kreu sdesna u levo,
inei driftovsku struju elektrona Indrift, koja je suprotnog smera od smera kretanja elektrona
znai, u desno. Injektovane upljine iz p-oblasti u n-oblast predstavljaju manjinske nosioce u toj
oblasti (na sl. 8.4a su one predstavljene belim kruiima). Njihova koncentracija je najvea ne-
posredno uz prelaznu oblast, tj. na poetku n-oblasti. upljine se kroz n-tip poluprovodnika (n-
oblast) kreu difuzijom sleva u desno, usled ega, takoe sleva u desno, nastaje difuziona struja
upljina Ipdiff. U bilo kojoj taki u n-oblasti ukupna struja koja protie kroz direktno polarisanu
diodu bie jednaka zbiru driftovske struje elektrona i difuzione struje upljina, tj. ID = Indrift + Ipdiff
(ovo je razlog zbog kojeg dioda spada u tkzv. bipolarne komponente komponente kod kojih
struju ine oba tipa naelektrisanja, i elektroni i upljine). S druge strane, u p-oblasti veinski
nosioci su upljine i one se kreu sleva u desno, od kojih nastaje driftovska struja upljina Ipdrift,
koja je istog smera sa smerom kretanja upljina znai, u desno. Injektovani elektroni iz n-
oblasti u p-oblast predstavljaju manjinske nosioce u toj oblasti. Kako je njihova koncentracija
najvea neposredno uz prelaznu oblast, oni se kroz p-tip poluprovodnika (p-oblast) kreu
difuzijom sdesna u levo, inei difuzionu struju elektrona Indiff, sa smerom suprotnim od difu-
zionog kretanja elektrona. I ovde, u bilo kojoj taki u p-oblasti ukupna struja koja protie kroz
direktno polarisanu diodu je jednaka zbiru driftovske struje upljina i difuzione struje elektrona.
130
Sl. 8.5. Simbolina predstava nastanka veoma male struje pri inverznoj polarizaciji diode.
Kada se, pak, na diodu dovede inverzan napon (sl. 8.3c), barijera se povea. U tom slu-
aju difuziona struja veinskih nosilaca kroz barijeru prestaje, a driftovska struja ne moe da
poraste iznad ravnotene, jer u prelaznoj oblasti nema odgovarajuih nosilaca. Na primer, difu-
zionoj struji upljina, koju ine veinski nosioci iz p-oblasti, dri ravnoteu driftovska struja istih
nosilaca koji su uli u prelaznu oblast. Prema tome, driftovska komponenta struje kroz p-n spoj
ne moe biti vea od difuzione. Da bi ona porasla, potrebno je da iz n-oblasti dou upljine.
upljine su u n-oblasti manjinski nosioci; njih ima vrlo malo, te e i struja u ovom smeru biti
vrlo mala, sl. 8.5. Zbog toga se p-n spoj zove i usmeraki spoj, jer on u jednom smeru proputa,
a u drugom ne proputa elektrinu struju.
8.1.1. Ravnoteno stanje na p-n spoju

Raspodela koncentracije primesa u okolini metalurskog spoja moe biti takva da je prelaz
sa p- na n-tip poluprovodnika skokovit, linearan, eksponencijalan, ili po nekoj drugoj funkciji
(erfc, Gausovoj, itd.). Skokovitim prelazom se moe smatrati onaj prelaz kod kojeg je koncen-
tracija primesa priblino konstantna u samoj prelaznoj oblasti, sl. 8.6. Tako se i spoj dobijen
difuzijom u izvesnim uslovima moe smatrati skokovitim, a to je kada je dubina p-n spoja
relativno mala. Duboki difundovani p-n prelazi su priblino linearni. Nadalje e se samo analizi-
rati skokoviti p-n spojevi pri sobnoj temperaturi (T = 300 K).
Neka su otpornosti p- i n-oblasti silicijuma respektivno p = 0,009 cm i n =1 cm. Sa
sl. 7.18 se za ove otpornosti dobija da je koncentracija akceptora NA = 1019 cm-3, a koncentracija
donora ND = 51015 cm-3. U tom sluaju koncentracija manjinskih nosilaca u p-tipu (elektrona),
na osnovu (7.1) i ni = 1,131010 cm-3, iznosi n po ni2 / N A 1,281020/(11019) 13 cm-3, a
upljina u n-tipu p no ni2 / N D 1,281020/(51015) 2,6104 cm-3. Na sl. 8.7 su slikovito
prikazane koncentracije akceptora, upljina i elektrona u p-tipu i koncentracije donora, elektrona
131
i upljina u n-tipu silicijuma sa pomenutim brojnim vrednostima. Ovde je uzeto da je
koncentracija veinskih nosilaca priblino jednaka koncentraciji primesa (pretpostavlja se da su
sve primese jonizovane).
Sl. 8.6. Aproksimacija skokovitom raspodelom primesa (skokovit pn-spoj).
Sl. 8.7. Uz ilustraciju vrednosti koncentracija nosilaca naelektrisanja

i primesa u p- i n-oblasti silicijuma koje ine p-n spoj.
132
Na sl. 8.8a nacrtana je prelazna oblast p-n spoja. Kako je ovaj crte u linearnoj razmeri,
to slika ne prua pravi odnos veliina. Sa leve strane metalurkog spoja, usled odlaska upljina,
ostali su nekompenzovani akceptorski joni. Sa desne strane, odlaskom elektrona, ostali su ne-
kompenzovani donorski joni. Kako u ravnotei p-n spoj mora biti elektroneutralan (+Q = |Q|),
to je broj nekompenzovanih donora sa jedne strane jednak broju nekompenzovanih akceptora sa
druge strane. Prema tome, prelazna oblast e biti ira sa one strane sa koje je koncentracija
primesa manja (u ovom sluaju u n-oblasti (xn >> xp)).
Koncentracija veinskih nosilaca kroz prelaznu oblast opada za nekoliko redova veliine
(sl. 8.7), te je u odnosu na koncentraciju primesnih jona zanemarljivo mala. To daje mogunost
da se u razmatranjima pretpostavi da postoji totalno osiromaenje nosilaca naelektrisanja u
prelaznoj oblasti (sl. 8.8b). Drugim reima, aproksimacija totalnim osiromaenjem prelazne
oblasti, koja se, kao to je reeno, jo zove i barijera i oblast prostornog naelektrisanja, kazu-
je da je u toj oblasti koncentracija nekompenzovanih primesa jednaka ukupnoj koncentraciji pri-
mesa. Totalno osiromaenje se posebno moe prihvatiti u sluaju kada se prikljui takav spo-
ljanji napon na p-n spoj da se barijera povea (pri inverznoj polarizaciji, sl. 8.3c).
Sl. 8.8. Prelazna oblast skokovitog p-n spoja (nije u pravoj razmeri): (a) p-n spoj sa naznakom
prelaznih oblasti; (b) aproksimacija totalnog osiromaenja.
U p-tipu poluprovodnika Fermijev nivo je blizu vrha valentne zone, a u n-tipu blizu dna
provodne zone. Kako je u ravnotei Fermijev nivo u celom poluprovodniku konstantan, to e
nastati krivljenje zona, sl. 8.9. Na osnovu sl. 8.9 moe se pokazati da se za kontaktnu razliku
potencijala Vbi p-n spoja dobija:
kT p po N N
Vbip n Vbi = ln U T ln A 2 D , (8.1)
q p no ni
pri emu su k Bolcmanova konstanta, a UT = kT/q tkzv. termiki potencijal i na sobnoj tempe-
raturi (T = 300K) je UT 0,026 V.
Analogno, kontaktna razlika potencijala n-p spoja data je izrazom:
kT nno N N
Vbin p = ln U T ln A 2 D . (8.2)
q n po ni
133
Sl. 8.9. (a) Odvojeni poluprovodnici p- i n-tipa pri termodinamikoj ravnotei;
(b) ravnoteno stanje na p-n spoju bez prikljuenog spoljanjeg napona.
Na sl. 8.10 prikazane su zavisnosti kontaktnih razlika potencijala u Si od koncentracije

primesa u slabije dopiranoj oblasti, pri emu je, na osnovu (8.1) i (8.2), raunato sa koncentraci-
jom primesa u jae dopiranoj oblasti NA = 51016 cm-3, NA = 1018 cm-3 i NA = 51019 cm-3,
Sl. 8.10. Zavisnosti kontaktnih razlika potencijala za skokovite

p-n spojeve Si od koncentracije primesa u slabije dopiranoj oblasti.
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Prikljuenjem spoljanjeg napona napon na barijeri se menja. Drugim reima, usled di-
rektnog napona V, napon barijere VB, koji je u ravnotei bio jednak kontaktnoj razlici potencijala
(VB = Vbi), smanjuje se na VB = Vbi V; ukoliko se prikljui inverzni spoljanji napon ( Vinv ),
napon barijere se poveava i iznosi VB = Vbi ( Vinv ) = Vbi + Vinv .
8.1.2. Kapacitivnost prostornog naelektrisanja

U prelaznoj oblasti, kao to je pokazano, postoji prostorno naelektrisanje od jonizovanih
primesa. Ako je, dakle, re o p-n spoju, prema sl. 8.8 u p-oblasti irine xp postojae negativno
naelektrisanje Qp = qSxpNA (S je povrina p-n spoja), a u n-oblasti irine xn pozitivno nalektri-
sanje Qn = qSxnND. S obzirom da poluprovodnik ima tano definisanu vrednost dielektrine
konstante s = 0rs (0 dielektrina konstanta vakuuma), to se naelektrisanja Qp i Qn mogu
smatrati kao naelektrisanja na oblogama jednog kondenzatora, pri emu je rastojanje izmeu tih
obloga w = xp + xn. Kapacitivnost takvog kondenzatora
S
C = s (8.3)
w
zove se kapacitivnost prostornog naelektrisanja ili barijerna kapacitivnost.
Kako se, kao to je reeno, promenom napona na diodi moe menjati vrednost irine pre-
lazne oblasti p-n spoja, tj. w (sl. 8.4 i sl. 8.5), to se, na osnovu (8.3), moe spoljanjim naponom
V menjati i barijerna kapacitivnost u relativno irokim granicama. Na sl. 8.11 je, u funkciji napo-
na, prikazana promena barijerne kapacitivnosti jedne diode sa skokovitim p-n prelazom U praksi
je to iskorieno kod varikap dioda (videti deo 4.3.3). Iako je promena kapacitivnosti sa
naponom vea kod direktno polarisanih p-n spojeva, koristi se samo inverzna polarizacija dioda,
s obzirom da tada kroz diodu protie zanemarljivo mala struja (o emu e kasnije biti vie rei).
koje se ugrauju u tjunere televizora i radio aparata (napominje se da su prave varikap diode sa
tkzv. superstrmim prelazom, a ne sa skokovitim p-n spojem).
Sl. 8.11. Kapacitivnost skokovitog p-n spoja u funkciji napona na diodi.
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8.2. STRUJA DIODE
Difuziona struja. Uz pretpostavku strmog p-n spoja, na sl. 8.12a je kvalitativno pred-
stavljena raspodela nosilaca naelektrisanja du nepolarisane diode. Meutim, kada se na p-n spoj
prikljui direktni napon V (na p-tip pozitivan a na n-tip negativan pol napona, sl. 8.3b), smanjie
se napon barijere na vrednost VB = Vbi V, odnosno smanjie se koee elektrino polje u pre-
laznoj oblasti p-n spoja. Usled toga nastae injekcija nosilaca naelektrisanja, i to upljina iz p- u
n-oblast i elektrona iz n- u p-oblast, sl. 8.12b. Stoga to sada postoji gradijent koncentracije
manjinskih nosilaca naelektrisanja, a u skladu sa onim to je ranije napomenuto, proticae u n-
tipu difuziona struja upljina i u p-tipu poluprovodnika difuziona struja elektrona.
Sl. 8.12. Kvalitativna predstava koncentracija nosilaca naelektrisanja du

(a) nepolarisane i (b) direktno polarisane (samo za manjinske nosioce) p-n diode.
Injektovane upljine, kao manjinski nosioci u n-oblasti, kreui se du x-ose u desno ine
difuzionu struju upljina (ija je gustina Jpdif). Te upljine se rekombinuju sa veinskim nosio-
cima elektronima, sl. 8.13; istovremeno, usled prikljuenog napona elektroni se du n-oblasti
kreu u suprotnom smeru od kretanja upljina, tj. sdesna u levo i to njihovo kretanje definie
driftovsku struju elektrona, ija je gustina Jndrift. Drugim reima, kako gustina difuzione struje
upljina Jpdif opada, tako gustina driftovske struje elektrona Jndrift raste (sl. 8.13). Smer difuzione
struje upljina je u smeru kretanja upljina, a ovo kretanje je u smeru opadanja njihove kon-
136
centracije, tj. u desno. Elektroni se, pak, kreu u susret upljinama, u levo, te je i smer struje
elektrona u desno. U p-oblasti je situacija obrnuta: injektovani elektroni se difuziono kreu u
levo (od njih potie difuziona struja elektrona gustine Jndif Jnd). Ovi elektroni se u p-oblasti
rekombinuju sa veinskim upljinama (sl. 8.12), koje se, pak, kreu sleva na desno, usled kojih
nastaje driftovska gustina struje Jpdrift.
Sl. 8.13. Kvalitativna predstava raspodele gustina struja u p-n diodi.
Ne ulazei u nain analitikog odreivanja, za struju diode se dobija:
V V
I = I s exp 1 I s exp , (8.4)
UT UT
gde je V spoljanji napon na diodi, UT termiki potencijal (UT = 0,026 V pri T = 300K), a Is je in-
verzna struja zasienja diode.
Struja Is je nazvana inverznom zbog toga to bi, na osnovu srednjeg lana u (8.4), ta
struja tekla pri inverznoj polarizaciji. Naime, pri inverznoj polarizaciji (na n-tip pozitivan a na p-
tip negativan pol napona, sl. 8.3c) je u jedn. (8.4) exp(-V/UT) << 1 ve pri naponima V = 0,2V,
tako da iz (8.4) sledi da je tada I = Is. Inverzna struja zasienja je veoma mala (kod silicijum-
skih dioda reda pA do nA), s obzirom da nju odreuju koncentracije manjinskih nosilaca naelek-
trisanja, a one su, kao to je pokazano, male.
Pri direktnoj polarizaciji p-n spoja eksponencijalna funkcija u jedn. (8.4) brzo raste i ve
pri naponu veem od 0,2V je exp(V/UT) >> 1. Prema tome, p-n spoj ukljuen u kolo elektrine
struje, proputa struju kada je direktno polarisan, a praktino je ne proputa pri inverznoj pola-
rizaciji; drugim reima, p-n spoj (dioda) ima usmerake karakteristike, sl. 8.14. Kao to se sa
sl. 8.14a vidi, struja silicijumske diode naglo poinje da raste oko 0,6V, ali se kao napon voe-
nja diode uvek uzima V = 0,7 V.
Izraz (8.4) daje izuzetno dobro slaganje teorijskih i eksperimentalnih vrednosti struja pri
direktnoj polarizaciji diode za napone V 0,4 V, a to su upavo oni naponi pri kojima se dioda i
koristi. Pri niim direktnim naponima, a posebno pri inverznoj polarizaciji izmerene vrednosti
inverznih struja Ir su znatno vee od Is (obino je Ir 1000Is). Stoga, pri inverznoj polarizaciji
ne treba raunati sa strujom Is, ve sa sa inverznom strujom Ir >> Is.
137
Sl. 8.14. Struja (Id I) jedne silicijumske diode u funkciji napona.
Sl. 8.15. Praktian model silicijumske diode.
138
Ako to nije posebno naglaeno, za struju diode se koristi desni lan u izrazu (8.4). Kao
to se i sa sl. 8.14 vidi, a ve je to i pomenuto, struja koja protie kroz diodu pri inverznoj pola-
rizaciji je veoma mala, reda nA. Zbog tako izuzetno male struje inverzne polarizacije, a relativno
velike struje kada je dioda direktno polarisana, dioda se, u prvoj aproksimaciji, moe smatrati
elektrinim ventilom, tj. komponentom koja u jednom smeru (direktna polarizacija) proputa, a u
suprotnom (inverzna polarizacija) ne proputa struju.
Stoga je mogue uvesti tkzv. praktian model diode, koji je za silicijumsku diodu dat
na sl. 8.15. Naime, u ovom modelu se dioda pri direktnoj polarizaciji u kolu prikazuje kao
kratkospojeni prekida P sa padom napona izmeu katode i anode Vd = 0,7 V (sl. 8.15a); pri
inverznoj polarizaciji prekida P je otvoren, a zbog Iinv = 0 napon izmeu anode i katode je jed-
nak naponu izvora napajanja Vbat (sl. 8.15b). Pri tom, strujno-naponska karakteristika se smatra
idealnom (sl. 8.15c), sa naponom voenja kod silicijuskih dioda Vd = 0,7 V.
8.2.1. Testiranje ispravnosti dioda

Korienjem univerzalnih mernih instrumenata (multimetara), bilo digitalnih, bilo analo-
gnih, mogue je veoma brzo i efikasno ustanoviti da li je dioda ispravna ili ne. Naime, veina
digitalnih multimetara ima mogunost direktnog testiranja ispravosti dioda. Tipian takav multi-
metar, kao to se vidi na sl. 8.16, ima oznaku diode ka kojoj treba usmeriti funkcionalni prek-
lopnik. Svi multimetri poseduju baterije kojima se napajaju. U primeru na sl. 8.16 prikazani mer-
ni instrument se napaja sa Vbat = 2,6 V.
Ispravna dioda. Prikljuivanjem pozitivnog pola baterije digitalnog multimetra (crvena
ica na sl. 8.16a) na anodu i negativnog pola (cna ica na sl. 8.16a) na katodu, na displeju se
oitava vrednost napona na diodi koja moe biti od 0,5 V do 0,9 V, sa tipinom vrednou oko
0,7 V (kao na sl. 8.16a). Vrlo esto takvi multimetri poseduju i zvuni signal koji se u tom tre-
nutku oglaava. Da bi bili sigurni da je dioda stvarno (tanije: najverovatnije) ispravna, okreu se
izvodi diode (dioda se fiziki okrene za 180o, sl. 8.16b); tada se ista testira pod uslovima inver-
zne polarizacije. U tom sluaju se na displeju oitava napon napajanja instrumenta (2,6 V na
primeru na sl. 8.16b). Kada se merenje ispravnosti diode vri analognim multimetrom, prek-
lopnik se postavi u poloaj kojim se izabira merenje otpornosti. Napominje se da je kod takvih
instrumenata u odnosu na digitalne multimetre izmenjen polaritet napona napajanja samog in-
strumenta: oznaka uzemljenja (obino iz nje izlazi crna ica) je na pozitivnom, a oznaka koja
oznaava merenje otpornosti (trebalo bi po pravilu da bude crvena ica) je na negativnom polu
baterije kojom se napaja multimetar. Stoga e kod ispravne diode igla multimetra skrenuti kraj-
nje desno. Kada se dioda okrene (anoda i katoda izmene prethodni poloa), merna igla multime-
tra se ne pomera (u zavisnosti koji merni opseg otpornosti je izabran moe se desiti da se igla
malo i pomeri u desno).
Neispravna dioda. Neispravna dioda moe biti kada se dioda ponaa kao prekid u kolu
(tkzv. otvorena dioda) ili kada je kratkospojena. U testu u kojem se koristi digitalni multimetar
na displeju se kod otvorene diode i pri direktnoj i pri inverznoj polarizaciji oitava ista identifi-
kacija, tj. napon baterije u instrumentu, sl. 8.17a. (kod nekih multimetara pie OL). Sa druge
strane, kod kratkospojene diode i pri direktnoj i pri inverznoj polarizaciji na displeju pie takoe
ista cifra, ali je to ili 0 (kao na sl. 8.17b) ili napon znatno manji od napona baterije u instru-
mentu. Kada se koristi analogni instrument, skretanje merne igle je isto i pri direktnoj i pri in-
verznoj polarizaciji diode, s tim to je kod otvorene diode skretanje igle znatno vee nego kod
kratkospojene diode.
139
Sl. 8.16. Test kojim se pokazuje da je dioda ispravna.
Sl. 8.17. Test kojim se pokazuje da je dioda neispravna: (a) kod otvorene diode i pri
direktnoj i pri inverznoj polarizaciji je ista identifikacija (kod nekih multimetara pie OL);
(b) kod kratkospojene diode i pri direktnoj i pri inverznoj polarizaciji na displeju pie ista
cifra: ili 0 ili napon znatno manji od napona baterije u instrumentu.
140
8.3. PROBOJ p-n SPOJA
Inverzni napon na p-n spoju se ne moe poveavati neogranieno. Pri izvesnom inverz-
nom naponu Vpr inverzna struja poinje naglo da raste, sl. 8.18. Kada je nastupio ovaj trenutak,
govori se o proboju p-n spoja, a Vpr je probojni napon. Proboj moe nastati usled tunelskog
efekta, odnosno neposrednog prelaska elektrona iz valentne u provodnu zonu pod uticajem
elektrinog polja (Zenerov proboj). Drugi uzrok proboju moe biti umnoavanje (multiplikacija)
nosilaca naelektrisanja usled jakog elektrinog polja (lavinski proboj).
Sl. 8.18. Strujno-naponske karakteristike dve diode u lin-lin razmeri: kod jedne diode proboj
nastaje usled tunelovanja a kod druge usled lavinskog umnoavanja nosilaca naelektrisanja.
8.3.1. Zenerov proboj

Iz fizike je poznato da elektroni, usled svoje talasne prirode, mogu prolaziti kroz poten-
cijalnu barijeru. Prolaenje elektrona kroz barijeru mogue je ako on moe da zadri svoju ener-
giju i na drugoj strani barijere. Verovatnoa prolaenja je utoliko vea ukoliko je barijera ua, a
takoe i ukoliko ima vie elektrona sa jedne strane barijere i vie slobodnih mesta (nezauzetih
energetskih nivoa) sa druge strane. Takva situacija moe da se ostvari kod inverzno polarisanog
p-n spoja.
Naime, pod uticajem inverznog napona barijera na p-n spoju se proiruje, ali se i ener-
getske zone krive. U sluaju kada je krivljenje zona toliko veliko da provodna zona u n-tipu bu-
de naspram valentne zone u p-tipu (sl. 8.19), ispunie se uslov za tunelsko prelaenje elektrona
iz valentne zone poluprovodnika p-tipa u provodnu zonu poluprovodnika n-tipa, s obzirom da u
valentnoj zoni u p-tipu ima mnogo elektrona, a u provodnoj zoni u n-tipu mnogo praznih mesta
(nezauzetih stanja). Kako verovatnoa tunelskog prelaza zavisi i od irine barijere, to je za
nastajanje ovog proboja potrebno da irina barijere bude mala, a to e biti ako su i p-tip i n-tip
poluprovodnika jako dopirani i istovremeno oformljuju strm p-n prelaz. Napominje se da tunel-
ski proboj (Zenerov proboj Vz) p-n spoja nastaje pri inverznim naponima koji nisu vei od 5 V
(sl. 8.18).
141
Sl. 8.19. Uz objanjenje tunelskog prelaska elektrona iz valentne u provodnu zonu.
8.3.2. Lavinski proboj

Lavinski proboj nastaje udarnom jonizacijom atoma poluprovodnika u prelaznoj oblasti
p-n spoja. Na sl. 8.20 je prikazan mehanizam jonizacije. Naime, pod uticajem jakog elektrinog
polja, elektroni se kreu i dobijaju poveanu kinetiku energiju. Na kraju slobodnog puta l elek-
tron se sudari sa atomom kristalne reetke. Ako izmeu dva sudara elektron stekne kinetiku
energiju jednaku ili veu od energije jonizacije, izvrie jonizaciju atoma, te stvoriti jo jedan
slobodan elektron. Sada oba elektrona u sledeim sudarima stvore jo dva elektrona i tako dalje
se elektroni umnoavaju. Prilikom stvaranja slobodnog elektrona stvara se i upljina, koja se kre-
e u suprotnom smeru. Prelazei slobodan put, i ona, sudarom sa atomom, moe da izvri njego-
vu jonizaciju. Prema tome, bilo da pone proces umnoavanja nosilaca elektronima, bilo up-
ljinama, usled toga to se pri sudaru stvara par elektron-upljina, u ovom procesu uestvuju i
elektroni i upljine, a inverzna struja pri naponu Vpr naglo poinje da raste (sl. 8.18).
Sl. 8.20. Uz objanjenje lavinskog umnoavanja nosilaca naelektrisanja.
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8.4. KONTAKT METAL-POLUPROVODNIK
Pri kontaktu metala sa poluprovodnikom (m-s kontakt) obrazuje se oblast prostornog nae-
lektrisanja u okolini kontakta. Kod kontakta metala sa n-tipom poluprovodnika prelaskom elek-
trona iz poluprovodnika u metal formira se u poluprovodniku oblast pozitivnog, a u metalu ob-
last negativnog prostornog naelektrisanja. Treba naglasiti da je u povrinskom delu metala nae-
lektrisanje rasporeeno samo do jednog atomskog sloja, usled ega se ova oblast u metalu za-
nemaruje. Znai, oblast prostornog (nepokretnog) nalektrisanja je, praktino, samo u polupro-
vodniku. Drugim reima, u poluprovodniku n-tipa neposredno uz metal postoji osiromaena
oblast (osiromaena elektronima). Osiromaeni sloj m-s kontakta je analogan osiromaenoj ob-
lasti p-n spoja, a to znai da se i kod m-s kontakta pojavljuje kontaktna razlika potencijala Vbim s ,
ali je ona manja nego kod p-n spojeva ( Vbim s < Vbip n ). Kod kontakta metala i poluprovodnika p-
tipa se u poluprovodniku uz metal pojavljuje oblast (sloj) koja je osiromaena upljinama.
Pri direktnoj polarizaciji (kod m-s kontakta sa n-tipom poluprovodnika na metal pozitivan
a na poluprovodnik negativan pol napona, a kod m-s kontakta sa p-tipom poluprovodnika na
metal negativan a na poluprovodnik pozitivan pol napona) smanjuje se kontaktnta razlika po-
tencijala Vbim s za vrednost prikljuenog napona direktne polarizacije V. Obrnuto, pri inverznoj
polarizaciji naponom VR, kontaktna razlika potencijala se poveava za vrednost tog napona. To
znai da e pri direktnoj polarizaciji m-s kontakta kroz njega proticati vea struja nego pri in-
verznoj polarizaciji, a to, pak, znai da i m-s kontakt ima usmerake osobine, sl. 8.21.
Sl. 8.21. Strujno-naponska karakteristika Si diode sa p-n spojem i otkijeve diode.
Diode na bazi m-s kontakta zovu se otkijeve diode. Osnovna razlika izmeu otkijevih
dioda i dioda sa p-n spojevima je u tome to je kod prvih struja uglavnom posledica kretanja
143
veinskih nosilaca naelektrisanja, dok je kod p-n spojeva struja najveim delom uslovljena di-
fuzionim kretanjem manjinskih nosilaca nalektrisanja. Stoga su otkijeve diode znatno bre od
dioda sa p-n spojevima, s obzirom da kod njih nema nagomilavanja manjinskih nosilaca nae-
lektrisanja.
Razlika u strujno-naponskoj karakteristici otkijevih dioda i silicijumskih dioda sa p-n
spojevima najbolje se moe uoiti sa sl. 8.21. Tipine vrednosti napona pri kojima u direktnom
smeru struja naglo poinje da raste su kod Si dioda oko 0,6 V, dok je ta vrednost kod otkijevih
dioda oko 0,3 V. Istovremeno, inverzna struja otkijevih dioda je oko tri do etiri reda veliine
vea od inverzne struje Si diode. Ali, sa druge strane, kao to je pomenuto, otkijeve diode su
bre od silicijumskih dioda, te su, stoga, pogodnije za tad na visokim uestanostima.
8.5. PRIMENA DIODA U IZVORIMA NAPAJANJA

Nijedan elektronski ureaj ne bi mogao da radi bez jednosmernog izvora napajanja. Neki
ureaji (raunari, televizori, DVD plejeri) se direktno prikljuuju na mreni napon, koji je kod
nas uestanosti 50 Hz i efektivne vrednosti 220 V, dok drugi (mobilni telefoni, lap-topovi) kori-
ste baterije. Da bi oni ureaji koji se direktno prikljuuju na mreni napon mogli da rade, neop-
hodno je da se taj naizmenini mreni napon ispravi, tj. da se od naizmeninog napona dobije
jednosmerni napon. Taj proces se odvija u ispravljaima, sl. 8.22. Ispravljai su neophodni i kod
mobilnih telefona, lap-topova i mnogih drugih ureaja koji danas koriste punjive baterije (nikl-
kadmijumske, nikl-metal hibridne, litijum-jonske), s obzirom da se te baterije dopunjuju jedno-
smernim naponima iz ispravljaa. Osnovna elektronska komponenta u ispravljaima jeste dioda.
Sl. 8.22. Princip dobijanja jednosmernog (ispravljenog) napona od naizmeninog mrenog napona.
144
Princip na kome se zasniva dobijanje jednosmernog od naizmeninog napona pomou je-
dne diode prikazan je na sl. 8.23. Kada na anodu diode naie pozitivna poluperioda ulaznog
napona Vin (od trenutka t0 do trenutka t1, sl. 8.23a), dioda proputa struju i na potroau (otpor-
niku RL) stvara pad napona Vout istog oblika sa ulaznim naponom (sl. 8.23a). Meutim, kada na
anodu u vremenskom periodu od t1 do t2 (sl. 8.23b) naie negativna poluperioda ulaznog napona
Vin, dioda ne proputa struju i na potroau je izlazni napon Vout jednak nuli. Nailaskom sledee
pozitivne poluperiode ulaznog napona dioda ponovo provede, a zatim sa negativnom polupe-
riodom napon na izlazu ponovo biva jednak nuli, sl. 8.23c. Nedostatak ovog naina ispravljanja
jeste to struja protie kroz potroa samo za vreme jedne poluperiode naizmeninog napona,
dok je za vreme od t1 do t2 struja kroz potroa jednaka nuli.
Sl. 8.23. Ispravljanje napona pomou jedne diode.
Sl. 8.24. Ispravljanje napona pomou dve diode.
145
Bolji nain dobijanja ispravljenog napona dobija se pomou dve diode, sl. 8.24. Na istoj
slici je prikazan i transformator koji mreni napon od 220 V sniava na eljenu vrednost, i tako
snieni naizmenini napon se sa sekundarnog namotaja (sekundara) transformatora dovodi na
diode D1 i D2. Za vreme pozitivne poluperiode naizmeninog napona vodi dioda D1 (sl. 8.25a), a
dioda D2 je tada inverzno polarisana i kroz nju ne protie struja (dioda D2 je zakoena). Situa-
cija je potpuno izmenjena kad na diodu D2 naie negativna poluperioda napona sa sekundara:
tada ona vodi (sl. 8.25b), a dioda D1 je tada zakoena. Kao posledica, kroz potroa sve vreme
protie struja, koja na njemu stvara pad napona Vout kao na sl. 8.25b.
Sl. 8.25. Prikaz voenja i zakoenja pojedinih dioda u ispravljau sa dve diode.
Najei i najbolji nain dobijanja ispravljenog napona postie se pomou etiri diode ve-
zane na nain prikazan na sl. 8.26 (tako vezane diode ine tkzv. Grecov spoj). Naime, za vreme
pozitivne poluperiode naizmeninog napona koji se dovodi sa sekundara transformatora provede
dioda D1; struja prolazi kroz potroa RL i strujni krug se zavrava preko diode D2 (sl. 8.26a).
Drugim reima, tada vode diode D1 i D2, a diode D3 i D4 su tada zakoene. Meutim, kada na
diodu D3 naie negativna poluperioda napona sa sekundara, uloge dioda su izmenjene: tada vode
diode D3 i D4 (sl. 8.26b), a diode D1 i D2 su tada zakoene. Na taj nain kroz potroa sve vreme
protie struja, koja na njemu stvara pad napona kao na sl. 8.26b. Na sl. 8.27 je prikazano neko-
liko razliitih Grecovih spojeva, na kojima se vidi gde se prikljuuje naizmenini napon, a sa
kojih izvoda se uzima + i ispravljenog napona (to je, takoe, naznaeno i na sl. 8.26).
Do sada je bilo rei o nainima ispravljanja napona. Meutim, tako dobijeni su i kod pu-
notalasnog (sl.8. 28b), a posebno kod polutalasnog ispravljanja (sl. 8.28a), takvi da su talasni ob-
lici napona na izlazu neprihvatljivi za praktinu primenu (na primer kod audio ureaja bi bio ja-
ko ujan nedozvoljeni brum). Stoga se posle ispravljakih dioda koristi kondenzator velike kapa-
citivnosti (obino su to elektrolitski kondenzatori kapacitivnosti nekoliko stotina F), sl. 8.29.
146
Sl. 8.26. Ispravljanje napona pomou etiri diode (Grecov spoj).
Sl. 8.27. Nekoliko razliitih Grecovih spojeva.
Uloga kondenzatora (sl. 8.28 i sl. 8.29) se ogleda u sledeem: u prvom trenutku kada
dioda provede, kondenzator se napuni (sl. 8.39a) i napon na njemu je VC = Vp(in) 0,7 V, gde je
Vp(in) maksimalna vrednost ulaznog napona. Odmah nakon toga kondenzator poinje da se prazni
preko potroaa RL (sl. 8.29b) i to pranjenje kondenzatora traje sve do trenutka kada, pri pozi-
tivnoj poluperiodi naizmeninog napona, struja koja protie kroz diodu ne dopuni kondenzator
(na sl. 8.29c je to trenutak koji je iznad t2). Na taj nain se dobija prilino ispeglan napon na
potroau, sl. 8.28. Oigledno je, stoga, da e to peglanje ispravljenog napona biti bolje ukoli-
ko je kapacitivnost kondenzatora vea, s obzirom da je vreme pranjena kondenzatora srazmerno
kapacitivnosti istog.
Na kraju, na sl. 8.30 dat je izgled jednog ispravljaa sa etiri diode, a na sl. 8.31 je prika-
zano nekoliko vrsta dioda, sa naznakom na kom je izvodu katoda.
147
Sl. 8.28.Naponski oblici ispravljenog napona bez kondenzatora i sa kondenzatorom.
Sl. 8.29 Uz objanjenje uloge kondenzatora u ispravljaima.
148
Sl. 8.30. Izgled jednog ispravljaa sa etiri diode.
Sl. 8.31. Razliite vrste dioda.
149
9. BIPOLARNI TRANZISTORI
9.1. VRSTE TRANZISTORA
Sama re tranzistor nastala je saimanjem rei TRANSfer-resISTOR, koje na engles-
kom jeziku znae prenosna otpornost. Moe se, s pravom, rei da je elektronska revolucija
zapoela pronalaskom bipolarnih tranzistora 1947. godine. Do tada su se poluprovodnici koristili
samo za termistore, fotodiode i ispravljae. 1949. godine okli je publikovao teoriju o radu polu-
provodnikih dioda i bipolarnih tranzistora i od tog trenutka poinje nagli razvoj kako teorijskih
istraivanja, tako i industrijske proizvodnje ovih komponenata. Zahvaljujui intenzivnom napret-
ku tehnologije poveala se, znatno, pouzdanost, snaga, granina uestanost i primena bipolarnih
tranzistora.
Za razliku od dioda, koje su, kao to je pokazano, elektronske komponente sa dva izvoda,
tranzistori su komponente sa tri izvoda, sl. 9.1. Ti izvodi su kontaktirani za tri oblasti: oblast
tranzistora iz koje se injektuju nosioci naelektrisanja zove se emitor, oblast u koju se injektuju ti
nosioci je baza, a oblast u koju ekstrakcijom iz baze dolaze nosioci zove se kolektor, sl. 9.1a.
Osnovna karateristika bipolarnog tranzistora jeste da je to komponenta koja ima pojaavaka
svojstva, tj. da signal koji se dovodi na ulaz tranzistora biva pojaan na njegovom izlazu, to je
figurativno prikazano na sl. 9.1b.
Sl. 9.1. Bipolarni tranzistor komponenta sa tri izvoda (a) i kao pojaavaka kompoenta (b).
Bipolarni tranzistor se sastoji od dva p-n spoja, sl. 9.2. Meutim, naglaava se da ti p-n
spojevi moraju da budu u jednoj poluprovodnikoj komponenti tranzistor se ne moe, dakle,
dobiti jednostavnim spajanjem dva p-n spoja (dve diode); osnovno svojstvo tranzistora sastoji se
ba u tome da izmeu tih p-n spojeva postoji uzajamno dejstvo strujom jednog spoja moe se
upravljati struja drugog p-n spoja. Kao to se sa sl. 9.2 vidi, u zavisnosti od toga koga je tipa
srednja oblast, koja se, kao to je reeno, zove baza, razlikuju se p-n-p (nadalje e se oznaavati
sa PNP) i n-p-n (NPN) tranzistori.
150
Sl. 9.2. Ilustrativni i ematski prikazi PNP (a) i NPN (b) tranzistora.
Sl. 9.3. NPN tranzistor kao diskretna komponena i u okviru integrisanih kola.
151
Sl. 9.4. Kvalitativna predstava preseka epitaksijalnog dvostruko difundovanog
PNP tranzistora male snage
Bipolarni tranzistori male i srednje snage se najee dobijaju planarnom tehnologijom,

pri emu se emitorski i kolektorski spoj oformljuju dvostrukom difuzijom primesa u epitaksijalni
sloj. Na sl. 9.3 prikazan je NPN, a na sl. 9.4 PNP planarni tranzistor. Epitaksijalni sloj je sa
niskom koncentracijom primesa i prvenstveno slui za poveanje probojnog napona spoja kolek-
tor-baza (ceo kolektor ne moe biti sa niskom koncentracijom primesa, jer bi, u tom sluaju, bila
velika redna otpornost kolektora, a time i veliki pad napona na toj otpornosti; sa druge strane,
velika koncentracija primesa u kolektoru dovela bi do niskog probojnog napona kolektorskog
spoja, to bi bilo neodrivo za normalan rad tranzistora).
Sl. 9.5. Fotografija diskretnog tranzistorskog ipa (a) i njegova montaa u metalno kuite TO 18.
152
Ne ulazei u tehnoloki niz proizvodnje bipolarnih tranzistora, na sl. 9.3 su prikazana dva
NPN tranzistora: jedan se odnosi na diskretnu komponentu (svaki tranzistor je pojedinana kom-
ponenta), a drugi je izdvojen iz jednog integrisanog kola. Osnovna razlika izmeu njih ogleda se
u tome to se kod diskretnog tranzistora kolektorski i emitorski kontakt nalaze sa suprotnih stra-
na, a kod tranzistora u integrisanim kolima su svi kontakti sa jedne strane, sl. 9.3. Stoga kolek-
torska struja kod diskretnog tranzistora protie vertikalno kroz komponentu, a kod integrisanog
tranzistora ona je najveim delom planparalelna.
Slika 9.5 prikazuje fotografiju ipa jednog diskretnog bipolarnog tranzistora i figurativni
odnos veliina samoga ipa i kuita.
Kako tranzistor ima tri izvoda, to se on moe ukljuiti na 6 razliitih naina u dva elek-
trina kola, pri emu je jedan kraj zajedniki za oba kola. Meutim, u praksi se koriste samo 3
naina vezivanja; to su: spoj sa uzemljenom (zajednikom) bazom (sl. 9.6a), spoj sa uzemljenim
emitorom (sl. 9.6b) i spoj sa uzemljenim kolektorom (sl. 9.6c).
Sl. 9.6. Tri naina vezivanja PNP tranzistora: (a) sa uzemljenom bazom; (b) sa uzemljenim emi-
torom; (c) sa uzemljenim kolektorom.
9.1.1. Nain rada tranzistora

U normalnom radnom reimu (aktivnom reimu) jedan p-n spoj tranzistora je direktno, a
drugi inverzno polarisan; direktno polarisan spoj jeste emitor-bazni (ili, kratko, emitorski)
spoj, a inverzno polarisan spoj je kolektor-bazni (kolektorski) spoj. Prema tome, kod PNP
tranzistora pozitivan pol izvora prikljuen je za emitor preko metalnog kontakta, a negativan za
bazu; pozitivan pol kolektorskog izvora prikljuen je na bazu, a negativan na kolektor (sl. 9.2a).
Kod NPN tranzistora je obrnuto (sl. 9.2b).
Na sl. 9.7 figurativno je prikazano kako se kreu elektroni kod normalno polarisanog
NPN tranzistora sa uzemljenim emitorom, sa naznakom smerova emitorske IE, bazne IB i kolek-
torske struje IC, s napomenom da su smerovi struja suprotni od smera kretanja elektrona.
Rad bipolarnog tranzistora bie objanjen na primeru PNP tranzistora sa uzemljenom ba-
zom. Analiza, meutim, ostaje nepromenjena i kod NPN tranzistora, sa napomenom da kod nje-
ga naponi i struje menjaju smerove, a upljine i elektroni uloge. Dakle, sve ono to se kod PNP
tranzistora odnosi na upljine, kod NPN tranzistora odnosi se na elektrone, i obratno.
Na sl. 9.8 ematski su prikazane komponente struja u PNP tranzistoru (u preseku AA' na
sl. 9.4). Naime, usled direktne polarizacije emitorskog spoja upljine se, koje su u emitoru ve-
inski nosioci naelektrisanja, iz emitora injektuju u podruje baze; ove injektovane upljine ine
emitorsku struju upljina IpE. Sa druge strane, iz baze, gde su veinski nosioci, elektroni prelaze
153
u podruje emitora, inei emitorsku struju elektrona InE. Kako su elektroni i upljine nosioci
naelektrisanja suprotnog znaka, to je i emitorska struja elektrona InE istog smera kao i emitorska
struja upljina IpE, tako da je emitorska struja IE jednaka zbiru ovih dveju struja. Meutim, samo
komponenta struje koja nastaje prolaskom upljina kroz emitorski spoj doprinosi pojaavakom
svojstvu tranzistora, s obzirom da ona efektivno uestvuje u formiranju kolektorske struje. Otuda
se u konstrukciji tranzistora tei da se emitorska struja elektrona InE kroz emitorski spoj to vie
smanji (ne treba zaboraviti da je ovde re o PNP tranzistoru; kod NPN tranzistora je upravo obr-
nuto). Prema tome, emitorska struja IE je:
I E = I pE + I nE . (9.1)
Sl. 9.7. Figurativna predstava kretanja elektrona u normalno polarisanom NPN tranzistoru.
154
Sl. 9.8. Komponente struja u PNP tranzistoru u aktivnom reimu rada.
Injektovane upljine e se, usled njihove poveane koncentracije u bazi uz emitorski spoj,
difuziono kretati kroz bazu ka kolektorskom spoju, sa napomenom da su u bazi upljine manjin-
ski nosioci naelektrisanja. Kreui se ka kolektoru, jedan manji broj upljina se rekombinuje sa
elektronima u bazi; ta komponenta struje upljina obeleena je sa IpB = InB (sl. 9.8). Meutim,
daleko najvei broj upljina injektovanih iz emitora stie do prelazne oblasti kolektorskog spoja.
Kako je, zbog inverzne polarizacije, elektrino polje u prelaznoj oblasti kolektorskog spoja tak-
vog smera da pomae kretanje manjinskih nosilaca naelektrisanja (u ovom sluaju upljina), to,
praktino, sve upljine koje su stigle do kolektorskog spoja prelaze u kolektor, inei kolektorsku
struju upljina IpC. Kroz inverzno polarisani kolektorski spoj protie i struja ICB0, koja se sastoji
od tri komponente: inverzne struje upljina kao posledice prelaska ravnotenih manjinskih
nosilaca (pno) iz baze, struje zasienja elektrona koja potie od ravnotenih manjinskih nosilaca
u kolektoru (npo) i generaciono-rekombinacione struje usled generacije nosilaca u kolektorskoj
prelaznoj oblasti, ali, zbog toga to je ICB0 << IpC, o struji ICB0 nadalje se nee voditi rauna.
Prema tome, bazna struja IB e biti:
I B = I pB + I nE , (9.2)
a kolektorska struja IC je:
I C I pC . (9.3)
Na osnovu sl. 9.8 moe se, takoe, videti da je:
I E = I B + IC . (9.4)
Dakle, iz jedn. (9.1) do (9.4) sledi:
155
I B = I E I C = I pE + I nE I pC . (9.5)
Bazna struja je vrlo priblino jednaka razlici emitorske struje upljina IpE i kolektorske
struje upljina IpC, s obzirom da je struja InE znatno manja u poreenju sa strujama IpE i IpC.
Kolektorska struja upljina IpC je vrlo malo manja od emitorske struje upljina IpE, jer se samo
neznatan broj upljina gubi rekombinacijom sa elektronima u toku difuzionog kretanja kroz ba-
zu; stoga je bazna struja relativno mala. (Napominje se da je bazna struja vrlo mala samo kod
tranzistora male snage; naprotiv, kod tranzistora velike snage bazna struja moe iznositi i neko-
liko ampera, to je osnovni nedostatak takvih bipolarnih tranzistora snage.)
Ako se na red sa izvorom VBE (sl. 9.2a) prikljui izvor naizmenine struje, polarizacija
emitorskog spoja menjae se u ritmu pobudnog naizmeninog napona. Oigledno je da e se u
istom ritmu menjati i emitorska i kolektorska struja i da e, s obzirom na reeno, i naizmenine
komponente emitorske i kolektorske struje biti priblino jednake. Sa druge strane, otpornost
direktno polarisanog emitorskog spoja je mala, dok je otpornost inverzno polarisanog kolektor-
skog spoja vrlo velika. Drugim reima, tranzistor se ponaa u odnosu na spoljanji kolektorski
prikljuak kao izvor konstantne struje. To omoguava da se na otporniku vezanom na red u
kolektorskom kolu dobije znatno vea snaga i napon od onih kojim se tranzistor pobuuje, to je
osnovno svojstvo tranzistora (tranzistorski efekat) kao pojaavake komponente. Napominje se
da je do sada bilo rei o tranzistoru sa uzemljenom bazom, koji ne moe da slui kao strujni
pojaava, jer je kolektorska struja manja od emitorske; meutim, kao to e kasnije biti poka-
zano, znatno strujno pojaanje se moe dobiti kod tranzistora sa uzemljenim emitorom.
9.2. KOEFICIJENT STRUJNOG POJAANJA

Odnos izlazne i ulazne struje zove se koeficijent strujnog pojaanja. Tako, kod tranzistora
sa uzemljenom bazom, koeficijent strujnog pojaanja je:
IC
= za VEB = const. (9.6)
IE
Ovde, zapravo, nije re o strujnom pojaanju, s obzirom da je < 1; ovaj termin koe-
ficijent strujnog pojaanja ima pravo znaenje kod tranzistora sa uzemljenim emitorom, gde
predstavlja odnos kolektorske (izlazne) i bazne (ulazne) struje:
IC
= za VBE = const. (9.7)
IB
Veza izmeu koeficijenata strujnih pojaanja tranzistora sa uzemljenim emitorom i

uzemljenom bazom dobija se iz (9.6) i (9.7):
IC
I IC IE
= C = = = . (9.8)
I B I E IC IC 1
1
IE
Iz poslednjeg izraza, takoe, sledi:
156

= . (9.9)
1+
Treba napomenuti da su vrednosti koeficijenta strujnog pojaanja kod svih tipova tranzis-
tora 1 (ali uvek < 1), a vrednosti koeficijenta strujnog pojaanja kod tranzistora male
snage su 100300, dok su kod tranzistora snage te vrednosti znatno manje ( 2060). Koe-
ficijent strujnog pojaanja se esto obeleava i sa hFE.
9.3. STATIKE STRUJNO-NAPONSKE KARAKTERISTIKE
9.3.1. Statike strujno-naponske karakteristike

tranzistora sa uzemljenom bazom
Ulazna strujno-naponska karakteristika tranzistora sa uzemljenom bazom jeste zavis-
nost ulazne struje IE od ulaznog napona VEB. Ova zavisnost je prikazana na sl. 9.9a. Vidi se da za
VCB = 0 i VCB < 0 karakteristika odgovara strujno-naponskoj karakteristici emitorskog p-n spoja.
Kada tranzistor radi u zasienju kada je i kolektorski spoj direktno polarisan (VCB > 0), pri
istom emitor-baznom naponu emitorska struja je manja nego u sluaju kada je VCB < 0. Takoe,
sa sl. 9.10a vidi se da pri naponima VEB < VEB(0) (kada je IE = 0), emitorska struja menja znak, tj.
tee u suprotnom smeru od smera koji ima kada tranzistor radi u aktivnom reimu.
Izlazne karakteristike tranzistora sa uzemljenom bazom predstavljaju zavisnost izlazne
struje IC od izlaznog napona VCB pri konstantnoj ulaznoj struji IE. Uobiajeno je da se sa pozi-
tivnim predznakom uzimaju struje koje utiu u tranzistor, iako kod PNP tranzistora bazna i
kolektorska struja istiu iz tranzistora. U skladu sa takvim oznaavanjem, na sl. 9.9b su prika-
zane izlazne karakteristike PNP tranzistora (zato je kolektorska struja IC sa negativnim pred-
znakom; kod NPN tranzistora su i IC i VCB sa pozitivnim znakom). Vidi se da je za IE = 0
kolektorska struja jednaka struji kolektorskog p-n spoja (pri otvorenom ulazu) i da su te karak-
teristike, praktino, pomerene za IE kada je IE > 0.
9.3.2. Statike strujno-naponske karakteristike

tranzistora sa uzemljenim emitorom
Ulazna karakteristika tranzistora sa uzemljenim emitorom jeste zavisnost ulazne struje
IB od ulaznog napona VBE, sl. 9.10. Treba naglasiti da je u aktivnom reimu rada VBE > 0 i kada
je IB = 0, s obzirom da i tada kroz emitorski spoj protie inverzna struja kolektorskog spoja,
usled ega na emitorskom spoju postoji izvestan napon VBE(0) (sl. 9.10). Ako je, pak, VCE = 0
(VCB = VEB) napon VBE je, pri datoj baznoj struji, manji nego u sluaju VCE << 0, to je posledica
direktno polarisanog kolektorskog spoja, te se struja raspodeljuje izmeu emitorskog i
kolektorskog spoja.
Izlazne karakteristike tranzistora sa uzemljenim emitorom predstavljaju zavisnost izlaz-
ne struje IC od izlaznog napona VCE pri konstantnoj ulaznoj struji IB, sl. 9.11. Vidi se da i kada je
bazna struja jednaka nuli, izmeu kolektora i emitora protie struja ICE0; ova struja praktino je
jednaka ICE0 = (1 + )ICB0, pri emu je, kao to je pomenuto, ICB0 struja inverzno polarisanog ko-
157
lektorskog p-n spoja. Sa sl. 9.11 se, takoe, vidi da su, desno od isprekidane krive (aktivna ob-
last emitorski spoj direktno a kolektorski spoj inverzno polarisan), izlazne karakteristike para-
lelne (to je samo teorijski, dok su u praksi one nagnute sa pozitivnim koeficijentom nagiba, sl.
9.12); isprekidana kriva oznaava granicu oblasti zasienja (saturacije) i njome je odreen
napon zasienja VCEsat izmeu emitora i kolektora nakon kojeg je kolektorska struja praktino
konstantna i jednaka ICsat. Levo od isprekidane krive (za napone 0 < VCE VCEsat i struje 0 < IC <
ICsat) je i kolektorski p-n spoj direkno polarisan i ta oblast se ne koristi u pojaavake svrhe.
Sl. 9.9. Statike strujno-naponske karakteristike PNP tranzistora sa uzemljenom bazom:

(a) ulazne i (b) izlazne karakteristike.
158
Sl. 9.10. Ulazne karakteristike PNP tranzistora sa uzemljenim emitorom.
Sl. 9.11. Izlazne karakteristike PNP tranzistora sa uzemljenim emitorom.
Napon izmeu kolektora i emitora se ne moe neogranieno poveavati, s obzirom da je,

u normalnom reimu rada, kolektorski spoj inverzno polarisan, te e u jednom trenutku u njemu,
kao kod inverzno polarisane diode (odeljak 8.3, sl. 8.18), nastati proboj VCB0. Meutim, kod tran-
zistora sa uzemljenim emitorom, pored probojnog napona VCB0, postoji i proboj izmeu
kolektora i emitora VCE0. Ne ulazei u analizu i mehanazme nastanka proboja VCE0, ovde su samo
na sl. 9.13 prikazane izlazne karakteristike tranzistora u oblasti proboja. Napominje sa da je
napon proboja VCE0 izmeu kolektora i emitora manji od probojnog napona kolektor-baznog
spoja VCB0, a moe se priblino odrediti iz izraza:
159
VCB 0
VCE 0 = , (9.10)
(1 + )1 / m
gde je m koeficijent ija je vrednost, zavisno od koncentracoje primesa u bazi, 2 m 4.
Sl. 9.12. Realne izlazne karakteristike NPN tranzistora sa uzemljenim emitorom.
Sl. 9.13. Izlazne karakteristike NPN tranzistora sa uzemljenim emitorom u oblasti proboja.
160
9.4. PRIMENA TRANZISTORA
Osnovna primena tranzistora je kao pojaavake komponente u pojaavakim kolima i
prekidake komponente u prekidakim kolima.
Da je tranzistor sa uzemljenim emitorom elektronska komponenta koja ima pojaavake
osobine vidi se sa sl. 9.14. Naime, na sl. 9.14 je prikazan NPN tranzistor sa koeficijentom struj-
nog pojaanja = 200. Izvorima napajanja VCC (u primeru na sl. 9.14 je VCC = 6,5 V) i VBB
obezbeuju se potrebni naponi za rad tranzistora u aktivnom reimu: izborom vrednosti ot-
pornosti otpornika RB podeava se napon izmeu baze i emitora (VBE 0,7 V, kojim se osigurava
bazna struja IB = 40 A), a vrednou otpornosti otpornika RC definie se tkzv. radna prava.
Naime, sa sl. 9.14a je VCE = VCC RC I C , odakle je:
VCC 1
IC = VCE . (9.11)
RC RC
Sl. 9.14. Uz objanjenje primene tranzistora kao pojaavake elektronske komponente.
161
Poslednji izraz (IC = f(VCE)) u koordinatnom sistemu IC VCE, u kojem su i izlazne karak-
teristike tranzistora, predstavlja radnu pravu, sl. 9.14b (za primer na sl. 9.14, ako se eli da u
radnoj taki M, u kojoj je bazna struja IB = 40 A, kolektorska struja pri naponu VCE = 3,5 V bu-
de IC = 8 mA, iz (9.11) se dobija da otpornost otpornika RC iznosi RC = 375 ).
Kada se na bazu dovede i naizmenini signal Vin (sl. 9.14a), jednosmernoj baznoj struji IB
se superponira naizmenina komponenta ib(t) = Ibmsin(t) (u primeru na sl. 9.14 je amplituda
naizmenine bazne struje Ibm = 35 A). Pri pozitivnoj poluperiodi naizmeninog signala pove-
ava se i kolektorska struja (od take M u levo po radnoj pravoj, sl. 9.14b; za primer na sl. 9.14
pri maksimalnoj vrednosti Ibm = 35 A promena kolektorske struje je do take A, u kojoj je Icm =
Ibm = 200 35 A = 7 mA, odnosno u taki A kolektorska struja je ICA = ICM + Icm = 8 + 7 = 15
mA). Isto tako, pri negativnoj promeni naizmenine komponente bazne struje, kolektorska struja
se po radnoj pravoj od jednosmerne radne take M smanjuje u desno (za primer na sl. 9.14
promena kolektorske struje je do take B, u kojoj je kolektorska struja je ICB = ICM Icm = 8 7
= 1 mA). Dakle, ako je promena bazne struje IB, promena kolektorske struje je IC = IB (za
primer na sl. 9.14 je IB = 70 A, tako da je IC = 20070 A = 14 mA). Drugim reima, malom
promenom ulazne struje mogue je ostvariti relativno veliku promenu izlazne struje, koja na
otporniku RC stvara pad napona koji se dalje, na isti nain, moe poveavati; treba napomenuti
da je naizmenina komponenta napona na otporniku RC, usled vc(t) = RCic(t) = RCib(t) =
RCIbmsin(t) u protivfazi sa baznom strujom kad se bazna struja poveava napon na kolek-
toru se smanjuje i obrnuto (kao to je i naznaeno na sl. 9.14a).
Kao to je i pokazano na sl. 9.14, radna taka na radnoj pravoj pomerala se do dake A,
odnosno do take B. To je, stoga, da ne bi dolo do deformacije signala. Naime, na sl. 9.15a su
ponovo prikazane izlazne karakteristike jednog NPN tranzistora sa naznakom dozvoljenog po-
meranja radne take Q po radnoj pravoj; na pomenutoj slici ta oblast se kree od saturacije (za
dati primer je VCEsat 0,5 V) do prekidne oblasti, kada je IB = 0 (VCEprekid 9,5 V na sl. 9.15a). U
suprotnom, ako je ulazni signal relativno veliki, odnosno takav da radna taka na radnoj pravoj
zalazi bilo u oblast saturacije, bilo u prekidnu oblast, dolazi do deformacije izlaznog signala
bilo u pogledu izlazne struje Ic, bilo u pogledu izlaznog napona Vce, sl. 9.15b (napominje se de su
jednosmerne komponente napona i struje oznaene u indeksu velikim, a naizmenine malim slo-
vom).
Sl. 9.15. Dozvoljeno pomeranje radne take po radnoj pravoj (a) i

deformacija izlaznog signala kada radna taka zalazi i u oblast saturacije
i u prekidnu oblast (b) (ovde je ak uzeto da je u pitanju idealni tranzistor sa VCEsat = 0 V).
162
Kao to je reeno, pored primene kao pojaavake komponente u pojaavakim kolima,
tranzistor se koristi i kao prekidaka komponenta u prekidakim kolima. Naime, ako se tranzi-
stor dovede u stanje zakoenja, a to je kad je bazna struja IB = 0 (tada radna prava preseca u I-V
karakteristikama pravu koja se odnosi na IB = 0, sl. 9.15a), tada tranzistor ne vodi (kroz njega ne
protie struja, tj. IC = 0) i moe se tretirati kao otvoren prekida, sl. 9.16a. Napon na kolektoru,
koji je tada priblino jednak naponu napajanja VCC moe se tretirati kao logika jedinica (1),
to se moe da iskoristi u digitalnim logikim kolima. Naprotiv, kada napon izmeu kolektora i
emitora opadne na VCEsat (kae se tranzistor je u zasienju), kroz njega protie maksimalna
kolektorska struja, tj. IC(sat), i tranzistor se tada ponaa kao zatvoren prekida, sl. 9.16b; u tom
sluaju napon izmeu kolektora i emitora je majmanji i to moe da bude logika nula u digital-
nim kolima.
Sl. 9.16. Tranzistor kao prekidaka komponenta.
9.5. ELEKTRINI MODEL TRANZISTORA

U cilju uspenog projektovanja nekog elektronskog kola (ukljuujui i integrisana kola),
pogodno je raspolagati elektrinim modelom tranzistora koji se koriste u razliitim simulatorima
rada elektonskih kola. Osnovni model se zove Ebers-Molov model, koji su Ebers i Mol razvili na
bazi poznavanja fizike rada samih bipolarnih tranzistora. Na sl. 9.17 prikazan je uproen ovaj
elektrini model i to samo kada je emitorski spoj direktno, a kolektorski inverzno polarisan.
Na osnovu dosadanjeg izlaganja moe se, u normalnom reimu rada, kada je emitorski
spoj direktno a kolektorski spoj inverzno polarisan, spoj kolektor-baza predstaviti strujnim izvo-
rom koji zavisi od vrednosti napona VBE izmau baze i emitora. S obzirom da je IC = IE + IB IE,
a struja IE je struja direktno polarisanog emitorkog spoja, to se na osnovu (8.4) moe napisati:
VBE
I C I E I s exp . (9.12)
UT
Stoga se izrazom (9.12) moe predstaviti strujni izvor kolektorskog spoja, to je prikazano na sl.
9.17.
Sa druge strane, direktno polarisani emitor-bazni spoj se na uproenom Ebers-Molovom
modelu predstavlja diodom (sl. 9.17), sa strujom IB = IC/(+1).
163
Sl. 9.16. Uproeni Ebers-Molov model NPN i PNP tranzistora za rad u aktivnom reimu.
9.6. TESTIRANJE ISPRAVNOSTI TRANZISTORA

S obzirom da se tranzistor, praktino, sastoji od dva p-n spoja, testiranje njegove isprav-
nosti je slino testiranju ispravnosti dioda (odeljak 8.2.1 i slike 8.16 i 8.17). Stoga je na sl. 9.17
prikazan samo jedan od naina ispitivanja emitorskog i kolektorskog spoja digitalnim multime-
trom (sa napomenom da preklopnik treba prebaciti u poloaj koji oznaava merenje dioda).
(a) (b) (c) (d)

Sl. 9.17. Testiranje ispravnosti dioda:
(a) direktno polarisan emitor-bazni spoj; (b) inverzno polarisan emitor-bazni spoj;
(c) direktno polarisan kolektor-bazni spoj; (d) inverzno polarisan kolektor-bazni spoj.
164
10. MOS TRANZISTORI
Do sada je sve vreme bilo rei o bipolarnim komponentama, tj. o komponentama u koji-
ma u procesu provoenja elektrine struje uestvuju obe vrste nosilaca naelektrisanja (i elektroni
i upljine). Za razliku od njih, MOS tranzistori su unipolarne komponente kod kojih u pro-
voenju elektrine struje u normalnom radnom reimu uestvuje samo jedna vrsta nosilaca nae-
lektrisanja. Odmah treba napomenuti da je najvea prednost MOS tranzistora u tome to su to
naponski kontrolisane komponente, za razliku od strujno kontrolisanih (strujom baze) bipolar-
nih tranzistora. Ovo je od veoma bitnog znaaja, posebno u komponentama snage.
MOS (Metal-Oxide-Semicoductor) tranzistori spadaju u grupu tranzistora sa efektom po-
lja, takozvane FET (Field-Effect Transistor), tako da se mogu sresti i pod nazivom MOSFET.
Zanimljivo je da je princip rada tranzistora sa efektom polja predloen jo 1932. godine, ali je
prve zamisli o izradi ovih tranzistora bilo mogue ostvariti tek kada se ovladalo planarnom teh-
nologijom. Tek 1960. godine je proizveden prvi silicijumski MOS tranzistor korienjem procesa
termike oksidacije. Nakon toga MOS tranzistor je postao osnovna komponenta integrisanih kola
vrlo visoke gustine pakovanja, kao i procesora i memorija.
Sl. 10.1. Principijelna struktura MOS tranzistora
Na sl. 10.1 je predstavljena principijelna struktura MOS tranzistora. Praktino, u silici-

jumski supstrat (osnovu) koji, kao to e kasnije biti pokazano, moe biti ili p- ili n-tipa, difun-
duju se dve oblasti suprotnog tipa provodnosti (u p-supstrat difunduju se n-oblasti, a u n-supstrat
p-oblasti). Prva difundovana oblast zove se sors, a druga drejn. Na povrini supstrata naini se
165
vrlo tanak sloj oksida (SiO2, Si3N4), a preko njega (ali obavezno da zahvata oblasti sorsa i
drejna) sloj metala koji slui kao upravljaka elektroda. Ova upravljaka elektroda zove se gejt.
10.1. VRSTE MOS TRANZISTORA

Kao to je reeno, u procesu provoenja elektrine struje u normalnom radnom reimu
uestvuje samo jedna vrsta nosilaca nelektrisanja. U zavisnosti od toga koja vrsta nosilaca ue-
stvuje u provoenju, MOS tranzistori se dele na n-kanalne i p-kanalne, sl. 10.2.
Sl. 10.2. Osnovne strukture n-kanalnih i p-kanalnih tranzistora.
Ve u samom nazivu o tipu MOS tranzistora pominje se kanalni, to ukazuje na to da u

strukturi MOS tranzistora postoji neki kanal. Naime, re je o kanalu koji se formira u supstratu
izmeu sorsa i drejna, i koji, praktino, uspostavlja elektrinu vezu izmeu te dve oblasti, odno-
sno omoguava da protie elektrina struja izmeu sorsa i drejna, sl. 10.3 i sl. 10.4.
Sl. 10.3. n-kanalni MOS tranzistor pre (a) i posle (b) uspostavljanja (indukovanja) kanala.
166
Sl. 10.4. p-kamalni MOS tranzistor pre (a) i posle (b) uspostavljanja (indukovanja) kanala.
Kanal moe biti ugraen (na primer difuzijom ili implantacijom primesa) ili, to je mno-
go ei sluaj, indukovan. Kod MOS tranzistora sa indukovanim kanalom, kanal se formira
elektrinim poljem koje nastaje usled primene odgovarajueg napona na gejtu.
MOS tranzistor je osnovna komponenta integrisanih kola (IC) vrlo visoke gustine pako-
vanja. U praktinim izvoenjima danas dominiraju CMOS IC. CMOS kao osnovnu jedinicu
imaju komplementarni par sastavljen od po jednog n- kanalnog i p-kanalnog MOS tranzistora.
Na sl. 10.5 prikazano je oznaavanje MOS tranzistora u elektrinim emama. Napominje
se da se srednje oznake na pomenutoj slici koriste kod tranzistora kod kojih supstrat nije na po-
tencijalu sorsa, ve se on prikljuuje na poseban izvor napona.
Sl. 10.5. Oznaavanje MOS tranzistora.
10.1.1. Osnovni principi rada MOS tranzistora

Nadalje e biti rei samo o najee korienim MOS tranzistorima, a to su MOS tranzi-
stori sa indukovanim kanalom i sa uzemljenim sorsom i supstratom (supstrat i sors su kratko-
spojeni). Takvi tranzistori, sa potrebnim polarizacijama, prikazani su na slikama 10.3 i 10.4.
167
Sl. 10.6. n-kanalni MOS tranzistor sa relevantnim podacima za analizu njegovog rada.
Sl. 10.7. Prikljuivanjem pozitivnog napona na gejt u odnosu na p-supstrat indukuje se n-kanal.
Kao to je ve pomenuto, na povrini, izmeu sorsa i drejna a jednim delom i iznad njih,
nalazi se tanak sloj oksida (SiO2, Si3N4), koji slui kao dielektrik, sl. 10.6. Preko oksida nalazi se
gejt (upravljaka elektroda), kojeg ini tanak sloj aluminijuma (kod MOS tranzistora sa alumini-
jumskim gejtom) ili polikristalnog silicijuma (kod tranzistora sa polisilicijumskim gejtom). S
obzirom da su i sors i drejn oblasti suprotne provodnosti od provodnosti supstrata, to se u oblasti
sorsa i drejna u supstratu (zato to je koncentracija primesa u supstratu znatno nia nego u sorsu i
drejnu) formiraju prelazne oblasti p-n spojeva, koje se, zbog toga to su sors i drejn veoma blizu
(L je reda m), spajaju (sl. 10.7). U daljem razmatranju naina rada MOS tranzistora ove pre-
lazne oblasti se nee analizirati, a bie pomenute samo kada je to neophodno.
168
MOS tranzistori koriste efekat poprenog polja (normalnog na povrinu), kojim se ostva-
ruje inverzija tipa provodnosti povrinskog sloja poluprovodnika ispod gejta i na taj nain formi-
ra kanal izmeu sorsa i drejna. Naime, ako se, na primer, kod n-kanalnog MOS tranzistora gejt
prikljui na pozitivan napon u odnosu na p-supstrat, pri emu su i sors i drejn uzemljeni, sl. 10.7,
u supstratu e se neposredno ispod oksida na njegovoj povri, usled Kulonove sile, indukovati
negativno naelektrisanje i to tako to e se upljine iz povrinskog sloja udaljiti i ostaviti nekom-
penzovane negativno naelektrisane akceptorske jone. Poveavanjem pozitivnog napona na gejtu
sve vie se udaljavaju upljine, a iz zapreminskog dela supstrata ka povini kreu manjinski ele-
ktroni sve dok, pri odreenom naponu na gejtu, ne nastupi inverzija tipa provodnosti supstrata.
Drugim reima, pri jednoj vrednosti napona na gejtu, koji se zove napon praga i obeleava sa
VT, povrinski sloj p-supstrata ispod oksida gejta, a izmeu sorsa i drejna, ponaa se kao n-tip
poluprovodnika. Stoga se ta oblast ponaa kao kanal od sorsa do drejna (sors i drejn su istog tipa
provodnosti kao indukovani kanal, sl. 10.7), tj. ako se u tim uslovima dovede pozitivan napon na
drejn u odnosu na sors, elektroni iz sorsa kroz kanal mogu driftovski da dou do drejna, odnosno
u tom sluaju izmeu sorsa i drejna e proticati struja drejna, sl. 10.3. Ukoliko je napon na gejtu
vei, utoliko je jaa inverzija tipa, odnosno utoliko je vei broj elektrona u kanalu. Kada je re
o p-kanalnom MOS tranzistoru inverzija tipa n-supstrata ostvaruje se negativnim naponom na
gejtu u odnosu na supstrat, a u indukovanom kanalu se skupljaju upljine, sl. 10.4.
Kao to je reeno, napon na gejtu VT potreban da se stvori kanal od sorsa do drejna je na-
pon praga. Tano definisanje napona praga je veoma teko. Zbog toga se za napon praga uslovno
moe prihvatiti definicija da je to onaj napon izmeu upravljake elektrode (gejta) i supstrata pri
kome koncentracija manjinskih nosilaca na povrini postaje jednaka koncentraciji veinskih no-
silaca u unutranjosti supstrata.
10.2. IZLAZNE KARAKTERISTIKE MOS TRANZISTORA

Uspostavljanje kanala izmeu sorsa i drejna omoguuje proticanje struje od sorsa do drej-
na kada se prikljui odgovarajui napon na drejn (slike 10.3, 10.4 i 10.8). Izlazne karakteristike
MOS tranzistora predstavljaju zavisnosti struje drejna ID od napona na drejnu VD.
Sl. 10.8. Proticanje struje drejna u n-kanalnom MOS tranzistoru pri malim naponima na drejnu.
169
Pri veoma malim naponina na drejnu kanal se moe predstaviti kao otpornik, tako da je
struja drejna u jednom delu ID-VD karakteristike priblino linearno proporcionalna naponu na
drejnu; to je tkzv. linearna oblast rada MOS tranzistora (sl. 10.10). Nakon linearne oblasti, a pri
naponima |VD| < |VG VT|, struja drejna sporije raste sa poveavanjem napona na drejnu, sl.
10.11. To je, stoga, to se kanal u okolini drejna suava, sl. 10.9a, kao posledica poveavnja
irine prelazne oblasti p-n spoja drejn-supstrat (sl. 10.7), koji je inverzno polarisan. Ta oblast,
zajedno sa linearnom oblau, sve do napona na drejnu |VD| = |VG VT| zove se triodna oblast,
sl. 10.11 (zato to podsea na slinu oblast na strujno-naponskoj karateristici triode).
Sl. 10.9. n-kanalni MOS tranzistor u: (a) linearnoj oblasti rada (mali napon na drejnu);
(b) na ivici zasienja i (c) u zasienju.
Sl. 10.10. ID-VD karakteristike n-kanalnog MOS tranzistora u linearnoj oblasti rada.
Kada u taki y = L debljina kanala postane jednaka nuli, dolazi do prekida kanala (sl.
10.9b) i to se deava pri naponu na drejnu |VD| = |VG VT|. Napon drejna pri kome nastaje prekid
kanala zove se napon zasienja (saturacije) VDsat. Sa daljim poveanjem napona na drejnu (sl.
10.8), tj. pri |VD| > |VG VT|, duina kanala se smanjuje sa L na L' (sl. 10.9c). Na prvi pogled
moe se pomisliti da e struja drejna prestati da tee. Meutim, ona i dalje protie i sa
170
poveanjem napona na drejnu ostaje konstantna, sl. 10.11. To znai da broj nosilaca
naelektrisanja koji sa sorsa stiu u taku y = L' ostaje nepromenjen, a s obzirom da su oni
zahvaeni poljem osiromaene oblasti drejna, bivaju prebaeni u drejn, tako da struja drejna
ostaje, takoe, nepromenjena i konstantna. Zbog toga se oblast rada MOS tranzistora pri
naponima VD VDsat zove oblast zasienja (sl. 10.11).
Sl. 10.11. Izlazne (ID-VD) karakteristike n-kanalnog MOS tranzistora.
Sl. 10.12. Struja izmeu sorsa i drejna ne prestaje i kada se kanal prekine, jer se MOS
tranzistor ponaa kao bipolarni tranzistor u stanju prodiranja.
Da struja drejna ostaje konstantna nakon prekida kanala moe se protumaiti i uz pomo
sl. 10.12. Naime, u pogledu rasporeda p- i n-oblasti n-kanalni MOS odgovara strukturi NPN
tranzistora (za p-kanalni MOS ova struktura e biti PNP tranzistor). Sors sa kanalom je emitor,
drejn je kolektor, a supstrat MOS tranzistora je baza. Prelazna oblast irine w prostire se od drej-
171
na do kanala (sl. 10.12). Ovo u potpunosti odgovara sluaju kod bipolarnog tranzistora kada se
prelazna oblast kolektorskog spoja prostire od kolektora do emitora, pa kod bipolarnog tranzisto-
ra nastaje proboj (dostignut je tkzv. napon prodiranja). Dakle, kod MOS tranzistora proboj na-
staje izmeu kanala i drejna i struju drejna ograniava samo otpornost preostalog dela kanala L'.
Da bismo izveli zavisnost struje drejna od napona na njemu, kao i od napona na gejtu,
posmatrajmo ponovo sliku 10.6, sa naznaenim koordinatnim sistemom na njoj.
Na osnovu izraza za gustinu driftovske struje
J = qnv = qn n K y , (10.1)
struja drejna kroz kanal (pretpostavlja se da koncentracija nosilaca ne zavisi od z) je:

x
I D = J S = q n K yW ndx , (10.2)
0
gde su: S povrina kanala normalna na smer struje, Ky elektrino polje u smeru y, W irina
kanala (sl. 10.6), a n efektivna pokretljivost elektrona u kanalu.
Kako koncentracija elektrona opada sa udaljavanjem od povrine po sloenom zakonu,
integral u (10.2) relativno je teko izraunati. Stoga se vri aproksimacija kojom se vrednost po-
menutog integrala izjednaava sa ukupnom koliinom naelektrisanja po jedinici povrine kanala
(povrine gejta), koja zavisi od elektrinog polja u oksidu:
x
dQ
q ndx = = D x = ox K x , (10.3)
0
dS x
pri emu su: Q koliina naelektrisanja na povrini Sx gejta, Dx dielektrini pomeraj, ox

dielektrina konstanta oksida i Kx elektrino polje normalno na povrinu gejta. Prema tome, iz
(10.2) i (10.3) sledi:
I D = n oxWK x K y . (10.4)
Elektrino polje u pravcu kanala je:
dV y
Ky = . (10.5)
dy
Elektrino polje u oksidu, koje utie na provodnost kanala, zavisi od efektivnog napona
na gejtu (VGeff = VG VT) i potencijala take y na kanalu. Smatrajui da je oksid homogen i bez
prostornog naelektrisanja, debljine tox, bie:
VGeff V y VG VT V y
Kx = = . (10.6)
t ox t ox
Zamenom vrednosti Ky iz (10.5) i Kx iz (10.6) u (10.4), dobija se:
n oxW dV y
ID = (VG VT V y ) . (10.7)
t ox dy
172
Iz jednaine (10.7), razdvajanjem promenljivih i integraljenjem du kanala, sledi:
n oxW
L VD
I D dy = (V G VT V y )dV y . (10.8)
0
t ox 0
Granice za promenljivu y su poetak (0) i kraj (L) kanala, a za promenljivu Vy napon kod
sorsa, Vy(0) = 0, i napon kod drejna, Vy(L) = VD. Posle integraljenja i sreivanja dobija se:
ID =
n oxW
2t ox L
[ ] [
2(VG VT )VD VD2 = n 2(VG VT )VD VD2 , ] (10.9)
gde je
n oxW
n = . (10.10)
2t ox L
Jednaina (10.9) za struju drejna vai samo za |VG VT| |VD|, odnosno u triodnoj oblasti,
sl. 10.11. Za male napone na drejnu drugi lan u srednjim zagradama u (10.9) se moe zane-
mariti u odnosu na prvi lan, pa je tada struja drejna:
VD
I D 2 n (VG VT )V D = , (10.11)
Ron
gde je Ron otpornost kanala pri malim naponima na drejnu:
1
Ron = . (10.12)
2 n (VG VT )
Iz (10.11) vidi se da za vrlo mele napone na drejnu struja drejna linearno zavisi od
napona drejna, tj. tada se MOS tranzistor nalazi u linearnoj (omskoj) oblasti rada, sl. 10.10.
Drugim reima, tada se MOS tranzistor ponaa kao otpornik ija je otpornost kontrolisana
naponom izmeu gejta i sorsa.
Sa druge strane, kada se u (10.9) uvrsti |VG VT| = |VD|, dobija se izraz za struju drejna
I D = n (VG VT ) ,
2
(10.13)
koji reprezentuje parabolu koja deli triodnu oblast od oblasti zasienja na izlaznim karakteristi-
kama MOS tranzistora, sl. 10.11.
Realna struja drejna e, ipak, rasti sa porastom napona na drejnu, posebno kod MOS tran-
zistora sa kratkim kanalima. Ovaj efekat se najjednostavnije moe opisati izrazom:
2 V
I D = n (VG VT ) 1 + D , (10.14)
VA
gde je VA tkzv. Erlijev napon, ije se znaenje vidi na sl. 10.13.
173
Sl. 10.12. Realna struja drejna ipak raste sa porastom napona na drejnu.
Sl. 10.13. Uz objanjenje definicije Erlijevog napona.
10.3. PRENOSNE KARAKTERISTIKE MOS TRANZISTORA

Prenosne karakteristike MOS tranzistora predstavljaju zavisnost struje drejna od napona
na gejtu, tj. ID = f(VG) pri VD = const. One se mogu dobiti iz jedn. (10.9) za triodnu oblast i iz
jedn. (10.12) za oblast zasienja, stavljajui VD = const.
174
Sl. 10.14. Grafika konstrukcija prenosnih karakteristika
n-kanalnog MOS tranzistora iz datih izlaznih karakteristika.
Drugi nain dobijanja prenosnih karakteristika je grafiki, sl. 10.14. Izabere se vrednost
napona VD = const. na izlaznim karakteristikama MOS tranzistora i povue vertikala, koja prese-
ca karakteristike VG = const. u takama A, B, C, D, E. U koordinatnom sistemu ID-VG koji se
nacrta levo od izlaznih karakteristika povuku se vertikalne prave za odgovarajue VG. Horizon-
talne linije povuene iz taaka A, B, C, D i E su odgovarajue struje drejna za napone VG = 3 V,
4 V, 5 V, 6 V i 7 V na sl. 10.14. Na preseku odgovarajuih horizontalnih i vertikalnih linija dobi-
jamo take A', B', C', D' i E', koje lee na prenosnoj karakteristici. Kada ih spojimo, dobijamo
prenosnu karakteristiku MOS tranzistora za izabranu vrednost napona na drejnu. Presek ove ka-
rakteristike sa VG-osom daje vrednost napona praga VT (na sl. 10.14 je VT = 3 V).
175
11. OSNOVI FOTOELEKTRONSKIH
KOMPONENATA
Prilikom osvetljavanja poluprovodnika u njemu se poveava koncentracija i manjinskih i
veinskih nosilaca. To je tkzv. unutranji fotoelektrini efekat. Ovaj efekat se javlja kada usled
energije fotona elektroni prelaze iz valentne zone (sl. 11.1a), ili sa primesnih nivoa, u provodnu
zonu, kao i iz valentne zone na primesne nivoe. Pri tom, energija fotona mora biti vea ili
jednaka aktivacionoj energiji Ea odgovarajueg prelaza, tj.:
hf E a , (11.1)
gde je h = 6,6710-34 Js Plankova konstanta, a f uestanost elektromagnetnog zraenja (svet-

losti).
Iz jedn. (11.1) se dobija maksimalna talasna duina elektromagnetnog talasa koji moe
izazvati fotoefekat, tkzv. crvena granica fotoefekta. Crvena granica unutranjeg fotoefekta u
poluprovodnicima esto se nalazi u oblasti infracrvenog zraenja (max reda nekoliko m), tako
da se neke poluprovodnike komponente mogu koristiti u prijemnicima infracrvenog zraenja.
Osvetljavanje poluprovodnika i poluprovodnikih komponenata ima sledee posledice:
1. Poveava se provodnost poluprovodnika; ovaj fenomen je iskorien kod fotootpornika
(deo 3.5.4).
2. Ukoliko je fotoefekat u blizini p-n spoja, nastaje poveanje inverzne struje p-n spoja.
3. Usled difuzionog kretanja nosilaca, na p-n spoju e se promeniti visina barijere, te os-
vetljen p-n spoj moe sluiti kao izvor elektrine energije.
Obrnuto, prilikom proticanja struje kroz p-n spoj, usled rekombinacije nosilaca moe biti
emitovana svetlost (sl. 11.1b), te takav elemenat moe sluiti kao izvor svetlosti.
Sl. 11.1. Apsorpcija (a) i emisija (b) svetlosti.
176
11.1. FOTODIODA
Na sl. 11.2 prikazan je presek fotodiode. To je planarna dioda kod koje je anodni kontakt
izveden samo na delu difundovane povrine, tako da je samo mali deo povrine p-tipa zaklonjen
kontaktom. Svetlost koja pada na povrinu prodire u silicijum. Struja inverzno polarisane diode
pri osvetljavanju poraste usled poveanja koncentracije manjinskih nosilaca u p-oblasti, koja je
vrlo tanka, i u n-oblasti u dubini ispod prelazne oblasti. Osim toga, inverzna struja poraste i usled
generacije nosilaca u prelaznoj oblasti. Stvoreni elektroni odlaze iz prelazne oblasti u n-oblast, a
upljine u p-oblast.
Sl. 11.2. Fotodioda i njen grafiki simbol.
Sl. 11.3. Statike karakteristike fotodiode.
Ako je koncentracija generisanih nosilaca proporcionalna svetlosnom fluksu koji je

pao na aktivnu povrinu diode, tj. ako je n i p , onda e i poveanje inverzne struje biti
proporcionalno svetlosnom fluksu:
177
I = K , (11.2)
gde se koeficijent K zove osetljivost fotodiode.

Na sl. 11.3 prikazane su strujno-naponske karakteristike fotodiode. One podseaju na
tranzistorske karakteristike bipolarnog tranzistora sa uzemljenom bazom, samo je ovde parame-
tar svetlosni fluks.
11.2. FOTOGENERATOR (SOLARNA ELIJA)

Fotogenerator stvara elektromotornu silu pod uticajem svetlosti. To je, u stvari, fotodioda
koja nije prikljuena na spoljanji izvor napajanja. Naime, pod dejstvom ugraenog polja u pre-
laznoj oblasti p-n spoja, svetlou generisani elektroni iz prelazne i p-oblasti prei e u n-oblast,
a upljine iz prelazne i n-oblasti u p-oblast, sl. 11.4. Usled prelaska ovih nosilaca naruie se rav-
notea, anoda e se naelektrisati pozitivno, a katoda negativno. Ako spojimo krajeve (anodu i
katodu), potei e struja, to znai da se ovakva dioda ponaa kao generator elektrine energije.
Drugim reima, ovakva dioda, koja se esto zove solarna elija, pretvara sunevu energiju u
elektrinu. Paralelnim i rednim vezivanjem veeg broja solarnih elija (sl. 11.4) dobijaju se so-
larni paneli dovoljno velike elektrine energije da mogu da napajaju manje potroae.
Sl. 11.4. Uz opis foto elije i solarnih panela.
Struja nastala usled foftoefekta, a koja protie kroz neki potroa, kao to je reeno kod
fotodiode, proporcionalna je svetlosnom fluksu:
178
I = KF . (11.3)
Ako dioda nije kratkospojena, kontaktna razlika potencijala se mora smanjiti za V0 da bi

potekla i difuziona struja, odnosno da bi ukupna struja bila jednaka nuli.
Na sl. 11.5 prikazana je statika karakteristika fotogeneratora. Karakteristika za neosvet-
ljeni fotogenerator ( = 0) je praktino karakteristika diode. Osvetljavanjem je porasla inverzna
struja, te se karakteristika prosto sputa na nie. Struja je usled svetlosnog fluksa (jedn. (11.3))
jednaka struji kratkog spoja fotogeneratora.
Sl. 11.5. Diodna karakteristika fotogeneratora pomera se na nie za

veliinu struje kroz p-n spoj nastale usled svetlosnog fluksa.
Sl. 11.6. a. Ekvivalentna ema, b. grafiki simbol fotogeneratora.
Na sl. 11.6a prikazana je ekvivalentna ema fotogeneratora. Idealnoj diodi, kroz koju
protie difuziona struja usled promene barijere, na red je vezana otpornost Rs, a paralelno otpor-
nost Rp i strujni generator fotoelektrine struje I. Za razliku od redne otpornosti, paralelna
otpornost Rp se uglavnom moe zanemariti. Ekvivalentna ema fotogeneratora kod koga su za-
nemarene i redna i paralelna otpornost prikazana je na sl. 11.7a, a radni deo njegove statike
karakteristike na sl. 11.7b.
Sa sl. 11.7 vidi se da se fotostruja I deli na jednu kroz otpornost potroaa Rp to je
spoljanja struja I i drugu I1 to je difuziona struja kroz diodu. Reim rada fotogeneratora se
bira tako da korisna snaga bude najvea. Kako je korisna snaga
179
Sl. 11.7. a Uproena ekvivalentna ema fotogeneratora; b strujno-naponska
karakteristika fotogeneratora u aktivnom podruju.
PK = UI , (11.4)
to se Rp tako bira da osenena povrina na sl. 11.7b bude maksimalna.

Danas se intenzivno radi na poboljanju karakteristika fotogeneratora, odnosno solarnih
elija, prvenstveno u cilju poveanja stepena korisnog dejstva. Postignuti su izuzetno dobri re-
zultati, pa se u mnogim delovima sveta, gde ima dosta sunanih dana, velikim solarnim panelima
koji sadre veoma veliki broj solarnih elija, a koji se i kompjuterski upravljaju tako da na njih
uvek pada najvie svetlosti, dobijaju izvori relativno velike elektrine energije, sl. 11.8.
Sl. 11.8. Razliiti primeri primene solarnih elija.
180
11.3. FOTOTRANZISTOR
Dalje poveanje osetljivosti fotoelemenata postie se fototranzistorima. Na sl. 11.9a pri-
kazan je presek fototranzistora. Kao to se vidi, fotodiodi je dodat jo mali emitor, te je dobijen
tranzistor, koji ima veliku povrinu kolektorskog spoja. Svetlost deluje uglavnom na kolektorski
spoj. Ovaj tranzistor je zatvoren u providno kuite kako bi svetlost prodire do tranzistorske
strukture. S obzirom da je najveim delom osvetljen kolektorski p-n spoj, to je kao da je kolek-
tor-baznom spoju paralelno vezana fotodioda, sl. 11.9c, a kako je bazna struja praktino jednaka
fotostruji I, to znai da je kolektorska struja IC = I. Drugim reima, fototranzistor je puta
osetljiviji od fotodiode koja ima istu efektivnu povrinu.
Sl. 11.9. Fototranzistor: a presek; b grafiki simbol;

c fototranzistor je ekvivalentan fotodiodi i obinom bipolarnom tranzistoru.
11.4. SVETLEE DIODE (LED)

Dosad smo analizirali poluprovodnike komponente koje svetlosni signal ili svetlosnu
energiju pretvaraju u elektrini signal, odnosno u elektrinu energiju. Svetlea dioda, sl. 11.10,
koja se znatno ee zove LED (od Light-Emitting Diode) ili fotoluminiscentna dioda, vri
obrnuti proces: elektrinu energiju, odnosno elektrini signal pretvara u svetlosnu energiju.
Na sl. 11.1b prikazan je osnovni princip na kome se zasniva rad svetleih dioda. Naime,
elektron u valentnoj zoni ima manju energiju od elektrona u provodnoj zoni za veliinu irine
zabranjene zone Eg. Ako je mogua rekombinacija direktnim prelaskom elektrona iz provodne u
valentnu zonu, a kod svetleih dioda se biraju upravo takvi poluprovodniki materijali koji to
omoguavaju, oslobaa se tom prilikom elektrina energija ija je vrednost jednaka Eg. Ova
energija se pretvara u foton svetlosti energije hf = Eg.
181
Sl. 11.10. Svetlee diode (LED); anoda je uvek sa duim izvodom.
Da bi poluprovodnik emitovao svetlost, neophodno je da postoji veliki broj pobuenih

elektrona. Pobuivanje elektrona sa nieg na vii energetski nivo najbolje se postie injekcijom,
dakle pomou p-n spoja pri direktnoj polarizaciji, sl. 11.11a. U tom sluaju slobodni elektroni iz
provodne zone n-tipa prelaze u provodnu zonu p-tipa. Poto u p-tipu ima mnogo upljina, po-
rae intenzitet rekombinacije, te e nastati svetlosno zraenje tkzv. spontana emisija. Uko-
liko je struja vea, a to je direktna struja diode IF, bie vea i jaina svetlosti, sl. 11.11b.
Sl. 11.11. a Nain povezivanja luminiscentne diode;

b zavisnost jaine svetlosti od struje direktno polarisane diode.
Od irine zabranjene zone zavisie energija fotona, odnosno talasna duina svetlosti. Pre-
ma tome, izborom poluprovodnika moemo dobiti eljenu talasnu duinu svetlosti, sl. 11.12. Od-
mah treba istai da se LED ne realizuju u silicijumskoj tehnologiji, tako da je njihov napon pri
182
direktnoj polarizaciji znatno vei od 0.7 V. Drugim reima, LED se izrauju od poluprovod-
nikih materijala ije su vrednosti energetskih procepa vee nego u sluaju silicijuma. Na primer,
trokomponentno jedinjenje galijum-arsenid-fosfid (GaAsP) zrai vidljivu crvenu svetlost, dok se
LED od galijum-arsenida (GaAs) koristi za infracrveno (nevidljivo) podruje spektra, sl. 11.13.
Sl. 11.12. Spektralne karakteristike LED u vidljivom delu spektra.
Sl. 11.13. Spektralna karakteristika LED za infracrveno podruje.
11.5. KOMPONENTE SA SVETLOSNOM SPREGOM

Sve poluprovodnike komponente koje imaju ulaz i izlaz, iako se tretiraju kao da imaju
etiri izvoda, u sutini imaju samo tri kraja, s obzirom da je jedan kraj zajedniki i za ulazno i za
izlazno kolo. Prema tome, nije mogue ulaz izolovati od izlaza. I ne samo to, ve postoji i po-
vratno dejstvo izlaznog kola na ulazno.
Kod komponenata sa svetlosnom spregom, koji se popularno zovu optokapleri, ulaz je
izolovan od izlaza i, osim toga, izlaz nema nikakvog povratnog dejstva na ulaz. Izmeu izlaznog
i ulaznog kola potencijalna razlika moe biti i nekoliko kilovolta.
Komponenta sa svetlosnom spregom sastoji se od dve nezavisne optokomponente koje su
u nekom kuitu, obino plastinom, zatopljene. Prva komponenta je svetlea dioda (LED), a
183
druga je neka od fotokomponenata: fotootpornik, fotodioda ili, najee, kao to je prikazano na
sl. 11.14, fototranzistor. Izmeu njih je providan izolator. LED je prema tranzistoru okrenuta ta-
ko da zrai najvei intenzitet svetla, a fototranzistor je okrenut prema diodi svojom fotoosetlji-
vom stranom.
Sl. 11.14. Komponenta sa svetlosnom spregom (optokapler).
Svetlost se od svetlee diode do fototranzistora moe prenositi i posredstvom svetlosnog

provodnika. To je nit nainjena od transparentnog materijala, sa izuzetno dobro obraenom povr-
inom. Svetlost se usled totalne refleksije od zida prenosi kroz nit sa vrlo malim slabljenjem.
11.6. POLUPROVODNIKE LASERSKE DIODE

Poluprovodniki laseri predstavljaju praktino jednu od najbitnijih optoelektronskih na-
prava, koje se koriste u optikim fiber komunikacijama, kao i u optikom skladitenju podataka
u nizu aplikacija u mnogim oblastima.
Sl. 11.15. Laserskie diode u razliitim kuitima.
184
Veina laserskih dioda male snage inkapsulirana su u kuita tranzistorskog tipa (sl.
11.15 a, b i c), a manji deo ima kuita drugih oblika, sa razliitim talasnim duinama svetla koje
emituju (npr. oko 670 nm za crveno podruje spektra). Laserske diode koje se koriste u optikim
komunikacijskim sistemima ugrauju se u kuita koja na prozoru imaju ugraen (nalepljen)
svetlovod (sl. 11.15 d i e).
Na sl. 11.16 ilustrativno je prikazano poreenje veliine laserskih dioda sa drugim pred-
metima.
Sl. 11.16. Uz prikaz dimenzija laserskih dioda.
Slika 11.17 prikazuje delove diodnog lasera. Okruglo kuite zatvoreno je hermetiki. Sa
prednje strane (gore) ima tanki stakleni prozor kroz koji prolazi laserska svetlost, a sa zadnje
strane tri elektrina kontakta (noice). U kuitu se nalazi ne samo laserski ip mikronskih di-
menzija, priblino 0,5 5 300 m (desni gornji uago na slici, strelice oznaavaju snopove
svetlosti), nego i jedna integrisana fotodioda, takoe mikronskih dimenzija. Ona slui za prae-
nje intenziteta svetla lasera koje dolazi iz zadnjeg ogledala laserske diode. Ova fotodioda, u prin-
cipu, omoguuje kontrolu snage i talasne duine zraenja lasera optoelektronskom povratnom
vezom, preko odgovarajueg sklopa koji je deo elektronike za napajanje diode.
Sl. 11.17. Uz prikaz inkapsulirane laserske diode.
185
Bitna karakteristika lasera, koja ga izdvaja od ostalih izvora svetlosti, jeste emisija strogo
definisanih (uzanih) snopova monohromatske svetlosti. Sam princip rada laserske diode je slian
radu svetlee diode, sl. 11.18, ali za razliku od LED kod koje svetlost nastaje usled spontane
emisije, kod laserskih dioda svetlost je rezultat procesa stimulisane emisije. Drugim reima, kod
lasera se sreemo sa terminom stimulisana emisija, jer i sam naziv laser potie od Light Ampli-
fication by Stimulated Emission of Radiation, to znai: pojaanje svetlosti stimulisanom emisi-
jom zraenja. Stimulisana emisija nastaje kada kod direktno polarisane diode pored emisije foto-
na (spontana emisija) dolazi do stvaranja fotonske lavine, tj. kada svaki ovako stvoreni foton uz-
rokuje stvaranje drugih fotona koji imaju iste optike osobine (istu frekvenciju, smer, stanje po-
larizacije).
Sl. 11.18. Uz slinost i razliku izmeu svetlee diode i laserske diode.
Kod laserske diode se p-n spoj nalazi u optikoj upljini (rezonatoru) koju ine kristalne
ravni po kojima je kristal seen, tako da fotoni nastali stimulisanom emisijom doivljavaju vie-
struke refleksije unutar ovog rezonatora. Ako pojaanje emisije svetlosti (kao posledica stimuli-
sane emisije) uspe da kompenzuje gubitak fotona usled apsorpcije i difuzije iz p-n spoja, moe se
pojaviti laserski efekt, odnosno laserska emisija, sl. 11.19.
Sl. 11.19. Ilustracija laserske emisije.
Laserski efekat se javlja u ravni p-n spoja ako kroz njega protie struja elektrona dovolj-
no velike gustine. Poluprovodniki diodni laser nema spoljanjih ogledala. Viestruka refleksija
186
unutar rezonatora lasera odvija se na izlaznim ravnima kristala poluprovodnika (sl. 11.20) ija je
prirodna refleksivnost samo oko 30%. Meutim, veliko pojaanje kojim se odlikuje laserska
dioda ipak, i sa ogledalima tako niske refleksije, omoguava lasersku emisiju. Treba napomenuti
da je laserski efekat u smeru normalnom na osu laserskog zraenja uguen time to se dve bo-
ne ravni naprave da budu hrapave, ime se onemogui refleksija svetla u tom smeru koja bi,
inae, dovela do dodatnih gubitka i smanjenja efikasnosti laserske diode.
Sl. 11.20. Ilustracija viestruke refleksije laserskog zraka unutar rezonatora.
Treba napomenuti da se laserske diode proizvode od poluprovodnika sa tkzv. direktnim

prelazom nosilaca iz provodne u valentnu zonu, u koje ne spada silicijum. To su jedinjenja iz III
i V ili iz II i VI grupe periodnog sistema. I ne samo to, ve se p-n spoj formira kao heterospoj, a
to znai da je takav spoj sainjen od razliitih poluprovodnikih jedinjenja. Na sl. 11.21a je
prikazana realna struktura jednog InGaAsP poluprovodnikog lasera. Slika je dobijena skeniraju-
im elektronskim mikroskopom, i na njoj se lepo vidi struktura laserskog ipa. U cilju boljeg ob-
janjenja realne strukture na slici 11.21b data je skica te iste strukture. Uoava se da je aktivni
sloj mikronskih dimenzija, oko 0.3 3 m (duina ipa je 200 300 m).
a. b.
Sl. 11.21. Realna struktura InGaAsP poluprovodnikog lasera (a) i skica iste strukture (b).
187
12. OSNOVI INTEGRISANIH KOLA
Integrisano kolo je sloeno elektrino kolo sastavljeno iz mnotva elemenata objedinjenih
na jedinstvenoj podlozi i spremno za ugradnju u sloenije sisteme, ali kao jedinstvena kompo-
nenta. Ono u sebi sadri itave elektrine eme sa razliitim komponentama, kao to su tran-
zistori, otpornici, kondenzatori. Sastoji se (sl. 12.1) od kuita koje je od plastike ili keramike,
izvoda pomou kojih se montira na tampanu plou i ipa (u kojem su integrisani svi elementi) u
sreditu integrisanog kola, koji je sa izvodima povezan najee veoma tankim icama.
Sl. 12.1. Integrisano kolo sa osnovnim sastavnim delovima.
Broj izvoda zavisi od tipa integrisanog kola, tj. od njegove funkcije i moe se rei da je
taj broj standardizovan za razliite funkcije. Upravo funkcija koju obavlja uslovljava osnovnu
podelu integrisanih kola na: analogna (na primer, operacioni pojaava, sl. 12.2), digitalna (na
primer, procesor, sl. 12.3) i meovita na primer, A/D i D/A konvertori ona koja obrauju i
analogni i digitalni signal na istom ipu (ip poluprovodnika ploica s monolitnim sklopom).
12.1. VRSTE INTEGRACIJE

Posle otkria tranzistora, verovatno najzasluniji izum koji je doveo do elektronske revo-
lucije kakvu poznajemo u sadanjem obliku, posebno kada je re o raunarskoj tehnologiji, jesu
integrisana kola, koja su uslovila tehnoloki napredak nezabeleen u istoriji civilizacije. Naime,
integrisana kola su postajala i postaju i sada sve bra i monija zahvaljujui stalnom poveavanju
188
broja komponenata u njima, a novi modeli raznovrsne raunarske opreme pojavljuju se takvom
brzinom da ih s potekoama prate i najbolje upueni poznavaoci. Da se, na primer, automobil-
ska industrija razvijala istim tempom, automobil bi danas prelazio milion kilometara s potro-
njom od jednog litra goriva, razvijao bi brzinu veu od milion km/h, kotao bi svega nekoliko
evra, imao bi teinu manju od 100 g, a vreme eksploatacije bi mu bilo preko 10000 godina.
Sl. 12.2. Nekoliko SMD operacionih pojaavaa i oznaka u emama.
Sloenost, odnosno kompleksnost integrisanih kola meri se stepenom integracije, koji

predstavlja broj osnovnih elemenata (sada se tu misli na broj tranzistora) integrisanih u jednom
kolu. Usavravanjem tehnologije stepen integracije iz godine u godinu raste. O ovakvom tempu
razvoja govori poznati Murov zakon (sl. 12.4), nazvan po osnivau Intela Gordonu Muru, koji
kae da se broj elektronskih komponenata u procesoru udvostruuje svakih 18 meseci. Meutim,
fantastian napredak koji je doiveo silicijumski ip, ucrtan Murovim zakonom, ima svoje gra-
nice posle kojih nee postojati fizika mogunost da u jedan silicijumski ip stane jo elektron-
skih komponenata. Ogranienje je uslovljeno smanjivanjem najmanje komponente integrisanog
kola na veliinu atoma, kada e dalji razvoj mikroprocesora biti zaustavljen. Poluprovodnika
tehnologija potovala je Murov zakon gotovo 40 godina, a prema miljenju mnogih strunjaka to
bi trebalo da potraje do 2020. godine, dok mikroprocesori ne dou do atomske granice, to e
znaiti kraj ere silicijuma.
Po stepenu integracije integrisana kola se mogu podeliti u sledee grupe:
SSI (od Small Scale Integration) kola malog stepena integracije (sl. 12.5), koja u sebi
sadre do 100 osnovnih elemenata;
MSI (od Medium Scale Integration) kola srednjeg stepena integracije (sl. 12.5), sa
100 do 1000 osnovnih elememata;
LSI (od Large Scale Integration) kola visokog stepena integracije (sl. 12.6), koja ima-
ju 1000 do 10000 elemenata;
189
Sl. 12.3. Procesor (iz generacije 486) u okviru personalnog raunara.
Sl. 12.4. Prikaz poveanja broja tranzistora u Intelovim procesorima tokom godina.
VLSI (od Very Large Scale Integration) kola vrlo visokog stepena integracije (sl.
12.6), koja u sebi sadre 10000 do 100000 tranzistora;
ULSI (od Ultra Large Scale Integration) kola izuzetno visokog stepena integracije (sl.
12.7), sa preko milion tranzistora po integrisanom kolu ili ipu;
190
U2LSI3 (od Ultra-Ultra Large Scale Integration) kola izuzetno-izuzetno visokog ste-
pena integracije (sl. 12.8), sa preko milijardu tranzistora po integrisanom kolu ili ipu (sa preko
milion tranzistora po mm2).
Sl. 12.5. Neka od SSI i MSI integrisanih kola.
Sl. 12.6. LSI i VLSI integrisanih kola.
Dakle, broj tranzistora u procesorima koji se sada ugrauju u raunare vei je od milijar-
de. Stoga je disipacija na njima izuzetno velika. Kao primer kako se poveava snaga disipacije
Intelovih procesora sa smanjivanjem duine kanala MOS tranzistora, na sl. 12.9 je prikazan dija-
gram koji u budunosti predvia snage za koje je komentar izlian. (Napominje se da su ve sada
napajanja naponima od 0.8 V, tako da za snagu od npr. 80 W, struja iznosi 100 A!). Iz tog raz-
loga je ULSI i U2LSI kola potrebno dodatno hladiti. Hlaenje moe biti pasivno dodavanjem
3
Ovaj termin nije zvani~an, ve} je autor ovog teksta dao "sebi za pravo" da ga uvede.
191
masivnih hladnjaka koji odaju toplotu, ili aktivno ugradnjom ventilatora (to je danas redovan
sluaj kod procesora).
Sl. 12.7. Intelovi procesori 486 iz generacije ULSI kola.
Intel: 45 nm-ski procesor Intel: 32 nm-ski procesor AMD: 45 nm-ski procesor

Sl. 12.8. Nove generacije etvojezgarnih procesora.
Sl. 12.9. Murov prikaz poveanja snage sa smanjivanjem duine kanala

tranzistora u Intelovim procesorima tokom godina.
192
12.2. VRSTE INTEGRISANIH KOLA
Integrisana kola se mogu podeliti na vie naina: prema vrsti podloge (sl. 12.10), prema
tehnologiji izrade (sl. 12.11) i prema nainu rada.
Sl. 12.10. Podela integrisanih kola prema vrsti podloge (osnove).
Sl. 12.11. Podela integrisanih kola prema tehnologiji izrade.
12.2.1. Monolitna integrisana kola

Daleko najvei broj svih dananjih integrisanih kola jesu monolitna integrisana kola
sve njegove osnovne komponente su od istog materijala. Ova kola se jo zovu i planarna inte-
grisana kola, i to iz tri razloga: prvo, njihova izrada je bazirana na planarnom tehnolokom po-
stupku; drugo, struktura osnove na kojoj su realizovai elementi kola je planarna, tj. ravna, i tree,
dimenzije elemenata kola, normalne na povrinu osnove, su za vie od reda veliine manje od
debljine osnove, pa se stie utisak kao da su svi elementi u jednoj ravni.
Ne ulazei u detalje, ovde se istiu dve bitne prednosti planarnog procesa u poreenju sa
svim ostalim postojeim procesima, koja se nee posebno opisivati:
p-n spojevi, kao osnovni delovi svih bipolarnih i unipolarnih monolitnih integrisanih
kola, zatieni su na povrini poluprovodnika oksidnim slojem od spoljanjih uticaja, to omo-
guuje da se postignu vrlo male vrednosti struja inverzno polarisanih p-n spojeva i visoka pouz-
danost elemenata kola;
193
tehnika fotolitografije omoguuje postizanje izuzetno malih dimenzija elemenata kola i
istovremenu proizvodnju velikog broja istovetnih integrisanih kola na jednoj poluprovodnikoj
ploici, sl. 12.12 i sl. 12.13.
Dimenzije ipa monolitnih integrisanih kola, zavisno od sloenosti i funkcije koju inte-
grisano kolo treba da obavlja, mogu biti od nekoliko mm2 (kao na sl. 12.14a) do preko 350 mm2
(kao kod procesora na sl. 12.8). Na sl. 12.14b je prikazano jedno minijaturno SMD integrisano
kolo na vrhu prsta, upravo da bi se mogla da oceni njegova veliina.
Sa sl. 12.11 vidi se da monolitna integrisana kola mogu biti bipolarna, unipolarna i bipo-
larno-unipolarna (BiNOS i BiCMOS). U bipolarnim integrisanim kolima osnovni element je
NPN tranzistor. Izrada svih ostalih elemenata (dioda, PNP tranzistora, otpornika i kondenzatora)
je prilagoena tehnologiji NPN tranzistora. Bipolarna integrisana kola se odlikuju velikom opte-
retljivou, ali i relativno velikom sloenou.
Sl. 12.12. Planarna tehnologija omoguuje istovremenu proizvodnju velikog broja istovetnih integri-
sanih kola na jednoj poluprovodnikoj ploici (svaki kvadrat predstavlja jedno integrisano kolo).
Sl. 12.13. Uveana slika dva istovetna ipa dobijena planarnom tehnologijom.
194
a. b.
Sl. 12.14. Poreenje ipa sa veliinom nokta (a) i minijaturnog SMD operacionog
pojaavaa sa vrhom prsta (b).
Osnovni element unipolarnih integrisanih kola je MOS tranzistor, odnosno komplemen-

taran par n-kanalnog i p-kanalanog MOS tranzistora CMOS (s obzirom da su digitalna CMOS
integrisana kola od veoma velike vanosti u savremenoj elektronici, nadalje e vie rei biti o
CMOS invertoru, sl. 12.15).
Od bipolarnih i unipolarnih elemenata mogue je realizovati i kombinovana integrisana
kola (BiMOS i BiCMOS, sl. 12.11). U sutini, kod njih je osnova bipolarna ili MOS tehnologija,
pri emu se drugi osnovni element (npr. MOS tranzistor u bipolarnoj tehnologiji) radi komple-
mentarnim postupkom.
CMOS invertor
Osnovna elija digitalnih CMOS integrisanih kola jeste CMOS invertor, u kojem se kori-
sti par MOS tranzistora sastavljen od jednog n-kanalnog i jednog komplementarnog p-kanalnog
tranzistora, sl. 12.15. Korienje komplementarnog para MOS tranzistora omoguava projekto-
vanje digitalnih kola sa minimalnom potronjom energije. Karakteristika CMOS kola da imaju
nisku potronju energije enormno je proirila primenu digitalnih kola, koja se kree od dejih
igraaka do mobilnih telefona i kompjutera koje sada poznajemo. Prekidaka brzina, odnosno
maksimalna radna frekvencija, bila je u poetku nedostatak CMOS kola, ali je savremenim teh-
nolokim postupcima postugnuto izuzetno smanjivanje dimenzija MOS tranzistora, to je dovelo
do veoma velikog porasta brzine. Smanjivanje dimenzija je, takoe, omoguilo porast nivoa
integracije, dovodei do realizacije digitalnih integrisanih kola velikih operativnih mogunosti.
Stoga je CMOS tehnologija danas postala dominantna elektronska tehnologija.
CMOS invertor redovno se formira u supstratu n-tipa koji je istovremeno podloga inte-
grisanog kola kao celine i podloga p-kanalnog tranzistora. Da bi se formirao n-kanalni tranzistor,
potrebno je u zajednikom n-supstratu oformiti lokalnu p-podlogu. Ona se dobija difuzijom bora.
U tako dobijeno p-podruje difunduju se n+-podruja sorsa S1 i drejna D1 n-kanalnog tranzistora,
sl. 12.15b. p-kanalni tranzistor dobija se difuzijom bora direktno u n-podlogu, ime se formiraju
p+-podruja sorsa S2 i drejna D2.
U CMOS invertoru upravljake elektrode G1 i G2 n-kanalnog i p-kanalnog tranzistora
meusobno su spojene i slue kao ulazna elektroda invertora. Drejn D1 n-kanalnog i drejn D2 p-
195
kanalnog tranzistora su takoe meusobno spojeni i oni su izlazna elektroda invertora, sl. 12.15.
Sors S1 n-kanalnog tranzistora je uzemljen, a sors S2 p-kanalnog tranzistora je spojen na napaja-
nje VDD.
Uz pretpostavku da su p-kanalni i n-kanalni tranzistori komplementarni po karakteristika-
ma i da su im naponi praga suprotni po predznaku i jednaki po apsolutnom iznosu, princip rada
CMOS invertora moe se objasniti pomou slika 12.15 i 12.16. Naime, kad se na ulaz G CMOS
invertora dovede napon logike nule, to odgovara naponu VGS1 = 0, tada n-kanalni MOS ne
vodi. Istovremeno je napon izmeu kontrolne elektrode G2 i sorsa S2 p-kanalnog MOS
tranzistora negativan i priblino jednak VDD. Zato to je napon praga tog tranzistora negativan,
p-kanalni MOS tranzistor vodi. Meutim, kako je n-kanalni tranzistor zatvoren, p-kanalni MOS
radi s vrlo malom strujom drejna Is n-kanalnog MOS tranzistora, te se nalazi na samom poetku
triodnog podruja. Zato je napon VDS1 = Viz VDD, pa logikoj nuli na ulazu odgovara logika
jedinica na izlazu. Taj sluaj ilustrovan je na sl. 12.16a. Radna taka T1 odgovara izlaznom
naponu VDD i struji drejna ID = IS. Pri tome se menjanjem napona napajanja VDD moe menjati po
elji napon logike jedinice.
a.
b.
Sl. 12.15. Presek (a) i ematski prikaz (b) MOS invertora.
196
Sl. 12.16. Uz opis rada CMOS invertora: a - stanje logike jedinice
na izlazu; b - stanje logike nule na izlazu.
Ukoliko se na ulaz CMOS invertora dovede napon logike jedinice, tj. napon +VDD, tada
n-kanalni MOS tranzistor vodi. Istovremeno je napon kontrolne elektrode G2 prema sorsu S2 jed-
nak nuli, pa p-kanalni tranzistor ne vodi. Zato n-kanalni MOS tranzistor vodi vrlo malu struju
drejna p-kanalonog MOS tranzistora, te se nalazi na samom poetku triodnog podruja karakte-
ristika. Taj sluaj je predstavljen na sl. 12.16b, gde je oznaena taka T2 koja odgovara stanju
logike nule na izlazu.
Dakle, i pri voenju n-kanalnog i pri voenju p-kanalnog MOS tranzistora troi se veoma
malo energije, s obzirom da u oba sluaja protie izuzetno mala struja drejna jednog od tranzisto-
ra.
12.2.2. Tankoslojna i debeloslojna integrisana kola

Paralelno sa monolitnim integrisanim kolima razvijala su se, ali u znatno manjoj meri, i
integrisana kola u tehnologiji debelog i u tehnologiji tankog filma. U oba sluaja kao podloga
kola slui tanka ploica od izolatorskog materijala, npr. od specijalnih vrsta keramike.
U tehnologiji debelog filma se na podlogu metodom sito-tampe nanose provodni, otpor-
ni, dielektrini i izolatorski slojevi, pomou kojih se formiraju pasivne komponente debelosloj-
nog integrisanog kola (npr. otpornici, kondenzatori, provodne veze), sl. 12.17.
Sl. 12.17. Debeloslojna integrisana kola.
197
U tehnologiji tankog filma se za nanoenje odgovarajuih slojeva koristi tehnika va-
kuumskog naparavanja ili tehnika katodnog (jonskog) raspravanja. Ovom tehnologijom, kao i
debeloslojnom, mogu se dobiti dovoljno kvalitetne pasivne komponente, sl. 12.18. Mada je
ovom tehnikom mogue dobiti i pojedine aktivne komponente, one se u praksi, ipak, dodaju kao
diskretne. Na sl. 12.19 prikazano je nekoliko razliitih tankoslojnih inetgrisanih kola.
Sl. 12.18. Otponiki modul u tehnici debelog ili tankog filma (sloja).
Sl. 12.19. Tankoslojna integrisana kola.
12.2.3. Hibridna integrisana kola

Hibridna integrisana kola su kombinacija monolitnih kola i elemenata s kolima uraenim
tehnikama debelog ili tankog filma. Pri tome, pasivne komponente se realizuju debeloslojnom ili
tankoslojnom tehnologijom. Aktivna kola, realizovana planarnim procesom, dodaju se naknadno
u formi ipa koji se na pasivnoj podlozi povezuje sa debeloslojnim ili tankoslojnim komponen-
tama. Stoga postoje deboslojna i tankoslojna hibridna integrisana kola, sl. 12.20 i sl. 12.21.
U optem sluaju, u jednom hibridnom kolu mogu da budu i tankoslojne i debeloslojne i
monolitne i diskretne aktivne i pasivne komponente. Tehnologija kojom se komponente povezu-
ju odreuje naziv kola. Tako, na primer, debeloslojna hibridna integrisana kola, osim debelosloj-
nih pasivnih elemenata, mogu da sadre u ip formi aktivne komponente (tranzistore, diode, mo-
nolitna integrisana kola) i tankoslojne komponente. Stoga to se sve te komponente meusobno
povezuju tehnikom debelog filma, kola se zovu debeloslojna.
198
Sl. 12.20. Debeloslojna i tankoslojna hibridna integrisana kola.
Kombinovanjem svih raspoloivih tehnika koje omoguuju hibridno udruivanje kom-

ponenata (sl. 12.21) dobijaju se integrisana kola optimalnih karakteristika. Tako, na primer,
tankoslojni otpornici imaju manje tolerancije otpornosti, a tehnika debelog filma omoguuje vei
raspon vrednosti otpornosti otpornika. Ako u jednom hibridnom integrisanom kolu postoje oba
zahteva, kolo e se uraditi u debeloslojnoj tehnologiji, pri emu e se otpornici, kod kojih se tra-
e uske tolerancije otpornosti, realizovati kao ip komponenta tankoslojnom tehnologijom.
Ovde je neophodno istaknuti da se hibridna integrisana kola neuporedivo manje koriste
od monolitnih integrisanih kola. To je, stoga, to je monolitna tehnologija znatno univerzalnija, s
obzirom da omoguuje realizaciju i aktivnih i pasivnih komponenata veoma irokog raspona
vrednosti osnovnih parametara, i to, takoe, omoguuje za nekoliko redova veliine veu gusti-
nu pakovanja, kao i znanto veu pouzdanost. Sa druge strane, hibridnom tehnikom se prven-
stveno realizuju pasivne komponente. Dodue, tankoslojna tehnologija omoguuje realizaciju
tranzistora koji su slini MOS-u, ali se, po pravilu, u hibridnoj tehnici, kao to je pomenuto,
199
aktivne komponente dodaju u obliku ipa napravljenog planarnom tehnologijom. Moe se rei da
e se korisnik opredeliti za hibridnu tehniku u sledeim sluajevima:
kod maloserijske proizvodnje, jer je hibridna tehnologija, zbog nie cene, prihvatljivija;
za izradu kola specijalne namene;
kada se monolitnom tehnikom ne mogu ostvariti potrebne performanse (npr. vee kapa-
citivnosti kondenzatora);
kada je potrebno smanjiti dimenzije sistema realizovanog na tampanoj ploi sa diskret-
nim komponentama (sl. 12.22).
Ovo hibridno IC sadri 2 SMD integrisana Ovo debeloslojno hibridno IC sadri 20

kola, precizne debeloslojne otpornike i integrisanih kola i 600 ica za bondiranje
tankolsojne otpornike i kondenzatore
Sl. 12.21. Razliita hibridna integrisana kola.
Sl. 12.22. Spoljanji izgled hibridnih integrisanog kola.
200
13. TAMPANE PLOE
tampane ploe slue da se na njih montiraju pasivne komponente (otpornici, kondenza-
tori, kalemovi, diode), aktivne diskretne komponente (bipolarni i MOS tranzistori), integrisana
kola i sve ostale elektronske komponente, kao i za meusobno elektrino povezivanje tih kom-
ponenata. Na sl. 13.1 je prikazan deo tampane ploe za komponente sa izvodima (komponente
su sa suprotne strane), na kojoj se vide zalemljeni izvodi tih komponenata (sjajne zadebljane ta-
ke) i natampane provodne veze izmeu komponenata; na sl. 13.2 se vidi prednji deo
tampane ploe sa otvorima za izvode komponenata, koji e titi zalemljeni sa suprotne strane
ploe.
Sl. 13.1. Deo tampane ploe za komponente sa izvodima; komponente su sa suprotne strane.
Sl. 13.2. Prednji deo pripremljene tampane ploe za komponente sa izvodima.
201
Primenom tampanih provodnih veza u proizvodnji elektronskih ureaja obezbeuje se
vea pouzdanost komponenata i samih ureaja, poboljana tehnoloka izvodljivost (uslovljena
automatizacijom nekih montanih procesa), poveana gustina pakovanja komponenata (zbog
smanjenja dimenzija i mase pojedinih komponenata), poveana brzina rada i zatita od smetnji.
Za tampanu plou neophodna je fabriki pripremljena tanka ploa od nekog izolaci-
onog materijala, npr. od vitroplasta, pertinaksa (obino se zove kairani pertinaks) ili fiber-
stakla sa epoksidnom smolom, na koju je sa jedne ili sa obe strane nanesen tanak sloj bakra.
Na sl. 13.3 su predstavljene jednoslojne tampane ploe, koje se, pak, dele na jednostrano
(sl. 13.3a) i dvostrano (sl. 13.3b) tampane ploe. Jednostrano tampane ploe imaju provo-
dne veze samo na jednoj strani podloge, dok su dvostrano tampane ploe (kao i na sl. 13.2)
sa provodnim vezama na obema stranama. Pored njih, u industrijskoj proizvodnji i za veoma
sloena elektronska kola koriste se i vieslojne tampane ploe, sl. 13.4. Vieslojne tampane
ploe se sastoje od naizmenino rasporeenih slojeva provodnog i izolacionog materijala
spojenih zajedno. Provodni slojevi su povezani preko metaliziranih otvora koji se koriste kako
za montiranje, tako i za elektrino povezivanje komponenata.
Sl. 13.3. Jednoslojne tampane ploe.
13.1. JEDNOSLOJNE TAMPANE PLOE

Postoji vie naina da se jednoslojna tampana ploa napravi, i svi su oni zasnovani na
istom principu, a to je da se ukloni tanak sloj bakra sa neeljenih mesta, a da ostane samo ta-
mo gde je potrebno (za provodne veze i stopice za koje se leme komponente). Uklanjanje
sloja bakra ostvaruje se tako to se ploica nagriza hemijskim putem nekom kiselinom, ili se
nepotrebni delovi bakra mehaniki odstranjuju posebnim glodalicama.
202
Sl. 13.4. Vieslojne tampane ploe.
13.1.1. Izrada crtea tampanog kola

Da bi se na ploici ostvarile provodne tampane veze, potrebno je prvo da se na njoj
iscrta ema tih veza. To se radi tako to se na bakarni povrinski sloj (jednom od tehnika koje e
u delu 13.1.2 biti opisane) nanosi slika tampanih veza, vodei, pri tom, rauna da se provodne
veze ne seku i da budu to krae (na sl. 13.5 prikazane su dve dobro i dve loe projektovane pro-
vodne veze).
Nadalje e se, kao najprostiji sluaj, razmatrati samo jednostrano tampane ploe kao na
sl. 13.3a, a da bi postupak izrade maske bio jasniji, prikazae se kako se, od ulaznih taaka 1 i
2 do izlaza + i , crta tampa za elektrino kolo sa sl. 13.64 (to je jedan klasian stabilisani
ispravlja kod kojeg se, pomou trimer potenciometra TP, izlazni napon moe podesiti na bilo
koju vrednost do 9 V).
4
Primer sa sl. 13.6 i slike ozna~ene sa "*", kao i dobar deo obja{njenja vezan za njih, uz saglasnost autora Miomira
D. Filipovi}a i izdava~a Mikoelektronika (Beograd, 2008) preuzet je iz knjige "Komponente i prakti~na realizacija
elektronskih ure|aja".
203
Dobro Loe
Dobro Loe
Sl. 13.5. Dobro i loe projektovane provodne tampane veze.
Sl. 13.6*. Klasian stabilisani ispravlja.
Pre poetka crtanja tampanog kola neophodno je nabaviti sve komponente, da bi se

znale kolike su im dimenzije i kolika su rastojanja izmeu njihovih izvoda (noica). Takve ras-
poloive komponente sa naznakom njihovih relevantnih dimenzija za ispravlja sa sl. 13.6, od
ulaznih taaka 1 i 2 do izlaza + i , prikazane su na sl. 13.7.
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Sl. 13.7*. Komponente za ispravlja sa sl. 13.6.
(O prikazanim komponentama videti sledee delove: za Grecov spoj (a) deo 6.1.6;
za elektrolitske kondenzatore (b) i (g) deo 4.1.5; za otpornik (c) deo 4.1.1); za Zener diodu
(d) deo 6.1.3; za trimer potenciometar (e) deo 4.2.3: za NPN tranzistor (f) deo 7.1.1)
Sl. 13.8*. Postupak crtanja tampanog kola ispravljaa sa sl. 13.6.
Postupak crtanja je prikazan na sl. 13.8. Prvo su, sl. 13.8a, nacrtana dva kruia prenika
2 mm do 3 mm, na meusobnom rastojanju od oko 13 mm. To su stopice u koje e biti zalem-
ljene noice elektrolitskog kondenzatora C1 (sa sl. 13.7b). Ispod ovih stopica, a na osnovu di-
menzija sa sl. 13.7a, nacrtane su etiri stopice na meusobnom rastojanju od oko 5 mm u koje e
se zalemiti noice Grecovog spoja (usmeraa). Prema sl. 13.6, noica usmeraa koja je obeleena
sa +, spojena je sa + noicom kondenzatora C1, a noica obeleena sa , spojena je sa
noicom kondenzatora. Te dve veze su na sl. 13.8a nacrtane u obliku dve izlomljene prave linije.
Pri tome, treba se truditi da te linije budu, kao to je ve reeno, to krae i da se dobro pazi da se
ne dodirnu meusobno ili sa nekom od stopica pored kojih prolaze. Na sl. 13.8a su nacrtani i
kondenzator C1 i Grecov usmera onako kako izgledaju gledani sa donje strane (gde su im
noice), mada oni ne mogu da se vide, jer se nalaze sa suprotne strane ploice. Zgodno ih je,
ipak, crtati, da bi se lake snalazili i pri crtanju i pri kasnijoj montai komponenata na ploicu.
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Na sl. 13.8b su nacrtane jo dve stopice, 1 i 2, koje su povezane sa stopicama u koje
se leme noice Grecovog spoja, obeleene sa . U stopice 1 i 2 e biti zalemljene dve
bakarne ice kojima se na ploicu dovodi naizmenini napon sa sekundara mrenog transforma-
tora. Desno od kondenzatora C1 i Grecovog usmeraa, vodei rauna o dimenzijama, nacrtane su
stopice za otpornik R i Zener diodu D.
U daljem postupku crtanja tampanih veza, na sl. 13.8c su dodate i linije kojima su otpor-
nik R i Zener dioda D spojeni meusobno, kao i sa + krajem kondenzatora C1 i krajem
Grecovog spoja. Na istoj slici su nacrtane i stopice u koje e biti zalemljene noice NPN tran-
zistora T, elektrolitskog kondenzatora C2 i trimer potenciometra TP, kao i dve stopice (gore de-
sno, sa oznakama + i ) u koje se leme dve bakarne ice kojima se odvodi ispravljeni izla-
zni napon. Odgovarajuim meusobnim povezivanjem pomenutih stopica, kao i njihovim spaja-
njem sa ostalim komponentama, dobija se konaan izgled tampane ploe, prikazan na sl. 13.8d.
To je pogled na ploicu sa strane tampe. Sve komponente su sa druge strane (strane kompo-
nenata), pa kao to je ve reeno, ne mogu da se vide.
Raspored komponenata i izgled tampanih veza ne mora da bude kao na sl. 13.8d. Na pri-
mer, samo malo drugaijim rasporedom komponenata dobija se izgled tampane ploe kao na sl.
13.8e, odnosno na sl. 13.8f, na kojoj je prikazano kolo sa slike 13.8e bez komponentata, onako
kako ono stvarno treba da izgleda. Pored toga, sigurnije je, posebno ako kroz provodne veze teku
vee struje, da same veze budu ire. Stoga, kolo sa slike 13.8f moe da izgleda kao na sl. 13.9, na
kojoj su linije kroz koje teku struje proirene do maksimuma (napominje se da u sluaju
ispravljaa sa sl. 13.6 to nije neophodno). Time se ostvaruje uteda tenosti za nagrizanje bakra,
ploica postaje otpornija na mehanika oteenja, a komponente se efikasnije hlade, jer bakarne
povrine odvode sa njih toplotu i emituju je u okolni prostor. Nekada se upravo eli da se
provodna povrina za masu (uzemljenje) ureaja maksimalno povea, to doprinosi stabilnijem
radu ureaja, posebno ako su to ureaji koji rade na visokim uestanostima.
Sl. 13.9*. Drugaiji oblik (u odnosu na sl. 13.8f) tampanih veza ispravljaa sa sl. 13.6.
13.1.2. Prenoenje crtea na ploicu

Pripremljeni crte tampanih veza neophodno je sada preneti na povrinu ploice na kojoj
se nalazi bakar. Postoji vie naina prenoenja tog crtea. Najjednostavnije je da se crtanje pro-
vodnih veza kao na sl. 13.8 uradi alkoholnim flomasterom direktno na bakarnoj povrini.
Meutim, ovako relativno prost postupak crtanja crtea tampanog kola mogu je samo kada su
u pitanju elektronski ureaji koji nisu sloeni, kao to su ispravljai, razni pojaavai, alarmni
ureaji, jednostavniji digitalni ureaji i sl.
Opisani postupak nije mogue koristiti u sloenijim digitalnim ureajima koji imaju vrlo
veliki broj minijaturnih stopica i vrlo tanke provodne veze (linije). Jednostavno, stopice su suvie
malih dimenzija, a linije suvie tanke (ak i do desetog dela milimetra) i sasvim blizu jedna po-
red druge, tako da ih nije mogue nacrtati rukom. U takvim sluajevima koristi se raunar i neki
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od programa za projektovanje tampanih kola (primer jednog takvog tampanog kola prikazan je
na sl. 13.10b). Najpoznatiji su TANGO, OrCAD PCB, PROTEL, EAGLE, itd. U takvim sluaje-
vima se za prenoenje crtea koristi fotopostupak.
Za prenoenje crtea fotopostupkom potreban je fotolak u obliku spreja, a postupak je
sledei:
1. tampano kolo se nacrta rukom (npr. kao na sl. 13.10a), ili odtampa visokokontrastno na
printeru sa raunara na poluprovidnoj hartiji (pausu) ili nekom drugom propustljivom materijalu
za ultraljubiastu (UV) svetlost (fotografski film, prozirna folija visoke stabilnosti i sl.). Kako
odtapani sloj treba da prijanja uz bakarni sloj na ploici, to je crtanje, odnosno printanje crtea
neophodno izvesti u Mirror (kao lik u ogledalu) opciji, sl. 13.10. Sam nacrt mora biti izraen
tako da budui elektrino provodni putevi budu potpuno neprozirni za UV deo spektra, a da
delovi koji e odgovarati nagrienim povrinama bakarne folije budu potpuno prozirni.
a. b.
Sl. 13..10. Crtei koji se prenose fotopostupkom mora da budu u Mirror opciji (kao lik u ogledalu).
2. Bakarna povrina treba da bude savreno ista. Najbolje ienje mogue je postii ne-
kim prakom koji sadri sitan pesak (npr. VIM), a zatim je prebrisati suvom istom tkaninom
(povrina mora biti sjajna, bez otisaka prstiju, a posle ienja se bakarni sloj ne sme dodirivati
prstima).
3. Bakarna strana ploice se ravnomerno isprska lakom (sl. 13.11) u tankom sloju. Nano-
enje laka je potrebno izvesti u (cik-cak) horizontalnoj i zatim vertikalnoj osnovi, koso drei
sprej na udaljenosti oko 20 cm. Lak je, neto manje nego fotografski film, osetljiv na svetlost, pa
se prskanje obavlja u nekoj polutamnoj prostoriji. Osim toga, lak je osetljiv i na prainu, pa i o
tome treba voditi rauna. Sloj laka treba da je vrlo tanak i ravnomerno preliven preko cele povr-
ine.
4. Suenje laka na ploici na sobnoj temperaturi moe da potraje itava 24 sata. Ovo vreme
se skrauje na samo oko 15 minuta ako se suenje obavlja u penici tednjaka, na temperaturi
oko 70C. Pri suenju lak promeni boju, odnosno postane malo svetliji. Hlaenje ploice traje
nekoliko minuta. I suenje i hlaenje treba obavljati u polumraku, titei ploicu od svetlosti.
5. Za dalji rad potrebni su ravno staklo i komad ravne drvene podloge istih dimenzija, koje
su vee od dimenzija tampane ploice koja se pravi. Prema sl. 13.12, na drvenu podlogu se stavi
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ploica. Bakarna strana, koja je isprskana lakom, mora da bude gore. Na nju se stavi paus sa
crteom kola. Strana na kojoj je crte mora da bude sa donje strane, tako da boja kojom je crte
pravljen lei na bakru. Preko pausa se stavi staklo. Staklo se pritisne i komadima lepljive trake
spoji po uglovima za drvenu podlogu (tako je dobijen tkzv. sendvi). Sve ovo se radi u polu-
mraku sa to manje svetlosti koja bi mogla da oteti fotolak.
Sl. 13.11*. Prskanje ploice lakom.
Sl. 13.12*. Sendvi: drvena podloga, ploica sa lakiranim bakrom na gore, paus sa slikom na dole, staklo.
6. Sledei korak je osvetljavanje (ekspozicija) ploice (sl. 13.13). Sendvi, sa staklom na

gore, stavi se ispod UV (ultravioletne) sijalice i dri ispod nje nekoliko minuta. U nedostatku ove
sijalice moe da se koristi i neki drugi izvor svetlosti talasne duine od 370 nm do 440 nm (uz
striktno pridravanje uputstva za vreme osvetljavanja ploice), pri emu je neophodno da ploica
bude ravnomerno osvetljena. Da bi cela povrina ploice bila ravnomemo osvetljena, s vremena
na vreme ploicu treba pomerati levo-desno, napred-nazad. Vreme izlaganja sendvia svetlo-
sti, kao i udaljenost izvora svetlosti od ploice, zavisi od vrste i jaine svetla, ali i od vrste foto-
laka.
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Sl. 13.13. Osvetljavanje (ekspozicija) ploice.
7. Odmah nakon zavretka osvetljavanja, ploica se odvoji iz sendvia u zatamnjenoj

prostoriji i izlae procesu koji se zove razvijanje. Razvija se pravi tako to se 7 grama natri-
jum hlorida (NaOH iva soda) rastvori u jednom litru vode na sobnoj temperaturi. Ploica se,
sa bakarnom stranom okrenutom na gore, stavi u neku plitku posudu od plastike ili keramike i
sipa razvija, tako da prekrije ploicu za nekoliko milimetara (sl. 13.14a). Ploica ostaje u rast-
voru oko 2 minuta, dok lak koji nije bio zatien od svetlosti (to je sav lak van stopica i linija na
crteu) ne bude rastvoren. Razvijanje je gotovo kada se na ploici pojavi crte tampanog kola,
nacrtan lakom, sl. 13.14b. Odmah treba izvaditi ploicu i isprati je pod mlazom vode. Raz-
vijanjem prestaje svaka osetljivost na svetlo i tako dobijen sloj je stabilan u duem vremenskom
periodu.
a. b.
Sl. 13.14. a Uz proces razvijanja; b razvijena ploica.
Pre nego to bude rei o zavrnom delu u dobijanju tampane ploice, a to je nagrizanje,
odnosno odstranjivanje vika bakra sa ploice koji nije bio zatien crteom, ovde e se navesti
jo jedan nain prenoenja crtea na ploicu, koji po kvalitetu daje tampane veze skoro kao i
fotografska tehnika, ali je znatno jednostavniji (jer se preskau koraci od 3 do 7 opisani u okviru
fotopostupka). Naime, postoji posebna plastina folija koja se zove Press and Peel Blue (PnP
Blue). To je tanka plastina folija presvuena specijalnim plavim premazom. Spoj izmeu pre-
maza i plastine podloge je veoma slab. ema tampane veze se otiskuje na PnP Blue, a zatim se
peglanjem prenosi na istu bakarnu povrinu ploice. Zagrejana pegla topi toner, usled ega se
on lepi za bakar. Zatim se PnP Blue skida sa ploice, a toner ostaje na bakru.
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13.1.3. Nagrizanje ploice
Krajnji rezultat opisanih postupaka projektovanja tampanog kola i njegovog precrtava-
nja na ploicu je nagrizanje vika bakra, odnosno odstranjivanje sa ploice bakra koji nije zati-
en stopicama i linijama. To se u kunim uslovima obavlja pomocu ferihlorida, ili pomou me-
avine sone kiseline i vodonik peroksida (hidrogena). Treba naglasiti da su oba sredstva za na-
grizanje, kao i veina drugih kiselina, otrovni, opasni za oi, otvorenu ranu i sluzokou. Dakle,
pri radu sa sredstvima za razvijanje, treba biti oprezan.
Nagrizanje pomou ferihlorida
U trgovini se ferihlorid (FeCl3) moe nabaviti ili kao tenost crveno-smee boje, ili u
vrstom stanju u obliku grumenova kristala. Da bi se dobila tenost, u plastinu posudu u kojoj
0,5 kg grumenja treba naliti jedan litar vode i saekati da se grumenovi otope.
Za nagrizanje ploice je potreban neki plitak sud, najbolje pravougaonog oblika, izraen
od plastike, stakla ili keramike. Ferihlorid se sipa u sud tako da dubina tenosti bude nekoliko
centimetara. Ploica, sa bakrom na dole, stavlja se tako da pliva po povrini tenosti (sl.
13.15). Ploicu treba povremeno vaditi iz rastvora i proveravati kako se proces razvija, jer ako
ploica suvie dugo ostane u rastvoru, on e poeti da unitava i bakar ispod boje. Vaenje plo-
ice se vri iskljuivo nemetalnim pomagalima (plastinom pincetom ili, kao na sl. 13.15, pomo-
u selotejpa zalepljenog u obliku malog draa za gornji deo ploice). Pored toga, potrebno je
pomerati ploicu, naroito ako je veih dimenzija, nekoliko puta levo-desno da bi se bilo sigurno
da se ispod nje nisu zadrali mehuri od vazduha.
Sl. 13.15*. Nagrizanje ferihloridom.
Tenost e poeti da nagriza i rastvara bakar koji nije zastien flomasterom ili lakom i
posle izvesnog vremena, oko 15 minuta, sav ovaj bakar e nestati i ploica e izgledati kao na sl.
13.16a. Kada je nagrizanje zavreno i na ploici nema vie nezatienog bakra, treba je prvo do-
bro oprati u vodi, a zatim skinuti boju koja je titila tampane veze. Na ploici e se pojaviti
sjajne bakarne linije i stopice kao na sl. 13.16b.
Nagrizanje pomou H2O + HCl + H2O2
Umesto ferihlorida, za nagrizanje se ee koristi meavina 35% hlorovodonine (sone)

kiseline (HCl), hidrogena (H2O2 vodonik peroksid, ili kako se jo zove, oksien) i vode. Smea
se pravi neposredno pre nagrizanja.
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a. b.
Sl. 13.16. Izgled ploica posle nagrizanja (a) i posle uklanjanja zatitnog sloja (b).
Na dno plitkog plastinog ili nekog drugog nemetalnog suda stavi se ploica sa bakrom
na gore i sipa sona kiselina tako da tenost prekrije ploicu (sl. 13.17). Zatim se u nju dodaje
hidrogen, koji se sipa direktno iznad ploice. Koliina hidrogena koji se dodaje zavisi od njegove
koncentracije, kao i od koncentracije sone kiseline. To znai da treba iznad ploice sipati malo
hidrogena, podii malo levi pa desni kraj suda, da se tenosti izmeaju, i posmatrati ploicu.
Smea je potpuno providna, i ako bakar posle desetak sekundi pone da menja boju, nagrizanje
je poelo. Pri tome, iz tenosti izlaze mehurii, a ako i nema ili ih je malo, dodaje se jo malo hi-
drogena. Pri dodavanju hidorogena se pazi da se ne pretera, jer ako mehuria ima previe, te-
nost e poeti da se zagreva i moe da uniti boju.
Sl. 13.17*. Nagrizanje sonom kiselinom i hidrogenom.
Proces nagrizanja se lako prati, jer je tenost providna. Nagrizanje je zavreno kada na
ploici nema vie nezatienog bakra (sl. 13.16a). Nju treba izvaditi i dobro oprati u vodi, a boju
koja je titila tampane veze treba skinuti (sl. 13.16b) trljanjem vlanom krpicom, zamoenom u
neko od prakastih sredstava za ienje.
Zavrena ploica, sa prethodno izbuenim rupicama (obino prenika 1 mm) za kompo-
nente i dve rupe od 3 mm za zavrtnje kojima se ploica montira u kutiju u koju je smeten is-
pravlja sa slike 13.6, prikazana je na sl. 13.18a.
13.1.4. Dvostrano tampana ploa

Pored jednostrano kairanog pertinaksa o kome je do sada bilo rei, kao to je reeno (sl.
13.3b) postoji i pertinaks na ije je obe strane naneen tanak sloj bakra. On se najee koristi pri
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praktinoj realizaciji elektronskih kola koja imaju mnogo linija kojima se spajaju komponente,
dovode i odvode signali, itd.
a. b. c.
Sl. 13.18*. a Zavrena tampana ploica ispravljaa sa sl. 13.6; b crte tampane
ploice (sl. 13.8b); c tampana ploa sa komponentama.
Komponente se montiraju na jednoj strani strani komponenata, a veina veza, sve ko-
je mogu da se ostvare, su na suprotnoj strani, kao i kod obinih (jednostranih) tampanih ploa.
Preostale veze se crtaju na strani komponenata. Spojevi izmeu bakarnih linija (veza) sa jedne i
sa druge strane ostvaruju se na taj nain to se te linije crtaju tako da se ukrtaju, a na mestu
ukrtanja se bui rupica kao za komponentu. U fabrikoj proizvodnji te rupe se metalizuju (ob-
loe metalom), ime se ostvaruje potreban spoj. U kunoj izvedbi spoj se ostvaruje tako to se
kroz rupicu provue komad ice koji se zalemi za obe bakarne linije. Moe i kolo da se tako pro-
jektuje, da kroz tu rupicu prolazi prikljuak neke komponente koji se zalemi za obe bakarne lini-
je.
Ako se crte tampanih veza koji se realizuje na jednostrano kairanom pertinaksu po
precrtavanju na bakarnu stranu ploice pomeri malo levo ili desno, to nema velikog znaaja. Ali
u sluaju dvostrane tampe, ak i vrlo malo pomeranje moe da dovede do toga da je vrlo teko,
esto i nemogue, ostvariti potrebne veze izmeu jedne i druge strane. Zato je najbolje nacrtati
samo jednu stranu, izvriti nagrizanje bakra i izbuiti rape. Rupe kroz koje prolaze provodnici
kojima se ostvaruje spoj izmeu veza sa suprotnih strana, omoguuju da se veze sa druge strane
nacrtaju tano na potrebnim mestima. Naravno, te veze ne smeju da prelaze preko ostalih rupa,
jer su one zauzete. Zatim se izvri nagrizanje bakra i sa te strane.
Dok se nagriza jedna strana, druga mora biti zatiena. To se najlake ostvaruje tako to
se na nju, pomou lepljive trake, privrsti komad neke plastine folije otporne na kiseline.
13.2. VIESLOJNE TAMPANE PLOE

Odmah treba rei da se vieslojne tampane ploe, iji su popreni preseci prikazani
na sl. 13.4 i sl. 13.19, ne realizuju u kunim uslovima, ve je njihova proizvodnja iskljuivo
industrijska, s obzirom da su za njih neophodne veoma velike investicije i skupa oprema.
Na svetskom tritu postoje dve velike grupe proizvoaa ovih tampanih ploa.
Prvu grupu ine tkzv. nezavisni ili trini proizvoai, koji svoje proizvode nude na otvo-
renom tritu. Te ploe su, pre svega, namenjene za ugradnju u ureaje koji se proizvode i
prodaju u veoma velikom broju (TV aparati, PC raunari, mobilni telefoni). Pored toga, ova
grupa proizvoaa nudi mogunost kupcima da i sami uestvuju u dizajniranju tampanih
ploa, ime je trite znaajno proireno i na proizvodnju ureaja koji se ne proizvode u
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tako velikim serijama. Drugu veliku grupu proizvoaa vieslojnih tampanih ploa ine tkzv.
proizvoai zatvorenog tipa, koji proizvode ove ploe iskljuivo za ugradnju u svoje sopstvene
proizvode (Hewlett Packard, Texas Instruments, IBM).
Sl. 13.19. Popreni presek vieslojne tampane ploe.
Sl. 13.20. Blok ema tipinog tehnolokog niza za proizvodnju vieslojnih tampanih ploa.
Kao to je ve reeno, vieslojne tampane ploe se sastoje od naizmenino raspore-

enih slojeva provodnog i izolacionog materijala spojenih zajedno (sl. 13.4 i sl. 13.19). Pro-
vodni slojevi su povezani preko metaliziranih otvora koji se koriste kako za montiranje, tako i
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za elektrino povezivanje komponenata, uz napomenu da se pojedini itavi provodni slojevi
koriste kao kontakti za napajanje ili za uzemljenje (sl. 13.19)
Proces proizvodnje vieslojnih tampanih ploa predstavlja veoma sloen tehnoloki po-
stupak koji ubuhvata preko 50 proizvodnih koraka, ali se, grubo, moe podeliti u 9 procesnih ko-
raka, kao to je prikazano blok emom na sl. 13.20. Procesi projektovanja, kao i formiranja unu-
tranjih i spoljanjih slojeva tampane ploe su potpuno automatizovani primenom snanih rau-
nara i softverskih paketa za razmetaj komponenata. Trei procesni korak (laminiranje unutra-
njih slojeva) je proces spajanja razliitih slojeva, u kojem se elektrino povezuju provodni likovi
prethodno nezavisno uraeni na svakom sloju bakar-dielektrik. Ovaj proces na kraju ukljuuje i
presovanje sloenih ploa u jedinstvenu sendvi tampanu plou (sl. 13.4 i sl. 13.21). Posle bu-
enja otvora (etvrti korak, sl. 13.20) i njihovog ienja (peti korak), pristupa se metalizaciji
otvora. Proizvoai za metalizaciju koriste razliite materijale: jedni je izvode hemijskim nano-
enjem bakra, drugi za to koriste ugljenik, trei grafit, a etvrti se opredeljuju za paladijum. Za-
vrna obrada na kraju (sl. 13.20), izmeu ostalog, predvia i elektrotestiranje ploe u cilju otkla-
njanja neispravnosti provodnih veza, kao to su prekidi i kratki spojevi.
13.3. TAMPANE PLOE ZA POVRINSKU MONTAU

To su, praktino, vieslojne tampane ploe sa stopicama prilagoenim za komponente za
povrinsku montau (SMD), sl. 13.21. Procenjuje se da svetsko trite ovakvih tampanih ploa
iznosi izmeu 20 i 25 milijardi dolara. Do pre par godina vodei proizvoai su bili SAD i Ja-
pan, a sada je primat preuzela Kina, uz stalno prisutnu tendenciju daljeg rasta proizvodnje.

Metalizirana rupa
Sl. 13.21. Deo vieslojne tampane ploe za povrinsku montau komponenata.
Na sl. 13.22 je prikazana fotografija (sa uveanjem 16 puta) dela tampane ploe sa povr-
inski montiranim komponentama, a sl. 13.23 se, takoe, odnosi na deo takve ploe, snimljenom
odozgo.
214
Sl. 13.22. Fotografija (sa uveanjem 16 puta) dela tampane ploe sa povrinski
montiranim komponentama.
Sl. 13.23. Snimak odozgo dela tampane ploe sa povrinski montiranim komponentama.
215
216
VISER, SP- ELITE, PREDMET: Energetska Elektronika
KOREKCIJA FAKTORA SNAGE U

PREKIDAKIM
IZVORIMA NAPAJANJA
Prof. Dr eljko Despotovi, dipl.el.in
TA JE FAKTOR SNAGE???
Power Factor Correction-PFC

KOREKCIJA FAKTORA SNAGE
UTICAJ DIODNOG ISPRAVLJAA NA MREU
OTRI IMPULSI STRUJE

TRAJANJE IMPULSA 1ms-2ms
KAPACITIVNA STRUJA
VII HARMONICI
KOLIKA JE VRNA VREDNOST ULAZNE
STRUJE???????
POJEDNOSTAVLJENA RAUNCA!!!
Pretpostavimo da imamo prekidaki izvor napajanja bez

PFC , ija je aktivna snaga 220W
Napaja se iz 220V, 50Hz
Efektivna vrednost ulazne struje je 1A
Ako impuls struje traje 1ms, a trajanje poluperiode je
10ms, zakljuujemo da je vrna vrednost strujnog
impulsa 10A
Ovo sve vai kako za (+)periodu tako i za (-) periodu
Zamislimo da je na jednoj fazi povezano 200 PC raunara
Ukupna vrna struja po poluperiodi je 200x10A=2kA
Problemi: strujni udari, padovi napona, naponski
propadi ili sagovi, generisanje viih harmonika....
KAKO RETI PROBLEM????

Izmeu punotalasnog ispravljaa i kondenzatora (hold-up) se

postavlja podiza napona
BOOST konvertor
Potreban USLOV da bi se obezbedila sinusna ulazna struja je da
moramo realizovati podiza (boost-er) napona
elimo da ostvarimo sinusnu struju umesto otrih impulsa, a da
efektivna vrednost ostane ista
POREENJE KLASINOG I SAVREMENOG
REENJA ULAZNOG PC NAPAJANJA
PC NAPAJANJE SA KOREKCIJOM FAKTORA SNAGE
POETNO PUNJENJE hold-up
KONDENZATORA
NTC je nelinearni
otpornik ograniava
poetnu struju punjenja
kondenzatora
U poetnom trenutku t+0
napon na kondenzatoru je
jednak 0V
Stoga je kondenzator
KRATAK SPOJ U
POETKU
Nakon njegovog punjenja
kolo je spremno za START
PODIZA NAPONA - BOOST
PRINCIPSKA EMA
KLJUNE KOMPONENTE: L, D i S PFC kontroler?????

PRIGUNICA L (DC struja) KAKVA JE NJEGOVA
BRZA DIODA D ARHITEKTURA
PREKIDA S (MOSFET, IGBT)
OPTEREENJE-PC napajanje JEDNO MOGUE REENJE
PFC kontrolno kolo programirana strujna
kontrola
vrne ("peak") vrednosti struje
DETALJNI PRIKAZ PFC UPRAVLJAKOG KOLA
UPRAVLJAKI BLOKOVI:
-sinusna referenca
-mnoa
-komparator (poreenje naponske rampe i izlaza mnoaa)
-naponski pojaava
-RS flip flop
-generator takta (clock)
A KAKVI SU STVARNI TALASNI OBLICI
ULAZNE STRUJE
OVIH NAPAJANJA ??????????
Ulazna struja
PC napajanja
bez korekcije
faktora snage
Faktor snage:
jako lo
ULAZNA STRUJA 10A/c

MRENI NAPON 100V/c
Ulazna struja
PC napajanja
bez korekcije
faktora snage ali
sa prigunicom
postavljenom
prema mrenom
napajanju
Faktor snage:
PF=0.75
ULAZNA STRUJA 5A/c

MRENI NAPON 200V/c
U OVOM SLUAJU NAPOJNA
MREA VIDI PC RAUNAR
KAO OMSKU OTPORNOST

Ulazna struja
tipinog PC
napajanja
sa korekcijom
faktora snage
Faktor snage:
PF=1
ULAZNA STRUJA 1A/c

MRENI NAPON 100V/c
HVALA NA
PANJI!!!!
?
PITANJA ???? ????
DILEME ???? U Beogradu
12.12.2011 god.
ELEKTRINI PRETVARAI
SNAGE
ENERGETSKI PRETVARAI
UVODNO
PREDAVANJE
PREDAVA: Dr eljko Despotovi

Energetski pretvarai elektrine energije su ureaji koji
transformiu elektrinu energiju od predajnika (generator, izvor)
ka prijemniku (potroau).
Elektrina energija moe biti:
DC-Direct Current
- jednosmerna (jednosmerna struja i napon) =
- naizmenina (naizmenina struja i napon) ~ AC-Alternating Current
Prema ovoj osnovnoj funkciji postoji podela na:

AC/DC pretvarae (pretvaraju naizmeninu struju/napon u jednosmernu struju/napon)
ISPRAVLJAI
DC/AC pretvarae (pretvaraju jednosmernu struju/napon u naizmeninu struju/napon)

INVERTORI
DC-DC pretvarae (pretvaraju jednosmernu struju jednog naponskog nivoa

u jednosmernu struju drugog naponskog nivoa)-transformatori napona - OPERI
Mogu biti sputai napona (step-down) ili podizai (step-up)
AC-AC pretvarae (pretvaraju naizmeninu struju jednog naponskog nivoa u naizmeninu

struju drugog naponskog nivoa)
-podizai i sputai naizmeninog napona (PODEAVAI NAPONA)
-pretvarai uestanosti (CIKLOKONVERTORI)
OSNOVNI VIDOVI PRETVARANJA ENERGIJE
Primena pretvaraa je raznovrsna, a njihove snage mogu biti reda od 1W
(npr. u kunim ureajima, u elektronskim ureajima) do reda 100 MW.
Podela oblasti primene pretvaraa, po snazi (naponu i struji).

(1) U ovoj oblasti snage pretvraa su u opsegu od npr.
10VA do 100VA i to su aparati iroke potronje.
(2) Ureaji koji se koriste u hemijskoj industriji i

metalurgiji npr. za elektrolizu; naponi su ovde relativno
niski ali struje zato mogu imati veoma velike jaine.
(3),(4) Jednosmerni elektromotorni pogoni i

naizmenini elektromotorni pogoni.
(5) VF (visokofrekventne) pei: ovde je napon reda

1kV, P (~ 10kW, ~ 1MW).
(6) Elektrina vua
(7) Jednosmerni prenos elektrine energije

Poluprovodnike komponente koje se koriste u energetskim pretvaraima
SW-kontrolisani prekidaki
element (tranzistor ili tiristor)
D-dioda
L-induktivnost
C-kapacitivnost
F1,F2-zatitni elementi
(ultra brzi osigurai)
U elektronici je najbitnije da li poluprovodnika komponenta verno prenosi ili odrava signal, dok je
koeficijent korisnog dejstva manje vaan.
U energetici je situacija potpuno obrnuta. Najvaniji pokazatelj nekog pretvaraa je njegov stepen
korisnog dejstva.
Prekidaki elemenat -SW

TIRISTORI-SCR (Silicon Controlled Rectifiers)
MCT (Mos Controlled Thyristor)
GTO (Gate Turn- Off)
TRANZISTORI:
BJT (Bipolar Junction Transistor)
MOSFET (Metal Oxide Semiconductor FET)
IGBT (Insulated Gate Bipolar Transistor)
TIRISTORI-SCR
TIRISTORI ZA VELIKE SNAGE
IGBT tranzistor 150A/600V(danas je to glavni
poluprovodniki prekida snage)
OPSEZI PRIMENE KONTROLISANIH PREKIDAKIH ELEMENATA-SW
Podela oblasti primene energetskih prekidaa po snazi i radnoj uestanosti
AC/DC pretvarai-ISPRAVLJAI
220V, 50/60Hz
AC ulaz: monofazni ili trofazni 3x380/220V, 50/60Hz
1 3
AC DC AC DC
ulaz izlaz ulaz izlaz
MONOFAZNI DIODNI ISPRAVLJAI TROFAZNI DIODNI ISPRAVLJAI
1 3
AC AC
DC DC
ulaz ulaz
izlaz izlaz
kontrola kontrola PRIMENA:

-aparati za zavarivanje
-jednosmerni motorni pogoni
KONTROLISANI
TIRISTORSKI ili TRANZISTORSKI ISPRAVLJAI -punjai baterija
MONOFAZNI , TROFAZNI -jednosmerni izvori napajanja
-visokonaponske DC aplikacije
TIRISTORSKI: POLUUPRAVLJIVI I PUNOUPRAVLJIVI
- DC transmisije dalekovodima
NEUPRAVLJIVI AC/DC PRETVARAI DIODNI ISPRAVLJAI
POLUUPRAVLJIVI i PUNOUPRAVLJIVI AC/DC PRETVARAI-ISPRAVLJAI
DC/AC pretvarai-INVERTORI
DC 1 AC monofazno
izlaz optereenje
ulaz
Vc PRIMENA:
Vc-kontrolni napon
regulator -regulisani motorni pogoni
-kune aplikacije
-el.vua
DC 3 trofazno -DC transmisije
ulaz optereenje
AC
Vc izlaz
regulator
DC ulaz: jednosmerni izvori napajanja, izlaz ispravljakih jedinica,
solarne elije, DC vetrogeneratori , baterije, gorivne elije
Praktine reaalizacije DC/AC pretvaraa-INVERTORA
DC/DC pretvarai-OPERI
CHOPPER=seka
DC DC optereenje
ulaz izlaz
povratna sprega
Vc-kontrolni napon Vc
regulator
Pretvaraju nestabilisani DC ulazni napon u stabilisani DC izlazni napon

zahtevanog nivoa
DC ulaz: jednosmerni izvori napajanja, izlaz ispravljakih jedinica, solarne elije,

DC vetrogeneratori , baterije, gorivne elije
PRIMENA: Prekidaki izvori napajanja-Switch Mode Power Supply (SMPS),
kontrola jednosmernih motora, punjai baterija
Kombinovani AC/DC i DC/DC pretvara = AC/DC pretvara (ispravlja)
~ =
~ = = ~ ~
=
AC/DC DC/DC AC/DC
AC/DC
pretvara
AC/AC pretvarai
PODEAVAI NAPONA
PRETVARAI UESTANOSTI
PODEAVAI NAPONA- Dvosmerni spojevi
MONOFAZNI
PODEAVAI NAPONA- Dvosmerni spojevi
TROFAZNI
DIREKTNI AC/AC pretvarai-CIKLOKONVERTORI
Ulazna uestanost je vea od izlazne f1>f2

PRIMENA: sporohodni motorni pogoni velikih snaga ( >1MW)
INDIREKTNI PRETVARA UESTANOSTI
PRETVARA 1PH/1PH
Dva pretvaranja energije

AC-DC i DC-AC to je ustvari AC-AC
INDIREKTNI PRETVARA UESTANOSTI
PRETVARA 1PH/3PH
Dva pretvaranja energije: AC-DC i DC-AC to je ustvari AC-AC

AC-DC-AC pretvara: Rezonantni invertor za indukciono grejanje P=60kW,
izlazne uestanosti 5kHz
Energetsko kolo trofaznog

mrenog ispravljaa i
rezonantnog
pretvaraa uestanosti sa
rezonantnim LC kolom
SISTEM ENERGETSKIH PRETVARAA-Koncentrisani DC BUS sistem
SISTEM ENERGETSKIH PRETVARAA- Altenativni izvori napajanja
Solarne elije
Jednosmerni vetrogenerator
Kontrolisani DC-DC i DC-AC pretvarai- Alternativni izvori napajanja
SISTEM ENERGETSKIH PRETVARAA-Alternativni izvori napajanja
Solarne elije
Trofazni vetrogenerator
Kontrolisani AC-DC i DC-AC pretvarai- Alternativni izvori napajanja
SISTEM ENERGETSKIH PRETVARAA-ELEKTRINA VUA
PREKIDA KAO OSNOVNI ELEMENAT ENERGETSKOG PRETVARAA
U ENERGETSKOJ ELEKTRONICI JE OD MAKSIMALNE VANOSTI
SLEDEE :
Prekidaki elemenat pa i dioda ili ima napon a nema struju ili obrnuto!
Sredine nema!
To ustvari znai ovo:
poluprovodnika komponenta ne sme biti u isto vreme izloena i

spoljanjem naponu i spoljanjoj struji u tom sluaju zbog prevelikog
zagrevanja trenutno dolazi do proboja, tj. razaranja materijala.
Zato se kae da u energetici poluprovodniki pretvarai rade u ON OFF

reimu (SW ukljuen ili iskljuen).
Idealna prekidaka karakteristika

DIODA
Kada je polarizovana direktno, kroz diodu protie relativno velika struja; pad
napona na njoj je, meutim vrlo mali, pa je discipacija snage mala.
Na krajevima inverzno polarizovane diode javlja se veliki napon ali je inverzna

struja dosta mala pa je i discipacija snage vrlo mala.
Proticanja tenosti kroz cev je analogan sluaj (model) provoenju diode.
NEPOVRATNA KLAPNA U CEVOVODU

TRANZISTOR
C
C
B B
E
E
NPN PNP
ANALOGNI MEHANIKI MODEL JE

KONTROLISANA KLAPNA U CEVI U
KOJOJ STRUJI FLUID
TIRISTOR - SCR
ANALOGNI MEHANIKI MODEL
p1 p2
1 2
U smeru jedan (1) tenost moe da protie jedino kada skinemo rezu, a
pritsci su takvi da je p1 > p2 .
Oigledno kada struja tee ne moemo ponovo da stavimo rezu, jedino
ako se spolja ne promene uslovi .
To e se desiti na primer kada protekne struja suprotnog smera.
HIDRAULIKE ANALOGIJE PREKIDAKIH ELEMENTA
IDEALNE KARAKTERISTIKE PREKIDAKIH ELEMENATA
ELEKTRINI PRETVARAI SNAGE
PREDAVANJE -1
POLUPROVODNIKE KOMPONENTE

OSNOVA POLUPROVODNIKA- MONOKRISTAL SILICIJUMA
Si- etvorovalentan el. konfiguracija zadnjeg nivoa : nsnp

KOVALENTNA VEZA-sparivanje elektrona
(a)-monokristal u odsustvu spoljnjeg elektrinog polja (b)-Dejstvo spoljnjeg elektrinog polja

PRIMESNI POLUPROVODNICI
Fosfor-P petovalentan, el. kofiguracija nsnp

Bor-B trovalentan, el. konfiguracija nsnp1
PREDSTAVE POLUPROVODNIKA P i N TIPA
Predstave poluprovodnika, (a)- P tip materijala , (b)-N tip materijala

P-N spoj bez polarizacije
INVERZNO POLARISAN P-N SPOJ
DIREKTNO POLARISAN P-N SPOJ
MATEMATIKE JEDNAINE P-N SPOJA (DIODE)
kT I
VD = ln D + 1
q IS
VD
I D = I S e VT 1 VT =
kT
V T= 26mV
q
Inverzna struja zasienja jako zavisi od temperature

T T1
I S (T ) = I S (T1 ) 2 10
STRUJNO-NAPONSKA KARAKTERISTIKA DIODE
Karakteristike diode, (a)-simbol i vezivanje u elektrinom kolu, (b)-strujno

naponska karakteristika
KONCEPT RADNE PRAVE
+ V AA RI D VD = 0
V VD Kako predstaviti diodu za velike signale, a
I D = AA da se ne koristi nepraktini eksponencijalni
R model volt-amperske karakteristike, ili
grafiki koncept radne prave?
MODEL DIODE ZA VELIKE SIGNALE-direktno
polarisana dioda
V 0.6V
VTO 0.9V . VD = VTO + rd I D
MODEL INVERZNO POLARISANE DIODE
Model-1 Model-2: blagi porast inverzne struje sa

Rr 100k poveanjem inverznog napona zbog
sekundarnih efekata u diodi
Temperaturna zavisnost karakteristike diode
Parametri diode prag provoenja , odnosno inverzna struja zasienja

jako zavise od temperature.
Teorijski inverzna struja zasienja raste ako temperatura T raste za

8% / C (praktino 7% / C), odnosno poraste dva puta za svakih 10
C
Ako je struja diode konstanta, napon na direktno polarisanoj diodi-prag

opada sa porastom temperature.
Pri tom je temperaturni gradijent napona za Si
dV
2.2mV / oC
dT
IDEALIZOVANE KARAKTERISTIKE DIODA
Idealizovane karakteristike dioda, (a)-referntni smerovi,

(b)-model 1, (c)-model 2
v D VTO i D (0,+ )
v D = 0 i D (0,+ )
VTO v D V R i D = 0
i D = 0 v D (0, )
v D VR i D (0, )
KATALOKI PARAMETRI ENERGETSKIH DIODA
INVERZNI NAPONI
VRSM Neponovljivi vrni inverzni napon (moe povremeno da se javi na

diodi; ako se esto javlja degradirae karakteristike diode; esto
se u katalozima sree i oznaka V
DSM
V RRM Ponovljivi vrni inverzni napon (moe se uzastopno

primenjivati bez oteenje diode; esto se u katalozima sree
i oznaka V
DRM
V( BR ) R Probojni napon pri inverznoj polarizaciji; dioda ulazi u proboj i

moe biti unitena; normalno se u eksploataciji energetske
diode ova vrednost nikada ne postie
STRUJE
1 T
I FAV Nazivna srednja vrednost struje voenja I FAV = i F (t ) dt
T 0
Ova jednaina vai za bilo koji talasni oblik struje. Ne sme da se
prekorai ni pri najpovoljnijim uslovima hlaenja
Alternativne oznake I TAV , I DAV

1 T 2
Nazivna efektivna vrednost struje voenja I RMS = i F (t ) dt
I FRMS T 0
I SM Udarna struja u stanju voenja
maksimalna vrna vrednost jedne polovine sinusnog talasa

udarne struje (pri kratkom spoju) u trajanju od 10ms
TOPLOTNI IMPULS DIODE I 2 t

Ova veliina slui pri izboru odgovarajuih ultrabrzih osiguraa
(tip R) za zatitu dioda od oteenja usled prevelikih struja kratkih
spojeva
T
( I 2 t ) diode = Adiode = i D2 dt
0
( I 2 t ) diode ( I 2 t ) ultrabrzog osig

2 2
( I t ) diode = 2( I t ) ultrabrzog osig
KAPACITIVNOSTI U DIODI
Dok se dioda nalazi u stanju voenja, oko P-N spoja se
nalazi nagomilano dodatno naelektrisanje.
Ubrizgani nosioci naelektrisanja se ire u prostor gde je

njihova koncentracija manja
Q D = I D Difuziono naelektrisanje
ID struja kroz P-N spoj
srednje vreme ivota nosilaca naelektrisanja dok se ne rekombinuju

dQ D
Difuzioni kapacitet CD = ID
dV D CD =
VT
zakljuak: dok dioda (P-N spoj) vodi, u njoj se nalazi nagomilano neko
naelektrisanje
KAPACITIVNOSTI U DIODI
Inverzno polarisan P-N spoj
kapacitivnost prostornog tovara
CTO
CT =
VR
3 1+
o
CTO kapacitet pri naponu 0V
VR napon inverzne polarizacije
o ugraeni napon skokovitog P-N spoja (visina

potencijalne barijere)
zakljuak: svaki inverzno polarisan P-N spoj poseduje neki kapacitet

PROBOJNE DIODE Zener diode
PROST STABILIZATOR NAPONA
VS Vo Vo VZ
IS = =
RS RS
IZ = IS IL
Vo
IL =
RL
I Z I Z min
VS VZ VZ
IZ =
RS RL
uslov da bi stabilizator napona radio:
VS VZ VZ
I Z min
RS RL
BRZE DIODE
Ove diode se koriste kao zamajne diode u jednosmernim pretvaraima, kolima za
prenaponsku zatitu i sl. Glavna karakteristika im je da mogu veoma brzo da
preu iz provodnog u neprovodno stanje (kada se inverzno polariu).
Brza dioda u kolu sputaa napona Vs>Vo

Inverzni oporavak brze diode
Povraeno naelektrisanje Qrr
di D VS
Vreme trajanja oporavka diode t rr =
dt L
POVRAENO NAELEKTRISANJE
I RM
t rr = +tf
di F

dt
2Q rr
I RM
t rr
I RM t f
Qf
vreme oporavka t rr 2
di tf t 2f 2Q rr
t rr = g ( I FM , F , T ) t rr = + +
dt 2 4 di F
di F
Q rr = f ( I FM , ,T ) dt
dt
Disipirana energija u diodi u toku jednog gaenja
W1 = Q f VR (0.2....0.4) VR Qrr
Tipovi brzih dioda prema talasnim oblicima struje oporavka
Dioda tipa snap-off je veoma brza

dioda, ali zbog oscilatornog zavretka
procesa oporavka. Ova dioda se manje
koristi u pretvaraima.
Ultrabrza dioda se preporuuje za

korienje u visokofrekventnim
pretvaraima
Postoje otki diode koje umesto P-N spoja

imaju P-metal spoj. One u bre od najbrih
dioda (pod uslovom da su od Si), imaju male
probojne napone (50-100V) i mnogo velike
inverzne struje zasienja (2-10mA).
U poslednje vreme na tehnolokom tritu

poluprovodnika su se pojavile silicijum
karbidne (SiC) diode koje rade na viim
probojnim naponima.
Brze diode pri prelasku iz stanja blokiranja u stanje voenja
U neprovodnom stanju centralno podruje oko P-N spoja je siromano nosiocima

naelektrisanja.
Kada se naponu izvora promeni polaritet, potrebno je konano vreme da

nosioci naelektrisanja stignu iz visoko-dopiranih podruja do centralnog i da ga preplave.
Zakljuak:otpor diode u poetnim trenucima znatan, a pad napona na diodi je vei od

stacionarnog
Disipacija snage u brzim diodama
Ukupna snaga disipacije u energetskoj diodi
PTOT = PFAV + PRAV

disipacije snage u stanju inverzne polarizacije
disipacije snage u provodnom stanju
PROVODNO STANJE:
Trenutna vrednost snage gubitaka usled voenja p F = (VTO + rd i F ) i F
Srednja vrednost snage gubitaka usled voenja
1 T 1 T

PFAV = p F (t ) dt = VTO i F dt + rd i F dt
2
T 0 T 0T 0
PFAV = VTO I FAV + rd I FRMS
2
INVERZNA POLARIZACIJA
GUBITCI
PRAV = f VR (Q f + I RO t R )
tR = T t p
2Q rr2
Q f = Q rr (0.2....0.4) Qrr
di
2( F )
dt
Redno vezivanje dioda
Diode se pri inverznoj polarizaciji ponaaju kao veoma velika

otpornost (reda vie M). Zbog razlike u inverznih karakteristika
dioda, ove otpornosti se mogu znatno razlikovati.
Ovaj problem se reava paralelnim vezivanjem otpornika dovoljno

visoke otpornosti da ne predstavlja problem njihovo zagrevanje, a
opet i dovoljno niske, da se pravilno raspodele naponi na diodama
PARALELNO VEZIVANJE DIODA
Paralelnim vezivanjem dioda postie se rad sa viim direktnim strujama
U paralelnoj vezi imamo zajedniki napon na

diodama.
Zbog razlike karakteristika raspodela struja moe

biti veoma razliita
Problem bi se mogao reiti vezivanjem malih

otpornosti na red sa diodama, meutim zbog velikih
gubitaka na otpornicima ta tehnika se samo
delimino primenjuje
Reenja:
-geometriji spojnih provodnika kojima se vezuju diode

-reaktanse u obliku pogodno oblikovanih spojnih vodova
-feritnih prstenova oko provodnika
-klasiranjem dioda prema direktnom padu napona
Bipolrani tranzistori-BJT
Bipolar Junction Transistor NPN ili PNP
Tehnoloki gledano, emitor je vrlo jako dopiran, baza neto slabije, a

kolektor dvojako - slabo u blizini BC spoja, a jae u blizini odvodne
elektrode
Rad BJT-a zasniva se na injekciji naelektrisanja iz emitora u bazu
OSNOVNI REIMI RADA TRANZISTORA
BJT u reimu zasienja
Osnovno kolo sa BJT, (a)-elektrina ema , (b)-elektrini simbol i njegov diodni ekvivalent
VCE = VCC RC I C Sa porastom struje baze , raste i struja kolektora ,

tako da u jednom trenutku napon B-E postaje
V BB 0.7V
IB =
RB VBE VCC RC I C = VCC RC I B
IC = I B U tom sluaju spoj C-B postaje direktno polarisan i
tranzistor ulazi u zasienje
Strujno pojaanje BJT
IC
=
IB
Kako postii vee strujno pojaanje pri veim strujama?
Jedan od naina je korienje tranzistora u tzv. Dralington spoju

Darlington spoj BJT
1 1
I C1
2 1 1 =
I B1
IC2
2 =
I B2
I E1 = 1 I B1 + I B1 = ( 1 + 1) I B1 I E1 = I C1 + I B1
I C = I C1 + I C 2
I E1 = I B 2 I C 2 = 2 ( 1 + 1) I B1
I C = 1 I B1 + 2 ( 1 + 1) I B1
IC
D = 1 2
I B1
Praktina realizacija Darlington sprege
(a)-otpori za zatvaranje struja curenja, (b)-ubrzavanje gaenja.

Statike karakteristike BJT
Ulazna statika karakteristika BJT
Ulazno kolo tranzistora (spoj B-E) je

poluprovodnika dioda, pa su i
statike krive
I B = I B (VBE )
sline volt-amperskim
krivama diode, ali je vaan i
uticaj parametra V
CE
VBE VCE spoj BC je propusno je polarisan, to znai da i kolektor injektira naelektrisanje u bazu,
te time dobijamo velike struje baze
VBE VCE spoj B-C polarisan je nepropusno, te I B = I B (VBE ) slabo zavisi od VCE
Izlazne karakteristike BJT
zona aktivnog reima rada.
Izlazna statika karakteristika BJT

PREKIDAKA KARAKTERISTIKA BJT
(a)-realna, (b)-idealna
I C 0 VCE = 0
VCE 0 I C = 0
Analiza prekidakog reima BJT (UKLJUENJE)
(a)-prekidako kolo, (b)-ukljuenje, (c)-iskljuenje

tud vreme kanjenja (delay time)
U toku ovog vremena se puni kapacitet spoja B-E, pa je ovo vreme odreeno strujom punjenja i veliinom datog kapaciteta CBE
tur vreme porasta struje pri ukljuenju (rising time)

Ovo vreme je upravo potrebno da manjinski nosioci na putu kroz bazu stignu do kolektorskog spoja
U toku ovog vremena dakle dolazi do akumulacije manjinskih nosilaca u bazi i do porasta njihovog gradijenta koncentracije,
pa tako i raste struja kolektora do svoje ustaljene vrednosti
tu vreme ukljuenja
=
tud + tur
Analiza prekidakog reima BJT (ISKLJUENJE)
(a)-prekidako kolo, (b)-ukljuenje, (c)-iskljuenje
tis -vreme nagomilavanja (storage time)

U ovom intervalu dolazi do evakuacije nagomilanih akumulisanih naelektrisanja. Obino se u ovom intervalu vri prvo
rastereenje baze odvoenjem vika nosilaca naelektrisanja.
tif -vreme opadanja (fall time)

Nakon evakuacije vika nosilaca naelektrisanja se menja gradijent manjinskih nosilaca, odnosno sa njegovim
padom opada i struja kolektora. Drugim reima bazno podruje se skuplja do svojih metalurkih granica
ti vreme iskljuenja
=
tis + tif
U reimu voenja (on-state)
napon na spoju C-E je jednak u CE ( SAT )
struja kolektora IC = I0
Snaga gubitaka u ovom sluaju je jednaka
.
PON = uCE ( SAT ) I o
OBLAST SIGURNOG (BEZBEDNOG RADA TRANZISTORA)
Oblast dozvoljenog rada BJT odnosno SOA (Safe Operating Area)
Ogranienja maksimalne snage disipacije
Ogranienje zbog sekundarnog proboja

(kada dolazi do lokalnog fokusiranja struje i unitenja kolektorskog spoja)
MOSFET- tranzistori
SIMBOL
STRUKTURA N-KANALNOG MOSFET-a

KARAKTERISTIKE MOSFET-a
(a)-ulazna karakteristika, b)-izlazna karakteristika

Osnovno prekidako
kolo sa MOSFET-ima
talasni oblici pri ukljuenju i iskljuenju

Oblast bezbedbog rada jednog tipinog energetskog
MOSFET-a
TIRISTOR SCR (Silicon Controlled Recttifier)
Tiristor je etvoroslojna poluprovodnika upravljiva komponenta sa izvedene tri
elektrode : pored anode (A) i katode (K) postoji i upravljaka elektroda - gejt (G).
Osnovu predstavlja
etvoroslojna
P-N-P-N struktura
Pojava tiristora, krajem pedesetih godina

(1956. Belove laboratorije), omoguila je
izradu regulisanih ispravljaa i drugih vrsta
pretvaraa, tako da su veoma brzo
potisnuli do tada koriene prekidae -
transduktore
DIAC- DIode Alternating Current
Dijak je petoslojna P-N-P-N

poluprovodnika komponenta sa
izvedene dve elektrode (A1 i A2).
Naponsko strujna karakteristika mu je

takva da praktino ne provodi struju
do probojnog napona (oko 30 V).
Probojni napon je problino jednak za

oba polaritetanapona.
INVERZNO POLARISANA P-N-P-N STRUKTURA
U AK < 0
kroz strukturu tee veoma
mala inverzna struja
I RO 0.
unutranji P-N spoj 2 je

direktno polarisan, ali u na
njemu nema nosioca
naelektrisanja.
DIREKTNO POLARISANA P-N-P-N STRUKTURA
Direktno polarisani tiristor moe da

se nalazi u dva stabilna stanja:
provodnom i neprovodnom
Ako napon U D poraste do vrednosti

probojnog napona u direktnom smeru
U D ( BR )
dolazi do lavinske multipilkacije parova
elektron-upljina u ispranjenoj zoni
oko centralnog P-N spoja.
Tiristor se prevodi u provodno stanje tako to se:
-direktno polarie
-dovede impuls struje na gejtu
-dok traje impuls struje na gejtu, struja tiristora mora da postane
vea od struje hvatanja (latching current)
IL
Tiristor ostaje u provodnom stanju sve dok je jegov struja vea od struje
dranja (holding current)
IH
Dok tiristor vodi, oko centralnog P-N spoja postoji
nagomilano neko naelektrisanje koji je jednako:
Q = Q p + Qn
tiristor moe prevesti u provodno stanje i osvetljavanjem centralnog P-N,
Pravilan nain prevoenja tiristora u provodno stanje je ubrizgavanjem struje u

gejt
Tranzistorska analogija tiristora
= IC / I E
= IC / I B
I E = IC + I B
IE 1
= = 1+
IC

=
1+
Zavsinost strujnih pojaanja i od temperature i struje kolektora

=
1+
Tranzistorska analiza tiristora
I A = I C1 + I B1 + I CBO1
I I A = 1 I A + I B1 + I CBO1
1 = C1
IA I A (1 1 ) I CBO1 = I B1 = I C 2
I C 2 = 2 I K + I CBO 2
IC2 I A (1 1 ) I CBO1 = I C 2 = 2 I K + I CBO 2
2 =
IK
I K = I A + IG I A (1 1 ) = 2 I A + 2 I G + I CBO1 + I CBO 2
2 I G + I CBO
IA =
1 1 2
Volt-Amperska karakteristika tiristora
Da bi se tiristor ukljuio potrebno

je da struja bude vea od
takozvane struje prihvatanja
(latching current )
150 mA (za tiristore reda 10A)
oko oko 1.5 A (za tiristore reda 1000 A)
Pri smanjenju struje, u jednom trenutku tiristor ponovo 80 mA (za tiristore reda 10 A) do
oko oko 0.5 A (za tiristore reda
postaje neprovodan. Ova minimalna struja naziva se i 1000 A)
struja dranja (holding current )
Volt-Amperska karakteristika DIAC-a
Probojni napon je problino jednak za oba polariteta napona.
Prestanak voenja struje nastaje kad ona padne ispod struje dranja
(a)-strujno kolo, (b)-strujno naponska karakteristika

Kada tiristor pree u stanje voenja, struja tiristora praktino zavisi od spoljnjeg
kola (optereenja).
U tom sluaju njegova volt-amperska karakteristika se moe priblino predstaviti
pravom linijom (slino kao kod energetske diode ili DIAC-a).
Volt-Amperska karakteristika gejta
granina kriva
maksimalni dozvoljeni maksimalna

napon gejta dozvoljena disipacija
gejta
granina kriva
minimalni napon
gejta pri kome se
tiristor sigurno maksimalno
prevodi u dozvoljena struja gejta
provodno stanje
minimalna struja gejta

pri kojoj se tiristor
prevodi u provodno
stanje
Koncept radne prave primenjen na kolo gejta tiristora
VCC V g
Ig =
Rg
Radna prava u moguoj radnoj oblasti gejta
Potrebno vreme trajanja upravljakog impulsa kod razliitih
strmina struje optereenja
Struja gejta, obino je reda 50 mA

za male tiristore, dok je za velike
tiristora 300-400mA.
Trajanje impulsa treba da bude
nekoliko desetima mikrosekundi.
Kod ukljuenja omskog
optereenja trajanje impulsa na
gejtu je znatno krae nego u
sluaju induktivnog optereenja.
U sluaju induktivnog tereta
(struja se sporo uspostavlja),
impuls treba da traje sve dok
struja optereenja ne premai
vrednost struje prihvatanja
Dinamike karakteristike tiristora-ukljuenje
tz vreme kanjenja ukljuenja (reda 1us)
tp vreme porasta struje (nekoliko us)
t on vreme ukljuenja
Parazitna kapacitivna struja koja moe ukljuiti tiristor
Tiristor u provodno stanje moe da prevede i brzi porast napona u direktnom smeru
Ustvari kapacitet inverzno polarisanog

sentralnog P-N spoja moe da propusti
struju ija je jaina
dU AK
CCB
dt
Tipine vrednosti su u opsegu od 200 ...
1000 V/us
Prevelika brzina porasta struje di/dt moe neeljeno ukljuiti tiristor
Impuls na gejtu aktivira odreenu zonu na kristalu tiristora. Ova zona se

vremenom iri na celu povrinu
Tipine vrednosti su u
opsegu od 200 ... 1000 V/s
Potrebno je odreeno vreme da se provodna zona proiri od kontakta gejta

po celoj povrini tiristora.
Ako je optereenje isto omsko ili kapacitivno, struja pri ukljuenju veoma brzo
raste i njena gustina na aktiviranom delu povrine moe biti previsoka tako da
moe doi do razaranja tog dela kristala i trajnog oteenja tiristora, zbog
lokalnog pregrevanja
Zatite protiv prevelikog porasta struje i napona na tiristoru
ISKLJUENJE TIRISTORA
Najei nain iskljuivanja tiristora je promena polariteta anodnog napona.
Pri tome treba saekati odreeno vreme koj se u strunoj praksi
naziva "vreme odmaranja", a obeleava se sa t q
To je vreme koje je potrebno da se rekombinuju naelektrisanja u okolini
centralnog P-N spoja tiristora, koji je bio u stanju voenja
Ovo vreme se rauna od trenutka prolaska struje tiristora kroz nulu, do
trenutka kada moe ponovo da primi direktan napon
tq = trr + toff
Kod brzih tiristora koji se koriste u

invertorima i operima deklarie se
gornja granina vrednost za i
ona iznosi od 20s....60s.
Kod sporih tiristora koji se koriste u

ispravljaima, za se daje tipina vrednost
i obino iznosi 100s....300s.
TIRISTOR- kao idealan prekida
Pretpostavke:
-U analizama rada pretvaraa tiristor e biti posmatran kao bistabilni prekidaki
elemenat koji moe biti u stanju ukljuenosti ili iskljuenosti
-Struja prihvatanja i struja dranja jednake nuli IL=0 i IH=0
-Inverzna struja i napon u provodnom stanju jednaki nuli
-Vremena ukljuenja i iskljuenja jednaka nuli
- Idealizovana karakteristika tiristora
HIDRAULIKE
ANALOGIJE
PREKIDAKIH
ELEMENTA
-dioda
-tiristor
-tranzistor
Osnovno prekidako kolo sa tiristorom
Okidni impulsi na gejtu ig

sinhronizovani su sa mrenim
naponom u
Kontrolna veliina je ugao ukljuenja

Ugao se rauna od trenutka
kada su se stekli uslovi da provede tiristor
a to je prolazak mrenog napona kroz nulu

ISPITIVANJE TIRISTORA
ELEKTRINI PRETVARAI SNAGE
VISER- studijski program NET
PODEAVAI
NAIZMENINOG
NAPONA
POLUTALASNI DIODNI ISPRAVLJA
2
1 1 2
V AVG =
2
t = 0
v d d ( t ) =
2 t =0
2V sin( t ) d ( t ) =

V = 0,45V
IAVG = VAVG / R
POLUTALASNI TIRISTORSKI ISPRAVLJA

1 2
V AVG ( ) =

t=
2V sin(t )d (t ) = (1 + cos )
2
V
IAVG = VAVG / R
POLUTALASNI DIODNI ISPRAVLJA SA INDUKTIVNIM
OPTEREENJEM
di
v S = Ri + L
dt
Rt
2V
id = sin( t ) + Ae L
Z
2V 2VL
A= sin =
Z Z2
Z= R 2 + ( L ) 2
L
= tan 1 ( )
R
POLUTALASNI TIRISTORSKI ISPRAVLJA SA INDUKTIVNIM OPTEREEN
R
2V (t )
id = sin(t ) e L
sin( ) za t .
Z
Za isto induktivno optereenje (R=0)
2V
id = [ sin(t ) sin( ) ]
L 2 2
2V
id = [ 1 cos(t ) ] za =0
L
TA SE DEAVA AKO SE PODEAVA NAPONA SA JEDNIM TIRISTOROM
OPTERETI SA R-L POTROAEM?
TIRISTOR POINJE DA VODI U TRENUTKU / ALI STRUJA NE PADA U NULU U
TRENUTKU t=T/2
ZBOG POSTOJANJA INDUKTIVNOSTI U ENERGETSKOM KOLU PRODUAVA SE VREME

VOENJA PREKO T/2 (mora da se ukloni energija nagomilana u magnetnom polju L!!!!)
PODEAVA NAPONA SA JEDNIM TIRISTOROM I ISTO
INDUKTIVNIM OPTEREENJEM
-INTERVAL VOENJA STRUJE POINJE KADA TIRISTOR DOBIJE IMPULS NA GEJTU I TRAJE
DOK NE NESTANE STRUJA U INDUKTIVNOSTI.
-INTERVAL VOENJA JE SIMETRIAN OKO TRENUTKA t=T/2
KADA TIRISTOR UE U STANJE VOENJA PO II KIRHOFOVOM ZAKONU MOE SE NAPISATI

DIFERENCIJALNA JEDNAINA:
Ovo je jednaina impulsa struje koja
tee kroz tiristor T1.
Kada prestaje da tee struja?
Kada je :
poetni uslov je iL =0 za t=/, odnosno:
Jedno reenje je trivijalno:
Drugo reenje je:
Odnosno
ODGOVARAJUA EFEKTIVNA VREDNOST NAPONA BIE PUTA

VEA OD ONE KOJA SE IMA U SLUAJU OTPORNOG OPTEREENJA R
(zbog talasnog oblika koji sadri dva dela iste povrine)
POLUTALSANI ISPRAVLJA SA POVRATNOM (ZAMAJNOM) DIODOM
didI
vS = RidI + L di dII
dt 0 = Ri dII +L
dt
2 VS 2 VS (t ) RL
idI = sin(t ) + idI ( ) sin( ) e ( )
R
Z Z
idII = idI ( ) e L
KADA JE INDUKTIVNOST OPTEREENJA DOVOLJNO VELIKA DA SE MOE SMATRATI
BESKONANOM, OPTEREENJE MOEMO PREDSTAVITI STRUJNIM PONOROM Io.
MONOFAZNI PUNOTALASNI NAIZMENINI PRETVARA (omsko
optereenje)
- kanjenje paljenja od trenutka

kada tiristor moe da provede
-Zbog prirode potroaa struja prati oblik napona na potroau.

-Pri prolasku napona izvora kroz nulu dolazi do gaenja tiristora jer struja
potroaa pada na nulu.
-Za =0, napon izvora se u celosti prenosi na potroa.
-Kada raste, napon na potroau se smanjuje.
1) Efektivna vrednost napona
potroaa
Trenutna vrednost napona na potroau
je:
Efektivna vrednost napona potroaa je:
2) Snaga na potroau je:
za
3) Srednja vrednost struje tiristora
srednja struja tiristora je maksimalna za =0 i iznosi:
za = srednja vrednost je:
4) Efektivna vrednost struje tiristora
za =0, efektivna vrednost struje

tiristora je maksimalna i iznosi:
5) Efektivna vrednost struje potroaa je:
Dakle, struja kroz svaki od tiristora je 1,41 puta manja od struje potroaa.
Za =0 je odnos srednje i efektivne vrednosti struje tiristora:

MONOFAZNI PUNOTALASNI NAIZMENINI PRETVARA
(induktivno optereenje)
-Zbog prisustva induktivnosti u potroau, kada upalimo tiristor struja ne moe

trenutno promeniti vrednost, ve poinje da raste od nule.
-Iz istog razloga se tiristor ne gasi pri prolasku napona potroaa kroz nulu jer
struja nastavlja da tee.
-Za kolo moemo postaviti sledeu jednainu:
Reenje ove jednaine je izraz za struju:
Gde je:
Interesuje nas ugao pri kome struja kroz potroa prestaje da tee i tiristor
se gasi.
Taj ugao se nalazi reavanjem jednaine:
-Ako upalimo tiristor u trenutku , vidimo da e struja kroz potroa tei za <t<.
-Zatim se tiristor gasi i struja poinje ponovo da tee kad se upali drugi tiristor.
-Postojae neki ugao paljenja k za koji e struja potroaa biti neprekidna,
odnosno za koji e se trenuci gaenja jednog i paljenja drugog tiristora poklapati.
To znai da je:
Vrednost za k se nalazi gornjom smenom za k u izrazu za struju potroaa i
reavanjem jednaine:
Dakle za < < , struja e biti prekidna.
Za = struja potroaa e biti neprekidna i sinusnog oblika datog izrazom:
to znai da e struja potroaa kasniti za naponom izvora za ugao .
ta e se desiti za 0 < < ?

Za 0 < < e oblik struje potroaa zavisiti od naina na koji pobuujemo
tiristore.
Ako ih kao do sad palimo impulsom u gejtu, moe se desiti da kad
pobuujemo gejt tiristora uslovi za njegovo provoenje ne postoje jer provodi
onaj drugi, a kad se uslovi steknu impuls paljenja je proao.
Tada se tiristor nee uopte upaliti (kao to pokazuje slika).
Dakle, struja e tei samo u jednom smeru i imati neeljenu jednosmernu

komponentu.
1) Efektivna vrednost napona na potroau
- ugao paljenja tiristora, - ugao gaenja tiristora
Ova efektivna vrednost napona potroaa je vea nego u sluaju da je

potroa ista otpornost jer je > .

Struje tiristora su maksimalne za = .
4) Faktor snage
Zbog prisustva induktivnosti u potroau postojae i aktivna i reaktivna
snaga.
Faktor snage se definie kao odnos aktivne i prividne (ukupne) snage.
Za prostoperiodine reime, faktor snage je tesno povezan sa uglom
impedanse - :
Za sloenoperiodine reime (kad su signali prekidni) ova veza vie ne

vai i ugao impedanse se ne sme povezivati sa reaktivnom snagom.
Tada se faktor snage mora izraunavati po definiciji:
MONOFAZNI PUNOTALASNI NAIZMENINI PRETVARA
(potroa je isto induktivno optereenje)
-Kada tiristor upalimo u uglu , struja kroz induktivnost se ne moe trenutno

promeniti kao to je to bio sluaj kod isto otpornog potroaa.
-Struja raste od nulte vrednosti sve dok napon ima pozitivnu vrednost.
-Kada napon na induktivnosti promeni znak, tiristor se ne gasi jer kroz njega jo
tee struja.
-Znai da tiristorom ne moemo upravljati nezavisno od prirode potroaa, kao
to je to sluaj sa tranzistorom.
-Kada napon na induktivnosti postane negativan, struja poinje da opada.
-Interesuje nas ugao pri kome e vrednost struje kroz induktivnost pasti na
nulu.
-Zbog simetrije u odnosu na ugao , vidi se da je:
Ovu tvrdnju moemo dokazati nalaenjem izraza za struju induktivnosti u

zavisnosti od ugla paljenja :
Postavljanjem uslova da je vrednost struje u uglu jednaka nula,
dobijamo:
Da bi se drugi tiristor upalio mora se prvi ugasiti. Ugao gaenja prvog

tiristora mora biti manji od ugla +, kad palimo drugi tiristor.
Znai, ako elimo simetrino paljenje tiristora ugao paljenja moemo

smanjivati samo do /2.
1) Efektivna vrednost napona na potroau


TROFAZNI PODEAVAI NAIZMENINOG NAPONA
Trofazni sistem se zasniva na trofaznom generatoru koji generie napone fazno
pomerene za 3/2, tj. 120o.
Potroa se moe spregnuti u "zvezdu" ili "trougao".

Potroa u sprezi "zvezda"
Interesuje nas struja i napon potroaa.

U trofaznim sistemima sve izraavamo preko linijskih
napona i struja jer njih moemo da merimo. Imaemo
da je:
Snaga potroaa je:

Potroa u sprezi trougao"
Napon na svakom potroau je jednak linijskom

naponu (meufaznom).
Struje kroz potroae su fazno pomerene i

primenom Kirhofovih pravila i fazorskog
dijagrama se dobija
Snaga potroaa je:
Dakle, bez obzira na spregu potroaa, zavisnost snage potroaa od linijskih

struja i napona je ista.
To znai da merenjem linijskih napona i struja moemo stei utisak o snazi
potroaa.
Trofazni punotalasni naizmenini pretvara sa potroaem u spoju
"zvezda"
- sa nultim provodnikom
-Ovaj sluaj je identian sluaju kad imamo
tri posebna monofazna podeavaa, pa ga
tako i analiziramo.
-Da bi potekla bilo koja od linijskih struja iz
faza potrebno je da je ukljuen barem 1 od
ovih 6 tiristora.
-Ovo je mogue zbog postojanja nultog
provodnika kuda struja moe da se zatvori.
-Kad su sve tri grane provodne struja kroz
nulti provodnik je:
- bez nultog provodnika
-U ovom sluaju da bi protekla bilo kakva
struja kroz potroa moraju biti provodne
najmanje 2 grane.
-Ako je provodna samo jedna grana

(ukljuen samo jedan tiristor) struja kroz
potroa nee tei jer nema kuda da se
zatvori (nema nultog provodnika).
-Ako su provodne 2 grane tada e

prikljueni linijski (meufazni) napon
napajati 2 grane potroaa, pa je na
svakom potroau napon: Ul/2
Linijski naponi su:
Ako su sve 3 grane provodne situacija je kao da imamo nulti provodnik, jer je napon
zvezdita nula. Tada su na svakom od potroaa fazni naponi uR, us, uT koji su u
odnosu na meufazne napone uRS , uST, uTR fazno pomereni za /6. Struje kroz
potroae su istovremeno i linijske i u fazi su sa faznim naponima uR, us, uT
PRIMERI TROFAZNIH VEZA (REGULACIJA SNAGE ELEKTRO OTPORNIH PEI)
Pri vezi u zvezdu sa izvedenim zvezditem

trofazna
Sprega se svodi na tri monofazna podeavaa
napona
sa antiparalelnim tiristorima.
Kod veih snaga antiparalelni tiristori se

vezuju
u trougao
Pri sprezi antiparalelnih tiristora u trouglu

manja je srednja i efektivna vrednost struje
kroz jedan tiristor, u odnosu na spregu
zvezda, i to 1.73 puta.
REGULACIJA REAKTIVNE SNAGE
Brza ili dinamika regulacija
IZVODI SE NA SREDNJE NAPONSKOM NIVOU (6kV, 10kV i 35kV)

UREAJI ZA MEKANO UPUTANJE ASINHRONIH (kaveznih)
MOTORA SOFT STARTERI
Tipine karakteristike asinhronog motora u

funkciji broja obrtaja n:
-momenat M(n)
-struja I(n)
Karakteristika optereenja motora (radne maine):
ns-sinhrona brzina -momenat ML(n)
f-uestanost
p-broj pari polova
DIREKTNI UPUTA (ELEKTRO MEHANIKI PREKIDA)
napon motora
UPUTA zvezda-trougao (elektro mehaniki)
napon motora
ELEKTRONSKI UPUTA (naizmenini podeava napona-antiparalelna tiristorsk grupa)
napon motora
podeljivi su
napon starta Uboost i
vreme rampe tramp
TROFAZNE VARIJANTE TIRISTORSKIH UPUTAA (JEDNOPOLNA EMA)
ANTIPARALELNA VEZA TIRISTORA U SVAKOJ FAZI
ANTIPARALELNA VEZA TIRISTORA U SVAKOJ FAZI,

SVAKA OD GRUPA IMA BY-PASS SA PREKIDAEM
KAD SE ZAVRI STARTOVANJE PREKIDA PRESPAJA
TIRISTORSKU GRUPU, TAKO DA SE SMANJUJU
ZNAAJNO DISIPACIONI GUBICI
OTPOR PREKIDAA ~ 1m -3m
PAD NAPONA TIRISTORU 1V-2V
DVE ANTIPARALELNE VEZE TIRISTORA

ZA REVERZIRANJE MOTORA
DVE ANTIPARALELNE VEZE TIRISTORA

ZA REVERZIRANJE MOTORA, SVAKA OD
GRUPA IMA BY-PASS PREKIDA
VARIJANTA TROFAZNOG UPUTAA SA TIRISTORSKIM GRUPAMA U DVE FAZE
NIJE DOZVOLJENO!!!!!
ZATO??????
VARIJANTA TROFAZNOG UPUTAA SA TIRISTORSKIM GRUPAMA U SVE TRI FAZE
UOITI MANJI GABARIT

UPUTAA
TIPINE KARAKTERISTIKE ASINHRONOG MOTORA PRI STARTU
SA KORIENJEM TIRISTORSKOG SOFT STARTERA
STRUJA MOMENAT
MOMENAT PRI PUNOM
NAPONU
MOMENAT PRI SNIZENOM

NAPONU
U
MOMENAT OPTEREENJA
(RADNE MAINE)
OGRANIENJE POLAZNE STRUJE

MOMENAT JE PROPORCIONALAN U
MANA: POLAZNI MOMENAT JE MALI
LINIJSKI NAPON I NJEGOVA ZAHTEVANA PROMENA
-Talasni oblik linijskog napona trofaznog asinhronog -Promena napona statora motora po
motora uz korienje regulacije napona. unapred zadatoj vremenskoj rampi.
-Promenom ugla regulacije menja se efektivna -Uvek postoji neki poetni napon,
vrednost napona na prikljucima motora da bi se ostvario polazni momenat.
NEKE TIPINE KARAKTERISTIKE POGONA SOFT STARTER +ASINHRONI MOTOR
-Tipini grafik momenta i struje asinhronog -Grafik momenta motora u zavisnosti od vrednosti
motora u zavisnosti od broja obrtaja prilikom napona napajanja
direktnog putanja motora u praznom hodu. -Uoava se uticaj promene efektivne vrednosti
-Polazna struja skoro 6 puta vea od nominalne. napona napajanja na momenat motora.
-Uticaj na struju motora, pri nekom zadatom
klizanju, je direktno proporcionalan.
ISPRAVLJAI ZA GALVANIZACIJU (OPCIJE TIRISTORSKE GRUPE)
SA JEDNIM
TIRISTOROM
SA DVA
TIRISTORA
(ZAJEDNIKE KATODE)
TRIAC
ZA MANJE
STRUJE DO 50A
MOGU SE KORISTITI U TROFAZNIM ILI MONOFAZNIM VEZAMA

ISPRAVLJAI ZA NAPAJANJE ELEKTROSTATIKIH FILTERA PREIAVANJE
DIMNIH GASOVA NA TERMOELEKTRANAMA
Podeavai napona se koriste i kod VN ispravljaa-ELEKTROSTATIKI IZDVAJAI

odnosno elektrostatiki filtri
Tipina vrednost napona elektrodnog sistema filtra je 40kV..100kV
Tipina vrednost struje 1-2A
Regulacija izlaznog napona se vri antiparalelnom vezom tiristora.
-Elektrostatiki filteri su komore kroz koje prolazi dimni gas iz loita kotla
i on je pun leteeg pepela
-Sadre viskonaponske jedinice za izdvajanje estica u dimnom gasu (oko 60%
sastava dimnog gasa ine estice, ostalo su oksidi sumpora, azota i sl.)
-Sade otresae za otresanje izdvojenog pepela sa elektroda
-Odvajanje svih pomenutih tipova vrstih produkata se ostvaruje jakim
elektrostatikim poljem koje se formira u izdvajakim komorama
-U izdvajakim komorama se nalaze dve vrste elektroda: talone i emisione,
kao i ureaji za otresanje izdvojenih estica sa talonih elektroda
Zidovi komora i talone elektrode (u vidu
metalnih zavesa od talasastog lima) su Emisione elektrode (ramovi sa
pozitivne elektrode. icom ili nizovi cevi sa iljcima su
negativne elektrode.
Negativne elektrode oko sebe generiu koronu koja naelektrisava estice

leteeg pepela, koje zatim idu prema talonoj elektrodi gde se sakupljaju i uklanjaju.
Emisione elektrode
Talone elektrode
TIRISTORSKI PRETVARA za regulaciju napona elektrostatikih filtara
Napon napajanja je 0.4kV; Regulacija se vri antiparalelnom vezom tiristora Th1 i Th2.
Podeavanjem njihovog ugla paljenja , visoki jednosmerni napon na elektrodama
filtra se dri tik ispod proboja. Prigunica L1 i otpornik Rx ograniavaju struju kratkog spoja
(kad se desi proboj ili kvar).
Diodni ispravlja je napravljen sa etiri grupe redno vezanih dioda (zajedno sa paralelnim
elemantima za izjednaavanje potencijala du lanaca dioda).
Redno vezane diode , prigunica L1 i VN transformator se nalaze u istom sudu sa uljem.
PRAKTINA REALIZACIJA UPRAVLJAKOG DELA
ELEKTROSTATIKIH FILTARA
NAPONSKA
REGULACIJA
i
DETEKCIJA
KORONE
Nakon ukljuenja ispravljaa (trenutak t1) , napon vrlo brzo postie granicu probojnog napona.
U trenutku t2 dolazi do preskoka, pa se izlazni napon sputa za regulisanu vrednost (-dU/dt).
Vremenski interval t2-t1 predstavlja vreme putanja filtra u pogon.
Nakon toga napon ponovo raste do granice proboja regulisanom brzinom (+dU/dt).
Ako se desi da se granica probojnog napona smanji, regulisanim ispravljaem se osigurava rad u blizini probojnog
napona.
U trenutku t3 dolazi do strujnog preoptereenja filtra,to se detektuje u struji na primarnoj strani (I>1,2In), kada
dolazi do iskljuenja i trajanje prekida usled prekoraenja za oko 80ms (interval t3-t4) i redukcije napona u odnosu
na to prekoraenje za U2.
U trenutku t5 dolazi do formiranja elektrinog luka izmeu filtarskih elektroda, koji se odrava do trenutka t6. Ovo
trajanje je reda veliine 200ms. Nakon ovog vremenskog intervala, regulator obezbeuje sputanje izlaznog napona
na nulu i vri se deblokiranje rada ispravljaa (interval t7-t6).
U ovom intervalu se obezbeuje gaenje elektrinog luka procesom dejonizacije. Nakon ovog intervala se ponovo
podie napon i uspostavlja normalni reim rada. Novouspostavljena vrednost napona je odreena pomenutim
uslovima u filtru i ona je nia od prethodne vrednosti tako da U3 predstavlja redukciju nakon gaenja elektrinog
luka.
EKSPERIMENTALNI REZULTATI-Merenja u realnim eksploatacionim uslovima
Vizuelno praenje izlaznog dima; (a)-VF napajanje, (b)-iskljueni ESI, (c)- 50Hz-no
napajanje (antiparalelna veza tiristora)
FAZNO UPRAVLJANJE SA TRIJAKOM: Okidno kolo s dvosmernim
regenerativnim prekidaem
VI
V
V
Talasni oblici napona na ulazu VI, optereenju Vo i kondenzatoru V1.

Faznim upravljanjem ukljuuje se napon na optereenju pri odreenim faznim uglovima.
Tok snage se moe podesiti izmeu 0-100%. Potroai iznad izvesnih graninih snaga
smeju biti u pogonu samo uz posebnu dozvolu, jer fazno upravljanje proizvodi povratna
dejstva na mreu reaktivna snaga
FAZNO UPRAVLJANJE SA TRIJAKOM
OSVETLJENJEM I KOMUTATORNIM MOTOROM
Ukljuuje optereenje kod prolaska napona kroz nulu
NULTA SKLOPKA Upravljanje optokaplerom
Elektronski poluprovodni releji
Prednosti:
-galvansko odvajanje
upravljakog kola i
optereenja
-ukljuivanje bez
odskakivanja
-dug vek upotrebe
-neznatne radio
smetnje
-velika brzina
ukljuivanja
PRIMER:
Elektronski relej za
AC struje 1-40A
Upravljaki napon
3-30V DC
UPRAVLJANJE PAKETOM OSCILACIJA
Nulte sklopke koje ukljuuju optereenje nakon podeenog broja perioda naizmeninog napona deluju kao
da su upravljane paketom oscilacija, odnosno kao puno-talasno upravljane.Srednja primljena snaga
optereenja moe iznositi 0-100%.
PREDNOSTI:
-nema oscilacija u mrei jer je struja
sinusoidna
-nema upravljake reaktivne snage jer je
faktor snage jednak 1
NEDOSTACI:
-nije prikladno za rasvetu zbog treperenja
-nije prikladno za pogone zbog trzanja
PRIMENA: regulacija grejanja I
temperature
(pei za topljenje, suionice, maine za
arenje ice i odlivaka, maine za obradu
plastike)
T=1/f
Ts=tE +tP
P=(tE/Ts)Pmax
Pmax=U/R
TIPINA KARAKTERISTIKA TERMIKE OBRADE ARENJEM METALNIH
ODLIVAKA (na pr. lopatica mlinova za ugalj na termoelektranama)
temperaturno-vremenski dijagram
1.Maksimalna temperatura zagrevanja bez

regulacije
2.Brzina kontrolisanog zagrevanja (tipino je
+100C/h)
3.Maksimalna emperatura kontrolisanog
zagrevanja (temperatura na kojoj se metalni
deo ari zadato vreme)
4.Vreme trajanja procesa arenja
5.Brzina kontrolisanog hlaenja (tipino je -
200C/h)
6. Minimalna temperatura kontrolisanog
hlaenja
7. Slobodno hlaenje do sobne temperature
MIKROPROCESORSKA KONTROLA ELEKTRO-OTPORNOG
ZAGREVANJA METALNIH DELOVA -principijelno elektrino kolo
MOGUI NAINI KONTROLE ELEKTRO-OTPORNOG ZAGREVANJA
KONKRETNA REALIZACIJA
EKSPERIMENTALNI SNIMCI
Zapis temperaturnog profila zagrevanog uzorka na X-Y pisau

Zapis temperaturnog profila zagrevanog
uzorka na industrijskom pisau
Osciloskopski
snimak
oblasti III
ENERGETSKI PRETVARAI
ZA KOMPENZACIJU
REAKTIVNE ENERGIJE
predava: Dr eljko Despotovi
POJAM REAKTIVNE ENERGIJE
REAKTIVNA ELEKTRINA
ENERGIJA
Reaktivna energija (ili u zapadnoj varijanti: jalova, to plastinije
opisuje njen karakter), sa stanovita fizike je onaj deo ukupne
isporuene elektrine energije koji se troi na uspostavljanje i
odravanje magnetnog polja u elektrinim mainama.
Odavde je jasno da su najvei potroai reaktivne energije
elektromotori i transformatori.
Svoje ime reaktivna energija je dobila zbog injenice da njena
potronja ne doprinosi aktivnoj odnosno korisnoj snazi, ali bez
potronje reaktivne energije elektrina maina ne bi ni mogla da
radi.
Strogo govorei reaktivna energija je mnogo iri pojam i javlja se
i kod potroaa kao to su: frekventni regulatori, soft starteri,
jednosmerni pogoni, ispravljai, itd.
REAKTIVNA ENERGIJA-problemi
I) PRIMER: TIPIAN cos=0.8 za ASINHRONE MOTORE, MOTOR SNAGE npr.10kW,
svakog sata utroi 10kWh aktivne energije i 7.5kVArh reaktivne energije 10kW se
pretvori u rad, dok se 7.5kVAr se utroi da bi se izvrila magnetizacija polova motora
(krajnji potroa nema nikakvu direktnu korist od ove energije a mora de je plati!!!!!!)
II) REAKTIVNA ENERGIJA MORA DA SE TRANSPORTUJE OD MESTA PROIZVODNJE

(GENERATOR-TRANSFORMATOR-VOD-POTROA) I ZAUZIMA KAPACITET KABLA
(Za pomenuti motor od 10kW struja koja potie od aktivne energije iznosi oko 25A, a od
reaktivne energije oko 19A, tako da ukupno kroz napojni vod protie oko 45A i doprinosi
poveanju otpornih gubitaka u vodu i njegovo grejanje). Posledice zagrevanja voda
(kabla) su vei pad napona koji raste sa njegovom duinom.
Prisustvo reaktivne komponente Potreban presek provodnika

(crvena boja) je zauzela oko 40% ako je potroa u potpunosti
potrebnog kapaciteta- cos=0.8 kompenzovan- cos=1
SNAGA POTROAA NAIZMENINE STRUJE
AKTIVNA SNAGA
REAKTIVNA SNAGA
PRIVIDNA SNAGA
IZRAZI ZA AKTIVNU I REAKTIVNU SNAGU
KOMPENZACIJA REAKTIVNE
ENERGIJE
Pod kompenzacijom reaktivne energije podrazumeva
se instalacija opreme koja generie reaktivnu energiju
na mestu montae i time kompenzuje potronju
reaktivne energije u pogonu.
Ovim se drastino smanjuje koliina preuzete
reaktivne energije iz mree, a time i rauni za utroenu
reaktivnu energiju.
Trokovi za reaktivnu energiju tipino ine oko 15 %
ukupnog rauna za elektrinu energiju.
Kompenzacijom reaktivne snage ova kompletna
stavka bi trebalo da bude skoro potpuno eliminisana.
Cene opreme za kompenzaciju su takve da se ova
investicija isplati u roku od 6 meseci do 2 godine.
ZATO JE POTREBNO IZVRITI
KOMPENZACIJU REAKTIVNE
ENERGIJE? ?
DOBIT ZA POTROAA: Potroai koji u svom raunu imaju stavku za reaktivnu
energiju imaju direktnu finansijsku dobit (nakon izvrene kompenzacije reaktivne
energije iz rauna se eliminie stavka koja se odnosi na reaktivnu energiju ili se
znaajno umanjuje). Uloeni novac za kompenzaciju reaktivne energije se vraa u
periodu eksploatacije od 10-30 puta.
DOBIT ZA EES: Kompenzacijom reaktivne energije se smanjuje ukupna struja u

mrei za vrednost reaktivne struje, smanjuje se optereenje transformatora,
poveava se stabilnost elektroenergetskog sistema (EES), sigurnost snabdevanja
potroaa i na kraju smanjenje tehnikih gubitaka aktivne energije u celom EES-u).
FAZORSKI DIJAGRAM OPTEREENJA
TIPOVI KOMPENZACIJE REAKTIVNE
ENERGIJE
TIPOVI KOMPENZACIJE REAKTIVNE
ENERGIJE
FAKTORI SNAGE ZA NEKE
KARAKTERISTINE POTROAE
Potroa Faktor snage

Elektromotor 0.85-0.93
Fluorescentne cevi 0.50-0.90
Ispravljai 0.70-0.90
Indukcione pei 0.60-0.80
Prese za plastiku 0.70-0.90
STEPENASTI REGULATORI
REAKTIVNE ENERGIJE
KONDENZATORSKI KONTAKTORI
Kondenzatorski kontaktori ukljuuju i

iskljuuju kondenzatorske baterije koje
imaju male induktivnosti i male gubitke
PRIGUNI OTPORI se ukljuuju

neposredno pre ukljuenja
kondenzatorskih baterija, da bi
se smanjile struje ukljuenja ispd 70In.
OSIGURAI za kondezatorske
baterije su vrednosti 1.6In....2.5In
TIRISTORSKI REGULATORI
REAKTIVNE ENERGIJE
U sluaju da su dnevne promene induktivne komponente struje velike, paralelno

optereenju se moe prikljuiti fiksna baterija kondenzatora dovoljno velike
kapacitivnosti, tako da se potroa zajedno sa baterijom kondenzatora prema
mrei ponaa kao otporno-kapacitivno optereenje.
Zatim se paralelno sa baterijom kondenzatora vezuje induktivno optereen fazni

regulator pomou koga se faktor snage podeava na maksimalnu vrednost.
TIRISTORSKI FAZNI REGULATOR SA
INDUKTIVNIM OPTEREENJEM
1 t
i L (t ) = 2 U sin t dt
L /
1 x 1 1
iL = 2 U sin x dx = 2 U ( cos x )x = 2 U (cos cos x )
L L L
1
i L (t ) = 2 U (cos cos t ) 2 t
L
/2
osnovni harmonik struje - i1

IZRAUNAVANJE FEKTIVNE VREDNOST
STRUJE PRVOG HARMONIKA
Amplituda osnovnog harmonika struje

1 2 4 2U
A1 = i ( x ) cos xdx = [cos cos x ] cos xdx
0 L
2 2U sin 2
A1 = 1 +
L 2
Efektivna vrednost struje prvog harmonika
A1 2U sin 2
I1 = = 1 +
2 L 2
TA JE SAVIIM HARMONICIMA???
Amplitude struja viih harmonika
1 2 4 2U sin k cos k cos k sin
Ak =
i( x ) cos kxdx Ak =
L

k ( k 2 1)
0
Neeljena harmonijska izoblienja

potiu uglavnom od treeg harmonika
koji ima maksimalnu vrednost za
= 1200
2U 3 2U
A3 = A3MAX = = 0.138
L 4 L
A3MAX U 3 U
I3 = = = 0.138
2 L 4 L
EFEKTIVNA VREDNOST TREEG HARMONIKA
Sadraj harmonika u struji kod monofaznog tiristorskog regulatora sa induktivnim optereenjem

TIRISTORSKI REGULATOR kao ekvivalent
PROMENLJIVOJ PRIGUNICI
Ako se posmatra osnovni harmonik struje, uoava se da se fazni
tiristorski regulator sa isto induktivnim optereenjem ponaa prema
mrei, kao prigunica promenljive induktivnosti.
Promenom faznog ugla u opsegu / 2
induktivnost prigunice se moe podeavati u opsegu od
L do beskonane vrednosti, odnosno
MIN LMIN L +
UKUPNA TROFAZNA SNAGA KOMPENZATORA je jednaka:
6 2 sin 2
Q = 3U f I 1 = 3U l I 1 = U l 1 + /2
L 2
gde je za spregu tiristorskog regulatora u trougao U f = U l
tj. efektivne vrednosti faznog i linijskog napona su jednake i iznose 380V(400V)
TIRISTORSKI REGULATOR kao ekvivalent
PROMENLJIVOJ PRIGUNICI
TIRISTORSKI KOMPENZATOR SA
PROIRENIM OPSEGOM UGLA PALJENJA
U sluaju ove konfiguracije faznog regulatora

ugao paljenja tiristora se moe menjati u punom
opsegu:
0
Stoga je ova konfiguracija povoljnija u odnosu na
konfiguraciju sa antiparalelnom vezom tiristora kod
koje je opseg regulacije bio u intervalu:
/2
Efektivna vrednost struje osnovnog harmonika je ista ko i kod faznog regulatora sa
antiparalelnom vezom tiristora:
A1 2U sin 2
I1 = = 1 + 0
2 L 2
AC/DC energetski pretvarai
(NEKONTROLISANI PRETVARAI DIODNI ISPRAVLJAI)
Predava: Dr eljko Despotovi

AC/DC pretvarai-ISPRAVLJAI
220V, 50/60Hz
1 3
AC DC AC DC
1 3
AC AC
DC DC
ulaz ulaz
izlaz izlaz

KONTROLISANI
IDEALNI POLUTALSANI ISPRAVLJA: MONOFAZNI-OTPORNO OPTEREENJE
DC izlazni napon
RMS izlazni napon

IDEALNI POLUTALSANI ISPRAVLJA: MONOFAZNI,R-L OPTEREENJE
UGAO ODREUJEMO IZ USLOVA:

KORIENJE ZAMAJNE DIODE ZA ELIMINISANJE NEGATIVNOG IZLAZNOG NAPONA
IDEALNI POLUTALSANI ISPRAVLJA: MONOFAZNI, OPTEREENJE: R-DC izvor
(PUNJA BATERIJE SA PREDOTPOROM)
IDEALNI POLUTALSANI ISPRAVLJA: MONOFAZNI, OPTEREENJE: R-L DC izvor
Poetak voenja diode

IDEALNI POLUTALSANI ISPRAVLJA: MONOFAZNI,OPTEREENJE: R-C
D D on
D off
C
IDEALNI PUNOTALSANI SPRAVLJA : MONOFAZNI, OPTEREENJE: R
(TALASNI OBLICI)
Ovaj transformator mora biti 1.75 puta predimenzionisan u odnosu na klasini sa AC ulazom i izlazom
IDEALNI PUNOTALSANI SPRAVLJA U GRECOVOM SPOJU: MONOFAZNI,
OPTEREENJE: R (TALASNI OBLICI)
IDEALNI PUNOTALSANI SPRAVLJA U GRECOVOM SPOJU: PRORAUNI
IDEALNI PUNOTALSANI SPRAVLJA U GRECOVOM SPOJU: MONOFAZNI,
OPTEREENJE: R L-DC izvor (tipina primena za punjae baterija)
IDEALNI PUNOTALSANI SPRAVLJA: MONOFAZNI, OPTEREENJE: R -L
IDEALNI PUNOTALSANI SPRAVLJA: MONOFAZNI, OPTEREENJE: JAKO INDUKTIVNO
IDEALNI PUNOTALSANI SPRAVLJA: MONOFAZNI, OPTEREENJE: PRETENO
INDUKTIVNO (DC MOTOR SA VELIKOM REDNOM PRIGUNICOM)
IDEALNI PUNOTALSANI SPRAVLJA: MONOFAZNI, OPTEREENJE: STRUJNI PONOR
L
EFEKAT RASIPNE INDUKTIVNOSTI Ls
(a)-elektrina ema
(b)-izlazni napon
(c)- napon na Ls
(d)- struja Ls
EFEKAT RASIPNE INDUKTIVNOSTI Ls - kolo za analizu
PUNOTALSNI ISPRAVLJA SA KAPACITIVNIM FILTROM
TALASNI OBLICI REALNOG DIODNOG ISPRAVLJAA SA RC FILTROM
UNIVERZALNI ISPRAVLJA SA NAPAJANJEM 110/220V AC
PRIEMENA U MRENIM NAPAJANJIMA ATX napajanje

PUNOTALSNI ISPRAVLJA U GRECOVOM SPOJU: SIMULACIJA
NAPAJANJE
220V,50Hz
115V, 50Hz
NAPAJANJE
POREENJE IZLAZNOG NAPONA PRI 115V, 50Hz i 230V,50Hz

DETALJAN PRIKAZ IZLAZNOG NAPONA PRI 230V, 50Hz i 115V,50Hz

ELEKTRINA EMA TIPINOG ATX-napajanja
ATX napajanje-DETALJ ULAZNOG ISPRAVLJAA
TROFAZNI AC-DC pretvari (MREOM VOENI ISPRAVLJAI )
Trofazni ispravlja sa transformatorom sa srednjom takom

TROFAZNI ISPRAVLJA SA TRANSFORAMATOROM SA SREDNJOM
TAKOM- talasni oblici
TROFAZNI ISPRAVLJA SA TRANSFORAMATOROM SA SREDNJOM TAKOM- prorauni
TROFAZNI ISPRAVLJA SA TRANSFORAMATOROM SA SREDNJOM TAKOM- prorauni kad je
optereenje strujni ponor
TROFAZNI MOSNI ISPRAVLJA-otporno optereenje
TROFAZNI MOSNI ISPRAVLJA-optereenje strujni ponor Io
TROFAZNI MOSNI ISPRAVLJA
EKVIVALENCIJA SA DVA TROFAZNA POLUMOSNA ISPRAVLJAA
TROFAZNI MOSNI ISPRAVLJA-talasni oblici
LINIJSKI NAPON I
LINIJSKA STRUJA
HARMONIJSKI SASTAV
TROFAZNI MOSNI ISPRAVLJA- izraunavanje srednjih i efektivnih vrednosti
MONOFAZNI ISPRAVLJAI (IZBOR KAPACITIVNOG FILTRA) -rekapitulacija
TROFAZNI ISPRAVLJAI (IZBOR KAPACITIVNOG FILTRA) - rekapitulacija
AC/DC ENERGETSKI PRETVARAI
(KONTROLISANI TIRISTORSKI ISPRAVLJAI)
Predava: Prof. dr eljko Despotovi

AC/DC pretvarai-OPTE
220V, 50/60Hz
1 3
AC DC AC DC
1 3
AC AC
DC DC
ulaz ulaz
izlaz izlaz

KONTROLISANI
(rekapitulacija)
NEUPRAVLJIVI AC/DC PRETVARAI -DIODNI UMNOAVAI (rekapitulacija)
MONOFAZNI POLUTALASNI KONTROLISANI ISPRAVLJAI
sa otpornim optereenjem
Srednja vrednost izlaznog napona
Srednja izlazne struje
Efektivna vrednost izlaznog napona

MONOFAZNI KONTROLISANI ISPRAVLJAI
POLUTALASNI sa isto induktivnim optereenjem
Opseg upravljanja
UPAV = 0
Efektivna vrednost napona potroaa
Struja potroaa
Srednja vrednost struje potroaa
Efektivna vrednost struje potroaa

za kontrolu pujenja baterija i akumulatora
Tiristor se moe ukljuiti samo kad je u > Vc

jer je tada napon na tiristoru pozitivan, tj.
ne pre ugla za koji je:
Dakle opseg upravljanja za je

< < ,
odnosno
arcsin(m) < < .
Tiristor se gasi za u < Vc
Kada je tiristor ukljuen kroz potroa tee struja:

ANALIZA I PRORAUNI
Efektivna vrednost struje potroaa
Srednja vrednost napona potroaa
Efektivna vrednost napona potroaa
Izraunavanje snage isporuene potroau Faktor snage izvora

za kontrolu punjenja baterija i akumulatora, sa PRIGUNICOM
Srednja vrednost napona potroaa
Aktivna snaga razvijena na potroau
Struja dostie maksimum za t = - , kada je u = Vc i zatim poinje da opada.

Za neki ugao struja postaje nula. Ugao se dobija reavanjem jednaine:
MONOFAZNI PUNOTALASNI ISPRAVLJA SA TRANSFORMATOROM SA
SREDNJOM TAKOM
ANALIZA RADA

1 U m U m U 2
U SR =
U m sin d = sin d =
(1 + cos ) =

(1 + cos )

U SR U 2
I SR = = (1 + cos )
ROPT ROPT
1 U m U m U 2
2 R 2
I FSR = I
m sin d = sin d = (1 + cos ) = (1 + cos )
R 2 2R
1 I m2 2
( I m sin ) 2 d =
2
I Feff = sin d
2
U 1 I 1
I Feff = 1 + sin 2 = 1 + sin 2
R 2 2 2 2
MONOFAZNI PUNOTALASNI ISPRAVLJA SA TRANSFORMATOROM SA
SREDNJOM TAKOM ZA POBUDU DC MOTORA
ANALIZA RADA I TALASNI OBLICI za Ud>0
ANALIZA RADA I TALASNI OBLICI za Ud0
90<<160170
1020-ogranienje trajanja inverzne ogranienje ugla upravljanja u
polarizacije tiristora invertorskom reimu
+180
>to to-VREME ODMORA TIRISTORA
MONOFAZNI PUNOTALASNI MOSNI ISPRAVLJA
U toku svake poluperiode napona

izvora provode po dva tiristora to
rezultuje punotalasnim ispravljanjem
i simetrinim oblikom struje izvora.
Na ovaj nain struja izvora nema

jednosmernu komponentu, pa se
moe upotrebiti transformator
kao izvor naizmeninog napona.
Kod ovog ispravljaa postoje dva

impulsa struje potroaa za
vreme jedne periode napona
izvora pa se moe okarakterisati
kao "dvopulsni".
MONOFAZNI PUNOTALASNI MOSNI ISPRAVLJA SA OMSKIM
OPTEREENJEM-izraunavanje srednjih i efektivnih vrednosti
SREDNJA VREDNOST STRUJE POTROAA
EFEKTIVNA VREDNOST STRUJE POTROAA
SREDNJA VREDNOST NAPONA POTROAA
EFEKTIVNA VREDNOST NAPONA POTROAA

UPRAVLJAKA KARAKTERISTIKA (potroa omska otpornost)
MONOFAZNI PUNOTALASNI MOSNI ISPRAVLJA SA JAKO INDUKTIVNIM
OPTEREENJEM (L) -izraunavanje srednje vrednosti izlaznog napona
UPRAVLJAKA
KARAKTERISTIKA
MONOFAZNI PUNOTALASNI POLUUPRAVLJIVI MOSNI
ISPRAVLJAI
MONOFAZNI PUNOTALASNI POLUUPRAVLJIVI MOSNI ISPRAVLJAI-
analiza rada
U sluaju kad je Z=R (ista omska otpornost) talasni oblici izlaznog napona su isti za oba tipa
ispravljaa.
U sluaju kad je optereenje strujni ponor razlikovae se talasni oblici izlaznog napona
Kada vode T1 i D2:
Kada u2<0 provee D4, D2 prestaje da provodi,

pa se struja I zatvara kroz T1 i D4:
Kada se ukljue T3, gasi se T1, pa se struja I

zatvara kroz T3, potroa i D4:
Kada u2>0 provee D2, D4 prestaje da provodi,

pa se struja I zatvara kroz T3 i D2:
UPRAVLJAKA KARAKTERISTIKA
EFEKAT RASIPNE INDUKTIVNOSTI
u N1
e= m=
m N2
N1 N2
e = E 2 sin t X k = Lk
S k = 2 Lk I d
SREDNJA VREDNOST IZLAZNOG NAPONA
2 2 2
Ud = E cos X k Id

PRIMENA: Regulacija broja obrtaja vunih motora (elektrine lokomotive)
TROFAZNI POLUMOSNI ISPRAVLJA sa otpornim optereenjem
TROFAZNI POLUMOSNI ISPRAVLJA sa strujnim ponorom kao optereenjem
e1 = E 2 sin t
e2 = E 2 sin(t 1200 )
e3 = E 2 sin(t 2400 )

3 6
Uo = E cos
2
TROFAZNI POLUMOSNI ISPRAVLJA sa strujnim ponorom kao optereenjem
(analiza talasnih oblika struja)
Struje kroz primarne namotaje

se mogu odrediti iz uslova da
zbir MPS po zatvorenom
magnetnom putu bude jednak
0.
Ako se zanemari struja
magneenja transformatora
izjednaavanjem MPS za levi i
srednji stub se dobija:
Slino vai i za levi i desni

stub:
m=1 Trea jednaina:
REAVANJEM OVOG
SISTEMA JEDNAINA SE
DOBIJA
m=N1/N2
E-EFEKTIVNA VREDNOST FAZNOG NAPONA NA SEKUNDARU
SREDNJA VREDNOST IZLAZNOG NAPONA
STRUJE PRIMARA:
PRENOSNI ODNOS TRANSFORMATORA
m=N1/N2
SREDNJA VREDNOST NAPONA NA

OPTEREENJU
3 6
Ud = E cos
2 m
EFEKTIVNA VREDNOST STRUJE U
NAMOTAJIMA SEKUNDARA
EFEKTIVNA VREDNOST STRUJE U NAMOTAJIMA
PRIMARA
EFEKTIVNA VREDNOST STRUJE DOVODNIM

PRIKLJUCIMA (LINIJSKI PROVODNICMA)
FAKTOR SNAGE ISPRAVLJAA

UPRAVLJAKA KARAKTERISTIKA
UPRAVLJAKA KARAKTERISTIKA- trofazni polumosni ispravlja sa izvedenom nulom
TROFAZNI POLUMOSNI ISPRAVLJA-uticaj rasipne induktivnost Lk
Posmatra se komutacija izmeu T1 i T3
Diferenciranjem ovog izraza i mnoenjem

sa Lk se dobija:
Takoe vai:
Napon na komutacionoj prigusnici je:
Struja tiristora T1 se dobija reavanjem integrala:
Trenutak zavretka komutacije:
Srednja vrednost izlaznog napona:

TROFAZNI MOSNI ISPRAVLJA (PUN MOST- 6 TIRISTORA)
TOPOLOGIJA
ANALIZA TALASNIH OBLIKA
va = E 2 sin t
vb = E 2 sin(t 1200 )
vc = E 2 sin(t 2400 )
3 2
Vd = VLL cos

VLL = 3E
3 6
Vd = E cos

Spektar linijske struje
Furijeov red viih harmonika:
Efektivna vrednost linijske struje:
Ia = Ib = Ic
Ukupno harmonijsko izoblienje:

Vd = 0
Vd > 0
+
-
Talasni oblici
izlaznog napona
za razliite
vrednosti ugla
upravljanja
Vd < 0
EFEKAT
KOMUTACIONE
INDUKTIVNOSTI
3 6 3X k
Vd = E cos Id

X k = Lk
L k = Ls
VLL = 3E
POTPUNO UPRAVLJIVI TIRISTORSKI ISPRAVLJAI-REKAPITULACIJA
DC/DC PRETVARAI-OPERI
IGBT
SCR, GTO
Predava: Prof.dr eljko Despotovi

OPTE DC/DC pretvarai-OPERI
Pretvaraju nestabilisani DC ulazni napon u stabilisani DC izlazni napon
zahtevanog nivoa CHOPPER=seka
operi su DC/DC pretvarai koji pretvaraju jednosmernu struju jednog naponskog nivoa u
jednosmernu struju drugog naponskog nivoa.
Oni se esto nazivaju i transformatori napona ili OPERI (engl. CHOPPER=seka).
DC ulaz: jednosmerni izvori napajanja, izlaz ispravljakih jedinica, solarne elije,
DC vetrogeneratori , baterije, gorivne elije i sl.
PRIMENA: PRIMENA: Prekidaki izvori napajanja- Switch Mode Power Supply

(SMPS), kontrola jednosmernih motora, punjai baterija, elektrina vozila, elektrina
vua i sl.
Kombinovani AC/DC i DC/DC pretvarai =AC/DC pretvarai
(ispravljai)
~ =
~ = = ~ ~
=
AC/DC DC/DC AC/DC
Ulazni
AC/DC
pretvara
OSNOVNO OPERSKO KOLO BEZ AKUMULACIONIH ELEMENATA
T
1 t 1
V0 SR = vo dt = 1 VS = f t1 VS = VS
T 0 T T
Srednja vrednost izlazne struje
V0 SR VS
I0 = =
R R
T-Perioda opovanja Nekad se oznaava i sa D
f-Uestanost opovanja
t1 koeficijent radnog reima opera (duty-cycle)
=D=
T
0 1 odnosno 0% 100%
VS R R
EKVIVALENTNA ULAZNA OTPORNOST Rin _ ekv = = =
I0 D
=0 Rin _ ekv =
=1 Rin _ ekv = R
ZAKLJUAK: opersko kolo obezbeuje kontinualnu promenu ulazne otpornosti.
PROMENA NORMALIZOVANE ULAZNE OTPORNOSTI OPERA BEZ
AKUMULACIONIH ELEMENATA SA ISTO OMSKIM OPTEREENJEM U
ZAVISNOSTI OD KOEFICIJENTA RADNOG REIMA
IZRAUNAVANJE EFEKTIVNE VREDNOSTI IZLAZNOG NAPONA I IZLAZNE SNAGE
EFEKTIVNA VREDNOST IZLAZNOG NAPONA
T
1 2 t1
V0 eff =
T 0
v0 dt =
T
VS = VS = D VS
SREDNJA VREDNOST IZLAZNE SNAGE

T
1 t1 2 1 VS2 VS2
PiSR =
T
0
vo i dt = VS =
T R R
= D
R
OSNOVNE TOPOLOGIJE OPERA SA AKUMULACIONIM ELEMENTIMA I
DIODOM
operi za snienje napona

(engl. buck converters)
VOUT < VIN
operi za poveanje napona

(engl. boost converters)
VOUT < VIN
operi za snienje/poveanje
napona (obrtai napona)
(engl. buck-boost converters)
VOUT < VIN

VOUT >VIN
OPER SPUTA NAPONA
BUCK PRETVARA
DVA MOGUA REIMA RADA:
-KONTINUALNI (NEPREKIDNI ) REIM RADA
-DISKONTINUALNI (PREKIDNI) REIM RADA

TALASNI OBLICI I EKVIVALENTNO KOLO ZA OPER SPUTA NAPONA
BUCK PRETVARA u KONTINUALNOM REIMU
OPER SPUTA NAPONA-BUCK u KONTINUALNOM REIMU
OPER SPUTA-BUCK u KONTINUALNOM REIMU
OPER SPUTA NAPONA -BUCK u KONTINUALNOM REIMU
OPER SPUTA NAPONA -BUCK u DISKONTINUALNOM (PREKIDNOM)REIMU
OPER PODIZA NAPONA
BOOST PRETVARA

TALASNI OBLICI I EKVIVALENTNO KOLO ZA OPER PODIZA NAPONA
BOOST PRETVARA u KONTINUALNOM REIMU
OPER PODIZA NAPONA-BOOST u KONTINUALNOM REIMU
OPER PODIZA NAPONA -BOOST u DISKONTINUALNOM (PREKIDNOM)REIMU
OPER PODIZA NAPONA -BOOST u DISKONTINUALNOM (PREKIDNOM)REIMU
OPER OBRTA NAPONA
BUCK BOOST
PRETVARA

TALASNI OBLICI I EKVIVALENTNO KOLO ZA OPER OBRTA NAPONA
BUCK - BOOST PRETVARA u KONTINUALNOM REIMU
OPER OBRTA NAPONA BUCK - BOOST PRETVARA u
KONTINUALNOM REIMU
KONTINUALNOM REIMU
KONTINUALNOM REIMU
OPER OBRTA NAPONA BUCK - BOOST PRETVARA u PREKIDNOM
(DISKONTINUALNOM) REIMU
OPER OBRTA NAPONA BUCK - BOOST PRETVARA u PREKIDNOM
(DISKONTINUALNOM) REIMU
PRIMENA OPERA : REGULACIJA MOMENTA (VUNE SILE) I BRZINE
JEDNOSMERNIH MOTORA SA NEZAVISNOM POBUDOM
OPERSKO KOLO ZA POBUDU DC MOTORA
SA TIRISTORSKI KONTROLISANOM NEZAVISNOM POBUDOM
OSNOVNO OPERSKO KOLO ZA POBUDU DC
MOTORASA NEZAVISNOM POBUDOM-ANALIZA RADA
OSNOVNI TIPOVI OPERA: REKAPITULACIJA
Invertori
VSI
Invertori su sistemi energetske elektronike koji jednosmerni napon ili struju pretvaraju
voltage sour e inverters CSI urrent sour e inverters

naizmenini napon ili struju. Prema prirodi ulazne promenljive mogu biti naponski (
) ili strujni ( ) invertori. Prema broju
faznih prikljuaka na izlazu, invertori su najee monofazni ili trofazni, ali za pogon motora
postoje invertori i sa drugaijim brojem faza.
Od invertora se zahteva da konverziju energije ostvare sa visokim koe ijentom korisnog
dejstva, pa su na raspolaganju za sintezu invertora prekidai i reaktivni elementi. Izlazna
veliina esto treba da bude sinusoidalnog talasnog oblika, ali ponekad to nije sluaj.
Sinusoidalni talasni oblik nije mogue bez disipa ije stvoriti od napona ili struja konstantnih u
vremenu, pa se zahtev za sinusoidalnim oblikom svodi na sinusoidalni oblik srednje vrednosti
izlazne veliine tokom periode prekidanja. Stoga e se usrednjavanje esto koristiti tokom
analize invertora, to na nivou periode prekidanja, sto na nivou periode moduliueg signala koja
je obino znatno vea od periode prekidanja, osnosno odreivanja jednosmerne komponente.
Naponom napajan monofazni invertor
Naponom napajan monofazni invertor, ili naponski invertor, treba na izlazu da ostvari
naizmenini napon zadate amplitude, talasnog oblika i frekven ije, uzimajui energiju iz
jednosmernog naponskog izvora na ulazu. Izlazna impedansa ovakvog invertora e biti mala,
kao to je to i impedansa jednosmernog izvora koji napaja invertor. Stoga se podrazumeva
potroa visoke unutranje impedanse kako bi se spreili impulsi struje.
single pole double throw, SPDT

Funk ionalna ema naponom napajanog monofaznog invertora je prikazana na sli i 1 i sastoji
se iz dva dvopoloajna jednopolna ( ) prekidaa. Pomou ova
dva prekidaa mogue je na izlazu ostvariti dva napona, u poloaju 1 kada je
vOU T = vIN
to uslovljava
iIN = iOU T
i u poloaju 2 kada je
vOU T = vIN
to uslovljava
iIN = iOU T .
U nekim primenama je ovaj skup mogunosti za realiza iju izlaznog napona dovoljan, ali ee
nije. Stoga se izlazni naponi drugaijih nivoa dobijaju smenjivanjem dva raspoloiva stanja
prekidaa i ltriranjem dobijenog napona tako da u izlaznom naponu dominira srednja vrednost
realizovanog napona u okviru periode prekidanja. U tabeli 1 su rezimirana stanja prekidaa
u invertoru, izlazni napon, ulazna struja i naznaena su trajanja pojedinih stanja. Na osnovu
podataka iz tabele 1, smatrajui da su vIN i iOU T konstantni tokom periode prekidanja, srednja
vrednost izlaznog napona invertora tokom periode prekidanja se dobija kao
vOU T = hvOU T i = (2d 1) vIN
dok je srednja vrednost ulazne struje tokom periode prekidanja
iIN = hiIN i = (2d 1) iOU T
Treba napomenuti da ovako dobijena srednja vrednost ulazne struje samo u sluaju konstantnog
d predstavlja i njenu jednosmernu komponentu. U sluaju da je d promenljivo, jednosmerna
1
iIN
+ 1 S1 iOUT
2 +
+
vIN vIN
vOUT iOUT
-
1 S2 -
2
Slika 1: Naponom napajan invertor.
Tabela 1: Naponom napajan monofazni invertor, stanja.
stanje trajanje vOU T iIN
1 d TS vIN iOU T
2 d TS vIN iOU T
komponenta ulazne struje se dobija usrednjavanjem srednje vrednosti ulazne struje jo jednom,
tokom periode signala d(t), koja je nuno vea od periode prekidanja.
Na osnovu izvedenih jednaina za srednju vrednost izlaznog napona i srednju vrednost
ulazne struje, mogue je napraviti model invertora za srednje vrednosti struja i napona u formi
elektrinog kola, kako je prikazano na sli i 2. Kolo sa slike 2 se moe predstaviti pomou
idealnog transformatora prenosnog odnosa 1 : (2d 1), kako je prikazano na sli i 3. Iako oba
ekvivalentna modela karakteriu iste jednaine, u praksi se zbog ustaljenih navika i nebrige o
ulaznoj struji vie koristi ekvivalentna ema sa slike 2.
iIN iOUT
+ +
+
vIN (2d-1) iOUT (2d-1) vIN vOUT
- -
Slika 2: Naponom napajan invertor, model za srednje vrednosti struja i napona.
iIN iOUT
+ 1 2d-1 +
vIN vOUT
- -
Slika 3: Naponom napajan invertor, transformatorski model.
2
Strujom napajan monofazni invertor
Dualan naponom napajanom invertoru je strujom napajan invertor, ili strujni invertor,
predstavljen na sli i 4. Prema prikazu sa slike 4, prekidaka mrea je ista kao i kod naponom
napajanog invertora, ali drugaije okrenuta. Meutim, realiza ija prekidaa i upravljanje
prekidaima e se bitno razlikovati. Kod strujom napajanog invertora izlazna impedansa izvora
je velika, kao i izlazna impedansa invertora. Stoga ulazna impedansa potroaa mora biti mala,
kako bi se izbegli naponski impulsi.
S1 iOUT
iIN 1 +
+ 2
+ v
vOUT OUT
iIN vIN
S2 -
- 1
2
Slika 4: Strujom napajan invertor.
Kod strujom napajanog monofaznog invertora u poloaju prekidaa 1 vai
iOU T = iIN
i
vIN = vOU T
dok u poloaju 2 vai
iOU T = iIN
i
vIN = vOU T .
U daljoj analizi e se smatrati da su iIN i vOU T konstantni tokom periode prekidanja. Stanja
invertora su rezimirana u tabeli 2, na osnovu ega je srednja vrednost izlazne struje invertora
iOU T = hiOU T i = (2d 1) iIN
dok je srednja vrednost ulaznog napona
vIN = hvIN i = (2d 1) vOU T .
Kao i kod naponom napajanog invertora ova srednja vrednost nije nuno jednosmerna
komponenta, poto moe biti periodina sa periodom vezanim za period promene d(t). Zato je
za odreivanje jednosmerne komponente ulaznog napona potrebno jo jedno usrednjavanje, na
nivou periode signala d(t).
Prema jednainama za srednje vrednosti izlazne struje i ulaznog napona, mogue je
napraviti model strujom napajanog invertora za srednje vrednosti struja i napona tokom
periode prekidanja. Uobiajeni model koji koristi naponom kontrolisan naponski izvor i strujom
kontgrolisan strujni izvor je prikazan na sli i 5, dok je model koji koristi idealni transformator
prenosnog odnosa (2d 1) : 1 prikazan na sli i 6. Kao i kod naponom napajanog invertora, u
praksi se zbog ustaljenih navika ee koristi model sa slike 6.
3
Tabela 2: Strujom napajan monofazni invertor, stanja.
stanje trajanje iOU T vIN
1 d TS iIN vOU T
2 d TS iIN vOU T
iIN iOUT
+ +
+
vIN (2d-1) vOUT (2d-1) iIN vOUT
- -
Slika 5: Strujom napajan invertor, model za srednje vrednosti struja i napona.
iIN iOUT
+ 2d-1 1 +
vIN vOUT
- -
Slika 6: Strujom napajan invertor, transformatorski model.
Spregnuto i nezavisno upravljanje prekidaima
U dosadanjoj analizi, impli itno je smatrano da oba dvopoloajna prekidaa u invertoru

imaju isto stanje, S1 i S2 su uvek ili oba u stanju 1, ili oba u stanju 2. Ovakav nain upravljanja
prekidaima u invertoru se naziva spregnuto upravljanje prekidaima, kada jedan bit kodira
stanje invertora. Osim ovog naina upravljanja, mogue je i nezavisno upravljanje prekidaima,
kada se prekidai mogu nai u razliitim stanjima i kada je trenutna vrednost izlazne veliine
(napona kod naponskih invertora, odnosno struje kod strujnih invertora) jednaka nuli. U tom
sluaju su potrebna dva bita za kodiranje stanja invertora. Dodatni stepen slobode, da trenutna
vrednost izlazne veliine bude jednaka nuli, moe da se koristi u sintezi srednje vrednosti izlazne
veliine. Na ovaj nain se, uz sloenije upravljanje, moe smanjiti talasnost na izlazu, odnosno
smanjiti sadraj viih harmonika u izlaznoj veliini. Razlike izmeu spregnutog i nezavisnog
upravljanja prekidaima e biti detaljnije razmatrane prilikom analize realiza ija invertora i
prilikom analize spektra izlazne veliine.
4
Potpuno kontrolisana stanja
Kod realiza ije naponskih invertora (naponom napajanih invertora) ilj je da izlazni napon
bude denisan kontroliuom promenljivom, nezavisan od smera struje potroaa. Dualno je
kod strujnih invertora, struja potroaa treba da bude kontrolisana nezavisno od napona na
potroau. U analizi koja sledi bie razmatran naponski invertor.
inverter leg
Naponski invertori se pomou elektronskih prekidaa realizuju pomou takozvanih stubova
( ). Stub se sastoji iz dva kontrolisana prekidaa i dve zamajne diode, kako je
prikazano na sli i 7. Kontrolisani prekidai su unidirek ioni, mogu voditi struju samo u smeru
suprotnom od smera u kome mogu voditi diode koje su im paralelno vezane. Zato se esto kae
za diode da su antiparalelne. Ovo je sluaj kod svih elektronskih prekidaa, a ta injeni a
dobija na znaaju kod realiza ije invertora, dok je kod d /d konvertora bila znatno manje
znaajna.
U tabeli 3 su prikazane sve mogue kombina ije stanja prekidaa. Stanje 3, u kome su oba
prekidaa ukljuena je zabranjeno, jer dovodi do kratkog spoja ulaznih izvora, to se u praksi
svodi na pregorevanje prekidaa. Stanje 0, u kome su oba prekidaa iskljuena je dozvoljeno,
ali u tom stanju izlazni napon zavisi od smera izlazne struje. Preostala dva stanja, 1 i 2, daju
izlazni napon koji je nezavisan od smera struje potroaa. Stoga se ova stanja nazivaju potpuno
kontrolisanim i koriste se u realiza iji invertora. Stanje 0 se koristi prilikom prenosa provoenja
izmeu prekidaa, poto se nikako ne sme dopustiti stanje 3. Stoga se promene stanja 12
i 21 realizuju kao 102 i 201, sa kratkotrajnim boravkom u stanju 0, a sve u ilju
izbegavanja stanja 3 usled preklapanja pobudnih signala.
Na osnovu prethodne analize se moe zakljuiti da su potpuno kontrolisana stanja ona
stanja kod kojih je u stubu ukljuen tano jedan od dva prekidaa. Ovaj zakljuak e biti
dosta korien u analizama koje slede.
+
vIN/2 S1 D1
vOUT
iOUT
+
vIN/2 S2 D2
Slika 7: Invertor, analiza jednog stuba.
Tabela 3: Invertor, analiza jednog stuba.
iOU T > 0 iOU T < 0

stanje S1 S2 vOU T vodi vOU T vodi
0 0 0 vIN /2 D2 vIN /2 D1
1 0 1 vIN /2 D2 vIN /2 S2
2 1 0 vIN /2 S1 vIN /2 D1
3 1 1 zabranjena kombina ija
5
Realiza ija monofaznih invertora
Naponski invertor
Monofazni naponom napajan invertor se realizuje pomou dva stuba kako je prikazano
na sli i 8. Takav invertor ima etiri potpuno kontrolisana stanja, koja su navedena u tabeli 4.
Stanja su numerisana dekadnim zapisom binarnog broja koji ine stanja pojedinanih prekidaa.
Dva od tih stanja, 5 i 10, daju izlazni napon i ulaznu struju koji su jednaki nuli. Nenulti
izlazni napon daju stanja 6 i 9, koja su potpuno kontrolisana. Dakle, realiza ija sa slike 8 daje
mogunost da trenutna vrednost izlaznog napona bude jednaka nuli. Ova mogunost se moe, a
ne mora, koristiti u radu invertora. U zavisnosti od toga koristi li se ova mogunost ili ne, postoje
dva naina upravljanja invertorom: spregnuto upravljanje stubovima i nezavisno upravljanje
stubovima. Za ispravan rad sa potpuno kontrolisanim stanjima S2 = S1 i S4 = S3. Kod
spregnutog upravljanja stubovima dodatno je S3 = S1, pa je jedan bit dovoljan da karakterie
stanje invertora. Kod nezavisnog upravljnja stubovima dva bita kodiraju stanje invertora.
iIN
S3 D3 S1 D1
iOUT
+
vIN
+
S4 D4 S2 D2
vOUT
Slika 8: Monofazni naponski invertor.
Tabela 4: Monofazni naponski invertor, potpuno kontrolisana stanja.
stanje S1 S2 S3 S4 vOU T iIN
5 0 1 0 1 0 0
6 0 1 1 0 vIN iOU T
9 1 0 0 1 vIN iOU T
10 1 0 1 0 0 0
Kod spregnutog upravljanja stubovima, ako je S1 ukljuen tokom dTS , srednja vrednost
izlaznog napona je
vOU T = (2d 1) vIN
dok je ulazna struja
iIN = (2d 1) iOU T .
6
Kod nezavisnog upravljanja stubovima ne postoji veza izmeu stanja S1 i S3. Neka je invertor
u stanju 9 tokom d1 TS , a u stanju 6 tokom d2 TS . Tada je
vOU T = (d1 d2 ) vIN
i
iIN = (d1 d2 ) iOU T .
Poto je u sluaju spregnutog upravljanja stubovima
d2 = 1 d1
formule za nezavisno upravljanje subovima se svode na formule za spregnuto upravljanje

stubovima.
Strujni invertor
Strujni invertor, prikazan na sli i 9 dualan je naponskom. Umesto antiparalelnom vezom
prekidaa i diode, elektronski prekidai se kod strujnih invertora najee realizuju rednom
vezom kontrolisanog prekidaa i diode. Dioda se vezuje na red kako bi obezbedila blokiranje
inverzne struje prekidaa, poto prekidaki elementi poput MOSFET-a imaju integrisanu
parazitnu zamajnu diodu, pa nemaju mogunost blokiranja inverzne struje. Blokiranje inverzne
struje je veoma vano u situa ijama kada su istovremeno ukljueni S1 i S3, kao i S2 i S4, jer bi
bez blokiranja inverzne struje prekidaa potroa sa niskom ulaznom impedansom bio kratko
spojen.
Kod strujnog invertora zabranjene prekidake kombina ije su drugaije nego kod naponskog
invertora. Dok kod naponskog invertora nije bilo doputeno kratko vezivati naponski izvor vezan
na ulaz, kod strujnog invertora nije doputeno ostaviti otvorenim strujni izvor na ulazu. Stoga,
mora da vodi bar jedan od prekidaa S1 i S3 i bar jedan od prekidaa S2 i S4. Prenos provoenja
S1S3 se realizuje kao S1(S1+S3)S3, dakle postoji period vremena tokom koga vode oba
prekidaa. Analogno se komutuju S2 i S4.
+
S3 S1
D3 D1
iOUT
iIN vIN
+
S4 S2
D4 D2 vOUT
-
Slika 9: Monofazni strujni invertor.
Kako se vidi iz tabele 5, potpuno kontrolisana stanja su karakterisana sa S3 = S1 i S4 = S2,

dakle dva bita su dovoljna da kodiraju potpuno kontrolisano stanje invertora. Kod spregnutog
upravljanja stubovima je dodatno S2 = S1, pa je samo jedan bit dovoljan da opie stanje
7
Tabela 5: Monofazni strujni invertor, potpuno kontrolisana stanja.
stanje S1 S2 S3 S4 iOU T vIN
3 0 0 1 1 0 0
6 0 1 1 0 iIN vOU T
9 1 0 0 1 iIN vOU T
12 1 1 0 0 0 0
invertora. Ako je tokom d1 TS invertor u stanju 9, a tokom d2 TS invertor u stanju 6, srednja

vrednost izlazne struje je
iOU T = (d1 d2 ) iIN
dok je srednja vrednost ulaznog napona
vIN = (d1 d2 ) vOU T .
Poto je u sluaju spregnutog upravljanja stubovima
d2 = 1 d1
formule za nezavisno upravljanje subovima se svode na formule za spregnuto upravljanje

stubovima.
Na osnovu izloenog se moe zakljuiti da kod realiza ija monofaznih invertora sa etiri
kontrolisana prekidaa imamo dva stanja u kojima je izlazna veliina (napon kod naponskog
invertora i struja kod strujnog invertora) jednaka nuli. Ova dva stanja se mogu koristiti u
sintezi srednje vrednosti izlazne veliine. Na primer, dok je izlazna veliina pozitivna ona se
moe sintetisati samo korienjem stanja kada je trenutna vrednost izlazne veliine pozitivna ili
nula. Takoe, realiza ija je mogua i primenom samo stanja kada je izlazna veliina ili pozitivna
ili negativna, ali je tada talasnost na izlazu vea.
8
Impulsni irinski modulator
Impulsni irinski modulator je sistem koji na osnovu moduliueg signala generie impulsno
irinski modulisan signal zadate frekven ije. Modulator se sastoji iz komparatora, prikazanog
na sli i 10 i os ilatora koji generie trougaoni ili testerasti napon zadate frekven ije i amplitude.
vM +
vPWM

vOSC
Slika 10: Impulsni irinski modulator.
vOSC, vM
Va A
B C vM
-TS/2 TS/2 t
vOSC
D -Va E
vPWM
-TS/2 0 TS/2 t
dTS
(d/2)TS (d/2)TS
TS
Slika 11: Impulsni irinski modulator, vremenski dijagrami signala.
Signali na ulazu i izlazu impulsnog irinskog modulatora su prikazani na sli i 11. Na osnovu
slinosti trouglova ABC i ADE sledi
Va vM d TS
=
2Va TS
odakle je
1 vM
d = 1
2 Va
pa je faktor ispunjenosti impulsa na izlazu impulsnog irinskog modulatora

1 vM

d=1d = 1+ .
2 Va
9
Faktor 2d 1 koji se esto sree u analizi invertora je
vM
2d 1 =
Va
pa je izlazna veliina monofaznog invertora sa spregnutim upravljanjem stubovima
propor ionalna moduliuem signalu.
Modulator radi u linearnom reimu za Va vM Va kada je 0 < d < 1. U linearnom
reimu, pod pretpostavkom da je
vM = m Va sin (0 t)
amplituda izlaznog napona monofaznog naponskog invertora sa spregnutim upravljanjem

stubovima je
Vm = m VIN
|m| 1. |m| > 1
overmodulation
i linearno je zavisna od indeksa modula ije za Ukoliko je dolazi do
premodula ije ( ) kada se javljaju intervali prekidanja tokom kojih prekidai
ne menjaju stanje. U ovoj oblasti je amplituda generisanog napona vea od VIN , ali je izlazni
napon izoblien. Krajnji ishod poveanja amplitude moduliueg signala, odnosno indeksa
modula ije, je zasienje u kome u tokom periode moduliueg signala invertor samo jednom
menja stanje to na izlazu daje napon pravougaonog oblika. Tada je amplituda generisanog
napona
4
Vm = VIN 1.2732 VIN

to je za 27.32% vie od maksimuma u linearnom reimu. Ovo poveanje amplitude
fundamentala (osnovnog harmonika) izlaznog napona je praeno izoblienjem, dakle poveanim
sadrajem viih harmonika. Sama grani a sigurnog zasienja modulatora je zavisna od oblika
Vm/VIN
1.27
0 1 mX m
linear overmodulation saturation
Slika 12: Impulsni irinski modulator, kriva modula ije.
izlaznog napona os ilatora i odnosa frekven ija os ilatora i moduliueg signala. U sluaju
simetrinog trougaonog napona na izlazu os ilatora, prikazanog na sli i 11, modulator je sigurno
zasien za
2 fS
m>
f0
to odreuje mX sa slike 12.
10
Spektar generisanog napona
x(t)
1
TS /2 0 TS /2 t
d TS
Slika 13: Pobudni signal prekidaa.
+
X 2
x(t) = d + sin (kd) cos (kS t)
k=1
k
2
S =
TS
X0 = d
2
XCk = sin (kd)
k
XSk = 0
zasien modulator
+
4 X 1
vOU T = VIN sin ((2k 1) 0 t)
k=1
2k 1
4
VOU T m (2k 1) = VIN
(2k 1)
VOU T m (2k) = 0
11
Trofazni invertor
iIN
S1 D1 S3 D3 S5 D5
+
vIN
S2 D2 S4 D4 S6 D6
i1 i2 i3
v1 v2 v3
Slika 14: Trofazni invertor.
S1 S3 S5
VIN +

S2 S4 S6
v1 v2 v3
Slika 15: Trofazni invertor, pojednostavljena prezenta ija.
12
Tabela 6: Trofazni invertor, potpuno kontrolisana stanja.
stanje S1 S3 S5 v12 v23 v31
0 0 0 0 0 0 0
1 0 0 1 0 VIN VIN
2 0 1 0 VIN VIN 0
3 0 1 1 VIN 0 VIN
4 1 0 0 VIN 0 VIN
5 1 0 1 VIN VIN 0
6 1 1 0 0 VIN VIN
7 1 1 1 0 0 0
13
Impulsna irinska modula ija kod trofaznih invertora
VIN/2 +
S1 S3 S5
VIN/2 +
S2 S4 S6
v1 v2 v3
Slika 16: Impulsna irinska modula ija kod trofaznih invertora.
Kod impulsne irinske modula ije:

1 2
dk = 1 + m sin 0 t (k 1)
2 3
k {1, 2, 3}

1 2
vk = m VIN sin 0 t (k 1)
2 3
1
Vm = m VIN
2
1
Vm max P W M = VIN
2
14
Trofazni sistem napona
v12 = v1 v2
v23 = v2 v3
v31 = v3 v1
Transforma ijom faznih napona u linijske se gubi informa ija o referentnom poten ijalu. Gde
god da je referentni poten ijal, linijski naponi su isti. Zbir tri linijska napona uvek mora da
bude jednak nuli prema Kirhofovom zakonu za napone, linearno su zavisni. Zbir faznih napona
u optem sluaju ne mora biti jednak nuli, ne postoji ziko ogranienje koje to uslovljava ni
bilo kakva zavisnost izmeu njih.
Transforma ija linijskih napona u fazne je u matrinoj formi data sa

v12 1 1 0 v1

v23 = 0 1 1 v2

v31 1 0 1 v3

1 1 0

det 0 1 1 = 0

1 0 1
Transforma iona matri a je singularna jer na osnovu linijskih napona nije mogue
jednoznano odrediti fazne napone. Kako je

1 1 0

rank 0 1 1 = 2

1 0 1
dovoljna je jedna dodatna jednaina da bi se odredili fazni naponi. Neka je
v1 + v2 + v3 = 0.
Ovo fazne napone ini linearno zavisnim, to oni u optem sluaju ne moraju biti, ali
se pogodnim izborom referentnog poten ijala (da nov referentni poten ijal bude vN =
(v1 + v2 + v3 ) /3) gornji uslov uvek moe ispuniti. Tada je

v1 1 0 1 v12
1
v2 = 1 1 0 v23

3

v3 0 1 1 v31
Za predstavljanje linearno zavisnih faznih napona dovoljna su dva realna broja, odnosno
jedan vektor u ravni, dat sa
V~P = (vP X , vP Y )
15
nazvan fazor napona. Jedinini vektori naponskih osa su
~i = (1, 0)
!
~j = 1 3
,
2 2
i !
~k = 1 3
, .
2 2
Linijski naponi se dobijaju kao skalarni proizvodi ( dot produ t ) fazora napona i jedininih
vektora odgovarajuih naponskih osa
v12 = ~i V~P
v23 = ~j V~P
i
v31 = ~k V~P .
v23
v31P
~P
V
0 v12P v12
v23P
v31
Slika 17: Odreivanje linijskih napona iz fazora.
16
Modula ija prostornih vektora
~6
V
v23
VIN VIN
~2
V ~4
V
~7
V
VIN ~0
V VIN v12
~5
V
~3
V
VIN VIN
v31
~1
V
Slika 18: Fazori koje moe da generie invertor.
~4
V
~4
d4 V
~SV M
V
~0 , V
V ~7
~5
d5 V
~5
V
Slika 19: Modula ija prostornih vektora.
V~SV M = da V~a + db V~b + d0 V~0 + d7 V~7
17
da + db + d0 + d7 = 1
Grani a za d 0 = 0, d 7 = 0:
V~SV M = da V~a + db V~b
db = 1 da

V~SV M = da V~a + (1 da ) V~b = V~b + da V~a V~b
18
Poreenje impulsne irinske modula ije i modula ije prostornih
vektora
~6
V
v23
VIN VIN
V~SV M
~2
V ~4
V
~7
V
VIN ~0
V VIN v12
~5
V
~3
V
VIN VIN
v31
~1
V
Slika 20: Modula ija prostornih vektora, maksimalna amplituda.
Kod modula ije prostornih vektora:
VLm max = VIN
1
Vm max SV M = VIN
3
Vm max SV M 2
= 1.1547
Vm max P W M 3
dobitak u amplitudi od 15.47% bez izmena u energetskom delu kola.
19
Six-step invertor
vP
S1 S3 S5
VIN +

S4 S6 S2
vM
v1 v2 v3
Slika 21: Six-step invertor, oznaavanje prekidaa.
1 2 3 4 5 6 1 2 3 4 5 6
0 T/2 T 3T/2 2T
t
S1 on
off
t
S2 on
off
t
S3 on
off
t
S4 on
off
t
S5 on
off
t
S6 on
off
t
Slika 22: Six-step invertor, stanja prekidaa.
20
S4 = S1
S6 = S3
S2 = S5
Tabela 7: Six-step invertor.
stanje S1 S3 S5 v12 v23 v31 v1 v2 v3

1 2 1
1 1 0 1 VIN VIN 0 VIN VIN VIN
3 3 3
2 1 1
2 1 0 0 VIN 0 VIN VIN VIN VIN
3 3 3
1 1 2
3 1 1 0 0 VIN VIN VIN VIN VIN
3 3 3
1 2 1
4 0 1 0 VIN VIN 0 VIN VIN VIN
3 3 3
2 1 1
5 0 1 1 VIN 0 VIN VIN VIN VIN
3 3 3
1 1 2
6 0 0 1 0 VIN VIN VIN VIN VIN
3 3 3
Linijski naponi:

2 3
V1m = VIN

6
V1RM S = VIN

r
2
VRM S = VIN
3
r
2
T HD = 1 31.08%
9
Fazni naponi:
2
V1m = VIN

2
V1RM S = VIN

2
VRM S = VIN
3
r
2
T HD = 1 31.08%
9
21
1 2 3 4 5 6 1 2 3 4 5 6
0 T/2 T 3T/2 2T
t
v12
VIN
t
-VIN
v23
VIN
t
-VIN
v31
VIN
t
-VIN
Slika 23: Six-step invertor, linijski naponi.
1 2 3 4 5 6 1 2 3 4 5 6
0 T/2 T 3T/2 2T
t
v1
2VIN/3
VIN/3
-VIN/3 t
-2VIN/3
v2
2VIN/3
VIN/3
-VIN/3 t
-2VIN/3
v3
2VIN/3
VIN/3
-VIN/3 t
-2VIN/3
Slika 24: Six-step invertor, fazni naponi.
22
1 2 3 4 5 6 1 2 3 4 5 6
0 T/2 T 3T/2 2T
t
vP
t
VIN/3 2VIN/3
vM
-2VIN/3 -VIN/3
Slika 25: Six-step invertor, naponi pozitivnog i negativnog ulaznog terminala invertora.
23
Problem sa faznim naponima
vP
VIN/2 +
S1 S3 S5
VIN/2 +
S4 S6 S2
vM
v1 v2 v3
Slika 26: Six-step invertor, uveden referentni poten ijal.
1 2 3 4 5 6 1 2 3 4 5 6
0 T/2 T 3T/2 2T
t
v1
VIN/2
t
-VIN/2
v2
VIN/2
t
-VIN/2
v3
VIN/2
t
-VIN/2
Slika 27: Six-step invertor, fazni naponi prema novom referentnom poten ijalu.
V N = V 1 Z I1
V N = V 2 Z I2
V N = V 3 Z I3
24
1 2 3 4 5 6 1 2 3 4 5 6
0 T/2 T 3T/2 2T
t
vP
VIN/2
vM
t
-VIN/2
Slika 28: Six-step invertor, naponi pozitivnog i negativnog ulaznog terminala invertora prema
novom referentnom poten ijalu.
1 2 3 4 5 6 1 2 3 4 5 6
0 T/2 T 3T/2 2T
t
vN
VIN/6
-VIN/6 t
Slika 29: Six-step invertor, poten ijal zvezdita (neutrala) simetrinog linearnog potroaa
prema novom referentnom poten ijalu.
3 V N = (V 1 + V 2 + V 3 ) Z (I 1 + I 2 + I 3 )
I1 + I2 + I3 = 0
1
VN = (V + V 2 + V 3 )
3 1
1
vN = (v1 + v2 + v3 )
3
25
vP
VIN/2 +
S1 S3 S5
VIN/2 +
S4 S6 S2
vM
i1 i2 i3
v1 v2 v3
iN vN
Slika 30: Six-step invertor, 3-wire i 4-wire povezivanje.
26
0 Operation principle of power semiconductors

0.1 Basic switching processes
Apart from a few special applications, power semiconductors are mainly used in switching
applications. This leads to some basic principles and operation modes which apply to all power
electronics circuitries. The most important goal of all efforts in developing the product range of
power semiconductors and their applications in circuits is to reach minimum power losses. Limit
conditions for the ideal switch are characterized as follows:
ideal switch
- On-state: vs = 0; - < is <
- Off-state: is = 0; - < vs <
- Switching behaviour: no conversion of energy during active turn-on/ turn-off
The application of such ideal switches and, consequently, the use of power semiconductors is
therefore subject to restrictive switching conditions.
Switches in inductive circuits (impressed current)

A switch applied in an inductive circuit (Fig. 0.1) can actively be turned on, i.e. it can be turned
on at any time. There is no power loss under the condition of infinite switching time, since the
bias voltage may drop directly over the line inductance.
If the circuit is live, turn-off is not possible without conversion of energy, since the energy stored
in L has to be converted. For this reason, turn-off of the switch without any energy conversion is
only possible if is = 0. This is also called passive turn-off, since the switching moment is
dependent on the current flow in the circuit. A switch that is running under these switching
conditions is called zero-current-switch (ZCS).
vs
L is
- On-state: vs = 0; - < is <

- Switching behaviour: active turn-on at |vs| > 0
passive turn-off at is = 0
Figure 0.1 Switch in an inductive

circuit
1
Switch between capacitive nodes (impressed voltage)

Nondissipative turn-on of a switch under a impressed voltage is only possible if vs = 0. This is
called passive turn-on, since the voltage waveform and, thus, the zero crossing is determined by
the outer circuit. Active turn-off, however, will be possible at any time. Switches running under
those switching conditions are called zero-voltage-switches (ZVS).
us
is
- On-state: vs = 0; - < is <

- Switching behaviour: active turn-off at |is| > 0
passive turn-on at vs = 0
Figure 0.2 Switch between

capacitive nodes
Figure 0.3 shows current and voltage waveforms during the basic switching processes described
above. The use of real power semiconductors as switches will lead to the following conditions.
Before active turn-on, the current-transferring semiconductor is under positive voltage. Voltage
may drop, if, triggered by the controller, the current increases by a certain rate given by the turn-
on mechanism of the power semiconductor.
This turn-on mechanism together with the series inductance is limiting the current rise and
voltage distribution within the circuit between power semiconductor and inductance. Turn-on
power losses of the given power semiconductor are diminished to a minimum value by increase
of inductance.
During passive turn-off of a live power semiconductor carrying current in positive direction,
current drops to zero due to the voltage polarity of the outer circuit. Current is conducted back as
reverse current by the charge carriers still stored in the semiconductor until the semiconductor
has recovered its blocking capability to take up the negative circuit voltage.
Active turn-off of a live power semiconductor will, first of all, produce a voltage rise in positive
direction triggered by the controller. Then, the effective parallel capacitance will take over the
current flow given by the turn-off mechanism of the power semiconductor. The energy loss
caused by the turn-off procedure is reduced by the increase of capacitance for the given power
semiconductor.
A passively switched power semiconductor is under negative voltage before turn-on. If this
voltage changes polarity due to processes in the outer circuit, the power semiconductor will take
up current in positive direction, which will lead to turn-on overvoltage in case of impressed
current rise.
2
Switching Process Waveform Equivalent Circuit
iS
V V
active ON Vq S iS S
Vq
d iS dV S
dt > 0 ; dt <0
Vq > 0
iS
iS
passive OFF V
S
Vq
di d VS
S <0 <0
; V
dt dt S
Vq Vq < 0
VS
active OFF
iS V
S iS
di dV S
S <0 >0
dt ; dt iq
V
S
iS
passive ON iq
iS
d iS d VS
>0 ; >0 V iq
dt dt S
Basic Switching Processes
Figure 0.3 Basic switching processes
Every power electronic system works according to two basic function principles:
firstly, turn-on and turn-off of connection leads between energy exchanging circuitries by
means of one switch each - called cyclic switching of single switches
and
secondly, alternating switching of two switches each, alternating current- and voltage-
carrying - called commutation.
Both basic principles may be integrated into one circuit and the circuit split into several different
operation modes.
3
0.2 Operation principle of power semiconductors

The operation principle of power semiconductors is clearly defined in the previously explained
active and passive switching procedures during cyclic switching of single switches and inductive
or capacitive commutation. Figure 0.4 shows a summary of the relationships between current and
voltage during the different possible switching procedures.
Hard switching (HS, Figure 0.7)

Hard turn-on is characterized by an almost total vK voltage drop over the current-carrying switch
S1 at a current commutation time tK causing considerable power loss peaks within the power
semiconductor. Commutation inductance is at its minimum value at that moment, i.e. the turned
on semiconductor determines the current increase. Current commutation is terminated by passive
turn-off of switch S2. Commutation and switching time are almost identical.
In case of hard turn-off, voltage over S1 increases up to a value exceeding voltage vK while
current continues flowing. Only then current commutation is started by passive turn-on of S2.
The commutation capacitance is very low, so that the voltage increase is mainly determined by
the features of the power semiconductor. Therefore, switching and commutation time are almost
the same and there are very high power loss peaks within the switch.
Soft switching (ZCS, ZVS, Figures 0.8 and 0.9)

In the case of soft turn-on of a zero-current-switch the switch voltage will drop relatively fast to
the forward voltage drop value, if LK has been dimensioned sufficiently. Thus, power losses in
the switches are almost avoidable during current commutation. Current increase is determined by
the commutation inductance LK. Current commutation is terminated by passive turn-off of S2,
which will cause an increase of the commutation time tK compared to the switching time tS.
Active turn-off of S1 will initialize soft turn-off of a zero-voltage-switch. The decreasing switch
current commutates to the capacitance CK and initializes the voltage commutation process. CK is
bigger than CKmin, which has considerable influence on the voltage increase rate. Power losses
will be reduced by the delayed voltage increase at the switch.
Resonant switching (ZCRS, ZVRS, Figures 0.10 and 0.11)

We are talking about resonant turn-on, if a zero-current-switch is turned on at that moment when
current iL almost drops to zero. Switching losses are still reduced compared to soft switching.
Since the switch cannot actively determine the time of zero-current crossing, the controllability
is slightly restricted.
On the other hand, we are talking about resonant turn-off of a zero-voltage-switch, if the
commutation voltage almost drops to zero during the turn-off process. Once again, switching
losses are reduced compared to soft turn-off of the zero-voltage-switch accepting the loss of one
control possibility.
Neutral switching (NS, Figure 0.12)

If the switch voltage as well as the switch current are zero at the moment of switching, this is
called neutral switching. This is mostly the case with the application of diodes.
4
ON OFF
E
V E
V V
V
Hard Switching
HS HS
V
V V
V
E
E
ZCS Soft Switching ZVS
V
V
E
V
ZCRS Resonant Switching ZVRS
iS
E
VS
V V
Neutral Switching NS
NS
Figure 0.4 Switching procedures (vK = driving commutation voltage, iL = load current)
5
0.3 Power electronic switches

A power electronic switch integrates a combination of power electronic components or power
semiconductors and a driver for the actively switchable power semiconductors. The internal
functional correlations and interactions of this integrated system determine several
characteristics of the switch.
Figure 0.5 shows the power electronic switch system with its interfaces to the external electric
circuitry (normally high potential) and to the control unit (information processing, auxiliary
power supply). The necessary potential separation is supported by optical or inductive
transmitters.
The possible combinations of power semiconductors differing from each other by switch current
and voltage direction are shown in Figure 0.6.
Galvanic Power Semiconductor Devices

Isolation Driver (e.g. MOSFETs; IGBTs; Diodes)
External
Snubbers
L INT L EXT
Control A
Unit GI1
C INT C EXT
Power GI2
Supply L INT B
L EXT
Internal
Parasitics
Figure 0.5 Power electronic switch system
On the one hand, the parameters of a complete switch result from the switching behaviour of the
semiconductor which, by design of the semiconductor chips, has to be adapted to the operation
mode of the whole switch. On the other hand, the driver unit is responsible for all main
parameters of the switch and takes charge the most important protectional functions.
6
iS current-unidirectional current-bidirectional
vS
voltage-unidirectional
(foward blocking)
AGTO
DR
DR
DR
( foward and reverse blocking)
SGTO
voltage-bidirectional
DR
SGTO DR DR
DR
DR
DR DR
DR DR
SGTO = symmetrical GTO

AGTO = asymmetrical GTO
Figure 0.6 Possible combinations of power semiconductors
Basic types of power electronic switches

Due to the operational principles of power semiconductors, which are mainly responsible for the
dominant characteristics of the circuits, power electronic switches may be split up into the
following basic types. The main current and voltage directions result from individual circuit
requirements.
Hard switch (HS, Figure 0.7)

Except for the theoretical case of pure ohmic load, a single switch with hard turn-on and turn-off
switching behaviour can be used only together with a neutrally switchable power semiconductor
in a commutation circuit with a minimum passive energy store (CKmin; LKmin). Compared to the
neutral switch which does not have any control possibility, the hard switch may be equipped
with two control possibilites, namely individually adjustable turn-on and turn-off. Figure 0.7
shows the possible switch configurations. As for the symmetrical switch arrangements, only one
alternating current-carrying switch will operate acitvely with two control possibilities while the
other one switches neutrally.
7
S1 S1
iL iL
VK VK
=
S2 S2
S1 S1
iL iL
VK VK
=
S2 S2
Figure 0.7 HS commutation circuits
Zero-current-switch (ZCS, Figure 0.8)

Power semiconductors in zero-current-switches are turned on actively and turned off passively.
Accepting the loss of one control possibility compared to HS, active switching may proceed with
considerably decreased power losses due to sufficient series inductance. Figure 0.8 shows the
possible switch configurations of a ZCS in an equivalent commutation circuit, which are also
applicable in circuits with cyclic switching without commutation. Such circuits are characterized
by continuous inductive commutation processes, i.e. active turn-on is followed by passive turn-
off.
LK LK
2 2
S1 S1
iL iL
VK VK
LK S2 LK S2
2 2
LK
2
S1
iL
VK
LK
2 S2
Figure 0.8 ZCS commutation circuits
8
Zero-voltage-switch (ZVS, Figure 0.9)

Zero-voltage-switches are designed in such a way that they may be turned off actively and turned
on passively when the switch voltage drops to zero. Active turn-off may just cause very low
losses, if the parallel capacitance has been chosen high enough. Compared to HS a decrease of
power losses is possible by accepting the loss of control possibility. Figure 0.9 shows the
possible switching arrangements of zero-voltage-switches in capacitive commutation circuits.
However, zero-voltage-switches may also be applied in circuits without commutation, where
active turn-off and passive turn-on of the same switch are alternating.
CK CK
S1 S1
2 2
iL iL
VK VK
CK CK
S2 S2
2 2
CK
S
2 1
iL
VK
CK
S
2 2
Figure 0.9 ZVS commutation circuits
Zero-current-resonant-switch (ZCRS, Figure 0.10)

If a zero-current-switch is controlled in such a way that active turn-on is started exactly when
current is at zero-crossing, there will be no current commutation. Consequently, even if there is a
minimum commutation inductance, the power losses are lower than in zero-current-switches;
they are just caused by the still necessary change in charge of the junction capacitances of the
power semiconductors. The further power loss reduction compared to ZCS demands, at the same
time, another loss of controllability, since the turn-on moment is not controllable, but is triggered
by the zero-current-crossing given by the outer circuitry. Energy flow can only be controlled
indirectly with ZCRS, either conducting or rejecting several current cycles.
S1
iL
VK
S2
Figure 0.10 ZCRS commutation circuit
9
Zero-voltage-resonant-switch (ZVRS, Figure 0.11)

This basic type of switch is a borderline case of the ZVS. If a ZVS actively turns off exactly at
zero-crossing of the applied commutation alternating voltage, the increasing switch voltage will
trigger the current commutation process. Even in the case of minimum commutation capacitance
power losses are reduced, however at the expense of active controllability. Indirect control is
also possible with the ZVRS, if several commutation voltage cycles are connected through or
rejected.
S1
iL
VK
S2 =
Figure 0.11 ZVRS commutation circuit
Neutral switch (NS, Figure 0.12)

A commutation process is finished by neutral turn-on or turn-off of a neutral switch. In this case
current and voltage drop to zero. Generally, a diode already includes these features. A neutral
switch with actively switchable power semiconductors owes this special features to a special
driver circuit.
S1 S1
iL iL
VK VK
S2 S2 =
Figure 0.12 NS commutation circuits
Figure 0.13 shows a summary of all basic types of power electronic switches. The blank squares
are modifications of the basic types, which are required in almost all applications. If the resonant
conditions in a circuit working with soft or resonant switches are broken, the switches will have
to cope with hard switching apart from their original features (modified ZVS = MZVS; modified
ZCS = MZCS), in order to keep up operation of the whole system (see also chapter 3.8). Mostly,
the switches are operated in this deviating mode only for a very short time. In the case of hard
active turn-off of a ZVS or hard active turn-on of a ZCS, the switches are operated as ZVHS and
ZCHS, respectively.
10
ON
soft Resonant neutral
OFF hard
LK in Series iL = 0 VS = 0
hard HS MZCS ZVHS
soft MZVS ZVS

CK in Parallel
resonant ZVRS
VK = 0
neutral ZCHS ZCS ZCRS NS

iS = 0
Figure 0.13 Power electronic switches
11
1 Basics
1 Basics
1.1 Application fields and todays application limits of IGBT and
MOSFET power modules
V [V]
104
7500
6500 SCR-DISCS
4500
GTO/IGCT-
3300 DISCS
2500
IGBT-Modules
1700
103
Power MOSFET-
Modules
200
102
102 103 2400 3000 6000 104 I [A]
Figure 1.1 Application fields of the latest power semiconductors
As shown in Figure 1.1, a variety of circuitries in power electronics can be produced today with
MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate
Bipolar Transistors), which were introduced into the market one by one in the mid 80s.
Compared to other switchable power semiconductors, such as conventional GTO-thyristors,
these types of transistors have a number of application advantages, such as active turn-off even
in case of short-circuit, operation without snubbers, simple control unit, short switching times
and, therefore, relatively low switching losses.
The production of MOSFETs and IGBTs is comparatively simple and favourable and can easily
be managed by todays technologies in microelectronics.
It was mainly due to the rapid development of IGBTs and power MOSFETs that power
electronics continued open up new markets, and that their fields of application increased
tremendously at the same time. Bipolar high-voltage power transistors that were still very
common a few years ago, have been almost completely replaced by IGBTs.
13
1 Basics
Most applications for currents of some 10A use transistors with silicon chips that are integrated
in potential-free power modules. These modules contain one or several transistor systems, diodes
adapted to the transistors (free-wheeling diodes) and, if required, passive components and
intelligence, see chapter 1.4..1.6.
Despite the disadvantage of one-side cooling, power modules are maintaining their hold in high-
power electronics against the meanwhile also available disc-cells with IGBTs and diodes, which
are able to dissipate about 30 % more of the heat losses by two-side cooling. This is mainly due
to integrated, tested isolation of the chips to the heatsink, possible combinations of different
components in one module and low costs due to batch production, apart from their easy
assembly.
IGBT-modules especially, are going through a permanently successful process of market

penetration accompanied by increased efficiency, withstanding the new and further development
of other - competitive - power semiconductors. Today IGBT-modules are produced managing a
forward blocking voltage of 6.5 kV, 4.5 kV, 3.3 kV and 2.5 kV, e.g. 3.3 kV/2.4 kA [192], [196].
IGBT converters (multi-level-switch and IGBTs in series connection) for the MW-range up to
more than 6 kV supply voltage can already be produced now .
MOSFETs, on the other hand, are being developed for even higher frequency applications; also
in the high current range more than 500 kHz can be produced with the corresponding wirings
and assembly topologies.
Apart from the small power application range, for which chip-on-chip solutions are gaining more
and more importance, IGBT and MOSFETmodules are the basic components for the integration
of complete electronic and also mechatronic systems in future.
1.2 Power MOSFET and IGBT
1.2.1 Different structures and functional principles

In the following descriptions we restrict ourselves to n-channel-enhancement power MOSFETs
and IGBTs (enhancement transistors), representing the majority of transistors used in power
modules.
If a positive control voltage is applied, a conducting channel with electrons as charge carriers
(majority carriers) is generated within the existing p-conducting silicon. Without applying a
control voltage, these components would block (self-blocking).
Other designs, which will not be dealt with any further in this chapter, are p-channel-
enhancement transistors (induction of a positively charged channel within p-silicon by applying
negative control voltage/self-blocking) and n- and p-channel depletion types (depletion
transistors), which turn on without applied control voltage (self-conducting). In these transistors,
the control voltage generates a space charge zone that cuts off the channel and interrupts the
main current flow.
In most applications the vertical structures shown in Figure 1.2 and Figure 1.4 are used, where
gate and source (MOSFET) or emitter (IGBT) are located on top of the chip, whereas the chip
bottom serves as drain (MOSFET) or collector connection. The load current is conducted
vertically through the chip outside the channel.
The power MOSFETs and IGBTs shown in the sections have a planar gate structure, i.e. a
lateral (horizontal) conductive channel is generated in case of on-state.
The planar gate, which has been further developed to the double-implanted gate in modern high-
density transistors, is the dominating gate structure for power MOSFETs and IGBTs still today.
14
1 Basics
However, recently developed transistors have a trench-gate-structure, with the gates integrated
vertically to the structure. During on-state, a vertical channel is generated on both sides of the
gate. These and other new developments not dealt with any further in this chapter will be
discussed in chapter 1.2.4.
The lateral MOSFET- and IGBT-structures taken over from microelectronics also have their
drain- or collector layer allocated on their chip surface as n+-(MOSFET) or p+-well. Load
current is conducted horizontally through the chip. Since the n-zone can be isolated to the IC-
substrate by an oxide layer, several isolated MOSFETs or IGBTs may be integrated together
with other structures on one chip.
Due to the fact that lateral transistors are only able to generate a current density of about 30 % of
that in vertical structures and, thus, require more space on the assembly, they are used preferably
in complex, monolithic circuits.
The structural design of the power MOSFET (Figure 1.2) as well as the IGBT (Figure 1.4)
consists of a silicon-micro-cellular structure of up to 820,000 cells per cm2 (latest high-tech
60 V-MOSFETs) or about 100,000 cells per cm2 (high-voltage-IGBTs) distributed over a chip
surface of 0.3...1.5 cm2.
The cell-sections show the analogue structure of the MOSFET and IGBT control zones.
The n--zone has to take up the space charge zone during off-state and accommodates p-charged
wells with a low marginal (p-) and a high central (p+) doping.
These wells also include n+-silicon-layers which are connected to the aluminium- metallized
source (MOSFET) or emitter (IGBT) electrode. A control zone (gate) consisting, for example, of
n+-polysilicon is embedded in a thin isolation layer of SiO2 above the n+-areas.
By applying a sufficient positive control voltage between gate and source (MOSFET) or emitter
(IGBT), an inversion layer (n-conducting channel) is generated in the p-area below the gate.
Electrons may be conducted from source or emitter to the n--drift-area via this channel.
In contrast to the identical structure of MOSFET and IGBT including the n--zone, there are
differences regarding the third electrode, which will determine all further functions.
15
1 Basics
Power-MOSFET [277]
Source A Gate Source
B D
Drain
Al
SiO2
n+
-
d
-
p- p- G
- Gate
p+ - p+
Source
- S
-
-
D
- Drain
-
-
- G
Gate
-
n- - n-
n+ n+
Source
S
B A
-
Drain -
a) b)
A-B: wide of elementary cell
d: length of channel
Figure 1.2 Power-MOSFET (SIPMOS Siemens)

a) MOSFET-cell with charge flow during on-state
b) Common switch symbols
Figure 1.2 explains the structure and function of a vertical n-channel-enhancement power-
MOSFET with planar gate structure.
The MOSFETs layer structure described above results from epitaxial, implantation and
diffusion processes on a substrate of n+-conductive silicon material with a drain contact on its
reverse side.
The electrons flowing in the electrical voltage field between drain and source are attracted by the
drain connection, thus absorbing the space charge zone; consequently, the drain-source voltage
will decrease and the main current (drain current) will be able to flow.
Since the electrons are conducting current by 100 % and are majority charge carriers in the n--
drift area, the highly resistive n--zone will not be flooded by bipolar charge carriers; the
MOSFET is a unipolar component.
Whereas the drain-source on-resistance of low-voltage MOSFETs is composed of single cellular
resistances about 5 % to 30 %, 95 % of the RDS(on) of high reverse voltage MOSFETs result from
the n--epitaxial area resistance.
Therefore, on-state voltage drop
VDS(on) = I D R DS(on) with ID: drain current and
R DS(on) = k V(BR)DS 2.4...2.6 with k: material constant, e.g. k = 8.3 10 -9 A -1

for a chip surface of 1 cm2;
V(BR)DS: Drain-source forward breakdown voltage
as a theoretical limit value of the actually available MOSFETs is always higher for MOSFETs
from about 200...400 V off-state voltage than for comparable bipolar components and the current
16
1 Basics
carrying capacity is lower. Recently developed structures with improved parameters will be dealt
with in chapter 1.2.4.
On the other hand, there are no storage effects because the majority charge carriers are
exclusively responsible for charge transportation. Very short switching times may be produced
however, requiring rather high control currents for changing the internal capacitances in the case
of extensive components (high voltage/ high current) with about 0.3 C per cm2 chip surface.
The capacitances resulting from the physical structure of the MOSFETs are the most important
parasitic elements in Figure 1.3; their influence on the characteristics of components will be
described in the corresponding chapters.
Source CGS Gate Source
RG
D
(Drain)
Al
SiO2
n+
RW
RD
p- CGD p-
p+ p+
CDS CGD CDS
RD
RG
G
(Gate)
CGS RW
n- n- "Inverse Diode"
n+ n+
(Source)
Drain S
a) b)
Figure 1.3 Power-MOSFET-cell with the most important parasitic elements

a) Parasitic elements within the cellular structure
b) Equivalent circuit with parasitic elements
The follwing table explains causes and designations of the parasitic capacitances and resistances
in Figure 1.3:
Symbol Designation
CGS Gate-source capacitance Overlapping gate and source metallization;
dependent on gate-source voltage; independent of
drain-source voltage
CDS Drain-source capacitance Junction capacitance between n--drift zone and p-
well; dependent on cell surface, drain-source
breakdown voltage and drain-source voltage
GGD Gate-drain capacitance Miller capacitance; generated by overlapping of
gate and n--drift zone
RG Gate resistance (internal) Poly-silicon-gate resistance; in modules with
several transistor chips often additional series
resistors are needed to minimize oscillations
between chips
RD Drain resistance Resistance of n--zone; often main part of
MOSFET-on-state-resistance
RW Lateral resistance of p- Base-emitter resistance of parasitic npn- bipolar
well transistor
17
1 Basics
IGBT [278]
Emitter A Gate Emitter

B
+ +
Collector
SiO2 Al C
n+
+ -
+ - +
d G E
+ p- +
p- -
+ - + Gate Emitter
p+ p+
-
-
+ - +
+ + - + +
+ + - + +
Collector
+ + - + +
C
+ + - + +
+ + - + + G
n- 2 3 1 1 3 2 n- Gate
p+ p+ E
Emitter
B A
+ + -
Collector - + +
A-B: wide of elementary cell

a) d: length of channel b)
Figure 1.4 IGBT with NPT-structure

a) IGBT-cell with charge distribution during on-state
b) Common switch symbols
Figure 1.4 explains structure and function of a vertical n-channel-enhancement IGBT with
planar gate and NPT-(Non-Punch-Through)-structure.
In contrast to MOSFETs, IGBTs are equipped with a p+-conductive area with connection to the
collector below the n-zone.
After having passed the n--drift area, the electrons enter the p+-area, thus arranging for positive
charge carriers (holes) to be injected from the p+-zone to the n--zone. The injected holes will
flow directly from the drift-area to the emitter-p-contact as well as laterally to the emitter passing
the MOS-channel and the n-well. In this way the n--drift area will be flooded with charge carriers
which are conducting the main current (collector current); this charge enhancement will lead to a
space charge reduction and, consequently, to a reduction of the collector-emitter voltage.
Although, compared to the pure ohmic on-state behaviour of the MOSFET, the IGBT has an
additional threshold voltage at the collector pn-junction layer, the on-state voltage of high-
voltage IGBTs (from about 400V) is lower than that of MOSFETs because of the enhancement
of minority carriers in the highly resistive n--zone. In comparison to MOSFETs, IGBTs may be
designed for considerably higher voltages and currents for similar chip surfaces.
On the other hand, the surplus p-storage charge QS that has not been extracted during the
collector voltage increase period has to recombine in the n--zone during turn-off. Qs has an
almost linear characteristic in the low-current range and rises proportionally to the forward
current in the rated current and overcurrent range according to a radical law. [282]:
Qs I0.8...1 in the low-load forward current range

Qs I0.5 in the rated current and overcurrent range.
Qs V(BR)CE 2...2.7
18
1 Basics
Storage charge enhancement and depletion processes cause switching losses, a delay time
(storage time) and a collector tail-current during turn-off. (see chapter 1.2.3).
Apart from the Non-Punch-Through-structure (NPT) shown in Figure 1.3, the Punch-
Through (PT)-structure is also applied in IGBTs today. It was the conceptional basis for the
first IGBTs.
Basically, the two structures differ in the PT-IGBTs highly-doped n+-layer (buffer layer)
between n-- and p+-zone and in the manufacturing process.
Whereas the n+- and n--layers in a PT-IGBT are usually generated on a p+-substrate by an
epitaxial procedure, the basis of the NPT-IGBT is a thin, hardly doped n-wafer, at the reverse
side of which the collector p+-zone is generated by implantation. The MOS-control zones on top
of both IGBTs are identical in their planar structure.
Figure 1.5 compares both IGBT-structures and their electrical field characteristics during off-
state.
Emitter Gate Emitter
Al
E
n n
p
p p
n-
n-
n+
p+ n+
p+
A x
Collector
a)
Emitter Gate Emitter
Al
E
n n
p
p p
n-
n-
p p
p
x
Collector
b)
Figure 1.5 IGBT-structures and off-state electrical field characteristics [193]

a) PT-IGBT
b) NPT-IGBT
19
1 Basics
The space charge zone in a PT-IGBT or IGET (E: epitaxial structure) spreads over the whole n--
area during off-state. In order to keep the epitaxial layer as thin as possible for high off-state
voltages also, the electrical field is reduced by the highly doped n+-buffer at the end of the n--
drift area.
The n--drift area in an NPT-IGBT or IGHT (H: homogeneous structure) is dimensioned large
enough so that the electrical field can be completely discharged within the n--drift area during
off-state at maximum off-state voltage. The electrical field cannot spread over the whole n--zone
(punch through) within the permissible operation range.
For further explanations on IGBT-functions and the deviating characteristics of PT- and NPT-
components it is, first of all, necessary to study the equivalent circuit resulting from the IGBT-
structure (Figure 1.6b).
Emitter CGE Gate Emitter
RG C
(Collector)
Al
SiO 2
n+
RW p- CGC p- RD
p + p +
CGC CCE
RD RG
G
CCE (Gate)
CGE RW
n- n-
p+ p+ (Emitter)
E
Collector
a) b)
Figure 1.6 IGBT-cell (NPT-structure) with the most important parasitic elements
a) Parasitic elements in the cellular structure
b) Equivalent circuit with parasitic elements
Causes and designations of the parasitic capacitances and resistances in Figure 1.6 are analogous
to Figure 1.3.
Symbol Designation
CGE Gate-emitter capacitance Overlapping gate and source metallization;
dependent on gate-emitter voltage; independent
of collector-emitter voltage
CCE Collector-emitter Junction capacitance between n--drift zone and p-
capacitance well; dependent on cell surface, drain-source
breakdown voltage and drain-source voltage
GGC Gate-collector capacitance Miller-capacitance: generated by overlapping of
gate and n--drift zone
RG Gate resistance (internal) Poly-silicon-gate resistance; in modules with
several transistor chips often additional series
resistors are needed to minimize oscillations
between chips
RD Drift resistance Resistance of n--zone (base resistance of a pnp-
transistor)
20
1 Basics
Symbol Designation
RW Lateral resistance of p- Base-emitter resistance of the parasitic npn-
well bipolar transistor
Apart from internal capacitances and resistances, the equivalent circuit of the IGBT also shows
features of the ideal MOSFET and the parasistic npn-transistor: n+-emitter zone (emitter)/p+-
well (base)/n-drift zone (collector) with the lateral p+-well resistance below the emitters as base-
emitter resistance RW. In addition to that a pnp-transistor may be generated by sequence of p+-
collector (emitter)/ n--drift (base)/ p+-well (collector), which represents together with the npn-
transistor thyristor circuit.
Latch-up of this parasitic thyristor may happen basically during on-state (when a critical current
density is exceeded, which decreases with rising chip temperature) and also during turn-off
(dynamic latch-up due to the increased hole current compared to on-state operation), as soon as
the following latch-up preconditions are met:
M ( npn + pnp ) = 1 with pnp , npn = T E
M: multiplication factor;
npn, pnp: current gain of the single transistors in base circuit;
T: base transportation factor;
E: emitter efficiency
This will lead to a loss of controllability of the IGBT and, therefore, to its destruction.
The following design measures will reliably prevent latch-up in modern IGBTs under all
permissible static and dynamic operation conditions; the turn-off current density of dynamic
latch-up, for example, is about 15 times the rated current density.
At first, the base-emitter resistance RW of the npn-transistor is reduced by means of
- high doping of the p+-well directly below the n-emitters, and
- shortening of the n-emitters
to such an extent, that the threshold voltage of the npn-transistor base-emitter diode will not be
reached in any permissible state of operation.
Furthermore, the hole current (npn-transistor base current) is kept on a minimum level by a low
current amplification in the pnp-transistor. However, switching behaviour and ruggedness have
to be optimized with the on-state characteristics which also depend considerably on the pnp-
transistor design.
This has been produced for PT- and NPT-IGBTs in different ways [278].
For PT-IGBTs, the efficiency (emitter efficiency) of hole injection of the p+-zone into the n--drift
area is very high, since the substrate is very thick and highly doped. The pnp-current
amplification may only be lowered with the help of the base transportation factor (n--drift zone,
n+-buffer), implementing additional recombination centres (e.g. by gold doping or electron beam
radiation) to reduce charge carrier life time in the n+-zone.
The hole current adds up to 40...45 % of the total current.
In case of NPT-IGBTs the p+-emitter zone generated at the collector by implantation is much
thinner than the PT-IGBT-substrate. Therefore, the doping material concentration can be exactly
dimensioned during wafer production. The very thin p+-layer guarantees a low emitter efficiency
(E = 0,5) of the pnp-transistor, so that it is not necessary to lower the base transportation factor
by reducing charge carrier life time.
The hole current sums up to 20...25 % of the total current.
21
1 Basics
Compared to the PT-IGBT, the NPT-IGBT shows the following advantages resulting from
diminished emitter efficiency, longer charge carrier life time and more exact design possibilities,
which is still to be detailed in chapters 2 and 3:
- positive on-state voltage temperature coefficient (automatic static balancing in the case of
parallel connection),
- lower, but partly longer turn-off tail current; lower turn-off losses at Tj = 125C,
- (in the case of hard switching) shorter switching times and reduced switching losses,
- considerably reduced temperature dependency of switching times / switching losses
(Tj = 125C) and tail current,
- increased overcurrent stability by improved current limitation in case of overload.
Compared to the epitaxial substrates of the PT-IGBT, todays production of the homogeneous n--
substrate as basic material for NPT-IGBTs is more favourable, provided that the much thinner
silicon wafers are handled properly.
1.2.2 Static behaviour

In this chapter the static behaviour of power MOSFETs- and IGBT-modules is to be examined
regarding the current-voltage characteristics of the main terminals in the Ist and IIIrd quadrant of
the respective output characteristic (Figure 1.7).
On-State Region
(Saturation Region) Active Region
ID, IC
On-State OP2
Current Forward Area
Pfw/max
Forward
Blocking
Current OP1
On-State Forward Blocking V , V
DS CE
Voltage Voltage
Reverse Blocking
(Series Diode)
Reverse Area
Reverse Conducting
(Antiparallel-Diode)
Figure 1.7 Basic output characteristic of a power transistor module
22
1 Basics
The Ist quadrant shows the forward area, where power transistor modules can block high
voltages and switch high currents.
The exact designation blocking state - analogous to thyristors - for blocking in the Ist quadrant
is hardly used in connection with transistors. Usually, this is called forward off- state (as in the
following explanations) or off-state (as long as there is no risk of confusion).
Via the gate electrode, the power-MOSFET or IGBT is turned from the forward off- state (OP1
in Figure 1.7) to the conductive state or on-state (OP2), where it can conduct load current. The
active region is only passed during switching.
Contrary to the perfect switch off-state voltage and on-state current are limited (see chapter 0).
During the forward off-state a cut-off current (forward off-state current) causes blocking power
dissipation within the transistors.
In the conductive state the voltage left at the main power terminals depends on the on-state
current and is called on-state voltage, causing on-state power dissipation. The maximum power
dissipation during on-state (not during switching) is shown by the on-state power dissipation
hyperbola for Pfw/max in the output charcteristic.
The current-voltage characteristics in the IIIrd quadrant of the output characteristic show the
reverse behaviour of power transistor modules, in case a negative voltage is applied to the main
terminals. This behaviour is determined by the characteristics of the transistors (reverse
blocking, reverse conducting) and the features of the diodes within the power module (connected
in series or anti-parallel to the transistors).
1.2.2.1 Power-MOSFET
The functional principles of the power-MOSFET described above result in the output
characteristics in Figure 1.8a.
23
1 Basics
Avalanche-Breakdown
Ohmic Region
ID
Active Region
V ID
RDS(on)= I DS ID
D
VGS @VDS
gfs =
VGS
VF0 VGS(th) VGS
VDS
VF (-VDS) VGS < VGS(th) V(BR)DSS
Forward Blocking
Characteristic
b)
a) IF (-ID)
Figure 1.8 a) Output characteristics of a power-MOSFET (n-channel-enhancement-type)

b) Transfer characteristic ID = f(VGS)
Forward off-state
When applying a positive drain-source voltage VDS and a gate-source voltage VGS smaller than
the gate-source threshold-voltage VGS(th), there will only be a very small zero gate voltage drain
current IDSS between drain- and source connection.
IDSS will rise slightly with increasing VDS. If a certain specified maximum drain-source voltage
VDSS is exceeded, this will cause an avalanche breakdown of the pin-junction p+-well/n--drift
zone/n+-epitaxial layer (breakdown voltage V(BR)DSS). Physically, V(BR)DSS is almost equivalent to
the breakdown voltage VCER of the parasitic bipolar npn-transistor in a MOSFET, generated by
the sequence of layers: n+-source zone (emitter)/p+-well (base)/n--drift zone/n+-epitaxial layer-
drain connection (collector), see Figure 1.3.
The multiplication current generated by the avalanche breakdown of the collector-base diode
may lead to destruction of the MOSFET as soon as the bipolar transistor is turned on.
However, the base and emitter zones are almost short-circuited by metallization of the source;
both zones are only separated by the lateral resistance of the p+-well.
Several structural improvements, such as small MOSFET cells, homogeneous cell arrangement,
low-resistive p+-wells, optimized marginal structures and highly homogeneous technological
procedures, may facilitate a very small avalanche breakdown current per cell in modern
MOSFETs, so that the bipolar transistor will not yet be turned on, in case the defined
specifications are strictly complied with.
24
1 Basics
Therefore, a permissible avalanche energy EA for single pulses or periodic load (limited by the
maximum chip temperature) can be defined; see chapter 2.2.1.
Since several parallelled MOSFET-chips in power modules cannot guarantee absolute
symmetrical conditions, the maximum EA-value is only applicable for one single chip.
On-state
The forward on-state at positive drain-source voltage VDS and positive drain current ID can be
divided into two characteristic regions (Figure 1.8, Ist quadrant).
Pinch-off or active region

At a gate-source voltage VGS slightly exceeding the threshold voltage VGS(th), current saturation
will cause a considerable drop of voltage over the channel (horizontal region of the output
characteristic). The drain current ID is controlled by VGS.
The transfer behaviour shown in Figure 1.8b is called forward transconductance gfs defined as
follows:
gfs = dID/dVGS = ID/( VGS-VGS(th)).
Forward transconductance in the pinch-off region rises proportionally to the drain current ID and
the drain-source-voltage VDS and drops with increasing chip temperatures.
Within the permissible operation conditions for power modules with several paralleled
MOSFET-chips, the pinch-off region is only passed during turn-on and turn-off.
On the other hand, stationary operation within the pinch-off region is mostly prohibited by the
manufacturer, because VGS(th) will drop when the temperature rises and, therefore, thermal
instability between the single chips might result from minor production deviations.
Ohmic region
The ohmic region, which is also called on-state during switching operations, is reached as soon
as ID is determined only by the outer circuit. The on-state behaviour can be characterized as the
quotient of changed drain-source-voltage VDS and drain-current ID via the turn-on resistance
RDS(on). Consequently, the forward voltage VDS(on) may be defined by the following equation
already mentioned in chapter 1.2.1 (large-signal behaviour)
VDS(on) = R DS(on) I D
RDS(on) is dependent on the gate-source voltage VGS and the chip temperature. RDS(on) is
approximately doubled within the MOSFET operation temperature range between 25C and
Reverse operation
During reverse operation (IIIrd quadrant) the MOSFETcharacteristic is equivalent to a diode
characteristic at VGS < VGS(th) (continuous curve in Figure 1.8a). This is caused by the parasitic
diode within the MOSFET; the MOSFET reverse on-state behaviour at closed channel is
controlled by the on-state voltage of the collector-base pn-junction or source-drain pn-junction,
respectively (inverse diode, bipolar current flow) (Figure 1.9a).
25
1 Basics
Source Gate Source
Al
n+ VGS = 0 V
p- p- VDS = -VF
p+ + p+
-
+ + +
-
-
- -
- -
n- n-
a)
n+ n+
Drain
Source Gate Source
Al
n+ VGS > VGS(th)

p- p-
VDS > -VF0 (z.B. -0.2 V)
p+ p+
-
- -
-
-
-
-
b)
n- n-
n+ n+
Drain
Source Gate Source
Al
n+
VGS > VGS(th)
p- p-
VDS < -VF0 (z.B. -0.7 V)
p+ p+
-
-
+
+ +
-
- - -
-
n- n- c)
n+ n+
Drain
Figure 1.9 Inverse operation of a power-MOSFET [277]

a) At closed channel (bipolar current flow)
b) At open channel and small negative VDS (unipolar current flow)
c) At open channel and big negative VDS (combined current flow)
The bipolar inverse diode is utilized for currents up to the limit values specified for MOSFETs.
In practice, however, the inverse diode
- causes relatively high on-state power losses, which have to be dissipated together with the
MOSFET power losses and
26
1 Basics
- sets limits to the MOSFETs application field as a hard switch (see chapter 0) by its
unfavourable turn-off behaviour.
As shown in Figure 1.9b the conductance in the MOSFET-channel is principally controllable

even at a negative drain-source-voltage, if a gate-source voltage is applied exceeding the
threshold voltage.
If the drain-source voltage is limited to a value lower than the inverse diode threshold voltage by
external components, for example by paralleling of a Schottky-diode, the inverse current will be
conducted from drain to source as a unipolar electron current (majority carrier current). Then,
the turning-off corresponds to the turn-off behaviour of a MOSFET.
The inverse current is dependent on VDS and VGS. (broken curve in Figure 1.8a).
Operation with combined current flow according to Figure 1.9c (semi-coloned curve in Figure
1.8a) is given, if the channel is open and a conducting bipolar inverse diode is connected (drain-
source voltage higher than diode threshold voltage). This results in a reduced on-state voltage
compared to simple paralleling of diode and MOSFET, since the injected charge carriers will
also diffuse laterally, thus increasing the MOSFETs conductivity.
Apart from that, MOSFET-chips with fast inverse diodes have been developed by several
manufacturers during the past few years (e.g. FREDFETs; Fast Recovery Epitaxial Diode Field
Effect Transistors)[277]. Hole life time at inverse operation is minimized in FREDFET-chips by
selective heavy-metal diffusion into the n--drift area, similar to the design of fast diodes.
1.2.2.2 IGBT
The functional principle of the IGBT described in chapter 1.2.1 results in the output
characteristic in Figure 1.10.
Avalanche-Breakdown
Saturation Region
Active Region
IC
IC
IC
gfs=
VGE
VGE
VCE
-VCE VGE < VGE(th)V(BR)CES
Forward Blocking
Characteristic VGE(th) VGE
IGBT without hybride b)

Antiparallel-Diode
IGBT with hybride

Antiparallel-Diode I (-I )
F C
a)
Figure 1.10 a) Output characteristic of an IGBT (n-channel-enhancement-type)

b) Transfer characteristic IC = f(VGE)
27
1 Basics
Forward off-state
In analogy to the MOSFET, the collector-emitter cut-off current ICES between collector and
emitter is only very small, if the collector-emitter voltage VCE is positive and the gate-emitter
voltage VGE is lower than the gate-emitter threshold voltage VGE(th) .
As a consequence of increasing VCE, the ICES-value rises slightly. When a certain specified
maximum collector-emitter voltage VCES is exceeded, there will follow an avalanche breakdown
of the pin-junction layers p+-well/n--drift zone/n+-epitaxial layer (avalanche breakdown voltage
V(BR)CES). Physically, V(BR)CES corresponds approximately to the reverse collector-emitter voltage
VCER of the bipolar pnp-transistor in the IGBT structure. (see Figure 1.6).
The multiplication current generated by the avalanche breakdown of the collector-base diode
may lead to destruction of the IGBT, as soon as the bipolar transistor is turned on.
However, base and emitter are almost short-circuited by metallization of the emitter, only
separated by the lateral resistance of the p+-well.
By several structural improvements within the IGBT, similar to the measures taken for
MOSFETs as described in chapter 1.2.2.1, the avalanche breakdown current per cell is kept at a
minimum level, which results in a high forward off-state voltage stability (avalanche stability).
On-state
Also with the IGBT, the forward on-state at a positive collector-emitter voltage VCE and a
positive collector current IC can subdivided up in two characteristic regions (Figure 1.10, Ist
quadrant).
Active region
At a gate-emitter voltage VGE slightly exceeding the threshold voltage VGE(th), current saturation
will cause a considerable voltage drop over the channel (horizontal region of the output
characteristics). The collector current IC is controlled by VGE.
The transfer behaviour shown in Figure 1.10b is called - in analogy to the MOSFET - forward
transconductance gfs defined as follows:
gfs = dIC/dVGE = IC/( VGE-VGE(th))
Forward transconductance in the cut-off region rises proportionally to the collector current IC and
the collector-emitter voltage VCE, and decreases with increasing chip temperatures.
Within the permissible operation conditions for power modules with several paralleled IGBT-
chips, the cut-off region is only passed during turn-on and turn-off.
Equivalent to MOSFET modules, stationary operation within the cut-off region will mostly be
prohibited, since VGE(th) will decrease when the temperature rises and, also with IGBTs, thermal
instability between the single chips might result from minor production deviations.
Saturation region
The saturation region (steep region of the output characteristic), also called on-state during
switching operation, is reached as soon as IC is determined only by the outer circuit. The on-state
behaviour is characterized by the IGBT voltage VCEsat (collector-emitter saturation voltage). At
least for highly blocking IGBTs, the saturation voltage is considerably smaller than the on-state
voltage of a comparable MOSFET due to the n--drift-zone being flooded with minority carriers.
As already mentioned, VCEsat of PT-IGBTs will drop at a temperature increase within rated
current operation, whereas VCEsat of NPT-IGBTs will rise proportionally to the temperature.
28
1 Basics
Reverse operation
During reverse operation (Figure 1.10, IIIrd quadrant) the IGBT collector pn-junction is poled in
reverse direction and there is no inverse conductivity, other than with MOSFETs.
Although, due to the large n--drift zone, this is actually the structure of a highly resistive pin-
diode, at least in the case of NPT-IGBTs, the reverse voltage in todays IGBTs is only some
10V. Apart from design of the chip margin, this is due to the fact that the chips have been
designed mainly to comply with a high off-state voltage and an optimized collector heat
dissipation.
IGBT-switches designed for special reverse applications have therefore been equipped solely
with adapted, fast hybrid diodes connected in series.
So, the characteristics of the external or hybrid diodes (see chapter 1.3) are exclusively
responsible for the reverse on-state behaviour of IGBT-modules.
1.2.3 Hard switching behaviour of MOSFETs and IGBTs

Most switching applications for transistor switches require hard switching of ohmic-inductive
loads with continuous load current, i.e. the time constant of the load L/R is much bigger than the
cycle l/f of the switching frequency.
The resulting basic waveforms for drain or collector current and drain-source or collector-emitter
voltage are shown in Figure 1.11a.
VGG
VGS(th)
VGE(th)
t1 t2 t3 t4 t
iD, iC
IL
MOSFET It (IGBT)
vDS, vCE
VDD
VCC
VDS(on) MOSFET
VCE(sat)
a) IGBT t
29
1 Basics
VDD
IL
iD, iC
on
IL iD
VGG
off VCC
IL
VDD vDS, vCE

VCC
iC
VGG
b)
Figure 1.11 Typical hard switching behaviour of MOSFET and IGBT (ohmic-inductive load with
free-wheeling circuit)
a) Current and voltage waveforms
b) Curve and measurement circuit
As already depicted in chapter 0, Figure 0.4 a high short-time transistor current and voltage
during turn-on and turn-off are typical features of hard switching.
In contrast to all types of thyristors, such transistors operate without passive snubber networks
thanks to the dynamic junction which is generated in the drift zone during switching operation.
In a transistor, however, considerable switching energy
E on , E off = u idt
t on , t off
is dissipated as explained by the graph iC = f(vCE) (and iD = f(vDS)) in Figure 1.11b.

The curve may be directed nearer towards the axes with passive snubber networks. Switching
losses are shifted from the transistor to the snubber, the total efficiency will decrease in most
cases (chapter 3.8).
Since the size of the operating area is influenced by many (non-ideal) transistor features apart
from current/ voltage limitations and switching times, the SOA (Safe Operating Area) is given in
the datasheets for different operating conditions (see chapters 2.1.2, 2.2.3 and 2.3.3).
Moreover, passive circuit elements have a tremendous influence on switching losses and
operating areas, apart from the non-ideal transistor features and the diode characteristics
described in chapter 1.3. The effects of such passive circuit elements also indicated in Figure
1.11a are explained in detail in chapter 3.4.1.
Physically, the typical current-voltage characteristics in Figure 1.11a are caused by the free-
wheeling diode, which has to prevent current snap-off by load inductance:
30
1 Basics
- When the transistor is turned on, the free-wheeling diode can only take up reverse recovery
voltage (turn off), after the load current has completely commutated to the transistor.
Therefore, the collector or drain-current has to reach the load current level, before the
collector-emitter (or drain-source) voltage may fall to the on-state value.
- When the transistor is turned off, the free-wheeling diode can only take up the load current
(turn on), after it has reached on-state voltage polarity. This will be the case when the
collector-emitter (or drain-source) voltage has exceeded the commutation voltage level,
before the collector or drain-current may fall to the cut-off current value.
As shown in Figure 1.11a, the drain-source or collector-emitter voltage of comparable

components will, shortly after turn-on of the MOSFET or IGBT, drop within some 10ns to a
value, that is equivalent to the voltage drop over the n--drift area. Whereas in the MOSFET the
on-state voltage has already been reached by this, the n--area of the IGBT is now flooded with
positive charge carriers from the p-collector zone. After this procedure has been finished (appr.
100ns up to some s), the static value of the on-state saturation voltage V CE(sat), which is
relatively low for highly blocking components, has been reached (conductivity modulation).
During turn-off of the MOSFET, the internal capacitances have to be recharged, that there are no
charge carrier influence left in the channel area. Thereafter, the neutrality interferences in this
area will quickly be reduced and the drain current will drop rapidly.
The procedure within the IGBT is principally the same. However, after the emitter current in the
n--drift zone has been turned off, a large number of p-charge carriers generated by injection from
the IGBT-collector zone is still left. These p-charge carriers have now to be recombined or
reduced by re-injection, which would cause a so-called collector tail current It. (Figure 1.11a).
Since this tail current will fade away within some s only with already increased collector-
emitter voltage, the hard turn-off power losses in the IGBT are mainly determined by the tail
current waveform (see chapter 2.3.2, 3.1.3) and are considerably higher than those in MOSFETs.
Apart from the explained differences, the switching behaviour of MOSFETs is very similar to
that of IGBTs due to the equivalent gate structure.
As described in chapter 1.2.1, the forward on-state and forward off-state capability, the reverse
behaviour and the limits of the transient currents and voltages during switching are influenced by
the internal structures of the bipolar transistor and the lateral resistances.
The switching behaviour (switching velocity, switching losses) of MOSFET and IGBTpower
modules is determined by their structural, internal capacitances (charges) and the internal and
outer resistances.
Contrary to the ideal of a powerless voltage control via the MOSFET or IGBTgate, a frequency-
dependent control power is required resulting from the necessary recharge currents of the
internal capacitances, see chapter 3.5.
Moreover, the commutation processes are affected by the parasitic connection inductances
existing in the power layout and generated by connection of transistor chips in power modules;
they induce transient overvoltages and may cause oscillations due to the circuit and transistor
capacitances (see chapter 3.4).
In the following, the switching behaviour of MOSFETs and IGBTs is to be analysed in relation
to the internal capacitances and resistances of the transistor.
31
1 Basics
When the MOSFET (IGBT) is turned off, CGD (CGC) is low and is approximately equal to CDS
(CCE).
During on-state CGD (CGC) will increase rapidly due to inversion in the enhancement layer below
the gate zones, as soon as the gate-source (emitter) voltage has exceeded the drain-source
(collector-emitter) voltage.
Additionally, CGD (GGC) will increase dynamically during the switching procedure due to the
Millereffect:
CGDdyn = CGD ( 1- dvDS/dvGS) (MOSFET)

CGCdyn = CGE ( 1- dvCE/dvGE) (IGBT)
In most datasheets the following voltage-dependent low-signal capacitances of turned off

transistors are given (see chapters 2.2.2, 2.2.3).
IGBT
Power MOSFET
Ciss = CGS + CGD Ciss = CGE + CGC Input capacitance
Crss = CGD Crss = CGC Reverse transfer capacitance
Coss = CGD + CDS Coss = CGC + CCE Output capacitance
For calculation of the switching behaviour, these datas may only be applied to a certain extent,
since e.g. Ciss and Crss will again increase enormously in a fully switched on transistor
(VDS < VGS bzw. VCE < VGE), a fact that is not considered in most datasheets (Figure 1.12 and
Figure 1.13) [277].
Therefore, switching times in relation to gate current, drain-source voltage and drain current are
determined with the aid of the MOSFET gate charge characteristic indicated in the datasheets,
plotting the gate-source voltage over the gate charge QG on condition of rated current and
20 % or 80 % of the maximum drain-source voltage (Figure 1.12).
Load conditions and measurement circuit are equivalent to Figure 1.11. However, for
simplification purposes, constant current is supposed to be fed to the gate.
Now, switching intervals may be determined very simply with the following relation (see chapter
3.5.1):
iG = dQG/dt
32
1 Basics
VGS [V] 16
VDS1<VDS2
VDS1 VDS2
VGG 10
t4(VDS2)
t3(VDS2)
t1 t2 t3(VDS1) t4(VDS1)
VGS(th)
2
0
QG1 QG2 250 QG3 500 QGtot QG [nC]
Figure 1.12 a) Gate-source voltage characteristic (VGS) of a power MOSFET dependent on the gate charge QG (gate
charge characteristic)
b) Low-signal capacitances of a power MOSFET
Turn-on: switching interval 0...t1 (blocked transistor)

Gate current will be triggered by applying a control voltage.
Up to the charge quantity QG1 the current iG solely charges the gate capacitance CGS. The gate
voltage VGS rises. As VGS is still below the threshold voltage VGS(th), no drain current will flow
during this period.
Turn-on: switching interval t1...t2 (rise of drain current)

As soon as VGS has reached VGS(th)-level at t1, the transistor is turned on, first passing the active
region (see chapter 1.2.2.1).
Drain current rises to IL-level (ideal free-wheeling diode) or even exceeds IL - as indicated in
Figure 1.11a for a real free-wheeling diode. Similarly, VGS, which is connected to the drain
33
1 Basics
current in the active region by the transconductance gfs with ID = gfs * VGS, will increase up to the
value VGS1 = ID/gfs (time t2).
Since the free-wheeling diode can block the current only at t2, VDS will not drop considerably up
to t2.
At t = t2 charge QG2 has flown into the gate.
Turn-on: switching interval t2...t3 (transistor during turn-on)

When the free-wheeling diode is turned off, VDS will drop almost to on-state value VDS(on) by
time t3. Between t2 and t3 drain current and gate-source voltage are still coupled by
transconductance; therefore, VGS remains constant. While VDS is decreasing, the Miller
capacitance CGD is recharged by the gate current iG with the charge quantity (QG3-QG2). By t = t3
charge QG3 has flownflown? into the gate.
Turn-on: switching interval t3...t4 (ohmic characteristic area)

At t3 the transistor is turned on, its curve has passed the pinch-off area to enter the ohmic area.
VGS and ID are no longer coupled by gfs.
The charge conducted to the gate (QGtot-QG3) at this point affects a further increase of VGS up to
the gate control voltage VGG. Since the drain-source on-resistance RDS(on) depends on ID and VGS,
the on-state voltage VDS(on) = ID * RDS(on) may be adjusted to the physical minimum by the total
charge quantity Qgtot conducted to the gate.
The higher the drain voltage VDD (or commutation voltage), the bigger the charge Qgtot required
to reach a certain gate-source voltage, see Figure 1.12.
Turn-off
During turn-off the described processes are running in reverse direction; the charge QGtot has to
be conducted out of the gate by the control current.
For approximations to determine the gate charge quantity required for turn-off, the gate charge
characteristic in Figure 1.12 may be used.
The further the specific transistor application deviates from the hard switch-application
described, the more the step-form of the gate-source voltage blurs. The intervals decoupled by
the free-wheeling diode during hard switching will then more or less merge into one another,
which requires a more complex explanation of the switching behaviour. [278].
The above-mentioned description may be applied to IGBTpower modules by analogy. The

switching behaviour can be determined correspondingly by the gate charge characteristic also
indicated in the datasheets.
Since an IGBTgate is mostly switched between a positive and a negative gate voltage, also a
certain charge quantity is required to switch the gate capacitance between 0V and VGG-.
Therefore, the gate charge characteristic has to be extended as depicted in Figure 1.13. to
calculate the total gate charges.
34
1 Basics
VGE [V]
VCE2>VCE1
VCE1 VCE2
VGG+ 15
t4(VCE2)
t3(VCE2)
t1 t2 t3(VCE1) t4(VCE1)
VGE(th)
QG- 0
QG1 QG2 250 QG3 500 QGtot QG [nC]
a)
VGG-
b)
Figure 1.13 a) Extended IGBT gate charge characteristic for gate control between VGG+ and VGG-
b) IGBT low-signal capacitances
1.2.4 New developments in MOSFET and IGBT technology

For the time being, the most important goals in research and development of MOSFET- and
IGBT chips are:
a) Reduction of the on-state voltage
b) Reduction of switching power losses
c) Improved ruggedness (overcurrent-, overvoltage-behaviour, switching performance)
d) Increased off-state voltage for high-volt transistors
e) Consequent to a)...c): increased current density (shrinking)
f) Provided that e) is complied with, increase of current per chip or decrease of chip surface and
costs
g) Optimized low saturation and high speed-IGBTs
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1 Basics
h) Integration of monitoring, protection and driver functions or power electronic circuits

(monolithic, chip-on-chip or silicon-on-insulator)
Especially during the past years a rapid development progress is to be noted concerning mainly
the optimization of the horizontal and vertical cell design, the refinement of the cell structure and
the successful handling of ultra-thin silicon wafers.
With mastery of the thin-wafer technology (wafer thickness 100m), for example, the production
of extremenly low-loss 600V-IGBTs in NPT-technology had been possible [164].
For the time being, the principal improvement potential for MOSFETs and IGBTs lies in
optimizing the cell design.
Firstly, there are new superfine structures, such as the S-FET product range by SIEMENS,
thanks to the latest self-adjusting processes realizing an on-state resistance that is a fifth of that
of conventional MOSFETs and a clearly improved switching and avalanche stability [216].
These structures, which are applied in similar forms also in modern high-density IGBTs, contain
double-implantation gates with spacers in the margin region (Figure 1.14).
Spacer
AISi
Source
TEOS
Polysilicon
Body C p+ n+ p
Drain n-
Figure 1.14 Double-implantation gate structure (Siemens S-FET) [298]
A lately developed gate structure for MOSFETs and IGBTs which will replace the conventional
gate structure is the trench-gate, which allows for a vertical passage of the channel in the p-well
(Figure 1.15). Since this structure provides for more active silicon surface, control of the channel
cross-section becomes easier and a smaller channel resistance may be realized. The on-state
losses can be reduced by about 30 %.
Furthermore, the cell surface can again be reduced, allowing higher current density, reduced on-
state losses, improved latch-up stability, reduced switching losses and a higher breakdown
voltage compared to planar MOSFETs and IGBTs.
The disadvantages, however, are a decreased short-circuit stability and an approximately three
times higher gate capacitance compared to that of planar elements.
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1 Basics
n Structure of Field Stop IGBT

emitter gate emitter
n-emitter
p p
gate oxide
n-
field stop
layer
n
p-emitter
collector
Figure 1.15 IGBT-cell with trench-gate and field stop layer
Also the so-called IEGTs (Injection Enhaced Gated Transistors) for extremely high voltage
applications (4.5...6.5 kV) have been designed in trench technology; due to the cathode emitter
structure, the leak-off process of the holes is impeded, causing a charge carrier density similar to
that of thyristors during on-state [194].
A remarkable progress within the high-volt power MOSFET has been made with the CoolMOS
introduced by SIEMENS in 1998 [216]. As shown in Figure 1.16, the MOSFET-cell structure of
the CoolMOS has been equipped with p-conducting areas in the drift zone which are connected
to the p-wells.
Source Gate Source Source Gate Source
Al Al
SiO2 SiO2
n n n n
p+ p+ p+ p+
p p
p p
p p
n- n- n- n-
n+ n+ n+ n+
Drain Drain
a) b)
Figure 1.16 MOS- cell structures

a) Conventional structure
b) CoolMOS-structure (principle)
Since, during forward off-state, the electrical field is not only handled in vertical, but also in
horizontal direction, the n--drift area may be drastically reduced in size compared to
conventional MOSFETs, by increasing its conductivity at the same time.
The turn-on resistance RDS(on) will then not increase in the exponential way described under
chapter 1.2.1 anymore (exponent 2.4...2.6), but only linearly to the breakdown voltage V(BR)DS.
37
1 Basics
By this, the forward on-state losses of a 600V-CoolMOS, for example, will be reduced by the
factor 5 in contrast to a conventional MOSFET with the same chip surface. Only 1/3 of the
previous chip surface is required to manage the same current. Switching losses will be halved
and on-state losses will be reduced to about 35 %; due to the reduced chip surface, also gate
capacitance and gate charge will decrease to about a third of the previous value [216].
However, the bad dynamic behaviour of the inverse diodes inside the CoolMOS-structure is
disadvantageous. This restricts the application in hard switching topologies with inductive
commutation.
Further progress will be achieved with the use of other semiconductor materials, such as silicon
carbide (SiC).
Compared to Si, SiC shows an almost 10 times higher breakdown field intensity.
In spite of restricted mobility of the electrons, on-state resistances reduced by the factor 1/300
are realizeable in unipolar components, which guarantees for a high-voltage application range far
beyond 1000V. As for bipolar SiC-components, the smaller drift area results in a scaled down
storage charge. On the one hand, the energy gap, which is three times as big as that of Si, allows
operating temperatures up to 500C; on the other hand the threshold voltage of bipolar
components is increased to 2.5V.
Other unfavourable effects lie in the considerably higher junction capacitances compared to Si-
components and in todays still tremendous technological problems: diffusion of impurity
centers is almost impossible, non-defective big surfaces are currently not realizeable and todays
fundamental technologies for the margin design are not applicable to SiC. [282], [124], [130].
The integration of monitoring, protection and driver functions or power electronic circuits
(monolithic, chip-on-chip or silicon-on-insulator) to the chip is more and more gaining
importance in low-voltage (e.g. car electronics) or low-current (e.g. consumer products) batch
applications.
For example, driver-, protection-, system- and diagnostic functions have been integrated on one
chip in the intelligent SMARTPOWER-transistors, leading to a reduction of power losses and
to an improvement of the system reliability apart from the advantages of system miniaturization
[277], [213], [232].
The simplest method is to generate e.g. protection- and sensor units to manage currents, voltages
or temperatures on control supply potential by diffusion to the MOSFET- or IGBT-chip surface.
Popular designs to be mentioned are the SENSFET and the Sense-IGBT, where source- or emitter
current, respectively, are separated into a main circuit conducting the main current share and a
parallelled measuring circuit. By inverse feedback of the measuring signal to the control circuit,
the measuring current is reduced by increase of the sense-resistance [194]. Sense-IGBTs are
integrated in many IPMs.
The TEMPFET is equipped with an integrated temperature sensor, which is used as overcurrent
indicator at the same time and which will short-circuit the gate-source-connection, in case a
certain temperature limit has been exceeded.
PROFETs and HITFETs, for example, contain a complete driver circuit with overcurrent-/short-
circuit-protection, overvoltage- and overtemperature-protection, gate-protection, load indicator,
polarity protection, over- and undervoltage turn-off and a charge pump for generation of the gate
voltage, e.g. [4], [277].
The PROFET is being produced as single- and multi-channel high-side switch up to a break-over
voltage of 60V.
In contrast to the high-side switch, there is not sufficient supply voltage generated for the
protection logic during on-state of a MOSFET for a low-side switch. Therefore, an integrated
38
1 Basics
temperature sensor in the HITFET will reduce the gate voltage at a high chip temperature that the
drain voltage is able to increase to the minimum supply voltage-value of 3V and the protection
circuit may react.
With reference to [232], monolithic integration of whole inverters with power semiconductors,
high-voltage ICs for driver/ protection and micro-electronic system control circuits is limited to
1A/ 600V (soon up to approx. 2A) and 5A/75V for the time being, the disadvantages compared
to hybrid system integration of chips (currently up to 30A/ 1200V and up to 150A towards the
year 2002) being the limitation of the blocking voltage to 600 V, restricted ruggedness reffering
to short-circuit- and pulse-currents and tripled losses in the used lateral transistors in contrast to
vertical transistors.
1.3 Free-wheeling- and snubber-diodes
1.3.1 Demands to free-wheeling and snubber-diodes

Modern fast switching devices require fast diodes as free-wheeling diodes. With every turn-on of
the switch, the free-wheeling diode is commutated from conductive to blocking state. At this
process, it has to show soft-recovery behaviour. For a long time, the importance of fast diodes
had been underestimated. The performance of the switch had been impaired by the free-wheeling
diodes. During the past few years, however, free-wheeling diodes had regained importance, and
significant progress could be made by improving the reverse-recovery behaviour.
1.3.1.1 Reverse voltage and forward voltage drop

The reverse voltage VR indicates that, at a specified voltage, the leakage current must not exceed
the limit current IR.
The specifications in the databooks are indicated for an operating temperature of 25C. In the
case of lower temperatures, the blocking capability will decrease, e.g. by approximately 1.5 V/K
for a 1200V-diode. For components which are operated at temperatures below the ambient
temperature, this has to be considered in the circuit layout.
I
IF
VR
VF
V
IR
Figure 1.17 Definition of reverse and forward voltage of a diode
At temperatures above the ambient temperature the reverse voltage will increase accordingly,
however affecting an simultaneous increase of the leakage current. Therefore, a leakage current
39
1 Basics
value is specified also for high temperatures (125C or 150C). In case of gold-diffused devices
the leakage current can rise very steeply, which might cause thermal instability in circuits, where
the whole system is operated at high temperatures due to the losses of the switching devices.
VFRM
1,1 VF
VF
0,1 VF
tfr
t
Figure 1.18 Turn-on behaviour of power diodes
The continuous forward voltage VF indicates that, at a specified current, the forward voltage
drop over the diode must not exceed the specified limit value. Typically, these limit values are
specified at ambient temperature. A decisive factor in the power loss balance, however, is the
forward voltage at higher temperatures. All datasheets of free-wheeling diodes should contain a
note of this temperature dependency.
1.3.1.2 Turn-on behaviour

When the diode passes over to conductive state, the voltage will at first increase to the repetitive
peak forward voltage VFRM, before it drops to forward voltage level again. Figure 1.18 shows the
currently valid definition of VFRM and the turn-on time tfr.
This definition, however, does not give much information on the behaviour of free-wheeling and
snubber-diodes for IGBTs, because
- the rise of the on-state current di/dt is so high that e.g. VFRM may increase to 200V or even
300V for an unsuitable 1700V-diode, which is more than 100 times VF,
- the diode is normally turned on f run the blocking state, generating a considerably higher
VFRM than if it is turned on from its neutral state.
A low VFRM-value is one of the most important requirements to snubber-diodes, since the
snubber-circuit becomes effective only after turn-on of the diode.
The repetitive peak forward voltage is also of importance for free-wheeling diodes, which are
designed for a reverse voltage of > 1200V. When the IGBT is turned off, a peak voltage is
generated over the parasitic inductances, which is still superimposed by VFRM of the free-
wheeling diode. The sum of both components may lead to critical voltage peaks.
However, this measurement is not trivial, since the inductive component and VFRM cannot be told
apart in the application conform chopper circuit. Measurements may only be made with the open
construction directly at the bonding wires of the diode.
40
1 Basics
On the other hand, turn-on behaviour of a diode is not important for the power loss balance,
since turn-on losses only amount to a small percentage of the losses during turn-off and forward
on-state and may therefore be neglected.
1.3.1.3 Reverse recovery behaviour

When passing over from the conductive to the blocking state, the internal diode storage charge
has to be discharged. This results in a current flowing in reverse direction in the diode. The
waveform of this current is characterized as the reverse-recovery behaviour.
Figure 1.19 shows the simplest circuit for the characterisation.
LK
IL
VK
Figure 1.19 Reverse-recovery test circuit
S depicts an ideal switch, IL is the current source, VK a voltage source and LK stands for the
commutation circuit inductance.
After closing switch S, a soft-recovery diode will show a current and voltage characteristic as
shown in Figure 1.20. Figure 1.20 is an example for a soft-recovery behaviour of a diode.
Figure 1.21 shows two examples for diode current characteristics with snappy switching
behaviour. Firstly, the definitions are explained by referring to Figure 1.20.
41
1 Basics
t0
I
V,I
trr
tirm
ts tf
tw
0
0,2 IRRM
dI/dt
dI r/dt
IRRM
V
VM
t
Figure 1.20 Current and voltage characteristic of the reverse recovery process of a soft-recovery diode in a circuit
as shown in Figure 1.19 and definition of the characteristics of the recovery behaviour
The commutation velocity dI/dt is determined by voltage and inductance:

dI VK
= (1.1)
dt L K
At t0 current is at zero passage. At tw the diode starts to block. At this instant, the pn-junction in
the diode gets free of charge carriers. At tirm the reverse current is at its maximum IRRM.
After tirm the current will fall to leakage current level, the current characteristic depends solely on
the diode. If the current drops very steeply, this is called snappy recovery behaviour. If the
current drops very softly, this is called soft recovery behaviour.
The reverse recovery time trr is defined as the time between t0 and the time, where the current has
dropped to 20 % of IRRM. The subdivision of trr into tf and ts shown in Figure 1.20 defines as
quantitative value for the recovery behaviour:
tf
Soft factor s = (1.2)
ts
This definition is insufficient, because, as a consequence, the current characteristic as in Figure
1.21a would be snappy. The characteristic in Figure 1.21b, however, would be classified as soft
even though tf > ts holds, there is a hard snapp-off.
42
1 Basics
ts tf ts tf
0,2 IRRM 0,2 IRRM
a) b)
Figure 1.21 Current characteristic for two different possibilities of snappy reverse recovery behaviour
Better is the definition:
dI
I=0
Soft-factor S= dt (1.3)
dI r
max
dt
Measurements have to be taken at a current flow of less than 10 % and of 200 % of the specified
current. By this also the charactertistic in Figure 1.21b will be defined as snappy.
Moreover, this considers that small currents are extremely critical for the reverse-recovery
behaviour.
The occurring overvoltage is determined by dIr/dt according to the inductance law
dI
Vind = L K r (1.4)
dt max
Therefore, overvoltage occurring under certain measuring conditions or the peak voltage
VM = VK + Vind may also be seen as characteristics for the recovery behaviour. VK and dI/dt have
to be figured in this context.
But also this definition is not sufficient, because it still neglects the following parameters:
1. Temperature. Mostly, high temperatures have a negative influence on the recovery
behaviour. But for certain fast diodes, the recovery behaviour will get worse at ambient
temperature or at lower temperatures.
2. Applied voltage. Higher voltages will lead to impaired reverse recovery
3. Rate of rise of commutation current dI/dt. The dependency on dI/dt is very different for
diodes of various manufacturers. Some types of diodes react more softly with increase of
dI/dt, other types behave more snappy.
All these different influences may not be summarized in one simple definition of quantity.
Therefore, the circuit in Figure 1.19 and the definitions according to (1.2) or (1.3.) are only
usefull to explain the effects of the single production parameters of diode behaviour. An overall
estimation of reverse recovery behaviour can only be made under application-related conditions.
An application-related measuring circuit is shown in Figure 1.22.
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1 Basics
L1
+
RGon
IL
Driver RGoff
VK L2
LL
V
L3
Sensor I
-
Figure 1.22 Application-related chopper circuit of a step-down converter (double-pulse operation) for reverse
recovery measurements
The commutation velocity dI/dt is adjusted by the gate resistor RGon of the switching device. VK
is the DC-link voltage. A parasitic inductance L1 is generated in the connections between
capacitors, IGBT and diode. Figure 1.23 shows the IGBT control signals and the current flow
within IGBT and diode under double-pulse operation. By turn-off of the IGBT, the load current
will be taken over by the free-wheeling diode. As soon as the IGBT is turned on next time, the
diode will be commutated, characterizing its recovery behaviour at that moment. During turn-on,
the IGBT also takes over the reverse current of the free-wheeling diode. This procedure is
depicted for a soft-recovery diode in Figure 1.24 at a higher resolution of the time axis. Figure
1.24a shows an IGBT current and voltage characteristic and also the turn-on power losses.
Figure 1.24b shows the FWD-current and voltage characteristic as well as power losses.
V(t)
Driver
t
I(t)
IGBT
I(t) t
FWD
t
Reverse-Recovery-Current
Figure 1.23 Driver control signal, IGBT- and FWD-current waveforms in a circuit according to Fig. 1.22 (double-
pulse operation)
44
1 Basics
While the IGBT conducts the peak reverse current IRRM, the IGBT-voltage is still on DC-link
voltage level (1200V in Figure 1.24a). This is the moment of maximum turn-on losses in the
IGBT.
The diode reverse recovery characteristic may be divided up into two phases:
1. The phase of increase up to the reverse peak current and the consequent reverse drop current
with dIr/dt. dIr/dt is within the range of dI/dt as far as a soft-recovery diode is concerned. The
peak reverse recovery current IRRM exerts most stress on the switching device.
V IGBT turn-on
1200V
IRRM Diode
150A
I
P=V*I
Eon P:10 5 W/div
Won
0 0
SKM 200 GB 173 D T = 125C
a)
200ns/div
0
Diode turn-off
150A
I V
-1200V
IRRM tail current
P:10 5 W/div
Eoff
SKM 200 GB 173 D P=V*I T = 125C
0
200ns/div b)
Figure 1.24 Current, voltage and power losses during IGBT turn-on (a) and diode turn-off (b) for a measurement in a
test circuit according to Figure 1.22
2. The tail phase, where the reverse current slowly declines to zero. There is no point in
defining a trr. The main power losses in the diode are due to the tail phase, where voltage has
already been applied to the diode. A snappy diode without tail current would cause less
45
1 Basics
switching losses, but would be unsuitable for the application. In the IGBT, the switching
losses during the tail phase are not that extreme, because the applied voltage has already
decreased at that time.
Compared to IGBT switching losses, the losses the diode are low in the application (diode
switching losses in Fig. 1.24b are drawn to the same scale as the IGBT switching losses in Fig.
1.24b). In order to keep power losses of both, IGBT and diode, as low as possible, it is important
to care for a small peak reverse current and to have the main part of the storage charge
discharged during the tail phase. A limit to this is set by the maximum switching losses that can
be dissipated in the diode.
The peak reverse recovery current IRRM is the most important parameter for the diode taking
influence on the total losses. Therefor it should be minimized.
In a typical application, where the chopper is in a semiconductor module, the parasitic
inductance Lges is in the range of 40nH, reducing the generated overvoltage. Due to lack of ideal
switches, the voltage applied to the IGBT will drop to a certain degree during the recovery
phase. The voltage taken becomes
dI R
V(t) = VK L ges + VCE (t) (1.5)
dt
with VCE(t) being the voltage still applied to the IGBT at the respective time. It is typical of soft-
recovery diodes that, for moderate rates of rise up to 1500A/s and minimized parasitic
inductances, V(t) is smaller than VK at any time and that there will be no voltage peaks.
1000
950 Platinum-diffused Diode Conditions:

VK = 800 V
dI/dt = 1200 A/s
900 Tj = 150C
[V]
max
850
800
CAL-Diode
750
700
1 10 100
Forward Current [A]
Figure 1.25 Peak voltage during commutation in dependence of forward on-state current as a parameter for the
switching behaviour of diodes
Figure 1.25 gives an example for characterization of the recovery behaviour by this method. In
these conditions, the overvoltage occurring in a CAL-diode has been compared to that occurring
in a diode, the charge carrier life of which had been adjusted by platinum-diffusion, showing
soft-recovery behaviour by reduced p-emitter efficiency. A platinum-diffused diode behaves as
soft as a CAL-diode at rated current (75A). Smaller currents, however, will cause overvoltages
up to a maximum of more than 100 V at 10 % of rated current due to snappy switching
behaviour. Even smaller currents are switched more slowly by the applied IGBT, affecting a
46
1 Basics
decrease of overvoltage. In contrast to that, there will be no substantial overvoltage on any of

those conditions with CAL-diodes.
All further explanations in this manual are based on the following definition:
A diode shows soft-recovery behaviour, if, in all conditions relevant to the application in an
application-related circuit, no overvoltage occurs, caused by reverse current snap-off due to the
diode.
Relevant conditions being the total current range, all commutation velocities useful for the
application and the temperature range of -50C up to +150C. This definition is valid as long as
dI/dt is not too high (> 6 kA/s) or high parasitic inductances (> 50 nH) are applied, which might
lead to circuit-dependent voltage peaks also with soft-recovery diodes.
An equally important requirement for free-wheeling diodes with a voltage from 100V upwards
(apart from soft switching behaviour) is dynamic ruggedness. Figure 1.24b shows that nearly
the whole DC-link voltage is taken up by the diode, while it is still conducting a substantial tail
current. If the IGBT is switched very steeply (small gate resistance RG), reverse current and tail
current will rise, at the same time causing a decrease of VCE at the IGBT, which switches over to
the diode with a respectively higher dV/dt. The density of the current-carrying charge carriers
(holes) will then be above the original doping density, the consequence of which will be an
inevitable avalanche breakdown in the semiconductor at applied voltages far below reverse
voltage level (dynamic avalanche). To manage these operating conditions is characteristic of the
dynamic ruggedness of a free-wheeling diode. The dynamic ruggedness may be defined as
follows:
The dynamic ruggedness is the ability of a diode to manage high rates of rise of commutating
di/dt and a high DC-link voltage at the same time.
If the diode shows no sufficient dynamic ruggedness, manufactures limit the dI/dt of the IGBT or
admit only a maximum reverse recovery peak current of the diode thus accepting increased
switching losses.
1.3.1.4 Demands on free-wheeling diodes used in the rectifier and inverter mode of voltage
source converters
Free-wheeling diodes in IGBT- or MOSFET-converters have to cope with different requirements
depending on whether they are used in rectifiers or inverters with the same power regarding the
power losses occurring.
Typically, the average energy flow in inverter mode is directed from the DC-link to the AC-side,
i.e. a consumer is connected to and supplied by the AC-side (e.g. three-phase motor).
On the other hand, the average energy flow in rectifier mode is directed from the AC-side to the
DC-link. In this case the converter works as a pulse rectifier connected to an AC-mains or
generator.
Although the power performance in both cases is the same, the power semiconductors are subject
to different power losses basically due to the opposite phase shift between voltage and current on
the AC-side, when in rectifier or inverter operation.
This can be explained using to the basic circuit in Figure 1.26.
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1 Basics
iIGBT1 iDiode1
Vd/2 Diode D1
IGBT T1
Vout iL
IGBT T2 Diode D2
Vd/2
iIGBT2 iDiode2
V, i Vout(1)
Vd/2
Vout
iL
-Vd/2
Figure 1.26 Basic circuit of a converter phase with IGBTs and free-wheeling diodes
It shows:
- if vout = positive and iL > 0: current flow over IGBT 1,
- if vout = negative and iL > 0: current flow over diode 2,
- if vout = positive and iL < 0: current flow over diode 1,

- if vout = negative and iL < 0: current flow over IGBT 2.
Consequently, the IGBT- and FWD- on-state power losses occurring at a given RMS-current
value are dependent on the cos phi between voltage and current fundamental frequency as well
as on the modulation factor m of the converter (determines duty cycles).
In the case of inverter-operation 0 m*cos phi 1. Power losses in semiconductors reach their
limits, if m*cos phi = 1. In this case maximum on-state losses and, therefore, total losses in the
IGBTs have been reached, whereas losses in the free-wheeling diodes are at their minimum.
In the case of rectifier operation 0 m*cos phi -1. Power losses in semiconductors reach their
limits, if m*cos phi = -1. In this case, minimum on-state losses and, therefore, total losses in the
IGBTs have been reached, whereas losses in the free-wheeling diodes are at their maximum.
Applied to the characteristics in Figure 1.26, this situation is given when the fundamental
48
1 Basics
frequency of the pulse rectifier converts pure active power from the line and the neutral point of
the line is connected to the centre point of the DC-link voltage.
This is illustrated with the graphs in Figure 1.27 with an example.
IGBT 1200 V / 50 A; Vd = 540 V; ILeff = 25 A; Tj = 125C

30
25
Forward Losses [W]
20
IGBT
15
10
Diode
5
0
-1 -0,8 -0,6 -0,4 -0,2 0 0,2 0,4 0,6 0,8 1
m*cos phi
25
Switching Losses [W]
20
IGBT
15
10
Diode
5
0
0 1 2 3 4 5 6 7 8 9 10
Switching Frequency (kHz)
Figure 1.27 Switching and forward on-state losses of IGBT and free-wheeling diode in a VSI
At given DC-link voltage and RMS-AC-current values the switching losses of the components
are merely dependent (linear) on the switching frequency (Figure 1.27).
A large number of the available IGBT and MOSFET modules with integrated free-wheeling
diodes are dimensioned for being applied in inverters regarding the power losses that may be
dissipated at rated current (e.g. cos phi = 0.6...1). Due to their reduced on-state and total losses,
diodes have been designed for a considerably lower dissipation of power losses compared to
IGBTs (ratio IGBT : diode 2..3:1).
Therefore, the use of power modules with higher rated current is recommended when
dimensioning pulse rectifiers with the same converter power as a corresponding pulse inverter.
Example:
Driving system:
* Power supply (400 V/50 Hz) pulse rectifier (fs = 10..12 kHz) DC-link pulse inverter
(fs = 10..12 kHz) three-phase motor (400 V/50 Hz/22 kW)
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1 Basics
* Pulse rectifier with standard IGBT-modules (phase leg) 1200 V/100 A (Tc = 80C)
* Pulse inverter with standard IGBT-modules (phase leg) 1200 V/75 A (Tc = 80C)
This difference is not required for power modules with higher rated diodes.
1.3.2 Structure of fast power diodes

We have to distinguish between two basic types: Schottky-diodes and pin-diodes.
In Schottky-diodes, the metal-semiconductor junction serves as blocking junction. There is no
diffusion voltage at the pn-junction as in pin-diodes; this guarantees a lower on-state voltage as
with any pin-diode, provided the n--zone is very thin. When passing over from conductive to
blocking state, ideally only the space charge zone has to be charged. Due to this, the component
is suitable for very high frequencies (> 100 kHz). This advantage is, however, restricted to
voltages < ~ 100 V. In this range, the Schottky-diode is the appropriate free-wheeling diode for a
MOS-transistor. If, on the other hand, the component is dimensioned for higher voltages,
- the on-state voltage will rise considerably, since wB increases and only one sort of charge
carriers is available (unipolar) and
- the leakage current will rise considerably, which will cause thermal instability.
p p
n-
n-
Schottky-
Barrier n- w
w B
n+
n+ n+
Schottky-Diode Epitaxial-Diode Diffused Diode
N ,N
A D
n+ p+ n+ p+ n+
n- n-
n-
w w w
Figure 1.28 Schottky-, pin-epitaxial - and pin-diffused diode structures

Top: structure
Bottom: doping profile (scheme)
The advantages of pin-diodes become effective in the range of more than 100V. In diodes
produced today, the middle zone is not i (intrinsic), but of n-type with a very low doping level
(n-) compared to the marginal zones. In pin-epitaxial-diodes (Figure 1.28, mid) a n--zone is
separated from the highly-doped n+-substrate (epitaxy). Then, the p-zone is diffused. By this
technology, a very small base width wB down to some m may be produced, the silicon wafer
being thick enough to manage high production yields. By diffusion of recombination centres
50
1 Basics
(mainly gold-diffusion) very fast diodes can nevertheless be produced with a low forward on-
state voltage due to the small wB. However, the on-state voltage will always be above the
diffusion voltage of the pn-junction of 0.6 to 0.8 V. The main applications of epitaxial (epi-)
diodes are within the range of 100 V and 600 V, some manufacturers are even producing epi-
diodes for 1200 V.
From 600 V upwards the n--zone will be enlarged to such an extent that a diffused pin-diode
(right Figure) may be produced. The p- and n+-zones are diffused into the n--wafer. Similar,
recombination centres are necessary to adjust the dynamical characteristic.
As the major applications of power modules are within the range above 100 V, pin-diodes will
be explained in more detail in the following.
1.3.3 Characteristics of fast power diodes

As for free-wheeling diodes, a compromise has to be found for optimizing the contrasting
requirements. Therefore, we have to come up against the physical limits of the material, which
makes the design of excellent free-wheeling diodes very sophisticated.
1.3.3.1 Forward and blocking behaviour

In forward direction, there is the pn-junction and the resistance of the adjacent n--zone. The
voltage drop is composed of
Vf = Vdiff + Vohm (1.6)
The pn-junction diffusion voltage Vdiff is dependent on the doping of both pn-junction sides and
is, typically, between 0.6...0.8V. For fast diodes with a blocking voltage of 600V and more, the
ohmic part prevails. Charge carrier lifetime of free-wheeling diodes has to be kept very low so
that the on-state voltage will depend exponentially on the base width wB and the charge carrier
lifetime [283]:
wB
3kT 2L A
VOhm = e (1.7)
8q
LA is the ambipolar diffusion length
n p kT
L A = D A , with the ambipolar diffusion constant D A = 2 .
n + p q
k: Boltzmann-constant; 1.38066 _ 10-23 J/K
q: electronic charge; 1.60218 _ 10-19 C
n and p stands for the mobility of the electrons and holes on condition of a n--zone flooded by
free electrons and holes [284]. Due to this exponential correlation, the smallest possible wB
should be selected.
In spite of this, the base width wB has a definite influence on the blocking voltage. Two different
cases may occur (see Figure 1.29):
If wB has been dimensioned in such a way that the space charge zone cannot protrude into the n+-
zone (triangular characteristic), this is called non-punch-through structure [285]. If wB has been
dimensioned in such a way that the space charge zone will protrude into the n+-zone, the
characteristic will be trapezoidal, which will be called punch-through-diode. However, a real
punch-through, where the space charge zone would reach the area of another doping type, is not
realized in this case. Nevertheless, the designation has generally been accepted.
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1 Basics
E0 E0
-E(w)
p -E(w) n+ p n+
E1
n- n- w*
0 wB 0 wB
w w
non-punch-through (NPT) -Diode punch-through (PT) -Diode
a) b)
Figure 1.29 Dimensioning of a diode for triangular (a) and trapezoidal (b) characteristic
For an ideal NPT-diode wB is dimensioned so that it is located at the end of the triangular
characteristic. If the doping is optimal, the minimum width for wB would then be
2 1 7
wB = 2 C V
3 6 6
R (1.8)
with C = 1.8*10-35 cm6V-7

Minimum doping necessary for PT-diodes can be calculated similarly. As a extreme, the
characteristic would be rectangular, E1 = E0 (see Figure 1.29). Consequently,
1 7
w B (PT, extreme) = C6 6
VBD (1.9)
Compared to wB of the NPT dimensioning (1.8):
2

w B (PT, extreme) = 2 3 w B (NPT) 0.63w B (NPT) (1.10)
This extreme case, however, may not be achieved, but with the existing technology it may be
approximated by
w B (PT) 0.66 w B (NPT) (1.11)
The difference between PT-structure according to (1.11) and NPT-structure according to (1.8)
adds up to about 0.8 V on-state voltage, considering the necessary low charge carrier lifetime.
Therefore, PT-structure should be preferred.
1.3.3.2 Turn-on behaviour

When the diode is turned on, it has to overcome the resistance of the low-doped base. Therefore,
the turn-on peak voltage will increase proportionally to wB. The turn-on peak voltage becomes
critical, especially if a significant base width wB has to be chosen due to a high blocking voltage
over 1200V. In this respect, PT-diodes will show optimized turn-on behaviour.
Free-wheeling diodes always contain recombination centres. For free-wheeling diodes
dimensioned for applications of 1200V and more, recombination centres that cause increase of
the base resistance have to be avoided. A like recombination centre would be one that had been
generated by gold-diffusion. Recombination centres generated by platinum-diffusion, electron
52
1 Basics
beam radiation or light ions will only slightly increase the turn-on overvoltage in comparison to
diodes without recombination centres.
1.3.3.3 Turn-off behaviour

The turn-off behaviour of fast diodes is determined by the way in which the charge declines to
zero. Figure 1.30 shows the procedure for a snappy diode, Figure 1.31 for a soft-recovery diode.
1E+20
N A, N D, p
Charge Carrier Hill n+

1E+18
t0
1E+16 Hole Current

Electron Current
p t2
t3
t4 t2
1E+14
n- t3
t5
100 200 w in m
Figure 1.30 Diffusion profile and decline of charge carriers (density of holes) in a snappy diode (ADIOS-simulation)
During on-state, the n--zone is flooded by > 1016 cm-3 electrons and holes, the concentration of
electrons n and holes p presumably being the same. After commutation the charge carrier hill is
within the n--zone between t2 and t4, provided n p. The decline of charge carriers towards the
cathode is effected by the flow of electrons, that move towards the anode by the flow of holes,
which flow as reverse current in the outer circuit. In case of the snappy diode in Figure 1.30 the
charge carrier hill declines to zero shortly after t4. Between t4 and t5 the diode will suddenly turn
from its state with charge carrier hill to a state without charge carrier hill, the reverse current
snaps off. The switching behaviour of the diode is snappy.
Figure 1.31 shows the same procedure for a soft-recovery diode. A charge carrier hill feeding the
reverse current is kept during the whole procedure. At t5 the diode has already taken on the
applied voltage. The procedure described in Figure 1.31 will lead to a tail current as shown in
Figure 1.24.
Whether soft-recovery behaviour is reached or not, depends on the successful reduction of
charge carriers. This is difficult to achieve by microstructures on the surface, a technology where
the semiconductor industry has made an enormous progress in the past. Therefore, it has taken a
relatively long period of time until the reverse recovery behaviour could be controlled.
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1 Basics
1E+20
NA, N D, p
1E+18 n+
Charge Carrier Hill
t0
1E+16
Hole Current t5
t6 Electron Current
p t2
t3
t4
1E+14
n-
t5 t6
100 200
w in m
Figure 1.31 Diffusion profile and decline of charge carriers (density of holes) in a soft-recovery diode (ADIOS-
simulation)
The following measures will effect a softer recovery behaviour:

1. The basis width wB of the n--zone is enlarged, NPT-dimensioning is applied (see equation
(1.9)), an additional zone is generated in the diode, which is not reached by the field at rated
voltage. But this will lead to extreme increase of the on-state voltage (see equation (1.7)) or
the VF/QRR-ratio. Nevertheless, this inconvenience is accepted even in lately developed
solutions (as mentioned e.g. in [286]).
2. In order to slightly neutralize the wB-increase, a two-phase n--zone may be applied [287]
showing a highly doped area near to the nn+-junction. In Figure 1.30 and 1.31 a similar effect
is realized by a flat gradient at the nn+-junction. This measure on its own will not be
sufficient in order to reach soft-recovery behaviour.
3. Inversion of the charge carrier distribution by a low-efficiency p-emitter (see chapter
1.3.4.1).
4. An axial charge carrier lifetime profile, providing for a low charge carrier life at the pn-
junction, and a longer charge carrier life at the nn+-junction (see chapter 1.3.4.2).
To guarantee for soft-recovery behaviour on any condition, usually several of those measures
have to be taken at the same time. Progress in this respect has always to be assessed on
consideration of the acceptance of a high on-state voltage drop or a higher QRR.
1.3.3.4 Dynamic ruggedness

While the space charge zone is increasing, a hole current, carrying IR, is flowing through the
empty area of the n--zone. Therefore, the density p of the holes is:
IR
p= (1.12)
qv d A
In this equation, vd stands for the drift velocity (7.57*106 cm/s) and A for the area of the diode.
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1 Basics
The hole density (shown in Figure 1.30 and 1.31 from t2 to t4 each) must no longer be neglected
with respect to the basic doping level [288]. P is added to the positively charged donators ND, the
effective doping Neff at that moment is
N eff = N D + p (1.13)
This will cause premature avalanche breakdown. Electrons and holes will be generated at the pn-
junction by dynamic avalanche. The holes will move through the highly doped p-zone. On the
other hand, the electrons will move through the n--zone, causing an effective doping
N eff = N D + p n av (1.14)
Here, nav stands for the density of the electrons generated by dynamic avalanche, which move
from the pn-junction through the space charge zone, partly compensating the hole density and
thus counteracting the avalanche effect. In [289] dynamic avalanche is designated as a self-
limiting effect: it is limited to a degree which is just sufficient to manage the field intensity
resulting from the reduced effective doping. Consequently, the diode is not likely to be destroyed
by dynamic avalanche.
Reduced forward current will cause reduced reverse current, and consequently reduced density
of holes p (according to (1.12)). But, since the switching devices have a higher dV/dt at smaller
currents, stress caused by dynamic avalanche may be higher, if small currents are applied.
For diodes dimensioned for higher blocking voltages, has to be increased due to the enlarged
wB. This will cause higher reverse currents, leading to increased hole density and to dynamic
avalanche according to (1.12). But dynamic ruggedness is especially important for the
application in this case.
1.3.4 Modern diodes with optimized recovery behaviour
1.3.4.1 Emitter conception

In the conventional pin-diode the pn-junction is flooded by more charge carriers than the nn+-
junction (Figure 1.30). The idea of the emitter conception is to invert the charge carrier
distribution: the nn+-junction is to be flooded by more charge carriers than the pn-junction. This
is achieved by reducing the injection quantity at the p-emitter.
p+ p+ p
Schottky-
Barrier
n- n-
n+ n+
a) b)
Figure 1.32 P-emitter for improvement of soft-recovery behaviour:

a) Emitter structures, e.g. the merged PiN/ Schottky diode
b) Reduced p-doping
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1 Basics
Various emitter structures had been considered, which, in summary, would meet this effect by
their functions. One example is the merged PiN/Schottky-diode, consisting of a sequence of
p+-zones and Schottky-areas [290] (Figure 1.32a). There is a number of structures similar to that,
comprising also structures with diffused p- and n-zones.
The advantages of Schottky or similar zones, however, are restricted to voltages below 600V. As
for blocking voltages of 1000 V and more, the ohmic potential drop will prevail. Only the
reduced injection area at the p-zone remains. The same effect as with emitter structures is
achieved by a continuous low-doped p-zone (Figure 1.32b). On balance the result of the
application of these structures is that they have not lived up to the set expectations.
Also the latest developments are aiming at the reduction of the emitter doping quantity and, thus,
the improvement of recovery behaviour. [132], [291]. Further progress can be made by reducing
the depth of penetration.
However, with a dI/dt-rate of more than 1000 A/s, some diodes with reduced p-doping do not
show sufficient dynamic ruggedness. Figure 1.33 shows a failure statistics considering more than
16 production lots with 25642 free-wheeling diodes altogether. The failure results in a hole
within the active area of the diode. This points to filamentation.
According to statistics, the number of failures caused by low-doped diodes and therefore higher
resistance in the p-zone (Figure 1.33, 160 /squ) was higher than that of diodes with re-
increased doping (Figure 1.33, 60 /squ), but those had shown impaired soft switching
behaviour. This demonstrates the contrast of both requirements to this technology: soft switching
behaviour on the one hand, and dynamic robustness on the other hand. Even accepting the
restriction of soft switching behaviour could not completely avoid failures. In order to guarantee
safe field application, all modules had to be subjected to a full load test in a chopper circuit under
field conditions.
3
2,47
2,5
1,5 1,31
0,38
0,5 0,33
0,23 0,19
0,15 0,18 0,19 0,12 0,16 0,19
0,04
0,04 0,00 0,00
0
Production Lot
160 Ohm/squ 60 Ohm/squ
Figure 1.33 Proportion of failures of diodes with reduced p-doping for several production lots (at very high dI/dt)
It seems possible that the failures in Figure 1.33 may be reduced by technological optimization.
However, it remains doubtful whether they can be completely avoided.
SEMIKRON has, at least, stopped any developments related to the emitter conception for free-
wheeling diodes in fast switches.
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1 Basics
1.3.4.2 Controlled Axial Lifetime (CAL) - conception

Recombination centre profiles similar to those shown in Figure 1.34a and 1.34b can be generated
by implantation of protons or He++-ions in silicon. Some time ago, this technology which
required accelerators performing up to 10 MeV, had been exclusively reserved for research
purposes, but the situation has changed. Basic research is interested more and more in the GeV-
range, and medium energy accelerators are available for other fields of application.
NA,N D NA,N D
N rek N rek
N rek
p+ n+ p+ n+
a n- b n-
Figure 1.34 Axial profile of recombination centres generated by light ion radiation
a) Narrow partial zone with higher concentration of recombination centres in the middle of the n--zone
b) Narrow zone with high concentration at pn-junction
The first assumption, that the best results could be achieved by implantation of a zone of highly
concentrated recombination centres in the middle of the n--zone as depicted in Figure 1.34a, had
proven wrong. The arrangement of such a zone at the pn-junction as in Figure 1.34b turned out
to be more favourable [292] [293].
Reference [147] explains that the relation between peak reverse current and forward on-state
voltage is improved with approximation of the recombination centre peak to the pn-junction.
If the recombination centre peaks are arranged directly at the pn-junction, the charge carrier
distribution will be inverted during on-state. The charge carrier distribution shown in Figure 1.31
results from a calculation based on the recombination centre profile according to Figure 1.35.
As for the CAL-diode, the recombination center peak (generated by He++-implantation) has been
arranged in the p-zone close to the pn-junction as in Figure 1.35, since this will lead to reduction
of leakage currents. He++-implantation has been combined with an adjustment of the basic charge
carrier lifetime, preferably achieved by electron beam radiation.
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1 Basics
Ba
1E+16
Recombination Centers
Peak
1E+15
[cm-3]
Basic-Recombination Center Density

rec
1E+14
- +
p n n
1E+13
0 50 100 150 200
x [m]
Figure 1.35 Recombination centre profile in the CAL-diode (scheme)
The characteristics of a CAL-diode in combination with an IGBT have already been referred to
in Figure 1.24. The reverse peak current can be decreased by the recombination centre peak
level, which is to be adjusted by the He++-implantation dose. The biggest share of the storage
charge of the CAL-diode occurs in the tail current, which, on the other hand, can be controlled
by the basic recombination centre density. Reduction of the basic charge carrier lifetime will
reduce tail current duration, however at increase of the on-state voltage of the diode. Recovery
behaviour can be greatly controlled by both parameters, basic charge carrier lifetime and He++-
implantation dose. So the diode will show soft-recovery behaviour under any operating
conditions, especially when low currents are applied.
CAL-diodes manufactured this way are proving a high dynamic ruggedness. CAL-diodes
dimensioned for 1200 V and 1700 V have been tested under lab conditions at dI/dts up to
15 kA/cms without destruction of the diode.
CAL-diodes are especially not likely to fail under the operating conditions shown in Figure 1.33.
This fact is based on the production of over 26 million CAL-diodes up to now.
A ruggedness test of a 3,3 kV CAL-diode is shown in Figure 1.36. In the measurements in

Figure 1.35 stress on the diode is still intensified by an additional parasitic inductance of 0.5 H,
generating a peak voltage of 1500 V directly subsequent to the commutation.
In contrast to other diodes, CAL-diodes may also be operated in this voltage range at a high dI/dt
(here 2000 A/cms).
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1 Basics
I [A] U[V]
3000
200 2500V
100A
2000
1000
-200
0
125C 1800A/S
500 1000 2000
Figure 1.36 Ruggedness test of a 3300 V-CAL-diode
The base width wB can be dimensioned comparatively narrowly for CAL-diodes, similar to the
PT-dimensioning indicated in equations 1.10 and 1.11. This provides for a comparatively low
on-state voltage or a better compromise between switching behaviour and on-state voltage,
respectively. The base width is also of special importance to the turn-on behaviour of the diode.
The forward recovery voltage VFR increases proportionally to wB; components designed for
1700V and more are likely to generate some 100 V VFR in the free-wheeling diode due to high
dI/dt during turn-off of the IGBT. In contrast to conventional diodes, VFR can be reduced by
more than 50 % in 1700 V-CAL-diodes. [106].
Recently developed free-wheeling diodes for IGCTs as well as snubber-diodes [294] are being
produced according to the CAL-conception, because
1. dynamic robustness is one of the most important demands,

2. dimensioning similar to PT-dimensioning results in an improved cosmic ray stability,
3. a favourable trade-off between on-state voltage and switching characteristics of the diode
may be adjusted by the measure mentioned above,
4. minimum VFR can be achieved in snubber-diodes,
5. a low leakage current can be realized compared to the conventional gold-diffusion process.
1.3.4.3 The concept of hybrid diodes

The concept of the hybrid diode was invented in 1991 [295], [296]. This conception is based on
the idea that a soft-recovery diode is connected in parallel to a PT-diode with a low on-state
voltage, but a snappy recovery behaviour, as shown in Figure 1.37.
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1 Basics
Anode
IS IE
p
wS - p
n -
n wE
+ +
n n
soft-recovery Diode punch through Diode
DS DE
Cathode
Figure 1.37 Structure of a hybrid diode
The function principle is shown in Figure 1.38. The main part of the on-state current is
conducted by the snappy diode DE. The rest is conducted by diode DS. Current IS is conducted
through diode DS and is the first to drop to zero passage, reaching its reverse current peak at t1.
At this time, diode DE is still carrying forward current. At t1 the pn-junction of diode DS is free of
charge carriers. Now, diode DE is commutated with increased dI/dt. The total current is still
determined by the outer circuit.
I snap-off- Diode
DE
t4
t
soft-recovery-
Diode DS
t1
t2
t3
Figure 1.38 Current flow in the components of a hybrid diode
At t2 the pn-junction of DE is free of charge carriers. Between t2 and t3 the reverse current in DE
will snap off. It will then rise accordingly in diode DS, which is not completely free of charge at
that moment. The total current does not show a reverse current snap-off. Consequently, there will
be no induced overvoltage. The charge carrier density in diode DS is reduced between t3 and t4.
The combination behaves soft.
To achieve efficient function of the hybrid diode, DS has to supply sufficient charge even after
the reverse current snap-off of DE. To manage this, the soft diode DS has to take on between
10 % and 25 % of the forward current. Therefore, the forward voltages have to be attuned.
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1 Basics
The first modules that contained hybrid diodes were introduced to the market the beginning of
1996. They have been applied preferably as free-wheeling diodes in chopper circuits with 100V-
or 200V-MOSFET switches. Here, an epitaxial diode designed for 400V is used as snappy diode
DE. The part of the soft-recovery diode DS is taken over by a modified CAL-diode. The basic
recombination centre density in it is kept on low-level, which results in a forward voltage of
about 1.1 V at 150 A/cm.
V V
on
on 0
100 200 300 400 [ns] 100 200 300 400 [ns]
Figure 1.39 Voltage characteristic in a 350 A, 100 V chopper module,

on the left: with epitaxial diodes, on the right: with a hybrid diode
Figure 1.39 shows the voltage taken at turn-on of the MOSFET in a 350 A/100 V chopper
module.
The diagram to the left shows the voltage characteristic for the free-wheeling diode being
realized by parallelling of 7 epitaxial diodes.
The diagram to the right shows the voltage characteristic, if one of the 7 epitaxial diodes has
been replaced by the soft-recovery diode DS. The induced peak voltage will decrease from 100 V
to 33 V, the interfering oscillations will disappear. By application of a like free-wheeling diode,
the MOSFET can be turned on with a high dI/dt. If the turn-on time of the MOSFET is reduced
from 1.3 s to 0.3 s by decreasing the gate resistance, the voltage characteristic will still be
acceptable. Total losses of the circuit will drop to 48 % (= sum of line- and switching losses of
all components).
Hybrid diodes are of special advantage in a voltage range of 600 V. In this range, diodes with a
minimum wB may be applied, if they are integrated as part of a hybrid diode. On the other hand,
hybrid diodes will not offer decisive advantages to high-voltage applications, since differences in
wB between soft-recovery CAL-diodes and PT-diodes are not that serious.
1.3.5 Series and parallel connection of fast power diodes
1.3.5.1 Series connection

In series connections, attention must be paid to the symmetry of circuits with respect to static
reverse voltage and with respect to the dynamic reverse voltage.
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1 Basics
C R
C R
Figure 1.40 RC-circuit for series connection of fast diodes
With reference to the static reverse voltage, the variation of leakage current due to production
processes will drive the components with the lowest leakage current to avalanche mode. As long
as the avalanche stability of the components can be relied on, no resistors will have to be
connected. If, however, components with a blocking capability of > 1200 V are connected in
series, it is common practice to parallel a resistor.
This parallel resistor has to be dimensioned with respect to the fact that voltage distribution is
always determined by its resistance.
If the leakage current is supposed to be independent of the voltage and if resistance tolerances
are neglected, the simplified rule for dimensioning the resistance for series connection of n
diodes of a specified reverse voltage Vr will be [297] :
nVr Vm
R< (1.15)
(n 1) I r
Vm stands for the maximum series voltage and Ir for the maximum spread of leakage current in
the diode, based on the maximum operating temperature. According to [297] it may be supposed
with high confidence that
Ir = 0.85 Irm, (1.16)
with Irm being specified by the manufacturer. According to this estimation, the current conducted
through the resistor is approximately 6-times the leakage current in the diode.
Considering existing experiences, it will be sufficient for modern free-wheeling diodes to
dimension the resistor in such a way that it will carry a current three times as high as the
maximum leakage current of the diode. However, even then considerable power losses are
generated within the resistor.
Dynamic voltage distribution may differ basically from static voltage distribution. If the pn-
junction in one diode is free of charge carriers earlier than in another one, this diode will also
take on voltage earlier.
If capacitor tolerances are neglected, a simple dimensioning rule can be used for this capacitor
paralleled to a series connection of n diodes of a specified reverse voltage Vr:
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1 Basics
(n 1) Q RR
C> (1.17)
n Vr Vm
QRR stands for the maximum variation of storage charge of the diodes. In all probability, it can
be supposed that
QRR = 0.3QRR (1.18)
if all diodes used are taken from the same production lot. QRR is specified by the semiconductor
manufacturer. The charge stored in this capacitance is maintained in addition to the storage
charge generated when the free-wheeling diode is turned off and has also to be taken up by the
IGBT during turn-on. Based on these dimensioning rules, the occuring charge will be up to twice
the storage charge of a single diode.
Free-wheeling diodes are usually not connected in series, due to the following additional sources
of power dissipation:
- n-fold diffusion voltage of the pn-junction,
- power losses in the parallel resistor,
- increased storage charge to be taken up by the IGBT,
- more components necessary for the RC-circuit.
This holds, if a freewheeling diode for the required voltage range is available.
Series connection may however be made exceptionally, if the on-state power losses are not of
considerable importance and if the application is dependent on short switching times and low
storage charge, which is typical for low-voltage diodes.
1.3.5.2 Connection in parallel

Connection in parallel does not require any additional RC-circuit. It is important for parallel
connection that the variation of the on-state voltage is kept as low as possible.
A decisive parameter to assess the parallelling capability is the temperature dependency of the
on-state voltage. If the on-state voltage drops due to increasing temperature, the temperature
dependency of the on-state voltage will be negative, the only advantage of which can be noticed
in the power loss balance.
If the on-state voltage rises due to increasing temperature, the temperature dependency will be
positive.
V[V] V[V]
Figure 1.41 Temperature dependency of the forward on-state voltage for different types of diodes
Left side: extremely negative temperature dependency
Right side: positive temperature dependency above rated current (75 A)
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1 Basics
A positive temperature dependency is of advantage for the application-specific parallelling, since

a heated diode carries less current and the system stabilizes. An extremely negative temperature
coefficient (> 2 mV/K) involves the risk of thermal instability for parallel connection of diodes,
which always show spreading of the forward on-state voltage due to production processes.
Parallelled diodes are thermally coupled
- via the substrate in case of parallelling within the module,
- normally via the heatsink in case of parallelling of modules.
Principally, at a slightly negative temperature coefficient, this coupling effect will be sufficient
to avoid thermal runaway of the diode with minimum on-state voltage. For diodes with a
negative temperature coefficient of > 2 mV/K we recommend selecting a lower total rating than
the current of the single diodes would add up to (derating).
1.4 Power modules: special features of multi-chip structures
1.4.1 Structure of power modules

In a power module several power semiconductors (MOSFET or IGBT chips and diode chips)
which are electrically isolated from the mounting surface (heatsink) are integrated into a case on
a common base plate.
The chips are soldered (or glued) to the metallized surface of an isolation substrate, which
electrically isolates the chips from the module base plate, and at the same time creates good
thermal conductivity.
The chip top sides are connected to the structured areas of the metallized surface by thin Al-bond
wires.
In addition to that, passive elements such as gate resistors, shunts/ current sensors or temperature
sensors (e.g. PTC-resistors) may be integrated into the module (hybrid) and also partly into the
transistor chips (monolithic).
Moreover, intelligent power modules contain additional protection and driver circuits, see
chapter 1.6.
The currently used isolation substrates for power modules are listed in the table below:
Isolation material
ceramic: aluminum oxide Al2O3 organic: epoxy
aluminum nitride AlN polyimide (Kapton)
(beryllia oxide BeO)
(silicon carbide Si3N4)
Substrates
Metal sheets: (Direct Copper Bonding) Metal sheets: IMS (Insulated Metal
Substrate)
AMB (Active Metal Brazing) Multilayer-IMS
Thick film layers: TFC (Thick Film Copper)
DCB (Direct Copper Bonding)

Figure 1.42 shows the structure of a power module with IGBTs and free-wheeling diodes in the
most common current technology with substrates made of DCB-ceramics with Al2O3 or AlN
isolation, combining good thermal conductivity and high isolation voltage.
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1 Basics
Diode-Chip
IGBT-Chip
Solder
DBC Substrate
Solder
Cu-Baseplate
C1 E1 G1 E2 C2,E1
E2 G2
C1 C2
3 2 1 G2 E2
E2 E1
G1 E1
Figure 1.42 Structure of an IGBT module SKM100GB123D in a SEMITRANS 2 case
For production of a DCB-substrate, copper surfaces with a thickness of e.g. 300 m are applied
to the top and bottom areas of the isolation material (thickness 0.38...0.63 mm) by means of
eutectic melting over 1000C. After the necessary track structure for the module circuitry has
been etched into the top side copper surface, the chips are soldered on, and the connection to the
contacts on the chip top side is effected by bonding. The bottom side of the DCB-ceramic
substrate is fixed to the module base plate (thickness e.g. 3 mm) mainly by soldering, see Figure
1.42.
Other module types (e.g. SEMITOP, SKiiPPACK, MiniSKiiP) do not necessarily require a base
plate and the previous soldering procedure may be avoided. In these modules, the DCB-substrate
is pressed on to the heatsink by means of suitable case constructions (see chapter 1.5).
Advantages of the DCB-technology compared to other structures are mainly the high current
conductivity due to the copper thickness, good cooling features due to the ceramic material, the
high adhesive strength of copper to the ceramic (reliability) and the optimal thermal conductivity
of the ceramic material [52].
AMB (Active Metal Brazing)

The AMB process (brazing of metal foil to substrate) has been developed on the basis of DCB
technology. The advantages of AMB-substrates with AlN-ceramic materials compared to
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1 Basics
substrates with Al2O3-ceramic materials are e.g. lower thermal resistance, lower coefficient of
expansion and improved partial discharge capability.
Figure 1.43 explains the differences between DCB and AMB.
eutectic copper
DCB AMB solder
copper/ silver/
copper copper/
oxide titanium
ceramic
aluminium oxide
Figure 1.43 Direct Copper Bonding (DCB) and Active Metal Brazing (AMB)
IMS (Insulated Metal Substrate)

IMS is mainly applied in the low cost/ low power range and is characterized by direct connection
of the isolation material to the module base plate. For insulation, polymers (such as epoxies,
polyamides) are usually applied to an aluminum base plate. The upper copper layer is produced
in foil form and glued on the isolation substrate (similar to PCB production) and is structured by
etching (Figure 1.44).
Chip (Si ; 280 m)

Solder (SnAg ; 80 m)
Copper (Cu ; 100 m)
Isolation (Polyimid ; 125 m)
Baseplate (Al ; 3 mm)
Figure 1.44 Basic structure of an IMS power module [194]
Advantages of IMS are low costs, filigree structure of tracks (possible integration of driver and
protection facilities), high mechanical robustness of substrate and relatively wide substrate areas,
compared to DCB.
The very thin isolation layer, however, leads to comparably high coupling capacitances against
the mounting surface (see chapter 1.4.2.6). Furthermore, the thin upper copper layer only
provides a comparably low spread of heat, which is improved by additional metallized heat
spreading layers under the chips or by adding Al-particles to the isolation layer.
TFC (Thick-Film-Copper)-thick film substrates

Just as with DCB, the basic material for thick film substrates is an isolation ceramic, which is
glued directly on to the base plate or a heatsink by means of silicone or applied by soldering
(Figure 1.45).
The tracks on the top side of the ceramic substrate are made of copper and are applied by screen
printing. The power semiconductor chips or other components are soldered or glued on to the
tracks.
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1 Basics
Chip (Si ; 280 m)

Solder (SnAg ; 80 m)
Printed Conductor (Cu 30-200 m)
Isolation (Al 2O3 (96%) ; 380 m)
Adhesive (Silicone ; 35 m)
Baseplate (Al or Cu ; 3 mm)
Figure 1.45 Basic structure of a TFC-power module [194]
TFC-technology can also be combined with standard thick film technology.

Since very low resistances may be produced by the paste materials which are usually applied in
thick film technology, and since isolated tracks can be arranged one on top of the other and
connected to each other, quite a number of system components may be integrated very closely
together. However, the very filigree tracks (thickness e.g. 15 m)will limit the current capability
of such structures to about 10 A.
1.4.2 Features of power modules

The assessment of parameters relevant for module assemblies will always depend upon the
specific application. The most important parameter with respect to railway drives, for example,
will be reliability, whereas low costs are the decisive criterion for the production of consumer
goods.
In this chapter, the applicability of a power module is to be regarded under the aspects of the
following comprehensive criteria: optimized complexity of a module, heat dissipation
capability, isolation voltage and partial discharge stability, temperature resistivity and load-
cycling capability of the internal connections, internal low-inductance structure, static and
dynamic symmetry of the structure, electromagnetic stability, defined and safe failure behaviour,
simple assembly and connection technology and favourable, non-polluting production and
recyclability.
1.4.2.1 Complexity
Optimized complexity cannot be defined in general. On the one hand, complex modules will
reduce appliance costs and minimize problems encountered when several components are to be
combined (parasitic inductances, interferences, wrong wiring).
On the other hand, increasing complexity will impair the universality of a module (reduced
production lots). The number of tests and the costs per module will increase. With an increasing
number of integrated components and connections the module will be more likely to fail and the
efforts for repair will be higher. Drivers, sensors and protection facilities have to meet high
demands for thermal and electromagnetic stability.
Up to now, none of the following module configurations has gained acceptance as a world
standard with respect to the integration of drivers. The actual state of this development is
described in chapter 1.6. The universality of power modules is greatly impaired by increasing the
integration of driver functions, the module increasingly becomes a sub-system.
On the one hand, intelligent modules are aiming at real mass production markets (consumer,
automotive), on the other hand markets are also involved, where many like applications can be
supplied with innovative module systems consisting of similar basic elements. In spite of
inevitable redundancies, the user may profit from reduced system costs due to the synergies
achieved at the module manufacturer.
Regarding the arrangement of IGBTs and diodes in the most commonly used power modules, the
configurations shown in Figure 1.46 have mainly gained a position in the market, meeting the
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1 Basics
demands of most applications in power electronics and drive technology. Figure 1.46 is
correspondingly applicable to modules with power MOSFETs, which are mainly applied in
configurations for power supplies today.
a) b) c) d)
e) f) g) h)
i) j) k) l)
m) n) o)
p) q)
r)
Figure 1.46 Important configurations of power modules with IGBTs and diodes
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1 Basics
a) ...GA...: single switch, consisting of IGBT and hybrid inverse diode (as for MOSFET
modules, here and in the other configurations, mostly just a parasitic inverse diode). In case of
external bridge circuits, the inverse diodes are mutually acting as free-wheeling diodes.
b) ...GB...: dual module (halfbridge module) consisting of two IGBTs and hybrid diodes (free-
wheeling diodes)
c) ...GH...: H-bridge with two arms consisting of IGBTs and free-wheeling diodes
d) ...GAH...: asymmetrical H-bridge with two diagonal IGBTs with hybrid inverse diodes (free-
wheeling diodes) and two free-wheeling diodes across the other diagonal.
e) ...GD...: 3-phase bridge (Sixpack, inverter) with three arms consisting of IGBTs and free-
wheeling diodes
f) ...GAL...: chopper module with IGBT, inverse diode + free-wheeling diode on the collector
side
g) ...GAR...: chopper module with IGBT, inverse diode + free-wheeling diode on the emitter side
h) ...GDL...: 3-phase bridge GD with chopper GAL (brake chopper)
i) ...GT...: Tripack-module with three pairs of switches
j) ...GAX... single switch with series diode on the collector side (reverse blocking switch)
k) ...GAY... single switch with series diode on the emitter side (reverse blocking switch)
l) ...GBD... dual module with series diodes (reverse blocking switch)
m) ...B2U-diode rectifier and IGBT-H-bridge
n) ...B2U-diode rectifier and IGBT-inverter (three-phase-bridge)
o) ...B6U-diode rectifier and IGBT-chopper GAL (IGBT and free-wheeling diode on the
collector side)
p) ...B6U-diode rectifier and IGBT-H-bridge
q) ...B6U-diode rectifier and IGBT-inverter (three-phase-bridge)
r) ...B6U-diode rectifier , IGBT-chopper GAL and IGBT-inverter (three-phase-bridge)
The SEMIKRON code designation system for SEMITRANS-IGBT and MOSFET modules is
referred to in chapter 1.4.4; for SKiiPPACK, MiniSKiiP and SEMITOP see chapter 1.5.
1.4.2.2 Heat dissipation capability

In order to guarantee optimal utilization of the theoretical current capability, generated power
losses have to be conducted safely and straightforwardly through the connection and isolation
layers to the heatsink.
Figure 1.47 shows the internal characteristics of a module which affect the capability to dissipate
heat (internal thermal resistance R/ internal thermal impedance Z), which determines the
maximum losses in the module (current, switching frequency, voltage,...) together with cooling
and ambient conditions.
The R-C elements shown in Figure 1.47, which are assigned to certain structural elements, are
not meant to give an exact reflection of the physical heat conditions, but are only to illustrate the
vertical flow of power and the temperature drop from the chip to the heatsink. The thermal
resistances Rth characterize the static state, therefore they may be assigned to the structural
elements.
However, capacitances replace physical elements, and may be gained by the transformation of
real heat capacitances from volume elements (characterized by volume and specific heat) as
opposed to a common thermal reference potential.
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1 Basics
Ptot
Tj
Silicon RthSi
1
Chip ZthSi Silicon Chip 220 m
Chip 1 ... Chip n
Solder 80 m
RthSo1 Aluminium oxide -
Solder 2 Isolation 380 m
Chip-Cu ZthSo1
Upper & lower copper
layer 300 m
Upper RthCu1 Solder 80 m
Copper 3
ZthCu1 Baseplate
Layer
(Copper) 3 mm
Thermal
Isolator RthIso compound 50 m
4
(Al2O3 or
ZthIso Heatsink
AlN)
Lower RthCu2
5
Copper
ZthCu2
Layer
Rthjh = RthSi + RthSo1 + RthCu1 + RthIso + RthCu2 + RthSo2 + RthBa + RthTc
Solder RthSo2 Zthjh = ZthSi + ZthSo1 + ZthCu1 + ZthIso + ZthCu2 + ZthSo2 + ZthBa + ZthTc
6
Copper-
ZthSo2
Baseplate
TC
RthBa Chip 1 Chip n
Baseplate 7 Module
ZthBa
Silicon
Rthjc1 Rthjcn
... Solders
Zthjc1 Zthjcn DCB-Substrate
Thermal RthTc
8
Compound
ZthTc Baseplate
Baseplate
Rthjh, Zthjh
TC
Heatsink & Rthha
Heatsink- 9
Rthch1 Rthchn Thermal
Ambient Zthha ...
Zthch1 Zthchn Compound
Ta
Th
Rthha Heatsink / Air
Zthha
Ta
Figure 1.47a Basic structure of a power module with DCB illustrating the influences on heat dissipation
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1 Basics
Ptot
Tj
Silicon RthSi
1
Chip ZthSi
Silicon Chip 220 m

Solder RthSo1 Chip 1 ... Chip n
2
Chip-Cu Solder 80 m
ZthSo1
Aluminium oxide -
Isolation 380 m
Upper RthCu1 Upper & lower copper
Copper 3 layer 300 m
Layer ZthCu1
Thermal
compound 50 m
Isolator RthIso Heatsink

4
(Al2O3 or
ZthIso
AlN)
Rthjh = RthSi + RthSo1 + RthCu1 + RthIso + RthCu2 + RthTc

Lower RthCu2
5
Copper Zthjh = ZthSi + ZthSo1 + ZthCu1 + ZthIso + ZthCu2 + ZthTc
ZthCu2
Layer
Thermal RthTc
8 Chip 1 Chip n
Compound
ZthTc Module Tj
Th Silicon
Rthjh1 Rthjhn
Heatsink & Rthha
... Chip-solder
Heatsink- 9 Zthjh1 Zthjhn DCB-Substrate
Ambient Zthha Thermal Compound
Baseplate
Ta
Rthha Heatsink / Air

Zthha
Ta
Figure 1.47b Basic structure of a power module with DCB without base plate illustrating the influences on heat
dissipation
The quality of the dissipation of total power losses Ptot generated in chips during forward on-
state and blocking state and during switching can be expressed by a minimized temperature drop
Tjh = Tj - Th
from chip (chip temperature Tj) to heatsink (heatsink temperature Th). It is quantified as thermal
resistance Rthjh (stationary) or thermal impedance Zthjh (transient).
Figures 1.47 and 1.48 illustrate the internal influences of the module on Rthjh and Zthjh:
- chip (surface, thickness, geometry and position),
- structure of the DCB-substrate (material, thickness, top side structure),
- material and quality of connections between chip and substrate (solder, adhesive,..),
- existence of a base plate (material, geometry),
- backside soldering of the substrate to the base plate (material, quality),
- assembly of the module (surface qualities/ thermal contact to the heatsink, thickness and
quality of thermal paste or thermal foil).
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This list is still to be supplemented by the mutual heating of chips (thermal coupling) in complex
power modules.
For modules with base plate the external thermal resistance or impedance (base plate-heatsink) is
indicated with Rthch or Zthch, respectively, in contrast to the internal resistance Rthjc or
impedance Zthjc (chip-base plate):
Rthjh = Rthjc + Rthch
Zthjh = Zthjc + Zthch

This difference cannot be made for modules without base plate.
Figure 1.48 indicates the Rthjc-shares of the above-mentioned influences for the most common
module structures of today described in chapter 1.4.2 with Al2O3-direct-copper-bonding (DCB)-
substrates and Cu-base plates as well as for modules with insulated metal substrates (IMS).
10% 3% 2% 11%
20% 2% Baseplate
Solder
Solder
8% Cu
Baseplate Si
Cu
6% Si
Al2O3 Polyimid
82%
56%
Figure 1.48 Influences on the internal thermal resistance of a 1200 V-power module, chip surface
9 mm * 9 mm [194]
a) For DCB-substrates (Al2O3) on a Cu-base plate
b) For IMS
The main share of thermal resistance is allotted to internal module insulation (the alternative of
external insulation with foils or something similar would result in a deterioration of insulation by
an even further 20 %...50 %!). Compared to Al2O3 with a purity of 96 % (heat conductivity
= 24 W/m*K), which is applied as a standard in common DCB-modules, improvements can be
made by using highly pure (99 %) Al2O3 ( = 28 W/m*K) or aluminum nitride (AlN,
= 150 W/m*K). In modules with high isolation voltages (thicker isolation ceramics) especially,
AlN, which is still very expensive, is preferred nowadays.
Despite the high thermal conductivity of its material (Cu: = 393 W/m*K), the base plate also
contributes to a considerable share of thermal module resistance due to its thickness
(2.5...4.5 mm). This share may be only partly reduced, since a reduction of the base plate
thickness would also bear the consequences of reduced temperature spreading and, thus,
reduction of the area through which the heat passes under the chips. In modules without base
plate the lack of heat spreading in Cu is compensated by missing thermal resistances of base
plate and rear-side soldering.
Furthermore, on condition there is a suitable assembly technology (DCB is pressed on to the
heatsink over wide areas), the chips will adhere closer to the substrate compared to constructions
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1 Basics
with base plate, since base plate and heatsink will never fully contact each other because of
unavoidable unevenness generated during the soldering process and, since the base plate is only
fixed to the heatsink by means of pressure screws positioned at the margins (Figure 1.49).
Module
Baseplate
a)
pressure pressure
Module
Baseplate
Thermal
Compound b)
Heatsink
pressure
DCB-Substrate
DCB
Thermal
Compound (thin!) c)
Heatsink
Figure 1.49 Problems arising through contact of power module to heatsink

a) Module with base plate before mounting (base plate with convex bending)
b) Module with base plate after mounting (strongly exaggerated!)
c) DCB-module without base plate (e.g. SEMITOP, SKiiP, MiniSKiiP)
Another factor that must not be neglected is the thermal resistance of the chip-substrate and (if
applicable) substrate-base plate connections, which are produced as solder connections (e.g.
= 75 W/m*K). The share of this resistance may be reduced by about 50 %, in cases where there
is no base plate.
The thermal resistance share of metal substrate areas (Cu: = 393 W/m*K) depends mainly on
the structure of the top side copper surface, which is used as chip carrier and internal electrical
connection system of the module. While the lateral heat flow in the lower copper layer is
practically not impaired, spreading of heat is limited by the geometrical dimensions of the copper
layers under the chips. It had been determined in reference [194] that Rthjc of a chip of
6.5 mm*6.5 mm on a Al2O3-DCB-ceramic substrate exceeds the value of a ten times as big
copper area by about 15 %, provided the chip and copper areas are identical.
The thermal resistance share of silicon chips increases proportionally to the thickness of the
chips, which is determined by forward blocking voltage and chip technology.
Moreover, the chip area determines the area through which the heat passes between chip and
base plate or heatsink.
On the one hand, the thermal resistance is reduced by increased chip areas due to a bigger area
through which the heat passes. On the other hand, an increase of the area/ circumference ratio of
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1 Basics
the chip will increase the influence of the thermal coupling of the heat flowing inside the chips
on the thermal resistance, heat spreading will be diminished. Both opposite tendencies will lead
to dependency of the thermal resistance Rthjc on the chip area Ach shown in Figure 1.50.
Rthjc [K/W]
10
IMS ; K=0.65
DCB (Al 2O3) ; K=0.76
DCB (AlN) ; K=0.96
0,1
0,01
10 100 ACh [mm2] 1000
Figure 1.50 Dependency of thermal resistance Rthjc on chip area Ach [194]
The dependency of Rthjc on Ach is almost linear, when the total heat conductivity of the substrate
(e.g. AlN-DCB) is high, since the chip area will hardly influence heat spreading. The worse the
heat conductivity of the ceramics, the higher the non-linearity of the Rthjc-dependency on Ach.
Therefore, the maximum power loss density in the chips (chip utilization) will be drastically
reduced by increasing the chip areas in like assemblies.
This correlation is also valid for the influence of module mounting to the heatsink, which is done
with thermal paste or thermal foils. With a value of = 0.8 W/m*K the heat conductivity of this
layer is relatively low, which will cause a thermal transient resistance Rthch between module base
plate and heatsink. Besides the thickness d of the thermal paste layer, the Rthch-share in the
thermal resistance Rthjh between chip and heatsink will also rise with increasing chip area.
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Rthca [K/W]
0,3
d=
0,25 50m
0,2 30m
20m
0,15
10m
0,1 5m
0,05
0
0 20 40 60 80 100 120 140
2
ACh [mm ]
Figure 1.51 Thermal resistance of thermal paste Rthca of a DCB-substrate (Al2O3) according to [279] and [194]
First of all, Figure 1.51 shows the influence of an optimal mounting technology (thin thermal
paste layer) on thermal parameters.
Secondly, it shows that thermal limits are set to the use of bigger chips to increase power output;
the thermal resistance share Rthjh of thermal paste, for example, will amount to approximately
30 % at an application thickness of 30 m for a 50A-IGBT-chip (9 mm * 9 mm).
Currently, the maximum chip sizes used in power modules are between 30 mm2 (IMS) and
150 mm2 (Al2O3-DCB). Higher power output can be reached by decentralization of heat sources
(paralleling of a maximum number of chips).
For the sake of a small geometry of the modules, more or less intensive thermal coupling of
chips has to be accepted, which is due to the tight arrangement of transistor and diode chips.
According to the calculations in reference [194] an increase of the chip temperature caused by
thermal coupling e.g. on a Al2O3-DCB-ceramic substrate should always be taken into
consideration, if the distance a of the chips equals:
a = 0.58 A Ch
As already mentioned above, apart from the static behaviour of power modules the dynamic
thermal behaviour, which is characterized by the thermal impedance Zth, is also of major
importance.
Figure 1.52 shows the characteristic of the thermal impedances Zthjc of a module with Al2O3-
DCB-substrate for different chip areas versus time.
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1 Basics
Zthjc [K/W] 56 mm 81 mm 121 mm

1
0,1
0,01
0,001
0,0001
1,00E-05 1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01
t [s]
Figure 1.52 Thermal impedances Zthjc of a module with Al2O3-DCB-substrate for different chip areas versus time
[194]
For the given module structure the Zth-characteristics for different chip areas may be shifted
against each other, i.e. the absolute values will change proportionally to the chip area, however,
without influencing the time constants of the exponential functions.
Accordingly, thermal impedances for different chip areas may be calculated similarly to the
thermal resistances in a given structure by
Zthjc1(t)/Zthjc2(t) = Rthjc1/Rthjc2 = (ACh2/ACh1)K.
Hereby, the exponent K, as a parameter indicating the influence of heat accumulation effect, may
be determined from Figure 1.50 [194].
1.4.2.3 Isolation voltage/ partial discharge stability [275]

Advancing in the high-voltage application range will result in increasing demands on IGBT-
modules for high isolation voltages and a high partial discharge stability.
Isolation and partial discharge stability are dependent on the thickness, material and
homogeneity of the insulation on the chip bottom and the case materials and, sometimes, on the
chip arrangement too.
The current transistor modules are subject to isolation test voltages between 2.5 kVeff and 9 kVeff,
applied to every module during production.
Figure 1.53 shows the maximum attainable isolation voltages for different isolation substrates
and todays standard substrate thicknesses d.
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13 kV
Isolation voltage
7 kV 7 kV
6 kV
Al2O3 AlN Epoxyd Polyimid

d=
[mm] 0.38 0.63 0.12 0.025
Figure 1.53 Isolation voltages for different isolation substrates with DCB, IMS and TFC
1.4.2.4 Power cycling capability

Power cycling at frequencies below approximately 3 kHz, especially at duty cycle operation,
such as prevails in traction, lift and pulse applications, will expose the internal connections in a
module to temperature cycling, such connections being:
- bonded joints,
- underside soldering of chips,
- solder connection of DCB and base plate,
as well as substrate lamination (Cu on Al2O3 or AlN).
The different coefficients of the length expansion of the layers cause thermal stress during
production and operation, which will finally lead to wear and tear of the material; module load
life (number of possible switching cycles) will be shortened when the amplitude of the chip
temperature fluctuation increases during these cycles.
Test procedures are dealt with in chapter 2.7; the correlation of module life and temperature
cycling amplitude will be explained in chapter 3.2.3.
Figure 1.54a explains the structural details relevant to the module life of an IGBT.
Bond Bonding Wire

Bond IGBT
2
Diode Bond
Chip Solder
Substrat
Base Plate Solder
Thermal Grease Base Plate (GP)
Heatsink
a)
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1 Basics
L/L Thermal Coefficient of Expansion

30
25
20
15
10
5
0
Al2O3 AlN Al Si Cu AlSiC b)
[75Vol%SiC]
3 x 3 mm
3 x 3 mm
System: standard 34mm module SKiiP pressure system

0,38mm-Al2O3 / Cu base plate 0,38mm-Al2O3
Results: T-Tkk L/L L T-Tkk L/L L
[K] [1E-6/K] [m] [K] [1E-6/K] [m]
silicon 69,7 4,1 0,86 62,6 4,1 0,77
substrate 55,4 8,3 1,38 48,3 7,8 1,13
base plate 40,5 17,5 2,13
2,13 0,00
silicon 1,38 1,23
0,86 0,89
substrate
base plate
0,00 0,50 1,00 1,50 2,00 2,50 0,00 0,50 1,00 1,50 2,00 2,50
L [m] L [m]
c)
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1 Basics
3 x 3 mm
3 x 3 mm
System: standard 34mm module 34mm module SKiiP pressure system

0,63mm-AlN / Cu base plate 0,63mm-AlN / AlSiC base plate 0,63mm-AlN
Results: T-Tkk L/L L T-Tkk L/L L T-Tkk L/L L
[K] [1E-6/K] [m] [K] [1E-6/K] [m] [K] [1E-6/K] [m]
silicon 53,4 4,1 0,66 61,8 4,1 0,76 50,8 4,1 0,62
substrate 46,6 5,7 0,80 55,2 5,7 0,94 44,2 5,7 0,76
base plate 38,1 17,5 2,00 42,7 7 0,90
2,00 0,90 0,00
silicon 0,80 0,94 0,76
0,66 0,76 0,62
substrate
base plate
0,00 0,50 1,00 1,50 2,00 0,00 0,50 1,00 1,50 2,00 0,00 0,50 1,00 1,50 2,00
L [m] L [m] L [m]
d)
Figure 1.54 Thermal expansion in a power module
a) Standard assembly of module with base plate
b) Thermal coefficient of expansion
c) Comparison: assembly with and without copper base plate; Al2O3 substrate
d) Comparison: assembly with and without copper/AlSiC base plate; AlN - substrate
Figure 1.54 makes clear that the solder connection of the substrate to the copper base plate is
most critical, since it is the most extensive connection - medium differences in the expansion
coefficients of the adjacent materials provided. Therefore, high-quality solders and sophisticated
soldering procedures have to be applied in order to avoid deformation and destruction of the
substrate also in case of high temperature cycling amplitudes.
Moreover, often the DCB-substrates are divided up to keep the absolute difference of the
expansion coefficient as small as possible by reducing the solder areas.
Other, lately developed module types are replacing copper by a material with a smaller
expansion coefficient (such as AlSiC), see chapter 1.5.4 and [206].
It is also shown in Figure 1.54 that modules with AlN-DCB are especially sensitive, because the
expansion coefficient of AlN is very similar to that of the chip silicon, but there are greater
deviations to copper than with Al2O3. Therefore, todays modules with AlN-DCB and Cu-base
plate cannot completely utilize the actual material performance with reference to the
corresponding datasheets.
It has become very obvious that one of the main causes for wear and tear can be eliminated by
doing without a base plate and the necessary soldering, as long as the heat transfer from the
substrate to the heatsink can be sufficiently ensured and the disadvantages of reduced heat
spreading can be compensated. This has been realized with SKiiP, MiniSKiiP, SEMITOP and
SKiM technologies (see chapter 1.5).
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The temperature cycling capability of the soldering of the chips to the substrate can be improved
by
- use of AlN-substrates with less deviation of the expansion coefficient to Si than Al2O3,
- substitution of soldering by low-temperature connections; the connection between chips and
substrate is realized by sintering silver powder at comparably low temperatures
(150...200C), which will minimize thermal stress among the materials during production.
Bond connections. Also the lifetime of the connection between bond wire and chip is influenced
decicively by the difference in thermal coefficients of expansion.
Silicon shows a relative slight lenght expansion (4.7 ppm/K) during power cycling. However, the
Al-metallization of the emitter and gate contacts which are stressed by the same temperature
fluctuations shows a considerable higher relative lenght expansion (23 ppm/K).
The stress inside of the metallization caused by this difference in expansion effects a
rearrangement of the crystal grains. This process is called reconstruction.
The reconstruction - mostly identifiable by an optical dispersive surface leads to the
destruction of the bond wire connection [304]. Reconstruction of Al-contact metallization can be
reduced by a polyimide-cover.
The lifetime of the bond connection on the chip contact area is increased considerably using
bond covers. However, another type of failure occurs. The mechanical deflection of the bond
wire during thermal alternating stress caused by the different thermal expansion of substrate and
Al-wire leads to a fracture of the bond wire nearby the bond-heel on the PCB-sided juncture
since the chip-sided bond-heel is mechanical strengthened by the polyimide cover.
Bond wire failures are mostly observed in lifetime tests whereas the failure is caused really by
ageing of the solder layer. Caused by growing cracks in solder layer the thermal resistance
increases and effects a increasing chip temperature and thus a higher stress for both the bond
connection and chip solder layer. Finally, this positive feedback leads to a failure.
In any case, the ageing of solder connection has to be investigated at failure analysis. Using
todays technologies solder connections and bond connections have nearly the same lifetime at
cycles with high temperature ripples (T100K).
In state-of-the-art power cycling test equipment forward voltage drop and thermal resistance of
power devices are measured and recorded. So, both degeneration of solder layer and bond
connection failures (steps in foward voltage drop characteristic) can be observed.
Bond connections in IGBT and diode-disc cells have been replaced by pressure contacts with a
higher temperature cycling capability due to pressure contact technology. Processes for
transferring this direct pressure contact technology to power modules are also currently being
developed.
1.4.2.5 Internal low-inductive structure

With the example of a halfbridge module, Figure 1.55 shows the most important internal
parasitic inductances of a module, resulting from the necessary connections among the chips and
to the module terminals (bond wires, internal connections).
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LC
TOP
LG
LEC
BOTTOM
LG
LE
LCE = LC + LEC + LE
Figure 1.55 Parasitic inductances in a dual IGBT-module

LG: parasitic gate inductances
LC: parasitic TOP-collector inductance
LEC: parasitic inductance between TOP-emitter and BOTTOM-collector
LE: parasitic BOTTOM-emitter inductance
LCE: total parasitic TOP-collector-BOTTOM-emitter inductance
Minimization of these inductances, which induce overvoltages during turn-off and cause a dI/dt
reduction during turn-on as well as inductive coupling of control and power circuit, will directly
affect the performance of power modules.
Moreover, parasitic inductances in modules with internally paralleled chips may cause unequal
dynamic performance of the chips and oscillations between the chips.
Chapter 3.4.1 gives details on these correlations.
1.4.2.6 Internal structure-adapted to EMC

The short rates of rise of current and voltage within the ns-range realizable with MOSFET- and
IGBT-modules generate electromagnetic interference with frequencies far beyond the MHz-
range. Therefore, the parasitic elements typical of the internal and out-leading paths of
propagation in the module exert considerable influence on the interference voltages generated.
Suitable isolation materials, small coupling areas or conductive shields can reduce, for example,
asymmetrical interferences [193].
In addition to that, the internal connections in the module have to be of such a structure, that
excludes failures caused by outer stray fields or transformatory couplings into control lines.
Another aspect of electromagnetic compatibility is the earth current, i.e. the current
iE = CE * dvCE/dt that flows due to the capacitance CE of the isolation substrate caused by the
dvCE/dt generated in the IGBTs during switching via the earthed heatsink to the earth connector.
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This earth current is identified as earth-leakage current by line monitors; its permissible
maximum value is to be limited to 0.1...5 % (1 % anticipated) of the nominal output current as
soon as the new EN 50178 comes into effect.
Accordingly, the permissible switching speed will increase proportionally to the decrease of
capacitance of the isolation substrate.
Figure 1.56 compares the capacitances of the most commonly used substrates with respect to
their standard thicknesses. The deviating dielectric constants and the standard thicknesses
depending on thermal conductivity (thickest substrate material is AlN with 630 m, thinnest
substrate is required in IMS-structures with 120 m for epoxy isolation and 25 m for polyimide
isolation) result in respectively differing capacitances CE and, thus, in different limits of the
maximum switching velocity dvCE/dt for the maximum tolerable earth current iE.
Capacity per unit area

d=0.025 mm
140
120
100
80
d=0.12 mm
60
40 d=0.38 mm
d=0.63 mm
20
0
Al2O3 AlN Epoxy Polyimid
Figure 1.56 Capacitance per unit area for different isolation substrates
1.4.2.7 Defined safe behaviour in case of module failure

In the case of module failure (probably caused by use of wrong driver) the total energy stored in
the DC-link capacitors will be transferred, for example, in a voltage-supplied circuit within the
module case. After melting the bond wires this energy is mainly stored in the generated plasma,
which allows the module to explode.
In conventional transistor modules this may cause circuit interruption, short-circuit of the main
terminals or even bridging of the isolation; plasma and particles of the case might be spread over
the module surroundings with high kinetic energy.
With the proper case construction, the dangers involved may be limited and the particles spread
are guided in a defined direction.
The latest developments in this field guarantee, for example, that up to a defined energy level of
e.g. 15 kJ no particles will leave the module; even at 20 kJ the case might break, but no solid
metal particles would be hurled out [196].
1.4.2.8 Non-polluting recycling

Todays power modules usually exclude toxic materials (e.g. BeO) and the number of materials
used is kept as low as possible.
Case and other materials are flame-resistant and must not release toxic gas during burn-out (UL-
specification).
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The module has to be split up as simply as possible in metal and non-metal components during
recycling. Therefore, the currently available modules are cast solely with elastomeric materials
(soft moulding).
1.4.3 Assembly and connection technology: types of cases

Cases of current power modules containing 1...7 MOSFET or IGBT-switches are mostly
equipped with screw, plug-in or solder-terminals.
For the majority of transistor modules, different manufacturers are striving for a large degree of
compatibility with partly historically developed structures (Figure 1.57).
First of all, the inevitably deviating high-integration modules (e.g. SKiiPPACK, MiniSKiiP) are
not to be considered in the following.
GB GAL GAR GD GDL
GA
GB GAL GAR Sixpack: GD GDL
Figure 1.57a Transistor modules with base plate
SEMITOP
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SKiM 3
SKiM 4 SKiM 5
Figure 1.57b Transistor modules without base plate
The highest degree of standardization is assigned to module types with screw connectors. The
main supplies may be contacted by busbars or sandwich assemblies. Often, additional outputs are
provided for control and sense-units (e.g. control-emitter, sense-collector) in order to minimize
the influence of inductive voltage drop in the main circuit generated during switching, especially
at the bonded connecting wires. Auxiliary supplies are mostly designed as 2.8 mm flat strip plug
connectors, sometimes also as screw connectors.
For low-current modules the use of 6.3 mm or 2.8 mm flat strip plug connectors for power and
control circuit, respectively, has also been very common up to now.
Solderable modules for PCB-assembly (e.g. SEMITOP, ECONOPACK) are gaining importance,
because they offer cost advantages during automatic production and tooling procedures.
Optimized layout of connectors will take care of low-inductance assemblies, and currents up to
100 A may be realized by paralleling several solder connectors. In this respect, the necessary
track sections (for high currents) and the realization of long creepage paths on the PCB might be
problematic.
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1.4.4 SEMIKRON code designation system for SEMITRANS- and SEMITOP-power

modules
Different functions, internal circuits, current and voltage range and other informations are coded
by the manufacturers in their type designations.
The following tables indicate the code designation system for SEMIKRON MOSFET and IGBT-
modules.
SEMITRANS power-MOSFET-modules
There is an old and a new designation code for SEMITRANS-MOSFET-modules. The old
designation code had been introduced with the first MOSFET-modules, some of which are still
being produced, at the end of the eighties following the PRO-ELECTRON-recommendations by
SEMIKRON. All newly developed modules are designated according to the new code, which
gives more information and corresponds basically to the designation code for SEMITRANS-
IGBT-modules.
old designation code, e.g. new designation code, e.g.

SK M 1 5 1 A F R C SK M 120 B 020
SEMIKRON component SEMIKRON component
MOS technology MOS technology
Circuit configuration Drain current grade

1: Single switch (ID/A at Tcase = 25C)
2: Dual mode (halfbridge)
3: Special type Circuit configuration
4: 4-pack (H-bridge) A: Single switch
6: 6-pack (three-phase-bridge) B: Dual mode (halfbridge)
D: 6-pack (three-phase-bridge)
Voltage grade M: 2 MOSFETs in center tap connection
0: VDS = 50 V 5: VDS = 500 V
1: VDS = 100 V 8: VDS = 800 V Drain-source voltage grade
2: VDS = 200 V 9: VDS = 1000 V (VDS/V/10)
4: VDS = 400 V
Internal arrangement
0: 4...5 chips in parallel 3: Special type
1: 6 chips in parallel 4: 4+4 chips
2: 2 chips in parallel
A: avalanche-proof single chips

F: built-in fast inverse diode
R: built-in gate series resistors
C: built-in gate driver circuit (manufactured until 1996)
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SEMITRANS IGBT-modules
z.B. SK M 100 G B 12 3 D L
SEMIKRON component
M: MOS technology
D: 7D-pack (B6-diode input bridge with IGBT chopper)
Collector current grade (IC/A at Tcase = 25C)
G: IGBT switch
Circuit configuration
A: Single switch
AL: Chopper module (IGBT and free-wheeling diode on collector side)
AR: Chopper module (IGBT and free-wheeling diode on emitter side))
AH: Asymmetric H-bridge
AX: Single IGBT + series diode on collector side (reverse blocking)
AY: Single IGBT + series diode on emitter side (reverse blocking)
B: Dual module (halfbridge)
BD: Dual module (halfbridge) + 2 diodes in series (reverse blocking)
DL: 7-pack (three-phase-bridge + AL-chopper)
H: Full single phase H-bridge
M: 2 IGBTs in collector connection
Collector-emitter voltage grade (VCE/V/100)
IGBT-series no.
0: first generation 1988-1991 (collector current grade specified at Tcase = 80C)
1, 2: first generation 1992-1996 (collector current grade specified at Tcase = 25C)
(600V-types: PT-IGBTs, collector current grade specified at Tcase = 80C)
3: second generation (high density-NPT-IGBTs for 600 V and 1200 V),
first generation NPT-IGBT-chips for 1700 V, CAL-diodes;
600 V-types: collector current grade specified at Tcase = 80C,
1200 V-/1700 V-types: collector current grade specified at Tcase = 25C;
low inductance case
4: high density, lowVCEsat-NPT-IGBT-chips (1200 V, 1700 V)
5: high density, high speed-NPT-IGBT-chips (600 V, 1200 V)
6: Trench-NPT-IGBT-Chips
Features
D: fast inverse diode
K: SEMITRANS 5-case with screw connectors
L: 6-pack-case with solder pins
S: Collector-Sense-Terminal
I: enlarged inverse diode (higher power capability)
SKiiP converter in an
automobile with hybrid drive
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SEMITOP power modules

The SEMIKRON SEMITOP module range comprises solderable power modules with thyristors,
diodes, power MOSFETs and IGBTs; in the following only SEMITOPs with MOSFETs and
IGBTs are considered,
e.g. SK 100 G B 12 3 x
SEMIKRON component
Current rating in A at Th = 25C
G: IGBT-switch
M: MOSFET-switch
Circuit
A: Single switch
AL: Chopper module (IGBT/MOSFET + free-wheeling diode at collector side)
AR: Chopper module (IGBT/MOSFET + free-wheeling diode at emitter side)
AH: Asymmetric H-bridge
B: Dual module (halfbridge)
H: Full single phase H-bridge
Voltage grade (VCE/V/100 or VDS/V/100)
IGBT-series
2: PT-IGBT-chips (only for 600 V)
3: high density-NPT-IGBT-chips
4: high density, low VCEsat-NPT-IGBT-chips
5: high density, high speed-NPT-IGBT-chips
Features (not yet defined for SEMITOPs with IGBT and MOSFET-chips)
The fast inverse diode(s) integrated in every IGBT-SEMITOP are not indicated in the
designation code.
1.5 Examples for new packaging technologies

New packaging technologies are being developed mainly with regard to:
- improvement of heat dissipation and temperature cycling capability,
- minimized inductances in the module and in the supply leads by means of suitable module
construction,
- highly flexible assembly and connection technology, easy mounting at the users facilities,
- higher complexity of integration (converter circuits),
- integration of monitoring, protection and driver functions,
- delivery of tested electric or thermal-electrical systems.
The following four ranges of power modules, which have been developed with consideration to
the requirements mentioned above, are therefore regarded as exemplary.
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1.5.1 SKiiPPACK
Figure 1.58 shows the scheme of a SKiiPPACK (Semikron integrated intelligent Power Pack).
pressure plate pressure screw

PC board with
auxiliaryconnectors
elastic material
plastic pressure
main terminal spread
DCB substrate spring integrated in

with chips pressure spread as
auxiliaryconnector
housing thermal conductive
frame layer
heatsink
Figure 1.58 Basic SKiiPPACK structure
In contrast to conventional transistor modules, the DCB-substrates carrying the IGBT and diode
chips are not soldered on to a copper base plate, but are pressed almost with the complete surface
directly to the heatsink by means of a plastic pressure spread. The electrical connection of the
DCB to the SKiiPPACK terminals, designed for connection of laminated, low-inductance
busbars, is made by pressure contacts and low-inductive track layout. A metal plate serves as
pressure element and as thermal and EMI-shield for the driver circuit, which is also integrated
into the SKiiP case.
By paralleling many, relatively small IGBT-chips and with their optimal contact to the heatsink,
the thermal resistance may be reduced considerably compared to standard modules, since the
heat is spread evenly over the heatsink.
Three sizes of cases (2, 3 and 4 arms in GB, GAL or GAR-configuration) and different chip
arrangements as well as adapted driver components connected by simple external constructions
guarantee the realization of dual modules, H-bridges, SIXPACKS and SEVENPACKs in 600 V-,
1200 V- and 1700 V-technology. 3300 V-SKiiPPACKs are under development.
In Figure 1.59 the special flexibility of the SKiiPPACK principle is explained with an example.
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a)
b) c)
Figure 1.59 Possible applications of a SKiiPPACK with 3 identical DCBs (example)

a) View of a SKiiPPACK on an aluminium heatsink
b) SIXPACK
c) Dual module (halfbridge)
Besides transistor and diode chips, PTC-temperature sensors are integrated into the DCB; their
output signal directly affects driver operation (temperature limit) and - due to analogous
amplification in the driver - it can also be used for evaluation of the heatsink temperature.
The AC-connectors of the SKiiPPACK accommodate current sensors for overcurrent and short-
circuit protection of the IGBTs. Signal processing and linkage is done by the internal driver,
which is positioned on the pressure plate; this will be described in detail in chapters 1.6 and
3.5.8. The potential-free current signals may also be used as actual values for external sensors
and control circuits.
Advantages offered by SKiiPPACKs in comparison to conventional modules are:

- improved temperature cycling capability,
- reduced thermal resistance by direct heat transfer chip-DCB-heatsink,
- possibility of producing very compact constructions with high power density,
- low switching overvoltages due to thorough low-inductive structure, i.e. high permissible
DC-link voltage and reduction of interference generation,
- repairable and recyclable by excluding hard moulding and internal soldering,
- optimal adjustment of internal, intelligent driver,
- load test of complete systems carried out at manufacturer.
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Figure 1.60 shows SKiiPPACK cases and some of standard internal circuits. Further circuits are
available and may be integrated if required by the customer, respectively (e.g. brake chopper,
asymmetrical bridges).
Besides the heatsink shown below, other air or water-cooled heatsinks may also be used for
mounting of the SKiiPPACKs.
view from right Case S2 Case S3 Case S4/S5*
*
*
*
(with standard
heatsink for
air-cooling)
* case S5 has an additional DIN-Connector on the right quarter of top (for brake-chopper-input)
** F-Option: fibre optic connectors for driver input and fault detector output
Figure 1.60 SKiiPPACK cases and standard internal circuits
1.5.2 MiniSKiiP
Another new development for the low-power range, which is outstanding for its special
flexibility and easy mounting is SEMIKRONs MiniSKiiP with pressure contacts, the basic
structure of which is shown in Figure 1.61.
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Printed Circuit Pressure Screw

Board (PCB) Pressure Lid
Case
Contact Spring
Bond Wire
Chip
Isolation
Substrate
Heatsink
Figure 1.61 Basic structure of a MiniSKiiP
Basic elements of a MiniSKiiP are:

- DCB isolation substrate with soldered, wire-bonded semiconductor chips (e.g. IGBTs,
MOSFETs, diodes, thyristors) as well as other components, such as current and temperature
sensors, resistors and capacitors,
- silicone filled case with integrated contact springs and glued in DCB and
- hard plastic cover.
One or two screws take care of all electrical and thermal connections (to the heatsink) making a
detachable connection between SKiiP cover, PCB, MiniSKiiP and heatsink. The contact springs
have several functions: they serve as the electrical connection between the power
semiconductors on the DCB and the other circuits on the PCB, and also as pressure spring pad
between DCB and heatsink in the mounted state.
The high number of springs spread over the total MiniSKiiP area provides for even pressure
between components and heatsink, which guarantees a low thermal resistance.
For the current range above 10 A, the contacts are connected in parallel. The multitude of spring
shafts results in a high degree of flexibility concerning the production of many different circuits
for drives and power supplies as well as other applications.
Several types of cases designed for different power ranges are available from MiniSKiiP 1 (line
voltage up to 230 V, rated current up to 12 A) to MiniSKiiP 8 (line voltage up to 400 V, rated
current up to 125 A) (Figure 1.62).
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MiniSKiiP
Case M 1
MiniSKiiP
Case M 2
MiniSKiiP
Case M 3
MiniSKiiP
Case M 8a; Case M 8 M 8a M8
Figure 1.62 Standard MiniSKiiP types and circuits
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In the biggest MiniSKiiP (MiniSKiiP 8) curved, pressure contact springs are used because of the
high currents applied; these can be supported by compensating current sensors on the AC-side.
(Figure 1.63).
Figure 1.63 MiniSKiiP 8 curved springs with current sensors
In order to avoid too high a concentration of heat sources, the standard circuit is divided up over
two cases, one of them containing the uncontrolled or half-controlled bridge rectifier and the
brake chopper, the other containing the three-phase-converter.
1.5.3 SEMITOP
The product range of SEMITOP, which has already been mentioned, comprises 3 types of cases
(see Figure 1.57).
Just like SKiiPPACK and MiniSKiiP, SEMITOP is also assigned to those constructions without
base plate that generate widespread pressure of the DCB to the heatsink by a special construction
of the plastic housing.
One or two screws make a closed linkage between module and heatsink. In contrast to
MiniSKiiP the contacts to the PCB are made by two lines of solder pins.
Due to the ability of such a small module to integrate up to 12 power components, SEMITOP is
used preferably in low-size applications. The unrestricted useability of the space between the
solder pins for other printed circuit board components is advantageous in comparison to
MiniSKiiP, which is very similar in its technology.
1.5.4 New low-inductive IGBT module constructions for high currents and voltages
A very interesting and promising development in high-power electronics (e.g. 1.2 kA and
2.5/3.3 kV) is the low-inductive FLIP-module (ABB Semiconductors, [6]) and the SKiM20-
module (without base plate) by SEMIKRON (Figure 1.64).
These modules had been designed especially for high-power range. Therefore, the development
goals had been mainly high reliability (high power and temperature cycling capability), good
heat dissipation behaviour (decentralized heat sources / low thermal resistances), minimized
inductances in the module and module busbarring as well as safe failure behaviour (explosion
protection by means of defined areas for pressure balancing).
Figure 1.64 shows the basic assembly of a SKiM20-module as the most modern version of such
module constructions.
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Figure 1.64 Construction of an IGBT-module SKiM20
As the other SKiM-models shown in Figure 1.57 the SKiM20 has no base plate. From this the
advantageous basic features discussed in chapter 1.4.2.4 (Figure 1.54) result. The semiconductor
chips are arranged on three small areas of AlN ceramic substrates.
One ceramic substrate combined with a case element and a pressure spread element made from
plastic as well as a pressure plate forms a sub-module. The pressure spread element presses the
substrate almost over its full area to the heatsink. The main terminals of each sub-module are
soldered to the substrate. The control and auxiliary terminals are made as pressure contacts.
The case cover also acts as pressure element.
1.6 Integration of sensors, protective functions, drivers and intelligence

In the following, some examples for the integration of peripheral functions in power modules are
described, sorted by increasing degrees of integration.
Sense IGBT-Module
Sense IGBT-modules contain sense-IGBTs as described in chapter 1.2.4.
Compared to solutions with shunts in the emitter circuit, a much higher measuring resistance
may be chosen. Other than with overcurrent protection by VCE-monitoring, either shorter dead-
times are required or none at all.
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Modules with integrated temperature sensor

As an alternative to the TEMPFET (see chapter 1.2.4) as a solution for discrete power
semiconductors, simple PTC-temperature sensors in SMD-design are being used in modules
more and more, with a higher degree of integration; they are soldered on to the DCB-substrate
near the chips.
The heatsink temperature is indicated at a defined point by the sensors. Ideally, the transversal
heat flow between this point and the heatsink areas under the hottest chips may be neglected. A
suitable evaluation board takes care of overtemperature protection by active control on the driver
or processing the analogous signal.
Rugged Modules [281]

Besides the IGBT hybrid protective circuit are integrated into the case for protection of the IGBT
in case of failure. The terminal behaviour are determined by the driver just as with conventional
IGBTs; the protective circuits are activated only in case of failure and will limit the short-circuit
current.
IPM (Intelligent Power Modules) [280]

IPM modules are able to integrate, in addition to the IGBTs and free-wheeling diodes, drivers
and protective units (IPM minimal configuration) as well as complete inverter control units. The
user, himself, can no longer control switching and on-state characteristics, therefore IPMs are
often designed specifically for the application (ASIPM = Appl. Specif. IPM).
SKiiPPACKs (Semikron integrated intelligent Power Packs)

As already described in chapter 1.5.1, SKiiPPACKs contain a driver unit, laid out as an SMD-
PCB, which integrates all the necessary protective and monitoring functions and which is
positioned over the pressure plate. (see Figure 1.58).
SKiiPPACKs may be driven and supplied on potential of the superordinated control system
(CMOS or TTL level). The SKiiPPACK driver integrates all necessary potential separation, a
SMPS and the power drivers.
SKiiPPACKs are equipped with current sensors in the AC-outputs and temperature sensors as
well as an optional DC-link voltage sensor. The driver valuates the signals transmitted by the
sensors in order to care for overcurrent/ short-circuit, overtemperature and overvoltage
protection as well as supply-undervoltage protection. An error signal and standardized analogous
voltage signals of the actual AC-output current value, the actual heatsink temperature and,
optionally, the DC-link voltage are available on separate potentials at the driver connector for
evaluation in the superordinate control circuit.
Figure 1.65 describes the OCP (Over Current Protection) driver principle, which will be detailed
in chapter 3.5.8.
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Figure 1.65 OCP-driver principle [264], [265]
96
2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules
2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and

SKiiPPACK modules
2.1 General
2.1.1 Letter symbols, terms, standards
Letter symbols and terms [264], [265]

Voltages: firstly, two index letters are used to indicate the terminals between which the applied
voltage is taken. If the potential of the terminal designated with the first index letter is positive
versus the terminal designated with the second index letter (reference potential), the applied
voltage is positive, e.g. VCE.
As for diodes, F is used for the forward on-state voltage (positive anode potential versus
cathode potential) and R for the reverse blocking voltage (positive cathode potential versus
anode potential).
As for transistors, an additional third index letter may indicate the type of circuit between
terminal 2 and a non-designated third terminal, e.g. VCGR, where the third letter symbol is
defined as follows:
S: short-circuit between terminal 2 and 3,
R: resistor to be specified between terminal 2 and 3,
V: external voltage between terminal 2 and 3, to be specified,
X: resistor and external voltage between terminal 2 and 3, to be specified.
Index letters can be followed or preceded by other index abbreviations for further specification
of parameters, either with or without brackets and either as capital or small letters (e.g. V(BR)DS or
VGE(th) or VCEsat), for example:
(BR): breakdown voltage,
sat: saturation voltage,
(th): threshold voltage,
clamp: clamping voltage limited by external circuits.
Supply voltages are often marked by doubleindex letters, e.g. VGG (supply voltage of gate-
emitter circuit), VCC, VDD.
Currents: at least one index letter is used to specify a current. Positive values specify positive
currents, which enter the component at the terminal and are named first in the index, e.g. IGE. If
there is no danger of mix-up, only the first index letter is usually used, e.g. IC (collector current),
ID, IG. The same applies when indicating negative currents.
As for diodes, F is used for indicating forward on-state currents (anode-cathode) and R for
reverse currents (cathode-anode).
As for transistors, an additional third index letter may indicate the type of circuit between
terminal 2 and a non-designated third terminal, e.g. IGES, where the third letter symbol is defined
as follows:
S: short-circuit between terminal 2 and 3,
R: resistor to be specified between terminal 2 and 3,
V: external voltage between terminal 2 and 3, to be specified,
X: resistor and external voltage between terminal 2 and 3, to be specified.
97
Index letters can be followed or preceded by other index abbreviations, either with or without
brackets and either as capital or small letters, for example:
AV : average value,
RMS: effective value, (root mean square)
M: peak value (maximum),
R: periodic (repetitive),
S: non-periodic (spike),
puls: pulsed (direct current).
Other symbols: the terminology used for other symbol indications for electrical, thermal and
mechanical parameters mainly follows the terminology for voltages and currents; for further
explanation please see the following table. Index letters may also specify turn-on (on) and turn-
off (off) switching states (mostly in brackets).
Standards for terms and definitions

Details with regard to definitions, determination of terms, datasheet parameters and measurement
procedures may be taken, for example, from the following standards:
Standards, terms and definitions

DIN 40 900 T5 Semiconductors, switching symbols
DIN 41 781 Diodes: terms and definitions
DIN 41 785 T3 Power semiconductors: symbols
DIN 41 858 Field effect transistors: terms and definitions
IEC 191-1...4 Mechanical standards (cases)
IEC 50 (521) 1984, (551) 1982 International dictionary for electrical
engineering
IEC 617-5 Graphic symbols, switching symbols for diagrams
IEC 971 (1989-07) Semiconductor converters: designation system
Datasheet parameters and measurement procedures

DIN 41 791 T1 Principle designations for datasheets
DIN 41 792 T2 Test procedures: diodes
T3 Test procedures: heat resistance
IEC 747-1: 1983 Semiconductor components/ Volume 1: General
hints with reference to maximum ratings and
characteristics, test procedures
IEC 747-2: 1983, A1(1992), A2(1993) Rectifier diodes
IEC 747-8: 1984, A1(1991), A2(1993) Field effect transistors
IEC 60747-9: 1998 FDIS IGBTs (in preparation)
R & D standards and reliability

IEC 664-1: 1992 Co-ordination for the isolation of electrical
appliances < 1 kVeff
Volume 1: principles, test procedures
IEC 146-1-1: 1991/EN60146-1-1: 1993 Semiconductor converters: basic requirements
DIN EN50178 (VDE0160): 4/1998 Electronic devices for power systems:
general isolation test procedures
IEC 947-4-2/EN60947-4-2:1997 Designation system for low-voltage appliances,
volume 4.
UL 1557: 5/1993 Inflammability, isolation safety
98
UL 94-V0: 9/1981 Inflammability of plastic materials

IEC 747-1, IX: 1983 Components at risk of ESD (Electrostatic
Discharge)
DIN IEC 68-2-... Reliability tests
ISO 9001/EN29001: 1995 Quality system certification
DIN EN ISO 9001: 8/1994 Re-qualification of quality system
2.1.2 Maximum ratings and characteristics
Maximum ratings
Maximum ratings for modules indicated in the datasheets are extreme values of electrical,
thermal and mechanical load permissible without risk of destruction or damage. Every limit
value has been specified according to exactly defined conditions, which have inevitably to be
indicated in the datasheets, since some of these conditions have not (yet) been standardized.
Exceeding one of the maximum ratings may lead to destruction of the component, even if other
maximum ratings have not been strained to their utmost limit.
In addition to the static maximum ratings listed in the following there are so-called dynamic
maximum ratings, which designate the permissible course of the characteristics (current/ voltage)
during switching.
If not otherwise shown, the maximum ratings in the datasheets are valid at a chip or case
temperature of 25C, for higher temperatures deratings usually have to be considered.
Characteristics
Characteristics describe the features of components determined under certain specified
measuring conditions (mostly application-specific).
Just as with maximum ratings, all characteristics are subject to exactly specified ambient
conditions which have to be indicated in the datasheets, since some of those conditions are also
not standardized.
Characteristics are often indicated as typical values within a range.
The reference temperatures for chip or case are normally indicated with e.g. 25C or 125C so
temperature dependency has to be considered in the case of differing temperatures.
Limits and characteristics are published in the form of tables and diagrams.
2.2 Power MOSFET modules [264], [265]
2.2.1 Maximum ratings
MOSFETs/module structure
Drain-source voltage VDS
Maximum voltage between drain and source contacts of MOSFET chips for open or closed gate-
source circuit.
Parameter: case temperature Tcase = 25C
99
Drain-gate voltage VDGR

Maximum voltage between drain and gate,
Parameters: external resistance RGS between gate and source, case temperature Tcase = 25C
Continuous direct drain current ID

Maximum direct current at drain output
Parameters: case temperature, e.g. Tcase = 25C, 80C: ID@25C, ID@80C
Peak value of a periodic drain current IDM or pulsed drain current IDpuls
Peak value of current at drain output during pulse operation,
Parameters: pulse duration tp, case temperature, e.g. Tcase = 25C, 80C and pulse/break ratio
(diagram maximum safe operating area)
Single pulse avalanche energy dissipation EAS

Maximum avalanche energy dissipation from drain to source of a single chip during turn-off of
an unclamped inductive load (single pulse load),
Parameters: instantaneous drain current iD, drain-source supply voltage VDD, external gate-source
resistance RGS, external drain inductance L, chip temperature, e.g. Tj = 25C
Gate-source voltage VGSS or VGS

Maximum voltage between gate and source
Total power dissipation Ptot or PD

Maximum power dissipation per transistor/diode or within the whole power module
Ptot = (Tjmax-Tcase)/Rthjc,
Operating temperature range Tvj or Tj ; Tj(min)....Tj(max)

Permissible chip temperature range within which the module may be permanently operated
Storage temperature range Tstg; Tstg(min)....Tstg(max) )

Temperature range within which the module may be stored or transported without being subject
to electrical load.
Isolation test voltage Visol or Vis

Effective value of the permissible test voltage between input terminals/ control terminals (short-
circuited, all terminals connected to each other) and module base plate.
Parameters: test duration (1 min, 1 s), rate of rise of test voltage, if required;
according to IEC 146-1-1 (1991), EN 60146-1-1 (1993), section 4.2.1 (corresponds to VDE
0558, volume 1-1: 1993-04) and DIN VDE 0160 (1988-05), section 7.6 (corresponds to EN
50178 (1994)/ E VDE 0160 (1994-11) the test voltage shall only rise gradually up to its
maximum rating.
Grade of humidity
describes the permissible ambient conditions (atmospheric humidity) according to DIN 40 040
Grade of climate
describes the permissible ambient test conditions (climate) according to DIN IEC 68-1
100
Inverse diodes/ free-wheeling diodes

Forward current IF
Maximum forward current value of inverse or free-wheeling diodes,
Parameter: case temperature, e.g. Tcase = 25C, 80C
Peak forward current IFM or pulsed forward current IFpuls

Peak value of diode current during pulse operation
Parameters: pulse duration tp, case temperature, e.g. Tcase = 25C, 80C
2.2.2 Characteristics
MOSFETs/ module structure
Drain-source breakdown voltageV(BR)DSS
Breakdown voltage between drain and source, gate-source short-circuited (VGS = 0)
Parameters: Reverse drain current ID, case temperature Tcase = 25C
Gate-source threshold voltage VGS(th)

Gate-source voltage above which considerable drain current will flow,
Parameters: drain-source voltage VDS = VGS, drain current ID, case temperature Tcase = 25C
Zero gate voltage drain current IDSS

Blocking current between drain and source with gate-source short-circuited (VGS = 0) and drain-
source voltage VDS = VDSS,
Parameter: chip temperature, e.g. Tj = 25C and 125C
Gate-source leakage current IGSS

Leakage current between gate and source with drain-source short-circuited (VDS = 0) at
maximum gate-source voltage VGS,
Parameters: gate-source voltage VGS, case temperature Tcase = 25C
Drain-source on-resistance RDS(on)

Quotient of changing drain-source voltageVDS and drain current ID in a thoroughly gate-
controlled MOSFET at a specified gate-source voltage VGS and a specified drain current ID (at
rated current),
In this state VDS is proportional to ID, during large-signal behaviour the forward on-state voltage
VDS(on) = RDS(on) * ID.
Parameters: gate-source voltage VGS, drain current ID (rated current), case temperature
Tcase = 25C (RDS(on) is extremely dependent on temperature!).
Forward transconductance gfs

Quotient of changing drain current and gate-source voltage at a specified drain current ID (at
rated current),
Parameters: drain-source voltage VDS, drain current ID (rated current), case temperature
Tcase = 25C
Capacitance chip-case CCHC

Capacitance between a sub-component and the case base plate or the heatsink potential,
101
Input capacitance Ciss

Capacitance between gate and source with drain-source short-circuited for AC and gate-source
voltage VGS = 0.
Parameters: drain-source voltage VDS, measuring frequency f, case temperature Tcase = 25C
Output capacitance Coss

Capacitance between drain and source with gate-source short-circuited (VGS = 0),
Reverse transfer capacitance (Miller capacitance) Crss, Cmi

Capacitance between drain and gate with drain-source short-circuited at AC and gate-source
voltage VGS = 0. For measuring, the source has to be connected with the protective shield of the
measuring bridge.
Parasitic drain-source inductance LDS

Inductance between drain and source
Switching times
Switching times indicated in MOSFET datasheets are determined from a measuring circuit under
ohmic load according to Figure 2.1a. They refer to the gate-source characteristics during turn-on
and turn-off, see Figure 2.1b.
Switching times as well as real current and voltage characteristics are determined by internal
capacitances, inductances and resistances and by those of the gate and drain circuit; for this
reason, all indications in the datasheets and the characteristics depicted therein may serve only as
a guide.
As the current and voltage characteristics are not relevant to most applications, because they are
based on the application of pure ohmic load, their importance is actually restricted to the
definition of switching times.
The waveforms will deviate significantly especially if inductive or capacitive loads are involved
(chapter 1.2.3) and also the measurement results may differ.
102
a)
b)
Figure 2.1 a) Measuring circuit

b) Definition of MOSFET switching times under ohmic load
The following parameters are indicated relevant to switching times:

measuring circuit, drain-source supply voltage VDD, gate-source control voltage VGS, drain
current ID, gate series resistance RG (internal resistance of the control circuit), sometimes gate-
source resistance RGS, case temperature Tcase = 25C.
Turn-on delay time td(on)

After sudden turn-on of a positive gate-source control voltage VGG, the gate-source voltage VGS
starts to rise with a time constant determined by input capacitance and gate resistance. As soon
as the threshold voltage VGS(th) has been reached, the drain-source voltage VDS will start to
decrease and the drain current ID will begin to rise.
The turn-on delay time td(on) is defined as the time interval between the moment when the gate-
emitter voltage VGE has reached 10 % of its end value (VGG), and when the drain-source voltage
has dropped to 90 % of its initial value (VDD) .
Rise time tr
The rise time tr is defined as the time interval following the turn-on delay time, where the drain-
source voltage drops from 90 % to 10 % of its initial value (VDD). During this time, the drain
103
current will rise (therefore rise time), i.e. the major part of the turn-on losses is generated
during this time interval.
The sum of turn-on delay time td(on) and rise time tr is called turn-on time ton.
As the drain-source voltage VDS will not yet have reached its forward on-state value VDS(on) =
RDS(on) * ID at the (defined) end of ton, but still amounts to 10 % of VDD, there will still be higher
losses after ton than the forward on-state losses.
Turn-off delay time td(off)

After sudden turn-off of the positive gate-source control voltage VGG, the gate-source voltage
VGS starts to decline with a time constant determined by the input capacitance of the MOSFET
and the gate-source resistance RGS. The drain current which is coupled with the gate voltage in
the active operating area via forward transconductance gfs = diD/dvGS also begins to decrease,
whereas the drain-source voltage starts to rise accordingly.
The turn-off delay time td(off) is defined as the time interval between the moment when the gate-
emitter voltage VGE has declined to 90 % of its initial value (VGG), and the drain-source voltage
has risen to 10 % of the supply voltage VDD.
Fall time tf
The fall time tf is defined as the time interval following the turn-off delay time, where the drain-
source voltage rises from 10 % to 90 % of its end value VDD. During this time, the drain current
will fall accordingly (therefore fall time), i.e. most of the turn-off losses are generated here.
The sum of turn-off delay time td(off) and fall time tf is called turn-off time toff.
As the drain current ID will not have dropped to cut-off current level at the defined end of toff, but
still amounts to 10 % of its forward on-state value, there will still be higher losses after toff than
the blocking losses.
Internal thermal resistance junction to case Rthjc per MOSFET

The thermal resistance Rthjc describes the passage of heat between the MOSFET chips (index j)
and the module case (index c). It characterizes the static heat dissipation of a MOSFET system
within a module (mostly consisting of paralleled chips) and depends on chip size and module
assembly.
The temperature difference Tjc between chip temperature Tj and case temperature Tcase at a
constant power dissipation P is defined as follows: Tjc = Tj - Tcase = P * Rthjc.
Contact thermal resistance case to heatsink Rthch per MOSFET module

The thermal resistance Rthch describes the passage of heat between the module case (index c) and
the heatsink (index h). It characterizes the static heat dissipation of a MOSFET module (possibly
with several MOSFET switches) and depends on module size, heatsink and case surfaces,
thickness and parameters of thermal layers (pastes, foils, print covers) between module and
heatsink as well as on the mounting torque of the fixing screws.
The temperature difference Tch between case temperature Tc and heatsink temperature Th at a
constant total amount of single power dissipations Pn within the module is defined as follows:
Tch = Tcase - Th= Pn * Rthch.
Separate determination of Rthjc and Rthch is not possible for modules without base plate (e.g.
SEMITOP, SKiiPPACK, MiniSKiiP). For these module, Rthjh is indicated per MOSFET and per
module. The temperature differences may be calculated in analogy.
104
Mechanical data
Apart from the case construction type, the following mechanical data are usually indicated in
the datasheets:
Mounting torque M1 of the fixing screws (minimum and maximum value) in Nm or lb.in.;
Mounting torque M2 of the output terminals (minimum and maximum value) in Nm or lb. in.;
Weight w of the module in g;
Permissible acceleration under vibration a in m*s-2.
Free-wheeling diodes/ inverse diodes

Inverse diode forward voltage (negative source-drain voltage) VSD, VF
Negative source-drain voltage drop with gate-source short-circuited (VGS = 0). VSD describes the
forward characteristics of the parasitic inverse diodes of the MOSFETs or the hybrid free-
wheeling diodes, which are antiparallel to the MOSFETs.
Parameters: forward current IF; case temperature Tcase = 25C
Threshold voltage of the inverse diode V(T0)

Forward slope resistance of the inverse diode rT
With the help of threshold voltage and forward slope resistance a simplified approximation of
the forward characteristic may be produced. The threshold voltage indicates the point of
crossover with the voltage axis, the forward slope resistance determines the rate of rise of the
characteristic.
Reverse recovery time of the inverse diode trr

Reverse recovery time of the internal or hybrid MOSFET inverse diode during free-wheeling
operation, i.e. when a high drain current -ID = IF is commutated with a high diF/dt and a high
reverse voltage VR = VDD.
Note: trr depends very strongly on the temperature (almost doubled value between 25C and
Parameters: forward current IF; reverse voltage VR, rate of fall of forward current -diF/dt, chip
temperature Tj = 25C und 150C.
Recovered charge of inverse diode Qrr

Recovered charge of internal or hybrid MOSFET inverse diode during free-wheeling operation,
i.e. when a high drain current -ID = IF is commutated with a high diF/dt and a high reverse
voltage VR = VDD.
Note: Qrr depends very strongly on the temperature (initial value may be doubled or even
increased eight-fold between 25C and 150C).
temperature Tj = 25C and 150C.
105
2.2.3 Diagrams
Following the sequence of the datasheets, this chapter will give some hints concerning MOSFET
datasheet diagrams. In the case where the diagram concerned is detailed in other chapters, this
will be referred to.
Rated power dissipation PD of a MOSFET module versus case temperature Tcase
Figure 2.2 Rated power dissipation
Based on the rated power dissipation per MOSFET PD(25C) = (Tjmax 25C)/Rthjc which is limited
to Tcase = 25C per definition, the function depicted in the diagram describes derating at a higher
case temperature.
Maximum safe operating area during pulse operation (SOA)

As explained in chapter 1.2.3 the MOSFET has to manage an almost rectangular characteristic
i = f(u) between VDD and IL in the case of hard switching.
The SOA (Safe Operating Area)-diagrams indicate to what extent this may be realized during
different operations without risk of destruction:
The SOA is terminated by the following parameters:
- maximum drain current (horizontal termination);
- maximum drain-source voltage (vertical termination);
- maximum power dissipation or chip temperature (diagonal broken termination line in Figure
2.3);
- turn-on resistance (diagonal continuous termination line).
Figure 2.3 shows the maximum curve ID = f(VD) during switching and on-state for different
pulse durations tp at a double logarithmic scale.
It is important that the maximum ratings are valid at a case temperature Tc = 25C and for single
pulses, which will not heat the MOSFET over the maximum chip temperature Tj = 150.
Although the lowest of the depicted diagonals represents the hyperbola of the maximum
stationary power losses Ptot, MOSFET modules may only touch the linear characteristic area
during switching operation. Analogous operation over a longer period of time is not permitted,
since asymmetries due to spreading among the chips as well as negative temperature coefficients
of the threshold voltages might cause thermal instability.
106
Figure 2.3 Maximum safe operating area ID = f(VDS) during pulse operation (SOA)
Forward output characteristic ID = f(VDS)

Figure 2.4 shows the output characteristic (typical values) with parameter VGS (also see chapter
1.2.2.1).
Figure 2.4 Typical MOSFET output characteristic ID = f(VDS) with parameter VGS
Transfer characteristic ID = f(VGS)

The transfer characteristic (Figure 2.5) describes the behaviour of the MOSFET in the active
operating area at VDS = 25 V (linear operation). The drain current is coupled with the gate-source
voltage via ID = gfs * (VGS-VGS(th)).
107
Figure 2.5 Typical transfer characteristic ID = f(VGS)
On-resistance versus chip temperature

see chapter 2.6
Drain current derating versus case temperature

see chapter 2.6
Drain-source breakdown voltage versus temperature

As shown in Figure 2.6 the drain-source breakdown voltage of a MOSFET increases linearly to
the temperature. As the maximum rating indicated in the datasheets refers to Tj = 25C, deratings
at low chip temperatures have to be accepted .
Figure 2.6 Drain-source breakdown voltage V(BR)DSS versus Tj
108
Drain-source voltage derating versus rate of fall of drain current

see chapter 3.1.1
Internal capacitances versus collector-emitter voltage

see chapter 1.2.3
Gate charge characteristic

see chapter 1.2.3
Diode forward characteristic

see chapter 1.2.2.1
On-resistance versus drain current

Figure 2.7 explains the relationship between on-resistance RDS(on) and drain current ID or gate-
source voltage VGS for a fully controlled MOSFET.
Figure 2.7 Typical characteristic of on-resistance RDS(on) versus drain current ID and gate-source voltage VGS
The on-resistance decreases with increase of the gate-source voltage. At any point of the curve, a
slight increase of RDS(on) together with the drain current has to be considered.
Gate-source threshold voltage versus temperature

Figure 2.8 shows three curves with typical and limit values characterizing the relationship
between gate-source threshold voltage VGS(th) and MOSFET chip temperature Tj.
109
Figure 2.8 Gate-source threshold voltage VGS(th) versus temperature
VGS(th) will decrease linearly when Tj increases. The temperature coefficient of the threshold
voltage amounts to about 10 mV/K within the temperature range of -50...+150C.
Transient thermal impedances for IGBTs and free-wheeling diodes

see chapter 3.2
2.3 IGBT-modules [264], [265]
2.3.1 Maximum ratings
IGBTs/ module structure

Collector-emitter voltage VCES or VCE
Maximum collector-emitter voltage with gate-emitter short-circuited (VGE = 0)
Collector-gate voltage VCGR

Maximum collector-gate voltage,
Parameters: external gate-emitter resistance RGE; case temperature Tcase = 25C
Continuous collector current IC

Maximum direct current at collector output
Parameter: case temperature, e.g. Tcase = 25C, 80C: IC@25C, IC@80C
Peak value of a periodic collector current ICM or pulsed collector current ICpuls
Peak value of current at collector output during pulse operation
Parameters: pulse duration tp, case temperature, z.B. Tcase = 25C, 80C and pulse/ break ratio
Gate-emitter voltage VGES or VGE

Maximum gate-emitter voltage
110
Total power dissipation Ptot

Maximum power dissipation per transistor/ diode or within the whole power module
Ptot = (Tjmax-Tcase)/Rthjc,
Operating temperature range Tvj or Tj ; Tj(min)....Tj(max)

Permissible chip temperature range within which the module may be permanently operated.
Storage temperature range Tstg; Tstg(min)....Tstg(max) )

Temperature range within which the module may be stored or transported without being subject
to electrical load.
Isolation test voltage Visol or Vis

Effective value of the permissible test voltage between input terminals/ control terminals (short-
circuited, all terminals connected to each other) and module base plate.
Parameters: test duration (1 min, 1 s), rate of rise of test voltage, if required;
according to IEC 146-1-1 (1991), EN 60146-1-1 (1993), section 4.2.1 (corresponds to VDE
0558, volume 1-1: 1993-04) and DIN VDE 0160 (1988-05), section 7.6 (corresponds to EN
50178 (1994)/ E VDE 0160 (1994-11) the test voltage shall only rise gradually up to its
maximum rating.
Grade of humidity
describes the permissible ambient conditions (atmospheric humidity) according to DIN 40 040
Grade of climate
describes the permissible ambient test conditions (climate) according to DIN IEC 68-1
Inverse diodes/ free-wheeling diodes

Forward current IF
Maximum forward current value of the inverse or free-wheeling diodes,
Parameter: case temperature, e.g. Tcase = 25C, 80C
Peak periodic forward current IFM or pulsed forward current IFpuls

Peak value of the diode current during pulse operation
Parameters: pulse duration tp, case temperature, e.g. Tcase = 25C, 80C
2.3.2 Characteristics
IGBTs/ module structure

Collector-emitter breakdown voltage V(BR)CES
Breakdown voltage between collector and emitter, gate-emitter short-circuited (VGE = 0),
Parameters: collector blocking current IC, case temperature Tcase = 25C
Gate-emitter threshold voltage VGE(th)

Gate-emitter voltage above which considerable collector current will flow
Parameters: collector-emitter voltage VCE = VGE, collector current IC, case temperature
Tcase = 25C
111
Collector-emitter cut-off current ICES

Collector-emitter blocking current with gate-emitter short-circuited (VGE = 0) and collector-
emitter voltage VCE = VCES
Parameter: chip temperature, e.g. Tj = 25C and 125C
Gate-emitter leakage current IGES

Leakage current between gate and emitter with collector-emitter short-circuited (VCE = 0) and at
maximum gate-emitter voltage VGE
Parameter: gate-emitter voltage VGE, case temperature Tcase = 25C
Collector-emitter saturation voltage VCEsat

Saturation value of collector-emitter voltage (on-state voltage drop of the active IGBT) at a
specified collector current IC (at rated current, see chapter 2.3.3, or at maximum collector
current). For PT-IGBTs VCEsat will drop proportionally to the temperature within rated current
range, for NPT-IGBTs, however, it will rise proportionally to the temperature.
Parameters: collector current IC, gate-emitter voltage VGE, chip temperature, e.g. Tj = 25C and
125C.
For calculation of forward on-state losses the following parameters are often indicated
additionally in the datasheets: VCE(TO) (static collector-emitter threshold voltage) and rCE (on-
state slope resistance) of a substitutional straight line.
VCEsat = f(IC) = VCE(TO) + rCE * IC
This means that, for calculation, the saturation voltage characteristic is approximated by means
of a diode characteristic.
Forward transconductance gfs

Quotient of changing collector current and gate-emitter voltage at a specified collector current IC,
Parameters: collector-emitter voltage VCE, collector current IC (rated current, resp.),
case temperature Tcase = 25C
Capacitance chip-case CCHC

Capacitance between a sub-component and case base plate or heatsink potential
Input capacitance Ciss

Capacitance between gate and emitter with collector-emitter short-circuited for AC and gate-
emitter voltage VGE = 0.
Parameters: collector-emitter voltage VCE, measuring frequency f, case temperature Tcase = 25C
Output capacitance Coss

Capacitance between collector and emitter with gate-emitter short-circuited (VGE = 0).
Reverse transfer capacitance (Miller capacitance) Crss, Cmi

Capacitance between collector and gate with collector-emitter short-circuited for AC and gate-
emitter voltage VGE = 0. For measuring the emitter has to be connected with the protective shield
of the measuring bridge.
112
Parasitic collector-emitter inductance LCE

Inductance between collector and emitter
Switching times
More related to practice than switching times of MOSFETs, switching times of IGBTs indicated
in the datasheets are determined from a measuring circuit under ohmic-inductive load according
to Figure 2.9a. The load time constant L/R is high compared to the switching frequency cycle
duration T = 1/f, so that an continuous load current is generated by the load inductance.
Just as with MOSFETs, switching times of IGBTs refer to the gate-emitter characteristics during
turn-on and turn-off, see Figure 2.9b.
Switching times as well as real current and voltage characteristics are determined by internal and
external capacitances, inductances and resistances of the gate and drain circuit; for this reason,
all indications in the datasheets and the characteristics depicted therein may only serve as a
guide.
R
+15 V
L
IL
iC
VGG+ RGon VCC
vCE
vGE
RGoff
0V Ex
E
VGG-
-15 V a)
113
vGE
vGE
VGG+ 90%
10%
t
VGG-
idealized waveform
iC
IL 90% IL 90% IL
10% IL 10% IL
td(on) tr td(off) tf t
ton toff
vCE
VCC
t
Turn-on Turn-off b)
Figure 2.9 a) Measuring circuit

b) Definition of IGBT switching times under ohmic-inductive load [264],[265]
The following parameters are indicated in the datasheets relevant to switching times:
measuring circuit, collector-emitter supply voltage VCC, gate-emitter control voltages VGG+, VGG-
or VGE, collector current IC, external gate series resistors RGon ,RGoff (resistance of control circuit
at turn-on and turn-off), chip temperature Tj = 125C
Turn-on delay time td(on)

As already mentioned, the total forward on-state current of the IGBT is to be conducted by the
load inductance before turn-on.
After sudden turn-on of a positive gate-emitter control voltage, the gate-emitter voltage VGE
starts to rise with a time constant determined by IGBT input capacitance and gate resistance. As
soon as the threshold voltage VGE(th) has been reached, the collector current IC will start to rise.
The turn-on delay time td(on) is defined as the time interval between the moment when the gate-
emitter voltage vGE has reached 10 % of its end value, and the collector current iC has increased
to 10 % of the load current.
Rise time tr
The rise time tr is defined as the time interval following the turn-on delay time, where the
collector current iC increases from 10 % to 90 % of the load current. During this time interval
most of the turn-on losses are generated in the IGBT, since a certain share of IL is continuously
conducted through the free-wheeling diode as long as the iC-value is below load current IL.
114
Therefore, the collector-emitter voltage vCE will not drop significantly below the collector-
emitter supply voltage VCC.
The difference between VCC and vCE depicted in Figure 2.9b during tr is basically determined by
the transient voltage drop over the internal parasitic inductances of the commutation circuit.
The sum of turn-on delay time td(on) and rise time tr is called turn-on time ton.
As the collector-emitter voltage vCE will not yet have reached its forward on-state value VCEsat at
the (defined) end of ton, the major share of the switching losses will be generated after ton.
Turn-on peak current: after the total load current IL has been commutated to the IGBT, the
free-wheeling diode will block, releasing its recovered charge Qrr at the same time. Therefore,
the IGBT collector current iC will rise during reverse recovery of the free-wheeling diode (trr) by
the value of the peak reverse recovery current IRRM over IL (turn-on peak current see Figure
2.10).
iC (20 A / Div)
vCE (200 V / Div)
vGE (20 V / Div)
0,2 s / Div
Figure 2.10 Commutation from the conducting free-wheeling diode to the IGBT (turn-on peak current) during
turn-on of an IGBT
Dynamic saturation voltage: after having dropped very steeply during turn-on time, the
collector-emitter voltage vCE will decline relatively slowly (within s-range) to its static value
VCEsat. This dynamic saturation phase is necessary for flooding the wide n--zone of the IGBT
with (bipolar) minority carriers (conductivity modulation).
115
Turn-off delay time td(off)

After sudden turn-off of the positive control voltage and turn-on of a negative gate-source
control voltage, the gate-source voltage VGS starts to decline with the time constant determined
by the input capacitance of the IGBT and the gate resistance. The collector-emitter voltage vCE of
the IGBT begins to rise. The IGBTs collector current iC cannot drop considerably at that time,
since the free-wheeling diode is poled in reverse direction as long as VCC is higher than vCE and,
therefore, is not able to take over load current IL.
Due to this, the turn-off delay time td(off) for IGBTs is defined as the time interval between the
moment when the gate-emitter voltage vGE has dropped to 90 % of its turn-on value and the
collector current has declined to 90 % of the load current value.
Fall time tf
As soon as the collector-emitter voltage vCE has exceeded the supply voltage VCC during turn-off
of the IGBT, the load current may commutate to the free-wheeling diode, which is poled in
forward direction at that time and the collector current iC will drop.
The fall time tf is defined as the time interval, where the collector current iC drops from 90 % to
10 % of the load current IL.
The overshoot of vCE over VCC indicated in Figure 2.11 mainly results from the parasitic
inductances of the commutation circuit and increases proportionally to the turn-off speed - diC/dt
of the IGBT.
The turn-off time toff is defined as the sum of turn-off delay time td(off) and fall time tf.
Since iC will not have dropped to cut-off current level at the defined end of toff, but still amounts
to 10 % of the load current, the losses arising after toff will still exceed the blocking losses.
Tail time tt, tail current It

Other than with MOSFETs, the drastic decrease of power losses in IGBTs achieved by the
injection of minority carriers in the n--zone is realized by generation of a tail current It, shown
in Figure 2.11.
The tail time tt is not included in the turn-off time toff per definition, however it contributes to a
significant share of switching losses due to the collector-emitter supply voltage VCC which has
already been applied during that time interval.
116
vCE (200 V / Div)
iC (20 A / Div)
vGE (20 V / Div)
0,2 s / Div
Figure 2.11 Turn-off characteristics of an NPT-IGBT
Energy dissipation during turn-on Eon; energy dissipation during turn-off Eoff per cycle
The typical values of Eon and Eoff of an IGBT are indicated in the diagram turn-on/ turn-off
energy Eon, Eoff as a function of the collector current IC included in the datasheet.
Power dissipation during switching may be calculated by multiplication of the switching
frequency f with Eon or Eoff, respectively: Pon = f * Eon or Poff = f * Eoff.
The turn-on energy dissipation Eon comprises the effects of the reverse peak current of the free-
wheeling diode, which corresponds to the diode integrated in the power module. Energy
dissipation during turn-on may be determined by integration of the power dissipation during
turn-on Pon up to the moment when VCE amounts to approximately 3 % of the collector-emitter
supply voltage VCC.
Apart from the power losses generated during the actually defined turn-off time toff = td(off) + tf,
energy dissipation during turn-off also comprises the tail current losses generated during the tail
time tt up to the moment when the collector current has fallen below load current by 1 %.
Parameters: operating voltage, chip temperature Tj = 125C, control voltages, gate series
resistance.
Thermal resistance junction to case Rthjc per IGBT

The thermal resistance Rthjc describes the passage of heat between the IGBT chips (index j) and
the module case (index c). It characterizes the static heat dissipation of an IGBT system within a
module (mostly consisting of paralleled chips) and depends on chip size and module assembly.
The temperature difference Tjc between chip temperature Tj and case temperature Tcase at a
constant power dissipation P is defined as follows: Tjc = Tj - Tcase = P * Rthjc.
Contact thermal resistance case to heatsink Rthch per IGBT module

The thermal resistance Rthch describes the passage of heat between module case (index c) and
heatsink (index h). It characterizes the static heat dissipation of an IGBT module (possibly with
several IGBT switches) and depends on module size, heatsink and case surfaces, thickness and
parameters of thermal layers (pastes, foils, print covers) between module and heatsink as well as
on the mounting torque of the fixing screws.
117
The temperature difference Tch between case temperature Tc and heatsink temperature Th at a
constant total amount of single power dissipations Pn within the module is defined as follows:
Tch = Tcase - Th= Pn * Rthch.
Separate determination of Rthjc and Rthch is not possible for modules without base plate (e.g.
SEMITOP, SKiiPPACK, MiniSKiiP). For these module, Rthjh is indicated per IGBT and per
module. The temperature differences may be calculated in analogy.
Mechanical data
Apart from the case construction type mainly the following mechanical data are indicated in the
datasheets:
Mounting torque M1 of the fixing screws (minimum and maximum value) in Nm or lb.in.;
Mounting torque M2 of the output terminals (minimum and maximum value) in Nm or lb. in.;
Weight w of the module in g;
Permissible acceleration under vibration a in m*s-2.
Free-wheeling diodes
Inverse diode forward voltage (negative emitter-collector voltage) VEC, VF
Negative emitter-collector voltage drop with gate-emitter short-circuited (VGE = 0).
VEC describes the forward characteristics of free-wheeling diodes, which are connected
antiparallel to the IGBTs.
Parameters: forward current IF; case temperature Tcase = 25C
Threshold voltage of the inverse diode V(T0)

Forward slope resistance of the inverse diode rT
With the help of threshold voltage and forward slope resistance a simplified approximation of
the forward characteristic may be produced. The threshold voltage indicates the point of
crossover with the voltage axis, the forward slope resistance determines the rate of rise of the
characteristic.
Reverse recovery time of the inverse diode trr

Reverse recovery time of the IGBT inverse diode during free-wheeling operation, i.e. when a
high collector current -IC = IF is commutated with a high diF/dt and a high reverse voltage
VR = VCC.
Note: trr is very strongly dependent on the temperature (almost doubled value between 25C and
150C).
Recovered charge of inverse diode Qrr

Recovered charge of IGBT inverse diode during free-wheeling operation, i.e. when a high
collector current -IC = IF is commutated with a high diF/dt and a high reverse voltage VR = VCC.
Note: Qrr is very strongly dependent on the temperature (initial value may be doubled or even
increased eight-fold between 25C and 150C).
118
Thermal resistance junction to case Rthjc per diode

The thermal resistance junction to case Rthjc describes the passage of heat between diode chips
(index j) and module base plate (index c).
2.3.3 Diagrams
Following the sequence of the datasheets, this chapter will give some hints concerning IGBT
datasheet diagrams. In cases where the diagram concerned is detailed in other chapters, this will
be referred to.
Maximum total power dissipation Ptot of IGBT module versus case temperature Tcase
Figure 2.12 Maximum total power dissipation
Based on the maximum total power dissipation per IGBT (or per free-wheeling diode)
Ptot(25C) = (Tjmax 25C)/Rthjc which is limited to Tcase = 25C per definition, the function
depicted in the diagram describes derating at a higher case temperature.
119
Turn-on/ turn-off energy Eon, Eoff per pulse of an IGBT as function of the collector current
IC
Figure 2.13 Turn-on/ -off energy dissipation as function of IC
The turn-on/-off energies Eon, Eoff determined from a measuring circuit under ohmic-inductive
load are indicated versus different collector currents IC (e.g. chip temperature Tj = 125C,
collector-emitter supply voltage VCC = 600 V) with specified control parameters.
Switching losses may be determined by multiplying dissipation energy and switching frequency
f:
Pon = f * Eon Poff = f * Eoff.
Eon and Eoff are indicated for IGBT at rated current (Ic@ Tcase = 80C) in the characteristic values
of the datasheet.
Turn-on and turn-off energy Eon, Eoff per pulse of an IGBT as function of the gate series
resistors RG (RGon, RGoff)
see chapter 3.5.2
Maximum safe operating area during switch operation (SOA)

As explained in chapter 1.2.3 the IGBT has to manage an almost rectangular characteristic
i = f(u) between VCC and IL in case of hard switching.
The SOA (Safe Operating Area)-diagrams indicate to what extent this may be realized during
different operations without risk of destruction:
- SOA for switching, on-state and single pulse operation
- RBSOA (Reverse Biased SOA) for periodic turn-off
- SCSOA (Short Circuit SOA) for non-perdiodic turn-off of short circuits (chapter 3.6.2)
The SOA is limited by the following parameters:
- maximum collector current (horizontal limit);
- maximum collector-emitter voltage (vertical limit);
- maximum power dissipation or chip temperature (diagonal limits) see Figure 2.14;
Maximum safe operating area during pulse operation (SOA)

Figure 2.14 shows the maximum curve IC = f(VCE) during switching and on-state for different
pulse durations tp at a double logarithmic scale.
120
It is important that the maximum ratings are valid at a case temperature Tc = 25C and for single
pulses, which will not heat the IGBT over the maximum chip temperature Tj = 150.
Although the lowest of the depicted diagonals represents the hyperbola of the maximum
stationary power losses Ptot, IGBT modules may only touch the linear characteristic area with
approximately VCE > 20 V or VGE < 9 V during switching operation. Analogous operation over a
longer period of time is not permitted, since asymmetries due to variation among the chips as
well as negative temperature coefficients of the threshold voltages might cause thermal
instability.
Figure 2.14 Maximum safe operating area IC = f(VCE) during pulse operation (SOA)
Turn-off safe operating area

Figure 2.15 shows the turn-off safe operating area of an IGBT.
Figure 2.15 Turn-off safe operating area (RBSOA)
121
During periodic turn-off the IGBT may effect a hard turn-off of ICM@80C = TC for Tjmax and
defined driver parameters, provided that vCE (chip) has reached VCES-level (influence of parasitic
inductances and driver parameters, see chapters 3.4.1 and 3.5.2).
Safe operating area at short circuit

see chapter 3.6.2
Derating of collector current versus case temperature

see chapter 2.6; analogous to Figure 2.23b
Forward output characteristic IC = f(VCE)
Figure 2.16 shows the output characteristics for Tj = 25C and 125C (typical values) with
parameter VGE, also see chapters 1.2.2.2 and 2.6.
a) b)
Figure 2.16 Typical IGBT output characteristic IC = f(VCE) with paramter VGE
a) Tj = 25C b) Tj = 125C
Transfer characteristic IC = f(VGE)

The transfer characteristic (Figure 2.17) describes the behaviour of the IGBT within the active
area at VCE = 20 V and tp = 80 s (linear operation). The collector current is coupled with the
gate-emitter voltage via transfer transconductance: IC = gfs * (VGE-VGE(th)).
122
Figure 2.17 Typical transfer characteristic IC = f(VGE)
Gate charge characteristic

see chapter 1.2.3
Internal capacitances versus collector-emitter voltage

see chapter 1.2.3
Switching times versus collector current

Figure 2.18 shows typical dependencies of switching times td(on) (turn-on delay time), tr (rise
time), td(off) (turn-off delay time) and tf (fall time) on the collector current IC during hard
switching of inductive loads.
Figure 2.18 Typical dependency of switching times on collector current (inductive load)
The slightly overproportional increase of tr verifies that diC/dt does not increase to the same
extent as IC when the collector current rises.
123
Switching times versus gate resistor

see chapter 3.5.2
CAL diode forward characteristic

see chapter 1.3.1.1
Diode turn-off energy dissipation

Figure 2.19 demonstrates the dependency of the diode turn-off energy EoffD on the diode current
IF conducted before turn-off, and on the turn-on speed of the IGBT determined by gate resistance
RG, during current commutation between free-wheeling diode and IGBT (hard switching).
Figure 2.19 Diode turn-off energy dissipation EoffD versus collector current IC and gate resistance RG
As expected, the diode turn-off losses increase with the forward current as well as with the rate
of rise of commutation current due to a simultaneous rise of storage charge and reverse current
amplitude (see chapter 1.3.1.3).
Transient thermal impedances of IGBT and free-wheeling diode

see chapter 3.2.2.3
Free-wheeling diode reverse recovery current as function of forward on-state current

Figure 2.20 shows typical values of the peak reverse recovery current IRRM versus forward
current IF and di/dt determined by the gate resistance RG = RGon.
124
Figure 2.20 Typical peak reverse recovery current IRRM of free-wheeling diode versus IF and RG
As expected, the peak reverse recovery current is higher, the faster the IGBT is switched on
(low RGon).
At first, the reverse recovery current will increase together with rising forward current. If high
collector currents are applied, the share of charge carriers in the CAL-diode drift area, which
already re-combine during commutation, will increase with the duration of commutation;
therefore, IRRM will again drop in the high current range.
Free-wheeling diode reverse recovery current as function of diF/dt

Figure 2.21 depicts the typical dependency of the free-wheeling diode reverse recovery current
IRRM on di/dt, determined by control of the given gate resistances RG = RGon of the IGBT on the
measuring conditions indicated.
Figure 2.21 Typical free-wheeling diode reverse recovery current IRRM versus di/dt and RG
The reverse recovery current increases almost linearly to di/dt.
125
Free-wheeling diode recovered charge as function of diF/dt

Figure 2.22 shows the typical dependency of the free-wheeling diode recovered charge Qrr on
di/dt for different collector currents IC. In addition, the gate resistances RG = RGon have been
entered which determine the given di/dt on the measuring conditions indicated.
Figure 2.22 Typical free-wheeling diode recovered charge versus di/dt, RG and IC
Just like the reverse recovery current, the free-wheeling diode recovered charge will rise together
with the collector current and di/dt. The rate of rise will be more distinct for high collector
currents than for the low current range.
Rated collector current at short circuit as a function of gate-emitter voltage and

temperature
see chapter 3.6.2
2.4 Special parameters for MiniSKiiPs

Apart from IGBTs and diodes for inverters and brake choppers diodes (or thyristors) for input
rectifiers are also integrated in the MiniSKiiP.
Supplementary to forward and blocking characteristics (maximum ratings, characteristics), the
follwing parameters are specified for MiniSKiiPs:
Rectifier diode surge forward current IFSM

Peak value of a sinusoidal wave 50 Hz, which the diode is able to withstand without being
damaged in the case of breakdown, if this does not occur too often.
Rectifier diode peak load integral i2dt

Reference parameter for the selection of fuses to be calculated as follows:
i2dt = IFSM2 * T/4 = 5*10-3s * IFSM2 (@ f = 50 Hz)
Resistance/ temperature coefficient of the temperature sensor
Features of current sensors
126
2.5 Special parameters for SKiiPPACKs

SKiiPPACK datasheets have to include for example:
- static/dynamic maximum ratings and characteristics of IGBT and free-wheeling diode chips;
- thermal characteristics (including heatsink);
- indications on isolation voltage of module and of all potential separations;
- indications on threshold values of protective function;
- input level, output performance and delay times of the driver and
- indications on features related to mechanical stress and climate conditions.
Therefore, SKiiPPACK datasheets are much more complex, although, on the other hand, all
indications concerning the dependency of parameters on different driver conditions may be
ignored.
2.6 Temperature dependency of static and dynamic characteristics of

power modules
Almost all electrical characteristics of IGBTs, power MOSFETs and free-wheeling diodes are
more or less dependent on the chip temperature.
The following table reflects the characteristic tendencies of the most important component
parameters at rising temperature (<: rises; <<: rises steeply; >: falls; -: no notable temperature
dependency).
The special features marked with * are only valid for PT-IGBTs.
For dimensioning in practice, the parameters marked with !, which will be detailed later on, are
of main importance due to their distinct dependency on the temperature. For the temperature
dependency of the parameters of free-wheeling diodes please refer to the explanations under
chapter 1.3.
Parameter MOSFET IGBT Free-wheeling diode

Avalanche breakdown voltage < < <
Blocking current, blocking power dissipation < < <
Turn-on resistance/forward on-state voltage, <<! <(>*)! >
forward power dissipation
Turn-on time/energy dissipation during turn-on < < -
Turn-off time/energy dissipation during turn-off < <(<<*)! <<
Threshold voltage > > >
Forward transconductance > > -
For the interpretation of the parameters indicated in the datasheets it should be taken into
consideration that many ratings for power MOSFETs and IGBTs are related to a case
temperature of 25C and have still to be converted to the maximum operating temperature by
means of other indicated parameters.
This goes mainly for the maximum permissible drain or collector current ID, IDM, IC, ICM and the
maximum power dissipation Ptot or PD, respectively, which have to be reduced to ratings under
realistic operating conditions as described in chapter 3.1.2.
The required current reduction is determined by the forward and blocking power dissipations
which are also temperature-dependent, as well as by the switching losses.
127
The fact that blocking current and blocking power dissipation will increase by factor 3...6
between 25C and 125C is of only minor importance for dimensioning, because the blocking
power dissipation contributes to only a small share of total power dissipation.
In contrast to this, the forward on-state temperature dependency is of major importance, which,
therefore, shall be examined separately for the single components:
Power MOSFET
Figure 2.23 shows the increasing on-resistance RDS(on) of a power MOSFET and the resulting
over-proportional derating of the continuos drain current ID at higher temperatures with an
example.
a) b)
Figure 2.23 Forward on-state behaviour of a 100 V power MOSFET versus temperature
a) On-resistance RDS(on) b) Continuous drain current ID derating
RDS(on) is doubled within the operating temperature range of 25...150C; at Tcase = 80C only
75 % of the maximum drain current ID can be utilized even under static conditions.
On the other hand, the positive temperature coefficient of the forward on-state voltage offers
advantages such as simplified paralleling ability and high resistivity during hard switching.
IGBT
The various concepts of IGBTs (PT/NPT, see chapter 1.2.1) also differ in their thermal
behaviour.
This is explained in Figure 2.24 with the basic characteristic of the collector-emitter saturation
voltage VCEsat over the collector current IC at a chip temperature of 25C and 125C.
128
IC[A] 160 IC[A] 160

25C 125C 25C 125C
140 140
120 120
100 100
80 80
60 60
40 40
20 20
0 0
0 1 2 3 4 5 0 1 2 3 4 5
VCE [V] @VGE = 15 V VCE [V] @VGE = 15 V
a) b)
Figure 2.24 Forward characteristics of IGBTs

a) SEMITRANS NPT-IGBT 100A@25C b) PT-IGBT 100A@25C
The temperature coefficient of the forward on-state voltage VCEsat of the NPT-IGBT is positive
for the whole current (approx. 8 mV/K at IC@25C). The temperature coeffcient of VCEsat of the
PT-IGBT, however, is negative for the actually utilized forward current range and rises to zero
only when rated current has been approximated.
The resulting consequences for NPT-IGBTs compared to PT-IGBTs are higher forward power
dissipation on the one hand, and a better current symmetry on the other hand (homogeneous
temperature spreading/ ruggedness, unselected paralleling ability).
The IC-derating characteristic versus temperature analogous to Figure 2.22b is included in the
IGBT-datasheets as well.
As already mentioned, MOSFET and IGBT switching times and switching losses will also
increase when the temperature rises.
However, since dimensioning for hot chips has to be done in practice anyway, most ratings
included in the current datasheets are taken at 125C .
In this respect, another difference between NPT- and PT-IGBTs should be referred to (Figure
2.25, see chapters 1.2.1 and 1.2.3)
129
vCE (200 V / Div)

vCE (200 V / Div)
iC (20 A / Div) iC (20 A / Div)
vGE (20 V / Div)

vGE (20 V / Div)
0,2 s / Div 0,2 s / Div
a) b)
Figure 2.25 Turn-off behaviour of IGBTs

a) SEMITRANS NPT-IGBT b) PT-IGBT
The tail current It generated during turn-off will increase together with the temperature. Whereas
the tail current of an NPT-IGBT will have risen by almost 100 % at 125C compared to 25C
(Figure 2.25a), the tail current of PT-IGBT (Figure 2.25b) will be almost tripled within this
temperature range. This results in clearly reduced switching losses of NPT-IGBTs at high
temperatures compared to PT-types.
The minor temperature dependency of threshold voltage and forward transconductance has
practically no importance for switching operation. But it is a basic restriction to linear operation
of power modules.
2.7 Reliability
Reliability, i.e. maintaining the promised characteristics over a defined period of time, is one of
the most important quality features of power modules.
On the one hand, power modules are outstanding for their high electrical and thermal efficiency;
on the other hand, premature failure may cause danger, direct and consequent damage and, last
but not least, high costs.
Reliability is very difficult to express due to comparably small lots, often extreme long life
requirements (10...30 a) and complex test specifications, but may be defined by
- exact control of all influences on production processes (built-in reliability),
- reliability testing under conditions very close to the application in order to discover typical
failure mechanisms,
- testing of the components within the system and control of the most important parameters.
[231]
Some selected tests for power modules are shown in the following without going into details of
the extensive EN ISO 9001 quality assurance system, based on which SEMIKRON is able to
grant a 2 year TQM warranty on all its power semiconductors.
130
The following standard tests are being carried out for release and re-qualification of MOSFET
and IGBT modules still to become finalised by further, individual product-specific reliablity
testing:
Test Standards Test conditions

High temperature blocking voltage DIN 41749, IEC 147-4 1.000h, VDSmax, VCEmax, Tjmax
(HTRB)
Hot gate stress DIN 45930, CECC 50000-4, 5.2 1.000h, VGSmax, VGEmax, Tjmax
High temperature storage DIN 45930, CECC 50000-4, 4.3 1.000h, Tstgmax
Low temperature storage 1.000h, Tstgmin
Humidity temperature blocking DIN 45930, CECC 50000-4, 4.3 1.000h, 85C, 85 % relative humidity.
VCE, VDS = 0.8 VCEmax, VDSmax ; 80 V
Temperature cycling DIN IEC 68-2-14-test Na 100 temperature cycles Tstgmax/Tstgmin
Power cycling DIN 41794, IEC 147-4 20.000 cycles, Tj=100 K
Solder temperature DIN IEC 68-2-20, test Tb 2605C, 101 s
Solderability DIN IEC 68-2-20, test Ta 2355C, aging 3
Vibration/ acceleration acc.to DIN IEC 68-2-6,test Fc 5g
The following failure criteria according to standard MIL-STD-19500 are valid:

Gate-drain-/gate-emitter leakage current IGSS, IGES: > 20 nA or >100 % of initial rating
Zero gate voltage drain current or
collector-emitter cut-off current IDSS, ICES: > 100 A or >100 % of initial rating
(max. 2x of specified max. rating)
On-resistance/forward voltage RDS(on), VCEsat: > 120 % of initial rating
max. change of threshold voltage VGS(th), VGE(th): > 20 % of initial rating
Thermal resistance junction to case Rthjc: > 120 % of initial rating
Isolation test voltage Visol: < specified maximum rating
Figure 2.26 and Figure 2.27 show examples for test procedures depicting measuring circuits and
procedures for temperature cycling and power cycling.
Temperature versus time of DUT in

temperature cycling test
Tmax
Tmax
DUT
T [C]
Tmin
SEMIKRON standards:
-55/+150C
Tmin/Tmax =
-40/+125C Tmin
- maximum storage temperatures
- cycle time depending on thermal load
0 60 120 180
t [min]
Figure 2.26 Temperature cycling: measuring circuit and measuring procedure
131
SEMIKRON-THERM-SIM
Tjunction,max
DUT
Tcase Tcase,max
SEMIKRON standards:
heating and cooling time usually
controlled by Tcase
(alternatively time-controlled)
Tcase,min = 40C
Tjunction,max = 150C Tcase,min
1 cycle 60 seconds
0s 10s 20s 30s 40s 50s 60s 70s 80s 90s

Time
Figure 2.27 Power cycling: measuring circuit and measuring procedure
Principal characteristics of power modules related to reliability may be checked by means of

temperature and power cycling testing, see also chapter 1.4.2.4. Therefore, these tests are of
decisive importance for the qualification of modules.
132
3 Hints for application

3.1 Dimensioning and selection of MOSFET, IGBT and SKiiPPACK
modules
The selection of power modules for any static or short-term (overload) operating conditions of a
concrete application is subject to the consideration of
- voltage capacitance,
- current carrying capacity under realizeable cooling conditions and with reference to the
switching frequency and
- safe operating areas (SOA).
Under no circumstances that might occur during any static or dynamic operation must the
maximum ratings for blocking voltage (except for avalanche-proof MOSFETs), peak current,
junction temperature and safe operating area (see chapter 2.7) indicated in the datasheets be
exceeded. The same goes for the limit values of module case parameters (e.g. isolation voltage,
vibration strength, climate persistence, assembly instructions).
For the sake of high reliability and long life, modules have to be designed for managing a
specified number of switching cycles, which usually go along with considerable temperatures
cycling. (Chapters 1.4.2.4 and 3.2.3).
Furthermore, serious dimensioning will not presuppose total thermal utilization of the
semiconductors to their maximum ratings Tj(max) (e.g. 150C) in order to keep a margin for
theoretically unforeseeable cases and to be able to fall back upon the static and dynamic
characteristics taken at a maximum of 125C and guaranteed by the manufacturers.
As already explained in chapter 2.6, the most important characteristics of power modules will
deteriorate when the temperature rises. For this and other reasons, the determination of the
maximum operating temperature has to be paid special attention to.
3.1.1 Forward blocking voltage

Since most power modules are applied in DC-voltage links, which are AC-voltage supplied via
single-phase or three-phase rectifier bridges, the blocking voltages of universally applied IGBTs
(600 V, 1200 V, 1700 V) are adjusted to common line voltage levels; the same goes for highly
blocking MOSFET-modules.
Therefore, firstly a rough selection is made from line voltage (control angle 0 for controlled
rectifiers) VN or no-load direct voltage Vdi as follows:
VN/V rectification Vdi/V VDSS, VCES/V

24 B2 22 50
48 B2 44 100
125 B2 110 200
200...246 B2 180...221 500, 600
400...460 B6 540...621 1200
575...690 B6 777...932 1700
...1000... B6 1500 3300
133
Afterwards, it has to be checked whether on condition of utmost voltage capacitance, i.e.

- maximum stationary input voltage (nominal voltage + line voltage tolerance, e.g. 15 %),
- transient line overvoltage, as far as it has not yet been reduced by line filters, DC-link
capacitors and circuits on the DC-side (suppressor diodes, snubbers, varistors),
- turn-off overvoltage Vd + V
the maximum module voltage will be exceeded with
V = L * Imax/tf
with parameters as follows:
L: parasitic commutation inductance, see chapters 1.4.2.5 and 3.4.2,
Imax: maximum turn-off collector or drain current (mostly with active short-
circuit turn-off, see chapter 3.6),
tf: fall time of collector or drain current.
Here, special attention has to be paid to the fact that the maximum rating for VDSS/VCES indicated
in the datasheets is related to the characteristics of the transistor chips and not to the dynamic
terminal behaviour of the module. The internal module inductance LCE also indicated in the
datasheets (e.g. 20...30 nH) therefore corresponds to a share of L; the voltage applied to the
chips will exceed the voltage to be taken at the terminals by LCE * I/tf during turn-off.
This is expressed by a diagram in the SEMITRANS MOSFET datasheets, which explains the
derating of the permissible drain-source voltage at the terminals versus the rate of fall of the
drain current diD/dt ID/tf (Figure 3.1).
Figure 3.1 Drain-source voltage VDS derating of a SEMITRANS MOSFET-module SKM 111 A versus drain
current rate of fall diD/dt
3.1.2 Forward current

The maximum continuous drain or collector currents ID or IC, respectively, indicated in the
datasheets as typical currents for module designation and as maximum ratings may be calculated
for a stationary fully controlled transistor at a case temperature Tcase of, for example, 25C or
80C according to the following formula
ID = (T j(max) Tcase ) (R DS(on) R thjc ) (MOSFET-module)
or IC = (Tj(max) - Tcase)/(VCEsat * Rthjc) (IGBT-module)
134
For modules without base plate Th will replace Tcase and Rthjh will replace Rthjc. The ratings for
RDS(on) and VCEsat have been taken at a maximum chip temperature Tj(max).
These indications are only intended to give an orientation aid, since under real operating
conditions switching and (low) blocking losses will occur additionally to the forward on-state
losses, the case temperature will differ and the static maximum ratings of RDS(on) or VCEsat will
not be reached during the whole turn-on procedure.
At a given case temperature (25C, 80C), the peak current values for IDM or ICM are specified
for single pulses with a pulse duration of 1 ms and, at the same time, are designating the
maximum current ratings for periodic turn-on and turn-off (SOAR).
Therefore, the utilizeable forward current is determined

- mainly by the total power dissipation of the transistors and free-wheeling diodes of a power
module and the chip temperatures within the transistors and free-wheeling diodes arising
under specific cooling conditions (Rthca), which must not exceed Tj(max) (chapter 3.2.2),
- by the limits of the maximum safe operating area, see chapters 2.2 and 2.3. To avoid
exceeding the limit values during hard turn-on under ohmic-inductive load, the amount of
load current and reverse recovery current of the free-wheeling diode must not exceed IDM or
ICM, see Figure 3.2. Due to the reasons mentioned in chapter 1.3.1.3 a compromise has to be
found between turn-on speed of the transistor (increase of turn-on losses!) and conductable
load current in most cases.
Further restrictions in practice have possibly to be accepted resulting from the characteristics of
active overcurrent protection in the driver (see chapter 3.5).
3.1.3 Switching frequency

Figure 3.2 shows the measured turn-on and turn-off behaviour of a power MOSFET and an
IGBT module for one specific operating point.
Apart from the characteristics for vDS or vCE and iD or iC also the instantaneous power dissipation
p(t) had been determined by multiplication of instantaneous current and voltage values; the
integral of p(t) reflects the total MOSFET and IGBT losses over the whole period.
To determine total power dissipation of the power module, the losses of the free-wheeling
diode(s) within the module have to be added to the losses in the transistor, see chapter 3.2.1.
135
dv - caused current overshoot +

Avalanche
dt reverse-recovery-current Breakdown
vDS (50 V / Div)
iD (40 A / Div)
vDS (40 V / Div)

iD (10 A / Div)
Pon (1 kW / Div)
Poff (2 kW / Div)
0,1 s / Div Turn-on 0,2 s / Div Turn-off
a)
iC (20 A / Div)
vCE (200 V / Div)
vCE (200 V / Div) iC (20 A / Div)
Pon (20 kW / Div)

Poff (20 kW / Div)
0,2 s / Div Turn-on 0,2 s / Div Turn-off

b)
Figure 3.2 Measured switching processes (hard turn-on and turn-off under ohmic-inductive load)
a) Power-MOSFET module b) IGBT module
For explanations on quality features of current and voltage characteristics please refer to the
remarks on Figure 1.11 in chapter 1.2.3.
The actual limits to the switching frequency are set by the switching losses, because they are
increasing proportionally to the frequency.
Other terminations may be set by the transistor turn-on and turn-off delay times td(on), td(off), the
reverse recovery times of the free-wheeling diodes, the driver output power which increases
proportionally to the frequency and the minimum turn-on, turn-off or dead times necessary for
driver, interlocking, measuring, protection and monitoring functions, see chapter 3.5.1...3.5.4.
If switching losses are to be shifted to passive networks (snubbers) or overvoltages are to be
limited by snubbers, the recharge time of such networks required after low-loss switching has to
be considered as deadtime, see chapters 3.6 and 3.8.
Switching times of MOSFET and IGBT power modules are within the range of some 10 ns to
some 100 ns. Especially when high operating voltages and hard switching processes are
involved, the theoretically reachable maximum switching frequency cannot be utilized in most
cases, since the maximum switching speed is often determined by
- the turn-off speed, limited by the permissible switching overvoltage and
136
- the turn-on speed, limited by the permissible peak current (load current + reverse recovery
current of the free-wheeling diode depending on di/dt).
Moreover, transistor dv/dt and di/dt values, which are prone to be very steep within the high
power range, might cause electromagnetic interferences and problems due to dv/dt in certain
loads (machines).
Therefore, an optimized compromise between the requirements resulting from the application
(e.g. frequency out of range of audibility), switching times/ losses, power dissipation and EMC-
features has to be looked for when determining switching frequency and switching times.
These are the standard values for switching frequencies with standard modules, optimal technical
utilization provided:
for hard switching: MOSFET-modules low-voltage up to 250 kHz
high-voltage up to 100 kHz
IGBT-modules 600 V up to 30 kHz
1200 V up to 20 kHz
1700 V up to 10 kHz
3300 V up to 3 kHz
for soft switching: MOSFET-modules low-voltage up to 500 kHz
high-voltage up to 250 kHz
IGBT-modules up to 150 kHz
Higher switching frequencies can be realized with modules specially designed for fast switching.
3.2 Thermal behaviour
3.2.1 Balance of power losses
3.2.1.1 Single and total power losses
Introductory remarks
All explanations in chapter 3.2 refer to IGBT modules. All considerations and calculations are
applicable to MOSFET modules in analogy, provided all designation indices corresponding to
MOSFETs are exchanged.
The following explanations are focused on hard switching converters connected to a DC-voltage-
link.
In power electronics, IGBTs as well as diodes are operated mainly as switches, taking on various
static and dynamic states in cycles. In any of these states, one power dissipation or energy
dissipation component is generated, which heats the semiconductor and adds to the total power
dissipation of the switch. Therefore, the maximum junction temperature Tj= 150C (for silicon
components) given by the manufacturer has to be obeyed at any time of operation of the
converter when using power semiconductors.
Figure 3.3 shows a survey of the possible single power dissipations during switch operation.
137
Total Power Losses
Static Losses Switching Losses Driving Losses
On-state Losses Blocking Losses Turn-on Losses Turn-off Losses
Figure 3.3 Single power losses of power module switches
IGBT
Because they are only contributing to a minor share of the total power dissipation, forward
blocking losses and driver losses may usually be neglected.
On-state power dissipations (Pfw/T) are dependent on:

- load current (over output characteristic vCEsat = f (iC, vGE)),
- junction temperature,
- duty cycles.
For given driver parameters, the turn-on and turn-off power dissipations (Pon/T, Poff/T) are
dependent on:
- load current,
- DC-link voltage,
- switching frequency.
IGBT total power losses: Ptot/T = Pfw/T + Pon/T + Poff/T
Free-wheeling diode:
Because they are only contributing to a minor share of the total power dissipation, reverse
blocking power dissipations may usually be neglected. Schottky diodes might be an exception
due to their high-temperature blocking currents.
Turn-on power dissipations are caused by the forward recovery process. As for fast diodes, this
share of the losses may mostly be neglected as well.
On-state power dissipations (Pfw/D) are dependent on:

- load current (over forward characteristic vF = f (iF)),
- duty cycles.
For given driver parameters of the IGBT commutating with the diode, turn-off power
dissipations (Poff/D) are dependent on:
- load current,
- DC-link voltage,
- switching frequency.
Total diode power losses: Ptot/D = Pfw/D + Poff/D
138
Hybrid power module with n IGBTs and m diodes
Total module power losses: Ptot/M = (n*Ptot/T) + (m*Ptot/D)
3.2.1.2 Power losses of a step-down converter

Figure 3.4 shows the circuit diagram of a step-down converter with characteristics generated
under ohmic inductive load.
Transistor
Control
ON
OFF t
t1 T
vd
iC v out
i LH iL
T v CE i Lavg
i LL
iL
vd
t
D vF
v out iC
iF
t
iF
E off/T E fw/D E fw/T

E on/T
E off/D
Figure 3.4 Step-down converter under ohmic-inductive load
During the steady state of the circuit, power dissipations at a certain operation point may be
calculated as follows:
IGBT
Turn-on power dissipation: Pon/T = fs * Eon/T (vd, iLL, Tj/T)
Turn-off power dissipation: Poff/T = fs * Eoff/T (vd, iLH, Tj/T)
t
1 1
Foward power dissipation: Pfw/T = i C (t) v CE (t) dt
T0
Neglecting the load current ripple will result in:
Pfw/T = iLavg * vCEsat (iLavg, Tj/T) * (t1/T)

= iLavg * vCEsat (iLavg, Tj/T) * DT
DT = transistor duty cycle

iLavg = average load current
139
Free-wheeling diode
Turn-off power dissipation: Poff/D = fs * Eoff/D (vd, iLL, Tj/D)
T
1
T t1
Forward power dissipation: Pfw/T = v F (t) i F (t) dt
Neglecting the load current ripple will result in:

Pfw/D = iLavg * vF (iLavg, Tj/D) * (1-DT)
= iLavg * vF (iLavg, Tj/D) * (DD)
DD = diode duty cycle
The calculation of IGBT and diode forward power dissipation is based on an ideal duty cycle
(neglecting the share the switching time contributes to the total cycle duration).
Selected ratings for energy dissipations during switching as well as for the IGBT and diode
forward voltage drop are indicated in the datasheets (see chapter 2).
3.2.1.3 Power losses in pulsed voltage source inverters/rectifiers with sinusoidal currents
Basic circuit: Figure 3.5 shows ideal characteristics of an inverter phase for a sinusoidal
modulation according to the sinusoidal pulse-width modulation.
140
iC1 iF1
Vd/2 IGBT T1 Diode D1
V1 i1
IGBT T2 Diode D2
Vd/2
iC2 iF2
vref (t)
vref; vh
vh (t)
1/fS
1/fout
v1 (t) v1(1) (t) i1 (t)
i1; v1

2 fout
iC1
t
tfw/T1
iF2
t
tfw/D2
Figure 3.5 Converter phase with sinusoidal modulation according to sinusoidal pulse-width modulation
In the sinusoidal pulse-width modulation the pulse pattern is generated by comparison of a

reference voltage vref to an auxiliary control voltage vh, whereby the fundamental frequency of
the AC-parameters fout is determined by the reference voltage and the switching or pulse
frequency of the switches fs by the auxiliary control voltage.
The intersections of reference and auxiliary control voltage are the basis for commutation times
in the converter phase.
If v ref v h , this is called linear modulation mode of the inverter.
The following explanations refer to the linear modulation mode. Furthermore, it is presupposed
that the fundamental frequency of the AC-parameters is exceeded by the pulse frequency by far.
Voltage utilization of the converter may be expressed by the degree of modulation m. It indicates
the ratio between fundamental harmonics amplitude of the AC-voltage and 50 % of the DC-link
voltage. In case of a pure sinusoidal reference voltage, the degree of linear modulation will be
0 m 1.
141
The phase shift between the fundamental harmonics of AC current and voltage is described by
the angle .
The current and voltage characteristics for IGBTs and diodes, which are time-shifted, will turn
out to be identical due to the symmetrical structure of the inverter circuit. Therefore, it is enough
to consider just one IGBT (here T1) and one diode (here D2) with reference to the calculation of
power dissipation (the result is then multiplied by the corresponding number of IGBTs/ diodes
integrated in the inverter).
In contrast to the calculations under chapter 3.2.1.2 duty cycle, load current and junction
temperature are not constant under static operation, but vary depending on the fundamental
frequency of the AC side (e.g. 50/60 Hz). This means that switching and forward power
dissipations of IGBTs and diodes are subject to temporal variability and require a extensive
calculation of system power losses.
Consequently, exact results cannot be produced with greatly simplified calculation procedures.
Two calculation possibilities are to be introduced in the following.
1. Approximation of component characteristics by polynominal equations (detailed in [194])

In this calculation procedure, the dependencies of transistor and diode forward on-state voltages
on load current and junction temperature as well as of transistor and diode switching energy
dissipations on load current, DC-link voltage and junction temperature are approximated by
polynominal equations of the type y = f(x) = A + Bx + Cx. For this, the available component
parameters have to be taken from the datasheets or determined by simple pulse converter test
circuits, which, however, requires considerable effort.
The following set-up of the polynominal equations may be done by using conventional curve-
fitting software.
The coefficients A-C of a following equations comprise the determined dependencies of the
parameters.
Accordingly, equations 3.1-3.4 may be set up to calculate the average energy dissipation.
The following simplifications have been presupposed:
- transistor and diode switching times are neglected,
- temporally constant junction temperatures (permissible if fout = ..50 Hz),
- linear modulation of the converter,
- neglecting the switching frequency ripple of the AC-current.
Forward power dissipation

Including forward characteristic approximation of IGBT and diode according to y = A + Bx and
considering the temperature coefficients of the forward on-state voltages, results in the following
equations:
IGBT T1:
1 t A fw/T B 2 A B 2
Pfw/T1 = - dead i1 + fw/T i1 + m cos fw/T i1 + fw/T i1 (3.1)
2 TS 4 8 3
142
Diode D2:
1 t A B 2 A B 2
Pfw/D2 = + dead fw/D i1 + fw/D i1 m cos fw/D i1 + fw/D i1 (3.2)
2 TS 4 8 3
Figure 3.6 explains the influence of switching deadtime tdead on forward energy dissipations (tdead
determines the effective duty cycles) with the example of a 1200 V/50 A-IGBT-module.
Especially if high pulse frequencies are involved, the arm-interlock-deadtime tdead has to be
considered in the calculation of the average power forward dissipation.
|Pfwreal-Pfwideal | [%]
Pfwreal
30 IGBT
25 Diode
20
15
10
5
0
0 0,02 0,04 0,06 tdead/TS0,08
Figure 3.6 Forward power dissipations versus switching deadtimes (i1eff = 25 A; m = 0.8; cos = 0.8)
Switching losses
The following equations result from the approximation of the dependency of switching losses on
the current according to y = Bx + Cx in consideration of temperature and voltage coefficients of
the switching losses:
B C
IGBT T1: Pon + off/T1 = f s i1 on + off/T + on + off/T i1 (3.3)
4
B C
Diode D2: Poff/D1 = f s i1 off/D + off/D i1 (3.4)
4
Figure 3.7 shows one result of this calculation method with the example of a 1200 V/50 A-
IGBT-dual module in an inverter.
143
Pfw [W] IGBT

40 Diode
35
m*cos=0.64
30 0.1
25 -0.64
20
15
10
5
0
0 5 10 15 20 25 30 35
IRMS [A]
Psw [W] IGBT

50 Diode
Vd=700 V
40 500 V
30
20
10
0
0 5 10 15 20 25 30 35
IRMS [A]
Figure 3.7 a) Forward power dissipations (tdead = 5 s, T j = 125C)

b) Switching losses (fs = 10 kHz, Tj = 125C)
The product of m*cos determines how the total power dissipation is divided up on IGBT and
diode (see also chapter 1.3.1.4).
m*cos = 0.64 represents an operating point in inverter mode (motor load)

m*cos = 0.1 represents an operating point in motor starting mode
m*cos = -0.64 represents an operating point in rectifier mode
The procedure for calculation of IGBT and diode power dissipation described above shows very
exact results, however the determination of parameters requires great efforts.
Therefore, the following greatly simplified calculation mode to produce a rough calculation can
be recommended.
2. Simplified, linear approach [274]

Assumptions:
- transistor and diode switching times as well as switching interlocking times are neglected,
- temporally constant junction temperatures (permissible if fout = ..50 Hz.),
144
- linear modulation of the converter,

- neglecting switching frequency ripple of the AC current (sinusoidal current),
- fs >> fout.
Forward on-state power dissipation:

IGBT T1:
If the output characteristics are linearized with y = A + Bx, the temporal dependency of the
saturation voltage vCEsat may be expressed as follows:
v CEsat (t) = VCE0 + rCE i C (t) = VCE0 + rCE i1 sin t
with: VCE0 = threshold voltage of the output characteristic with iC = 0
rCE = on-state resistance of the IGBT (rate of rise of the output characteristic)
Considering the sinusoidal dependency of duty cycles versus time, the forward power dissipation
of IGBT T1 may be calculated according to
1 VCE0 r 2 V r 2
Pfw/T1 = i1 + CE i1 + m cos CE0 i1 + CE i1 (3.5)
2 4 8 3
Diode D2:
If the output characteristics are linearized with y = A + Bx, the temporal dependency of the
foward on-state voltage vF may be expressed as follows:
v F (t) = VF0 + rF i F (t) = VF0 + rF i1 sin t
with: VF0 = threshold voltage of the forward characteristic with iF = 0
rF = on-state resistance of the diode (rate of rise of the output characteristic)
Considering the sinusoidal dependency of duty cycles versus time, the forward power dissipation
of diode D2 may be calculated according to
1 VF0 r 2 V r 2
Pfw/D2 = i1 + F i1 m cos F0 i1 + F i1 (3.6)
2 4 8 3
Switching losses
IGBT T1:
Provided that the energy dissipation during switching is linearly dependent on the collector
current, the total power dissipation of an IGBT may be calculated with
Pon + off/T1 =
1

[ () ( )]
f s E on/T i1 + E off/T i1 (3.7)
Equation 3.7 is actually based on the assumption that the IGBT switching losses generated
during one sine half-wave are about identical to the switching losses generated if an equivalent
direct current is applied, which would correspond to the average value of the sine half-wave.
IGBT switching losses are approximately convertible linearly to other DC-link voltages.
145
Diode D2:
Provided that the energy dissipation during turn-off is linearly dependent on the diode current,
the total power dissipation of a diode may be calculated with:
Poff/D2 =
1

()
f s E off/D i1 (3.8)
This equation is also based on the assumption that the diode switching losses generated during
one sine half-wave are about identical to the switching losses generated, if an equivalent direct
current is applied, which would correspond to the average value of the sine half-wave.
Diode switching losses are approximately convertible linearly to other DC-link voltages.
The results rendered by the explained simplified calculation process are sufficient for estimating
the expected power dissipation during converter operation mode in practice.
The decisive advantage that is offered to the user is that all necessary parameters can be taken
directly from the corresponding module datasheets.
3.2.2 Calculation of the junction temperature
3.2.2.1 General hints

The calculation of junction temperatures is based on the simplified thermal equivalent block
diagram of Figure 3.8.
The designations used for transistor and diode are related to those in Figure 3.5.
The equivalent block diagram is restricted to one transistor and its commutating diode in a power
module, i.e. to those two components through which the load current is conducted during one
sine half-wave (here T1 and D2). The equivalent block diagram for T2 and D1 can be drawn up
in analogy.
146
T j/D2
T j/T1
Z thjc/T1 Z thjc/D2
P tot/D2 P tot/T1 T coup/D1 T coup/T2
TC Z thch
Th
Z thha
Ta
Ta
Z thx (t) = R thx [1- exp(- t/Tthx )]

=4
R thx1 R thx4
thx1 thx4
R thx1 R thx4
Figure 3.8 Simplified thermal equivalent block diagram of IGBT and free-wheeling diode in a power module
Explanation of designations:
Ptot Total power dissipation within transistor and free-wheeling diode
Tj Junction temperatures
Zthjc Thermal impedance from junction to module case
Tc Case temperature
Zthch Thermal impedance from module case to heatsink
Th Heatsink temperature
Zthha Thermal impedance from heatsink to ambient temperature (see chapter 3.3)
Ta Ambient temperature
Transistors and inverse diodes are soldered on a common copper plate in a power module.
Therefore, the elements Tcoup/D1 and Tcoup/T2 stand for the thermal coupling of T1 and D2 with
their corresponding antiparalleled elements D1 and T2, which becomes effective especially at
low fundamental frequencies.
Exact determination of this coupling effect is subject to extensive thermal simulation of the
module structure [194]. Therefore, this is usually neglected in simplified calculation processes.
147
If transistor and free-wheeling diode are integrated in the same module, a common heatsink and
case temperature may be presumed for simplification.
If this simplifaction is no more permissible for high-power single switches, the values for Zthch
have to be entered separately for transistor and diode.
Efficient thermal parameters between case and heatsink are also dependent on the following
factors: quality of the module base plate, contact pressure between module and heatsink, thermal
paste, surface quality of the heatsink. Please pay attention to the data and recommendations
given by the manufacturers (see chapter 1.4.2.2).
For computer-aided simulation of the temporal behaviour of the junction temperature thermal
impedances may be divided up into a chain circuit of R-C components (see Figure 3.8).
As a special service to the customer, SEMIKRON offers parameters of 4-6 R-C components for
determining the Zthjc of power modules in the databook. Parameters of the cooling systems are
also available on request (see chapter 3.3.6).
Following the equivalent block diagram of Figure 3.8, the characteristics of the junction
temperatures of transistor and diode versus time can be calculated according to the following
equations based on the case temperature:
n
Tj/T1 (t) = TC + Tcoup/D1 + PT1 (t) R
=1
th/T1 [1 - exp (- t/ th/T1 )] (3.9)
n
Tj/D2 (t) = TC + Tcoup/T2 + PD2 (t) R
=1
th/D2 [1 - exp (- t/ th/D2 )] (3.10)
Often only the average junction temperatures and their ripples are decisive for the thermal layout
of converters. Exemplary calculations for typical loads are explained in the following chapters.
3.2.2.2 Junction temperature during short-time operation

Short-time operation allows for higher currents to be conducted in the power semiconductors
than indicated in the datasheets for permanent operation. However, the highest junction
temperature generated under the given conditions should not exceed the maximum rating of
Tj = 150C.
The junction temperature can be calculated using formulas 3.9 and 3.10 in chapter 3.2.2.1.
148
Examples:
Single power dissipation pulse

P Tj
Tjmax
Tj0
t t
0 t1 0 t1
Figure 3.9 Power dissipation and junction temperature of single power dissipation pulse versus time
Maximum value of the junction temperature alteration at t1:

n
Tjmax = Tj (t 1 ) = P R [1 - exp (- t / )]
=1
th 1 th (3.11)
Junction temperature during cooling periode:

n n
T (t > t 1 ) = P R [1 - exp (- t/ )] - P R [1 - exp (- (t - t )/ )]
=1
th th
=1
th 1 th (3.12)
These formulas are based on a fixed case reference temperature.
Single sequence of m power dissipation pulses
P Tj
P2
P1
P3
T T T
j1 j2 j3
Tj0
t
0 0 t1 t2 t3
Figure 3.10 Power dissipation and junction temperature at single sequence of m power dissipation pulses versus
time
Junction temperature alteration at t1:

n
Tj1 = P1 R [1 - exp (- t / )]
=1
th 1 th (3.13)
149
Junction temperature alteration at t2:

n n
Tj2 = P1
=1
R th [1 - exp (- t 2 / th )] + (P2 P1 ) R [1 - exp ( (t
=1
th 2 - t 1 )/ th )] (3.14)
Junction temperature alteration at tm:
(P P-1 ) R [1 - exp ( (t - t -1 )/ th ) ]
m n
Tj (t m ) = th m (3.15)
=1 =1
These formulas are based on a fixed case reference temperature.
3.2.2.3 Junction temperature under pulse operation

The transistor and diode Zthjc-characteristics under periodic pulse conditions indicated in the
datasheets may be used for calculation of the average and maximum junction temperature under
power dissipation load periodically repeated along with the pulse frequency.
Figure 3.11 shows such a set of curves for the IGBT and the diode of a SKM100GB123D
module and a typical current and junction temperature characteristic in the transistor under pulse
operation.
a)
b)
Tj , i
Tjmax
Tjavg
Tjmin
i t
D=
Ts
t
t
c)
Ts
Figure 3.11 Transient thermal impedance Zthjc of IGBT (a) and diode (b) of a SKM100GB123D module
c) Current and temperature characteristic
150
The average junction temperature Tjavg results from multiplication of the thermal resistance Rthjc
with the average power dissipation Ptotavg. The latter is calculated by averaging the energy
dissipation per pulse over the whole pulse or switching duration Ts.
Ptotavg = fs * (Eon + Eoff + Efw)
Tjavg = Tc + Ptotavg * Rthjc

The maximum junction temperature Tjmax results from multiplication of Zthjc under pulse
operation with the maximum power dissipation Ptotmax. The latter is calculated by averaging the
energy dissipation per pulse over the on-state time t of transistor or diode, respectively, within
the pulse duration Ts.
Ptotmax = (Eon + Eoff + Efw)/t
Tjmax = Tc + Ptotmax * Zthjc
Examples with a SKM100GB123D IGBT:
Example 1: fs = 10 kHz; Ts = 100 s; D T = 0.2; t = 20 s

Tc = 80C; Eon + Eoff + Efw = 25 mJ
Rthjc = 0.2C/W, Zthjc = 0.04C/W (see Figure 3.11a)
Consequently: Ptotavg = 250 W; Ptotmax = 1250 W

Tjavg = 80C + 250 W * 0.2C/W = 130C
Tjmax = 80C + 1250 W * 0.04C/W = 130C


Tjavg = 80C + 50 W * 0.2C/W = 90C
Tjmax = 80C + 250 W * 0.042 C/W = 90.5C


Tjavg = 80C + 250 W * 0.2C/W = 130C
Tjmax = 80C + 1250 W * 0.042C/W = 132.5C
Example 4: fs = 50 Hz; Ts = 20 ms; DT = 0.5; t = 10 ms

Tc = 80C; Eon + Eoff + Efw = 5 J

Tjavg = 80C + 250 W * 0.2C/W = 130C
Tjmax = 80C + 500 W * 0.12C/W = 140C
151
Example 1 is calculated based on a typical IGBT pulse frequency of 10 kHz. The result shows
that there is no deviation between the average and maximum values of the junction temperature
due to the low thermal impedances at high frequencies.
The pulse frequency in example 2 and 3 had been reduced to 2 kHz, however keeping constant
values for the amount of energy dissipation in example 2 and for the average and maximum total
power dissipation in example 3. Both examples show a deviation between average and maximum
junction temperature.
Simply expressed, it may be presumed that a calculation based on average power dissipation and
static thermal resistance is sufficient for pulse frequencies above about 3 kHz.
Example 4 shows the drastic difference between average and maximum junction temperature at
very low pulse frequencies.
3.2.2.4 Junction temperature at fundamental harmonics frequency

Calculation of the junction temperature determined by the fundamental frequency of the
converter output current is only efficient, when it is computer-aided.
The thermal system as well as the electrical system per pulse duration have to be calculated in
detail in order to integrate the IGBT and diode junction temperature over a sine half-wave.
Figure 3.12 shows a principal calculation scheme which had been elaborated in source [194].
Thermal Model
Simulation of the Thermal

Junction Temperature Parameters
T j (t)
Electrical Model
Calculation of the
P(t) Temperature
Coefficients
Calculation of the
Converter
Losses per
Parameters
Switching Cycle
Figure 3.12 Principal calculation of the junction temperature in converters with sinusoidal output currents [194]
The thermal model mainly corresponds to Figure 3.8 simulating the thermal impedances by
means of RC-elements.
Switching losses per pulse may be calculated based on stored characteristics, if the current
converter parameters such as DC-link voltage and instantaneous load current are given. The
152
instantaneous junction temperature is entered into the calculation via the temperature
coefficients.
Figure 3.13 shows the power dissipation time characteristic and the average power dissipation in
an IGBT as well as the resulting junction temperature characteristics for different basic output
frequencies as the result of a simulation according to [194].
Tj/T [C] Ptot/T [W]

110 160
fourt->0Hz 140
100
5Hz
120
90 50Hz
100
80 80
Tjavg 60 Ptotavg
70
40
60 20
50 0
[rad] 2 [rad] 4
2 4
Figure 3.13 Simulated junction temperature and power dissipation characteristics of a 1200V/50A-IGBT under
inverter operation for different fundamental output frequencies; [194]
vd = 540 V; i1RMS = 25 A, fs = 8 kHz; cos = 0.8; m = 0.8; Th = 50C
In this example, the maximum junction temperature exceeds the average value by just about
4-5 K at a frequency of 50 Hz.
For low frequencies the average junction temperature is no longer permitted to determine the
thermal layout of the system because of its clearly increased maximum value.
Consequently, the permissible output current RMS-Valuefor a defined power module will
decrease at a given heatsink temperature and switching frequency.
Corresponding performance characteristics (e.g. for SKiiPPACK) are available by SEMIKRON
on request.
Moreover, Figure 3.13 shows that no temperature ripples with righ pulse frequency arise. This is
also confirmed by the calculations in chapter 3.2.2.3.
A very particular special case with regards to the thermal stress of power modules is the voltage-
and frequency-controlled starting procedure of a three-phase motor drive supplied by an inverter.
Figure 3.14 shows a related simulation example.
I1RMS [A] fout [Hz] m

40 50 1
35 40 0,8
30 30 0,6
25 20 0,4
20 10 0,2
15 0 0
0 0,5 1 1,5 t [s] 2 0 0,5 1 1,5 t [s] 2
153
Tj [C]
90
85
80
IGBT
75
70
65
60 Diode
55
50
0 0,5 1 t [s] 1,5
Figure 3.14 Start-up of a three-phase motor drive (parameters as in Figure 3.13), [194]
3.2.3 Evaluation of temperature characteristics with regards to module life

Power dissipation alterations below a repetition frequency of about 3 kHz will not be smoothed
by the transient thermal impedance of the chips any longer and will lead to temperature
fluctuations in the module (see chapter 3.2.2).
As already mentioned in chapter 1.4.2.4, all internal connections of power modules are subject to
wear and tear caused by temperature fluctuations. This fatigue of material is caused by thermal
stress due to the different expansion coefficients of the connected materials.
Therefore, it is important for thermal dimensioning to check, whether the chip temperature
fluctuations generated during periodic power cycling (pulse frequency, fundamental frequency,
power cycle) are so intensive that, in the worst case, the required number of cycles may not be
reached. In this case, not the maximum chip temperature Tjmax, but the temperature difference
Tj = Tjmax - Tjmin during given power cycles is considered as limit value for power losses of the
module.
The correlation between the possible number of power cycles n and the temperature cycling
amplitude Tj is subject to the influence of many parameters. Corresponding measurements
require a lot of time and effort, see chapter 2.7 and [231].
In tests with active power cycles the lifetime of a power module depends not only on the
temperature difference Tj but also on the average (medium) temperature Tm in the test
procedure. This was confirmed clearly by the results of LESIT-research project [303].
LESIT results of power cycling lifetime tests with power modules by different manufacturers are
shown in Figure 3.15. The parameter adjustment was done by SEMIKRON. These results
represent the state-of-the-art in 1995. Meanwhile, the lifetime was increased by improved solder
connections and optimized wire bond connections. So, 20000 cycles at T=100C and
Tj,min=40C are achieved. Presently, updated characteristics for SEMIKRON power modules are
in preparation.
154
LESIT results for power cycling lifetime
E
N f = A T exp a
kB Tm
number of cycles
30 40 50 60 70 80 90 100 110
delta T [C]
Tj,max=const.=120C Tj,medium=const.=80C Tj,min=const.=40C
Figure 3.15 LESIT results for power cycling lifetime
3.3 Cooling of power modules
3.3.1 Cooling devices, coolants and cooling methods

The heat potential due to forward, switching and blocking losses in power modules has to be
dissipated by means of heatsinks, which provide an expanded surface for convection and
radiation, spreading the heat flow as well as reducing the intensity of transient thermal processes.
Due to their isolation, all power modules of one system are mounted on to one common heatsink
which may also serve as an element of the construction (case, chassis etc.).
Heat dissipation in a heatsink works on the principle that the heat is dissipated to the coolant
either by direct heat transmission or via a heat carrier.
Heat carriers may be air, water or (more rarely) isolation oil, which is circulated by the effect of
gravity or by fans or pumps.
Air in natural and forced motion or coolant mixtures on the basis of water may serve as coolants.
In the following we would like to emphasise only natural (free convection) and forced air
cooling and water cooling systems with one coolant circuit each, since more sophisticated
cooling methods, such as heatpipes or boiling cooling are normally extremely application-
specific and oil cooling is not very commonly used with power modules.
155
The heatsink material has to be constructed for optimal heat spreading (high heat transfer
coefficient ), with acceptable material and handling costs. Therefore, aluminum is often
preferred ( = 247 W/K*m for pure Al), in special cases copper is also used ( = 398 W/K*m).
The dependence of heat spreading on the production process and the alloy used is remarkable;
practical heatsinks show -values between 150 W/K*m (Al-die cast alloy) and 220 W/K*m
(AlMgSi-extruded material).
Heat spreading has a considerable influence on the thermal efficiency of the heatsink. Therefore,
optimized dimensioning of root thickness, number of fins, fin height and fin thickness is of
importance:
- The root of a heatsink is the unfinned part of the mounting surface for the power modules,
where the temperature gradient to the module base plate is relatively low and where the heat
is spread.
- The fins of an air heatsink are used for dissipating the majority of the heat to the environment
by radiation and convection. In water heatsinks this task is fulfilled by more or less
structured water channels.
Rthha = T/Ptot = 1/( * A)
results from Q = * A * T = Ptot
(Q: dissipated heat quantity, : heat transfer coefficient, A: heat transfer area, T:
temperature difference to the environment, Ptot: power dissipation, Rthha: heat transfer
resistance of the heatsink)
It is recommended that a high number of fins is provided in order to increase the area of
dissipation. But it has to be guaranteed that the flow conditions are set in a way which will
not decrease greatly.
Consequent to this conclusion, the different optimization criteria for heatsinks with natural and
forced air cooling may be deducted.
The heatsink is heated more evenly when the power dissipation increases, i.e. the efficient heat
exchange surfaces are enlarged; in Figure 3.16 the heat exchange surface is further extended by
an increased heatsink length.
3.3.2 Thermal model of the cooling device

When explaining the thermal characteristics of power modules in chapter 1.4.2.2, the heatsink in
the thermal equivalent block diagram had been described by only one RC-element (Rthha,
Zthha).
However, with an increase of power dissipation at t = 0 from P = 0 to P = Pm , the characteristic
of the transient thermal impedance of the heatsink Zthhaversus time t is split up into several time
constants as shown in Figure 3.16 with an example. The total thermal impedance characteristic
Zthja(t) of the assembly may be determined by graphic addition of the thermal impedance
characteristics of the power module and the heat transition to the heatsink.
The Zth(t)-curves may be plotted as the sum of exponential functions using the following
equations:
T(t) = Pm R th [1 - exp (- t/ th )] and Z thha (t) = T(t)/Pm

156
i.e.
Z thha (t) = R th [1 - exp (-t/ th )]
The number of and the Rth- and -values are chosen so that a sufficient approximation of the
characteristic can be produced without applying complicated calculation procedures,
independent of the physical structure. One iteration method is described, for example, in source
[266].
The ratings for simulations indicated by SEMIKRON and mentioned briefly in the following
chapters are based on a 4-time-constants-model ( = 4).
3.3.3 Natural air cooling (free convection)

Natural air cooling is applied in low power range applications up to 50 W as well as in high
power range applications, if the use of fans is not possible or if extremely large cooling surfaces
are available in the device.
Since with free convection, the thermal transient resistance of the heatsinks usually exceeds the
internal thermal resistance of the power modules, the temperature difference between chip
(125C) and cooling air (45C) drops mainly over the heatsink. Near the modules, the heatsink
temperature is usually higher than with forced air cooling, for example 90...100C. Because
power losses are usually low with natural air cooling, heatsink root and fins do not have to be
very thick, since heat conductivity has only a minor influence on the thermal features. The fin
distances have to be selected sufficiently to obtain a favourable ratio between air uplift (drop of
temperature / density) and air friction. Black coating of the heatsink will improve the radiation
characteristics and, thus, the Rthha-value by about 15 % at a temperature difference of 50 K
between mounting surface and atmosphere [266]. The surface finish, however, does not impair
heat transfer between module base plate and heatsink.
3.3.4 Forced air cooling

In contrast to natural air cooling, forced air cooling can reduce the thermal heatsink resistance to
1/5...1/15. Figure 3.16 compares the Zthha(t) characteristics of natural and forced air cooling up to
the final Rthha-value with the example of different SEMIKRON P16/...-heatsinks.
157
a) b)
Figure 3.16 Zthha(t)-characteristics for different P16/...-heatsinks

a) Free convection
b) Forced air cooling
Compared to free convection, is much higher with forced air cooling. The rated surface
temperature of forced air-cooled heatsinks should not exceed 80...90C at a supply air
temperature of 35C (condition for datasheet ratings).
The heat conductivity of the heatsink has tremendous influence on the cooling effect, which
requires a thick root and a maximum number of fins. Because convection is mainly responsible
for the dissipation of heat, black coating of the heatsink will have almost no effects with forced
air cooling.
Rthha is mainly determined by the rate of air flow per time Vair/t, depending on the average
cooling air velocity vair and the transfer cross section A:
Vair/t = vair * A
Instead of the assumed laminar air flow, air whirlings on the fin surfaces will effect turbulent
flow conditions between the fins, which will improve heat dissipation to the atmosphere,
provided the fin surfaces are set out accordingly.
The transfer cross section of the heatsink will be reduced by increased number of fins and fin
width as well as by increased heatsink length (fin length L) and the cooling air-pressure drop p
will rise. Consequently, heat dissipation is dependent on the characteristics of the fan, which are
described in the fan characteristic p = f(Vair/t) (Figure 3.17).
158
FANS.XLS-2
4
mbar
SKF16A-230-01
SKF16B-230-01
3
SKF 16 B
2 SKF 16 A
0
0 200 400 600 3
m /h 800
Figure 3.17 Fan characteristic p = f(Vair/t) for SEMIKRON P16/... fans
The thermal transient resistance of the heatsink assembly Rthha depends on the rate of air flow
shown in Figure 3.19, which may be determined by combining fan and pressure drop
characteristics p = f(Vair/t, L) or p = f(vair, L) of the heatsink.
P16/...F with Fan

2
A = 7368 mm ; c=0,0377 x Vair [m/s]
450
Fan
400
P16/400F
350
P16/300F
300
p [Pa]
P16/200F
250 Meas. Points
200
150
100
50
0
0 100 200 300 400 500 600
3
Vair [m /h]
Figure 3.18 Air flow of a P16/... heatsink profile at various heatsink length
Apart from the air flow, Rthha is dependent on distribution and position of heat sources (power
modules) on the heatsink. Figure 3.19 explains these relationships with the example of a selected
SKiiP-assembly.
159
Figure 3.19 Thermal resistance of the heatsink Rthha of a SKiiP-assembly versus air flow and position of the
SKiiPPACK on the heatsink
Figure 3.20 shows the standard assembly of a 3-fold SKiiPPACK on an air-cooled heatsink
P16/280F.
Figure 3.20 SKiiPPACK 3 standard assembly with SKF 16B fan
To determine optimized conditions for forced air cooled heatsink profiles, heat conduction and
convection can also be integrated by the fin height layout, which will result in the following
formula on condition of some simplifications:
160
1
Rthha =
1 1
n U A
1 + exp 2h 1 + exp 2h
U
with =
A
(: heat-transfer coefficient, U: fin circumference, : coefficient of thermal conductivity of
heatsink, A: cross section of fins, h: fin height)
Often, several heatsinks have to be cooled by only one fan, for which they are either arranged in
parallel (heatsinks positioned side by side) or in series (heatsinks behind each other in direction
of air flow).
With regard to thermal stacking, which is preferred, for example, in three-phase inverter
applications with standard GB-circuit SKiiPPACKs (halfbridge modules), special attention
should be paid to the fact that the air is preheated for 2 of the 3 SKiiPPACKs, which has to be
taken into consideration when determining the thermal layout.
At an air flow rate of 300 m3/h, about 10 K temperature difference between supply and exhaust
air is presupposed as a standard value per kW dissipated power. Thermal details are given in
chapter 3.3.6.1.
3.3.5 Water cooling

Water cooling of power modules can be used for special high power inverters (MW-range) as
well as for small power devices, which already provide for a water circuit due to their working
principles (e.g. car drives, galvanic plants, inductive heating).
Mostly, the admission temperature of the coolant values is up to 50..70C when the heat of the
coolant is directly dissipated to the atmosphere; in industrial plants with active heat exchangers
the temperature is about 15..25C.
The temperature difference between heatsink surface and coolant which is lower than with air
cooling may be utilized in two ways:
- increased energy exchange at a high dynamic Tj of chip temperature per cycle (limits for
module life see chapter 3.2.3) or
- low chip temperature, long module life.
Due to its capability for high heat retention (thermal capacity cp = 4.187 kJ/kg *K) water is
principally preferred to oil or glycol for the dissipation of heat.
Figure 3.21 shows a SEMIKRON standard assembly with a 3-fold SKiiPPACK on a water-
cooled base plate.
161
~ ~ ~
11 Pin 2 Pin 26 12 14
Pin 1
DATE:..........................................
U.S. Patent No:.................
U.S. Patent No:.................
Pin 25
xxxxxxxxxxxxxxx
Ord.No:.......................................
SK.No: ...............................
SKiiP
output
1 2 3 4 7 8
+ - + - + -
Figure 3.21 SKiiPPACK 3 standard assembly with water-cooled base plate
Due to the corrosive effect of water and the mostly required frost-resistance, open or closed
circuit with pure water are hardly used.
By adding glycol, for example, the heat-retainability of the coolant will be diminished (e.g.
3.4 kJ/(kg*K) at an addition of 50 % glycol and a coolant temperature of 40C). As viscosity and
specific gravity of the coolant will rise, the thermal resistance from heatsink to coolant Rthhw will
considerably increase together with the share of glycol. Compared to pure water, a 50 % addition
of glycol will effect an increase of Rthhw by approximately 50...60 % and again by another
60...70 %, if the glycol share is increased up to 90 %.
To guarantee for corrosion protection, SEMIKRON water-cooled aluminum heatsinks contain a
minimum share of glycol of 10 %. The hardness of the cooling water may not exceed a degree of
6. At least for coolant temperatures higher than 60C we recommend to use a closed cooling
circuit.
Thermal stacking of heatsinks with power modules or SKiiPPACKs is also done in correlation
with water cooling. A difference of about 1.7 K per kW dissipated power between inlet and
outlet temperature of the coolant can be taken as a standard value for the preheating per heatsink
(SEMIKRON water-cooled heatsinks for SKiiPPACKs) for a 50/50 % water-glycol-mixture at a
coolant flow of 10 l/min.
For detailed information on SKiiPPACKs on water-cooled heatsinks please see chapter 3.3.6.2.
3.3.6 Heatsink ratings for SKiiPPACKs on standard heatsinks
3.3.6.1 Forced air cooling

The following table contains the characteristics R and for thermal calculation according to the
4-time-constants-model for SKiiPPACKs on standard heatsink P16 with fan SKF 16B (GD 133-
2k-40105).
Rthsa tot: stationary thermal resistance as a result of the temperature difference between
temperature sensor (Ts) and supply air (Ta), with reference to the total power
dissipation Ptot of the assembly
4
R thsa tot = R
=1
Zthsa tot: transient thermal impedance as a result of the temperature difference between
temperature sensor (Ts) and supply air (Ta),with reference to the total power
dissipation Ptot of the assembly
162
4
Z thsa tot = R [1 - exp (-t/ ]
=1

thermal characteristics (4-constants-model)
R1 R2 R3 R4 R 1 2 3 4
K/W K/W K/W K/W K/W s s s s
2-fold SKiiPPACK (Vair/t = 310 m3/h)

1.383_ 1.886_ 6.663_ 3.640_ 4.299_ 2.579_ 6.350_ 5.831 1.543_
10-2 10-2 10-3 10-3 10-2 102 101 102
3-fold SKiiPPACK (Vair/t = 305m3/h)

1.157_ 1.669_ 3.512_ 3.097_ 3.487_ 2.638_ 6.625_ 6.049 2.000_
10-2 10-2 10-3 10-3 10-2 102 101 10-2
4-fold SKiiPPACK (Vair/t = 300m3/h)

1.398_ 2.048_ 7.012_ 2.448_ 3.134_ 5.398_ 1.724_ 2.008_ 2.876_
10-3 10-2 10-3 10-3 10-2 102 102 101 10-2
In the case of thermal stacking of SKiiPPACKs, the reduction of air flow resulting from the
increased pressure drop and pre-heating of the backward SKiiPACKs by the cooling air
passing the front SKiiPPACKs has to be considered in the calculations.
Figure 3.22 explains the principle of thermal stacking:
1 1 2 1 2 3
FAN SKiiP FAN SKiiP SKiiP FAN SKiiP SKiiP SKiiP
Ptot1 Ptot1 Ptot2 Ptot1 Ptot2 Ptot3
Figure 3.22 Thermal stacking of SKiiPPACKs with forced air cooling
Pre-heating is determined by total power dissipation of the SKiiPPACKs Ptotn, stationary thermal
resistance Rthaa and transient thermal impedance Zthaa (resistance Rthaa/time constant aa) between
two adjacent heatsinks, see Figure 3.22. The following formulas are valid for determining the
transient thermal impedances Zthsatotn of every single SKiiPPACK:
SKiiPPACK no. 1
4
Z thsa tot1 = R [1 - exp (-t/ )]
=1
SKiiPPACK no. 2
4
Z thsa tot2 = R [1 - exp (-t/ )] + (Ptot1 /Ptot2 ) R thaa1 2 [1 - exp (-t/ aa1 2 )]
=1
163
SKiiPPACK no. 3
4
Z thsa tot3 = R [1 - exp (-t/ )] + [(Ptot1 + Ptot2 )/Ptot3 ] R thaa2-3 [1 - exp (-t/ aa 23 )]
=1
3.3.6.2 Liquid cooling

The following table contains the characteristics R and for thermal calculation according to the
4-time-constants-model for SKiiPPACKs on a standard water-cooled heatsink S1021450 with
mutual water inlet/outlet, 50/50 % water-glycol-mixture at a coolant temperature of 50C. Since
the temperature Ts of the internal temperature sensor of the SKiiP is also available here as a
reference point for the heatsink temperature Th, the following definitions are valid:
Rthsw tot: stationary thermal resistance as a result of the temperature difference between
temperature sensor (Ts) and coolant (Tw), with reference to the total power
dissipation Ptot of the assembly.
4
R thsw tot = R
=1
Zthsw tot: transient thermal impedance as a result of the temperature difference between
temperature sensor (Ts) and coolant (Tw),with reference to the total power dissipation
Ptot of the assembly.
4
Z thsw tot = R [1 - exp (-t/ )]
=1
Coolant thermal characteristics (4-constants-model)

by-pass
l/min R1 R2 R3 R4 R 1 2 3 4
K/W K/W K/W K/W K/W s s s s
2-fold SKiiPPACK
6 1.942_ 6.262_ 3.785_ 6.608_ 1.860_ 1.225_ 2.911 1.189_ 5.196_
10-3 10-3 10-3 10-3 10-2 10-1 101 101
10 1.942_ 6.262_ 4.402_ 2.993_ 1.560_ 1.225_ 2.911 1.782_ 1.131_

10-3 10-3 10-3 10-3 10-2 10-1 101 102
14 1.942_ 6.262_ 4.628_ 1.667_ 1.450_ 1.225_ 2.911 2.000_ 1.355_

10-3 10-3 10-3 10-3 10-2 10-1 101 102
3-fold SKiiPPACK
6 2.143_ 3.818_ 9.405_ 2.535_ 1.790_ 2.204_ 3.343 2.800_ 1.123_
10-3 10-3 10-3 10-3 10-2 10-1 101 102
10 2.143_ 3.818_ 6.683_ 2.057_ 1.470_ 2.204_ 3.343 2.367_ 1.094_

10-3 10-3 10-3 10-3 10-2 10-1 101 102
14 2.143_ 3.818_ 5.662_ 1.878_ 1.350_ 2.204_ 3.343 2.205_ 1.083_

10-3 10-3 10-3 10-3 10-2 10-1 101 102
164
4-fold SKiiPPACK
6 8.714_ 2.893_ 7.573_ 1.970_ 1.331_ 9.939_ 2.038 2.700_ 1.462_
10-4 10-3 10-3 10-3 10-2 10-2 101 102
10 8.714_ 2.893_ 4.785_ 2.052_ 1.060_ 9.939_ 2.038 1.868_ 9.085_

10-4 10-3 10-3 10-3 10-2 10-2 101 101
14 8.714_ 2.893_ 3.649_ 2.086_ 9.499_ 9.939_ 2.038 1.529_ 6.830_

10-4 10-3 10-3 10-3 10-3 10-2 101 101
Calculation of thermal stacking is basically made the same way as with air cooling.
3.4 Power design

MOSFET, IGBT or SKiiP power circuits are designed in printed circuit board technology, or by
means of cables or massive copper or aluminum bars, depending on the currents and voltages to
be switched.
Apart from the general specifications to be met, for example with regards to creepage and
striking distances or current density, the short switching times within the nano to microsecond
range demand a sophisticated power design, which also lives up to the requirements of high-
frequencies.
3.4.1 Parasitic inductances and capacitances

To analyse the effects of parasitic inductances and capacitances of converters, it will be
sufficient to examine one commutation circuit.
Figure 3.23 shows the commutation circuit of an IGBT-inverter with parasitic elements,
consisting of DC-link voltage vd (corresponds to commutation voltage vK) and two IGBT
switches with driver and inverse diodes. Commutation voltage is impressed by the DC-link
capacitance Cd. The impressed current iL flows out of the commutation circuit.
165
iK L11
C11 L61 L71
Driver L21
VDr T1 D1
RGon C31 C41
RGoff
C21 L31
E`1
Cd L41 L51
Vd(VK) iL
E1
C12 L62 L72
Driver L22
VDr T2 D2
RGon C32
RGoff C42
C22 L32
E`2
L42 L52
L12 E2
Figure 3.23 Commutation circuit with parasitic elements
The effects of parasitic elements / counter-measures
Total commutation inductance

In the commutation circuit with T1 and D2, the amount of L11, L61, L31, L41, L72, L52 and L12 is
effective as total commutation inductance. In analogy, the amount of L11, L71, L51, L62, L32, L42
and L12 is effective in the commutation circuit with D1 and T2.
During active turn-on of T1 or T2, respectively, the total commutation inductance becomes
effective as turn-on relief, which will reduce turn-on power dissipation in T1 or T2 (see chapter
3.8).
However, during active turn-off of T1 and T2 as well as during reverse-recovery-di/dt of D1 and
D2, switching overvoltages are generated in the transistors and diodes due to high di/dt caused
by the commutation inductances. This will increase turn-off power dissipation and voltage stress
of the power semiconductors.
This effect is especially critical with regards to short-circuits and overload (see chapter 3.6).
Moreover, together with parasitic capacitances unwelcome high frequency oscillations may be
generated.
Therefore, it is of major importance to minimize inductances in the commutation circuit of hard-
switching converters. Except for L11 and L12, all inductances are generated in the modules, which
may not be influenced by the user. In this respect, it is up to the manufacturers of power
166
modules, to keep on working on the minimization of internal inductances by improving module

assembly technologies (see chapter 1.4).
SEMIKRON datasheets indicate the internal inductances becoming effective at the module
output terminals (Example: SKM100GB123D: LCE = max. 30 nH).
In the case of single switch modules (1 IGBT/MOSFET + 1 inverse diode), the connection of
both modules has to be made as low-inductive as possible in an converter phase.
Low-inductance DC-link power busbars are of special importance. This goes for the connection
busbars of the capacitor battery itself as well as for connection of the power modules to the DC-
link. In this respect, laminated busbar systems (tightly paralleled plate systems) adapted to the
specific inverter layout have gained general acceptance in practice, achieving busbar inductances
up to 20...50 nH. Some examples of this are shown in Figure 3.31.
The effects of the remaining inductances L11+L12 on the power semiconductors can still be
reduced by connecting C-, RC- or RCD-circuits directly to the DC-link terminals of the power
modules. In most cases, a simple C-circuit with film capacitors within the range of 0.1...2 F is
connected.
Inductances of emitter or source

The elements L31 or L32 of the emitter/ source inductances are effective in the power circuit as
well as in the driver circuit of the transistors.
Due to the fast di/dt of the transistor current, voltages will be induced which will have the effect
of inverse feedback in the driver circuit (emitter/source inverse feedback). This, however, will
decelerate the charging process of the gate-emitter-capacitance during turn-on and the
discharging of the gate-emitter-capacitance during turn-off, resulting in increased switching
times and switching losses.
The inverse feedback effect of the emitter may be utilized for limitation of the collector current
di/dt in the case of short-circuits near the modules.
To minimize the inductances L31 and L32, power modules are equipped with separate emitter
control terminals.
If several BOTTOM driver stages of a converter are supplied by a common operating voltage
with negative DC-link reference, the parasitic inductances between the ground connectors of the
drivers and the negative potential of the DC-link may cause unwelcome oscillations in the
ground loops. This problem can be solved by HF-stabilization of the driver operating voltage
near to the output stage or separate supply voltage potentials of the BOTTOM driver stages in
high-power inverters.
Inductance L21 and L22

Inductances L21 or L22, respectively, designate the inductance of the supply line between driver
and transistor. Apart from increasing the impedance of the driver circuit, they may cause
unwelcome oscillations with the input capacitance of the transistor. This may be remedied by a
short, low-inductance connection between driver and transistor.
Capacitances
The capacitances Cxx in Figure 3.23 stand for the intrinsic capacitances in the power
semiconductors (voltage-dependent, non-linear) and cannot be influenced by the user. They
indicate the minimum value of the commutation capacitance CK and, principally, effect a
reduction of power dissipations during turn-off (see chapters 0 and 3.8).
167
Additional power dissipations are generated during active turn-on due to the recharge process of
the commutation capacitances; these have to be considered in many high-frequency MOSFET-
applications (...100 kHz...).
C11 and C12 cause an inverse dv/dt-feedback to the gate (Miller effect, see Figure 3.35).
In combination with the inductances near the switches, the intrinsic component capacitances may
cause unwelcome oscillations.
3.4.2 EMI/mains feedbacks
3.4.2.1 Processes in the converter

Processes in a converter system will always produce unwelcome interference due to the
switching operation of the power semiconductors on the one hand (Figure 3.24) and welcome
energy transmission with the corresponding signal processing on the other hand.
Processes in the Converter
Power Conversion Noise Propagation Information Processing

(Main Function) (parasitic) (necessary)
Reactions to
EMC
Mains and Load
Energy Transmission Noise Source of Noise Source of Control of

between Mains and Load Power Conversion Information Processing Power Conversion
- High Power - Middle Power - Small Power - Small Power
- DC-Parameters,
Fundamental Harmonics - Higher Harmonics - Higher Frequencies - Higher Frequencies
High-Energy-Processes Low-Energy-Processes
Figure 3.24 Energy processes in converters [299]
These processes can be divided up into high-energy-processes, which may cause interferences in
the mains and the load within a frequency range between fundamental frequency and about
10 kHz, and low-energy-processes above 10 kHz up to about 30 MHz, where noise radiation
and, consequently, non-conducted current flow will start to be propagated. The frequencies
mentioned originate more or less from possible measuring procedures, and not from physical
effects. In the low-frequency range, these effects are called converter mains feedbacks, which are
168
traditionally characterized by discrete harmonic current oscillations up to about 2 kHz. Above 10

kHz these oscillations are called radio interference voltages, which are indicated in dB/V and
are designated as interference voltages due to selective measurements. For the interim frequency
range, within which modern power semiconductors are switched, the first attempts are currently
being made to introduce measuring procedures as well as limit ratings. Discussions on these
disturbing side-effects are contradictory, since the same physical processes are described under
different aspects. The difference between designations such as zero current, leakage current or
asymmetrical interference voltage is only given by various frequency range classifications and
by the frequency dependency of all switching parameters. Since this frequency dependency is
continuous just as the transition to radio interference, the frequency transition ranges are
inevitably very broad.
3.4.2.2 Causes of interference currents

All interference is caused by the switching operation mode of power semiconductors. Causes of
interference may be explained by the equivalent commutation circuit in Figure 3.25.
idm LK Module
Network 1 2 Network 2
icm1 CK
S1 2
iL
VK
idm CK
S2
LK 2
2
icm2
Baseplate
icm
Zch
ZN1 ZN1 ZN2 ZN2
Heatsink
Zhg
GROUND
Figure 3.25 Equivalent commutation circuit with noise propagation paths [299]
In the case of inductive commutation switch S1 will switch to the conducting switch S2.
In a hard switching process (LK = LKmin, CK = CKmin) firstly the current will be commutated with
a di/dt given by the semiconductor characteristics of switch 1. Commutation is finalized by the
reverse-recovery-di/dt of switch 2, which determines voltage commutation and, consequently,
dv/dt together with the current-carrying inductance and the effective capacitances CK. The
effective capacitances comprise all capacitances C which are effective towards the neutral
potential. Together with the impedances of the commutation voltage connections to the neutral
potential parallel impedances of the commutation capacitances will become effective. At the
169
beginning of the commutation process, the di/dt of switch 1 will cause a symmetrical current
flow idm within the commutation voltage capacitance and the parallel network 1. The dv/dt at the
end of the commutation process caused by the reverse-recovery-di/dt of switch 2 and the
inductance L, which serves as supply current, conducts the currents icm asymmetrically via the
ground line through the parallel lines to the commutation capacitances CK.
Transition to soft turn-on by increase of LK (ZCS, chapter 3.8) will reduce the di/dt and,
consequently, symmetrical current interferences. At the same time, the increased inductances LK
will become effective in the circuit of the asymmetrical interference current. Dv/dt, at the
beginning of the commutation process, is determined by the switching characteristics of S1. The
voltage leap at the end of the commutation process is determined by the reverse recovery current
behaviour of switch S2. Transition to soft switching in ZCS-mode will reduce current
interferences and will change the frequency range of asymmetrical currents, without reducing
them considerably, also see chapter 3.8.3.
The capacitive commutation process is started by active turn-off of switch S1.

In the hard switching procedure (CK = CKmin) the asymmetrical interference current is determined
by the impedances towards the neutral potential which become effective parallel to the
commutation capacitances and by the semiconductor characteristics of switch S1. The current
commutation following the voltage commutation and, thus, the symmetrical interference current
is determined by the turn-off behaviour of S1 and by the turn-on behaviour of S2.
An increase of CK will require a zero-voltage-switch with soft turn-off (chapter 3.8). The turn-off
process starts with the first stage of current commutation with a di/dt, that is determined by
switch S1 at a reduced voltage. The delayed dv/dt will reduce the asymmetrical currents during
voltage commutation. Passive turn-on of S2 determines the di/dt during the second stage of
current commutation. Asymmetrical current interference will be reduced by soft switching in
ZVS-mode without changing symmetrical currents noticeably. Nevertheless, the increased
capacitances CK will diminish the symmetrical interference current in network 1 in relation to the
capacitive current divider. Soft switching converter circuits with turn-on or turn-off phase-shift
control will reduce asymmetrical and symmetrical interference currents when using zero-voltage
switches or zero-current switches, respectively. In converter circuits with auxiliary commutation
arms, where ZVS and ZCS are switched alternately, interference currents will not be reduced
considerably in comparison to hard switching circuits, see chapter 3.8.3.
3.4.2.3 Propagation paths

In order to take measurements on radio interference voltages, voltage fluctuations at the mains
connections of inverter to ground are selectively measured. The potential fluctuations refer to a
defined point of ground, which is determined in standard measurements by connection of a line
impedance stabilization network. Regarding symmetrical and asymmetrical interference currents
within the frequency range of EMI, all simple low-frequency switching elements are equipped
with additional inductances, resistances and capacitances, which will render a clearer simulation
of their frequency dependency.
Figure 3.26 shows the example of a simple step-down converter circuit, where network 1 is
represented by the line impedance stabilization network (LISN) and network 2 by the applied
load in contrast to Figure 3.25.
170
Module Wire Load DC-Link Wire LISN
VS
IS
GROUND
GROUND
GROUND
Figure 3.26 EMI-equivalent circuit of a step-down converter [193]
The module simulates switches S1 and S2 including the commutation inductances and
capacitances. The origins of interference currents described beforehand are illustrated in a
simplified way, namely as current source IS for symmetrical interference currents and as voltage
source VS for asymmetrical interference currents. In both sources the measured semiconductor
characteristics are included as a function of time (Figure 3.27).
Figure 3.27 Typical voltage and current characteristics of an IGBT-switch (top characteristic in V, bottom in A)
[193]
Figure 3.28 shows simulated results with the example taken from [193] based on the model of
Figure 3.26; these results are almost fully in accordance with the measurements actually taken.
171
EMI-Spectrum OP 450 V / 20 A / 5 kHz
+VZ -V Z
Frequency
Switch Current Switch Voltage
Fourier-Analysis of Current Fourier-Analysis of Voltage
VS
Frequency Frequency
Differential Mode Spectrum Common Mode Spectrum
+VZ -VZ +VZ -VZ
Frequency Frequency
Figure 3.28 Simulation results of a 1200 V/50 A NPT IGBT dual module
Operation parameters: DC-link voltage VDC = 450 V
Load current = 20 A
Pulse frequency = 5 kHz
The influence of additional paths of propagation via energy and information transmission lines of
the driver circuits have been examined in [299].
172
3.4.2.4 EMI suppression measures

Conventional interference suppression is based on the use of customised filters, which are
attached to the mains supply of the device. According to the set limit characteristics for a certain
type of device (see example tables) various filters are applied by means of the line impedance
stabilization network and standardized test assemblies, until the limit values are kept in all
frequency ranges [259].
Table of engineering standards

GENERIC Engineering standard Application Interference factor
EN 50 082/1 VDE 0839, part 82-1 Residential, commercial EMI immunity
and trade applications,
EN 50 081/1 VDE 0839, part 81-1 small businesses Interference emission
EN 50 082/2 VDE 0839, part 82-2 Industry, EMI Immunity
EN 50 081/2 VDE 0839, part 81-2 power stations etc. Interference emission
Examples for existing product standards

Classification of equipment Product Standards Interference factor
ISM-devices (industrial, scientific and EN 55 011 Interference emission
medical HF-devices) Generic EN 50 082-1/2 EMI immunity
Radio and television receivers and EN 55 013 Interference emission
connected equipment EN 55 020 EMI immunity
Household appliances EN 55 014 Interference emission
Generic EN 50 082-1 EMI immunity
Fluorescent lamps and EN 55 015 Interference emission
lights Generic EN 50 082-1 EMI immunity
Data processing EN 55 022 Interference emission
systems prEN 55 101, EN 55 024 EMI immunity
In this mostly empirical procedure, often costly filters are used. It will be more effective to
design and construct a circuit, which considers, from the beginning of any development
processes, the effects of electromagnetic interference and the optimization of propagation paths
with respect to their origins and to possible measuring points. Optimization means either to
produce high-resistance propagation paths for interference currents by the application of
selective blocking circuits or to create low-resistance short-circuit paths for interference currents
by using selective suction filter circuits.
In the following, selected measures are explained with regards to Figure 3.25.
Symmetrical interference current circuits will be closed via the capacitance of the commutation
voltage source. Ideal capacitance connected to switches 1 and 2 without the influence of any line
impedances would be required for the creation of a short-circuit path for interference currents.
Measurable radio interference voltages will then be generated via the capacitive voltage ripple,
which will effect a current flow over the paralleled effective circuits. Therefore, all measures that
may be taken to reduce symmetrical inerference currents will aim at the arrangement of
corresponding suction filter circuits parallel to the connection lines of the commutation voltage.
All efforts in this respect can be reduced in relation to which extent the creation of a filter circuit
as near as possible to the switch connections may be achieved by nearly ideal capacitances and
active filters.
Principally, asymmetrical interference currents will be propagated via the ground line. For
interference suppression it seems to be important to have extremely high-resistance impedances
173
in all switching points with steep potential increases versus ground potential and, at the same
time, to limit the jumping potential to the non-avoidable switch connections. In the example of
the equivalent circuit in Figure 3.25, firstly, interference suppression could be managed by
reduced coupling capacitances of the drivers and capacitances effective via the module base plate
and the heatsink. If the drivers do not receive switching information and are not supplied with
auxiliary energy by the neutral potential, no shifted currents will be conducted via the earth line,
i.e. the circuit will be closed within the appliance. There will be no flow of asymmetrical
interference currents. Interference currents propagating over the base plate may be reduced by
applying shielding measures and different isolation materials [193]. With application of the
measures mentioned above (near to the semiconductor chips) a considerable reduction of
interference currents can be achieved, as shown in Figure 3.29 with the example of an especially
modified IGBT module [193].
EMI-Spectra NPT-IGBT-Module
dBV
100 Standard
80
60 Modified Module
40
20
0,01 0,1 f / MHz 1 10 30
Figure 3.29 Comparison of interference spectra of a standard IGBT module and an EMI-optimized IGBT module;
[193];
Operation parameters: DC-link voltage = 450 V
Load current = 20 A
Pulse frequency = 5 kHz
The connection to network 2 via the choke coil depicted in Figure 3.25 is not influenced by these
measures. The coupling capacitance of this connection line can only be reduced by shortening
the line as far as possible. Ideally, an L/C filter should be connected directly to the the jumping
potential so that the inductance of which will attenuate the potential jumps to such an extent that
all other coupling capacitances in network 2 will not be able to contribute considerably to the
asymmetrical interference current. If network 2 is the supply point of the mains where the
standard measurement using LISN is done then this measure will be inevitable, i.e. the L/C filter
has to be part of the EMI filter.
3.4.3 Power units ready for installation

SEMIKRON offers power units ready for installation both in module and MiniSKiiP or SKiiP
product range, which are designed according to the above mentioned standards and optimized
with respect to the characteristics of the applied power modules.
The functional spectrum may comprise

- input rectifiers with diodes, thyristors or transistors,
174
- laminated DC-links with Cu- or Al-sandwich busbars, electrolytic or film capacitors, HF-
blocking capacitors, balancing and discharge resistors,
- inverter legs with IGBT or MOSFET modules or SKiiPPACKS,
- liquid coolant or forced air heatsinks; fan optional,
- driver with protection functions, sensors, power supply and potential isolation.
Before delivery, all power units have to pass application-specific functional testing.
Powerboards with MiniSKiiP

Figure 3.30 shows view and block diagram of a SKiiP025HAB powerboard with MiniSKiiP 8
layout for up to 15 kW power output at a line supply voltage of 400 V .
Controller Interface
Detections
Driver and VDC IGBT-Sixpack Current Temperatur

SCR-Driver Detection for Detection
DC-Link-Chopper Driver Detection Detection
a) Power Terminals
b)
Figure 3.30 Powerboard SKiiP 025HAB/NAB

a) Block diagram b) View (without fan)
MiniSKiiPs SKiiP 83 ANB15 (diode rectifier and brake chopper / version NAB) or SKiiP
AHB15 (half-controlled thyristor rectifier and brake chopper / version HAB) as well as SKiiP
83 AC12I (three-phase inverter with IGBTs 120A @ 25C and AC current sensors), DC-link
(700 F), potential-separated driver, power supply, overcurrent, overtemperature and
undervoltage protection and a DC-link charge circuit (for version HAB) are integrated into a
central PCB of the powerboard.
175
The PCB is mounted on to the heatsink via the MiniSKiiP components and additional support
pins.
SKiiP power units

SKiiP power units are equipped with one or several integrated SKiiPPACKs (also connected in
parallel), a sandwich DC-link and optional rectifiers, fans and additional snubber circuits, if
required by the customer.
Figure 3.31 shows different SKiiP-types with vertical or horizontal DC-link construction.
a) b)
c)
Figure 3.31 Construction types of SKiiP power units

a) Flat construction for wide switchboards
b) Vertical standard DC-link
c) SKiiP-RAC with IGBT rectifier and converter
For power supply voltages from 230V up to 690V all available SKiiPPACKs may be integrated
into SKiiP power units. Power outputs up to MW-range may be produced by paralleling
SKiiPPACKs, using either SEMIKRON standard heatsinks or, optionally, nearly any other
forced air or liquid coolant heatsinks supplied by the customer.
Figure 3.32 shows the example of a SKiiP power unit for a rectified 690 V mains (DC-link
voltage up to 1200 V), comprising 3 SKiiPPACKs SKiiP 1092GB170-474 CTV with fibre optic
inputs, a sandwich DC-link construction totalling up to 8.8 mF /1350 V and a radial fan. At a
pulse frequency of 3 kHz and a supply air temperature of 35C the effective output current
(50 Hz) will value up to 250 A during continuous operation and to 375 A for operation period of
1 min/10 min.
176
Figure 3.32 300 kVA inverter unit with SKiiPPACKs
Power units with SEMITRANS IGBT- or MOSFET-modules

For applications, where SKiiPPACK or MiniSKiiP power units will not be sufficient, assemblies
with SEMITRANS modules, SEMIDRIVERs, standard heatsinks and laminated DC-links may
be a solution. These can also be subjected to application-specific testing, if required.
The power units described above, which are characterized as sub-systems by nature, require a
different dimensioning by user and manufacturer compared to modules.
In this respect, SEMIKRON offers their calculation programme SKiiPsel to SKiiP and
MiniSKiiP customers as a tool for pre-selection and rough dimensioning, see chapter 3.10.2.
Further steps may then be co-ordinated by means of a checklist, which should consider, among
other things, the following technical aspects:
- application, power flow direction(s), circuit structure, required functions,

- mounting dimensions (size, weight), special requirements (oscillations, shock load, etc.),
- input (mains, generator, battery,etc.), input voltage range, cos , special requirements; for
mains feedback: fundamental frequency, pulse frequency, DC-link voltage,
- output (mains, transformer, DC-motor, AC-motor, reluctance motor, etc.), output voltage
range, output current, cos , overload (value/duration/frequency), fundamental frequency
(min./max.), current at min. fundamental frequency, pulse frequency, load cycles (current,
voltage, frequency, cos as a function of time),
- DC-link (electrolytic or film capacitors), rated voltage, min./max. capacitance, max. DC-link
voltage, ambient DC-link temperature,
- isolation test voltages, type of protection,
- driver, driver interface (transformer, optical), options (sensors for current, temperature, DC-
link voltage),
- cooling: ambient temperature/coolant temperature min./max; for natural air cooling: max. air
volume, admissible noise level,
- for liquid cooling: cooling medium (antifreeze, volume, rate of flow),
177
- storage temperature, special requirements with respect to climate, extreme altitude over NSL,
- required module life (power modules, DC-link capacitors).
3.5 Driver
3.5.1 Gate voltage and gate current characteristics

Driving process
As already described in chapter 1.2.3 the switching behaviour of MOSFET and IGBT modules
can be greatly controlled by recharge the gate capacitance.
In theoretical borderline cases, the gate capacitance recharge may be controlled by resistance,
voltage or current (Figure 3.33).
RG
C
G G G
iG
VGG G
VGG
E E E E
a) b) c)
Figure 3.33 Gate driving process for MOSFETs and IGBTs [194]
a) Control by resistance b) Control by voltage c) Control by current
The preferred variant is to drive the system via a gate resistor (or two separate resistors for turn-
on and turn-off) according to Figure 3.33a. Characteristic of this variant is the Miller plateau in
the gate-source or gate-emitter voltage, respectively (Figure 3.34). The switching speed is
adjusted by RG at a continuous supply voltage VGG; the smaller the RG, the shorter the switching
times. The disadvantage of resistance control is that the gate capacitance tolerances of the
MOSFET or IGBT will have direct influence on switching times and switching losses.
Impressed voltage at the transistor gate driven according to Figure 3.33b will eliminate this
influence; the switching speed of the transistor is directly determined by the gate dv/dt. Thanks
to this voltage no Miller plateau will be formed in the gate voltage characteristic. This requires
sufficient driver current capacity.
Current control by a positive and negative gate current generator, as shown in Figure 3.33c,
determins the gate charge characteristics (see Figure 1.12 and Figure 1.13) and is comparable to
resistance control with respect to gate voltage characteristics.
Control voltage ratings

Figure 3.34 shows the characteristics for gate current iG and gate-emitter voltage vGE in a
resistance controlled circuit.
178
vGE (5 V / Div)
iG (0,4 A / Div)
a) 0,2 s / Div
vGE (5 V / Div)
iG (0,4 A / Div)
b)
0,2 s / Div
Figure 3.34 Gate current and voltage characteristics during turn-on and turn-off
a) Turn-on b) Turn-off
The control voltage VGG for both polarities has to be dimensioned according to the electrical
strength of the gate isolation, which is usually indicated as 20V for current power MOSFETs and
IGBTs. This value may not be exceeded - not even transiently - which might require special
measures during turn-off, see chapter 3.5.2 and 3.6.3.2.
On the other hand, RDS(on) and VCEsat, respectively, will decrease when the gate voltage increases,
and, therefore, we recommend applying a positive control voltage, which delivers a gate voltage
of
VGS = +10 V for power MOSFETs and

VGE = +15 V for IGBTs
during stationary on-state. Most datasheet ratings are based on these measuring parameters.
As demonstrated in Figure 3.34, the gate voltage for IGBTs should be negative to the emitter
potential during turn-off and off-state; recommended values are -5...-8...-15 V.
179
This will maintain a negative gate current during the complete turn-off procedure (even if VGE
approaches VGE(th)) sufficiently to draw the main share of positive charge carriers from the n--
drift zone by means of a high dvCE/dt during turn-off time and, thus result in a short tail current.
Another, more serious disadvantage of blocking the IGBTs of a bridge circuit with VGE = 0 V
will occur during the reverse-recovery of the parallel inverse diode of the turned off transistor
because of the dvCE/dt (Figure 3.35).
vGE1
vGE(th)
vGE2 tdead
iC1 iF1
Driver
RG
+15V/0V
T1 D1
vGE1
iF2, vCE2
CGC2 iL
iC2 iL iF2 vCE2
iV
RG D2
Driver vCE2
+15V/0V
vGE2 T2 iF2
iC1, iC2
iC1 = iL + iC2 -iF2
a) iL
iC2
b)
Figure 3.35 Cross current in an IGBT bridge arm due to turn-on by dvCE/dt-
feedback of T2
a) Switching principle b) Current and voltage characteristics
The high dvCE/dt of the collector-emitter voltage vCE2 during the reverse-recovery-di/dt of D2
will effect a displacement current iV through the gate-collector capacitance CGC2, also see chapter
1.2.3
iV = CGC * dvCE/dt.
This displacement current, in turn, will cause a voltage drop over the resistance RG (or RGE/RG).
If, as a result of this, vGE rises and exceeds the threshold voltage VGE(th), T2 will be driven to its
active region during the reverse-recovery-di/dt (cross current, additional power dissipation in T1
and T2).
Other than with IGBTs, the application of a stationary negative gate-source voltage during off-
state is not recommended for driving power MOSFETs. Parasitic turn-on with all consequences,
as described above, is done within the MOSFET too at the same time. However, it will protect
the transistor structure of the MOSFET, which is only limited resistant to dv/dt. The equivalent
circuit of a power MOSFET (Figure 1.3) demonstrates the displacement current through CDS to
the base of the parasitic npn-bipolar transistor as a result of dvDS/dt. If the voltage drop at the
lateral p-well-resistor RW reaches threshold voltage level, the bipolar transistor will be turned on
parasitically, which may lead to destruction of the MOSFET by power dissipation during
periodic operation.
180
Parasitic turn-on of the MOSFET channel at VGS = 0 V over CGD will reduce dvDS/dt during
blocking state and will weaken the dangerous effect of bipolar transistor turn-on (see Figure
3.35).
Control current ratings, driving power

The total driving power PGavg to be delivered by the driver circuit can be determined from the
gate charge QGtot (see Figure 1.12 and Figure 1.13):
PGavg = (VGG + + VGG ) Q Gtot f s with Q Gtot = C Equiv. (VGG + + VGG )
Peak gate current values are calculated as follows:
I GMon = (VGG + + VGG ) / R Gon (ideal)
I GMoff = (VGG + + VGG ) / R Goff (ideal)

Driver power is calculated as follows:
P(VGG + ) = VGG + Q Gtot f s fs = switching frequency
P(VGG ) = VGG Q Gtot f s
Example: VGG+ = 15 V, VGG- = -15 V, RG = 3.3

QGtot = 2.3 C (SKM500GB123DS)
fs = 10 kHz, VDC = 600 V
Resulting in: I GMon = I GMoff = 9.09 A

PGavg = 0.69 W
P(VGG + ) = P(VGG ) = 0.345 W
I(VGG + ) = I(VGG ) = 23 mA (average)
3.5.2 Influence of driver parameters on switching features

As already mentioned, important features of driven power MOSFETs or IGBTs are dependent on
VGG+, VGG- and RG ratings. The following table shall give a first overview (<: increases,
> decreases, -: remains):
Rating/ characteristic VGG+ < VGG- < RG < see chapter
RDS(on), VCEsat > - - 3.5.2

ton, > < < 3.5.2
Eon > - < 3.5.2
toff < > < 3.5.2
Eoff - > < 3.5.2
turn-on peak current *) < - > 3.5.2
turn-off peak voltage *) - < > 3.5.2
dv/dt-sensitivity (MOSFET) < < > 3.5.1
( IGBT) < > < 3.5.1
actively limited ID, IC < - < 3.6.2
ruggedness to load short-circuits > - < 3.6.2
*) during hard switching under ohmic-inductive load
181
Forward characteristics (RDS(on), VCEsat)

The dependences of the forward characteristics of power MOSFETs and IGBTs on the drive
parameters can be read from their output characteristics (see chapter 1.2.2). In Figure 3.36 this is
explained with one example each for SEMITRANS-MOSFETs and IGBTs taken from the
current datasheets.
a) b)
Figure 3.36 Forward characteristics versus control voltage (gate voltage)

a) Power MOSFET-module SKM 111
b) IGBT-module SKM100GB123D
In SEMITRANS, SEMITOP and MiniSKiiP datasheets the recommended maximum ratings and
characteristic values mentioned in chapter 3.5.1 are indicated with VGG+ = 10 V for power
MOSFETs and VGG+ = 15 V for IGBT modules which is an acceptable compromise in
conventional applications between power dissipations, turn-on peak current and short-circuit
behaviour.
Switching times, switching losses (ton, toff, Eon, Eoff )

Control voltages and gate resistances will affect the various parts of turn-on time ton = td(on) + tr,
turn-off time toff = td(off) + tf and tail time tt of the IGBT in different ways:
Since the gate capacitance amounts to absolute ratings of VGG+ and VGG- before switching, the
recharge time will decrease (turn-on delay time td(on), turn-off delay time td(off)) on condition of a
given gate resistor RG if the recharge current or (VGG+ + VGG- ) increases.
On the other hand, switching times tr and tf and, consequently, energy dissipations Eon and Eoff
may only be affected by the switching control voltages VGG+ or VGG-, since they determine the
current flow through the gate resistor RG.
SEMITRANS-IGBT datasheets include diagrams showing the dependences of switching times

and energy dissipations on RG, measured for maximum current ratings IC @ 80C on condition of
hard switching under ohmic-inductive load (Figure 3.37).
182
a) b)
Figure 3.37 IGBT-switching times (a) and switching losses (b) of SKM100GB123D versus gate resistor RG at
Tj = 125C, VCE = 600 V, IC = 75 A, VGE = 15 V and on condition of hard switching under ohmic-
inductive load
Switching behaviour of free-wheeling diode and turn-on peak current of transistor

The turn-on energy dissipation of the IGBT indicated in Figure 3.37b already includes the
influence of the turn-off behaviour of the integrated free-wheeling diode on turn-on peak current
and turn-on power dissipations, see chapters 1.3.3.3 and 2.3.3.
a) b)
Figure 3.38 SKM100GB123D CAL-diode recovered charge Qrr (a) and peak reverse recovery current IRRM (b) versus
commutation speed diF/dt of diode current
The drain or collector current (iD, iC) rise time tr will decrease with rising gate current (higher
VGG+ or lower RG). This in turn will increase the current commutation speed diF/dt in the free-
183
wheeling diode, by which recovered charge Qrr and peak reverse recovery current IRRM are
determined.
These characteristics of CAL-diodes used in SEMITRANS-IGBT-modules are depicted in the
datasheets (Figure 3.38 and 3.39).
Increase of Qrr and IRRM will cause higher turn-off power dissipations in the internal free-
wheeling diode.
Since a higher diF/dt will result in an increase of Qrr and IRRM and, since IRRM is added to the load
current within the collector or drain current, turn-on peak current and turn-on energy dissipation
of the transistor will increase with its turn-on speed (Figure 3.37).
Figure 3.39 CAL-diode turn-off energy dissipation EoffD in a SEMITRANS IGBT-module SKM100GB123D
versus RG
Turn-off peak voltage

If either VGG- is increased or RG is decreased, the turn-off gate current of the driven transistor
will rise. As shown in Figure 3.37a, the drain or collector-current fall time tf will decrease, i.e.
-diD/dt or -diC/dt will increase. The voltage u = -L * di/dt induced during di/dt over the
parasitic commutation circuit inductance L will increase linear to the decreasing turn-off time.
3.5.3 Driver circuit structures and basic requirements on drivers

Figure 3.40 shows the basic structure of a comfortable driver circuit for one MOSFET- or
IGBT-bridge arm with TOP/BOTTOM interlock and protection functions close to the gate.
In the depicted driver, TOP and BOTTOM switches and signal processing unit are separated by
real potential isolation for control signals, control power and feedback of output and error
signals. In simple driver circuits these potential isolations may be combined (common energy
and signal transmission) or they are partly or even completely omitted (e.g. bootstrap circuits for
TOP voltage supply). Low-voltage switches or low-side choppers especially (only BOTTOM
switch is active) only require a very simplified driver structure, since single switches can be
realized without most interlock and dead-time functions.
184
error
IC, VDC
detect.
fast protection
input pulse Gate

STOP
buffer shaper protect.
pulse
shaper,
DC/DC-Converter
interlook VGG+
deadtime VGG-
&
VGG+
short VGG-
pulse
supres-
sion
input pulse Gate
SBOTTOM
buffer shaper protect.
VGG fast protection

watch
STATE
error error
latch IC
RESET detect.
Thmeasur.
Galvanic Isolation
Figure 3.40 Block diagram of bridge arm driver circuit with TOP/BOTTOM interlock and protection (IGBT driver)
The gate unit is the core part of the driver circuit and consists (mostly) of primary-side time
control stages for delay, interlock and minimum on and off times (see chapter 3.5.4), potential
isolation (with pulse shapers, if necessary) and a generator for positive/negative gate control
voltage. The power transistor gate may also be equipped with overvoltage protection, combined
with an active clamping for vDS or vCE (see chapter 3.6).
Figure 3.41 shows the principle of a generator for positive and negative gate control voltage
(designed for IGBTs with negative gate-emitter voltage).
Apart from the complementary source follower boosters with low-power MOSFETs, for
example, complementary drain or collector followers and totem-pole drivers with MOSFETs or
bipolar transistors are also commonly used [277].
Further solutions including integrated components are referred to in chapter 3.5.6.
185
GND
C
VGG+
RGon iG
Rin
RGoff
RGE
VGG-
C GND
GND
Figure 3.41 Turn-on and turn-off gate voltage generator
The gate resistance RG in Figure 3.41 has been divided up into two resistors RGon and RGoff for
turn-on and turn-off, respectively. By this means, the mostly inevitable cross current from VGG+
to VGG-, generated during switching of the driver MOSFETs, can be limited. The main
advantage, however, is that this solution offers the possibility of separate optimization of turn-on
and turn-off with regard to turn-on overcurrent and turn-off overvoltage (see chapter 3.5.2) and
to short-circuit behaviour (chapter 3.6.2). If only one output is available for RG, this function can
also be maintained by paralleling RGon and RGoff. Diodes connected in series to the resistors
should be arranged so that the cathode is directed towards the IGBT-gate for RGon and the anode
is directed towards the IGBT-gate for RGoff.
The gate-emitter resistor RGE (10... 100 k) should not be omitted in any application, since it
prevents unintentional charging of the gate capacitance even under driver operating conditions
with highly resistive output levels (switching, off-state and driver supply voltage breakdown).
The low-inductive capacitors C (0.22...1 F) serve as a buffer for VGG+ and VGG- near the driver
output and have to keep up a minimum dynamic internal driver resistance together with the low-
resistive driver circuit. Only under these circumstances the driver will be able to absorb
displacement currents due to dvCE/dt which are conducted via Miller capacitance to the gate and
are likely to cause switching failures, parasitic oscillations or inadmissible gate overvoltages.
Moreover, the following aspects have to be considered for the gate voltage generator layout:
- minimum parasitic inductances in the gate circuit, e.g. short (<< 10 cm), twisted connection
lines between driver and gate/ driver and emitter; minimum size of circuit arrangement
according to Figure 3.41
- elimination of feedback of load current to gate voltage caused by the parasitic emitter
inductance in the power module: connection of driver ground to the power module control
emitter,
- avoidance of ground loops,
- avoidance of transformative and capacitive coupling between gate and collector circuit (no
paralleling of critical tracks or wires; integration of shielded areas).
186
Of course, these requirements also have to be met by the potential isolated supply of the buffer
energy (e.g. by a switch mode power supply integrated in the driver) and by all other functional
units on the power transistor potential.
Low-pass filters, pulse shapers and pulse width triggered flip-flops integrated in the signal
transmission paths for interference suppression have to live up to the permissible minimum pulse
duration and the necessary response times to failures with regard to their delay times.
3.5.4 Integrated protection and monitoring functions of a driver

To protect MOSFET or IGBT modules in case of failure, the implementation of a variety of fast
responding and efficient protection functions in the driver is recommended, such as overcurrent
and short-circuit protection, protection from excessive drain-source or collector-emitter voltage,
gate overvoltage protection, overtemperature protection and monitoring of gate control voltages
VGG+ and VGG-.
With reference to Figure 3.40, the integration of protection functions in the driver is explained in
the following. Realization and dimensioning aspects are dealt with in chapter 3.6.
Overcurrent and short-circuit protection

The current signal can be generated as an analogous signal (measured via e.g. shunt, current
probe, RDS(on) of the driven power MOSFET or sense-source or sense-emitter-cells) or as a
maximum rating excess (desaturation of the IGBT). As soon as an error has been detected by
comparing the actual value to a fixed maximum rating, an error memory is set (ERROR status)
either already on switch potential or - in the case of potential-isolated sensors - in the primary
circuit of the driver, which will block the power transistors until the RESET-signal is triggered.
If the error memory is integrated on the secondary side, its state signal will be transmitted to the
primary side by a potential-isolated unit. In the case of integration of potential-isolating high-
precision current sensors - as for example in SKiiPPACKs and some MiniSKiiP-components -
their output signal may serve as actual value for control loops or for detection of ground currents.
Gate-overvoltage-protection
In contrast to all protection functions described so far, the gate protection has to limit periodicly
to the gate voltage without detection of an error which would require turn-off of the power
transistors. Therefore, there is no connection to the error memory. More details are described in
chapters 3.6.1 and 3.6.3.
Protection from excessive drain-source or collector-emittervoltage

Voltage limitation at the main terminals of a power transistor can be realized by the transistor
itself (avalanche-proof MOSFETs), by passive networks or by an active circuit, which realizes a
defined partial turn-on of the transistor in case of overvoltage (see chapter 3.6.3).
A simple protection, which is not able to detect switching peak voltages and other fast
overvoltage peaks, may (option U) be optionally integrated into the SKiiPPACK driver as a
static DC bus voltage monitoring. A quasi potential isolated sensor will indicate the actual DC
bus voltage value and transmits it to the main control circuit as analogous actual value and sets
the error memory to ERROR as soon as the limit value has been exceeded. Moreover, a brake
chopper buffer may protect for example the DC-link capacitors in case of load energy feedbacks
active loads).
187
Overtemperature protection
The temperature of the power transistor chips and the heatsink temperature near the chips can be
determined by the calculation methods described in chapter 3.6.3.3. If the sensor is isolated, the
temperature signal (e.g. voltage) may also be transmitted to a main control circuit. A threshold
switch on the primary side will set the error memory to ERROR as soon as a limit value has been
exceeded.
Supply undervoltage protection of the gate control voltages VGG+ and |VGG-|.
If the gate control voltage drop considerably, the secondary control, protection and transmission
functions may fail. Moreover, the power transistors can no longer be fully controlled or blocked.
In order to detect this critical state in time, either one of the control voltages or the function of
the internal power supply of the driver has to be monitored. In case of failure the error memory is
set to ERROR.
3.5.5 Time constants and interlock functions
Short-pulse suppression
When pulse transformers or opto-couplers are used for potential isolation of the control signals,
the driver has to be especially protected from too low or too short control impulses (interference
impulses) which might cause failure of the driver.
Schmitt-triggers, for example, can be connected in series to the potential isolation, which will
suppress all turn-on- or turn-off-signals lower than logic level (CMOS, TTL) or < 0.2...0.5 s. A
similar solution may be applied to the secondary side of opto-couplers.
Dead-time for bridge-arm control and arm short-circuit interlock

MOSFETs and IGBTs of the same bridge arm must not be switched on at the same time in
voltage source circuits, to avoid a bridge arm short-circuit.
In the static state this may be avoided by interlock of both drivers even if the driver input signals
are affected by interferences (not suitable for current source circuits because overlapping
operation of the drivers would be required).
Depending on the type of transistor, specific application and driver, the dead time has to total up
to tdead = 2...10 s.
Gating time of a short-circuit protection with measurement of drain or collector current and
drain-source or collector-emitter-voltage, respectively
If the transistors are to be turned off because one of the limit values of the given measurement
parameters has been exceeded, the turn-on peak current has to be gated from the measurement.
When monitoring the desaturation process of an IGBT, the dynamic saturation voltage
characteristic has to be considered too. During the first microseconds of the turn-on time
VCEsatdyn is considerably increased compared to its final value VCEsat (Figure 3.42). Therefore, the
monitoring circuit should respond according to the course of vCEsat during a gating time as
indicated in Figure 3.42. For the sake of safe short circuit protection, the gating time is only
allowed to amount to 10 s max. (see chapter 3.6).
188
Figure 3.42 Dynamic saturation voltage characteristic of an IGBT and possible protection level Vref
3.5.6 Transmission of control signal and driving energy

ontrol signal and driving energy have to be transmitted from the control unit to the driver stage,
which, in return, has to send out state and error signals and, if required, analogous measurement
values (current, temperature, DC bus voltage (optional)).
+ +
STOP STOP STOP STOP

PTOP PTOP PTOP
~ ~ ~ P ~
SBOT SBOT SBOT SBOT
PBOT PBOT PBOT

a) c)
- -
PBOT
+
PTOP
SBOT STOP
SBOT
PBOT ~
SBOT
b) SBOT
d)
-
Figure 3.43 Selected signal and energy transmission principles

STOP, SBOT: control signal for TOP/BOTTOM-switch
PTOP, PBOT: driving energy for TOP/BOTTOM-switch
a) Maximum variant b) Common energy supply of BOTTOM-drivers
c) Bootstrap principle d) Level-shifter principle
189
In most applications signals are transmitted via optical or transformatory (inductive) potential
isolation or via quasi potential isolations, such as bootstrap circuits or level-shifters.
Figure 3.43 shows the scheme of the most important configurations of signal and energy
transmission.
Figure 3.43a shows the most common configuration with potential isolations for control signal
(S) and driving energy (P), one for each driver circuit. This configuration is preferred (except for
low-cost applications) because of its high degree of interference immunity and minimum mutual
influence of the switches.
Variant b) contains separate potential isolations for the control signal of all BOTTOM-drivers,
but only one common potential isolation for the driving energy of the BOTTOM-drivers .This is
used mainly in low-power applications and preferred in many IPMs.
The principle of a bootstrap circuit for energy supply of the TOP-switch without a real potential
isolation is depicted in Figure 3.43c. Figure 3.43d shows the scheme of a level-shifter, where the
control signal STOP is transmitted without galvanic isolation via a high-voltage current source.
The simplest solution for applications with very low switching times is to drive the gate directly
by means of an pulse transformer, which will transmit the control signal modulated in the driving
energy (AC voltage) [277].
The most important requirements to potential isolation are high isolation voltage (2.5...4.5 kVeff)
and sufficient dv/dt-ruggedness (15...75 kV/s).
A high dv/dt-ruggedness can be realized by small coupling capacitances within pF-range from
the primary to the secondary side. This will minimize signal transmission interferences caused
by displacement currents during switching (Figure 3.44).
Cps1
prim
sec S1
signal
BOTTOM
BOTTOM
VS P7 S9 output 2
input 2 (BOTTOM)
internal
power CSS
supply
input 1 (TOP)
P14
sec
signal
TOP
TOP
S20 output 1
Cps2
Figure 3.44 Equivalent coupling capacitances in a halfbridge driver with potential isolation
Cps1: Capacitance between primary and TOP-secondary side
Cps2: Capacitance between primary and BOTTOM-secondary side
Css: Capacitance between secondary side TOP and BOTTOM
190
3.5.6.1 Control data and feedback

The following table contains the currently most common transmission units with and without
potential isolation and their most important features.
Potential isolation transformatory optical optical none
System Pulse transformer Opto- Fiber optic Level-shifter

coupler link
for power modules up to > 1700 V 1700 V > 1700 V 1200 V
Transmission directions bi-directional uni- uni-/bi- uni-directional

directional directional
Duty cycle restriction yes no no no
Coupling capacitance 5...20 pF 1...5 pF < 1 pF > 20 pF
dv/dt-immunity high low high low
Costs medium low high low
Supported by additional circuitry, pulse transformers are able to transmit feedback signals as
state informations during break times of the driver (e.g. dead time in halfbridge circuits); fiber
optic links equipped with double transmitters / receivers will work the same way.
Analogous output signals may be fed back from the driver to the main control unit for example
in a pulse-width modulated state by additional pulse transformers, opto-couplers or fiber optic
links.
The potential isolation is already integrated in current probes with Hall-sensors or compensated
magnetic sensors.
3.5.6.2 Driving energy

The basic, currently applied solutions and their most important features are mentioned in the
following:
Potential isolation transformatory none
System 50 Hz-power Switch-mode Bootstrap-circuit

supply power supply
Supplied by Auxiliary Auxiliary DC-link Operating voltage

voltage or voltage on BOTTOM-side
mains voltage
AC-frequency low very high medium medium (pulse fr.)

smoothing requirements high very low low low
for power modules 1200 V >1700 V 1700 V 1200 V
191
Output voltage positive and positive and negative only positive

negative
Duty cycle restriction no no no yes
Coupling capacitance high low medium low
Interference emission none high low none

(HF)
Costs low low high very low
3.5.7 Driver circuits for power MOSFETs and IGBTs

In most cases, modern drivers are equipped with monolithical driver ICs which are available as
single, half-bridge and full-bridge drivers in a large variety.
The function spectrum of these circuits mostly comprises:
- gate voltage generator;
- input for VCEsat- or VDS(on)-monitoring, sometimes also input for shunt or sense-emitter;
- supply undervoltage monitoring;
- error memory and error feedback output ;
- adjustable dead time generation and bootstrap power supply of the TOP-driver.
These standard drivers do not provide a real potential isolation. For some variants, the control
input may be configured for connection of opto-couplers or pulse transformers.
Moreover, progress is being made in the development of fast opto-couplers with power driver
output which have already integrate supply undervoltage- and VCEsat- or VDS(on)-monitoring. To
achieve simple driver units, a DC/DC-converter and few passive components merely have to be
added.
With the growing variety of function and protection parameters in driver circuits, the assemblies
necessary on the primary side also have to live up to more sophisticated requirements
comprising, for example, input signal logic, short-pulse suppression, dead time generation, error
memory and error evaluation, control of the DC/DC-converter and drive of the pulse
transformers.
For the production of low-cost driver circuits, these functions have been combined in a control-
ASIC developed by SEMIKRON called SKIC 2001 [154]. The SKIC 2001 is applied in
SEMIKRON drivers and is also available as a single IC.
3.5.8 SEMIDRIVER
SEMIDRIVERs are driver components for IGBT and MOSFET power modules (single switches,
bridge arms or 3-phase inverters) integrating mainly those function parameters depicted in the
block diagram of Figure 3.40. They are being produced in different types either as SKiiPPACK-
drivers or OEM-drivers for IGBT and MOSFET power modules.
192
3.5.8.1 OEM-drivers [225], [264], [272]

The following table shows a survey on the most important OEM-SEMIDRIVERs and their main
features.
SKHI 10, 21A, 22A,B 23/12, 24 26W, 27W, 61 BS01, SKAI
10/17 22A,BH 23/17 26F 27F 71 BS02 100
4
Driver A B B B B B B D/DL DL L
Type PCB Hybr. Hybr. PCB Hybr. PCB PCB Hybr. Subpr. PCB
Viso/kV, 4 2.5 2.5 4 4 2.5 4 2.5 2.5 2.5
AC1min 4
Signal I I I I I I I OC OC OC
trans- (FO) (FO) FO FO
mission
VGG+/V 15 15 15 15 15 15 15 15 15 15
VGG-/V -8 0 -8 -8 -8 -8 -8 -6.5 -8 0
IGAV/mA 100 40 40 50 80 100 150 20 15 90
IGM/A 8 8 8 8 1.5 8 30 2 1 1.5
dv/dt/ 75 50 50 75 50 75 50 15 15 50
kV/s
VCEsat- 600 600 600 600 600 600 600 600 - 600
monitoring 1200 1200 1200 1200 1200 1200 1200 1200 - 1200
for VCE/V 1700 1700 1700 1700 (1700) 1700
Short- + - - + - + + + - -
circuit soft
turn-off
A: Single driver D: Driver for three-phase inverter

B: Bridge arm driver (Dual) L: Driver for brake chopper
I: Pulse transformer DL: Driver for three-phase inverter and brake chopper
FO: Fiber optic link (): Interface optional
OC: Opto-coupler *: TOP-switch (BOTTOM-switch: 10kV/s)
Features valid for all SEMIDRIVERs are:

- Power supply +15 V on information potential (SKAI 100 also 24 V); integrated SMPS with
potential isolation,
- 15 V-C-MOS and/or 5 V TTL-compatible inputs with potential isolation using pulse
transformers or opto couplers,
- Short-circuit protection via VCE or current sensor inputs (SKHIBS 01/02),
- Supply undervoltage monitoring < 13 V,
- Error memory and error feedback output,
- Variable dead time between driver TOP and BOTTOM for bridge arms,
- Short-pulse suppression.
For the SKHI 24 and SKHI 22B it is possible to cancel the dead time between TOP and
BOTTOM and, thus to drive the TOP and BOTTOM switch synchrounously or in overlap mode
(e.g. CSI topologies).
Figure 3.45 illustrates which IGBTs of the SEMITRANS product range may be driven up to
which switching frequency by the drivers mentioned on the top of each diagram. For this, the
rated IGBT current IC@25C has been plotted in the ordinates. The diagrams are valid for
SEMIKRON modules with the voltage grade designations and series numbers 063 (600 V), 123
(1200 V) and 173 (1700 V). For other IGBT modules the values have to be adapted to the input
capacitances of the IGBTs which may vary from generation to generation.
193
SKHIBS 01/02 Recommended Application Range SKHI 61 Recommended Application Range

300 400
Rated IGBT Current @ 25C
600 V

600 V
1200 V 1200 V
300
200
/ Ampere
/ Ampere
200
100
100
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
f / kHz f / kHz
SKHI 22 Recommended Application Range SKHI 22 A/B Recommended Application Range

1000
500

600 V 600 V
1200 V 1200 V
750
1700V 1700 V
/ Ampere
/ Ampere
500
250
250
0
0
0 5 10 15 20 25 30 35
0 5 10 15 20 25 30 35
f / kHz
f / kHz
SKHI 10 Recommended Application Range SKHI 23 Recommended Application Range

3000 1500
600 V
600 V
1200 V 1250 1200 V
1700 V
2000 1000 1700 V
/ Ampere
/ Ampere
750
1000 500
250
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
f / kHz f / kHz
SKHI 26 Recommended Application Range SKHI 27 Recommended Application Range

4000 5000
600 V
1200 V 600 V
1700 V 4000 1200 V
3000
1700 V
/ Ampere
/ Ampere
3000
2000
2000
1000
1000
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
f / kHz f / kHz
194
SKHI 24 Recommended Application Range
1750
600V
1500
1200V
1250 1700V
1000
750
500
250
0
0 5 10 15 20 25 30 35
f / kHz
Figure 3.45 IGBT current and switching frequency ranges of SEMIDRIVERs
3.5.8.2 SKiiPPACK-drivers [112], [264]

All SKiiPPACK drivers mentioned in chapter 1.5.1 and 1.6 have been optimized with regard to
IGBT chips and inductances within the SKiiPPACKs, which guarantees optimal utilization of
chips, high interference immunity and a high degree of failure protection.
As an example, Figure 3.46 shows the block diagram of a SKiiPPACK dual module GB-driver.
innovation + service +UZK

option U :
analog DC link voltage monitoring
UDC_analog DCB
analogue
temperature
output
TOP
short pulse pulse high side power
+ supression transformer flip flop driver
VGE
DCB > max TOP TOP TOP TOP
option F:
fiber optic
link (TOP, ERR,
+15V stabilised
BOT)
TOP X10
input pulse shaper
14 + U
buffer DC / DC X11
interlock converter -8V
TOP TOP
deadtime X12 I
default:D=3sec;
fast turn off
X1 BOT primary side
option 1 : D=0;
input option 2: no
+15V stabilised
buffer interlock
BOT BOT
1
inhibit -8V
error latch, BOT

reset via short pulse pulse high side power
TOP=BOT=LOW under voltage supression transformer flip flop driver VGE
lockout, power ON BOT BOT BOT BOT
reset
I > Imax
primary side secondary side driver side load side
option V: +
24 V supply input -UZK
analogue current SKiiP use
4 kVAC 17 1
sense output X 10, X11, X12
normalised : 10V=125% I NENN
Figure 3.46 Block diagram of a GB-driver for a SKiiPPACK dual module
Basic features of SKiiPPACK-drivers:

- + 24 V supply voltage uncontrolled or + 15 V + 4 % on information potential; integrated
SMPS with potential isolation;
- 15 V CMOS input signal level; pulse transformers
- Isolation voltage (AC, 1 min) primary/secondary 3 kVeff for SKiiPPACK 600 V, 1200 V,
4 kVeff for SKiiPPACK 1700 V (3,5 kVeff for GDL-brake chopper);
- dv/dt-ruggedness min 75 kV/s (50 kV/s for GDL-brake chopper)
- Error memory with error feedback output (open-collector-output)
195
- Optional fiber optic input (option F);

- Current sensors, overcurrent/short-circuit protection by potential isolating current sensors in
the AC-outputs (for H-bridges and three-phase-bridges ground current monitoring at the
same time);
- Heatsink temperature sensors and monitors (near the chips);
- Supply undervoltage monitoring of the driver supply voltage;
- Optional DC-link voltage monitoring (option U).
For interlocking, input short-pulse suppression (<750 ns), dead time generation and interlock
TOP/BOTTOM have been implemented.
Current sensing and overcurrent protection

Figure 3.47 explains the principle of analogous current measurement via current sensors
integrated close to the AC-terminals in the SKiiPPACK case frame.
IS1
1st Compensating Winding
VA1
Sensor Apparent Ohmic
Coil Resistant _
Output
Primary Current Apparent Ohmic +
Resistant
2nd Compensating Winding IS2 VA2
Figure 3.47 Principle of current sensors integrated in SKiiPPACK and MiniSKiiP 8..I
The AC-output current of each phase is transmitted inductively into a magnetic field sensor,
which will detect positive and negative magnetic field peaks. The sensor current is controllable
via compensation windings, by which the output current will be reflected.
This method may even be used in power module applications subject to high thermal stress,
because no offset due to temperature will be generated in contrast to Hall-sensors. The sensor is
characterized by a small measuring fault (< 0,25 %), a low degree of non-linearity (< 0.1 %) and
short response times (< 1 s). Direct and alternating current may be measured, respectively.
The output currents of SKiiPPACK driver sensors have been summarized and normalized in
such a way that the type current (IC@25C) indicated in the datasheets will generate a voltage of
8V at the actual current output of the SKiiPPACK. The direction of voltage corresponds to the
direction of AC-current flow (> 0 V: current flow out of the SKiiPPACK/< 0 V: current flow
into the SKiiPPACK).
As soon as 125 % of IC@25C has been reached, this voltage will increase to its limit value of
10V, and the OCP inside the SKiiPPACK will be triggered off (OCP: Over Current Protection).
The IGBTs will be turned off within 1 s and the error memory will be set.
Figure 3.48 explains the advantages of OCP compared to overcurrent protection by VCE-
monitoring.
196
L1
L2
iL
vDC=
900V
vCE
UDC 900V
4 Imax(VCE) 4kA
Imax(OCP) 1.6kA
LK 1.6H
2
3
Figure 3.48 Current and voltage characteristics during overcurrent case I for VCE-monitoring and OCP
1) vCE-characteristic at overcurrent turn-off by vCE-monitoring
2) iL-characteristic (inverted) at overcurrent turn-off by vCE-monitoring
3) vCE-characteristic at overcurrent turn-off by OCP
4) iL-characteristic (inverted) at overcurrent turn-off by OCP
With the OCP-principle overcurrents will be detected and turned off earlier than with VCE-
monitoring, since no gating time comparable to VCE-monitoring will be required. Moreover, the
turn-off threshold level is not dependent on the temperature as with VCE-protection, where, for
example, ICERROR = 1.25IC@25C is set for VCEERROR@125C. Due to the positive temperature
coefficient of the saturation voltage in NPT-IGBTs, a considerable higher collector current might
flow on reaching the switching threshold VCEERROR@125C in a cold IGBT (about doubled at
25C/tripled at -25C).
The high collector current may possibly result in a high turn-off overvoltage.
The ability of modern IGBTs to turn off very fast in a wide range of the gate control (gate
resistance RGoff), however, may cause high turn-off overvoltages even during short-circuit soft
turn-off, which in most cases requires IC deratings.
197
Temperature sensing/ overtemperature protection

Temperature sensing is managed by a PTC-resistor with almost linear characteristic, which is
arranged on the DCB-substrate of one phase. The output signal is amplified and is provided as a
normalized analogous signal with a maximum error of 5 % within the range of 40...125C and is
used for overtemperature turn-off at 115C 3 K.
The analogous signal is normalized to 2 V at 41.5C and 10 V at 117.5C.
DC-link voltage detection (option U)

The DC-link voltage is detected by a highly resistive differential amplifier input which meets the
requirements of standard VDE 0160/EN 50178 (safe electrical isolation).
The output signal is normalized to 9 V corresponding to voltage Vdmax (measurement error 2 %).
Aquisition and evaluation of analogous signals

Thanks to the thoroughly EMI-conforming driver concept, shielded cables can mostly be done
without, even if long wires are used.
To guarantee faultless processing of the analogous SKiiPPACK signals, however, it is important
to avoid ground loops and voltage drops in measuring wires which are not caused by measuring
signals. Therefore, measuring currents have to be conducted on the ground side via the AUX-
GND-connections and not via power supply ground lines (see Figure 3.49).
controller, controller, pre-board, o.eq. cable additional cable SKiiP, OCP parallel board,
regulator, comparator differential amp. provides valid signal board (o.eq.) o.eq.
uses analogue signal
supply
clock- driver
supply +ripple current, voltage drop in GND wire, noise for signal value
signal
circuit
signal-GND supply-GND do NOT SKiiP-GND

connect
SKiiP-GND
IN_A GNDs ! para-
meter
OP
Regel- value
gre IN_B moni-
toring
very low current, through AUX_GND, correct value
signal-GND differential
amplifier GND_AUX
signal-GND
signal reffers to signal reffers to
signal GND SKiiP GND
Figure 3.49 Processing of analogous SKiiPPACK output signals
In the case of interferences in the environment we recommend the evaluation of any analogous
signal via a differential amplifier with reference to auxiliary ground (SEMIKRON: AUX-GND).
Remaining interference spikes should be filtered out by low-pass filters.
Further application hints with regard to SKiiPPACK-drivers are given in the SEMIKRON
databook [264].
Test equipment for batch production of SKiiPPACKs
198
3.6 Fault behaviour and protection
3.6.1 Types of faults

Components used in power electronics have to be protected from non-permissible stress in any
operational state - i.e. they have to be protected from leaving the safe operation areas indicated in
the datasheets.
Leaving SOAs will cause damage and, therefore, reduce component life. In the worst case, the
component might be destroyed immediately.
Therefore, it is most important to detect critical states and faults first, and to respond to them
adequately afterwards.
The explanations in this chapter refer mainly to IGBTs, but may be applied to power MOSFETs
in analogy. Special notes with regard to MOSFETs are indicated separately.
Fault currents
Fault currents are collector-/drain currents, which exceed standard operating values of a certain
application due to control or load errors.
They might lead to damage of the power semiconductors by the following mechanisms:
- thermal destruction by high power dissipation,
- dynamic avalanche,
- static or dynamic latch-up,
- overvoltages due to fault currents.
A difference is made between the following fault currents:
Overcurrent
Features:
- low collector current di/dt (depending on load inductance and driving voltage),
- fault current is conducted through the DC-link,
- transistor does not desaturate,
Causes:
- reduced load impedance,
- inverter control error,
Short-circuit current
Features:
- very steep collector current di/dt,
- fault current is conducted through the DC-link,
- transistor is desaturated,
Causes:
- Arm short-circuit (case 1 in Figure 3.50)
+ by defective switch
+ by faulty driver pulses for the arm switches
- Load short circuit (case 2 in Figure 3.50)
+ by faulty isolation
+ man-made errors (wrong connection wiring etc.)
199
Earth fault current (case 3 in Figure 3.50)

Features:
- Collector current di/dt is dependent on earth inductance and driving voltage
- Earth fault circuit is not closed over DC-link
- Desaturation of the transistor is dependent on fault current value
Causes:
- Connection between a voltage-carrying conductor and earth potential (by faulty isolation or
man-made errors)
Z1
Case 2
Case 1 Z2
Z3
Case 3
Figure 3.50 Causes of fault currents
Overvoltages
We are talking about dangerous overvoltages, if the avalanche break-down voltages of power
semiconductors are exceeded. This goes for transistors as well as for diodes.
With respect to IGBTs and MOSFETs, overvoltages may occur between collector and emitter (or
drain and source) - i.e. between the main terminals - as well as between gate and emitter (or gate
and source) - i.e. between the control terminals.
Causes of overvoltages between main terminals:

Figure 3.51 shows different types of overvoltages between main terminals of power
semiconductors with the example of a commutation circuit.
200
periodic
Overvoltages (OV)
LK aperiodic
2 iK
External OV Internal OV
Transient Spike in vK
S1
vS1 Switching-OV Asymmetries in Series
di K Connected Devices
RL LL iL LK
vK dt
vS2 L K = ... 0,1 H ... L K = ...1...50 H static dynamic

S2
LK VSI ZCS-Technique
2 LStray of Transformers
SMPS
L K = ...1...10 mH
Line-Commutated Converter
CSI (dc-link current breaking)
Figure 3.51 Types of overvoltages
Overvoltages in a commutation circuit may principally be divided into external and internal
overvoltages.
In this respect, an external overvoltage is to be comprehended as transient increase of the
impressed commutation voltage vK. This may happen for example in DC-voltage mains of
electric traction. Increased DC-link voltages are to be regarded in the same manner (caused e.g.
by active feedback loads or control errors in pulse rectifiers).
Internal overvoltages are generated by turning off the power-electronic switch against the
commutation circuit inductance LK (v = LK * diK/dt).
The following processes are characteristic for the generation of switching overvoltages:
- Active turn-off of load current iL by the active elements of switches S1 and S2 during normal
operation of a converter:
In many SMPS-applications (Switch-Mode Power Supply) the inductance LK is due to the
stray inductance of transformers, which may amount up to 10-100 H.
- Reverse-recovery-di/dt during passive turn-off (reverse recovery) of fast diodes in hard
switching converters or ZCS-converters:
due to their operation principle, ZCS-converters may also show an increased commutation
inductance within the range of 10 H (see chapter 3.8).
- High di/dt (...10 kA/s...) in case of short circuits and during turn-off of short circuit currents
in converters with DC voltage link ,
- Active interruption of DC link currents in CSI-topologies (big inductances).
Furthermore, overvoltages in power electronic devices may be generated by static or dynamic

asymmetries of switches connected in series (see chapter 3.7).
Overvoltages during normal operation of converters and converter fault operation may appear as
periodic (...Hz...kHz...) or aperiodic overvoltages
Causes of overvoltages between control terminals:

Overvoltages between control terminals of IGBTs and MOSFETs can be due to:
- supply voltage error of the driver,
- dv/dt-feedback (displacement current to the gate) via Miller capacitance (e.g. short circuit II,
see chapter 3.6.2),
201
- emitter-/source-di/dt-feedback (see chapter 3.4.1),

- increase of gate voltage during active clamping (see chapter 3.6.3.2).
Overtemperature
Dangerous overtemperatures arise, if the maximum junction temperature indicated by the device
manufacturer is exceeded (e.g. Tjmax = 150C for silicon devices).
During inverter operation overtemperatures might be generated by:

- increase of energy dissipation caused by fault currents,
- increase of energy dissipation caused by defective drivers,
- failure of the cooling system.
3.6.2 Behaviour of IGBTs and MOSFETs during overload and short-circuit operation
Overload:
Basically, the switching and on-state behaviour under overload does not distinguish from
standard operation under rating conditions. In order not to exceed the maximum junction
temperature, the overload range has to be restricted, since increased load current will cause
increased power dissipation in the device.
In this respect limits are set by the absolute value of the junction temperature as well as by
overload temperature cycles.
These limits are indicated in the datasheet SOA-diagrams.
Figure 3.52 shows selected examples for MOSFETs and IGBTs.
202
b)
a)
c)
Figure 3.52 SOA-diagrams for MOSFETs and IGBTs

a) Max. safe operating area MOSFET SKM111
b) Max. safe operating area IGBT SKM100GB123D
c) Turn-off safe operating area (! periodic !) IGBT
SKM100GB123D
Short circuit:
Principally, IGBTs and MOSFETs are short-circuit proof, i.e. they may be subjected to short
circuits under certain given conditions and turn them off, without damaging the power
semiconductors.
When considering short circuits (which is to be done with IGBTs), two different cases of short
circuits have to be distinguish.
Short circuit I (SC I)

In case of SC I the transistor is turned on to an existing load short circuit, i.e. full DC-link
voltage is applied to the transistor already before the short circuit occurs. The di/dt of the short-
circuit current is determined by the driver parameters (driver voltage, gate resistor). This
transistor current increase will induce a voltage drop over the parasitic inductance of the short
circuit, which is depicted as a decrease of the collector-emitter voltage characteristic (Figure
3.53).
203
vCE (500 V / Div)
iC (200 A / Div)
vGE (20 V / Div)
1 s / Div
Figure 3.53 SC I characteristics of an IGBT (SKM100GB123D)
The stationary short-circuit current adjusts itself to a value that is determined by the output
characteristic of the transistor. Typical values for IGBTs are up to 8-10 fold rated current (see
Figure 3.56b).
Short circuit II (SC II)

In this case the transistor is already turned on, before the short circuit occurs. Compared to SC I,
this case is much more critical with respect to transistor stress.
Figure 3.54 shows an equivalent circuit and principle characteristics to explain the SC II process.
LK
LSC LL LD
RL
iL
CGC LT
VDC
iC
RG
Driver VCE
VGE
204
v GE
t
1 2 3 4
iC
IC/SCM
IC/SC
IL
t
1 2 3 4
v CE
VCE/SC(off)
VCE/SC(on)
VDC
t
1 2 3 4
Figure 3.54 Equivalent circuit and principle characteristics of SC II [194]
As soon as the short circuit has occurred, the collector current will increase very steeply, the
di/dt is determined by DC-link voltage VDC and the inductance of the short-circuit loop.
During time interval 1 the IGBT is desaturated. The consequently high dv/dt of the collector-
emitter voltage will effect a displacement current through the gate-collector capacitance, which
increases the gate-emitter voltage. This in turn will cause a dynamic short-circuit peak current
IC/SCM.
After having completed the desaturation phase, the short-circuit current will drop to its static
value IC/SC (time interval 2). During this procedure, a voltage will be induced over the parasitic
inductances, which becomes effective as overvoltage in the IGBT.
The stationary short-circuit phase (time interval 3) is followed by turn-off of the short-circuit
current towards the commutation circuit inductance LK, which will again induce an overvoltage
to the IGBT (time interval 4).
205
The transistor overvoltages induced during a short circuit may exceed the values of normal
operation by several times.
vCE (500 V / Div)
iC (400 A / Div)
iC0 = 20 A
vGE (20 V / Div)
0,5 s / Div
Figure 3.55 SC II characteristics of an IGBT (SKM100GB123D with gate clamping)
The SOA-diagram at short circuit shown in the IGBT datasheets shows the limits for safe control
of a short circuit (Figure 3.56a).
206
a)
ICSC
ICN
VDC = 600 V
12 tp = 10 s
L = 25 nH
10 RGon = 10
Tj = 25C RGoff = 10
8
6
Tj = 125C
b) 4
VGE [V]
0 12 14 16 18
Figure 3.56 SOA at short circuit of an NPT-IGBT (SC SOA)

a) Normalized short-circuit current versus collector-emitter voltage (SKM100GB123D)
b) Normalized short-circuit current versus gate-emitter voltage (general)
The following important boundary conditions have to be fulfilled to guarantee safe operation:
- the short circuit has to be detected and turned off within max. 10 s,
- the time between two short circuits has to be at least 1 second,
- the IGBT must not be subjected to more than 1000 short circuits during its total operation
time.
Figure 3.56b shows the influence of gate-emitter voltage and junction temperature on the
stationary short-circuit current.
Short circuit I and II will cause high power dissipations in the transistor, which will increase the
junction temperature. Here, the positive temperature coefficient of the collector-emitter voltage
has a favourable effect (this also goes for the drain-source voltage), since it causes reduction of
the collector current during stationary short circuit (see Figure 3.56b).
Possibilities for reliable detection of fault currents and limitation of occurring overvoltages are
summarized in chapter 3.6.3.
207
3.6.3 Fault detection and protection

Errors in inverters may be detected at various points, and the reaction to detected errors may be
very differently.
We are talking about fast protection, if the error is detected within the switch itself and the
switches are turned off directly by the driver. The total response time of the switch may possibly
be only some 10 nanoseconds.
In case of error detection outside the switches firstly an error signal is transmitted to the control
board, where a reaction to the error is triggered. This is called slow protection. The running
processes are even related to converter control (e.g. the systems reaction to overload).
Modern converters mostly combine slow and fast protection procedures depending on the
specific application.
A comprehensive comparison of protection concepts is included in [194].
3.6.3.1 Detection and reduction of fault currents
Detection of fault currents

Figure 3.57 shows a voltage source inverter circuit. Here, the measuring points are marked where
fault currents can be detected.
6 6 6
3 3 3
5
7 7 7
4 4 4
2
Figure 3.57 Voltage source inverter (VSI) with detection points for fault currents
Fault currents can be designed as follows:

Overcurrent: detectable at points 1-7
Arm short circuit: detectable at points 1-4 and 6-7
Load short circuit: detectable at points 1-7
Ground short circuit: detectable at detection 1, 3, 5, 6 or by calculation of the difference
between 1 and 2
208
Principally, controlling short-circuit currents requires fast protection measures realizing direct
control on the driver output stage, since the transistor switch has to turn off within 10s after the
short circuit has occurred. For this, fault currents may be detected at detection points 3, 4, 6 and
7 (with OCP-drivers also at detection point 5, see chapter 3.5.8).
Measurements at points 1-5 may be taken by means of measuring shunts (e.g. integrated in
MiniSKiiPs) or inductive measuring current transformers (e.g. in OCP-SKiiPs and OCP-
MiniSKiiPs).
Measuring shunt:
- simple measuring method,
- requires low-resistance (10...100 m), low-inductance power shunts,
- measuring signal is highly sensitive to interferences,
- measuring values are not available with potential isolation.
Measuring current transformers:

- much more complicated realization compared to measuring shunt,
- Interference susceptibility of measuring signal is lower than with measuring shunt,
- measuring values are available with potential isolation.
At detection points 6 and 7 fault currents are detected directly at the IGBT/MOSFET-terminals.
Here, protection methods are vCEsat or vDS(on)-monitoring (indirect measuring method) and current
sensing, in case a sense-IGBT is used (direct measuring method). Figure 3.58 shows the
principle circuits.
VGG+
iC
i1 >> i2
vCE
i2 i1 vmeas
vmeas RSense
a) b)
Figure 3.58 Fault current detection by a) current sensing and b) vCEsat-monitoring
Current sensing with sense-IGBT:

In a sense-IGBT a few cells are combined to a sense-emitter generating two parallel current
arms. Information is given by the conducted collector current as soon as it passes the measuring
resistor. At RSense = 0 the current division ratio between both emitters is ideal, corresponding to
the ratio of number of sense-cells to total number of cells. If RSense is increased, the current
conducted in the measuring circuit will be reduced by feedback of the measuring signal.
Therefore, resistance RSense should be within a range of 1 - 5 to obtain a sufficiently exact
measuring result of the collector current.
209
If the turn-off current threshold value is only slightly more than the transistor rated current, the
current monitoring has to made ineffective during turn-on of the IGBT because of the reverse-
recovery current peak of the free-wheeling diode (in hard switching topologies).
For very high sense-resistances (RSense ) the measuring voltage corresponds to the collector-
emitter saturation voltage, so that current sensing acts as a vCEsat-monitoring.
VCEsat-monitoring:
VCEsat-monitoring makes use of the relationship between collector current and forward voltage
indicated in the transistor datasheets (output characteristic).
The collector-emitter voltage is detected by a fast high-voltage diode and compared to a
reference value. If the reference value is exceeded, the error memory will be set and the
transistor will be turned off. The fast desaturation process in the transistor manages fast detection
of short circuits. If the transistor is not desaturated by fault (e.g. if slowly increasing ground fault
currents and overcurrents are involved), the application of vCEsat-monitoring for fault detection
will be restricted.
To guarantee safe turn-on of the IGBT during normal operation, vCEsat-monitoring has to be
gated until the collector-emitter voltage has fallen below the reference voltage (see chapter
3.5.4). Since no short-circuit protection is given during this period, the gating time must not
exceed 10s.
Temperature dependency of the output characteristic as well as parameter spreading have
negative effects on vCEsat-monitoring. However, the substantial advantage compared to current
sensing with sense-IGBT is that this protection concept is applicable to every standard-
IGBT/MOSFET.
Fault current reduction

Improved protection of the transistor switch can be achieved by reduction or limitation of high
fault currents, especially with regard to short circuits and low-impedance ground fault circuits.
As explained in chapter 3.6.2, a short circuit of type II will generate a dynamic short circuit
overcurrent due to the increase of the gate-emitter voltage because of high dvCE/dt.
The amplitude of the short-circuit current may be reduced by clamping the gate-emitter voltage.
Suitable circuit variants are given in chapter 3.6.3.2.
Apart from limitation of dynamic short-circuit overcurrents, stationary short-circuit currents may
also be decreased by reducing the gate-emitter voltage (see Figure 3.56b of chapter 3.6.2). This
will reduce transistor power losses during the short-circuit time. At the same time, overvoltage is
decreased by turning off the lower short-circuit current. The principle is shown in Figure 3.59.
210
iC
RG iG
vCE
iM1
vGE
R1
vDriver M1
R Sense
Figure 3.59 Short-circuit current limitation by reduction of gate-emitter voltage
This protection technique limits the stationary short-circuit current to about three times the rated
current in rugged modules described under [281].
3.6.3.2 Overvoltage limitation
Overvoltage limitation between main terminals

Measures to limit overvoltages between main terminals (collector-emitter voltage, DC-link
voltage) can be divided into passive snubber-networks, active clamping and dynamic gate
control.
Independent of the kind of overvoltage limitation, the avalanche operation mode of MOSFETs
can be utilized (see Figure 3.2). Please follow closely the limit ratings indicated in the datasheets
or ask the manufacturer for corresponding limit ratings.
Passive snubber-networks
Passive networks (snubbers) are combinations of passive elements such as R, L, C, suppressor
diodes, diodes, varistors etc.
In addition to chapter 3.8.2 the following explanations will consider variants, which are not
responsible for switching loss reduction.
Figure 3.60 shows a summary of simple circuits.
211
Basic Circuit
A
LK
2
B iL
vK
LK
2
C
Snubber Variants
A A A A
C C C C
a) b) c) d)
Figure 3.60 Passive overvoltage limitation networks
The principle of passive snubber-networks is to avoid induction of dangerous overvoltages due

to the inductances of the commutation circuit LK by attaching a capacitor which absorbs the
energy stored in LK (E = LK/2*i). The capacitor will be charged with the voltage difference
V LK*i/C and will set a limit to overvoltages. The absorbed energy has to be discharged
again between two charging processes to keep up the function of the network. With simple
snubbers, this task is fulfilled by heat conversion in the snubber-resistors or by feedback to the
DC-link capacitor.
The simplest method is to clamp the DC link voltage directly to the power module terminals by
means of a capacitor (film capacitor or something similar). This measure is sufficient for many
VSI applications. In this case, the capacitance values are up to 0.1 - 2 F (Figure 3.60a).
To absorb parasitic oscillations between C and LK, voltage clamping may be achieved by an RC-
element (Figure 3.60b). This measure is recommended for low-voltage/ high-current applications
(e.g. MOSFET-converters), to avoid parasitic change of the DC-link voltage polarity at the
module terminals.
Figures 3.60c and d show some RCD-networks. The integrated fast diodes should feature low
forward turn-on overvoltage and soft-reverse-recovery behaviour.
The snubber-network itself has to be laid out with minimum inductance.
Passive networks do not require any active components, which is an additional advantage to their
simple topologies.
On the contrary, the overvoltage limit value can vary dependent on the operating point.
Therefore, dimensioning has to be based on the worst case.
212
Active Clamping [161], [261], [302]

Active clamping of MOS-controlled transistors designates direct feedback of the collector-
/drain-potential to the gate via a Zener-element. Figure 3.61 shows the basic principle and
variants produced with the example of an IGBT-switch.
LK
iZ
B Z A
Ds iC
R Goff
vCE
V-
vGE
a)
Variant A Variant B Variant C Variant D Variant E

A A A
A iZ iZ iZ A
iZ iZ
iZ Tn Zn iTA Zn iTA iZ
RGn
Zn Dn
Z1 Z1
TA TA
Z1 T1 RGA D1
RG1 RGA
B B b)
B B B
Figure 3.61 Basic principle (a) of active clamping and variants (b)
The feedback arm consists of a Zener-element Z and an attached diode Ds, which will stop
current flow from driver to collector, when the IGBT is turned on.
If the collector-emitter voltage passes the avalanche breakdown voltage of the Zener-element, a
current will be conducted to the IGBT gate via feedback coupling, which will raise the gate
potential to a value given by the IGBT transfer and output characteristic (ic = f(vCE,vGE)) (Figure
3.62). The clamping process will be continued as long as current is impressed by the series
inductance. The voltage applied to the transistor being determined by the current-voltage
characteristic of the Zener-element. The transistor operate in the active area of its output
213
characteristic (!!safe operating area!!) and converts the energy stored in LK to heat (Figure 3.62).
Figure 3.62 explains these correlations by depiction of typical characteristics.
collector current iC [A]

30,88
19,991
9,1022
-1,7864
collector-emitter-voltage vCE [V]
702,93
468,62
234,31
-5,5511e-17
t = 200 ns / RE
current iZ [A]
1,8263
1,2029
0,57954
-0,043831
692,21
459,65
227,1
-5,4504
t = 200 ns / RE
current iZ [A]
1,7929
1,1809
0,56895
-0,04303
gate-emitter-voltage vGE [V]
14,385
5,8105
-2,7637
-11,338
t = 500 ns / RE
Figure 3.62 Typical current and voltage characteristics during active clamping (variant A),(vK = 400 V, vcl = 640 V,
iC0 = 30 A, LK = 10 H, Tj = 30C, V- = -15 V, SKM100GB123D)
The gate charge peak current necessary for increasing the gate voltage at the beginning of the
clamping process is clearly shown in Figure 3.62.
214
Selection of the suitable variant produced is dependent on the average power dissipation in the
Zener-element. This is based on the following principle: the higher the voltage difference
between commutation voltage and clamping voltage, the lower the power dissipations in the
clamping circuit.
Another criterion of selection might be the rate of rise of the Zener-characteristic (Figure 3.63).
iZ
v Cl
A B C D
2
J Z [A/cm ]
160
140
A
120
B
100
C
80
D
60
40
20
0
200 400 600 800 1000
V Cl [V]
Figure 3.63 Static characteristics of selected Zener-elements [194]

A: Suppressor diode 06KE350, B: BUZ90 during avalanche breakdown
C: BUP400 during avalanche breakdown, D: BUZ78 as amplifier
Variant A of Figure 3.61 can be realized very easily and may be used at low clamping energy
applications (e.g. in pulsed voltage source converters).
The MOSFETs and diodes in variants B and E are operated in avalanche-mode.
In variants C and D the MOSFET/ IGBT serves as amplifier for the Zener current, variant D
being characterized by an especially high ruggedness.
Features of active clamping are summarized as follows:

- simple circuit arrangement,
- the transistor to be protected is part of the protection itself and converts the main share of
energy stored in LK in the clamping process,
- there is no need for power resistors and snubber capacitors,
- steep clamping characteristic,
- the switch voltage to be limited is independent of the operating point of the inverter,
- the principle does not require a separate power supply,
- conventional drivers may be applied,
- overvoltages during reverse-recovery-di/dt of the inverse diodes are limited at the same way,
- possibility to equip either every single transistor switch with a clamping circuit or to attach
one central clamper for one or several pairs of switches.
215
The principle of active clamping has not been utilized industrially so far, but for short-circuit
protection of inverters with DC-voltage links, where clamping is done only in case of faults of
the inverter at relatively low energies.
Investigations described under [161] show, however, that the active clamping process would also
turn out to be advantageous under periodic operation conditions of ZCS-switch mode power
supplies, where high energies are involved (clamping frequency: 15...30 kHz). All in all, the
possibilities and limits of this protection concept will still have to undergo extensive research
and development. This goes especially for periodic short-term operation of IGBTs and
MOSFETs in the acitve region of the output characteristic.
Dynamic gate control

In the procedure of dynamic gate control the di/dt and dv/dt and the consequently induced
overvoltages are directly determined by the driver.
Another more simple protection procedure of dynamic gate control is slow turn-off of IGBTs
and MOSFETs in case of overcurrents or short circuit applying higher gate series resistors (e.g.
driver stage SEMIKRON SKHI 23) or turn-off by defined current (current source control)
(Figure 3.64).
RG/ERROR >> RG
VGG+ ON RG/ERROR
RG
ERROR
VGG- OFF
a)
VGG+ ON
RG ERROR
VGG- OFF IG/ERROR
b)
Figure 3.64 Possible slow turn-off procedures in case of converter fault operation
a) Increased RGoff
b) Current source control
216
In the drivers introduced under [9], [47] and [61] the IGBT/MOSFET dv/dt and di/dt are
detected and fed back to the driver (Figure 3.65).
s + gate current
-
+
+ gate current
s
Figure 3.65 Direct dv/dt- and di/dt-detection
Here, the information on di/dt or dv/dt is got by inductance at the emitter or by capacitance at the
collector, respectively.
Overvoltage limitation between control terminals

Overvoltage limitation between control terminals is required for keeping up the maximum gate-
emitter/ gate-source voltage on the one hand, and for limitation of the dynamic short-circuit
current amplitude on the other hand.
Figure 3.66 shows a summary of simple circuit variants. For the sake of optimized efficiency the
limitation circuits should be laied out for low inductance and be attached as close as possible to
the gate.
Passive Gate Clamping
Zener-Diode Schottky-Diode MOSFET
RG RG
RG
V+
vDriver vDriver
vDriver
Figure 3.66 Simple gate voltage limitation circuits [194]
3.6.3.3 Overtemperature detection

Direct measurement of the junction temperature is only possible, if the temperature sensor is
attached very close to the semiconductor component (e.g. by monolithic integration or by
connecting of the temperature sensor and the power semiconductor chip).
Information on temperature can then be got from the evaluation of diode or thyristor blocking
currents.
However, technologies of that kind have only been applied in smart-power components so far.
In transistor power module applications temperatures are measured either outside the module
from the heatsink or inside the module by temperature-dependent resistors close to the power
semiconductor chips (e.g. with SEMIKRON SKiiP/ MiniSKiiP).
Because of the given thermal time constants, only information about the average temperature is
given (dynamic temperature measurement is not possible).
217
In the drivers introduced under [9], [47] and [61] the IGBT/MOSFET dv/dt and di/dt are
detected and fed back to the driver (Figure 3.65).
s + gate current
-
+
+ gate current
s
Figure 3.65 Direct dv/dt- and di/dt-detection
Here, the information on di/dt or dv/dt is got by inductance at the emitter or by capacitance at the
collector, respectively.
Overvoltage limitation between control terminals

Overvoltage limitation between control terminals is required for keeping up the maximum gate-
emitter/ gate-source voltage on the one hand, and for limitation of the dynamic short-circuit
current amplitude on the other hand.
Figure 3.66 shows a summary of simple circuit variants. For the sake of optimized efficiency the
limitation circuits should be laied out for low inductance and be attached as close as possible to
the gate.
Passive Gate Clamping
Zener-Diode Schottky-Diode MOSFET
RG RG
RG
V+
vDriver vDriver
vDriver
Figure 3.66 Simple gate voltage limitation circuits [194]
3.6.3.3 Overtemperature detection

Direct measurement of the junction temperature is only possible, if the temperature sensor is
attached very close to the semiconductor component (e.g. by monolithic integration or by
connecting of the temperature sensor and the power semiconductor chip).
Information on temperature can then be got from the evaluation of diode or thyristor blocking
currents.
However, technologies of that kind have only been applied in smart-power components so far.
In transistor power module applications temperatures are measured either outside the module
from the heatsink or inside the module by temperature-dependent resistors close to the power
semiconductor chips (e.g. with SEMIKRON SKiiP/ MiniSKiiP).
Because of the given thermal time constants, only information about the average temperature is
given (dynamic temperature measurement is not possible).
217
If given reference values (which are extremely application-specific) in converters are exceeded,
the system can react by immediate turn-off or by operation with reduced power.
3.7 Parallel and series connection of MOSFET, IGBT and SKiiPPACK

modules
3.7.1 Parallel connection
3.7.1.1 Problems of current sharing

To improve the current capability of power electronic switches, IGBT and MOSFET modules
can be connected in parallel.
By paralleling power modules, the transistors and necessary inverse diodes or free-wheeling
diodes are also paralleled. As parallel connection of fast diodes had already been dealt with in
chapter 1.3.5.2, only special characteristics of IGBTs/ MOSFETs will be discussed to in the
following.
Maximum utilization of the switch generated by parallel connection will only be achieved in the
case of ideal static (i.e. in the forward operation) and dynamic (i.e. at the moment of switching)
symmetrization of the single modules (current sharing).
Therefore, optimal symmetry conditions are of major importance for parallel connections in
practice.
Current sharing is mainly effected by the following factors:
Factor Influence on
static symmetry dynamic

symmetry
IGBT/MOSFET-parameters
vCEsat = f (iC, vGE, Tj) or RDSon = f (vGS, Tj)
x
iC = f (vGE, Tj) or iD = f (vGS, Tj) x
vGE(th) or vGS(th) x
td(on), td(off), tr, tf (in connection with

x
driver parameters)
Commutation circuit
Total loop inductance
(x) x
(inside the module + outside the module)
Driver circuit
Output impedance of driver
(including gate series resistances) x
218
Total loop inductance x

Driver circuit inductance carrying collector/ drain x

current
Influence of saturation voltage and RDS(on) respectively

The on-state voltage induced during stationary forward on-state is the same for both paralleled
transistors. Current distribution is dependent on the tolerances of the output characteristics.
Figure 3.67 shows how the total load current is distributed over two paralleled IGBTs with
different output characteristics.
IC [A] 30 IC1 Iload = IC1 + IC2

IC [A] 40
25 Istat. IC1
Istat
20
30 Idyn.
IC2
15 20
IC2
10 VGE1=VGE2=15V
TJ=125C 10
5
0 0
0 0,5 1 1,5 2 2,5 3 00,0 E+0 05,0 E-6 10,0 E-6 15,0 E-6
VCE [V] t [s]
Figure 3.67 Static current distribution over two paralleled IGBTs with different output characteristics
In the beginning, the major current share is conducted by the transistor with the lower saturation
characteristic, which is therefore subject to higher forward and switching losses, and, by
consequence, the junction temperature will increase rapidly.
In this respect, the temperature coefficient (TC) of the saturation voltage is of decisive
importance. If the TC is positive, i.e. if the saturation voltage rises together with the temperature,
the current will be shifted to the transistor which had carried the minor current share in the
beginning. Finally, the current will (ideally) be evenly distributed over the paralleled transistors.
Therefore, power semiconductors with a positive TC are preferably used for parallel
connections.
The TC of NPT IGBTs is positive over almost the whole rated current range. The same goes for
the RDSon of MOSFETs, featuring a positive TC by principle.
In contrast to that, the TC of PT IGBTs is negative over almost the whole rated current range.
Here, good thermal coupling between paralleled modules is substantial.
Influence of the transfer characteristic iC = f (vGE, Tj) and iD = f (vGS, Tj) respectively
Deviations in the transfer characteristics, threshold voltages and switching delay times will lead
to dynamic asymmetries at the moment of switching and, consequently, to different switching
losses, especially during turn-off.
219
Figure 3.68 shows the example of deviating transfer characteristics of paralleled NPT IGBTs and
thereby caused dynamic current asymmetry during turn-off.
Due to the common gate voltage during the Miller process, the IGBT with the steeper transfer
characteristic will conduct the major current share during dynamic current distribution and is
therefore subject to higher turn-off power dissipation.
While the positive on-state voltage TC of NPT-IGBTs is supporting parallel connections, the
steep transfer characteristic and high switching speed will have negative effects on dynamic
symmetry.
IC [A] 40 IC [A] 60
IC1 50
30 Idyn.
40
Idyn. off IC1 Istat.
20 30
IC2
20
10 IC2
10
VGE Miller
0 0
5 6 7 8 9 10 11 0,00E+00 5,00E-06 1,00E-05
VGE [V] t [s]
a) b)
Figure 3.68 a) Transfer characteristics of two paralleled NPT-IGBTs
b) Dynamic current distribution during switching
Furthermore, Figure 3.68 makes it clear that, in addition to the transfer characteristics, the
deviations of turn-on losses of IGBTs/ MOSFETs are basically determined by the turn-off
behaviour of the free-wheeling diodes.
Influence of loop inductance in the commutation circuit

Following the explanations in chapter 3.4.1, turn-on and turn-off power dissipations of power
semiconductors are determined by the commutation circuit inductance LK (loss reduction effect
during turn-on, generation of switching overvoltage during turn-off).
Paralleling of switches is always equivalent to paralleling of commutation circuits. If
commutation circuits are subject to different loop inductances, the switching speed of fast power
semiconductors may be differently, which would cause dynamic asymmetries. Therefore, a
strictly symmetrical layout of the commutation circuit should be realized.
Influence of the driver output impedance (including gate series resistances)

Impedance deviations of the driver circuits of paralleled transistors have to be minimized.
Existing deviations will lead to non-simultaneous switching and will contribute to unbalanced
distribution of switching losses.
Influence of loop inductance of the driver circuit

In combination with transistor input capacitances, the driver circuit loop inductance can generate
heavy oscillations, which might even spread between paralleled transistors (see chapters 3.7.1.2
and 3.4.1).
To avoid such parasitic oscillations, principally any loop inductance in the driver circuit has to
be minimized.
220
Influence of the collector-/drain-current-carrying inductance of the driver circuit

Fast alterations of the collector-/ drain-current during switching will induce voltages to the driver
circuit inductance, where the main current is conducted; these voltages are counteractive to the
gate charge or gate discharge, respectively (emitter-/ source negative feedback). The consequent
deceleration of the switching process will increase switching losses.
With respect to paralleling of transistors, different values of these inductances might contribute
to asymmetrical distribution of switching losses.
3.7.1.2 Module selection, driver circuit, layout

The following recommendations with reference to module selection, driver and layout for
paralleling of IGBTs and MOSFETs can be concluded from chapter 3.7.1.1.
Module selection
As for proper handling of dynamic symmetrization, NPT IGBTs are especially suitable for
parallel connection because of the positive TC of their saturation voltage. Furthermore, they are
outstanding for low tolerances and they are less temperature-dependent in their parameters.
Driver circuit
Figure 3.69 shows a proposal for the driver circuit layout for paralleling of IGBTs. The circuit is
driven by one common driver unit.
In addition to the common gate series resistances RGon and RGoff integrated in the driver, the
resistances RGonx and RGoffx damp parasitic oscillations between the gate-emitter/ gate-source
circuits. Moreover, they reduce the negative effects of the different transfer characteristics.
RGonx and RGoffx should be dimensioned with about 0.5 ...2 .
The resistances REx will suppress balancing currents via auxiliary emitters. They should be
dimensioned with about 0.5 .
The resistances RCx serve to determine the average actual vCE-/vDS-value in case overcurrent- and
short circuit protection is based on vCEsat-/vDS -evaluation.
They should be dimensioned with about 47 .
221
Driver
RCX RCX RCX
RGonx RGonx RGonx

RGon
RGoffx RGoffx RGoffx

RGoff
REX REX REX
Driver +
RCX RCX RCX
RGonx RGonx RGonx

TOP RGon
RGoff
REX REX REX
LOAD
RCX RCX RCX
RGonx RGonx RGonx

RGon
BOT
RGon
REX REX REX
Figure 3.69 Parallel connection of single and dual IGBT modules
If paralleled transistors are to be driven by separate driver units, the driver units should feature
identical signal propagation times and output parameters.
Layout
All power and driver circuits within the parallel circuit have to be laied out with minimum loop
inductance and strictly symmetrical wiring.
Modules have to be mounted to a common heatsink close to each other to guarantee optimal
thermal coupling (also because of symmetrization of inverse and free-wheeling diode).
Modern power modules are characterized by minimized internal inductances in the power and
driver circuit of only some nH. However, since different module constructions will also show
different inductance ratings, only modules of the same construction type should be connected in
parallel.
Derating
Even if all conditions for optimal module selection, driver circuit and layout design have been
fulfilled, an ideal static and dynamic symmetrization will not be achievable.
Therefore, derating has to be considered with respect to the total rated load current of the
switches. From practical experiences in different applications a derating of about 15-20 % can be
advised.
222
Example: Paralleling of three IGBT-modules with vCE = 1200 V/iC = 300 A

Rated current of the parallel circuit: iCtot = (3*300 A) * (0.8 ..0.85) = 720..765 A.
3.7.1.3 Parallel connection of SKiiPPACK modules

SKiiPPACK modules integrate power semiconductors and complete driver circuits in one
housing. In the case of direct paralleling of modules, symmetrization will be determined only by
the power layout (inductances, cooling system).
Differences in signal propagation times and driver output impedances of the single modules
might cause substantial asymmetries.
The Parallel-Board SKHBP2 and SKHBP4 assemblies by SEMIKRON support paralleling of

2 and 4 SKiiPPACK-modules, respectively.
Figure 3.70 shows a block diagram with a connected SKHBP2 for paralleling of two
SKiiPPACK-modules.
The SKHBP2 is responsible for the following main functions:

- Generation and synchronization of control signals for single modules out of one controller
signal,
- Generation of a common arm interlock time,
- Short-pulse suppression,
- Common ERROR-memory with RESET-function,
- Collection of feedback signals of the single modules and transfer to the controller (error
detection, analogous temperature output, for OCP-SKiiP: generation of the total actual load
current value).
223
SKiiPpack B
supply
24VDC FAN
or
15VDC
X1
controller X2
analogue infor-
mation present L 50108 ____ B U1 U2 U3
L 50099 ___ A
F - Option (optionally)
for plug on parallel board
X5
analogue
information
possible
FAN
SKiiPpack A
Figure 3.70 Parallel connection of two SKiiPPACK-modules with Parallel-Board SKHBP2
Despite connection of the parallel board, small differences in switching times might occur due to
differing signal propagation times within the single modules.
The consequent dynamic asymmetries may be minimized by series inductances (dynamic
decoupling) in the connected load paths.
These inductances might figure up to some Micro-Henry, and in many applications the
inductances of the load connection cables between output of the single modules and their point
of common connection can be utilized (see Figure 3.71).
224
load
L balancing L
inductance via
ferrite, coil, or
cable length
parallel
board
controller
Figure 3.71 Dynamic decoupling of paralleled single modules by the inductances of the load connection cables
As for total derating please follow the explanations in chapter 3.7.1.2.
3.7.2 Series connection
3.7.2.1 Problems of voltage sharing

To increase the blocking voltage of power electronic switches, IGBT and MOSFET modules
may be connected in series.
By series connection of power modules, the transistors and necessary inverse diodes or free-
wheeling diodes are connected in series. As series connection of fast diodes has already been
dealt with in chapter 1.3.5.1, only special problems of IGBTs/ MOSFETs will be referred to in
the following.
Maximum voltage utilization of the switch generated by series connection will only be achieved
in case of ideal static (i.e.during blocking state) and dynamic (i.e. in the moment of switching)
symmetrization of the single modules.
Therefore, optimal symmetry conditions are of major importance for the application of series
connections in practice.
Symmetrization is mainly influenced by the following factors:
225
Factor Determination of
static symmetry dynamic

symmetry
IGBT/MOSFET-parameters
iCES = f (vCE, vGE, Tj) or DSS = f (vDS, vGS, Tj) x
vGE(th) or vGS(th) x
td(on), td(off), tr, tf (in connection with x

driver parameters)
Driver circuit
Output impedance of driver
x
(including gate series resistances)
Total loop inductance x

Driver circuit inductance carrying collector/ drain x

current
Driver signal propagation times x
Reasons for static asymmetry

During stationary off-state of IGBTs / MOSFETs the conditions of symmetry are determined by
the blocking characteristics of the transistors connected in series.
The higher the blocking current of a transistor, or, in turn, the lower the blocking resistance, the
lower is the voltage taken up by the transistor, if it is connected in series.
The blocking current temperature coefficient for IGBTs and MOSFETs is positive, i.e. the
blocking current will increase linear to the rising temperature.
Reasons for dynamic asymmetry

All factors determining dynamic symmetrization mentioned above will finally lead to deviating
switching times of the transistors connected in series. The transistor turning off first and the one
turning on last will be burdened with the highest voltage and, consequently, with the highest
switching losses. Exceeding the maximum admissible transistor voltage must be avoided by the
countermeasures discussed in the following chapter.
3.7.2.2 Module selection, driver circuit, snubber networks, layout
Module selection and layout

Optimal symmetry conditions are always based on minor spreadings of parameters of the
modules connected in series.
Please avoid series connection of different types of modules or modules produced by different
manufacturers.
The power and driver circuits have to be laid out principally in consideration of minimum
parasitic inductances and strictly symmetrical arrangements (also see chapter 3.7.1).
226
Static symmetrization
To achieve optimal static symmetrization conditions, the influence of differing blocking currents
has to be decreased by paralleling of resistors.
Following chapter 1.3.5.1, the current conducted through the parallel resistor may be rated to
about 3-5 times as high as the transistor blocking current.
Example: Series connection of two IGBT-modules SKM400GA173D

vCES = 1700 V, iCES (vCES, Tj = 125C) = 4.5 mA
Application of a DC-link voltage of 2400 V will result in:

Rp = 75..125 k PRp = 19..11 W
Driver Rp
Driver Rp
2 x SKM 400 GA 173D
Figure 3.72 Static symmetrization with parallel resistors
Dynamic symmetrization
Optimal dynamic symmetrization is always based on minimum deviations of signal propagation
times of the driver stages.
Passive snubber-networks
RC or RCD networks can support dynamic symmetrization very efficiently (see Figure 3.73).
These networks reduce, and thus balance dv/dt speed during switching (compensation of non-
linear component junction capacitances). However, the high reliability achieved by attachment of
RC or RCD networks faces the requirement for more passive power components, which have to
be laid out for high voltages. Snubber networks are responsible for conversion of partly
substantial extra losses. Another disadvantage is that the quantitative performance is dependent
on the actual operating point of the circuit.
In contrast to that, there is no need for additional control circuitry and the use of standard driver
stages will be sufficient.
If passive networks are combined with active symmetrization technologies, they may be laid out
with lower parameters. A combination of active symmetrization and passive network is
introduced under [45] and [236]. Here, the RC networks are laid out with R = 3.3 and
227
C = 15 nF at a DC link voltage of 2.4 kV for series connection of four 1200 V/ 600 A IGBT-
switches.
R D R
Driver
C C
R D R
Driver
C C
Figure 3.73 Passive networks
Active symmetrization measures

Switching time correction [61]
Figure 3.74 shows one possibility of producing dynamic voltage symmetrization according to the
principle of switching time correction via delay times. This method does not require any
additional passive power components. There are no extra losses generated in the IGBTs/
MOSFETs.
On the other hand, this method demands high standards with respect to driver and control circuit.
VCE-
VCE
ref Detection
Driver
Delay
t d(ON)
t d(OFF)
Control-
signal VCE-
VCE
ref Detection
Driver
Delay
t d(ON)
t d(OFF)
Figure 3.74 Principle of switching time correction
228
dv/dt control [61], [9]

The principle of dv/dt-control is that a reference value for the dv/dt speed of single modules
during switching is compared to the actual values by the driver; the difference between those
values is transmitted to the driver output stage.
In this respect, the exact and reproduceable capacitive coupling or feedback of the actual dv/dt-
values might be problematic.
If the dv/dt-reference value is lower than the natural dv/dt during hard switching, additional
losses will be generated in the power transistors.
Consequently, the driver layout has to be more sophisticated, standard drivers may no longer be
used.
Similarly, di/dt control with inductive feedback of the di/dt speed of IGBTs / MOSFETs may be
achieved [9], [61].
dvCE / dt
Detection
V
CE
Input
Reference
dvCE / dt
Detection
Figure 3.75 Dynamic voltage symmetrization by dv/dt-control
Active voltage limitation / active clamping [37], [161], [236], [261]

The process of active clamping is characterized by indication of the collector-emitter voltage or
the drain-source voltage, respectively, and feedback to the gate by a Zener-element (see chapter
3.6.3.2, Figure 3.76).
If the transistor voltage passes the given maximum voltage, the gate voltage will be increased to
such an extent, that the operating point is shifted to the active region of the output characteristic
in accordance with the collector-/ drain-current conducted.
The additional losses generated in the transistor during active clamping are relatively low.
Active clamping has no influence on symmetrization of the switching edges.
This method works without time delays, the limitation voltage value being independent of the
operating point of the inverter.
Moreover, it is of advantage that almost any standard driver may be equipped with the clamping
device and that the voltage limitation will be ensured automaticly for turn-off of the antiparallel
diodes, too.
Protection is guaranteed even in the case of failure of the driver supply voltage.
229
VCE-
VCE Detection
max
Driver
VCE-
VCE max Detection
Control-
signal
Driver
Figure 3.76 Active voltage limitation / active clamping
Master-slave conceps [110]

A modification of the commonly known master/slave principle, which originates from thyristor
technology, is also applicable to dynamic voltage symmetrization (Figure 3.77).
Only the bottom switch (master) is equipped with a complete driver circuit with auxiliary power
supply and potential-separated control pulse input. This is the major advantage of the principle.
The driver circuit of the top switch (slave) integrates nothing but the output stage. The
decoupling between master and slave is taken over by a high blocking diode. The slave will be
turned on as soon as its emitter potential has dropped to a point where the decoupling diode is
able to turn on, i.e. with a slight shift in time. The slave is turned off by blocking the decoupling
diode. Principally, several slaves may be connected in cascade.
While this concept is able to manage turn-off symmetrization very well, turn-on symmetrization
will be strongly restricted.
Therefore, a combination of the master/slave concept and active clamping is recommended.
The disadvantage of disadvantageous turn-on symmetrization can be ignored in ZVS-
applications [110].
230
Slave
Driver
Master
Driver
Control-
signal
Figure 3.77 Basic principle of the master/slave concept
Conclusions
In addition to the high resistance parallel resistors for static symmetrization, passive and/or
active measures to manage dynamic symmetrization must be taken when IGBT or MOSFET
modules are connected in series.
Except for active clamping the variants introduced will merely protect the transistors, so that
additional passive RC networks for protection of the inverse diodes will be necessary.
The combination of active clamping and a reduced RC network seems to be a good compromise
for symmetrization of the switching edges with regard to circuit requirements, reliability and
functionality [236].
3.8 Soft switching in ZVS or ZCS-mode / switching loss reduction

networks
3.8.1 Requirements and application fields

At present, converter technology is dominated by topologies related to impressed direct voltages.
IGBTs and MOSFETs are operated almost entirely in hard switching mode in these circuits, i.e.
they are subject to high energy dissipation and power dissipation peaks resulting in typical
switching frequencies between 3 kHz and 20 kHz (IGBTs) or 50 kHz (high voltage MOSFETs),
respectively.
Increasing the switching frequency will principally lead to reduction of size and weight of
passive energy stores (chokes, capacitors, transformers, filters), which is of interest, for example,
with respect to the integration of transformers into converter systems.
Typical application fields:
- battery charging,
- UPS with potential-isolated DC-DC-converter,
- conventional power supplies (switch-mode power supplies),
- PFC-circuits,
- industrial power supplies (welding, electroplating, inductive and capacitive heating etc.).
231
If the required switching frequency cannot be attained in a hard-switch application, the resulting
power dissipations have to be reduced.
Basicly, there are two ways of reducing switching losses:
1. Attachment of additional switching loss reduction networks, whilst keeping the basic
circuitry.
2. Soft switching in ZVS or ZCS-mode.
3.8.2 Switching loss reduction networks

Power-electronic switches with conventional thyristors, GTOs or MCTs (MOS-controlled
thyristors) require switching loss reduction networks in order to guarantee operation within the
safe operating area, i.e. these networks are unavoidable if the components are to live up to their
basic functions during switching mode.
In contrast to that, the SOA-characteristics of modern IGBTs and MOSFETs allow operation
without the attachment of networks, and additional networks may only serve to reduce switching
losses or support symmetry tasks in the case of cascading.
Figure 3.78 shows a conventional step-down converter with IGBT and simple switching loss
reduction networks.
D
L
R
A A A
D R
VDC RCD - RC - RCD -
IGBT
Snubber Snubber Snubber
C
B B B
iL LL RL
FWD
Figure 3.78 Step-down converter with IGBT and simple switching loss reduction networks
Reduction of turn-on losses (RLD-network):

At first, the IGBT is in off-state (vce vDC) and the load current is conducted through the free-
wheeling circuit.
The commutation process from the free-wheeling diode to the IGBT (inductive commutation) is
triggered by active turn-on of the IGBT. As soon as the network inductance has reached a certain
value, it will almost completely absorb the commutation voltage (corresponds to the input DC-
voltage of the converter) when the collector current rises, so that the collector-emitter voltage is
quickly reduced to a very low level. At the same time, the network inductance will effect a
reduction of the current commutation speed.
232
On consideration of both aspects, IGBT turn-on losses may be reduced substantially .

The characteristics of collector current and collector-emitter voltage correspond to soft switching
as explained in chapter 0.
In chapter 3.8.3 we will demonstrate that the attachment of air coils, with ratings of only some
micro-Henry, will be sufficient to reduce IGBT and MOSFET power dissipations very
efficiently.
In addition to the reduction of IGBT turn-on losses, the turn-off losses of the free-wheeling diode
will also be decreased during the inductive commutation, since the reduced current commutation
speed will lead to low-level reverse recovery peak currents.
The combination of R-D will create a free-wheeling circuit for the snubber inductance, which
will set a limit to IGBT and FWD-overvoltages during turn-off.
Recommendations for dimensioning:

1. Do not make dimensions for network inductance any higher than necessary for switching loss
reduction (see chapter 3.8.3).
2. Minimize the internal snubber network inductance.
3. The relation of R and L results in a time constant ( = L/R) necessary for internal energy
discharge of the inductance. This, in turn, will result in a minimum IGBT static off-time
(duty cycle limitation) to achieve efficient reduction of turn-on power dissipations (no
residual current left in L). On the one hand, increasing R will result in shortening the
minimum IGBT static off-time, on the other hand, however, it will effect a higher voltage
and, consequently, higher power dissipations in the turned off power semiconductors.
Reduction of turn-off losses (RCD-network):

At first, the IGBT is in on-state and conducts the load current.
The commutation process from IGBT to free-wheeling diode (capacitive commutation) is
triggered by active turn-off of the IGBT.
The load current quickly commutates from the IGBT to the parallel D-C-leg, by which the
collector current will decrease on simultaneous reduction of the collector-emitter dv/dt.
This way turn-off losses in the IGBT will be reduced. The characteristics of collector current and
collector-emitter voltage then correspond to soft switching as explained in chapter 0.
Chapter 3.8.3 will explain, among other things, that the power loss reduction effect, which is
achievable at a certain capacitance, is strongly dependent on the specific structure of the
transistor (MOSFET, NPT-IGBT, PT-IGBT).
At the end of voltage commutation, the free-wheeling diode will turn on with low losses and take
over the snubber capacitance current.
With the next turn-on of the IGBT the energy stored by the network capacitance will be
discharged by resistance R.
Recommendations for dimensioning:

1. Do not make dimensions for the network capacitance any higher than necessary for switching
loss reduction (see chapter 3.8.3).
2. Use fast snubber diodes with low turn-on overvoltage (forward recovery).
3. Use pulse-proof capacitors (film capacitors etc.) with low internal inductance.
4. Minimize loop inductance of the IGBT-RCD-network.
233
5. The product of R and C results in a time constant ( = R * C) necessary for internal energy
discharge of the capacitance. This, in turn, will result in a minimum IGBT on-time (duty
cycle limitation) to achieve an efficient reduction of turn-off power dissipations (no residual
voltage left in C). On the one hand, a reduction of R will result in shortening the minimum
IGBT on-time, on the other hand, it will effect a higher current and, consequently, higher
power dissipations during turn-on of the transistor.
Anyway, bigger inductive and capacitive snubber elements will always lead to longer
commutation times!
In pulsed circuit topologies, where inductive and capacitive commutation processes alternate
within one common commutation circuit, the energy discharge in the elements L and C is subject
to power dissipations during the following commutation process.
In applications using simple snubber networks, as described beforehand, the total energy stored
is converted to heat mainly in the network resistor, and partially also in the transistor (dissipative
snubber). Despite losses being reduced in the switches, the total efficiency of the circuit will not
be improved.
Furthermore, there is a variety of low-loss snubber networks well-known from the relevant
literature (non or low-dissipative snubbers), where the energy is stored in resonant circuits or fed
back to the DC-link. However, such types of circuits are often very complicated to dimension,
and the production of layout and circuitry is subject to a great deal of effort [258], [78].
3.8.3 Soft switching
3.8.3.1 Typical current and voltage characteristics / power semiconductor stress

Soft switching is another possibility to reduce losses in power electronic switches.
Actually, the operation of power electronic switches in ZVS-mode (zero-voltage-switch) or
ZCS-mode (zero-current-switch) is called soft switching (see chapter 0).
The variety of converter circuits working according to these principles is generally assigned to
resonance or quasi-resonance technology.
ZVS:
- The commutation process is started by active turn-off, switching losses are reduced by
parallel connection of the commutation capacitance CK to the switch,
- the commutation process is completed by passive, low-loss turn-on at a switch voltage of
vs 0,
- the commutation inductance LK has been minimized.
ZCS:
- The commutation process is started by active turn-on, switching losses are reduced by series
connection of the commutation inductance LK to the switch,
- the commutation process is completed by passive, low-loss turn-off at a switch current of is
0,
- the commutation capacitance CK has been minimized.
For corresponding commutation circuits please refer to chapter 0.

Soft switching is based on the pre-condition that only one kind of commutation process - either
inductive commutation/ZCS or capacitive commutation/ZVS takes place in the commutation
circuit of a converter. With this restriction the loss of one control possibility has to be accepted
in comparison to hard switching .
234
Soft switching can only be realized, if the polarities of the driving commutation voltage vK or of
the commutated output current iL are reversed between two commutation processes of the same
kind.
In the case of commutation voltage polarity reversal, a reversed voltage is applied to the switch
during off-state.
In the case of current polarity reversal, a reversed current is applied to the switch during on-state.
The currently available IGBTs, MOSFETs and diodes are designed and optimized for hard
switch applications only, where they feature similar characteristics.
On the other hand, comprehensive examinations during the past few years ([433], [44]) have
demonstrated that differing component structures and technologies behave differently in many
aspects during soft switching (see chapter 3.8.3.3).
However, these differences, , are not recognizable by the user from the currently available
datasheets.
Figure 3.79 shows an example of a low-loss converter system with ZVS and ZCS including an
HF-transformer, the functions of which would be suitable for use in photovoltaic, battery charge
or UPS applications.
HF- VOLTAGE CYCLO- VOLTAGE

HF-INVERTER TRANSFORMER CLAMPER CONVERTER CLAMPER
i b5
i S5
vS1 ZCS v S5
RC RC
S1 S3 S5 S7
ZVS
i S1 i acp
Rd Ld id
vd
vacp v acs
vL CC
CC
S2 S4
S6 S8
vC vC
Figure 3.79 Converter system with ZVS and ZCS [49]
The system consists of a ZVS DC/AC-inverter, an HF-ferrite-transformer and a ZCS-cyclo-

converter, which is able to convert the HF-alternating voltage of the transformer (e.g. 20 kHz,
trapezoidal) to a low-frequency voltage (e.g. 50 Hz, sinusoidal). The time-shifted alternating
switching of ZVS and ZCS guarantees permanent soft switching in the system.
Figure 3.80 shows typical current and voltage characteristics as well as stress of ZVS and ZCS
with this example of an converter.
235
t0 t1 t 2 t3 t4 t5 t6 t 7 t 8 t 9 t10 t 11 t12 t13

v acp
Vd
v S5 , i S5 , i b5
v S5
V acs i b5 tH
ZCS i S5
- V acs
- VC
v S1, i S1
Vd v S1
ZVS
t
i S1
Figure 3.80 Typical characteristics for the circuit of Figure 3.79 [49]
ZVS (switch S1), 1 voltage direction, 2 current directions:

1. Passive turn-on of ZVS (diode) almost free of losses on condition that vs 0 at time t2 (end of
capacitive commutation process from S2 to S1),
2. Reversal of current direction within ZVS between t3 and t4, due to switching procedure in the
cyclo-converter. The switch current which comes from the diode is impressed to the
antiparallel IGBT, which is ready to take over the current - i.e. the gate is triggered - with a
di/dt determined by the outer circuit. Power losses in the IGBT are caused by the process of
conductivity modulation.
3. Active turn-off of ZVS (IGBT) at t6: power dissipations during active turn-off are reduced by
effectiveness of parallel commutation capacitance CK (fast current commutation to CK and
dvCE/dt-limitation).
ZCS (switch S5), 2 voltage directions, 2 current directions:

1. Active turn-on of ZCS (IGBT) at t3: power dissipations during active turn-on are reduced by
the effectiveness of series connection of the commutation inductance LK (in this case stray
inductance of transformer; fast voltage commutation to LK and di/dt-limitation).
2. Passive turn-off of ZCS subject to switching losses with reverse-recovery-di/dt of series
diode at t9. The current in the related IGBT drops to zero. At this time, no switching losses
are generated in the IGBT.
3. Reversal of voltage direction at ZCS between t11 and t13, due to switching in the DC/AC-
inverter: the switch voltage which comes from the diode connected in series to the IGBT is
impressed with a dv/dt determined by the inverter.
Power dissipations generated in the IGBT are due to discharge of the residual storage charge
left in the n--base. The losses are mainly determined by the time difference tH (called hold-off
time) as well as by the charge carrier lifetime.
If the hold-off times are very short, the losses arising can be compared to tail current power
dissipations during hard switching.
236
3.8.3.2 Requirements on semiconductor switches and their drivers
ZVS:
Power semiconductors:
- have to feature active turn-off and good power-loss reduction behaviour during turn-off,
- for IGBTs: - short charge carrier lifetime,
- minor influence of junction temperature on tail charge and charge
carrier lifetime,
- low forward turn-on overvoltage during conductivity modulation with zero-voltage turn-on
and impressed di/dt,
- since ZVS-diodes do not turn off with reverse-recovery-di/dt and take on reverse voltage at
the same time, there are only small requirements to their reverse-recovery behaviour
compared to hard switching.
Driver circuit:
The driver circuit has to comply with the following minimum requirements:
- active turn-off of IGBT/ MOSFET and
- switch voltage monitoring and passive turn-on of ZVS at vS 0 V.
Modified ZVS-mode:
The duration of a capacitive commutation process can be approximated as follows:
tKc (CK * vK)/iL
Explanations: CK: commutation capacitance (power loss reduction capacitance),
vK: commutation voltage,
iL: load current to be commutated.
With low load currents, the commutation process in power converters may last an undesirably
long time, which might endanger faultless operation of the circuit. This can be avoided by
application of modified zero-voltage-switches, which will break off the commutation process
after an adjustable maximum commutation time by active turn-on towards the not yet completely
recharged commutation capacitance. However, this bears the consequence of increased
switching losses.
Figure 3.81 shows the principle operation of a modified ZVS.
237
v ref
&
iS
1
tKmax ON
t t
Driver vS
OFF
t
Figure 3.81 Principle of a modified ZVS
ZCS:
Power semiconductors:
have to feature active turn-on and good power-loss reduction behaviour during turn-on,
low power semiconductor capacitance
for IGBTs: - short charge carrier lifetime,
- minor influence of junction temperature on tail charge and charge
carrier lifetime,
short dynamic saturation periods during turn-on
diodes: low reverse recovery charges.
Driver circuit:
The driver circuit has to comply with the following minimum requirements:
active turn-on of IGBT/ MOSFET and
switch current monitoring and passive turn-off of the ZCS at iS 0 A.
Modified ZCS-mode:
The duration of an inductive commutation process can be approximated as follows:
tKi (LK * iL)/vK.
Explanations: LK: Commutation circuit inductance (power loss reduction inductance),
vK: commutation voltage,
iL: load current to be commutated.
With low commutation voltages or high load currents, the commutation process in power
converters may last an undesirably long time, which might endanger faultless operation of the
circuit. This can be avoided by the application of modified zero-current-switches, which will
break off the commutation process after an adjustable maximum commutation time by active
turn-off towards the still live commutation inductance. However, this bears the consequence of
increased switching losses. Furthermore, zero-current-switches have to be equipped with an
overvoltage protection in almost any application (see also Figure 3.79 and chapter 3.6.3).
Figure 3.82 shows the principle operation of a modified ZCS.
238
-
i ref
&
iS
1
tKmax
OFF
t t
Driver vS
ON
t
Figure 3.82 Principle of a modified ZCS
3.8.3.3 Features of switches
ZVS with PT- and NPT-IGBTs [43], [49]
zero-voltage turn-on with impressed di/dt

Before the IGBT is able to conduct a current, it has to be turned on by the driver. Since
conductivity modulation within the n--base will not have taken place before the current is taken
over, the IGBT will react to the di/dt-impression by transient increase of the on-state voltage and,
thus, by increased on-state losses at this time interval (forward recovery). Dynamic overvoltage,
duration of conductivity modulation and, consequently, power dissipations depending mainly on
the basic doping of the n--base, emitter efficiency, charge carrier lifetime, di/dt, switch current
final value (load current) and temperature.
NPT-IGBTs, which are characterized by low emitter efficiency and long charge carrier lifetime,
will respond by relatively low forward voltage peaks (Figure 3.83). However, the procedure,
may take more than 10 s.
By contrast, the transient forward voltage peaks of PT-structures exceed the stationary forward
voltage by 30 to 40 times (high emitter efficiency, short charge carrier lifetime). However, this
procedure will only take some 100 ns (Figure 3.83b). The contrary tendency of voltage peak and
process duration will result in a certain alignment of power dissipations of NPT and PT-IGBT-
ZVS, which may contribute substantially to the total power dissipation in high-switching-
frequency applications (Figure 3.84a and b).
If the ZVS-short-circuit protection is based on a vCE-evaluation, it has to be gated during di/dt-

impression to avoid breakdown of the converter.
239
Collector Current iC [A] Collector Current iC [A]

50,4 54
33,6 36
16,8 18
0 -0,3
Collector-Emitter-Voltage vCE [V] Collector-Emitter-Voltage vCE [V]
10,5 54
7 36
3,5 18
0 0
t=500 ns/div t=500 ns/div
a) b)
Figure 3.83 a) di/dt-impression in a 1200 V/50 A-NPT-IGBT (di/dt = 50 A/s; i L = 50 A)

b) di/dt-impression in a 1200 V/50 A-PT-IGBT (di/dt = 50 A/s; i L = 50 A)
vCEdyn [V] E ONdyn [J]
PT-low-vCEsat PT-low-vCEsat
PT-high-speed PT-high-speed
NPT
NPT
di/dt [A/s] di/dt [A/s]

a) b)
Figure 3.84 a) Dynamic forward voltage amplitude of 1200 V/50 A-NPT and PT-IGBTs
versus impressed di/dt (iL = 30 A, Tj = 30C)
b) Power dissipations during di/dt-impression of 1200 V/50 A-NPT and PT-
IGBTs versus impressed di/dt (iL = 30 A, Tj = 30C)
active, low-loss turn-off

During active low-loss turn-off the IGBT current can be commutated directly to the paralleled
capacitance CK with reduced collector-emitter dv/dt, which provides reduced switching losses.
The tail current characteristic, i.e. discharge of charge stored in IGBT after blocking of
MOSFET-channel, is substantially determined by the collector-emitter dv/dt. Increasing the
commutation capacitance will lower the initial tail current value (comparable to a capacitive
current devider between IGBT and snubber capacitor). At the same time, the tail current will be
prolonged, which impairs the reduction of turn-off losses. For NPT-structures with long charge
carrier lifetime this will lead to unsatisfactory switching loss reduction (Figure 3.85a, Figure
3.86). On the other hand, the oscillogram in Figure 3.85b shows that with PT-structures the tail
current may already have dropped to zero before the collector-emitter voltage has reached the
level of the outer commutation voltage. The result of tests with 1200 V/50 A -PT-IGBT-modules
was that at a commutation capacitance CK = 30 nF, turn-off switching losses may be reduced by
50 % compared to hard switching (Figure 3.86). With NPT-IGBTs switching losses could be
reduced by merely 20 %.
240
Collector Current iC [A] Collector Current iC [A]

33 30
21,4 19,5
9,8 9
-1,8 -1,5
Collector-Emitter-Voltage vCE [V] Collector-Emitter-Voltage vCE [V]
540 561
360 374
180 187
0 0
Eoff =1,94 mJ t=500 ns/div Eoff=0.83 mJ t=200 ns/div
a) b)
Figure 3.85 a) Low-loss turn-off of 1200 V/50 A NPT-IGBTs at CK = 47 nF

b) Low-loss turn-off of 1200 V/50 A PT-IGBTs at CK = 30 nF
Eoffsoft/Eoffhard
Eoff [mJ]
NPT
PT-low vCEsat
NPT PT-low vCEsat

PT-high speed
PT-high speed
a) b)
Figure 3.86 a) Turn-off power dissipations of 1200 V/50 A-IGBTs versus commutation
capacitance CK (vK = 500 V; iL = 50 A; TC = 80C)
b) Turn-off power dissipations related to hard switching of 1200 V/50 A-IGBTs versus commutation
capacitance CK (vK = 500 V; iL = 50 A; TC = 80C)
ZVS with MOSFETs, [43]

MOSFETs are unipolar devices which should not be charged or discharged with any storage
charges. This results in the following special features for use in ZVS:
- There is no dynamic forward overvoltage during zero-voltage turn-on with impressed di/dt.
- Within the same class of devices the comparison to IGBTs shows that switching losses in
MOSFETs with commutation capacitances of some nF may be almost completely avoided
during turn-off. This is also supported by the relatively high output capacitance of MOSFETs
in the commutation circuit,
- The process, where the off-state transistor is subject to high dvDS/dt, which is critical for
MOSFETs (see chapter 3.5), does not exist in ZVS-mode.
Therefore, MOSFETs may be driven principally by negative gate-source voltage.
241
Fast diodes in ZVS

Fast diodes in ZVS feature the following special characteristics:
In ZVS diodes will not turn off with reverse-recovery-di/dt at simultaneous take-over of
reverse blocking voltage. The reverse-recovery behaviour of fast diodes is therefore negligible
compared to hard switching.
However, optimized dynamic turn-on is still required in ZVS-applications. In this respect, the
use of CAL-diodes is of special advantage (see chapter 1.3).
ZCS with PT- and NPT-IGBTs [44], [49], [146]

active, low-loss turn-on
Figure 3.87 shows the oscillogram of low-loss turn-on of a 1200 V/50 A NPT-IGBT as well as
the dependence of turn-on losses of different power semiconductors on the commutation
inductance LK. It becomes clear that IGBTs and MCTs, respectively, are capable of optimized
switching loss reduction. Power dissipations compared in the IGBTs and MCTs are almost
identical at a commutation inductance of only 3H and, as for IGBTs, they amount to merely
about 15 % compared to hard switching.
In contrast to turn-off during ZVS-mode, PT- and NPT-IGBTs can be turned on with equal
optimal loss reduction.
Power dissipations occurring during turn-on of IGBTs in ZCS-mode are caused by the processes
during dynamic saturation.
EON [mJ]
505
335
BJT
166
-4 NPT-IGBT
collector current iC [A]
72,1
48,1 PT-IGBT
24
MCT
0
t=250ns/div
a) b) LK [H]
Figure 3.87 a) Low-loss turn-on of NPT-IGBT (LK = 3.6 H)

b) Turn-on power dissipations of ZCS as a function of the commutation inductance LK (vK = 500 V,
iL = 30 A, Tj = 30C)
BJT = Bipolar Junction Transistor, MCT = MOS-Controlled Thyristor
Voltage reversal in turned off ZCS with removal of residual IGBT storage charge
Figure 3.88 shows the processes involved in passive turn-off of IGBT-ZCS (IGBT with series
and antiparallel diode) with subsequent change of the switch voltage polarity.
It becomes clear that, with PT-structures the residual charge to be removed is low (short charge
carrier lifetime) when the IGBT takes on forward blocking voltage after the hold-off time which
will reduce power dissipation during this process.
242
switch current i S [A] switch current i S [A]

26,7 27,1
14,3 14,4
1,9 iS 1,7
switch voltage vS [V] -10,4 switch voltage v S [V] -11

VS
522 571
138 172
-246 -228
-630 -627
NPT - IGBT t=1 s/div PT - IGBT t=1 s/div
Figure 3.88 Turn-off characteristics of 1200 V/50 A-NPT and PT-IGBTs (tH = 1.3 s, L K = 10H)
The dependence of residual storage charge on hold-off time is shown in Figure 3.89a. Here, the
advantages of PT-structures are illustrated very clearly. On the contrary, storage charges of PT-
structures are more temperature-dependent, which restricts the maximum switching frequency
due to the risk of thermal instability especially in the case of short hold-off times (Figure 3.89).
Qs [C] Qs [C]
NPT-IGBT (0,02C/K)
NPT-
IGBT Low-
VCEsat-PT-IGBT
(0,07 C/K)
High-Speed-PT-
IGBT
Low-VCEsat-PT- High-Speed-PT-IGBT
IGBT (0,04 C/K)
tH[s] Tj [C]
a) b)
Figure 3.89 a) Residual storage charge of PT and NPT-IGBT-ZCS as a function of hold-off time (vK = 400 V,
iL = 30 A, LK = 10H, T j = 60C)
b) Storage charge of PT and NPT-IGBT-ZCS as a function of the transistor junction temperature
(vK = 400 V, iL = 30 A, LK = 10 H, t H = 1.3 s)
An IGBT-ZCS-driver circuit is introduced in [44], where an additional collector current is fed to

the IGBT by the driver during hold-off time to remove the storage charge. This measure had
proven to effect a drastic reduction of power dissipations during blocking voltage take-on,
especially for hold-off times tH > 2 s.
ZCS with MOSFETs

The following special features have to be considered when using MOSFETs in ZCS:
Since MOSFETs do not feature dynamic saturation, MOSFETs with very small (...1 H...)
series power-loss reduction inductances may almost be relieved completely of turn-on losses.
However, the high output capacitance (typical for MOSFETs) will have negative effects on
turn-on power dissipations. If high switching frequencies are applied (> 50 kHz), the resulting
share of power losses has to be considered as a part of the total power dissipation.
243
Due to the unipolarity of MOSFETs there will be no removal of residual storage charge
during change of polarity of the switch voltage at the end of hold-off time. On the other hand,
the relatively high output capacitance has to be recharged.
Fast diodes in ZCS

The following special features have to be considered:
Diodes in ZCS will turn off with reverse-recovery di/dt at simultaneous take-on of reverse-
blocking voltage. Due to the existing commutation inductances, current will be commutated
in the diode at a lower speed compared with hard-switching converters (lower reverse current
peak, reduced turn-off losses).
The use of fast diodes as series diodes of IGBTs or MOSFETs in ZCS requires very good
dynamic turn-on behaviour of the diodes (see chapter 1.3).
3.8.3.4 Conclusions
The behaviour of IGBTs during hard switching is not applicable to soft switching. In principle
PT-IGBTs with a shorter charge carrier lifetime are more suitable for soft-switching applications
than NPT-IGBTs due to the dynamic processes explained before. This had been proven in tests
with 1200-V-switches by substantial reduction of total power dissipations in PT-IGBT-switches.
This comparison may not be transferred to other voltage classes. For new 600 V-devices the
result may be in favour of NPT-structures in case thin-wafer technologies are applied (reduced
forward voltage drop and carrier charge) due to the improved temperature-stability of the device
parameters.
MOSFETs - especially when used as ZVS - are preferred for soft-switching applications due to
their unipolar character.
Because the foward losses are high by principle, application at high switching frequencies
(> 50 kHz) as well as in the low voltage/ high current range is recommended.
New MOSFET-technologies with decreased RDSon-values (e.g. CoolMOS) provide even more
fields of application.
Since there is a variety of low-loss converter topologies with specific requirements to switches, a
standard conclusion on the limitation of frequencies of IGBT and MOSFET switches cannot be
drawn.
In the exemplary circuit in Figure 3.79 the following realistic maximum frequencies are given
for 1000..1200 V/ 20..50 A- devices:
NPT-IGBT: ZVS: 50 kHz ZCS: 70...80 kHz

PT-IGBT: ZVS: 70...80 kHz ZCS: 80...90 kHz
MOSFET ZVS: > 200 kHz ZCS: > 200 kHz
244
3.9 Handling of MOSFET, IGBT, MiniSKiiP and SKiiPPACK modules
3.9.1 Sensitivity to ESD and measures for protection

All MOSFET or IGBT power modules are sensitive to ESD (Electro Static Discharge) because
the thickness of the gate isolation only amounts to some ten nanometers.
The degree of sensitivity is dependent on the input capacitance value (MOSFET: CGS gate-
source capacitance/IGBT: CGE gate-emitter capacitance).
IGBTs and power MOSFETs with big chip areas are characterized by high input capacitances
and are classified as minor sensitive compared to small-signal components according to standard
MIL-STD 883C, procedure 3015.6.
With respect to the handling of IGBT or MOSFET power modules, the specifications of the
MIL-standard mentioned above as well as of standard DIN VDE 0843 TS, which is identical to
IEC 801-2, must be adhered to.
Inspection and further processing should be carried out only at specially prepared workplaces
with conductive tables, ground connections etc. by suitably dressed staff (antistatic overalls,
wrist strap, if available). All transportation and assembly equipment as well as PCBs have to be
adjusted according to the requirements of ESD-sensitive components before they are subjected to
further processing.
The power modules are delivered with gate and source terminals (MOSFET) or gate and emitter
terminals (IGBT) short-circuited by conductive foam or rubber, self-sealing copper sheet, a
pushed-on annular rivet or suitable conductive packaging system. As far as possible, this short
circuit should be removed not until connecting the gate.
3.9.2 Mounting instructions

For the sake of optimal thermal connection between power module and heatsink, module base
plate and heatsink surface must be clean and dust-free. The heatsink roughness should not
exceed 10 m (MiniSKiiP and SEMITOP: 6.3 m), flaws must not contribute to an unevenness
of more than 20m for a distance of 10 cm.
Before the power module is mounted to the heatsink, a very thin (30...50 m) and homogeneous
layer of thermal paste has to be applied to both mounting surfaces by means of a rubber roller,
for example.
For SEMIKRON power modules we recommend the use of thermal paste P12 (by Wacker
Chemie), which, however, contains some silicone. Another suitable silicone-free paste is, for
example, WLPF5 (by Fischer-Elektronik).
For the selection of connecting and fixing screws please refer to the following:
- assembly with washer and spring ring or crinkle type spring washer;
- minimum and maximum length of connecting screws according to module drawing and
arrangement of busbars;
- minimum strength given in databooks or resulting from required mounting torque;
- surface finish and corrosion resistance.
245
Suitable multiple purpose screws with non-detachable washers and spring rings are available by
SEMIKRON on request.
The torques indicated in the datasheets must be considered on assembly with screws. At first, the
mounting screws should be tightened diagonally at about half the torque, and with full torque
afterwards, using the same sequence. Due to subsidence of thermal paste, the screws should be
tightened up after a few hours.
With regard to solder contacts please refer to the solder specifications in the datasheets.
For the assembly of MiniSKiiPs please ensure that the contact pads on the PCB do not show any
inadmissible tin bulges, which might neutralize the spring effect. If necessary, the pads should be
covered during flow soldering.
If a no-clean-flux is used, cleaning of the PCB can be omitted.
3.9.3 SKiiPPACK: thermal testing ex works [265]], [93]], [233]]

SKiiPPACK-modules are delivered with heatsink; the module manufacturer guarantees proper
assembly and optimal layout of thermal connections.
The final functional test comprises a complete heating procedure to check thermal connections.
This will avoid assembly problems at the customer and guarantee high reliability ex works.
3.10 Dimensioning software
3.10.1 Model levels of mathematical circuit description

Actually, dimensioning of circuits with power semiconductors is identical to the commutation
circuit layout. If the connecting parameters of the commutation circuits can be defined very
clearly, considering all possible spreads, the layout can be determined very easily. In order to
limit a system to the parameters of its commutation circuit, the system design has to be more
comprehensive to aim at clear ratings of connecting parameters. Regarding a converter system,
the final layout of control unit, main energy buffers and substantial filter elements have to be
determined before dimensioning the power semiconductor environment and cooling system.
Such a top-down system design automatically requires the use of different model levels with
contrary system extent and model intensity (Figure 3.90).
246
Model
Level
System Extent
I
. .
. .
. . Goal of
. . Computation
. .
.
VI Information
Content
Limited Computation Performance
Figure 3.90 Relation between model level, system extent and information content
The information content of a model level determines, at the same time, the possible goals of
computation. Figure 3.91 shows a survey of the different model levels of circuit computation.
Since the switch network is the dominating part of a converter system, model levels are aligned
with the kind of mathematical consideration of the switching processes.
linearized average model (model level I)

By linearization in one operating point, multiple linkages between steady values and non-linear
characteristics are replaced by linear correlations. The system is then described by a linear
differential equation system, which is valid for only a sufficiently small tolerance around the
operating point. This level of approximation is applicable to examinations of the total system
stability including control circuits, as long as there are no limitations and all steady values are
monitored and kept with regard to deviations from the operating point. Comprehensive
simulation system software originating from automatic control technology is available. In this
respect, the efforts necessary for linearization by Taylor polynomials must not be
underestimated.
non-linear average model (model level II)

If the transfer behaviour of a power-electronics basic circuit is described by the transformed
average steady values ignoring switching functions, the non-linear average model will be the
result. The average values or fundamental harmonics are related to the period duration of the
power semiconductor switching frequency. The continuous or sampled control function is
multiplicatively linked to the steady values to be transformed. Especially if the transformation
relations are definite (pulsed circuits, continuous mode), the system can be described most
efficiently at this model level, if the influence of the pulse frequency may be ignored. The results
are valid on condition that there is an infinitely high pulse frequency, and the approximation is
relatively accurate, if the steady values do not change considerably during one pulse frequency
period. Also in this case, simulation programs oriented towards automatic control technology are
recommended as software.
247
Model Level I Model Level II Model Level III

Linearised Average Model Nonlinear Average Model Ideal Commutation Model
B2 - Bridge Configuration
Vz Vd
iz
D Vd id
D
vd Vz
iz id
Vd
Vd =V z D i z = id D
D
Model Level IV Model Level V

Real Commutation Model 2 - Pole - Switch Model
V(t)
V(t)
iz
id
Turn - on
vd Vz ZCS
i(t)
ZVS ZCS
i(t)
Turn - off
ZVS
Model Level VI
3 - Pole - Switch Model
Ic
c
Cbej Cbed
In(x=0) Ip(x=0)
b
Rb
PNP-BJT IGBT
In(x=W)
Ip(x=W) Model
MOSFET Cgdj
d
Cgd0 IMOS
Lg Rg
Gate Cdsj
g
Cgs0
s
Le
Emitter
Figure 3.91 Model levels for circuit computation
248
ideal commutation model (model level III)

This model level is based on an idealised chopper function. Switching as well as current and
voltage commutation procedures run in an infinitely short period of time. Regarding the
equivalent commutation circuit, this means that commutation inductances and capacitances will
be neglected. Since switching and commutation times are short compared to the pulse period
duration in hard switching applications, this model level gives quite accurate results especially
for hard switching basic circuits. Direct control functions are now turning to discrete control
functions, or they have to be generated by the converter control unit from the quasi-continuous
input control parameters according to the control principle of the switch network. The
continuous or sampling system description, which is still feasible by average models, can be only
partly utilized due to the switching function. Any switch state alteration, which is dependent on
control or system procedures, will lead to a sequence of system states, any of which is to be
described by a separate equation system. Numerically, two different methods have developed.
The first, which is state-oriented, calculates the individual equation system of the current state
with minimum ordinal number. The second, which is network-oriented, describes the switch
network with a uniform equation system with process-dependent changing of parameters. In both
cases a numeric time-step control with event detection and consideration function will be
required. Both methods feature specific advantages and disadvantages.
real commutation model (model level IV)

The real commutation model is based on consideration of elements in the commutation circuit. In
circuits with zero-voltage and zero-current-switches especially, the commutation time may no
longer be ignored with reference to the period duration of the switching frequency. Switching
times continue to be ignored. Whereas commutation is started by an active control signal, it is
finalized by passive processes in the electrical network (zero-current or zero-voltage-crossing).
Consideration of control parameters by a continuous or sampling control system as well as
converter control unit and numeric description of the complete circuit is realized by the same
methods as in the ideal commutation model.
2-pole-switch model (model level V)

This model level is applied if switching times of power semiconductors during real commutation
can no longer be ignored. In resonant or quasi-resonant basic circuits especially, it is of decisive
importance to the overall function that all conditions of resonance are obeyed. Since attenuation
of the resonant circuits is mainly determined by the switching losses of the power
semiconductors, the 2-pole-switch model comprises zero-current or zero-voltage-switches by
current or voltage sources with fixed time functions during switching. These time functions are
subject to experimental determination with reference to the specific operating point. Other than
with the real commutation model, detection of time transition between switching and
commutation process is required in case of 2-pole-switch model.
3-pole-switch model (model level VI)

At this model level, the state parameters are described by continuous functions, since the power
semiconductor characteristics are realized by an equivalent network with consideration to the
control input. The system may only be impaired by discontinuities resulting from the driver
control leads. Therefore, system description at this level demands a model library, which
comprises all power semiconductors used including active components of, at least, the driver
output units. Semiconductor models consist of concentrated passive elements and active current
249
and voltage sources. Exact parameters are only determinable by comprehensive measurements
and data by the semiconductor manufacturer. Due to the system extent this model level will
mostly be restricted to the calculation of single switching frequency periods. Therefore, it is to be
regarded as an efficient aid for switch dimensioning, which is less suitable for system
optimization. Numerically, we always recommend using a network-oriented method due to the
high number of nodes in the electrical circuit.
When selecting simulation software, the goal of computation and the resulting model level have
to be clearly defined. Simulation tools which are equally suitable for all model levels do not
exist. State and control or sample parameters in model levels I and II are constant, which makes
them applicable to description methods used in the field of control techniques. There is a variety
of simulation tools for this field of application. Model level VI is tailored towards the calculation
of electrical networks and is offered by a number of suppliers in many variants. As for the model
levels in between, the specialties of the varying state and control parameters have to be taken
into consideration, which requires a special numeric realization of time-step control and event
detection.
3.10.2 SEMIKRON software service

SEMIKRON offers a variety of possibilities to calculate and simulate many kinds of different
circuits and load conditions to give application support for power modules, especially for
SKiiPPACK and MiniSKiiP. The most important tool available for the customer is the program
package SKiiPsel, which is, however, restricted to the calculation of SKiiPPACKs and
MiniSKiiPs [273], [274], [276].
SKiiPsel is available on the SEMIKRON-CD-ROM [265].
This program offers the customers using SKiiPPACK and MiniSKiiP-components the possibility
of determining IGBT and diode power losses in important voltage-supplied circuits on condition
there is sinusoidal output current based on fixed driving conditions.
Development of the program was mainly based on user-convenience with respect to simple user
interface, useability of program without additional training and fast assessment of the
components for its application requirements.
Based on the operating conditions to be entered (current, voltage, frequency, load cycle,
temperature) the program is able to calculate power losses in the IGBTs and free-wheeling
diodes and the resulting chip and heatsink temperatures.
The program will select a suitable component by means of selection criteria determined by the
user, and it will check the suitability of the customers circuit arrangement.
With respect to cooling conditions, the user is free to choose specific options or to select those
stored in the program (air or water cooler, rate of flow of coolant).
Calculation results are given graphically and as a report via ACCESS. Results about the
temperature cycles under the calculated load conditions set up by the program will make
assessments of the expected power semiconductor lifetime possible.
SKiiPsel works with simple characteristic models based on measured and interpolated
dependencies.
The characteristics required for IGBT and diode chips used in SKiiPPACKs and MiniSKiiPs are
shown below:
250
VCE = f (IC) (IGBT) VF = f (IF) (diode)

VCE = f (Tj) VF = f (Tj)
and power losses in IGBT/ free-wheeling diode arms
Eon = f (IL) Eoff = f (IL)

Eon = f (Tj) Eoff = f (Tj)
generated when
- the SKiiPPACK is driven by the integrated driver
- the MiniSKiiP is driven according to recommendations given in the databook.
They are stored in the program and are not accessible to the user.
IGBT and diode power losses are calculated iteratively depending on output current, chip
temperatures and cooling conditions according to the principle described in chapter 3.2.
MathCAD
Another possibility of application support is the calculation of circuits with non-sinusoidal
output currents and conventional IGBT or MOSFET modules, which are not included in the
SKiiPsel database. For this, SEMIKRON has developed a special program package based on
MathCAD, which is able to produce thermal simulations of any customer circuit, e.g. buck and
boost converters, current source inverter systems and line commutated converter topologies.
Apart from maximum ratings and characteristics of SEMIKRON power semiconductors the
internal database contains, for example, data on heatsinks and experimental results of load cycle
testing with power modules.
Therefore, calculations on temperature cycling and component lifetime are possible for any load
cycles.
251
4 References
4 References
[1] Hierholzer, M.; Brunner, H.; Laska, T.; Porst, A.: "Characteristics of High Voltage IGBT Modules"
PCIM 1995, Nrnberg; Proc. Power Electronics, pp. 135-139
[2] Griessel, R.; Tursky, W.: "The Latest Step in Intelligent Integrated Power"
PCIM 1995, Nrnberg; Proc. Power Electronics
[3] Majumdar, G.; Hatae, S.; Fukunaga, M.; Oota, T.; Mori, S.; Thal, E.: "600 V HVIC Incorporated Application
Specific IPMs for Low Power Motor Control", PCIM 1995, Nrnberg; Proc. Power Electronics, pp. 155-161
[4] Hertrich, H., Reinmuth, K.: "HITFET-A New Generation of Intelligent Low Side Switches"
PCIM 1995, Nrnberg, Proc. Power Electronics, pp.9-15
[5] Konrad, S.; Anger, K.: Electro-thermal Model for Simulating Chip Temperatures in PWM Inverters"
PCIM 1995, Nrnberg, Proc. Power Electronics, pp. 219-228
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[338] R.Krmmer, T. Reimann, G. Berger, J. Petzoldt, L.Lorenz: On-line calculation of the chip temperatur of
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[339] U. Scheuermann, J. Lutz: High Voltage Power Module with Extended Reliability, EPE99-CD-ROM-
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[340] L. Lorenz: COOLMOS a new approach toward an idealized power switch, EPE99-CD-ROM-
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[341] Wheeler, N.; et. al.: A new 1200 V PT IGBT module using trench gate structure and local life time control,
EPE99-CD-ROM-Proceedings
[342] P.O. Jeannin, M. Akhbari, J.L. Schanen: Influence of Stray Inductances on Current Sharing during
Switching Transitions in Paralleled Semiconductors, EPE99-CD-ROM-Proceedings
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4 References
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semiconductor devices, EPE99-CD-ROM-Proceedings
270
3.11. [estofazni jednostrani ispravlja~ 1
3.11.[estofazni jednostrani ispravlja~
Za dobijanje usmerenih struja u postrojenjima ve}ih i najve}ih snaga koriste se {estofazne i vi{efazne sprege
koje u odnosu na trofazne sprege obezbe|uju u prvom redu manju valovitost struje i napona na prijemniku a uz to bolji
sa~inilac snage postrojenja, ve}i stepen iskori{}enja uz manje investicione tro{kove. Vi{efazne sprege naj~e{}e se
dobijaju pogodnim povezivanjem trofaznih i {estofaznih sprega.
t
iT6 iT1 iT2 iT3 iT4 iT5 iT6 iT1 iT2
t
Sl. 3.50. [estofazni jednostrani ispravlja~.
Na slici 3.50. je prikazan {estofazni jednostrani ispravlja~ jer su namotaji sekundara transformatora povezani
tako da ~ine {estofaznu zvezdu. Talasni oblik napona na optere}enju je isti kao kod trofaznog mostnog ispravlja~a
(slika 3.Error! Bookmark not defined..) s tom razlikom {to se, kod {estofaznog jednostranog ispravlja~a, napon na
2 Ispravlja~i
opter}enju sastoji od delova faznog napona sekundara transformatora dok se kod trofaznog mostnog ispravlja~a napon
na opter}enju sastoji od delova me|ufaznog napona sekundara transformatora pa je prema (3.Error! Bookmark not
defined.) srednja vrednost napona na optere}enju:
Ud =
3 2E

cos . bg (3.240)
Snaga dimenzionisanja transformatora
Efektivna vrednost struje kroz sekundarne namotaje transformatora je:

T
I =
1
T z
6
0
2
I d dt =
Id
6
. (3.241)
Efektivna vrednost struje kroz primarne namotaje transformatora je:

T
I =
2
T z
6
0
2
I d dt =
Id
3
. (3.242)
Snaga na koju treba dimenzionisati transformator je srednja vrednost prividnih snaga primara i sekundara
transformatora:
S=
1
2
c
S + S =
1
2
I
h FGH
m 3
I
3 U d + 3 E d =
6 2
IJ
3 E Id
K
FG 1 + 2 IJ .
H 3 6K (3.243)
Maksimalna snaga kojom se energija prenosi optere}enju postiè se onda kada je najve}i napon na optere}enju,
odnosno za ugao paljenja tiristora = 0. Prema (3.240) ova snaga iznosi:
3 2
P0 = EI d . (3.244)

Odnos snage na koju je potrebno dimenzionisati transformator i maksimalne snage kojom se energija moè prenositi
optere}enju je:
S
=

FG 1 + 2 IJ = 155
P0 2 2 H 3 6K . . (3.245)
Iz ovog izraza se vidi da je iskori{}enje transformatora znatno manje nego kod trofaznog mostnog ispravlja~a
(S/P0 = 1.05).
Spektar struje transformatora
Lo{e iskori{}enje transformatora kod ove sprege ispravlja~a je posledica velikih harmonijskih izobli~enja struje
sekundara transformatora. Na svakom stubu transformatora struje sekundara stvaraju magnetopobudnu silu M2.
Razvojem ove magnetopobudne sile u furijeov red:

bg
M2 t = Bk sinb kt g , (3.246)
k =1
dobija se amplituda k-tog harmonika:

2
LM FG IJ FG IJ OP .
Bk =
2

3
z

Id
m
b gb g 2I
sin kt d t = d cos k
kmN H K

3
cos k
2
H
3 KQ (3.247)
Iz izraza (3.247) se vidi da postoje samo neparni harmonici. Amplitude neparnih harmonika ~ija je u~estanost jednaka
celobrojnom umno{ku trostruke u~estanosti mre`nog napona iznose:
3.11. [estofazni jednostrani ispravlja~ 3
Bk =
4 Id
km
b
k = 3 2n 1 ;g n = 1,2,3, ... , (3.248)
dok su amplitude ostalih neparnih harmonika:
Bk =
2 Id
km
b g
k = 2n 1 ; n = 1,2,3, ... ; b g
k 3 2n 1 . (3.249)
Kod veze transformatora trougao - {estofazna zvezda, kako je to prikazano na slici 3.50. struje harmonika ~ija je
u~estanost jednaka celobrojnom umno{ku trostruke u~estanosti mre`nog napona zatvaraju se u trouglu jer su
me|usobno u fazi. Kod veze transformatora zvezda - {estofazna zvezda ako je u primaru priklju~en nulti provodnik,
kroz ovaj provodnik te~e zbir struja harmonika ~ija je u~estanost jednaka celobrojnom umno{ku trostruke u~estanosti
mre`nog napona, a ako nulti provodnik nije priklju~en ove struje se ne mogu zatvoriti u primarnom namotaju
transformatora, pa se javlja magnetopobudna sila prinudnog magne}enja Mpm, a struje primara transformatora stvaraju
magnetopobudne sile M1 = M2 Mpm (slika 3.51.). Stga se, kod ove sprege ispravlja~a izbegava veza primara
transformatora u zvezdu.
Sl. 3.51. Relativne vrednosti magnetopobudnih sila transformatora.
Napon dimenzionisanja poluprovodni~kih prekida~kih elemenata
Osim lo{eg iskori{}enja trensformatora nedostatak {estofaznog jednostranog ispravlja~a u odnosu na trofazni
mostni ispravlja~ je {to se za istu srednju vrednost napona na optere}enju tiristori moraju dimenzionisati na dvostruko
ve}i inverzni napon. Kod {estofaznog jednostranog ispravlja~a maksimalna vrednost inverznog napona tiristora jednaka
je dvostrukoj amplitudi faznog napona sekundara transformatora pa je odnos maksimalne vrednosti inverznog napona
tiristora i maksimalne srednje vrednosti napona na optere}enju:
Ur 2 2 E 2
= = , (3.250)
Ud 0 3 2E 3

dok je kod trofaznog mostnog ispravlja~a maksimalna vrednost inverznog napona tiristora jednaka amplitudi
me|ufaznog napona sekundara transformatora pa je odnos maksimalne vrednosti inverznog napona tiristora i
maksimalne srednje vrednosti napona na optere}enju:
Ur 6E
= = . (3.251)
Ud 0 3 6E 3

4 Ispravlja~i
Sprega transformatora zvezda - ra~vasta zvezda
Za ovu spregu, ~ija je {ema sa vektorskim dijagramom data na slici 3.52. vaì isti izraz za srdenju vrednost
napona na optere}enju kao za prethodno opisanu {estofaznu spregu (3.240).
Sl. 3.52. [estofazni jednostrani ispravlja~ sa transformatorom u sprezi zvezda - ra~vasta zvezda.
Vidi se da ova sprega ima tri unutra{nje i {est spolja{njih grana sekundara. Kroz spolja{nje grane proti~e struja
pojedinih tiristora, dakle strujni impulsi u trajanju jedne {estine periode, pa je efektivna vrednost struje u spolja{njim
granama:
I
I6 = d ,
bg (3.252)
6
a u unutra{njim granama proti~e struja koja je jednaka zbiru struja dve spolja{nje grane, dakle strujni impulsi u trajanju
jedne tre}ine periode, pa je efektivna vrednost struje u spolja{njim granama:
I
I3 = d .
bg (3.253)
3
U ovoj sprezi nema fluksa prinudnog magne}enja zato {to postoje uvek dve jednake magnetopobudne sile na dva
razli~ita stuba transformatora. Fazni napon sekundara transformatora je:
E = 2
E FG IJ
cos

= 3
E
m=
N
m H K
6 m N
. (3.254)
3.12. Sprega dva ispravlja~a sa me|ufaznom prigu{nicom 5
Struja kroz primarni namotaj te~e za vreme proticanja struje kroz sekundarne namotaje koji se nalaze na istom
stubu transformatora. Tako, na primer, u fazi "S" struja }e imati dva impulsa ~ije je trajanje 2/3: jedan pozitivan kada
rade faze 3 i 4 i jedan negativan kada rade faze 6 i 1. Efektivna vrednost struje primara transformatora je:
Id 2
I = . (3.255)
m 3
Snaga na koju treba dimenzionisati transformator je srednja vrednost prividnih snaga primara i sekundara:
S=
1
2
c h FGH
S + S =
1
2
I
3E d
m
2
3
I
JK
+ 3EIb3g + 6 EIb 6g , (3.256)
1 F I 2 E I d E I dI
S=
2 GH
3E d
m 3
+3
3 3
+6
3 6
JK
. (3.257)
Prema (3.254) sledi da je E'/m=E"/ 3 pa je:

F
1 E 2 E I d E I d I F 1IJ
S=
2 GH
3
3
Id
3
+3
3 3
+6
3 6
= JK GH 2+
2
E I d .
K (3.258)
Imaju}i u vidu (3.240), odnos snage na koju je potrebno dimenzionisati transformator i maksimalne snage kojom se
energija moè prenositi optere}enju je:
S
=
FG 2+
1IJ

= 1.42 ,
P0 H K
2 3 2
(3.259)
dakle iskori{}enje transformatora je ne{to bolje nego kod prethodno opisane sprege. Osim toga i komutacioni pad
napona je manji jer u komutaciji u~estvuju induktivnosti rasipanja polunamotaja sekundara. Tako, pri komutaciji faza 1
i 2, delovanje induktivnosti rasipanja dveju spoljnih grana se poni{tavaju jer se nalaze na istom stubu transformatora, pa
u komutaciji u~estvuju induktivnosti rasipanja dveju unutra{njih grana 001 i 002. Isto tako pri komutaciji faza 2 i 3 u
komutaciji u~estvuju induktivnosti rasipanja dveju spoljnih grana 022 i 023 jer se kroz unutra{nji namotaj 002 struja ne
menja. S obzirom na bolje iskori{}enje transformatora i manji komutacioni pad napona ova sprega se koristi u
postrojenjima manje i srednje snage (do nekoliko stotina kilovata). Ipak treba imati u vidu da je cena transformatora
ne{to ve}a zbog ve}eg broja izvoda.
3.12.Sprega dva ispravlja~a sa me|ufaznom prigu{nicom

Kada na svakom jezgru trofaznog transformatora postoje pored primarnog i dva identi~na sekundarna namotaja
mogu}e je ostvariti dve sekundarne zvezde u opoziciji. Povezuju}i zvezdi{ta ovih zvezda preko jedne prigu{nice sa
srednjim izvodom (Xm) ostvaruje se sprega ispravlja~a prikazana na slici 3.53.
Dve sekundarne zvezde rade nezavisno jedna od druge a paralelno u odnosu na prijemnik. Nezavisan rad ovih
sekundara omogu}uje prigu{nica Xm spre~avaju}i da se pojavi struja komutacije izme|u dve sekundarne zvezda ~ak i u
slu~aju da postoji, pri jednovremenom radu dva tiristora, potencijalna razlika izme|u dva zvezdi{ta.
Na slici 3.54. su prikazani karakteristi~ni talasni oblici napona istruja za ispravlja~ sa uglom paljenja =00
(diodni ispravlja~). Npon na me|ufaznoj prigu{nici je jednak razlici faznih napona u granama ~iji tiristori provode. Ako
posmatramo period kada zajedno provode tiristori T5 i T6 ili tiristori T2 i T3 napon na me|ufaznoj prigu{nici, prema
vektorskom dijagramu na slici 3.53. je:
u X = e6 e5 = e6 + e2 = e1 . (3.260)
m
Dakle napon na me|ufaznoj prigu{nici (um) se sastoji od delova faznih napona sekundara i njegov osnovni harmonik
ima tri puta ve}u u~estanost od u~estanosti mreè (slika 3.54.b). Sa slike 3.54.a se vidi da je talasni oblik napona na
optere}enju isti kao kod trofaznog pu{-pul ispravlja~a samo {to je amplituda napona na optere}enju:
U d max = 2 E sin
FG IJ ,
H 3K (3.261)
6 Ispravlja~i
Id
2
Id
2
Sl. 3.53. Sprega dva ispravlja~a sa me|ufaznom prigu{nicom.
e6 e1 e2 e3 e4 e5 e6 e1 e2
Ud
a)
u65 u21 u43 u65 t
um
i
b)
t
Id
2 i i1 i3 i5 i1
5
c)
t
Id
2 i6 i2 i4 i6 i2
d)
t
Id
iR 2
e)
t
Sl. 3.54. Talasni oblici napona i struja za spregu dva ispravlja~a sa me|ufaz-nom prigu{nicom.
pa je, prema (3.240) srednja vrednost napona na optere}enju:
Ud =
3 2E
sin
FG IJ
cos =
3 6E
bg
cos . bg
3 H K 2
(3.262)
Kako dve sekundarne zvezde rade paralelno, svaka daje polovinu jednosmerne struje. Impulsi struja pojedinih
faza prikazani su na slici 3.54.c i 3.54.d, a na slici 3.54.d je prikazan talasni oblik struje u primarnoj fazi "R". Fluks
prinudnog magne}enja ne postoji zato {to se magnetopobudne sile prinudnog magne}enja, koje bi stvarale svaka
zvezda posebno, me|usobno poni{tavaju jer su zvezde sekundara u opoziciji.
Snaga dimenzionisanja me|ufazne prigu{nice
Me|ufazna prigu{nica predstavlja, u stvari, delitelj napona i kroz nju proti~e struja megne}enja i koja je
posledica razlike napona pojedinih zvezdi{ta sekundara transformatora um (slika 3.54.b). Na slici 3.55.a je prikazana
ekvivalentna {ema ispravlja~a za period kada zajedno provode tiristori T1 i T2. Napon na me|ufaznoj prigu{nici je tada:
um = e2 e1 = e2 + e4 = e3 . (3.263)
Pod dejstvom ovog napona se razvija struja magne}enja i a struje pojedinih tiristora odnosno struje polunamotaja
me|ufazne prigu{nice su:
Id
iT 1 = i Xm = i , (3.264)
2 2
Id
iT 2 = i Xm = + i . (3.265)
1 2
Struja tiristora moè te}i samo u smeru od anode ka katodi pa stoga mora biti ispunjen uslov:
Id
0 iT 1b 2g I d i max I d 2 i max . (3.266)
2
Pri manjim strujama optere}enja dva tiristora mogu zajedno provoditi samo dok struja magne}enja me|ufazne
prigu{nice ne dostigne polovinu struje optere}enja. U tom trenutku struja tiristora T1 postaje jednaka nuli dok sva struja
optere}enja te~e kroz tiristor T2. Od tog trenutka do kraja teku}e {estine periode napon na me|ufaznoj prigu{-nici je
jednak nuli jer je:
i Xm = 0 ; i Xm = I d , (3.267)
2 1
zbog ~ega tiristor T1 postaje inverzno polarisan naponom uT1i = e2 e1 = e3 pa se gasi a ispravlja~ nastavlja da radi
kao trofazni pu{-pul ispravlja~.
Id Id
2 2
Id Id
2 2
a) b)
Sl. 3.55. Konstrukcija me|ufazne prigu{nice.
Na slici 3.56. su prikazani talasni oblici napona i struja ispravlja~a za slu~aj Id = Idkr = 2imax i
Id = Idkr/2 = imax. Smanjivanjem struje od Idkr do nule srednja vrednost napona na optere}enju raste od vrednosti:
8 Ispravlja~i
Idkr
Id = Idkr Id =
2
e1 e2 e3 e4 e1 e2 e3 e4
ud ud
t t
uXm1 uXm1
t t
Id Id
iXm2 iXm2
Id t t
iXm1 Id iXm1
t t
Sl. 3.56. Rad ispravlja~a za mele struje optere}enja.
Ud =
3 6E
2
cos bg (3.268)
do vrednosti:
Ud =
3 2E

cos , bg (3.269)
{to prestavlja pove}anje srednje vrednosti napona na optere}enju od:

F 3 2 E cos bg I
G
U d = G
J F 2 1IJ 100 b%g = 15.5 % .
1J 100 b %g = G
GH 3 26E cos bg JK H 3 K (3.270)
Dimenzionisanje me|ufazne prigu{nice se moè izvr{iti tako {to }e se ona posmatrati kao transformator na ~ijim
namotajima je napon jednak polovini osnovnog harmonika razlike napona izme|u dva zvezdi{ta a efektivna vrednost
struje svakog namotaja jednaka polovini jednosmerne struje optere}enja. Efektivna vrednost osnovnog harmonika
napona na jednom polunamotaju me|ufazne prigu{nice je:

U1m =
1 4 2 2E
z x FG IJ b g
sin x dx =
3 3
2 2
sin
0
3 H K
8
E, (3.271)
odakle sledi da je snaga na koju treba dimenzionisati prigu{nicu:
Id 3 3
S = U1m = EI . (3.272)
2 16 d
Maksimalna snaga optere}enja je:
3 6
P0 = EI d , (3.273)
2
pa je:
3 3
S 1
= 16 = = 0.088 . (3.274)
P0 3 6 8 2
2
Sa trostruko ve}om u~estano{}u koli~ina potrebnog bakra u trannsformatoru smanjuje se tri puta ili sav aktivni
materijal 1.5 puta {to zna~i da prava tipska snaga (za pore|enje sa transformatorom) iznosi:
S 0.088
= = 0.059 . (3.275)
P0 15
.
S obzirom da napon na krajevima me|ufazne prigu{nice i struja kroz istu sadrè i vi{e harmonike uzima se da tipska
snaga me|ufazne prigu{nice prakti~no iznosi 7% nominalne snage optere}enja. Induktivnost me|ufazne prigu{nice se
bira tako da njena struja magne}enja bude neprekidna do 1% nominalne struje optere}enja. Ako sa Sm ozna~imo
povr{inu poluperiode napona na na prigu{nici (um) onda je:
S Sm Sm
i = m Lm = . (3.276)
Lm i 0.01 I dn
Me|ufazna prigu{nica se, zbog potrebne simetrije, izvodi prema {emi prikazanoj na slici 3.55.b.
Magnetopobudne sile koje poti~u od jednosmerne struje se poni{tavaju a magnetopobudne sile koje poti~u od struje
magne}enja (i) deluju saglasno.
Snaga dimenzionisanja transformatora
Struja kroz sekundarne namotaje transformatora sastoji se od impulsa amplitude Id/2 u trajanju 2/3 pa je njena
efektivna vrednost:
1 I
I = d, (3.277)
3 2
dok je, prema slici 3.54. efektivna vrednost struje primarnih namotaja:
2 1 Id 1 Id
I = = . (3.278)
3 m 2 m 6
Tipska snaga transformatora je:

3
h FGH IJ + 3
1
2
c
S = S + S =
1
2
3E
1 Id
m 6
+ 6 E
1 Id
3 2
=
K
2
2
E I d , (3.279)
odnosno s obzirom na (3.273):

3
S + 3 2
= 2 = 1.26 . (3.280)
P0 2 3 6
Zbog dobrog iskori{}enja transformatora i malog komutacionog pada napona (svaki ispravlja~ komutuje polovinu
struje optere}enja) ova sprega se vrlo ~esto koristi za niskonaponske primene ve}e snage.
SNAGA POTROAA NAIZMENINE STRUJE
U sluaju vremenski promenljivih struja, snaga generatora i snaga prijemnika mogu biti pozitivne i
negativne. Isto vai i za rad. Ako je snaga prijemnika negativna, on se ponaa kao generator. Kada je
snaga generatora negativna, energija se iz mree dovodi generatoru.
Pored trenutne snage, u kolu naizmenine struje definiu se: srednja ili aktivna snaga, reaktivna
snaga i prividna snaga.
Neka su trenutne vrednosti struje i napona prijemnika impedanse Z dati sa
i (t ) = I m sin t
u (t ) = U m sin(t + )
Trenutna snaga koju prima prijemnik jednaka je:

p (t ) = u (t ) i (t ) = U m I m sin t sin(t + )
smenom
U m = 2U
I m = 2I
dobija se:
p (t ) = 2 UI sin(t ) sin(t + )
Uvodei trigonometrijsku transformaciju:
1
sin sin = [cos( ) cos( + )]
2
sledi:
p (t ) = u (t ) i (t ) = UI cos UI cos(2t + )
odnosno, razlikuju se konstantna i naizmenina komponenta (dvostruke uestanosti) trenutne vrednosti
snage potroaa.
Kao to se vidi sa vremenskog dijagrama snage, kod vremenski promenjivih struja i napona,
elektrini element u delu periode prima energiju od izvora, a u delu perioda vraa energiju izvoru. Sa slike
se vidi da elektrini element u nekim intervalima vremena radi kao potroa, a drugim vremenskim
intervalima kao generator.
U intervalima vremena u kojima su u i i istog znaka, trenutna snaga prijemnika je p > 0 (energija
pristupa prijemniku i u njemu se jednim delom pretvara u toplotu i druge vrste energije, a drugim delom se
nalazi u magnetnom i elektrinom polju prijemnika).
U intervalima vremena u kojima su u i i suprotnog znaka, trenutna snaga prijemnika je p < 0
(energija prelazi od prijemnika ostatku kola - npr. generatoru, u prijemniku se obavljaju nepovratni
procesi).
1
Aktivna (srednja) snaga definie se kao:
T T
1 1 1
P=
T p(t )dt = UI cos t
T 2
sin( 2t + )
0
0
1 1 4 1 4
P= UI cos T sin( T + ) + sin( 0 + )
T 2 T 2 T
1 1 1
P = UI cos T cos + cos
T 2 2
P = U I cos
Jedinica za aktivnu snagu je vat [W].
Za | | /2 aktivna snaga prijemnika je pozitivna i vea je to je manji ugao , tj. to je vei cos.
Sada se moe zakljuiti da trenutna vrednost snage osciluje sa srednjom vrednou UI cos i
amplitudom UI .
Reaktivna snaga predstavlja maksimalnu snagu povratnih procesa.
Q = U I sin
Reaktivna snaga je pozitivna u sluaju preteno induktivnog prijemnika ( > 0), a negativna u
sluaju preteno kapacitivnog prijemnika ( < 0).
Jedinica za reaktivnu snagu je volt amper reaktivni ili var [VAr] ili [var].
Deo energije koji se vraa izvoru je reaktivna energija. Srednja vrednost reaktivne energije je nula.
Reaktivna energija predstavlja nepovoljnu pojavu u kolima naizmenine struje. Prenos reaktivne
energije u oba smera predstavlja rasipanje energije.
Faktor snage predstavlja meru energetskog kvaliteta nekog elementa (cos). Distributeri elektrine
energije uslovljavaju snabdevanje visokom vrednou faktora snage.
Postupak poveanja faktora snage naziva se kompenzacija. Najpoznatiji potroai reaktivne
energije su elektromotori i transformatori. Sa druge strane, postoje i ureaji koji koriste reaktivnu energiju
suprotnog smera, koji ponitavaju (kompenzuju) reaktivnu energiju. Najpoznatiji ureaji takvih osobina su
kondenzatorske baterije koje se postavljaju na mestu potroaa, tako da se potroai snabdevaju
potrebnom reaktivnom energijom za rad npr. motora, ali se ona i kompenzuje kondenzatorom, te reaktivna
energija ne ide dalje od potroaa, odnosno ne prolazi kroz brojilo elektrine energije.
2
Prividna snaga prijemnika definie se kao proizvod efektivne vrednosti napona i struje prijemnika i
obeleava se sa S:
S =U I
Jedinica za prividnu snagu je volt amper [VA].
Prividna snaga jednaka je maksimalnoj snazi prijemnika (za maksimalni faktor snage cos =1) i ima
veliki znaaj.
Prividna snaga se obino daje kao karakteristika aparata i oznaava na njihovim ploicama.
Trougao snage. Slino trouglu impedanse mogue je nacrtati i trougao snage:
Iz trougla snage mogu se izvesti sledei izrazi: P = S cos

Q = S sin
S = P2 + Q2
Faktor snage cos sada se moe definisati kolinikom aktivne i prividne snage prijemnika:
P
cos =
S
Izrazi za aktivnu i reaktivnu snagu prijemnika mogu se predstaviti u vie oblika:

P = U I cos
P = Z I 2 cos
P = RI2
Q = U I sin
Q = Z I 2 sin
Q = X I2
S =U I
S =Z I2
3
1. Izmeu krajeva prijemnika je uspostavljen prostoperiodini napon efektivne vrednosti U = 220 V.
Struja prijemnika je prostoperiodina efektivne vrednosti I = 22 A i fazno zaostaje za naponom za /6,
pri emu su referentni smerovi za napon i struju usaglaeni. Odrediti snage prijemnika i faktor snage
prijemnika.

Aktivna snaga: P = 220 20 cos 3.8kW .
6
Prividna snaga: S = 220 20 4.4kVA .

Reaktivna snaga: Q = 220 20 sin 2.2kVAr .
6
Kako je: Q >0 preteno induktivni prijemnik.
3
Faktor snage: cos = cos = = 0.865
6 2
P 3.8 10 3
Faktor snage mogue je odrediti i iz odnosa: cos = = = 0.865
S 4.4 10 3
2. Dva prijemnika su vezana na red i ukljuena u kolo naizmenine struje. Pod ovim okolnostima su
prividne snage prijemnika S1 = 4 kVA i S2 = 5 kVA. Napon izmeu krajeva prvog prijemnika fazno
prednjai struji prijemnika za 5/12, a struja fazno prednjai naponu izmeu krajeva drugog prijemnika
za /3. Odrediti prividnu snagu redne veze ovih prijemnika.
Aktivna i reaktivna otpornost redne veze prijemnika su:

R = R1 + R2 i X = X1 + X 2 .
Mnoenjem ovih jednaina kvadratom efektivne vrednosti struje prijemnika, za aktivnu i reaktivnu
snagu redne veze prijemnika dobija se:
P = P1 + P2 Q = Q1 + Q2
Prividna snaga redne veze prijemnika je:
S = P2 + Q2
S = ( P1 + P2 ) 2 + (Q1 + Q2 ) 2
S = P12 + 2 P1 P2 + P2 2 + Q12 + 2Q1Q2 + Q2 2
S = ( P12 + Q12 ) + ( P2 2 + Q2 2 ) + 2 P1 P2 + 2Q1Q2
S = S1 2 + S 2 2 + 2 S1 cos 1 S 2 cos 2 + 2S1 sin 1 S 2 sin 2
S = S12 + S 2 2 + 2S1 S 2 (cos 1 cos 2 + sin 1 sin 2 )
S = S1 2 + S 2 2 + 2S1 S 2 cos(1 2 )
1 = 5 / 12
2 = / 3 S = 3.57kVA
4
3. Redna veza otpornika otpornosti R i kondenzatora kapacitivnosti C je prikljuena na strujni generator
prostoperiodine struje ig = 20 sin(500t + / 3) [A] . Izraz za trenutnu snagu koju prima ova redna
veza je: p = 0.6 cos(1000t + / 4) [ W ] . Odrediti otpornost R i kapacitivnost C.
Neka su izrazi za trenutne vrednosti prostoperiodine struje i i prostoperiodinog napona u:

i = I m sin( t + 1 )
u = U m sin(t + 2 )
Trenutna vrednost snage odreuje se kao:

p = u i = U m I m sin(t + 1 ) sin(t + 2 )
1
p =UmIm [cos(1 2 ) cos(2t + 1 + 2 )]
2
p = U I [cos( ) cos(2t + 21 + 2 1 )]
p = U I {cos cos[2(t + 1 ) + ]}
p = S cos S cos[2(t + 1 ) + ]
p = P S cos[2(t + 1 ) + ]
Poreenjem dobijenog izraza sa izrazom za trenutnu snagu, koji je dat u zadatku, dobija se:
P = 0.6W
S = 1VA
Kako je: P = R Ig2
P P 2P 2 0 .6
R= = = =
Ig 2
Im

2
Im 2
(20 10 )
3 2
2
R = 3k
(RI )
2 2
2 2 1 1
Iz izraza za prividnu snagu sledi: S = P2 + Q2 = g + Ig2 = Ig2 R2 +
C C
1
C=
S2
R2
Ig4
Im 20 10 3
Ig = = A C = 0.6F
2 2
= 500s 1
5
4. Za kolo naizmenine struje prikazano na slici poznato je U = 220 V, I = 1 A, U2 = 220 V. Aktivna i
reaktivna otpornost prvog prijemnika su R1 = 20 i X1 = 20 . Odrediti:
a) faktor snage drugog prijemnika,
b) faktor snage celog kola.
U 220
a) Z = = = 220 impedansa celog kola
I 1
U 220
Z2 = 2 = = 220 impedansa drugog prijemnika
I 1
Z 1 = R1 2 + X 1 2 = 50 impedansa prvog prijemnika
X1
tg 1 = = 0.75 1 = 36.8 fazna razlika napona i struje prvog prijemnika
R1
Z = R 2 + X 2 = ( R1 + R2 ) 2 + ( X 1 + X 2 ) 2
Z = Z12 + Z 2 2 + 2 Z1 Z 2 cos(1 2 )
Z 2 Z12 Z 2 2
cos(1 2 ) = = 0.1136
2Z1 Z 2
Jednaina ima dva reenja: (1 2 ) = 96.52
(1 2 ) = 263.48
Odakle se dobija: 2 60
2 226.68
Kako se fazna razlika napona i struje moe nalaziti samo u granicama /2, da bi aktivna snaga
prijemnika bila pozitivna ( P = UI cos > 0 ), odnosno da prijemnik ne bi radio kao generator,
fazni ugao 2 mora zadovoljiti uslov:

2 2 = 60 cos 2 = 0.5
2 2
R R1 + R2 R1 + Z 2 cos 2
b) cos = = = = 0.687
Z Z Z
6
5. Otpornik otpornosti R = 200 , kalem induktivnosti L = 2 mH i kondenzator kapacitivnosti C = 100 nF
vezani su paralelno, a izmeu njihovih krajeva je uspostavljen prostoperiodini napon efektivne
vrednosti U = 8 V, krune uestanosti = 105 s1 i poetne faze U = /4 prema usvojenom poetnom
trenutku i referentnom smeru. Odrediti struju kojom se napaja ova paralelna veza.
R = 200
X L = L = 10 5 2 10 3 = 200
1 1
XC = = 5 = 100
C 10 100 10 9
U
Efektivne vrednosti struja kroz pojedine prijemnike su: IR = = 40mA
R
U
IL = = 40mA
XL
U
IC = = 80mA .
XC
Ekvivalentna struja se odreuje kao: I = I x 2 + I y 2
Sa fazorskog dijagrama se moe videti da je: I x = I R = 40mA

I y = I C I L = 40mA
I = 40 2mA = 56mA
IL IC
Takoe, sa fazorskog dijagrama se oitava da je: tg = = 1 =
IR 4
Fazni ugao se definie kao razlika poetnih faza napona i struje, odnosno:
= U I

= I I = 0
4 4
7
6. Paralelna veza, prikazana na slici, prikljuena je na napon U = 100 V. Odrediti struje pojedinih
paralelnih grana i ukupnu struju kola, ako je: Z1 = 25.67 , 1 = 8 1032 i Z2 = 61.46 , 2 = 85020.
U
I1 = = 3 .9 A
Z1
U
I2 = = 1.63A
Z2
Sa vektroskog dijagrama struja i napona u kolu sledi:
I x = I 1 cos 1 + I 2 cos 2 = 3.9 cos(8132) + 1.63 cos(8520) = 0.70A
I y = I 1 sin 1 + I 2 sin 2 = 3.9 sin( 8132) + 1.63 sin( 8520) = 5.48A
I = I x 2 + I y 2 = 5.52A
Iy
= arctg = 8243
Ix
8
7. Otpornik otpornosti R vezan je paralelno jednom elementu nepoznatih karakteristika. Ova paralelna
veza je prikljuena na prostoperiodini napon intenziteta: u = 120 sin(4000t / 6) [V ] . Intenzitet
struje grane napajanja je: i = 6 sin(4000t + / 6) [A] , pri emu su referentni smerovi za struju i napon
usaglaeni. Odrediti otpornost R i parametre nepoznatog elementa.

u = 120 sin 4000t [V]
6

i = 6 sin 4000t + [ A]
6

Fazna razlika napona i struje napajanja paralelne veze je: = U I = =
6 6 3
Obzirom da fazna razlika napona i struje ima negativnu vrednost, celo kolo je kapacitivnog karaktera,
odnosno nepoznati element je kondenzator.
Fazorski dijagram struja i napona paralelne veze otpornika i kondenzatora dat je na slici:
Iz izraza za trenutne vrednost struje i napona imamo:
Im 6
I= = = 4.24A
2 2
Um 120
U= = = 84.85V
2 2
Sa fazorskog dijagrama sada sledi:
6 6 1
I R = I cos = cos 60 =
= 2.12A
2 2 2
U
R= = 40
IR
6 6 3
I C = I sin = sin 60 = = 3.67 A
2 2 2
U
XC = = 23.12
IC
1 1 1
XC = C= = = 10.82F .
C X C 4000 23.12
9
8. Dva prijemnika su vezana paralelno i prikljuena na prostoperiodini napon. Pod ovim okolnostima su:
aktivna snaga prvog prijemnika P1 = 100 W, efektivna vrednost struje drugog prijemnika I2 = 1 A,
faktor snage drugog prijemnika cos2 = 0.8, efektivna vrednost struje napojne grane I = 1.5 A i faktor
snage paralelne veze prijemnika cos = 0.9. Drugi prijemnik, a i paralelna veza oba prijemnika su, pod
datim okolnostima, preteno induktivni. Odrediti:
a) efektivnu vrednost struje prvog prijemnika,
b) faktor snage prvog prijemnika,
c) efektivnu vrednost prikljuenog napona.
a) P = P1 + P2
Q = Q1 + Q2
UI cos = UI1 cos 1 + UI 2 cos 2 (1)

UI sin = UI1 sin 1 + UI 2 sin 2 (2)
I1 cos 1 = I cos I 2 cos 2

I1 sin 1 = I sin I 2 sin 2
I12 cos 2 1 = I 2 cos 2 2 II 2 cos cos 2 + I 2 2 cos 2 2

I12 cos 2 1 = I 2 sin 2 2 II 2 sin sin 2 + I 2 2 sin 2 2
I12 = I 2 + I 2 2 2 II 2 (cos cos 2 + sin sin 2 )
I1 = I 2 + I 2 2 2 II 2 (cos cos 2 sin sin 2 )
I1 = I 2 + I 2 2 2 II 2 cos( 2 )
cos 2 = 0.8 2 = 36.87

cos = 0.9 = 25.84
I 1 = 0.553A
I cos I 2 cos 2 1.5 0.9 1 0.8 0.55
b) Iz jednaine (1) dobija se : cos 1 = = = 1
I1 0.553 0.553
P1 100
c) P1 = UI1 cos 1 U= = = 181.81V
I 1 cos 1 0.55
0.553
0.553
10
9. Dva prijemnika su vezana paralelno i prikljuena na strujni generator prostoperiodine struje. Prvi
prijemnik je preteno induktivan, a drugi preteno kapacitivan. Faktor snage prvog prijemnika je
cos 1 = 0.8, a faktor snage drugog prijemnika je cos 2 = 0.9. Efektivna vrednost struje prvog
prijemnika je tri puta manja od efektivne vrednosti struje drugog prijemnika.
a) Odrediti faktor snage celog kola.
b) Ispitati da li je kolo preteno kapacitivno ili preteno induktivno.
S obzirom na karakter dva praralelno vezana prijemnika moe se nacrtati vektorski dijagram:
cos 1 = 0.8 (ind ) 1 = 36.87

cos 2 = 0.9 (cap) 2 = 25.84
I2
I1 =
3
I = Ix2 + I y2
I x = I1 cos 1 + I 2 cos 2
I y = I1 sin 1 + I 2 sin 2
U raunu su uzete apsolutne vrednosti uglova, odnosno samo njihove brojne vrednosti bez obzira na
znak.
I 2 = Ix2 + Iy2
I 2 = I12 cos 2 1 + I 2 2 cos 2 2 + 2 I1 I 2 cos 1 cos 2 + I12 sin 2 1 + I 2 2 sin 2 2 2 I 1 I 2 sin 1 sin 2
I 2 = I12 + I 2 2 + 2 I1 I 2 cos(1 + 2 )
I = I 1 2 + (3I 1 ) 2 + 2 I 1 3I 1 cos(36.87 + 25.84)
I = 10 I 1 2 + 6 I 1 2 cos 62.71
I = I 1 10 + 6 cos 62.71
I = 3.57 I 1
I x I 1 cos 1 + I 2 cos 2 I 1 cos 1 + 3I 1 cos 2 0.8 + 3 0.9
cos = = = = = 0.98
I I I 3.57
Pod datim okolnostima, kolo je preteno kapacitivno.
11
10. Za kolo prikazano na slici poznate su: efektivna vrednost prikljuenog prostoperiodinog napona
U = 50 V, kao i efektivne vrednosti struje svih grana I = 1 A, I1 = 1 A i I2 = 1 A. Odrediti aktivnu i
reaktivnu snagu celoga kola.
Vektorski dijagram struja dva paralelno vezana prijemnika moe se predstaviti na sledei nain:
I = I x2 + I y2
Prvi prijemnik je isto kapacitivnog karaktera, te struja I1 fazno prednjai u odnosnu na napon za ugao
1 = 90 (kao to se to vidi sa slike), odnosno bie:
I x = I 2 cos 2
I y = I1 I 2 sin 2
I = I 2 cos 2 2 + I12 2 I1 I 2 sin 2 + I 2 2 sin 2 2
I = I12 + I 2 2 2 I1 I 2 sin 2
I12 + I 2 2 I 2 1
sin 2 = =
2 I1 I 2 2

2 = = 30
6
P = P1 + P2 = UI 1 cos 1 + UI 2 cos 2 = 25 3W
Q = Q1 + Q2 = UI 1 sin 1 + UI 2 sin 2 = 25VAr
12
TERMIKI PRORAUN HLADNJAKA POLUPROVODNIKIH
ELEMENATA
Da bi se odvela toplota stvorena na poluprovodnikom elementu (tiristor, dioda,
tranzistor i sl.) stvorena u njegovoj strukturi zbog provoenja struje, potrebno je
poluprovodnik montirati na odgovarajue rashladno telo (odgovarajueg toplotnog
otpora).
J - Si
C - Case
H - Heatsink
Amb -
Ambient
J (Junction) Silicijumski deo (spoj) poluprovodnika

C (Case) Kuite poluprovodnikog elementa
H (Heatsink)- Hladnjak na koji se montira kompletan poluprovodniki elemenat (koga
ine J i C)
A (Ambient)- Okolina u koju se preko H odvodi toplota sa poluprovodnika
U razumevanju problema i termikog prorauna koristiemo pojednostavljeni statiki i

dinamiki model toplotne eme poluprovodnikog elementa. Prikaz ovih modela je dat na
slici
Prvi ulazni podatak koji treba da imamo je snaga koja se razvija na poluprovodnikom
elementu T u stacionarnom stanju. Prekidake gubitke emo zenemariti. Snaga disipacije
je jednaka:
PDT = U (TO ) I T _ AVG + rT I T2 _ RMS (1)
Razvijena snaga PT se modelira kao strujni izvor I P i na svim toplotnim otporima ona ne
sme stvoriti razliku temperature u odnosu na temperaturu okoline veu od dozvoljene,
tako da temperatura silicijuma, odnosno spoja J ne pree maksimalnu dozvoljenu
vrednost. U elektrinoj analogiji toplotnih pojava , razlici temperature odgovara razlika
napona. Stoga se moe pisati da je prema statikom modelu, koji je dat na slici, ukupni
toplotni otpor jednak:
T (T TAmb )
R th =
PT
= RthJC + RthCH + RthH = J
PT
(2)
Kao reenje, trai se maksimalni doputeni toplotni otpor hladnjaka RthH(MAX).
TJ TAmb
RthH = ( RthJC + RthCH ) (3)
PT
U proraunu je potrebno odabrati da toplotni otpor hladnjaka bude to manji. Razumna

granica u inenjerskoj praksi je 0.2K/W ili manji!
TJ TAmb
RthH = ( RthJC + RthCH ) RthH (max) = 0.2 K / W (4)
PT
VIER, Beograd
STUDIJSKI PROGRAM: Nove energetske tehnologije
PREDMET: Elektrini pretvarai snage
PREDAVA: Prof.dr eljko Despotovi, dipl.el.in
Monofazni tiristorski regulatori sa induktivnim optereenjem-

KOMPENZACIJA REAKTIVNE ENERGIJE
Sl.1. Fazni regulator sa induktivnim optereenjem
Na Sl.1. je prikazan fazni regulator sa isto induktivnim optereenjem, kao i talasni oblici mrenog
napona na optereenju i struje optereenja. Izraz za struju se dobija iz teorije koja sledi:
Naponska jednaina za induktivni potroa ( = / 2) :

di L
uL = L (1)
dt
Struju i L dobijamo iz jednaine (1) integracijom :
1 t
L /
iL (t ) = u L (t ) dt (2)
Napon mree se menja po sinusnom zakonu u = 2 U sin t , tako da je jednainu (2) mogue napisati
kao :
1 t
L /
i L (t ) = 2 U sin t dt (3)
Uvodei smenu t = x dobijamo da je jednaina (3)
1 x
L
iL = 2 U sin x dx (4)
Reavanjem integrala u jednaini (4) dobijamo da je:
1 x 1 1
iL = 2 U sin x dx = 2 U ( cos x )x = 2 U (cos cos x )
L L L
Odnosno vremenska promena struje optereenja je sada data jednainom :
1
i L (t ) = 2 U (cos cos t ) (5)
L
pri uslovu da je :
2 t (6)
Izraz (5) vai za uglove :
/2 (7)
Na Sl.2. su dati talasni oblici mrenog napona u , napona na optereenju u L , struje optereenja i L i
struje njenog osnovnog harmonika i1 .
Sl.2. Talasni oblik prvog harmonika struje
Amplituda osnovnog harmonika struje i1 se dobija razvojem talasnog oblika struje u Furijeov red:
1 2 4 2U
[cos cos x ] cos xdx
L
A1 = i ( x ) cos xdx = (8)
0
Izraunavanjem integrala u jednaini (8) se dobija da je amplituda osnovnog harmonika struje i1 u
funkciji ugla jednaka :
2 2U sin 2
A1 = 1 + (9)
L 2
Stoga je efektivna vrednost struje osnovnog harmonika data relacijom:
A1 2U sin 2
I1 = = 1 + (10)
2 L 2
Vii harmonici struje ( i3 , i5 , i7 ,.... ), koji su posledica struje optereenja mogu se zanemariti jer su
oslabljeni velikom impedansom prigunice na viim uestanostima. Ako se posmatra osnovni harmonik
struje, uoava se da se fazni tiristorski regulator sa isto induktivnim optereenjem ponaa prema
mrei, kao prigunica promenljive induktivnosti. Promenom faznog ugla u opsegu / 2 ,
induktivnost prigunice se moe podeavati u opsegu od LMIN do beskonane vrednosti, odnosno
LMIN L + , kao to je prikazano na Sl.3.
Sl.3. Tiristorski regulator sa induktivnim optereenjem kao ekvivalent promenljivoj induktivnosti

Iz ovog razloga se ovi fazni regulatori primenjuju u sistemima za kompenzaciju reaktivne snage.
Mogunost postrojenja za distribuciju elektrine energije, da snabdeva prikljuene potroae dovoljnim

koliinama energije zavisi od naina na koji potroai koriste tu energiju. Mera efikasnosti korienja
elektrine energije je faktor snage koji je definisan kao odnos aktivne i prividne snage:
P
= (11)
S
Najvea vrednost faktora snage se ima za omsko optereenje tj. kada je P=UI, odnosno = 1 .
Smanjenje faktora snage se moe dogoditi iz dva razloga:
Kada je struja koja se uzima iz mree fazno pomerena u odnosu na napon, pa je za prenos energije
istom snagom potrebna znatno vea efektivna vrednost struje.
Kada struja optereenja nije prosto periodina. U ovom sluaju u struji osim prvog harmonika koji
vri prenos energije, postoje i vii harmonici ija se uestanost razlikuje od uestanosti mrenog
napona.
Ovi harmonici ne vre prenos energije ve samo utiu na poveanje efektivne vrednosti struje.
Poveanje efektivne vrednosti struje za istu snagu kojom se prenosi energija ima viestruke negativne
efekte:
Poveavanje gubitaka u distributivnoj mrei
Poveanje gubitaka u generatorima za proizvodnju elektrine energije
Na osnovu 2 nepotpuno korienje raspoloive mehanike snage
Kontaktna oprema se mora dimenzionisati na vee struje nego to je to potrebno
U ovom delu se analiziraju mogunosti popravke faktora snage za optereenja koja iz mree uzimaju
prostoperiodinu struju koja je fazno pomerena u odnosu na mreni napon. To su na primer vea
industrijska postrojenja gde struja kasni za mrenim naponom, tako da se potroa prema mrei ponaa
kao otporno-induktivno (R-L) optereenje.
Ako su promene induktivne komponente struje optereenja male, paralelno sa potroaem se moe
prikljuiti baterija kondenzatora odgovarajue fiksne kapacitivnosti, tako da u toku dana, faktor snage
vrlo malo odstupa od maksimalne vrednosti.
Za vee promene induktivne komponente struje baterija kondenzatora se mora podeliti u vie manjih
grupa pa se onda prema potrebi ukljuuje potreban broj grupa kondenzatora. Ukljuenje pojedinih
grupa kondenzatora se moe vriti pomou kontaktora ili poluprovodnikih prekidaa (tiristora, GTO,
IGBT i sl.) Kada se ukljuenje ostvaruje preko tiristora potrebno je ukljuenje vriti kada su napon na
kondenzatoru i mreni napon jednaki, jer bi u suprotnom moglo doi do oteenja tiristora zbog
prevelikih struja ukljuenja.
U sluaju da su dnevne promene induktivne komponente struje velike, paralelno optereenju se moe
prikljuiti fiksna baterija kondenzatora dovoljno velike kapacitivnosti, tako da se potroa zajedno sa
baterijom kondenzatora prema mrei ponaa kao otporno-kapacitivno optereenje. Zatim se paralelno
sa baterijom kondenzatora vezuje induktivno optereen fazni regulator pomou koga se faktor snage
podeava na maksimalnu vrednost. Principska ema ovakvog reenja je data na Sl.4.
Sl.4. Korekcija faktora snage induktivno optereenim trofaznim tiristorskim regulatorom
Jednaina (10) odreuje efektivnu vrednost prvog harmonika struje. Na slian nain se mogu izvesti i
efektivne vrednosti struja viih harmonika. Amplituda k-tog harmonika se izraunava iz osnovne
jednaine:
1 2
Ak =
i( x ) cos kxdx (12)
0
Reavanjem integrala (12) dobija se da je amplituda k-tog harmonika:
4 2U sin k cos k cos k sin

Ak = (13)
L k ( k 2 1)
Na Sl.5 je grafiki prikazan odnos pojedinih harmonika tako to su date njihove efektivne vrednosti. Sa
ove slike se uoava da neeljena harmonijska izoblienja potiu uglavnom od treeg harmonika, koji
ima maksimalnu vrednost za = 120 0 . Za ovu vrednost ugla iz relacije (13) se dobija da je:
4 2U sin 3 cos 3 cos 3 sin

A3 ( ) = (14)
L 3 (32 1)
odnosno:
2 2 2 2
sin 3 cos 3 cos 3 sin
2 4 2U 3 3 3 3
A3 = A3 MAX = A3 ( )= (15)
3 L 2
3 (3 1)
Odnosno krajnji izraz za A3MAX
2U 3 2U
A3 = A3 MAX = = 0.138 (16)
L 4 L
Efektivna vrednost struje treeg harmonika je data relacijom:
A3MAX U 3 U
I3 = = = 0.138 (17)
2 L 4 L
Ostali harmonici imaju zanemarljivo male vrednosti zbog velike impedanse induktivnog optereenja.
Sl.5. Sadraj harmonika u struji kod monofaznog tiristorskog regulatora sa induktivnim optereenjem
Ako se tri monofazna tiristorska regulatora veu u trougao, kao to pokazuje Sl.5., struje treeg
harmonika e se zatvarati unutar trougla i nee se pojavljivati u struju mree, tako da e harmonijska
izoblienja struje trofaznog kompenzatora biti zanemarljivo mala.
Ukupna trofazna reaktivna snaga trofaznog kompenzatora je data relacijom:
6 2 sin 2
Q = 3U f I 1 = 3U l I 1 = U l 1 + za / 2 (18)
L 2
gde je za spregu tiristorskog regulatora u trougao U f = U l tj. efektivne vrednosti faznog i linijskog
napona su jednake i iznose 380V(400V), kao to pokazuje Sl.4.
Umesto faznog regulatora sa antiparalelnom vezom tiristora (Sl.1) za realizaciju kompenzatora se moe
koristiti kao osnovna jedinica monofazni regulator sa dve prigunice kao to prikazuje Sl. 6
Sl.6. Kompenzator sa proirenim opsegom ugla paljenja
U sluaju ove konfiguracije faznog regulatora ugao paljenja tiristora se moe menjati u punom opsegu
tj. 0 . Stoga je ova konfiguracija povoljnija u odnosu na konfiguraciju sa antiparalelnom vezom
tiristora kod koje je opseg regulacije bio u intervalu / 2 .
Efektivna vrednost struje osnovnog harmonika je ista ko i kod faznog regulatora sa antiparalelnom
vezom tiristora:
A1 2U sin 2
I1 = = 1 + ; 0 (19)
2 L 2
jedina razlika je opsegu promene ugla paljenja.
Poreenjem ova dva reenja tiristorskih kompenzatora moe se zakljuiti da su prednosti reenja sa dve
prigunice u proirenom opsegu ugla paljenja tiristora. Za istu efektivnu vrednost osnovnog harmonika
potrebna je dvostruko vea vrednost prigunice, to za posledicu ima dvostruko manja harmonijska
izoblienja struje koja se uzima iz mree. Nedostatak ovog reenja je u nedovoljnoj iskorienosti
prigunica jer se magneenje svake pojedinane prigunice vri samo u jednu stranu, pa se postavlja
opravdano pitanje da li je poboljanje performansi kompenzatora dovoljno opravdano za znatno vei
utroak materijala (gvoa za magnetno kolo i bakra za namotaje).
APPLICATION NOTE
TOPOLOGIES FOR SWITCHED MODE

POWER SUPPLIES
by L. Wuidart
I INTRODUCTION
This paper presents an overview of the most the rectifier, different types of voltage
important DC-DC converter topologies. The converters can be made:
main object is to guide the designer in selecting
the topology with its associated power - Step down Buck regulator
semiconductor devices.
- Step up Boost regulator
The DC-DC converter topologies can be
divided in two major parts, depending on - Step up / Step down Buck - Boost regulator
whether or not they have galvanic isolation
between the input supply and the output II - 1 The Buck converter: Step down
circuitry. voltage regulator
II NON - ISOLATED SWITCHING
REGULATORS The circuit diagram, often referred to as a
chopper circuit, and its principal waveforms
According to the position of the switch and are represented in figure 1:
AN513/0393 1/18
APPLICATION NOTE
Figure 1: The step down Buck regulator
The power device is switched at a * Rectifier: VRRM Vin max

frequency f = 1/T with a conduction duty
cycle, = ton/T. The output voltage can also IF(AV) Iout (1-)
be expressed as: Vout = Vin .
Device selection:
* Power switch: Vcev or VDSS > Vin max
I
Icmax or ID max > Iout +
2
2/18
APPLICATION NOTE
II.2 The Boost converter: Step up voltage regulator
Figure 2 : The step up Boost regulator
ton
=
T
In normal operation, the energy is fed from Device selection:

the inductor to the load, and then stored in the
output capacitor. For this reason, the output * Power switch: Vcev or VDSS > Vout
capacitor is stressed a lot more than in the
Buck converter. Iout I
Icmax or IDmax > +
1- 2
Vin * Rectifier: VRRM > Vout
Vout =
1-
IF(av) > Iout
3/18
APPLICATION NOTE
II - 3 Buck-Boost converter: Step up/Step down voltage regulator

Figure 3 : The step up/step down Buck-Boost regulator
iL

For a duty cycle under 0.5 the conversion * Rectifier:

works in step down mode, for a duty cycle
VRRM > Vinmax + Vout
over 0.5, the converter then operates in the
step up mode.
IF (av) > Iout
Vin.
Vout =
1-
Device selection:
* Power switch :
Vcevmax or VDSS > Vinmax + Vout
Iout I
Icmax or IDmax > +
1- 2
4/18
APPLICATION NOTE
II.4 Summery
STEP DOWN STEP UP STEP UP/DOWN
Vout Vin . Vin/1- [-Vin . ] / [1- ]
RMS low high high

current in Cout
Supplied
input discontinuous continuous discontinuous
current
Gate drive floating grounded floating
III - ISOLATED CONVERTERS: is asymmetrical if the magnetic operating

point of the transformer remains in the same
The isolated converters can be classified quadrant. Any other converter is, of course,
according to their magnetic cycle swing in the called symmetrical.
B-H plot (see figure 4). An isolated converter
Figure 4 : B-H plot of symmetrical converters
5/18
APPLICATION NOTE
III - 1 Asymmetrical converters Vin

Vout =
n 1-
III - 1.1 Off-line flyback regulators
The energy is stored in the primary Lp Off-line flyback regulators are mainly used
inductance of the transformer during the for an output power ranging from 30W up to
time the power switch is on, and transferred 250W. Flyback topology is dedicated to
to the secondary output when the power multiple low cost output SMPS as there is
switch is off. If n = Np / Ns is the turns ratio no filter inductor on the output.
of the transformer we have:
Figure 5 : Isolated single switch flyback
R-C-D SNUBBER NETWORK
*Power switch:
VCEV or VDSS Vinmax + nVout + leakage inductance spike
* Secondary Rectifier:
Vinmax
VRRM Vout +
n
6/18
APPLICATION NOTE
a. Single switch versus double switch In a double switch flyback, the leakage
flyback inductance of the power transformer is
much less critical (see figure 6). The two
In the single switch flyback, an overvoltage demagnetization diodes (D1 and D2) provide
spike is applied across the power switch at a single non dissipative way to systematically
each turn off. The peak value of this clamp the voltage across the switches to the
overvoltage depends upon the switching time, input DC voltage Vin. This energy recovery
the circuit capacitance and the primary to system allows us to work at higher
secondary transformer leakage inductance. switching frequencies and with a better
So, a single switch flyback nearly always efficiency than that of the single switch
requires a snubber circuit limiting this structure. However, the double switch
voltage spike (see figure 5). structure requires driving a high side
switch. This double switch flyback is also
known as asymmetrical half bridge flyback.
Figure 6: Isolated double switch flyback
* Power switch:
VCEV or VDSS Vinmax
* Primary Rectifiers: D3 and D4
VRRM Vinmax
7/18
APPLICATION NOTE
b. Discontinuous versus continuous mode inductance of the transformer is completely

flyback demagnetized or not.
The flyback converter has two operating
modes depending whether the primary
Discontinuous mode
ADVANTAGES DISADVANTAGES
- High peak currents in rectifiers and power

- Zero turn-on losses for the power switch
switches
- Good transient line/load response - Large output ripple: Cout (disc.) 2 Cout (cont.)
- Feedback loop (single pole) easy to

stabilize
- Recovery time rectifier not critical: current
is zero well before reverse voltage is
applied
Figure 7: Discontinuous mode flyback waveforms
2Pout 2Pout
* Power switch: ICpeak * Rectifier: IFpeak
Vinmin max Vout (1- max)
2Pout Pout
IDrms IF(AV)
Vinmin (3max) Vout
8/18
APPLICATION NOTE
Continuous mode
ADVANTAGES DISADVANTAGES
- Peak current of rectifier and switch is half

- Recovery time rectifier losses
the value of discontinuous mode
- Low output ripple: -Feedback loop difficult to stabilize (2 poles

Cout (cont.) 0.5 Cout (disc.) and right half plane zero)
Figure 8: Continuous mode flyback waveforms
9/18
APPLICATION NOTE
* Power switch: in single switches, and up to 1kW in double

switch structures.
2Poutmax
ICpeak Single switch vs. double switch forward
max Vinmin (1+A )
In the single switch forward, the magnetizing
2Pout (1 + A + A2 )
IDrms energy stored in the primary inductance
Vinmin 3max is restored to the input source by
a demagnetization winding N d . Most
commonly, the primary and the
demagnetization windings have the same
* Rectifier: number of turns.
So, at turn-off, the power switch has to
2Pout withstand twice the input voltage during the
IFpeak demagnetization time, and then, once the
Vout (1 - max )(1+A ) input voltage (see figure 9).
The demagnetization and primary windings
Pout have to be tightly coupled to reduce the
IF(AV) voltage spike - more than the theoretical 2 V in
Vout - occuring at turn-off across the power
switch.
Ipeak I
with A =
Ipeak
III - 1.2 Off line forward regulators
The forward converter transfers directly the

energy from the input source to the load
during the on-time of the power switch. During
off-time of the power switch, the energy is
freewheeling through the output inductor
and the rectifier D2, like in a chopper (see
figure 1).
Vin
Vout =
n
A forward regulator can be realized with a

single switch structure or with a double switch
structure, according to the way the energy
stored in the transformer primary inductance
is demagnetized. Forward converters are
commonly used for output power up to 250W
10/18
APPLICATION NOTE
Figure 9: Isolated single switch forward
11/18
APPLICATION NOTE
* Power switch:
Np
VCEV or VDSS Vinmax [1 + ] + leakage inductance spike
Nd
1.2.Pout
Icpeak
Vinmin . max
1.2.Pout
IDrms
Vinmin . max
*Rectifiers:
Ns
VRRM Vinmax . + leakage inductance spike
FORWARD D1: Nd
IF(av) Iout .max
Vinmax . (Vout + VF)

VRRM
FREEWHEELING D2: Vinmin . max
IF(av) Iout
Nd
VRRM 1 + N Vinmax
DEMAGNETIZATION D3: p
Imagnpeak
IF(av) . max
2
12/18
APPLICATION NOTE
In the "double switch forward", also called 1.2.Pout

asymmetrical half bridge forward, the IDrms
magnetizing energy stored in the primary Vinmin . max
inductance is automatically returned to the
bulk capacitor by the two demagnetization * Rectifiers:
diodes D1 and D2.
Vinmax (Vout + VF)
The two power switches and demagnetisation VRRM
diodes have to withstand only once the input FORWARD D1: Vinmin . max
voltage Vin. As for the double switch flyback,
IF(av) Iout .max
the asymmetrical half bridge needs a
floating gate drive for the high side switch.
* Power switch: FREEWHEELING VRRM Vinmax (Vout + VF)

VCEV or VDSS Vinmax D2: IF(av) Iout
Figure 10: Half bridge asymmetrical forward converter
13/18
APPLICATION NOTE
III - 2 Symmetrical converters III - 2.1 Push/Pull converter
This type of converter always uses an even T1 and T2 switches (see figure 11) are
number of switches. It also better exploits alternately turned-on during a time ton. The
the transformers magnetic circuit than in secondary circuit operates at twice the
asymmetrical converters. So, smaller size switching frequency.
and weight can be achieved. A deadtime td between the end of conduction
of one switch and the turn-on time of the
The three most common structures used other one is required in order to avoid
are: simultaneous conduction of the two switches.
Vin
- PUSH/PULL Vout = 2
- HALF BRIDGE with capacitors n
- FULL BRIDGE Moreover, the snubber network in symmetrical
converters must be carefully designed,
since they inter-react with one another.
Figure 11: Push-Pull converter
14/18
APPLICATION NOTE
* Power switch
Pout
IDpeak or ICpeak
Vinmin
VCEV or VDSS 2Vinmax + leakage inductance spike
* Rectifier
(Vout + VF) Vinmax

VRRM + Voltage spike
max.Vinmin
Ioutmax
IF(av)
2
The switches are easy to drive since they are The capacitors in series across the supply fix
both referenced to ground, however they a mid-point so that switches withstand only
must withstand twice the input supply voltage. once the input voltage Vin.
The inherent flux symmetry problems can be However, this topology requires driving a
corrected with a current mode PWM control high side switch. When using bipolar switches,
circuit. transistors storage time should have tight
tolerances to avoid imbalance in operating
flux level.
III - 2.2 Half bridge converter
This topology can be used for an output

power capability up to 500W. As for the
push-pull converter, T1 and T2 switches are
alternately turned on during a time ton.
Vin .
Vout =
n
15/18
APPLICATION NOTE
Figure 12: Half bridge converter
* Power switch: 2Pout

ICpeak or IDpeak
Vinmin
VCEV or VDSS Vinmax
* Rectifier:
(Vout + VF) . Vinmax
VRRM + leakage inductance spike
max.Vinmin
Ioutmax
IF(av)
2
16/18
APPLICATION NOTE
Deadtimes (td an figure 12) between two Sometimes, power transformers are
consecutive switch conduction are absolutely paralleled to provide higher output power.
mandatory to avoid bridge-leg short circuit.
2Vin
III - 2.3 Full bridge converter Vout =
n
Because of the number of components, the
full bridge is for high power applications, Switch pairs T1 and T3, T2 and T4 are
ranging from 500 up to 2000W. alternately driven.
Figure 13: Full bridge converter
17/18
APPLICATION NOTE
* Power switch:
Pout
ICpeak or IDpeak
Vinmin
VCEV or VDSS Vinmax
* Rectifier:
(Vout + VF) Vinmax

VRRM + leakage inductance spike
max.Vinmin
Ioutmax
IF(av)
2
The full bridge provides twice the output state-of-the-art in switching regulator
power of the half bridge circuit with the same technology in order to reduce size and weight
switch ratings. of power packages.
Nevertheless, this topology requires 4 Output voltage and load current always
switches and clamping diodes. depend upon the application. The power
supply designs are often tailored to specific
IV - CONCLUSION applications. No simple procedure exists to
select the right topology.
Many significant technological changes in
power supply design have resulted in lower This paper provides an overview of the
cost per Watt with improved performance. most commonly used topologies and lists
the most important features for each
Today, designers keep going ahead with the topology.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
1999 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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NET VIER 2016/2017, Elektrini Pretvarai Snage - AC/AC pretvarai, profesor: Dr eljko Despotovi, dipl.el.

ENERGETSKI PRETVARAI NAIZMENINOG NAPONA

METODE PRETVARANJA NAIZMENIINOG NAPONA

PRETVARAI NAIZMENINOG NAPONA SA ISTIM OTPORNIM

Na Slici 3. prikazane su upravljake karakteristike pretvaraa naizmeninog napona

PRETVARAI NAIZMENINOG NAPONA SA INDUKTIVNIM

tako da je relativna vrednost napona na optereenju jednaka:

koja se moe koristiti za odreivanje ugla .

Pri preteno induktivnom optereenju pretvaraa znaajno je pitanje i odreivanje kritinog

STEPENASTA METODA PRETVARANJA NAIZMENINOG NAPONA

Slika 7. Pretvara naizmeninog napona sa stepenastim upravljanjem: a)ema, b) i c) vremenski

FAZNO STEPENASTA METODA PRETVARANJA NAIZMENINOG

ili posle pojednostavljenja:

Slika 9. Vremenski dijagrami napona i struja pretvaraa naizmeninog napona sa dvostepenim

IRINSKO IMPULSNA METODA PRETVARANJA NAIZMENINOG

grejai i sl. Ako se ukljuivanje i iskljuivanje potroaa odvija sa regulisanim trajanjem

ostvaruje se regulacija srednje snage na potroau:

gde je PMAX snaga potroaa bez prisustva regulacije (t1=0).

Srednja vrednost U x mora U

Srednja vrednost napona UX

U vui se koristi samo prva vrsta opera (BUCK).

Promenom t on moe se podeavati

kontinualno brzina i vuna sila.

Ukoliko bi postojali samo T1 i D1

Kod vozila za masovni transport snaga motora

Najee se koriste IGBT tranzistori

tf - odreuje komutacionu uestanost

Podstanice vrlo esto nisu receptivne (tj. ne mogu da prime

Rekuperacija Motorni reim

Struja rekuperacije preko gornje diode uveava napon na CF

QK se ukljuuje i rastereuje CF,

do t1 prekida vodi. U t1 prekida se otvara i dolazi do

Da bi zakljuili ta se dogaa moramo posmatrati

u A prekida poinje da se ukljuuje

CCG - parazitna kapacitivnost kolektor-gejt

PKOM t Ako usvojimo tRtF i da se

Mali prekidai imaju mali toplotni kapacitet pa se stoga

Za hlaenje se koriste toplotni ili freonske pumpe.

Freon ugroava ivotnu sredinu, koristi se samo u

Regulacioni blok dijagram tranzistiorskog vunog

Veoma esto poloaj pedale direktno odreuje Ia*.

Predavanja iz VUCE Postoji jo i zatita od pregrevanja.

Komutaciona kola iskljuuju tiristor.

Problem je kada USRmin>UM pol

Pri polasku f [0, f nom ] javljaju se

signalizacija i detekcija voza

Predavanja iz VUCE VF trafo

Frekvencija je stalna (ista) za jednu podsekciju.

U svakim kolima mora da postoji:

2. KOMPONENTE SA IZVODIMA I KOMPONENTE ZA

4.1. OPTE O KONDENZATORIMA 58

5.1. OPTE O KALEMOVIMA 85

6.1. KONSTRUKCIJA I PRORAUN 98

7. OSNOVNE OSOBINE POLUPROVODNIKA 108

7.1. ELEMENTARNI POLUPROVODNICI I POLUPROVODNIKA JEDINJENJA 108

8.1. p-n I n-p SPOJEVI 127

9. BIPOLARNI TRANZISTORI 150

9.1. VRSTE TRANZISTORA 150

10. MOS TRANZISTORI 165

10.1. VRSTE MOS TRANZISTORA 166

11. OSNOVI FOTOELEKTRONSKIH KOMPONENATA 176

11.1. FOTODIODA 177

12. OSNOVI INTEGRISANIH KOLA 188