EXPERIMENT-1

Title of the experiment:

        To Design the layout of N-MOS and study its characteristics.
Objective:

        To construct a N-MOS and to verify the voltage and time curve for output and its VI
characteristics.

Brief Theory:

    N-MOS is n-channel i.e negative channel metal oxide semiconductor field effect transistor, a
type of semiconductor i.e. +ve ly charged at the gate terminal so that transistor are turned
ON/OFF by movement of electrons. Here we consider it’s a Enhancement type MOSFET.

    A slab of p-type material is formed from the silicon base and it is referred to as substrate. The
source and drain terminals are connected through metallic contacts to N-doped region on p-
substrate. There are no channel between drain and source. The SiO 2

Layer is present to isolate the gate metallic platform from the region between the drain and
source.

    A voltage source is connected in between gate and source as well as in between drain and
source. As +ve potential is connected to the gate terminal so concentration of electron near SiO 2

increases with increase in voltage and the holes in p substrate is repealed due to the +ve potential
at gate. So a n-type region is created in between drain and source.

    When gate to source voltage is zero there is no drain current flow. The drain current start when
the gate to source voltage is increased from threshold voltage. Till threshold voltage the drain
current is zero.

    By keeping gate to source voltage constant and increasing drains to source voltage we can
draw the output voltage and current curve. When the drain to source voltage increases to more
+ve than gate to source voltage the channel starts decreasing and comes to pinch off point. So
drain current becomes constant after the pinch off point.

   

APPARATUS REQUIRED

       

1. PC
 2. MICROWIND SOFTWARE 3.0

Procedure      

i. Double click on Microwind icon.   

ii. By default the black board available is p substrate.
iii. Taking N-diffusion from the pallet box diffuse N-type impurity on the substrate to form
the drain & the source terminals.
iv. By taking the polysilicon form the gate of the N-MOS.
v. Apply a clock pulse to the gate and the drain terminal.
vi. Assign a output node to the source to observe the output in comparison to the both the
clock pulses.
vii. Then observe the characteristic curve of N-MOS. And voltage to time graph.

EXPERIMENT-2
Title of the experiment:

        To Design the layout of P-MOS and study its characteristics.
Objective:

        To construct a P-mos and to verify the voltage and time curve for output and its VI
characteristics.

Brief Theory:

    P-MOS is p-channel i.e positive channel metal oxide semiconductor field effect transistor, a
type of semiconductor i.e. -ve ly charged at the gate terminal so that transistor are turned
ON/OFF by movement of holes. Here we consider it as Enhancement type MOSFET.

    A slab of n-type material is formed from the silicon base and it is referred to as substrate. The
source and drain terminals are connected through metallic contacts to highly p-doped region on
n-substrate. There are no channel between drain and source. The SiO 2

Layer is present to isolate the gate metallic platform from the region between the drain and
source.
    A voltage source is connected in between gate and source as well as in between drain and
source. As -ve potential is connected to the gate terminal so concentration of holes near SiO 2

increases with increase in voltage and the electrons in n substrate is repealed due to the -ve
potential at gate. So a n-type region is created in between drain and source.

   
    By keeping gate to source voltage constant and increasing drains to source voltage we can
draw the output voltage and current curve. When the drain to source voltage increases to more
-ve than gate to source voltage the channel starts decreasing and comes to pinch off point. So
drain current becomes constant after the pinch off point.

   

APPARATUS REQUIRED

       

1. PC

2.   MICROWIND SOFTWARE 3.0

Procedure

viii. Double click on Micro wind icon.   

viii. By default the black board available is p substrate.so  form a n-substrate by taking the N-
well from pallete box.

viii. Taking P-diffusion from the pallet box diffuse P-type impurity on the substrate to form
the drain & the source terminals.

viii. By taking the polysilicon form the gate of the P-MOS.

viii. Apply a clock pulse to the gate and the drain terminal.

viii. Assign a output node to the source to observe the output in comparison to the both the
clock pulses.
viii. Then observe the characteristic curve of P-MOS. And voltage to time graph.