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n – WELL PROCESS
Step 1: Si Substrate
p substrate
Step 2: Oxidation
SiO2
p substrate
Photoresist
SiO2
p substrate
Step 4: Masking
Uv rays
n-well mask
P h o to re s is t
S iO 2
p s u b s tra te
P h otore sist
S iO 2
p s ub s tra te
Step 6: Acid Etching
Photoresist
SiO2
p substrate
SiO2
p substrate
Step 8: Formation of n-well
SiO2
n well
n well
p substrate
Polysilicon
Thin gate oxide
n well
p substrate
Polysilicon
Thin gate oxide
n well
p substrate
n well
p substrate
Oxidation
n well
p substrate
Masking
Step 11: N- diffusion
n+ n+ n+
n well
p substrate
Diffusion
n+ n+ n+
n well
p substrate
p+ n+ n+ p+ p+ n+
n well
p substrate
Step 13: Contact cuts
The devices are to be wired together
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
p-well CMOS process
LOGIC GATES
CMOS INVERTER
NAND Gate
NOR Gate
STICK DIAGRAM
Stick Diagram Colour Code
P diffusion Yellow/Brown
N diffusion Green
Polysilicon Red
Contacts Black
Metal1 Blue
Metal2 Magenta/Purple
Metal3 Cyan/L.Blue
PMOS transistor
INVERTER- STICK DIAGRAM
Step 1
Two horizontal wires are used for connection with VSS and
VDD. This is done in metal2, but metal1can be use instead.
Step 2
Two vertical wires (pdiff and ndiff) are used to represent the
p-transistor (yellow) and n-transistor (green).
Step 3
Step 5
NAND Gate
NOR Gate