A1244

Chopper-Stabilized, Two Wire Hall-Effect Latch

Features and Benefits Description

▪ High speed, 4-phase chopper stabilization The A1244 is a two-wire Hall-effect latch. The devices are
▫ Low switchpoint drift throughout temperature range produced on the Allegro™ advanced BiCMOS wafer fabrication
▫ Low sensitivity to thermal and mechanical stresses process, which implements a patented high frequency, 4-phase,
▪ On-chip protection chopper-stabilization technique. This technique achieves
▫ Supply transient protection magnetic stability over the full operating temperature range,
▫ Reverse battery protection and eliminates offsets inherent in devices with a single Hall
▪ On-board voltage regulator element that are exposed to harsh application environments.
▫ 3.0 to 24 V operation
Two-wire latches are particularly advantageous in cost-sensitive
▪ Solid-state reliability
applications because they require one less wire for operation
▪ Robust EMC and ESD performance
versus the more traditional open-collector output switches.
▪ Industry leading ISO 7637-2 performance through use of
Additionally, the system designer inherently gains diagnostics
proprietary, 40-V clamping structures
because there is always output current flowing, which should
Packages: be in either of two narrow ranges. Any current level not within
these ranges indicates a fault condition.
3-pin ultramini SIP 3-pin SOT23-W
1.5 mm × 4 mm × 3 mm 2 mm × 3 mm × 1 mm The Hall-effect latch will be in the high output current state
(suffix UA) (suffix LH) in the presence of a magnetic south polarity field of sufficient
magnitude and will remain in this state until a sufficient north
polarity field is present.
The device is offered in two package styles. The LH is a
SOT-23W style, miniature low profile package for surface-
mount applications. The UA is a 3-pin ultra-mini single inline
package (SIP) for through-hole mounting. Both packages are
lead (Pb) free, with 100% matte tin leadframe plating.

Not to scale Approximate footprint

Functional Block Diagram

V+ VCC

Regulator

To all subcircuits

Clock/Logic

0.01 μF Low-Pass Schmitt

Sample and Hold
Dynamic Offset

Filter Trigger
Cancellation

Amp Polarity

GND GND

UA package only

A1244-DS, Rev. 1
 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

Selection Guide
Operating Ambient Supply Current
Part Number Packing* Package Temperature, TA at ICC(L)
(°C) (mA)
A1244LLHLX-I1-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40 to 150 5 to 6.9
A1244LLHLX-I2-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40 to 150 2 to 5
A1244LUA-I1-T Bulk, 500 pieces/bag 3-pin SIP through hole –40 to 150 5 to 6.9
A1244LUA-I2-T Bulk, 500 pieces/bag 3-pin SIP through hole –40 to 150 2 to 5
*Contact Allegro™ for additional packing options

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 28 V
Reverse Supply Voltage VRCC –18 V
Magnetic Flux Density B Unlimited G
Operating Ambient Temperature TA Range L –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg –65 to 170 ºC

Pin-out Diagrams
Terminal List Table
3
Number
Name Function
LH UA
VCC 1 1 Connects power supply to chip

NC 2 – No connection
NC

1 2 1 2 3 GND 3 2,3 Ground

LH Package UA Package
3-pin SOT23W 3-pin SIP

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

ELECTRICAL CHARACTERISTICS Valid at TA = –40°C to 150°C, TJ < TJ(max), CBYP = 0.01 μF, through operating supply voltage
range; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage1,2 VCC Operating, TJ ≤ 165 °C 3.0 – 24 V
-I1 B < BRP 5 – 6.9 mA
ICC(L)
Supply Current -I2 B < BRP 2 – 5 mA
ICC(H) B > BOP 12 – 17 mA
Supply Zener Clamp Voltage VZ(sup) ICC(L)(max) + 3 mA, TA = 25°C 28 – – V
ICC(L)(max)
Supply Zener Clamp Current IZ(sup) VZ(sup) = 28 V – – mA
+ 3 mA
Reverse Supply Current IRCC VRCC = –18 V – – –1.6 mA
No bypass capacitor, capacitance of probe
Output Slew Rate3 di/dt – 90 – mA / μs
CS = 20 pF
Chopping Frequency fc – 700 – kHz
Power-Up Time2,4,5 ton – – 25 μs
Power-Up State4,6,7 POS ton < ton(max) , VCC slew rate > 25 mV / μs – ICC(H) – –
1V represents the generated voltage between the VCC pin and the GND pin.
CC
2The VCC slew rate must exceed 600 mV/ms from 0 to 3 V. A slower slew rate through this range can affect device performance.
3Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change.
4Power-Up Time is measured without and with bypass capacitor of 0.01 μF, B < B
RP – 10 G. Adding a larger bypass capacitor would cause longer
Power-Up Time.
5Guaranteed by characterization and design.
6Power-Up State as defined is true only with a V
CC slew rate of 25 mV / μs or greater.
7For t > t
on and BRP < B < BOP , Power-Up State is not defined.

MAGNETIC CHARACTERISTICS1 Valid at TA = –40°C to 150°C, TJ < TJ (max); unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit2
Magnetic Operating Point BOP 5 – 80 G
Magnetic Release Point BRP –80 – –5 G
Hysteresis BHYS BOP – BRP 40 – 110 G
1Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north
magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).
2 1 G (gauss) = 0.1 mT (millitesla).

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Application Information
Characteristic Symbol Test Conditions* Value Units
Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
Package Thermal Resistance RθJA 110 ºC/W
connected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W
*Additional thermal information available on Allegro Web site.

Power Derating Curve

25
24 VCC(max)
23
22
21
20
Maximum Allowable VCC (V)

19
18
17
16
15
LH, 2-layer PCB
14 (RQJA = 110 ºC/W)
13
12
11 UA, 1-layer PCB
10 (RQJA = 165 ºC/W)
9
8
7 LH, 1-layer PCB
6 (RQJA = 228 ºC/W)
5
4 VCC(min)
3
2
20 40 60 80 100 120 140 160 180

Temperature (ºC)

Power Dissipation versus Ambient Temperature

1900
1800
1700
1600
1500
1400
Power Dissipation, PD (m W)

1300
1200 2-
l
1100 (R aye
θJ rP
A = C
1000 11 B, P
1-la 0 º ac
900 y C/ ka
(R er PC W
) ge L
800 θJA = B H
165 , Pac
700 ºC/ k a
W) ge U
600 A
500 1-lay
400 er P
(R CB,
300 θJA =
228 Packag
ºC/W e LH
200 )
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

Characteristic Performance

A1244-I1 A1244-I1
Average Supply Current (Low) versus Temperature Average Supply Current (Low) versus Supply Voltage
7.0 7.0

Supply Current, ICC(L) (mA)

Supply Current, ICC(L) (mA)

TA = 150°C
6.5 6.5

VCC = 24 V

6.0 6.0
TA = 25°C TA = –40°C
VCC = 3.0 V

5.5 5.5

5.0 5.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26

Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

A1244-I1,I2 A1244-I1,I2
Average Supply Current (High) versus Temperature Average Supply Current (High) versus Supply Voltage
17 17
Supply Current, ICC(H) (mA)
Supply Current, ICC(H) (mA)

16 16 TA = –40°C
VCC = 24 V
TA = 150°C
15 15
VCC = 3.0 V TA = 25°C

14 14

13 13

12 12
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26

Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

A1244-I1,I2 A1244-I1,I2
Average Operate Point versus Temperature Average Operate Point versus Supply Voltage
85 85

75 75
Operate Point, BOP (G)
Applied Flux Density at

Operate Point, BOP (G)

Applied Flux Density at
65 65

55 55

45 45
VCC = 3.0 V TA = 25°C TA = 150°C
35 35
VCC = 24 V TA = –40°C
25 25

15 15

5 5
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26

Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

A1244-I1,I2 A1244-I1,I2
Average Release Point versus Temperature Average Release Point versus Supply Voltage
–5 –5

–15 –15
Release Point, BRP (G)
Applied Flux Density at

Release Point, BRP (G)

Applied Flux Density at

–25 –25
VCC = 3.0 V TA = –40°C
–35 –35
TA = 25°C
–45 –45
VCC = 24 V TA = 150°C
–55 –55

–65 –65

–75 –75

–85 –85
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26

Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

A1244-I1,I2 A1244-I1,I2
Average Switchpoint Hysteresis versus Temperature Average Switchpoint Hysteresis versus Supply Voltage
110
Switchpoint Hysteresis, BHYS (G)

110
Switchpoint Hysteresis, BHYS (G)

100 100
Applied Flux Density at

Applied Flux Density at

90 90
VCC = 24 V TA = 150°C
80 80
TA = 25°C
VCC = 3.0 V
70 70

TA = –40°C
60 60

50 50

40 40
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26

Ambient Temperature, TA (°C) Supply Voltage, VCC (V)

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

Functional Description

The A1244 output, ICC, switches high after the magnetic field
at the Hall sensor IC exceeds the operate point threshold, BOP .
When the magnetic field is reduced to below the release point
threshold, BRP , the device output goes low. This is shown in
figure 1.
The difference between the magnetic operate and release points
is called the hysteresis of the device, BHYS . This built-in hyster-
esis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.

I+
ICC(H)
Switch to High
Switch to Low
ICC

ICC(L)
0
B– B+
BOP
BRP

BHYS

Figure 1. Hysteresis for the A1244. On the horizontal axis, the B+ direc-
tion indicates increasing south polarity magnetic field strength, and the
B– direction indicates decreasing south polarity field strength (including
the case of increasing north polarity).

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

RSENSE

V+ VCC V+ VCC

CBYP CBYP
A1244 A1244
0.01 μF 0.01 μF

GND GND

ECU
RSENSE

(A) Low side sensing (B) High side sensing

Figure 2. Typical application circuits

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges. Chopper stabilization is
a unique approach used to minimize Hall offset on the chip. The
patented Allegro technique, namely Dynamic Quadrature Offset
Cancellation, removes key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. The chopper stabilization technique uses a 350 kHz
high frequency clock. For demodulation process, a sample and
hold technique is used, where the sampling is performed at twice
the chopper frequency. This high-frequency operation allows
a greater sampling rate, which results in higher accuracy and
faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall out-
put voltages and precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset, low-noise amplifiers
in combination with high-density logic integration and sample-
and-hold circuits.

Regulator

Clock/Logic
Low-Pass
Hall Element Filter
Sample and
Hold

Amp

Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation)

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

Power Derating
The device must be operated below the maximum junction tem- Example: Reliability for VCC at TA = 150°C, package LH, using a
perature of the device, TJ(max). Under certain combinations of low-K PCB.
peak conditions, reliable operation may require derating supplied
Observe the worst-case ratings for the device, specifically:
power or improving the heat dissipation properties of the appli-
RJA = 110 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
cation. This section presents a procedure for correlating factors
ICC(max) = 17 mA.
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.) Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
The Package Thermal Resistance, RJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
heat from the junction (die), through all paths to the ambient air.
This provides the allowable increase to TJ resulting from internal
Its primary component is the Effective Thermal Conductivity, K,
power dissipation. Then, invert equation 2:
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RJC, is relatively PD(max) = Tmax ÷ RJA = 15°C ÷ 110 °C/W = 136 mW
small component of RJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding. Finally, invert equation 1 with respect to voltage:

The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN
 T = PD × RJA
TJ = TA + ΔT
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then:
VCC(est) = PD(max) ÷ ICC(max) = 136 mW ÷ 17 mA = 8 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
(1) Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
(2) able operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est)
(3) and VCC(max) is reliable under these conditions.

PD = VCC × ICC = 12 V × 4 mA = 48 mW

 T = PD × RJA = 48 mW × 140 °C/W = 7°C

TJ = TA + T = 25°C + 7°C = 32°C

A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RJA and TA.

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

Package LH, 3-Pin SOT23W

+0.12
2.98 –0.08

1.49 D
4°±4°
3 A
+0.020
0.180–0.053

0.96 D

+0.10 +0.19 2.40

2.90 –0.20 1.91 –0.06
0.70
D
0.25 MIN

1.00

1 2

0.55 REF 0.25 BSC 0.95

Seating Plane
Gauge Plane B PCB Layout Reference View

8X 10° REF Branded Face

1.00 ±0.13
NNN

+0.10 1
0.05 –0.05
0.95 BSC C Standard Branding Reference View
0.40 ±0.10
N = Last three digits of device part number
For Reference Only; not for tooling use (reference DWG-2840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Active Area Depth, 0.28 mm REF
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion

D Hall element, not to scale

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

Package UA, 3-Pin SIP

+0.08
4.09 –0.05

45°
B

E C
2.04
1.52 ±0.05

10°
E 1.44 Mold Ejector
E
+0.08 Pin Indent
3.02 –0.05

Branded 45°
Face
0.79 REF
A NNN
1.02
MAX

1
1 2 3 D Standard Branding Reference View
= Supplier emblem
N = Last three digits of device part number

14.99 ±0.25 +0.03

0.41 –0.06
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.05
0.43 –0.07
A Dambar removal protrusion (6X)
B Gate and tie bar burr area
C Active Area Depth, 0.50 mm REF
D Branding scale and appearance at supplier discretion
E Hall element (not to scale)

1.27 NOM

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 Chopper-Stabilized, Two Wire
A1244
Hall-Effect Latch

Revision History
Revision Revision Date Description of Revision
Rev. 1 July 12, 2012 Update package drawing

Copyright ©2011-2013, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

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