A 22dB PSRR Enhancement in a

Two-Stage CMOS Opamp Using Tail Compensation

Paul M. Furth, Sri Harsh Pakala, Annajirao Garimella and Chaitanya Mohan
VLSI Laboratory, Klipsch School of Electrical and Computer Engineering,
New Mexico State University, Las Cruces, NM 88003, USA
Email: pfurth@nmsu.edu, sriharsh@nmsu.edu, garimella@ieee.org

Abstract— A new compensation technique known as tail com- nearly zero; hence the main motivation for selecting node VX
pensation is applied to a two-stage CMOS operational amplifier. in the compensation path. From node V1 to node VOU T power
The compensation is established by a capacitor connected be- supply noise is injected through the parasitic capacitance Cgd
tween the output node and the source node of the differential
amplifier. For the selected opamp topology, tail compensation in the tail compensation technique. As such, PSRR begins to
allows better performance in terms of bandwidth and power degrade at moderate rather than low frequencies.
supply rejection ratio (PSRR) when compared to Miller and cas-
&'' &'' &''
code compensation. Operational amplifiers using Miller, cascode
and tail compensation were fabricated in a 0.5-µm 2P3M CMOS $%
process. The circuits operate at a total quiescent current of 90 µA &*+, $%
**
&*+,
&!"# *23
with ±1.5V power supplies. Experimental results show that tail *- .-
&!"# !"
! ##
&(
&!"#
&) &)
compensation increases the unity-gain frequency by 60% and !" !"
! ##
! ##
25% and improves PSRR from the positive rail by 22 dB and &*+,
&$/0
26 dB over a frequency range from 23 kHz to 3.0 MHz compared &)
!$"
! *#
to Miller and cascode compensation, respectively. &1
Index Terms—Tail compensation, Miller compensation, power !"# !$# !%#
supply rejection ratio, two-stage opamps. Fig. 1. Primary VDD signal path created in (a) Miller (b) cascode and (c)
proposed tail compensation schemes.
I. I NTRODUCTION
II. CMOS T WO -S TAGE A MPLIFIER
Power supply rejection ratio (PSRR) often determines the
performance limit of sensitive analog circuitry such as ADCs, The circuit implementation of a two-stage operational am-
PLLs, VCOs and LDOs [1], [2]. Indeed, whenever the supply plifier with Miller, cascode and the proposed tail compensation
voltage is generated by a switched-mode power supply, ripple schemes is shown in Fig. 2. The circuit consists of two
noise is unavoidable. In portable communications devices, stages, a differential pair with single-ended load (M1 -M8 )
which utilize transceiver circuits operating at high frequencies, and a common-source output stage (M12 -M13 ). Generally the
supply ripple may even cause stability degradation at the effective transconductance of a differential amplifier equals the
frequency of transmission [3]. transconductance of differential input transistors M1 , M2 . In
While many existing techniques, such as Miller and cas- this case, the load of the first stage is cascode current source
code compensation [4]–[19], ensure stability of a closed-loop M3 -M4 . The current through M1 is not mirrored to node V1 ;
amplifier, in some circumstances they lead to poor PSRR. hence, the effective transconductance of the first stage reduces
Referring to Fig. 1, let V1 be the output of the first stage to 0.5gm1 = 0.5gm2 .
and VOU T be the output of the second stage of a two stage The current through transistor M1 is utilized to create a
CMOS opamp. Miller compensation is placed between nodes feed-forward path to node VOU T through mirror M5 -M6 and
V1 and VOU T and cascode compensation between nodes VY transistors M9 -M12 . The mirror formed by transistors M11 -
and VOU T , where node VY is the source of the cascoding M12 has a dimension ratio of 1:K, thus giving rise to a
transistor. The gain from VDD to nodes V1 [8] and VY is very feed-forward transconductance of 0.5Kgm1 . In this way, the
nearly unity, as will be demonstrated later. In this way, power current generated through the M1 branch is utilized for two
supply noise is easily induced through the large compensation purposes: (i) enhancing the negative going slew-rate and (ii)
capacitors to the output node, resulting in the degradation of biasing the output stage of the amplifier. The common-source
PSRR at low frequencies. transistor M13 in the second stage is similarly sized K times
To this end, we introduce a new compensation technique the unit-sized PMOS transistor. Bias voltages and currents are
called “tail” compensation which does not create a path from a generated by transistors M14 -M19 and resistors Rb .
node contaminated by VDD noise. In this technique, as shown
in Fig. 1(c), the compensating capacitor CT is connected to A. Op-amp Gain
the low impedance tail current node VX of the amplifier. As Let the output resistance and equivalent capacitance to
will be demonstrated later, the gain from VDD to VX is very ground of the first and second stages be denoted by R1 and

978-1-4673-1556-2/12/$31.00@2012 IEEE
 VDD M19 M9 M6 m=K
M4 M13
VBP VBP
Ib
Ib
VY Cascode
M18 VCP M10 M5 M3 CC
VCN V1 Miller
CM RM VOUT
Rb Rb V IN-­ VIN+
M1 VX M2
Ib Ib
VCN M7 m=2 RL CL
CT
M14 M15 2Ib
VBN Tail
VBN

M16 M17 M11 M8 m=2 M12

m=K
V SS Bias  Circuit  Feed-­forward  Path First  Stage Output  Stage

Fig. 2. Schematic of two-stage operational amplifier illustrating Miller, cascode, and tail compensation techniques.

C1 , and ROU T and COU T , respectively. Also, let the transcon- %- &-
"#$$%&!
'()*%+,-.#(+

ductance, output resistance, gate-to-source, and gate-to-drain "! "123

! ! ", ! ! !
capacitances of an individual transistor Mi be represented by %%
.*/0"!
gmi , roM i , Cgsi and Cgdi , respectively. Referring to Fig. 2, %123
! &! %! !
the gains of the first and second stages are "#$ . *0
'() .*+"#$ . *0 ", '()4 .*/"#$ &123
±
AV 1 = −0.5gm2 R1 , AV 2 = −g m13 ROU T (1)
where R1 = roM 2 ||(gm3 roM 3 roM 4 ) ≈ roM 2 and ROU T = '-,/(0%!
'()*%+,-.#(+
1%%023(&4-&0!5-.6

(roM 12 ||roM 13 ||RL ). The overall gain of the two-stage ampli- "$#
fier, including the feed-forward path is 7-#$!'()*%+,-.#(+
%3
AV = AV 1 AV 2 + 0.5Kgm1 ROU T . (2) "! "
! ! ! ! 123 ! !
! ! % .7/0
B. Tail Compensation .*+ .*+"" 6±" # .*/0"!
#$! 5 %123
The amplifier of Fig. 2 is implemented using all three "#$6 "5 &! %!
4 .*/""#$8±"5# &123
compensation techniques – Miller, cascode, and tail – in order
!
to clearly differentiate the performance of the proposed tail ± .*/
compensation technique. The tail compensation capacitor CT !
1%%023(&4-&0!5-.6
is introduced between node VOU T and node VX , a node with
"%#
a low input resistance of (1/gm1 )||(1/gm2 ). The output of the Fig. 3. Small signal model of opamps in Fig. 2 using (a) Miller and cascode
first stage is isolated from the feedback network by the current compensation and (b) proposed tail compensation.
buffer [12], [13] formed by transistor M2 . Current fed back
through� M2 establishes the� dominant low-frequency pole at capacitor COU T . Zero ωz1 depends only on the compensation
−1 capacitors. The non-dominant poles in Miller and cascode are
ωp1 = R1 ( C2T )gm13 ROU T .
real, whereas those in tail compensation are a complex pole
III. S MALL S IGNAL A NALYSIS pair with a theoretically computed damping factor Q = 0.76.
Small-signal models of the three compensation topologies
IV. P OWER S UPPLY R EJECTION R ATIO A NALYSIS
are shown in Fig. 3. Three LHP poles and two LHP zeros
were derived for each topology. A summary of the equations of The PSRR small signal models of the three different
poles and zeros and their unity-gain frequencies (ωU GF ) along compensation schemes are shown in Fig. 4. The opamp is
with their approximate frequencies for each compensation connected in a unity-gain configuration and an AC signal in
network are given in Table I. These theoretical values are series with the DC power supply voltage is placed at the VDD
computed with values from a SPICE operating point analysis terminal. The ratio VDD /VOU T defines PSRR.
using 0.5-µm transistor models. There are several differences in the PSRR small-signal
As one can observe, the dominant pole ωp1 in each models of Fig. 4 compared to the small-signal models of
configuration-Miller, cascode and tail-is established by com- Fig. 3. Since PSRR is measured in unity-gain configuration,
pensating capacitances CM , CC and CT , respectively. The input VIN + is now at ground and VOU T is connected to
effect of the first non-dominant pole ωp2 is approximately VIN − . Looking at the first stage of Fig. 4, the effect of
nullified through careful placement of the first LHP zero transistor M2 on node V1 is seen in resistance roM 2 and the
ωz1 . The second zero ωz2 is at very high frequencies (f > effect of the unity-gain feedback is through transconductance
150 MHz); hence, it has negligible effect on opamp stability. −0.5g m2 VOU T . Node V1 is also loaded by Cgs13 to VDD . For
The non-dominant poles ωp2 and ωp3 depend on output common-mode voltage signals, in particular VDD , node VX is
 TABLE I
E QUATIONS FOR AC S MALL - SIGNAL MODELS AND THEIR THEORETICALLY COMPUTED LOCATIONS

Pole/Zero Miller (Fig. 3(a)) f (Hz) Cascode (Fig. 3(a)) f (Hz) Tail (Fig. 3(b)) f (Hz)
1 1 1
ωp1 R1 CM gm13 ROU T
5k R1 CC gm13 ROU T
4k R1 (CT /2)gm13 ROU T
4.5k

gm13 CM g�m13 CC
ωp2 C1 CM +COU T (C1 +CM )
3M �C
OU T CC
16M
gm3 R1
+C1 (CC +COU T ) complex pole pair ωp2,3 15M
� � � � �
1 1 1 1 1 1 1 gm1 gm13
ωp3 RM C1
+ CM
+ COU T
170M R1 C 1
+gm3 CC
+ COU T
66M C1 Cgd13 +Cgd13 COU T +C1 COU T

1 gm3 gm2
ωz1 RM C M
8M CC
14M CT
10.4M

gm13 gm13 gm13

ωz2 KC1
250M KC1
250M C1
156M
�
gm2 gm13 gm2 gm2
ωU GF 2COU T CM
6.2M 2CC
8.3M CT
10.4M

TABLE II
E QUATIONS FOR THE LOCATION OF PSRR DOMINANT POLES

Pole Miller (Fig. 4(a)) f (Hz) Cascode (Fig. 4(a)) f (Hz) Tail (Fig. 4(b)) f (Hz)
ωp1,P SRR (roM 2 CM gm13 roM 13 )−1 1.5k (roM 2 CC gm13 roM 13 )−1 1.2k (roM 2 Cgd13 gm13 roM 13 )−1 23k

open, since it is loaded by cascode current source M7 -M8 (see As mentioned earlier, the reason for degraded PSRR perfor-
Fig. 2). Therefore, whatever current enters node VX through mance in Miller and cascode compensation techniques is that
transistor M1 must circulate back through transistor M2 onto noise from VDD appears unattenuated at nodes V1 and VY .
node V1 . The current entering node VX through transistor M1 , Small-signal analysis of the PSRR models in Fig. 4 yield the
VDD /roM 1 , appears at node V1 as a dependent current source, following gain equations from VDD to nodes V1 , VY , and VX .
as shown in Fig. 4. A final difference between the two models V1 1 VY
≈ 1+ ≈ 1, ≈1
in the first stage is that the impedance of the cascode buffer VDD gm13 roM 13 VDD
1/gm3 in Fig. 4(a) is now attached to VDD . VX 1
≈ (3)
Differences in the second stage of the PSRR small-signal VDD gm2 roM 13 (K + roM 2 gm13 )
model are that transconductance gm13 in parallel with re- Using small-signal parameters, the gain VX /VDD ≈ 2.5 ×
sistance roM 13 now go to VDD , rather than ground. ROU �
T 10−4 , which is close to 0.
is the equivalent resistance to ground at node VOU T , where The PSRR at low frequencies, P SRRDC , is the same for
ROU T = ROU �
T ||roM 13 . All other differences in the second Miller, cascode and tail compensation, and is given by
stage are due to measuring PSRR in unity-gain configuration,
wherein VIN + is tied to ground and VOU T to VIN − . P SRRDC = 0.5gm2 roM 2 gm13 roM 13 . (4)
!"#$%&'(!%)*'+#",-%+
The dominant pole determines the shape of the PSRR
( /* !2 (/#*"!"".!# # $%&#* frequency response, which is a single-pole system for fre-
!"" !"" '()#* $
$%&#
(/* quencies below the unity-gain frequency fU GF . A summary
!# !2 '' !+,- of the dominant pole equations are shown in Table II. In
Miller and cascode compensation, the dominant poles are
'& 1&
created by capacitors CM and CC , with theoretically computed
.(/0 !+,-
$%&0 '(4#* '+,- values of 1.5 kHz and 1.2 kHz, respectively. However, in
3( /#!+,- 5¶+,- tail compensation the dominant pole is caused by the small
! !
.-//'0(!%)*'+#",-%+
parasitic capacitance Cgd13 of transistor M13 and not the large
compensation capacitor CT . This leads to the dominant pole
"%#
1"-/(!%)*'+#",-%+ occurring at the moderate frequency of 23 kHz, leading to a
' (4#* higher PSRR for moderate-to-high frequencies.
!"" (/#* "!
"" .!# #
!"" '()#* V. E XPERIMENTAL R ESULTS AND C ONCLUSIONS
$ $%&#*
$%&# $
!# (/# '- !+,- The three designs were implemented in a 0.5-µm 2P3M
!5 CMOS process. A chip micrograph is shown Fig. 5. Measure-
$%&0 $ ments were performed using power supplies ±1.5V and a total
.(6/0!5 ( /0 bias current of 90 µA. The output load consisted of a 40 kΩ
$ 3(/# "!+,- .!5# 5¶+,- '+,- resistor in parallel with a 20 pF capacitor. Simulated open-
loop gain for all three schemes was 69 dB. To achieve a phase
margin of 63o , the required compensation capacitors-CM , CC
"&#
and CT -were 1.25 pF, 1.55 pF and 2.75 pF, respectively.
Fig. 4. PSRR Small signal model of opamps in Fig. 2 showing (a) Miller
and cascode compensation and (b) proposed tail compensation.
Measured transient waveforms of the amplifiers in an inverting supply noise sensitive analog applications, tail compensation
configuration with a gain of −1V /V are shown in Fig. 6. may prove beneficial, due to its increased fU GF and enhanced
While the Miller and cascode compensated designs achieved PSRR performance.
a measured fU GF of 6.4 MHz and 8.2 MHz, respectively, TABLE III
fU GF for the tail compensated design was 10.3 MHz, an S UMMARY OF M EASURED R ESULTS
improvement of 60% over Miller and 25% over cascode. Parameter/Design Miller Cascode Tail
UGF (MHz) 6.4 8.2 10.3
SR+/SR- (V/µs) (10%-90%) 6.3/2.9 5.8/3.0 3.4/5.1

(a)
PSRR @ 100 kHz (dB) 44 40 66
PSRR @ 3 MHz (dB) 14 8 36
Circuit area (µm x µm) 177 x 74 181 x 74 200 x 74

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50
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