Professional Documents
Culture Documents
Compal La-3631p R1a Schematics
Compal La-3631p R1a Schematics
1 1
IALAA
2
Minnesota 10A/10AG 2
4 4
PAGE 8,9
Turion 64 RTC Battery PAGE 22
PAGE 28 PAGE 36
LPC
33MHz (3.3V) BATT CONN/OTP
PAGE 37
1 1
CPU_CORE
PAGE 42
SIGNAL
Voltage Rails STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
DDR DIMM0 A4
DDR DIMM1 A6
4
Mini Card-WLAN 4
Mini Card-3G
New Card
H_CADIP[0..15] H_CADOP[0..15]
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
D D
H_CADIN[0..15] H_CADON[0..15]
<10> H_CADIN[0..15] H_CADON[0..15] <10>
+1.2V_HT
JP27A
D4 VLDT_A3 VLDT_B3 AE5 1 2
VLDT=500mA D3 AE4 C107 4.7U_0805_10V4Z
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP11
H_CADIN11
H_CADIP10
H3
H4
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
AB5
AA5
H_CADOP11
H_CADON11
H_CADOP10
+1.2V_HT
250 mil
VLDT CAP.
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP9 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H_CADIN9 F4 AC5 H_CADON9 1 1 1 1 1 1
C H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8 C102 C103 C101 C104 C106 C112 C
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
L0_CADIN_L8 L0_CADOUT_L8
HTT Inter face
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7 2 2 2 2 2 2
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L2
L0_CADIN_H5
L0_CADIN_L5
L0_CADOUT_H5
L0_CADOUT_L5 U1 H_CADON5 Near CPU Socket
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S1g1 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 4 of 45
5 4 3 2 1
A B C D E
2
DDR_B_D60 AE14 AB14 DDR_A_D60
R91 DDR_B_D59 MB_DATA60 MA_DATA60 DDR_A_D59
Y11 MB_DATA59 MA_DATA59 W11
1K_0402_1% DDR_B_D58 AB11 Y12 DDR_A_D58
+CPU_M_VREF DDR_B_D57 MB_DATA58 MA_DATA58 DDR_A_D57
4 AC12 MB_DATA57 MA_DATA57 AD13 4
DDR_B_D56 AF13 AB13 DDR_A_D56
1
1000P_0402_25V8J
0.1U_0402_16V4Z
DDR_B_D54 AF16 AB15 DDR_A_D54
MB_DATA54 MA_DATA54
2
C156
R90 DDR_B_D52 AF19 Y17 DDR_A_D52
1K_0402_1% DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51
AD14 MB_DATA51 MA_DATA51 Y14
DDR_B_D50 AC14 W14 DDR_A_D50
2 2 DDR_B_D49 MB_DATA50 MA_DATA50 DDR_A_D49
AE18 W16
1
DDRII Cmd/Ctrl//Clk
VTT9 C150 DDR_B_D33 MB_DATA34 MA_DATA34 DDR_A_D33
AA23 MB_DATA33 MA_DATA33 AB24
DDR_CS3_DIMMA# V19 Y16 DDR_A_CLK2 1.5P_0402_50V9C DDR_B_D32 AA24 Y24 DDR_A_D32
<8> DDR_CS3_DIMMA# MA0_CS_L3 MA0_CLK_H2 DDR_A_CLK2 <8> 2 MB_DATA32 MA_DATA32
DDR_CS2_DIMMA# J22 AA16 DDR_A_CLK#2 DDR_A_CLK#1 DDR_B_D31 G24 H22 DDR_A_D31
<8> DDR_CS2_DIMMA# MA0_CS_L2 MA0_CLK_L2 DDR_A_CLK#2 <8> MB_DATA31 MA_DATA31
DDR_CS1_DIMMA# V22 E16 DDR_A_CLK1 DDR_B_D30 G23 H20 DDR_A_D30
<8> DDR_CS1_DIMMA# MA0_CS_L1 MA0_CLK_H1 DDR_A_CLK1 <8> MB_DATA30 MA_DATA30
DDR_CS0_DIMMA# T19 F16 DDR_A_CLK#1 DDR_B_D29 D26 E22 DDR_A_D29
<8> DDR_CS0_DIMMA# MA0_CS_L0 MA0_CLK_L1 DDR_A_CLK#1 <8> MB_DATA29 MA_DATA29
3 DDR_B_CLK2 DDR_B_D28 C26 E21 DDR_A_D28 3
DDR_CS3_DIMMB# Y26 DDR_B_CLK2 DDR_B_D27 MB_DATA28 MA_DATA28 DDR_A_D27
<9> DDR_CS3_DIMMB# MB0_CS_L3 MB0_CLK_H2 AF18 DDR_B_CLK2 <9> 1 G26 MB_DATA27 MA_DATA27 J19
DDR_CS2_DIMMB# J24 AF17 DDR_B_CLK#2 DDR_B_D26 G25 H24 DDR_A_D26
<9> DDR_CS2_DIMMB# MB0_CS_L2 MB0_CLK_L2 DDR_B_CLK#2 <9> MB_DATA26 MA_DATA26
DDR_CS1_DIMMB# W24 A17 DDR_B_CLK1 C149 DDR_B_D25 E24 F22 DDR_A_D25
D DRII Data
<9> DDR_CS1_DIMMB# MB0_CS_L1 MB0_CLK_H1 DDR_B_CLK1 <9> 1.5P_0402_50V9C MB_DATA25 MA_DATA25
DDR_CS0_DIMMB# U23 A18 DDR_B_CLK#1 DDR_B_D24 E23 F20 DDR_A_D24
<9> DDR_CS0_DIMMB# MB0_CS_L0 MB0_CLK_L1 DDR_B_CLK#1 <9> 2 MB_DATA24 MA_DATA24
DDR_B_CLK#2 DDR_B_D23 C24 C23 DDR_A_D23
DDR_CKE1_DIMMB DDR_B_ODT1 DDR_B_D22 MB_DATA23 MA_DATA23 DDR_A_D22
<9> DDR_CKE1_DIMMB H26 MB_CKE1 MB0_ODT1 W23 DDR_B_ODT1 <9> B24 MB_DATA22 MA_DATA22 B22
DDR_CKE0_DIMMB J23 W26 DDR_B_ODT0 DDR_B_CLK1 DDR_B_D21 C20 F18 DDR_A_D21
<9> DDR_CKE0_DIMMB MB_CKE0 MB0_ODT0 DDR_B_ODT0 <9> MB_DATA21 MA_DATA21
DDR_CKE1_DIMMA J20 V20 DDR_A_ODT1 1 DDR_B_D20 B20 E18 DDR_A_D20
<8> DDR_CKE1_DIMMA MA_CKE1 MA0_ODT1 DDR_A_ODT1 <8> MB_DATA20 MA_DATA20
DDR_CKE0_DIMMA J21 U19 DDR_A_ODT0 DDR_B_D19 C25 E20 DDR_A_D19
<8> DDR_CKE0_DIMMA MA_CKE0 MA0_ODT0 DDR_A_ODT0 <8> MB_DATA19 MA_DATA19
C568 DDR_B_D18 D24 D22 DDR_A_D18
<8> DDR_A_MA[15..0] DDR_B_MA[15..0] <9> 1.5P_0402_50V9C MB_DATA18 MA_DATA18
DDR_A_MA15 K19 J25 DDR_B_MA15 DDR_B_D17 A21 C19 DDR_A_D17
DDR_A_MA14 MA_ADD15 MB_ADD15 DDR_B_MA14 DDR_B_CLK#1 2 DDR_B_D16 MB_DATA17 MA_DATA17 DDR_A_D16
K20 MA_ADD14 MB_ADD14 J26 D20 MB_DATA16 MA_DATA16 G18
DDR_A_MA13 V24 W25 DDR_B_MA13 DDR_B_D15 D18 G17 DDR_A_D15
DDR_A_MA12 MA_ADD13 MB_ADD13 DDR_B_MA12 DDR_B_D14 MB_DATA15 MA_DATA15 DDR_A_D14
K24 MA_ADD12 MB_ADD12 L23 C18 MB_DATA14 MA_DATA14 C17
DDR_A_MA11 L20 L25 DDR_B_MA11 DDR_B_D13 D14 F14 DDR_A_D13
DDR_A_MA10 MA_ADD11 MB_ADD11 DDR_B_MA10 DDR_B_D12 MB_DATA13 MA_DATA13 DDR_A_D12
R19 MA_ADD10 MB_ADD10 U25 C14 MB_DATA12 MA_DATA12 E14
DDR_A_MA9 L19 L24 DDR_B_MA9 DDR_B_D11 A20 H17 DDR_A_D11
DDR_A_MA8 MA_ADD9 MB_ADD9 DDR_B_MA8 DDR_B_D10 MB_DATA11 MA_DATA11 DDR_A_D10
L22 MA_ADD8 MB_ADD8 M26 A19 MB_DATA10 MA_DATA10 E17
DDR_A_MA7 L21 L26 DDR_B_MA7 DDR_B_D9 A16 E15 DDR_A_D9
DDR_A_MA6 MA_ADD7 MB_ADD7 DDR_B_MA6 DDR_B_D8 MB_DATA9 MA_DATA9 DDR_A_D8
M19 MA_ADD6 MB_ADD6 N23 A15 MB_DATA8 MA_DATA8 H15
DDR_A_MA5 M20 N24 DDR_B_MA5 DDR_B_D7 A13 E13 DDR_A_D7
DDR_A_MA4 MA_ADD5 MB_ADD5 DDR_B_MA4 DDR_B_D6 MB_DATA7 MA_DATA7 DDR_A_D6
M24 MA_ADD4 MB_ADD4 N25 D12 MB_DATA6 MA_DATA6 C13
DDR_A_MA3 M22 N26 DDR_B_MA3 DDR_B_D5 E11 H12 DDR_A_D5
DDR_A_MA2 MA_ADD3 MB_ADD3 DDR_B_MA2 DDR_B_D4 MB_DATA5 MA_DATA5 DDR_A_D4
N22 MA_ADD2 MB_ADD2 P24 G11 MB_DATA4 MA_DATA4 H11
DDR_A_MA1 N21 P26 DDR_B_MA1 DDR_B_D3 B14 G14 DDR_A_D3
DDR_A_MA0 MA_ADD1 MB_ADD1 DDR_B_MA0 DDR_B_D2 MB_DATA3 MA_DATA3 DDR_A_D2
R21 MA_ADD0 MB_ADD0 T24 A14 MB_DATA2 MA_DATA2 H14
DDR_B_D1 A11 F12 DDR_A_D1
DDR_A_BS#2 MB_DATA1 MA_DATA1
<8> DDR_A_BS#2 K22 MA_BANK2 MB_BANK2 K26 DDR_B_BS#2 DDR_B_BS#2 <9>
DDR_B_D0 C11 MB_DATA0 MA_DATA0 G12 DDR_A_D0
2 DDR_A_BS#1 2
<8> DDR_A_BS#1 R20 MA_BANK1 MB_BANK1 T26 DDR_B_BS#1 DDR_B_BS#1 <9> <9> DDR_B_DM[7..0] DDR_A_DM[7..0] <8>
DDR_A_BS#0 T22 U26 DDR_B_BS#0 DDR_B_DM7 AD12 Y13 DDR_A_DM7
<8> DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 <9> MB_DM7 MA_DM7
DDR_B_DM6 AC16 AB16 DDR_A_DM6
DDR_A_RAS# MB_DM6 MA_DM6
<8> DDR_A_RAS# T20 MA_RAS_L MB_RAS_L U24 DDR_B_RAS# DDR_B_RAS# <9>
DDR_B_DM5 AE22 MB_DM5 MA_DM5 Y19 DDR_A_DM5
DDR_A_CAS# U20 V26 DDR_B_CAS# DDR_B_DM4 AB26 AC24 DDR_A_DM4
<8> DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# <9> MB_DM4 MA_DM4
DDR_A_WE# U21 U22 DDR_B_WE# DDR_B_DM3 E25 F24 DDR_A_DM3
<8> DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# <9> MB_DM3 MA_DM3
DDR_B_DM2 A22 E19 DDR_A_DM2
FOX_PZ63823-284S-41F DDR_B_DM1 MB_DM2 MA_DM2 DDR_A_DM1
B16 MB_DM1 MA_DM1 C15
Athlon 64 S1 DDR_B_DM0 A12 E12 DDR_A_DM0
Processor MB_DM0 MA_DM0
Socket DDR_B_DQS7 AF12 W12 DDR_A_DQS7
<9> DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 <8>
DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
<9> DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 <8>
DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
<9> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <8>
DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
<9> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <8>
DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
<9> DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 <8>
DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
<9> DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 <8>
DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
<9> DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 <8>
DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
<9> DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 <8>
DDR_B_DQS3 F26 G22 DDR_A_DQS3
<9> DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 <8>
DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
<9> DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 <8>
DDR_B_DQS2 A24 C22 DDR_A_DQS2
<9> DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 <8>
DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
<9> DDR_B_DQS#2 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS#2 <8>
DDR_B_DQS1 D16 G16 DDR_A_DQS1
<9> DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 <8>
DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
<9> DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 <8>
DDR_B_DQS0 C12 G13 DDR_A_DQS0
<9> DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 <8>
DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
<9> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <8>
FOX_PZ63823-284S-41F
1 1
Athlon 64 S1
Processor Socket
2
2 2 2 2
B
1 R35
2 MAINPWON <36,37,39>
1
JP27D Q10 0_0402_5%
E
R87 F8 AF6 CPU_THERMTRIP#_R 3 1 1 R36
2
VDDA2 THERMTRIP_L H_THERMTRIP# <16>
C
680_0402_5% F9 AC7 CPU_PROCHOT#_1.8 0_0402_5%
VDDA1 PROCHOT_L MMBT3904_SOT23-3
D @ D
LDT_RST# B7
2
H_PW RGD RESET_L
A:PA_IXP600AD12 A7 PWROK
LDT_STOP# F10 LDTSTOP_L
VID5 A5 VID5 <42>
LDT_STOP# 2 1 CPU_SIC AF4 C6
<11,16> LDT_STOP# SIC VID4 VID4 <42>
R332 300_0402_5% AF5 A6
SID VID3 VID3 <42>
2
VID2 A4 VID2 <42>
R89 R53 1 2 44.2_0402_1% CPU_HTREF1 P6 C5 +3V_SB
+1.2V_HT HTREF1 VID1 VID1 <42>
680_0402_5% R54 1 2 44.2_0402_1% CPU_HTREF0 R6 B5 MP:Reserve pull up resistor
HTREF0 VID0 VID0 <42>
R490 for H_PROCHOT#
R53&R54 place them to CPU within 1" AC6 CPU_PRESENT# +1.8V 2 1
1
2
B
R43 300_0402_5% R490 @
W9 Q11
<40> VDDIOFB_H VDDIO_FB_H PSI# <42>
E
LDT_RST# TP1 Y9 CPU_PROCHOT#_1 .8 3 11 2 R42
<16> LDT_RST# VDDIO_FB_L H_PROCHOT# <16>
C
0_0402_5%
2
1
680_0402_5%
CPU _DBRDY G10 E10 CPU_DBREQ#
R333 DBRDY DBREQ_L
1
2
CPU_TRST# TCK TDO
<13> CPUCLK0_L 1 2 AD9 TRST_L
C545 3900P_0402_50V7K CPU_TDI AF9 R88
TDI 80.6_0402_1%
CPU_TEST25_H_BYPASSCLK_H E9 C9 CPU_TEST29_H_FBCLKOUT_P 1 2
C CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST29_H CPU_TEST29_L_FBCLKOUT_N C
E8 TEST25_L TEST29_L C8
CPU_TEST19_PLLTEST0 G9
+1.8V CPU_TEST18_PLLTEST1 TEST19
H10 ROUTE AS 80 Ohm DIFFERENTIAL PAIR
MISC
TEST18
AA7 TEST13 PLACE IT CLOSE TO CPU WITHIN 1"
2 1 CPU_TEST25_H_BYPASSCLK_H C2
R86 510_0402_5% TP4 TEST9 TP8
D7 TEST17 TEST24 AE7
TP5 E7 AD7 TP9 +1.8V
CPU_TEST25_L_BYPASSCLK_L TP6 TEST16 TEST23 TP10
2 1 F7 TEST15 TEST22 AE8
R48 510_0402_5% TP3 C7 AB8 CPU_TEST21_SCANEN
CPU_TEST19_PLLTEST0 TP11 TEST14 TEST21 TP7 VID1
2 1 AC8 TEST12 TEST20 AF7 1 2
R49 300_0402_5% R47 300_0402_5%
2 1 CPU_TEST18_PLLTEST1 C3 J7 CPU_PRESENT# 1 2
R50 300_0402_5% TEST7 TEST28_H R56 1K_0402_5%
AA6 TEST6 TEST28_L H8
THERMDC_CPU W7 AF8 CPU_TEST26_BURNIN# 1 2
THERMDA_CPU THERMDC TEST27 CPU_TEST26_BURNIN# R57 300_0402_5%
W8 THERMDA TEST26 AE6
Y6 TEST3 TEST10 K8
AB6 TEST2 TEST8 C4
CPU_TEST21_SCANEN 1 2
P20 H16 R55 300_0402_5%
Thermal Sensor P19
RSVD0
RSVD1
RSVD8
RSVD9 B18
N20
GMT G781P8F B: Change to GMT G781P8F from DVT. N19
RSVD2
RSVD3 RSVD10 B3
RSVD11 C1
+3VS H6
RSVD12
1 RSVD13 G6
C111 U6 D5
THERMDA_CPU 2 RSVD14
DXP+ VCC 1
2200P_0402_50V7K R24
B 2 THERMDC_CPU 3 RSVD15 B
DXN- ALERT# 6 1 RSVD16 W18
R26 RSVD4 RSVD17 R23
8 4 C105 R25 AA8
<15,30> EC_SMB_CK2 SCLK THERM# RSVD5 RSVD18
0.1U_0402_16V4Z P22 H18
2 RSVD6 RSVD19
<15,30> EC_SMB_DA2 7 SDATA GND 5 R22 RSVD7 RSVD20 H19
@ 220_0402_5% R77
@ 220_0402_5% R76
@ 220_0402_5% R75
@ 220_0402_5% R74
@ 220_0402_5% R73
HDT Connector
1
1
JP9
1 2
2
2
3 4
CPU_DBREQ# 5 6
CPU_DBRDY 7 8
CPU_TCK 9 10
CPU_TMS 11 12 +3VS
CPU_TDI 13 14
CPU_TRST# 15 16
14
CPU_TDO 17 18 U20D
19 20
12 LDT_RST#
P
21 22 HDT_RST# 11 A
23 24 O
26 B 13 SB_PWRGD <16,30>
G
A NOTE: HDT TERMINATION IS REQUIRED A
SN74LVC08APW_TSSOP14
FOR REV. Ax SILICON ONLY.
7
@ SAMTEC_ASP-68200-07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S1g1 CTRL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 16, 2007 Sheet 6 of 45
5 4 3 2 1
5 4 3 2 1
JP27F
AA4 VSS1 VSS66 J6
+CPU_CORE +CPU_CORE AA11 J8
JP27E VSS2 VSS67
AA13 J10
VDD(+CPU_CORE) decoupling. AC4
AD2
VDD1
VDD2
VDD43
VDD44
V12
V14
AA15
AA17
VSS3
VSS4
VSS5
VSS68
VSS69
VSS70
J12
J14
G4 VDD3 VDD45 W4 AA19 VSS6 VSS71 J16
H2 VDD4 VDD46 Y2 AB2 VSS7 VSS72 J18
+CPU_CORE J9 J15 AB7 K2
VDD5 VDD47 VSS8 VSS73
J11 VDD6 VDD48 K16 AB9 VSS9 VSS74 K7
J13 VDD7 VDD49 L15 AB23 VSS10 VSS75 K9
K6 VDD8 VDD50 M16 AB25 VSS11 VSS76 K11
1 1 1 1 K10 VDD9 VDD51 P16 AC11 VSS12 VSS77 K13
D 45level K12 T16 AC13 K15 D
+ C544 + C576 + C560 + C602 VDD10 VDD52 VSS13 VSS78
K14 VDD11 VDD53 U15 AC15 VSS14 VSS79 K17
45@ 820U_E9_2_5V_M_R7 45@ 820U_E9_2_5V_M_R7 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M L4 V16 AC17 L6
VDD12 VDD54 +1.8V VSS15 VSS80
L7 VDD13 AC19 VSS16 VSS81 L8
2 2 2 2
L9 VDD14 AC21 VSS17 VSS82 L10
L11 VDD15 VDDIO1 H25 AD6 VSS18 VSS83 L12
L13 J17 AD8 L14
Near CPU Socket M2
VDD16
VDD17
VDDIO2
VDDIO3 K18 AD25
VSS19
VSS20
VSS84
VSS85 L16
M6 VDD18 VDDIO4 K21 AE11 VSS21 VSS86 L18
M8 K23 AE13 M7
Power
+CPU_CORE VDD19 VDDIO5 VSS22 VSS87
M10 VDD20 VDDIO6 K25 AE15 VSS23 VSS88 M9
N7 VDD21 VDDIO7 L17 AE17 VSS24 VSS89 M11
N9 VDD22 VDDIO8 M18 AE19 VSS25 VSS90 M17
N11 VDD23 VDDIO9 M21 AE21 VSS26 VSS91 N4
1 1 1 1 1 1 1 1 1 P8 VDD24 VDDIO10 M23 AE23 VSS27 VSS92 N8
C123 C146 C125 C144 C122 C124 C145 C126 C142 P10 M25 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VDD25 VDDIO11 VSS28 VSS93
R4 VDD26 VDDIO12 N17 B6 VSS29 VSS94 N16
R7 P18 B8 N18
Ground
2 2 2 2 2 2 2 2 2 VDD27 VDDIO13 VSS30 VSS95
R9 VDD28 VDDIO14 P21 B9 VSS31 VSS96 P2
R11 VDD29 VDDIO15 P23 B11 VSS32 VSS97 P7
T2 VDD30 VDDIO16 P25 B13 VSS33 VSS98 P9
+CPU_CORE +CPU_CORE +CPU_CORE T6 R17 B15 P11
VDD31 VDDIO17 VSS34 VSS99
T8 VDD32 VDDIO18 T18 B17 VSS35 VSS100 P17
T10 VDD33 VDDIO19 T21 B19 VSS36 VSS101 R8
T12 VDD34 VDDIO20 T23 B21 VSS37 VSS102 R10
1 1 1 1 T14 VDD35 VDDIO21 T25 B23 VSS38 VSS103 R16
C143 C138 C129 C136 U7 U17 B25 R18
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDD36 VDDIO22 VSS39 VSS104
U9 VDD37 VDDIO23 V18 D6 VSS40 VSS105 T7
U11 VDD38 VDDIO24 V21 D8 VSS41 VSS106 T9
C 2 2 2 2 C
U13 V23 D9 T11
Under CPU Socket V6
VDD39
VDD40
VDDIO25
VDDIO26 V25 D11
VSS42
VSS43
VSS107
VSS108 T13
V8 VDD41 VDDIO27 Y25 D13 VSS44 VSS109 T15
V10 VDD42 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
FOX_PZ63823-284S-41F D21 VSS48 VSS113 U8
D23 U10
VDDIO decoupling. Athlon 64 S1
Processor Socket
D25
E4
VSS49
VSS50
VSS51
VSS114
VSS115
VSS116
U12
U14
F2 VSS52 VSS117 U16
F11 VSS53 VSS118 U18
F13 VSS54 VSS119 V2
+1.8V F15 V7
+1.8V VSS55 VSS120
F17 VSS56 VSS121 V9
F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
1 1 1 1 F23 VSS59 VSS124 V15
C153 C152 C155 C154 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.22U_0603_16V4Z VSS60 VSS125
H7 VSS61 VSS126 W6
H9 VSS62 VSS127 Y21
2 2 2 2
H21 VSS63 VSS128 Y23
H23 VSS64 VSS129 N6
J4 VSS65
+0.9V FOX_PZ63823-284S-41F
Under CPU Socket Near Power Supply
B
VTT decoupling. 1
C: Change to NBO CAP
+ C577
Athlon 64 S1
Processor Socket
B
220U_Y_4VM
2
Between CPU Socket and DIMM
+1.8V
+0.9V
1 1 1 1
C163 C177 C164 C172
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z
2 2 2 2 1 1 1 1 1 1 1 1
C556 C555 C548 C549 C559 C554 C552 C550
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
1 1 1 1 1 1
Near CPU Socket Right side.
C159 C160 C157 C158 C165 C176 +0.9V
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 1 1 1 1 1 1 1 1
to follow AMD Layout C140 C137 C133 C134 C130 C127 C147 C128
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
+1.8V review recommand for
EMI 2 2 2 2 2 2 2 2
A A
1
C: Change to NBO CAP
1 1 1 1
+ C652 Near CPU Socket Left side.
C183 C182 C162 C161 220U_Y_4VM
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2 2 2 2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S1g1 PWR & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 7 of 45
5 4 3 2 1
5 4 3 2 1
2
0.1U_0402_16V4Z
RP3
1000P_0402_25V8J
41 42 1 1 R148 DDR_A_MA12 8 1 1 2
VSS VSS
C249
DDR_A_D16 43 44 DDR_A_D20 1K_0402_1% DDR_A_MA9 7 2 C196 0.1U_0402_16V4Z
DQ16 DQ20
C243
DDR_A_D17 45 46 DDR_A_D21 DDR_A_MA8 6 3 1 2
DQ17 DQ21 DDR_A_MA5 C244 0.1U_0402_16V4Z
47 48 5 4
1
DDR_A_DQS#2 VSS VSS 2 2
49 DQS2# NC 50
DDR_A_DQS2 51 52 DDR_A_DM2 47_0804_8P4R_5%
DQS2 DM2 RP21
53 VSS VSS 54
2
DDR_A_D18 55 56 DDR_A_D22 DDR_A_MA3 8 1 1 2
DDR_A_D19 DQ18 DQ22 DDR_A_D23 R132 DDR_A_MA1 C254 0.1U_0402_16V4Z
57 DQ19 DQ23 58 7 2
59 60 1K_0402_1% DDR_A_MA10 6 3 1 2
DDR_A_D24 VSS VSS DDR_A_D28 DDR_A_BS#0 C199 0.1U_0402_16V4Z
61 DQ24 DQ28 62 5 4
DDR_A_D25 63 64 DDR_A_D29
1
DQ25 DQ29
65 VSS VSS 66 C: RP20 swap for DDR Shielding\. 47_0804_8P4R_5%
DDR_A_DM3 67 68 DDR_A_DQS#3 RP20
DM3 DQS3# DDR_A_DQS3 DDR_A_CAS#
69 NC DQS3 70 8 1 1 2
71 72 DDR_A_WE# 7 2 C232 0.1U_0402_16V4Z
DDR_A_D26 VSS VSS DDR_A_D30 DDR_CS1_DIMMA#
73 DQ26 DQ30 74 6 3 1 2
DDR_A_D27 75 76 DDR_A_D31 DDR_A_ODT1 5 4 C213 0.1U_0402_16V4Z
DQ27 DQ31
77 VSS VSS 78
C DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA 47_0804_8P4R_5% C
<5> DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA <5>
81 82 RP5
DDR_CS2_DIMMA# VDD VDD DDR_A_MA15 DDR_CS3_DIMMA#
<5> DDR_CS2_DIMMA# 83 NC NC/A15 84 8 1 1 2
DDR_A_BS#2 85 86 DDR_A_MA14 DDR_A_ODT0 7 2 C185 0.1U_0402_16V4Z
<5> DDR_A_BS#2 BA2 NC/A14
87 88 DDR_A_MA13 6 3 1 2
DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_RAS# C218 0.1U_0402_16V4Z
89 A12 A11 90 5 4
DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6 47_0804_8P4R_5%
93 A8 A6 94
95 96 RP8
DDR_A_MA5 VDD VDD DDR_A_MA4 DDR_A_MA14
97 A5 A4 98 8 1 1 2
DDR_A_MA3 99 100 DDR_A_MA2 DDR_A_MA15 7 2 C293 0.1U_0402_16V4Z
DDR_A_MA1 A3 A2 DDR_A_MA0 DDR_CKE1_DIMMA
101 A1 A0 102 6 3 1 2
103 104 5 4 C258 0.1U_0402_16V4Z
DDR_A_MA10 VDD VDD DDR_A_BS#1
105 A10/AP BA1 106 DDR_A_BS#1 <5>
DDR_A_BS#0 107 108 DDR_A_RAS# 47_0804_8P4R_5%
<5> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <5>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
<5> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <5>
111 VDD VDD 112
DDR_A_CAS# 113 114 DDR_A_ODT0
<5> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <5>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<5> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
DDR_A_ODT1 119 120 DDR_CS3_DIMMA#
<5> DDR_A_ODT1 NC/ODT1 NC DDR_CS3_DIMMA# <5>
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
B DDR_A_D35 B
137 DQ35 VSS 138
139 140 DDR_A_D44
DDR_A_D40 VSS DQ44 DDR_A_D45
141 DQ40 DQ45 142
DDR_A_D41 143 144
DQ41 VSS DDR_A_DQS#5
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_A_CLK2 <5>
165 VSS CK1# 166 DDR_A_CLK#2 <5>
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60
DDR_A_D57 DQ56 DQ60 DDR_A_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
193 194 DDR_A_D63
A VSS DQ63 A
<9,13,17,24,28> SMB_CK_DAT0 195 SDA VSS 196
<9,13,17,24,28> SMB_CK_CLK0 197 198 R121 2 1 0_0402_5%
SCL SAO R123 2
+3VS 199 VDDSPD SA1 200 1 0_0402_5%
1
C237 P-TWO_A5692A-A0G16-N
0.1U_0402_16V4Z Security Classification Compal Secret Data
2
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
DDRII SO-DIMM 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 8 of 45
5 4 3 2 1
5 4 3 2 1
1000P_0402_25V8J
1 9 10 DDR_B_DM0 DDR_B_DQS[0..7]
DDR_B_DQS#0 VSS DM0 DDR_B_DQS[0..7] <5> 47_0804_8P4R_5%
11 DQS0# VSS 12
C203
DDR_B_DQS0 13 14 DDR_B_D6 DDR_B_MA[0..15]
DQS0 DQ6 DDR_B_MA[0..15] <5>
15 16 DDR_B_D7 RP13
2 DDR_B_D2 VSS DQ7 DDR_B_DQS#[0..7] DDR_B_MA11
17 DQ2 VSS 18 DDR_B_DQS#[0..7] <5> 8 1 2 1
DDR_B_D3 19 20 DDR_B_D12 DDR_B_MA7 7 2 C261 0.1U_0402_16V4Z
DQ3 DQ12 DDR_B_D13 DDR_B_MA6
21 VSS DQ13 22 6 3 1 2
D DDR_B_D8 23 24 DDR_B_MA4 5 4 C267 0.1U_0402_16V4Z D
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 28 47_0804_8P4R_5%
DDR_B_DQS#1 VSS VSS
29 DQS1# CK0 30 DDR_B_CLK1 <5>
DDR_B_DQS1 31 32 RP10
DQS1 CK0# DDR_B_CLK#1 <5>
33 VSS VSS 34 8 1 2 1
DDR_B_D10 35 36 DDR_B_D14 DDR_CS2_DIMMB# 7 2 C257 0.1U_0402_16V4Z
DDR_B_D11 DQ10 DQ14 DDR_B_D15 DDR_B_BS#2
37 DQ11 DQ15 38 6 3 1 2
39 40 DDR_CKE0_DIMMB 5 4 C268 0.1U_0402_16V4Z
VSS VSS
47_0804_8P4R_5%
41 VSS VSS 42
DDR_B_D16 43 44 DDR_B_D20 RP9
DDR_B_D17 DQ16 DQ20 DDR_B_D21 DDR_B_MA5
45 DQ17 DQ21 46 8 1 2 1
47 48 DDR_B_MA8 7 2 C277 0.1U_0402_16V4Z
DDR_B_DQS#2 VSS VSS DDR_B_MA9
49 DQS2# NC 50 6 3 1 2
DDR_B_DQS2 51 52 DDR_B_DM2 DDR_B_MA12 5 4 C695 0.1U_0402_16V4Z
DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22 47_0804_8P4R_5%
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 60 RP11
DDR_B_D24 VSS VSS DDR_B_D28 DDR_B_MA3
61 DQ24 DQ28 62 8 1 2 1
DDR_B_D25 63 64 DDR_B_D29 DDR_B_MA1 7 2 C222 0.1U_0402_16V4Z
DQ25 DQ29 DDR_B_MA10
65 VSS VSS 66 6 3 1 2
DDR_B_DM3 67 68 DDR_B_DQS#3 DDR_B_BS#0 5 4 C241 0.1U_0402_16V4Z
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 72 47_0804_8P4R_5%
DDR_B_D26 VSS VSS DDR_B_D30
73 DQ26 DQ30 74
DDR_B_D27 75 76 DDR_B_D31 RP12
C
DQ27 DQ31 DDR_B_WE# C
77 VSS VSS 78 8 1 2 1
DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB DDR_B_CAS# 7 2 C229 0.1U_0402_16V4Z
<5> DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB <5>
81 82 DDR_CS1_DIMMB# 6 3 1 2
DDR_CS2_DIMMB# VDD VDD DDR_B_MA15 DDR_B_ODT1 C273 0.1U_0402_16V4Z
<5> DDR_CS2_DIMMB# 83 NC NC/A15 84 5 4
DDR_B_BS#2 85 86 DDR_B_MA14
<5> DDR_B_BS#2 BA2 NC/A14
87 88 47_0804_8P4R_5%
DDR_B_MA12 VDD VDD DDR_B_MA11
89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7 RP22
DDR_B_MA8 A9 A7 DDR_B_MA6 DDR_CS3_DIMMB#
93 A8 A6 94 8 1 2 1
95 96 DDR_B_MA13 7 2 C658 0.1U_0402_16V4Z
DDR_B_MA5 VDD VDD DDR_B_MA4 DDR_B_ODT0
97 A5 A4 98 6 3 1 2
DDR_B_MA3 99 100 DDR_B_MA2 DDR_CS0_DIMMB# 5 4 C256 0.1U_0402_16V4Z
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104 47_0804_8P4R_5%
DDR_B_MA10 VDD VDD DDR_B_BS#1
105 A10/AP BA1 106 DDR_B_BS#1 <5>
DDR_B_BS#0 107 108 DDR_B_RAS# RP14
<5> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <5>
DDR_B_WE# 109 110 DDR_CS0_DIMMB# 8 1 2 1
<5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
111 112 DDR_CKE1_DIMMB 7 2 C215 0.1U_0402_16V4Z
DDR_B_CAS# VDD VDD DDR_B_ODT0 DDR_B_MA15
<5> DDR_B_CAS# 113 CAS# ODT0 114 DDR_B_ODT0 <5> 6 3 1 2
DDR_CS1_DIMMB# 115 116 DDR_B_MA13 DDR_B_MA14 5 4 C235 0.1U_0402_16V4Z
<5> DDR_CS1_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
DDR_B_ODT1 119 120 DDR_CS3_DIMMB# 47_0804_8P4R_5%
<5> DDR_B_ODT1 NC/ODT1 NC DDR_CS3_DIMMB# <5>
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
B DDR_B_D34 VSS DQ38 DDR_B_D39 B
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_B_CLK2 <5>
165 VSS CK1# 166 DDR_B_CLK#2 <5>
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D58 189 190
DDR_B_D59 DQ58 VSS DDR_B_D62 +3VS
A 191 DQ59 DQ62 192 A
193 194 DDR_B_D63
VSS DQ63
<8,13,17,24,28> SMB_CK_DAT0 195 SDA VSS 196
<8,13,17,24,28> SMB_CK_CLK0 197 198 R423 1 2 4.7K_0402_5%
SCL SAO
+3VS 199 VDDSPD SA1 200 2 1
1 R427 0_0402_5%
PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
<15> PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] <15>
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
<15> PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] <15>
U5B
<24> PCIE_MRX_C_WLANTX_P3 AB9 GPP_RX3P GPP_TX3P AD5 PCIE_MTX_WLANRX_P3 C44 1 2 WLAN@ 0.1U_0402_16V7K PCIE_MTX_C_WLANRX_P3 <24>
<24> PCIE_MRX_C_WLANTX_N3 AA9 GPP_RX3N PCIE I/F GPP GPP_TX3N AD6 PCIE_MTX_WLANRX_N3 C43 1 2 WLAN@ 0.1U_0402_16V7K PCIE_MTX_C_WLANRX_N3 <24>
VGAR1@216MQA6AVA11FG_FCBGA465_RS690M
+3VS L50
1 1 AVDDI=250mA
L11 AVDD=100mA +LPVDD 1 2 +1.8VS
C515 C519 1 2 +AVDD 1 1 MBC1608121YZF_0603
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z FBM-L11-201209-300LMA30T_0805 1 1
2 2 C504 C513
GND to B20 C108 C115 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2 2
2 2
+1.8VS +AVDDQ 1 2UMA_TV_CRMA U5C
L12 R317 150_0402_1% MBC1608121YZF_0603
1 2 1 2UMA_TV_LUMA B22 AVDD1 PART 3 OF 5 TXOUT_L0P B14 UMA_TXOUT0+ <15> GND to E14
MBC1608121YZF_0603 1 1 AVDDQ=200mA R316 150_0402_1% C22 B15
AVDD2 TXOUT_L0N UMA_TXOUT0- <15>
1 2 UMA_CRT_R G17 AVSSN1 TXOUT_L1P B13 UMA_TXOUT1+ <15>
C113 C523 R299 UMA@ 150_0402_1% H17 A13 L14
AVSSN2 TXOUT_L1N UMA_TXOUT1- <15>
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 1 2 UMA_CRT_G +1.8VS A20 H14 +LVDDR18D 1 2 +1.8VS
2 2 AVDDDI TXOUT_L2P UMA_TXOUT2+ <15>
R297 UMA@ 150_0402_1% B20 G14 1 1
AVSSDI TXOUT_L2N UMA_TXOUT2- <15>
GND to A22 1 2 UMA_CRT_B TXOUT_L3P D17
R295 UMA@ 150_0402_1% +AVDDQ A21 E17 C109 C116
AVDDQ TXOUT_L3N 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
A22 AVSSQ 2 2
CRT/TVOUT
TXOUT_U0P A15 UMA_TZOUT0+ <15>
+1.8VS +NB_PLLVDD UMA_TV_CRMA C21 MBC1608121YZF_0603
<14> UMA_TV_CRMA C TXOUT_U0N B16 UMA_TZOUT0- <15> GND to A14, D12
L13 UMA_TV_LUMA C20 C17
<14> UMA_TV_LUMA Y TXOUT_U1P UMA_TZOUT1+ <15>
1 2 1 2 UMA_TV_COMPS D19 COMP TXOUT_U1N C18 UMA_TZOUT1- <15>
MBK2012221YZF 0805 1 1 PLLVDD18=625mA R300 @ 75_0402_1% B17
TXOUT_U2P UMA_TZOUT2+ <15>
UMA_CRT_R E19 A17 L54
<14> UMA_CRT_R RED TXOUT_U2N UMA_TZOUT2- <15>
C114 C522 UMA_CRT_G F19 A18 +LVDDR33A 1 2 +3VS
<14> UMA_CRT_G GREEN TXOUT_U3P
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z UMA_CRT_B G19 B18 LVDDR33=180mA 1 1
2 2 <14> UMA_CRT_B BLUE TXOUT_U3N
<14> UMA_CRT_VSYNC C6 DACVSYNC
GND to B10 A5 E15 C505 C537
<14> UMA_CRT_HSYNC DACHSYNC TXCLK_LP UMA_TXCLK+ <15>
D15 0.1U_0402_16V4Z 4.7U_0805_10V4Z
TXCLK_LN UMA_TXCLK- <15> 2 2
R58 1 2 715_0402_1% B21 H15
RSET TXCLK_UP UMA_TZCLK+ <15>
TXCLK_UN G15 UMA_TZCLK- <15>
+3VS UMA_CRT_SCL B6
<14> UMA_CRT_SCL UMA_CRT_SDA DACSCL +LPVDD
A6 D14 GND to C15
LVTM
UMA_CRT_SCL <14> UMA_CRT_SDA DACSDA LPVDD
1 2 LPVSS E14
R68 HDMI@ 24K_0402_5% +NB_PLLVDD A10
UMA_CRT_SDA PLLVDD(PLLVDD18) +LVDDR18D
1 2 B10 PLLVSS LVDDR18D_1 A12
R61 HDMI@ 24K_0402_5% B12 +3VS C499
LVDDR18D_2 +LVDDR33A 0.1U_0402_16V4Z
B24 C12
PLL PWR
+1.8VS +NB_HTPVDD +NB_HTPVDD HTPVDD LVDDR18A_1(LVDDR33_1)
B25 HTPVSS LVDDR18A_2(LVDDR33_2) C13
L52
14
1 2 C10 A16 U20A
<15,17,24,25,28,30,34> NB_RST# SYSRESET# LVSSR1
MBC1608121YZF_0603 1 1 HTPVDD=200mA NB_PWRGD C11 A14 LVDS_ENBKL 1
P
<30> NB_PWRGD POWERGOOD LVSSR3 A
NB_LDTSTOP# C5 D12 1 2 3 UMA_ENBKL <30>
C514 C520 LDTSTOP# LVSSR5 R488 2K_0402_5% O
<16> ALLOW_LDTSTOP B5 ALLOW_LDTSTOP LVSSR6 C19 2 B
G
@ 10U_0805_10V4Z 1U_0402_6.3V4Z
PM
LVSSR7 C15 UMA@
2 2 R45 2 +3VS
1 10K_0402_5% C23 C16 SN74LVC08APW_TSSOP14
7
HTTSTCLK LVSSR8
GND to B25 <13> HTREFCLK B23 HTREFCLK
MP:Add R488 and
NB_PWRGD
14
R489 for LCD
R65 2 1 10K_0402_5% C2 F14 U20B
+1.2V_HT +PLLVDD12 TVCLKIN LVSSR12 flash issue
F15 4
P
L15 LVSSR13 A
<13> NB_REFCLK B11 OSCIN O 6 UMA_ENVDD <15>
CLOCKs
1 2 +PLLVDD12 A11 LVDS_ENVDD 5
OSCOUT(PLLVDD12) B
G
MBC1608121YZF_0603 1 1 PLLVDD12=70mA 1 2 SN74LVC08APW_TSSOP14
<13> GFX_PCIE F2 R489 2K_0402_5%
7
C117 C110 GFX_CLKP LVDS_ENVDD
<13> GFX_PCIE# E1 GFX_CLKN LVDS_DIGON E12 UMA@
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z G12 LVDS_ENBKL
2 2 LVDS_BLON
<13> SBLINKCLK G1 SB_CLKP LVDS_BLEN F12 C:Set to DVD@
<13> SBLINKCLK# G2 SB_CLKN
DVO_D0(GPP_TX0P) AD14 PCIE_MTX_DVDRX_P0 C409 1 2 DVD@ 0.1U_0402_16V7K
PCIE_MTX_C_DVDRX_P0 <24>
R298 2 1 @ 3K_0402_5% DFT_GPIO0 D6 AD15 PCIE_MTX_DVDRX_N0 C414 1 2 DVD@ 0.1U_0402_16V7K
DFT_GPIO0 DVO_D1(GPP_TX0N) PCIE_MTX_C_DVDRX_N0 <24>
R301 2 1 @ 3K_0402_5% DFT_GPIO1 D7 AE15
R59 @ 3K_0402_5% DFT_GPIO2 DFT_GPIO1 DVO_D2(DEBUG6)
2 1 C8 DFT_GPIO2 DVO_D3(GPP_RX0P) AD16 PCIE_MRX_C_DVDTX_P0 <24>
R67 2 1 @ 3K_0402_5% DFT_GPIO3 C7 AE16
DFT_GPIO3 DVO_D4(GPP_RX0N) PCIE_MRX_C_DVDTX_N0 <24>
R60 2 1 @ 3K_0402_5% DFT_GPIO4 B8 AC17
R66 @ 3K_0402_5% DFT_GPIO5 DFT_GPIO4 DVO_D5(DEBUG9)
2 1 A8 DFT_GPIO5 DVO_D6(DEBUG10) AD18
DVO_D7(GPP_TX1N) AE19 PCIE_MTX_NEWRX_N1 C62 1 2 NEW@ 0.1U_0402_16V7K
PCIE_MTX_C_NEWRX_N1 <28>
DVO
<16> BMREQ# B2 BMREQ# DVO_D8(GPP_TX1P) AD19 PCIE_MTX_NEWRX_P1 C61 1 2 NEW@ 0.1U_0402_16V7K
PCIE_MTX_C_NEWRX_P1 <28>
MIS.
UMA_LCD_CLK A2 AE20
<15> UMA_LCD_CLK I2C_CLK DVO_D9(GPP_RX1N) PCIE_MRX_C_NEWTX_N1 <28>
<15> UMA_LCD_DAT UMA_LCD_DAT B4 AD20
+3VS I2C_DATA DVO_D10(GPP_RX1P) PCIE_MRX_C_NEWTX_P1 <28>
C:Set to UMA@ AA15 THERMALDIODE_P DVO_D11(DEBUG15) AE21
AB15 THERMALDIODE_N
2 1 UMA_LCD_CLK AD13
R64 UMA@ 4.7K_0402_5% DVO_VSYNC(DEBUG0)
C14 TMDS_HPD DVO_DE(DEBUG2) AC13
2 1 UMA_LCD_DAT +3VS R71 2 1 @ 4.7K_0402_5% B3 AE13
R62 UMA@ 4.7K_0402_5% R72 DDC_DATA DVO_HSYNC(DEBUG1)
1 2 4.7K_0402_5% C3 TESTMODE DVO_IDCKP(DEBUG14) AE17
NB_STRAP_DATA A3 AD17
STRP_DATA DVO_IDCKN(DEBUG13)
1 2 NB_STRAP_DATA
R70 10K_0402_5% VGAR1@216MQA6AVA11FG_FCBGA465_RS690M
1 2 +1.8VS
R63 @ 10K_0402_5% RS690 RS690 only
DFT_GPIO0 DFT_GPIO1 DFT_GPIO[4:2] DFT_GPIO5
2
+3VS
PULL HIGH
10K_0402_5%
LOW: 1.0V Memor y Bypass the loading These pin straps are used to configure PCI-E GPP mode: Enable debug bus via the memory
1
1K_0402_5%
Won't Support in IALAA pulled high) side port of EEPROM straps IO pads, if available in the package
111: register defined (register default to Config E) DEFAULT
2 1
+1.2V_HT U5E
A25 VSS1
2 1 F11 VSS2 PAR 5 OF 5 VSSA2 V12
C57 @ 330U_D2E_2.5VM
+
D23 VSS3 VSSA3 V11
L43 E9 V14
C54 VSS4 VSSA4
1 2 +1.2V_HT G11 VSS5 VSSA5 F3
10U_0805_10V4Z VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 Y23 V15
C55 U5D VSS6 VSSA6
P11 VSS7 VSSA7 A1
10U_0805_10V4Z +VDDA12
AA17 VDD_HT1 PART 4 OF 5 VDDA12_1 B1
C447 10U_0805_10V4Z
R24 VSS8 VSSA8 H1
D VDD_HT(I/O only)=800mA AB17 VDD_HT2 VDDA12_2 C1 AE18 VSS9 VSSA9 G3 D
C442 1 2 1U_0402_6.3V4Z AB19 D1 M15 J2
C456 1U_0402_6.3V4Z VDD_HT3 VDDA12_3 C58 10U_0805_10V4Z VSS10 VSSA10
1 2 AC18 VDD_HT4 VDDA12_4 D2 J22 VSS11 VSSA11 H3
C465 1 2 1U_0402_6.3V4Z AC19 D3 G23
C445 1U_0402_6.3V4Z VDD_HT5 VDDA12_5 VSS12
1 2 AC20 VDD_HT6 VDDA12_6 E2 J12 VSS13 VSSA13 J6
C432 1 2 1U_0402_6.3V4Z AD21 E3 C521 10U_0805_10V4Z L12
VDD_HT7 VDDA12_7 VSS14
AD22 VDD_HT8 VDDA12_8 F4 L14 VSS15 VSSA15 F1
AD23 VDD_HT9 VDDA12_9 E6 L20 VSS16 VSSA16 L6
AD24 G7 C500 1 2 1U_0402_6.3V4Z L23 M2
VDD_HT10 VDDA12_10 C441 1U_0402_6.3V4Z VSS17 VSSA17
AE23 VDD_HT11 VDDA12_11 L9 1 2 M11 VSS18 VSSA18 M6
+1.8VS AE24 M9 C453 1 2 1U_0402_6.3V4Z M20 J3
VDD_HT12 VDDA12_12 C512 1U_0402_6.3V4Z VSS19 VSSA19
AE25 VDD_HT13 1 2 M23 VSS20 VSSA20 P6
POWER
W17 A4 C506 1 2 1U_0402_6.3V4Z M25 T1
C492 VDD_HT14 VDDC_1 VSS21 VSSA21
1 2 1U_0402_6.3V4Z Y17 VDD_HT15 VDDC_2 A7 C463 1 2 1U_0402_6.3V4Z N12 VSS22 VSSA22 N3
C489 1 2 1U_0402_6.3V4Z A9 N14
VDDC_3 VSS23
J14 VDD18_1 VDDC_4 A19 VSSA24 R6
VDD_18=2mA J15 VDD18_2 VDDC_5 B9 L24 VSS25 VSSA25 U2
L45 B19 P13 T3
VDDC_6 VSS26 VSSA26
2 1 AB3 C9 P20 U3
GROUND
+1.2V_HT +VDDA12 +VDDA12 VDDA18_1(VDDA12_13) VDDC_7 VSS27 VSSA27
FBMA-L11-201209-221LMA30T_0805 AB4 D9 P15 U6
VDDA18_2(VDDA12_14) VDDC_8 L41 1 VSS28 VSSA28
10U_0805_10V4Z
VDDA_12=2.5A AC3 VDDA18_3(VDDA12_15) VDDC_9 D20 +1.2V_HT 2 +NB_VDDC R12 VSS29
C448 AD2 G20 FBMA-L11-201209-221LMA30T_0805 R14 Y1
C493 1U_0402_6.3V4Z VDDA18_4(VDDA12_16) VDDC_10 L44 1 VSS30 VSSA30
1 2 AE1 VDDA18_5(VDDA12_17) VDDC_11 H11 2 R20 VSS31
C470 1 2 1U_0402_6.3V4Z AE2 J11 FBMA-L11-201209-221LMA30T_0805 W23 W6
C490 1U_0402_6.3V4Z VDDA18_6(VDDA12_18) VDDC_12 VSS32 VSSA32
1 2 U7 VDDA18_7(VDDA12_19) VDDC_13 J19 Y25 VSS33 VSSA33 AC2
C486 1 2 1U_0402_6.3V4Z W7 L11 VDD_CORE=5A AD25 Y3
VDDA18_8(VDDA12_20) VDDC_14 VSS34 VSSA34
VDDC_15 L13 U20 VSS35 VSSA35 Y9
D11 VDDR3_1 VDDC_16 L15 H25 VSS36 VSSA36 Y11
+3VS E11 VDDR3_2 VDDC_17 L17 W24 VSS37 VSSA93 Y12
C VDDR3=70mA M12 Y22 Y14 C
VDDC_18 VSS38 VSSA94
AC12 VDD_DVO1(VDDR_1) VDDC_19 M14 AC23 VSS39 VSSA95 AA3
330U_D2E_2.5VM
C510
C491
C480
C483
C485
C471
C479
C474
C502
C529
C530
1 2 AD12 VDD_DVO2(VDDR_2) VDDC_20 N11 1 D25 VSS40 VSSA37 R9
C511 2.2U_0603_6.3V4Z AE12 N13 1 1 1 1 1 1 1 1 1 1 1 G24 AD1
VDD_DVO3(VDDR_3) VDDC_21 VSS41 VSSA38
C424
2 1 N15 + AC14 AC5
C498 0.1U_0402_16V4Z +NB_VDDPLL VDDC_22 VSS42 VSSA39
E7 VDDA12(VDDPLL_1) VDDC_23 P12 VSSA40 AC6
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
F7 VDDA12(VDDPLL_2) VDDC_24 P14 AC22 VSS44 VSSA41 AC7
2 2 2 2 2 2 2 2 2 2 2 2
F9 VSSA12(VSSPLL_1) VDDC_25 P17 R23 VSS45 VSSA42 AD3
+1.8VS G9 VSSA12(VSSPLL_2) VDDC_26 R11 C4 VSS46 VSSA43 AC9
VDDC_27 R13 AE22 VSS47 VSSA44 AC10
2 1 +VDDHT_PKG D22 VDDHT_PKG VDDC_28 R15 T23 VSS48 VSSA45 G6
C433 1U_0402_6.3V4Z +VDDA12_PKG1 M1 U11 T25 Y15
VDDA12_PKG1 VDDC_29 VSS49 VSSA46
2 1 +VDDA12_PKG2 AC11 VDDA12_PKG2 VDDC_30 U12 AE14 VSS50 VSSA47 AC4
C446 1U_0402_6.3V4Z U14 R17 P9
VDDC_31 VSS51 VSSA48
2 1 VDDC_32 U15 H23 VSS52 VSSA49 AE6
C430 1U_0402_6.3V4Z M17 AE10
VGAR1@216MQA6AVA11FG_FCBGA465_RS690M VSS53 VSSA50
A23 VSS54 VSSA51 M3
L49 AC15
+NB_VDDPLL VSS55
+1.2V_HT 1 2 F17 VSS56
MBC1608121YZF_0603 +VDDA12_PKG1
1 2 VDDPLL=50mA D4 VSS57
C516 C501 M13
4.7U_0805_10V4Z 1U_0402_6.3V4Z VSS59
1 AC16 VSS60
2 1
H12 VSS61
C484 B7 VSS62
4.7U_0805_10V4Z
2
GND to F9, G9.
B VGAR1@216MQA6AVA11FG_FCBGA465_RS690M B
A A
+3VS_CLK
+3VSNeed
VDD=500mA +3VS
to link "SM010007E00" VDDA=50mA
L57 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 +3VS_CLK L17
CHB2012U121_0805 +3VS_CLK_VDDA 1 2
1 1 1 1 1 1 1 1 1 1 1 1 MBC1608121YZF_0603
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
VDD_48=50mA C592 C590 C595 C593 C170 C636 C167 C594 C171
C168
C169
C179
L56 2 2 2 2 2 2 2 2 2 2 2 2
1 +3VS 1 2 +3VS_CLK_VDD48 @ 10U_0805_10V4Z 1
MBC1608121YZF_0603 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C588 C596 @
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z CPUCLK0_H <6>
2 1
1
U25
R101
+3VS_CLK 54 50 261_0402_1%
VDDCPU VDDA
14 VDDSRC GNDA 49
L58 23
2
VDDSRC CPUCLK0 R99 1
+3VS 1 2 +3VS_CLK_VDDREF 28 VDDSRC CPUCLK8T0 56 2 47.5_0402_1%
MBC1608121YZF_0603 44 55 CPUCLK0# R100 1 2 47.5_0402_1% CPUCLK0_L <6>
VDDSRC CPUCLK8C0
1 2 +3VS_CLK_VDD48 5 VDD48 CPUCLK8T1 52
39 VDDATIG CPUCLK8C1 51
C599 C597 +3VS_CLK_VDDREF 2 SBLINKCLK 1 2
VDDREF SBLINKCLK_R R366 33_0402_5% SBLINKCLK R356 49.9_0402_1%
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 60 VDDHTT SRCCLKT6 16 1 2 SBLINKCLK <11>
2 1 SBLINKCLK#_R R365 33_0402_5% SBLINKCLK# SBLINKCLK#
SRCCLKC6 17 1 2 SBLINKCLK# <11> 1 2
53 41 GFX_PCIE_R R397 1 2 33_0402_5% GFX_PCIE GFX_PCIE <11> R355 49.9_0402_1%
GNDCPU ATIGCLKT0 GFX_PCIE_R# R396 33_0402_5% GFX_PCIE# GFX_PCIE
15 GNDSRC ATIGCLKC0 40 1 2 GFX_PCIE# <11> 1 2
22 37 R92 49.9_0402_1%
GNDSRC ATIGCLKT1 GFX_PCIE#
29 GNDSRC ATIGCLKC1 36 1 2
45 35 R93 49.9_0402_1%
GNDSRC ATIGCLKT2
VDD_REF=50mA 8 GND48 ATIGCLKC2 34
38 GNDATIG ATIGCLKT3 30
1 31 SBSRCCLK 1 2
C603 GNDREF ATIGCLKC3 SBSRCCLK_R R360 33_0402_5% SBSRCCLK R354 49.9_0402_1%
58 GNDHTT SRCCLKT5 18 1 2 SBSRCCLK <16>
33P_0402_50V8J 19 SBSRCCLK_R# R359 1 2 33_0402_5% SBSRCCLK# SBSRCCLK# <16> SBSRCCLK# 1 2
XTALIN_CLK SRCCLKC5 CLK_PCIE_VGA_R R373 VGA@ 33_0402_5% CLK_PCIE_VGA R353 49.9_0402_1%
1 2 3 X1 SRCCLKT4 20 1 2 CLK_PCIE_VGA <15>
2 21 CLK_PCIE_VGA_R# R372 1 2 VGA@ 33_0402_5% CLK_PCIE_VGA# CLK_PCIE_VGA 1 2 VGA@ 2
SRCCLKC4 CLK_PCIE_VGA# <15>
1
2
Y3 XTALOUT_CLK 4 24 R352 49.9_0402_1%
+3VS_CLK X2 SRCCLKT3 CLK_PCIE_VGA# 1
SRCCLKC3 25 C:Set R377 and R376 with DVD@ 2 VGA@
R390 26 CLK_DVD_R R377 1 2 DVD@ 33_0402_5% CLK_DVD R351 49.9_0402_1%
SRCCLKT2 CLK_DVD <24>
@ 1M_0402_5% 27 CLK_DVD_R# R376 1 2 DVD@ 33_0402_5% CLK_DVD# CLK_PCIE_LAN 1 2
CLK_DVD# <24>
2
SRCCLKC2
1 2 CLK_RESET CLK_RESET 11 47 CLK_NEW_R R404 1 2 NEW@33_0402_5% CLK_NEW
CLK_NEW <28>
R102 49.9_0402_1%
1
ICS951462AGLFT_TSSOP64
HTREFCLK 1 2
3 +3VS R107 49.9_0402_1% 3
CLKREQ_WLAN# 1 2
+3VS_CLK R398 100K_0402_5%
CLKREQ_DVD# 1 2
R386 100K_0402_5%
EXT CLK FREQUENCY SELECT TABLE(MHZ) CLKREQ_NEW# 1 2
1
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R104 R395 100K_0402_5%
R105
R106
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
[2:1]
2
2
0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved
0 0 1 X 100.00 X/3 X/6 48.00 Reserved FS0
FS1
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved FS2
1
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
R108
R109
R110
4 4
CRT CONNECTOR L6
MP:Update D29 to meet CRT.
+CRT_VCC
CRT_DDC_CLK
JP24
1
CRT_R CRT_R_L CRT_DDC_DAT 2
<11> UMA_CRT_R 1 2 3
FCM2012C-800_0805 +5VS +R_CRT_VCC +CRT_VCC VSYNC
UMA@ D29 F2 H SYNC 4
CRT_R_L 5
2 1 1 2 6
L4 RB491D_SOT23 1A_6VDC_MINISMDC110 CRT_G_L 7
1 8
CRT_G 1 2 CRT_G_L C422
<11> UMA_CRT_G 9
FCM2012C-800_0805 CRT_B_L
UMA@ @ 0.1U_0402_16V4Z 10
1 1
2 11
L3 12
<11> UMA_CRT_B CRT_B 1 2 CRT_B_L UMA@ ACES_85201-1205
FCM2012C-800_0805
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
6P_0402_50V8K
6P_0402_50V8K
6P_0402_50V8K
UMA@ C:EMI solution to add
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 C13,C16,C21 in BOM with
1
+CRT_VCC
1 1 1 22P value.
R20 R19 R16 C17 C25 C37 C21 C16 C13
UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ A: Follow AMD command.
2 2 2 +3VS
1
2 2 2
2
R21 R18
B:As EMI request UMA@ UMA@
2
G
L3,L4,L6 need to link 19.1K_0402_1% 19.1K_0402_1%
Q4
2
SM010009L00 CRT_DDC_DAT
<11> UMA_CRT_SDA 3 1
D
2
G
2N7002_SOT23-3
Q5 UMA@
3 1 CRT_DDC_CLK
<11> UMA_CRT_SCL
D
2N7002_SOT23-3
+CRT_VCC UMA@
1 1
1 2 2 1 C:Chg. PN to SB770020010.
C428 0.1U_0402_16V4Z R282 10K_0402_5% C38 C24
5
1
UMA@ UMA@ @ @
470P_0402_50V8J 2 2 470P_0402_50V8J
P
CRT_HSYNC 2 OE# D_CRT_HSYNC H SYNC
2 4 1 2 2
<11> UMA_CRT_HSYNC A Y L40 UMA@ 10_0402_5%
G
U16
UMA@ D_CRT_VSYNC 1 2 VSYNC
3
10P_0402_50V8J
10P_0402_50V8J
1 1
1 2
C426 UMA@ C425 C427
5
1
0.1U_0402_16V4Z UMA@ UMA@
2 2
P
OE#
CRT_VSYNC 2 4
<11> UMA_CRT_VSYNC A Y
G U17
UMA@
3
SN74AHCT1G125GW_SOT353-5
3 TV-OUT CONNECTOR D4
@ DAN217_SC59
D5
@ DAN217_SC59 3
1
2
3
+3VS
1 2 C524
1 2 @ 22P_0402_50V8J
<15> VGA_TV_LUMA
R288 VGA@ 0_0402_5%
1 2 TV_LUMA 1 2
<11> UMA_TV_LUMA
R287 UMA@ 0_0402_5% L51 MBK1608121YZF_0603
1 2 TV_CRMA 1 2
<15> VGA_TV_CRMA
R290 VGA@ 0_0402_5% L53 MBK1608121YZF_0603
1 2 JP26
<11> UMA_TV_CRMA
1
1 1 @ 22P_0402_50V8J TV_LUMA_L 3 6
R307 R310 3
2 5
150_0402_1% 150_0402_1% C533
100P_0402_25V8K
C517
100P_0402_25V8K
1
C536
1
C535
1
2
1
TV-OUT Conn.
2
2 2 ALLTO_C10877-104A1-L_4P 1. Y ground
2
2 2 2. C ground
100P_0402_25V8K 100P_0402_25V8K 3. Y (luminance+sync)
4 4. C (crominance) 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TV-OUT, LVDS CONNECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 14 of 45
A B C D E
5 4 3 2 1
3
S
3 4 +3VS
3 4 VGA_ENVDD ENVDD
G
5 5 6 6 2
7 7 8 8
1
9 10 D AO3413_SOT23
1
9 10
11 11 12 12 +LCDVDD 80mil
13 14 R2
13 14
1
15 16 PCIE_MTX_C_GRX_N[0..15] 2K_0402_5% 1
15 16 PCIE_MTX_C_GRX_N[0..15] <10>
17 18 C4 B:Set "@".
2
17 18
1
D 19 20 PCIE_MTX_C_GRX_P[0..15] R5 D
19 20 PCIE_MTX_C_GRX_P[0..15] <10>
21 22 470_0805_5% R6 @ 4.7U_0805_10V4Z
+3VS 21 22 PCEI_GTX_C_MRX_N[0..15] 2
23 24 100_0402_5%
PCIE_GTX_C_MRX_N[0..15] <10>
1 2
23 24
25 25 26 26
3
PCEI_GTX_C_MRX_P[0..15] D Q3
S
+1.5VS 27 28 PCIE_GTX_C_MRX_P[0..15] <10>
2
27 28 Q2
G
29 29 30 30 2 2
31 32 2N7002_SOT23-3 G
31 32 AO3413_SOT23
33 34 S D
+LCDVDD Width: 80mils
1
33 34
35 35 36 36 C:Chg. PN to SB770020010.
37 38 +LCDVDD
37 38
1
39 39 40 40 1
41 41 42 42 +2.5VS
+2.5VS 43 44 C3 R7 80mil
PCEI_GTX_C_MRX_P15 43 44 PCIE_MTX_C_GRX_P15 0.047U_0402_16V4Z 100K_0402_5%
45 45 46 46
PCEI_GTX_C_MRX_N15 PCIE_MTX_C_GRX_N15 2
47 48 1
2
47 48
49 49 50 50
PCEI_GTX_C_MRX_P14 51 52 PCIE_MTX_C_GRX_P14 C2 C1
PCEI_GTX_C_MRX_N14 51 52 PCIE_MTX_C_GRX_N14 @ 4.7U_0805_10V4Z 0.1U_0402_16V4Z
53 53 54 54
2
55 55 56 56
PCEI_GTX_C_MRX_P13 57 58 PCIE_MTX_C_GRX_P13
PCEI_GTX_C_MRX_N13 57 58 PCIE_MTX_C_GRX_N13 +3VS DAC_BRIG
59 59 60 60 1 2 B:Set "@".
61 62 C407 @ 68P_0402_50V8J
PCEI_GTX_C_MRX_P12 61 62 PCIE_MTX_C_GRX_P12 BKOFF# INVT_PWM
63 63 64 64 1 2 1 2
PCEI_GTX_C_MRX_N12 65 66 PCIE_MTX_C_GRX_N12 R279 4.7K_0402_5% C401 @ 68P_0402_50V8J B+ +INV
65 66 BKOFF# L34
67 67 68 68 1 2
PCEI_GTX_C_MRX_P11 69 70 PCIE_MTX_C_GRX_P11 C413 @ 68P_0402_50V8J 1 2
PCEI_GTX_C_MRX_N11 69 70 PCIE_MTX_C_GRX_N11
71 71 72 72 1 2LCD_EDID_CLK FBMA-L11-201209-221LMA30T_0805 1 1
73 74 C9 @ 68P_0402_50V8J C390
PCEI_GTX_C_MRX_P10 73 74 PCIE_MTX_C_GRX_P10
75 75 76 76 1 2LCD_EDID_DATA C389
C PCEI_GTX_C_MRX_N10 77 78 PCIE_MTX_C_GRX_N10 C7 @ 68P_0402_50V8J 0.1U_0402_25V4Z 68P_0402_50V8J C
77 78 JP3 2 2
79 79 80 80 EMI
PCEI_GTX_C_MRX_P9 81 82 PCIE_MTX_C_GRX_P9 32
PCEI_GTX_C_MRX_N9 81 82 PCIE_MTX_C_GRX_N9 GND2
83 83 84 84 31 GND1
85 86 JP4
PCEI_GTX_C_MRX_P8 85 86 PCIE_MTX_C_GRX_P8 LCD_TZOUT1-
87 87 88 88 29 29 30 30 41 GND GND 42
PCEI_GTX_C_MRX_N8 89 90 PCIE_MTX_C_GRX_N8 27 28 LCD_TZOUT0- 39 40 LCD_TZCLK+
89 90 27 28 LCD_TZOUT0+ 39 40 LCD_TZCLK-
91 91 92 92 25 25 26 26 +3VS 37 37 38 38
PCEI_GTX_C_MRX_P7 93 94 PCIE_MTX_C_GRX_P7 LCD_TXOUT0+ 23 24 BKOFF# LCD_TZOUT2- 35 36
PCEI_GTX_C_MRX_N7 93 94 PCIE_MTX_C_GRX_N7 LCD_TXOUT0- 23 24 LCD_TZOUT2+ 35 36
95 95 96 96 21 21 22 22 33 33 34 34
97 98 LCD_TXOUT1+ 19 20 DAC_BRIG LCD_TZOUT1+ 31 32
PCEI_GTX_C_MRX_P6 97 98 PCIE_MTX_C_GRX_P6 LCD_TXOUT1- 19 20 INVT_PWM LCD_TZOUT1- 31 32 +3VS
99 99 100 100 17 17 18 18 29 29 30 30
PCEI_GTX_C_MRX_N6 101 102 PCIE_MTX_C_GRX_N6 LCD_TXOUT2- 15 16 27 28
101 102 15 16 27 28
0.1U_0402_16V4Z
103 104 LCD_TXOUT2+ 13 14 LCD_TXCLK- 25 26
PCEI_GTX_C_MRX_P5 103 104 PCIE_MTX_C_GRX_P5 13 14 LCD_TXCLK+ LCD_TXOUT0+ 25 26 BKOFF#
105 105 106 106 11 11 12 12 23 23 24 24 BKOFF# <30>
PCEI_GTX_C_MRX_N5 107 108 PCIE_MTX_C_GRX_N5 9 10 LCD_TXOUT0- 21 22 1
107 108 LCD_EDID_CLK 9 10 LCD_TXOUT1+ 21 22 DAC_BRIG
109 109 110 110 7 7 8 8 19 19 20 20 DAC_BRIG <30>
PCEI_GTX_C_MRX_P4 111 112 PCIE_MTX_C_GRX_P4 LCD_EDID_DATA 5 6 LCD_TXOUT1- 17 18 INVT_PWM C415
111 112 5 6 17 18 INVT_PWM <30>
PCEI_GTX_C_MRX_N4 113 114 PCIE_MTX_C_GRX_N4 +LCDVDD_C 3 4 LCD_TXOUT2- 15 16
113 114 +LCDVDD_C 3 4 LCD_TXOUT2+ 15 16 LCD_TXCLK- 2
115 115 116 116 1 1 2 2 +INV 13 13 14 14
PCEI_GTX_C_MRX_P3 117 118 PCIE_MTX_C_GRX_P3 11 12 LCD_TXCLK+ +INV
PCEI_GTX_C_MRX_N3 117 118 PCIE_MTX_C_GRX_N3 ACES_88242-3001 11 12
119 119 120 120 9 9 10 10
121 122 LVDS30CON@ LCD_EDID_CLK 7 8
PCEI_GTX_C_MRX_P2 121 122 PCIE_MTX_C_GRX_P2 L36 LCD_EDID_DATA 7 8
123 123 124 124 5 5 6 6
PCEI_GTX_C_MRX_N2 125 126 PCIE_MTX_C_GRX_N2 +LCDVDD 1 2 3 4
125 126 +LCDVDD_C 3 4
127 127 128 128 1 1 2 2
PCEI_GTX_C_MRX_P1 129 130 PCIE_MTX_C_GRX_P1 1 0_0805_5% 1
PCEI_GTX_C_MRX_N1 129 130 PCIE_MTX_C_GRX_N1 ACES_88242-4001
131 131 132 132
133 134 C403 C394 + LVDS40CON@
B PCEI_GTX_C_MRX_P0 133 134 PCIE_MTX_C_GRX_P0 0.1U_0402_16V4Z 22U_A_4VM B
135 135 136 136
PCEI_GTX_C_MRX_N0 PCIE_MTX_C_GRX_N0 A:Follow ISKAA modify for HDMI1932. 2
137 137 138 138
2
139 139 140 140
<20> VGA_HPD 141 141 142 142 CLK_PCIE_VGA <13>
<20> VGA_DVI_SCLK 143 143 144 144 CLK_PCIE_VGA# <13>
<20> VGA_DVI_SDATA 145 145 146 146
147 148 LCD_EDID_CLK R8 1 2 UMA@ 0_0402_5% UMA_LCD_CLK UMA_LCD_CLK <11>
147 148 NB_RST# <11,17,24,25,28,30,34>
149 150 LCD_EDID_DATA LCD_EDID_DATA R9 1 2 UMA@ 0_0402_5% UMA_LCD_DAT UMA_LCD_DAT <11>
<20> VGA_DVI_TXD0- 149 150
151 152 LCD_EDID_CLK
<20> VGA_DVI_TXD0+ 151 152
153 154 LCD_TXCLK- R255 1 2 LVDS30@ 0_0402_5%
153 154 UMA_TXCLK- <11>
155 156 LCD_TXCLK- LCD_TXCLK+ R256 1 2 LVDS30@ 0_0402_5%
<20> VGA_DVI_TXD1- 155 156 UMA_TXCLK+ <11>
157 158 LCD_TXCLK+
<20> VGA_DVI_TXD1+ 157 158
159 160 LCD_TXOUT0- R257 1 2 LVDS30@ 0_0402_5%
159 160 UMA_TXOUT0- <11>
161 162 LCD_TXOUT0- LCD_TXOUT0+ R258 1 2 LVDS30@ 0_0402_5%
<20> VGA_DVI_TXD2- 161 162 UMA_TXOUT0+ <11>
163 164 LCD_TXOUT0+
<20> VGA_DVI_TXD2+ 163 164
165 166 LCD_TXOUT1- R259 1 2 LVDS30@ 0_0402_5%
165 166 UMA_TXOUT1- <11>
167 168 LCD_TXOUT1- LCD_TXOUT1+ R260 1 2 LVDS30@ 0_0402_5%
<20> VGA_DVI_TXC+ 167 168 UMA_TXOUT1+ <11>
A:Delete 169 170 LCD_TXOUT1+
<20> VGA_DVI_TXC- 169 170
VGA_SMB_DAT/CLK 171 172 LCD_TXOUT2- R268 1 2 LVDS30@ 0_0402_5%
171 172 UMA_TXOUT2- <11>
173 174 LCD_TXOUT2- LCD_TXOUT2+ R269 1 2 LVDS30@ 0_0402_5%
bec'z delete 173 174 UMA_TXOUT2+ <11>
175 176 LCD_TXOUT2+
HDMI/1932 fun.. 175 176 LCD_TZOUT0- R261 1
<6,30> EC_SMB_CK2 177 177 178 178 2 LVDS40@ 0_0402_5% UMA_TZOUT0- <11>
<6,30> EC_SMB_DA2 179 180 LCD_TZOUT0- LCD_TZOUT0+ R262 1 2 LVDS40@ 0_0402_5%
179 180 UMA_TZOUT0+ <11>
181 182 LCD_TZOUT0+
181 182 LCD_TZOUT1- R266 1
+5VALW 183 183 184 184 2 LVDS40@ 0_0402_5% UMA_TZOUT1- <11>
+CRT_VCC 185 186 LCD_TZOUT1- LCD_TZOUT1+ R267 1 2 LVDS40@ 0_0402_5%
185 186 UMA_TZOUT1+ <11>
187 188 LCD_TZOUT1+
187 188 LCD_TZOUT2- R263 1
<26,28,30,35,38> SUSP# 189 189 190 190 2 LVDS40@ 0_0402_5% UMA_TZOUT2- <11>
VGA_ENVDD 191 192 LCD_TZOUT2- LCD_TZOUT2+ R264 1 2 LVDS40@ 0_0402_5%
A 191 192 UMA_TZOUT2+ <11> A
193 194 LCD_TZOUT2+
<30> VGA_ENBKL 193 194
195 196 LCD_TZCLK- R271 1 2 LVDS40@ 0_0402_5%
195 196 UMA_TZCLK- <11>
<14> VGA_TV_LUMA 197 198 LCD_TZCLK- LCD_TZCLK+ R270 1 2 LVDS40@ 0_0402_5%
197 198 UMA_TZCLK+ <11>
199 200 LCD_TZCLK+
<14> VGA_TV_CRMA 199 200
201 201 202 202
203 204
205
203
205
204
206 206
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
CRT CONNECTOR
VGA@ JAE_WB3F200VD1R1000~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 15 of 45
5 4 3 2 1
5 4 3 2 1
U26A B:Swap PCICLK7 and PCICLK2 for debug CLK fail issue.
SB600 SB U2
PCICLK0 PCICLK0 <18>
PCICLK1 T2 PCICLK1 <18>
PCICLK2 R419 1 2 22_0402_5%
PCI CLKS
<13> SBSRCCLK J24 PCIE_RCLKP PCICLK2 U1 CLK_PCI_SIO <34>
<13> SBSRCCLK# J25 V2 PCICLK3 R421 1 2 22_0402_5%
PCIE_RCLKN PCICLK3 CLK_PCI_EC <30>
PCICLK4 W3 PCICLK4 <18>
C632 0.1U_0402_16V7K SB_RX0P_C PCICLK5 R136 1 2 22_0402_5%
CPU
AA26 AC1 PCI_AD24
A20M#/SID AD24 PCI_AD25
Y27 FERR# AD25 AH2
ALLOW_LDTSTOP AA25 AC2 PCI_AD26
+1.8VS <11> ALLOW_LDTSTOP STPCLK#/ALLOW_LDTSTP AD26
C AH9 AH1 PCI_AD27 C
CPU_STP#/DPSLP_3V# AD27 PCI_AD28
B24 DPSLP_OD#/GPIO37 AD28 AD2
2 1 ALLOW_LDTSTOP W23 DPRSLPVR AD29 AG2 PCI_AD29
R112 1K_0402_5% AC25 AD1 PCI_AD30
<6> LDT_RST# LDT_RST#/DPRSTP#/PROCHOT# AD30
+3V_SB AG1 PCI_AD31
AD31
PCI INTERFACE
CBE0#/ROMA10 AB9 PCI_C/BE#0 <22>
EC_SWI#
1
RTC
2
2 1 1 2 1 2 +CHGRTC
1 1 R436 120_0402_5% 1
W=20mils C700
C688
2
C250 C251
1 2 SB_32KHI 0.1U_0402_16V4Z 1U_0402_6.3V4Z J4 0.1U_0402_16V4Z
2
2 2 @ JUMP_43X39 2
18P_0402_50V8J Y4
1
1
4 OUT NC 3
R417
1
20M_0603_5% 1 2 Close to SB600 pin E1
IN NC
A A
32.768KHZ_12.5P_1TJS125BJ4A421P
C679
2
SB_32KHO
1 2
18P_0402_50V8J
Security Classification Compal Secret Data
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
SB600-PCI_EXP/PCI/LPC/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 16 of 45
5 4 3 2 1
5 4 3 2 1
U26B
C662 2 0.01U_0402_25V7K SATA_STX_DRX_P0
<21> SATA_STX_C_DRX_P0
C665
1
1 2 0.01U_0402_25V7K SATA_STX_DRX_N0
AH21
AJ21
SATA_TX0+ SB600 SB AB29
<21> SATA_STX_C_DRX_N0 SATA_TX0- IDE_IORDY IDE_SDIORDY <28>
AH18 SATA_TX1+ IDE_IRQ AA28 INT_IRQ15 <28>
AJ18 SATA_TX1- IDE_A0 AA29 IDE_SDA0 <28>
10P_0402_50V8J 2 1 C195 SATA_X1 AH13 AB27
SATA_TX2+ IDE_A1 IDE_SDA1 <28>
AH14 SATA_TX2- IDE_A2 Y28 IDE_SDA2 <28>
1
AJ11 SATA_TX3+ IDE_DACK# AB28 IDE_SDDACK# <28>
Y2 R113 AH11 AC27
SATA_TX3- IDE_DRQ IDE_SDDREQ <28>
D 25MHZ_20P AC29 D
IDE_IOR# IDE_SDIOR# <28>
SERIAL ATA
10M_0402_5% AJ20 AC28
<21> SATA_DTX_C_SRX_P0 IDE_SDIOW# <28>
2
SATA_RX0+ IDE_IOW#
<21> SATA_DTX_C_SRX_N0 AH20 W28 IDE_SDCS1# <28>
2
10P_0402_50V8J 2 SATA_RX0- IDE_CS1#
1 C186 SATA_X2 AJ17 SATA_RX1+ IDE_CS3# W27 IDE_SDCS3# <28>
AH17 SATA_RX1- IDE_SDD[0..15] <28>
AJ16 AD28 IDE_SDD0
SATA_RX2+ IDE_D0/GPIO15 IDE_SDD1
AH16 SATA_RX2- IDE_D1/GPIO16 AD26
AJ13 AE29 IDE_SDD2
SATA_RX3+ IDE_D2/GPIO17 IDE_SDD3
AH12 SATA_RX3- IDE_D3/GPIO18 AF27
AG29 IDE_SDD4
SATA_CAL IDE_D4/GPIO19 IDE_SDD5
2 1 AF12 SATA_CAL IDE_D5/GPIO20 AH28
P-ATA 66/100
R118 1K_0402_1% AJ28 IDE_SDD6 B:1.Add PU R479 for BT_DET#
IDE_D6/GPIO21 +3VS
1 2 NB_RST#_R B:Chg. name to HDD_LED# and SATA_X1 AD16 SATA_X1 IDE_D7/GPIO22 AJ27 IDE_SDD7 2.Chg. BT_DET# from GPIO0 to GPIO51.
R119 8.2K_0402_5% dis-connect with EC bec'z AH27 IDE_SDD8
SATA_X2 IDE_D8/GPIO23 IDE_SDD9 BT_DET# 10K_0402_5% 2 R479
chg. to KB926. AD18 SATA_X2 IDE_D9/GPIO24 AG27 1
1 2 EC_RSMRST# R120
+3VS 1 2 10K_0402_5% IDE_D10/GPIO25 AG28 IDE_SDD10
R134 2.2K_0402_5% AC12 AF28 IDE_SDD11
<32> HDD_LED# SATA_ACT#/GPIO67 IDE_D11/GPIO26
AF29 IDE_SDD12
IDE_D12/GPIO27
OSC / RST
AE28 IDE_SDD13
NB_RST#_R IDE_D13/GPIO28 IDE_SDD14 +3VS
AG10 A_RST# IDE_D14/GPIO29 AD25
EC_RSMRST# E2 AD29 IDE_SDD15
<30> EC_RSMRST# RSMRST# IDE_D15/GPIO30
<13> SB_OSC_INT B23 14M_OSC 1 2
J3 R128 5IN1@ 1K_0402_5%
+3VALW SPI_DI/GPIO12 5IN1_EN
MP:Add U35 and C740, reserve C740 SPI_DO/GPIO11 J6 1 2 0: 5IN1 Disable
USB_48M_EXT R466 100K_0402_5%
SPI ROM
R1178 for LAN Leakage A17 USBCLK SPI_CLK/GPIO47 G3 1: 5IN1 Enable
problem. 1 2 SPI_HOLD#/GPIO31 G2 B:Chg. name to 5IN1_EN
2 1 USB_RCOMP A14 USB_RCOMP SPI_CS#/GPIO32 G6
5
USB INTERFACE
<29> USBP7+ E14 USB_HSDP7+
A:ISKAA-Add for CIR floating casue S3 shut down issue
<29> USBP7- D14 USB_HSDM7- FANIN0/GPIO50 N3 B:Chg. name to CIR_EN#
1 2 <29> USBP6+ G14 P2 BT_DET#
USB_HSDP6+ FANIN1/GPIO51 BT_DET# <29>
R1178 0_0402_5% H14 W4
<29> USBP6- USB_HSDM6- FANIN2/GPIO52 SPK_SEL <26>
@ <29> USBP5+ D16 USB_HSDP5+
+3V_SB <29> USBP5- E16 USB_HSDM5- TEMP_COMM P5
<29> USBP4+ D18 P7 5IN1_EN
USB_48M_EXT USB_HSDP4+ TEMPIN0/GPIO61 CIR_EN#
<13> USBCLK_EXT 1 2 <29> USBP4- E18 USB_HSDM4- TEMPIN1/GPIO62 P8 B:Move SB_INT_FLASH_SEL to GPIO63 bec'z
MBC1608121YZF_0603
R115 0_0402_5% <24> USBP3+ G16 T8 GPIO1 is not tri-state pin in SB600
USB_HSDP3+ TEMPIN2/GPIO63 SB_INT_FLASH_SEL <31>
<24> USBP3- H16 USB_HSDM3- TEMPIN3/TALERT#/GPIO64 T7 EC_THERM# <30>
HW MONITOR
1
L23 H18 V5
<29> USBP2- USB_HSDM2- VIN0/GPIO53
R130 <29> USBP1+ D19 L7
@ 10K_0402_5% USB_HSDP1+ VIN1/GPIO54
<29> USBP1- E19 USB_HSDM1- VIN2/GPIO55 M8
<29> USBP0+ G19 USB_HSDP0+ VIN3/GPIO56 V6
X1 @ 48MHZ_4P_FN4800002 <29> USBP0- H19 M6
2
USB OC
@ 0.1U_0402_16V4Z C217 C8 N2 AZ_BITCLK 33_0402_5% 2 1 R158 AZ_BITCLK_HD <26>
2 <30> EC_LID_OUT# USB_OC3#/GPM3# AZ_BITCLK
@ 12P_0402_50V8J AZ_SDOUT
AZALIA
A6 USB_OC4#/GPM4# AZ_SDOUT M2
1 AZ_BITCLK MDC@33_0402_5% 2
B:Chg. to SPI, DEL B6 USB_OC5#/DDR3_RST#/GPM5# AZ_SDIN3/GPIO46 K2 AZ_SDIN3_HD <26> 1 R160 AZ_BITCLK_MD <28>
B A Z_SYNC B
EC_FLASH# from GPM1# B4 USB_OC6#/GEVENT6# AZ_SYNC L3
C4 K3 AZ_RST#
<30> EC_SMI# USB_OC7#/GEVENT7# AZ_RST#
C5 33_0402_5% 2 1 R161 AZ_SDOUT_HD <26>
USB_OC8#/AZ_DOCK_RST#/GPM8#
C6 USB_OC9#/SLP_S2/GPM9# AC_BITCLK/GPIO38 L1
L2 AZ_SDOUT MDC@33_0402_5% 2 1 R163 AZ_SDOUT_MD <28>
AC_SDOUT/GPIO39 AC97_SDOUT <18>
A C97
A27 SSMUXSEL/SATA_IS3#/GPIO0 ACZ_SDIN0/GPIO42 L4 AZ_SDIN0_MD <28>
B:Del GPIO1 bec'z not tri-state pin for app.. A26 ROM_CS#/GPIO1 ACZ_SDIN1/GPIO43 J2
<27> SB_SPKR B26 J4 33_0402_5% 2 1 R155 AZ_SYNC_HD <26>
SPKR/GPIO2 ACZ_SDIN2/GPIO44
B27 SMARTVOLT/SATA_IS2#/GPIO4 AC_SYNC/GPIO40 M3
D23 L5 A Z_SYNC MDC@33_0402_5% 2 1 R157 AZ_SYNC_MD <28>
SHUTDOWN#/GPIO5 AC_RST#/GPIO45
GPIO/ SMBUS
SIDERST# B29
+3VS <28> SIDERST# GHI#/SATA_IS1#/GPIO6
A23 WD_PWRGD/GPIO7
C26 E23 33_0402_5% 2 1 R152 AZ_RST_HD# <26>
DDC1_SDA/GPIO8 NC1
D26 DDC1_SCL/GPIO9 NC2 AC21
C28 AD7 AZ_RST# MDC@33_0402_5% 2 1 R154 AZ_RST_MD# <28>
R409 SATA_IS0#/GPIO10 NC3
1 2 10K_0402_5% SIDERST# A4 LLB#/GPIO66 NC4 AE7
NC5 AA4
R410 1 2 2.2K_0402_5% SMB_CK_CLK0 <8,9,13,24,28> SMB_CK_CLK0 SMB_CK_CLK0 C27 T4 B:Del HDMI audio fun. bec'z remove SiI1932.
SMB_CK_DAT0 SCL0/GPOC0# NC6
<8,9,13,24,28> SMB_CK_DAT0 B28 SDA0/GPOC1# NC7 D4
R408 1 2 2.2K_0402_5% SMB_CK_DAT0 AB19
SBR1@ NC8
C3 SCL1/GPOC2#
F3 AZ_RST# 2 1
SDA1/GPOC3# 10K_0402_5% R140
A A
D D
Standard Straps
+3VS +3VS +3VS +3VS +3VS Debug Straps
1
1
R418 R139 R420 R146 R145
<16,22> PCI_AD28
@ 2.2K_0402_5% @ 10K_0402_5% 10K_0402_5% 10K_0402_5% @ 10K_0402_5%
<16,22> PCI_AD27
<16,22> PCI_AD26
<16,22> PCI_AD25
2
2
<17> AC97_SDOUT <16,22> PCI_AD24
<16> PCICLK4
1
<16> PCICLK6
R149 R142 R151 R138 R150
<16> PCICLK1
@ 2.2K_0402_5% @ 2.2K_0402_5% @ 2.2K_0402_5% @ 2.2K_0402_5% @ 2.2K_0402_5%
<16> PCICLK0
1
2
R133 R147 R144
10K_0402_5% @ 10K_0402_5% 10K_0402_5%
2
2
C C
B Un-Used Inputs Setting--GPIO pins Un-Used Inputs Setting--GPM pins Un-Used Inputs Setting--GPM pins B
GPIO4/SMARTVOLT/SATA_IS2# Config. GPIO to Output Mode. GPIO56/VIN3 Config. GPIO to Output Mode. GPM5#/DDR3_RST#/USB_OC5# Config. for internal PU.
GPIO5/SHUTDOWN# Config. GPIO to Output Mode. GPIO57/VIN4 Config. GPIO to Output Mode. GEVENT5#/S3_STATE Config. for internal PU.
GPIO7/WD_PWRGD Config. GPIO to Output Mode. GPIO58/VIN5 Config. GPIO to Output Mode.
GPIO8/DDC1_SDA Config. GPIO to Output Mode. GPIO59/VIN6 Config. GPIO to Output Mode.
GPIO9/DDC1_SCL Config. GPIO to Output Mode. GPIO60/VIN7 Config. GPIO to Output Mode.
GPIO10/SATA_IS0# Config. GPIO to Output Mode. GPIO61/TEMPIN0 Config. GPIO to Output Mode.
GPIO51/FANIN1 Config. GPIO to Output Mode. GPOC2#/SCL1 Config. GPIO to Output Mode.
A A
GPIO52/FANIN2 Config. GPIO to Output Mode. GPOC3#/SDA1 Config. GPIO to Output Mode.
+
C190 1 2 1U_0402_6.3V4Z SB_VDD_33=150mA
A28
C29
VDDQ_2 SB600 SB A20
+PLLVDD_ATA AD14
AJ10
PLLVDD_SATA_1 AVSS_SATA_1 AB14
AB16
C227 1U_0402_6.3V4Z VDDQ_3 VSS_2 L22 PLLVDD_SATA_2 AVSS_SATA_2
1 2 D24 A21 AB18
C193 1 2 1U_0402_6.3V4Z L9
VDDQ_4
VDDQ_5
POWER VSS_3
VSS_4 A29 +3VS 1 2 +XTLVDD_ATA +XTLVDD_ATA AC16 XTLVDD_SATA
AVSS_SATA_3
AVSS_SATA_4 AC14
C200 1 2 1U_0402_6.3V4Z L21 B1 MBC1608121YZF_0603 SB_AVDDC_33=5mA AC18
C240 1U_0402_6.3V4Z VDDQ_6 VSS_5 C209 AVSS_SATA_5
1 2 M5 VDDQ_7 VSS_6 B7 2 1 1U_0402_6.3V4Z AVSS_SATA_6 AC19
+
W29 VDDQ_15 VSS_14 F23 2 1 AG23 AVDD_SATA_8 AVSS_SATA_14 AF16
L20 AA12 G1 C668 22U_A_4VM AH22 AF18
VDDQ_16 VSS_15 C661 AVDD_SATA_9 AVSS_SATA_15
+1.2V_HT 1 2 +1.2VS_SB_VDD AA16 VDDQ_17 VSS_16 J1 1 2 1U_0402_6.3V4Z AH23 AVDD_SATA_10 AVSS_SATA_16 AG11
MBK2012221YZF 0805 AA19 J8 C197 1 2 1U_0402_6.3V4Z AJ12 AG12
VDDQ_18 VSS_17 C194 AVDD_SATA_11 AVSS_SATA_17
AC4 VDDQ_19 VSS_18 L6 1 2 0.1U_0402_16V4Z AJ14 AVDD_SATA_12 AVSS_SATA_18 AG13
AC23 L8 C206 1 2 0.1U_0402_16V4Z AJ19 AG14
VDDQ_20 VSS_19 AVDD_SATA_13 AVSS_SATA_19
+
+
C214 1 2 0.1U_0402_16V4Z P21 2 1 A9
VSS_28 C669 22U_A_4VM AVDDRX_0
+1.2VS_SB_VDD M13 VDD_1 VSS_29 R12 B10 AVDDRX_1
M17 R15 C224 1 2 1U_0402_6.3V4Z B12 A16
VDD_2 VSS_30 C228 1U_0402_6.3V4Z AVDDRX_2 AVSS_USB_1
SB_VDD_12=500mA N12 VDD_3 VSS_31 R18 1 2 B14 AVDDRX_3 AVSS_USB_2 C9
Core PWR
N15 T6 C211 1 2 1U_0402_6.3V4Z B17 C10
VDD_4 VSS_32 C212 0.1U_0402_16V4Z AVDDRX_4 AVSS_USB_3
N18 VDD_5 VSS_33 T9 1 2 AVSS_USB_4 C11
R13 U13 C673 1 2 0.1U_0402_16V4Z SB_AVDDC_33=15mA C12
VDD_6 VSS_34 C675 0.1U_0402_16V4Z AVSS_USB_5
R17 VDD_7 VSS_35 U17 1 2 +3V_SB A12 AVDDC AVSS_USB_6 C13
+3V_SB U12 V3 C14
VDD_8 VSS_36 AVSS_USB_7
U15 VDD_9 VSS_37 V8 A13 AVSSC AVSS_USB_8 C16
+
Special PWR/GND
C682 2 1 0.1U_0402_16V4Z AE27 C666 2 1 1U_0402_6.3V4Z 1 SB_CPU_PWR=10mA G11
C242 @ 10U_0805_10V4Z VSS_53 C667 1U_0402_6.3V4Z AVSS_USB_24
2 1 VSS_54 AG6 2 1 +V5_VREF AE11 V5_VREF AVSS_USB_25 G21
+PCIE_VDDR F27 AJ1 C201 2 1 1U_0402_6.3V4Z C188 SB_V5_VREF_5=5mA H11
PCIE_VDDR_1 VSS_55 0.1U_0402_16V4Z AVSS_USB_26
F28 AJ25 A24 H21
PCIE_VDDR_2 VSS_56 2 +3.3V_AVDDCK
SB_AVDDCK_33=10mA AVDDCK_3.3V AVSS_USB_27
SB_PCIEPVDDR_12=450mA F29 PCIE_VDDR_3 VSS_57 AJ29 AVSS_USB_28 J11
G26 PCIE_VDDR_4 +1.2V_AVDDCK A22 AVDDCK_1.2V AVSS_USB_29 J12
PCIE Analog PWR
GND to B22
1
+HDMI_5V_OUT
MP:Update D10 to meet HDMI. R429 R431 R430
HDMI@ HDMI@ @ @
D10 F1 1A_6VDC_MINISMDC110 2.2K_0402_5% 24K_0402_5% 24K_0402_5%
+5VS 2 1 2 1 +HDMI_5V_OUT
1
J1
RB491D_SOT23 R1176 R1177
D HDMI@ 1 2 HDMI@ HDMI@ D
1 2 VGA_HPD 19.1K_0402_1% 19.1K_0402_1%
1 <15> VGA_HPD
2
G
@ JUMP_43X79 C270
2
HDMI@ Q134
B:Need to open solder door 0.1U_0402_16V4Z <15> VGA_DVI_SDATA VGA_DVI_SDATA 3 1 HDMI_SDATA
2
D
of J1 for HDMI fun. PWR.
2N7002_SOT23-3
2
G
HDMI@
Q135
VGA_DVI_SCLK 3 1 HDMI_SCLK
<15> VGA_DVI_SCLK
D
2N7002_SOT23-3 C:Chg. PN to SB770020010.
B:1.Level shift circuit for HDMI. HDMI@
2.Reserve DDC PU Resistor and HPD PU Resistor.
HDMI Connector
VGA_DVI_TXD1- 1 2 R440 HDMI_R_D1- VGA_DVI_TXC- 1 2 R432 HDMI_R_CK-
<15> VGA_DVI_TXD1- <15> VGA_DVI_TXC-
0_0402_5% 0_0402_5%
@ @
L68 L66
1 1 2 2 1 1 2 2
JP35
PreMP:Change to common choke for EMI HDMI_HPD 19 HP_DET
4 4 3 3 4 4 3 3 +HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
HDMI@ WCM-2012-900T_0805 HDMI@ WCM-2012-900T_0805 HDMI_SDATA 16
VGA_DVI_TXD1+ SDA
<15> VGA_DVI_TXD1+ 1 2 R441 HDMI_R_D1+
<15> VGA_DVI_TXC+
VGA_DVI_TXC+ 1 2 R434 HDMI_R_CK+ HDMI_SCLK 15 SCL
C 0_0402_5% 0_0402_5% 14 C
Reserved
@ @ 13 CEC
HDMI_R_CK- 12 20
CK- GND
11 CK_shield GND 21
VGA_DVI_TXD2- 1 2 R442 HDMI_R_D2- VGA_DVI_TXD0- 1 2 R435 HDMI_R_D0- HDMI_R_CK+ 10 22
<15> VGA_DVI_TXD2- <15> VGA_DVI_TXD0- CK+ GND
0_0402_5% 0_0402_5% HDMI_R_D0- 9 23
D0- GND
@ @ 8 D0_shield
L69 L67 HDMI_R_D0+ 7
HDMI_R_D1- D0+
1 1 2 2 1 1 2 2 6 D1-
5 D1_shield
PreMP:Change to common choke for EMI HDMI_R_D1+ 4
HDMI_R_D2- D1+
4 4 3 3 4 4 3 3 3 D2-
2 D2_shield
HDMI@ WCM-2012-900T_0805 HDMI@ WCM-2012-900T_0805 HDMI_R_D2+ 1
VGA_DVI_TXD2+ D2+
<15> VGA_DVI_TXD2+ 1 2 R444 HDMI_R_D2+
<15> VGA_DVI_TXD0+
VGA_DVI_TXD0+ 1 2 R438 HDMI_R_D0+
0_0402_5% 0_0402_5% TYCO_1939864-1
@ @ HDMI@
+HDMI_5V_OUT
C739 2
0.1U_0402_16V4Z HDMI_HPD
HDMI@
5
1
B 1 B
P
OE#
2
2 4 VGA_HPD R425 2 C694
A Y 100K_0402_5% 0.1U_0402_16V4Z
G
U34 HDMI@ HDMI@
SN74AHCT1G125GW_SOT353-5
3
HDMI@ 1
1
MP:Update HDMI Hot Plug DET circuit, to add U34, C739.
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SiI1392&HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IALAA-Minnesota10A LA3631P
Date: Monday, May 14, 2007 Sheet 20 of 45
5 4 3 2 1
5 4 3 2 1
+3VS 8
V33 +3VS
V33 9
V33 10
GND 11
1 1 1 1 GND 12
C697 C691 C693 C696 13
GND
V5 14 +5VS
@ 10U_0805_10V4Z @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z 15
2 2 2 2 V5
V5 16
GND 17
Reserved 18
GND 19
V12 20
24 GND V12 21
23 GND V12 22
OCTEK_SAT-22SO1G_RV
C C
B B
A A
+3VS +AVDD_7412
+3VS
MBK1608301YZF_0603 MBK1608301YZF_0603 +3VS
2 1 0.1U_0402_16V4Z 0.01U_0402_25V4Z +CB_VDDPLL33 0.01U_0402_25V4Z 1 2
0.1U_0402_16V4Z
2 2 2 2 2
10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2
0.1U_0402_16V4Z PCI8412:5IN1 + 1394 + CardBus C288
U15
U19
P13
P14
P15
K19
W8
1U_0603_10V4Z
K1
P1
U11B 2 2 2 2 1
0.1U_0402_16V4Z 0.01U_0402_25V4Z
VCCP
VCCP
AVDD_33
AVDD_33
AVDD_33
VDDPLL_33
VDDPLL_15
VR_PORT
VR_PORT
M1 PCI_AD31
AD31 PCI_AD30 MSBS_SDCMD_SMWE#
AD30 M2 1 2
M3 PCI_AD29 R176 100K_0402_5%
AD29 PCI_AD28 5IN1@
AD28 M6
MC_PWRON# C8 M5 PCI_AD27 SMRE 1 2
SM_RB F8
MC_PWR_CTRL_0
MC_PWR_CTRL_1/SM_R/B#
AD27
AD26 N1 PCI_AD26 5 IN 1 LED R168 100K_0402_5%
N2 PCI_AD25 5IN1@
AD25 PCI_AD24 +5VS SDWP#_SMCE#
AD24 N3 1 2
P3 PCI_AD23 R187 100K_0402_5%
SD_CD# AD23 PCI_AD22 5IN1@
E9 SD_CD# AD22 R1
1
MS_CD# A8 R2 PCI_AD21 PCI_AD[0..31] SM_RB 1 2
MS_CD# AD21 PCI_AD[0..31] <16,18>
B8 P5 PCI_AD20 R254 R167 22K_0402_5%
SM_CD# AD20 PCI_AD19 5IN1@ 5IN1@
AD19 R3
SDCLK 2 1 T1 PCI_AD18 120_0402_5%
5IN1@ R213 22_0402_5% AD18 PCI_AD17
T2
2 2
MSCLK MSCLK_SDCLK_SMELWP# AD17 PCI_AD16
2 1 A7 MS_CLK/SD_CLK/SM_EL_WP# AD16 W4
5IN1@ R214 22_0402_5% MSBS_SDCMD_SMWE# E8 W7 PCI_AD15
SMELWP# MSD3_SDD3_SMD3 MS_BS/SD_CMD/SM_WE# AD15 PCI_AD14 D24
2 1 B6 MS_DATA3/SD_DAT3/SM_D3 AD14 R8
5IN1@ R215 22_0402_5% MSD2_SDD2_SMD2 A6 U8 PCI_AD13 5IN1@
MSD1_SDD1_SMD1 C7
MS_DATA2/SD_DAT2/SM_D2
MS_DATA1/SD_DAT1/SM_D1
AD13
AD12 V8 PCI_AD12 HT-191NB_BLUE_0603 +3VS 5 In 1 Card Power Switch
MSD0_SDD0_SMD0 B7 W9 PCI_AD11 C:Chg. Q32 and Q23 PN to
MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD11 PCI_AD10 +VCC_5IN1
V9 SB770020010.
1 1
AD10 PCI_AD9
AD9 U9
2
C PCI_AD8 D C
place near Chip 8412 AD8 R9
V10 PCI_AD7 5IN1_LED 2 Q32 R182 U9
SMRE AD7 PCI_AD6 G 5IN1@ 10K_0402_5%
A4 SD_CLK/SM_RE# AD6 U10 1 GND OUT 8
2
CLK_48M_CB SDCMD_SMALE C5 R10 PCI_AD5 S 2N7002_SOT23-3 2 7
3
SDD0_SMD4 SD_CMD/SM_ALE AD5 PCI_AD4 R225 IN OUT
C6 W11 3 6
1
SD_DAT0/SM_D4 AD4 IN OUT
2
1
SDWP#_SMCE# SD_DAT3/SM_D7 AD1 PCI_AD0 5IN1@ 5IN1@ 5IN1@
request. E7 SD_WP/SM_CE# AD0 R11 5IN1@
0.1U_0402_16V4Z 2
1
1 G5 4.7U_0805_10V4Z
SC_PWR_CTRL 1U_0603_10V4Z
C/BE3# P2 PCI_C/BE#3 <16>
C320 SMCLE B4 U5
SM_CLE C/BE2# PCI_C/BE#2 <16> +5VS
22P_0402_50V8J XD_CD# A3 V7
2 XD_CD#/SM_PHYS_WP#
PCI7412 C/BE1#
C/BE0# W10
PCI_C/BE#1
PCI_C/BE#0
<16>
<16>
2
+VCC_5IN1
U7 PCI_PAR <16> R195 CLK_PCI_CB
R173 1 PAR
2 1K_0402_1% P12 TEST0 FRAME# R6 PCI_FRAME# <16> 10K_0402_5%
1
CLK_48M_CB F1 W5 PCI_TRDY# <16> 8412@
<13> CLK_48M_CB CLK_48 TRDY#
+3VS R181 1 2 4.7K_0402_5%
P17 V5 PCI_IRDY# <16> R189 R188
1
PHY_TEST_MA IRDY# @ 10_0402_5% 5IN1@
STOP# V6 PCI_STOP# <16>
56.2_0402_1%
56.2_0402_1%
1U_0402_6.3V4Z
2 U6 DEVICE_ID 470_0805_5%
DEVSEL# PCI_DEVSEL# <16>
1
1 2
IDSEL
2
1394@ R177 R178 R186 6.34K_0402_1% R7 100_0402_5% 1
PERR# PCI_PERR# <16> D
1394@ 1394@ 1 2 T18 W6 R194 Q23
1 R0 SERR# PCI_SERR# <16>
T19 L3 100_0402_5% C309 MC_PWRON# 2
R1 REQ# PCI_REQ#2 <16>
JP37 XTPBIAS0 R13 L2 8402@ @ 22P_0402_50V8J 5IN1@ G
PCI_GNT#2 <16>
2
3
GND TPA+ XTPA0- TPA0P CLK_PCI_CB
7 GND TPA- 3 W14 TPA0N PCLK L1 CLK_PCI_CB <16>
6 2 XTPB0+ V13 K3
GND TPB+ TPB0P PRST# PCIRST# <6,16>
5 1 XTPB0- W13 K5
GND TPB- TPB0N GRST#
56.2_0402_1%
56.2_0402_1%
1 2 W17 L5
TPBIAS1 RI_OUT#/PME#
5 in 1 CardReader Conn.
1
K2 SDCMD_SMALE 29
VR_EN# C738 1 XD-ALE
CLOSE TO CHIP 222P_0402_50V8J XD_CD# 23 XD-CD MS-SCLK 8 MSCLK
R174 1 2 CPS SM_RB 25 XD-R/B MS-DATA0 4 MSD0_SDD0_SMD0
2
R17
SD-GND
42 1
GND
GND
18P_0402_50V8J C304 X_IN N.C. MS-GND
18 N.C. MS-GND 10
TAITW_R007-530-L3
47
48
5IN1@ B:IALAA only to add Pin47
A
and Pin48 to link to GND. A
5 4 3 2 1
5 4 3 2 1
A15
P10
F12
F14
VPPD1
L14
J19
J14
P6
P8
F6
F9
L6
J6
U11A C354 3
PCMCIA@ 0.1U_0402_16V4Z 3.3V
4 8
VCCB
VCCB
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3.3V OC
SHDN
S1_D10 C10 C364
GND
S1_D9 CAD31/D10 @ 4.7U_0805_10V4Z
A10 CAD30/D9
2
S1_D1 F11 B9 VPPD1 B:Set to "@".
S1_D8 CAD29/D1 DATA/VD2/VPPD1 VCCD0# PCMCIA@
E11 A9
16
S1_D0 CAD28/D8 CLOCK/VD1/VCCD0# VPPD0 R229 TPS2211AIDBR_SSOP16
C11 CAD27/D0 LATCH/VD3/VPPD0 C9
S1_A0 B13 PCMCIA@
S1_A1 CAD26/A0 10K_0402_5%
C13
1
S1_A2 CAD25/A1
A14 CAD24/A2
S1_A3 B14
S1_A4 CAD23/A3
B15 CAD22/A4
S1_A5 E14
S1_A6 CAD21/A5
A16 CAD20/A6
S1_A25 D19
S1_A7 CAD19/A25
E17 CAD18/A7 RSVD/D2 B10 S1_D2
S1_A24 F15 C4 VCCD1#
S1_A17 CAD17/A24 RSVD/VD0/VCCD1#
H19 CAD16/A17 RSVD D1
2
S1_IOWR# J17 E1
S1_A9 CAD15/IOWR# RSVD +3VS R217 JP21
J15 CAD14/A9 RSVD E2
S1_IORD# J18 E3 PCMCIA@ 1 2 S1_D3
S1_A11 CAD13/IORD# RSVD 43K_0402_5% S1_D4 GND DATA3 S1_D5
K15 CAD12/A11 RSVD F2 3 DATA4 DATA5 4
C S1_OE# S1_D6 S1_D7 C
K17 F3 5 6
1
S1_CE2# CAD11/OE# RSVD R216 0_0402_5% S1_CE1# DATA6 DATA7 S1_A10
K18 CAD10/CE2# RSVD F5 7 CE1# ADD10 8
S1_A10 L15 G6 2 1 S1_OE# 9 10 S1_A11
S1_D15 CAD9/A10 RSVD OE# ADD11
L18 CAD8/D15 RSVD H17 S1_A18 S1_A9 11 ADD9 ADD8 12 S1_A8
S1_D7 L19 M19 S1_D14 S1_A13 13 14 S1_A14
S1_D13 CAD7/D7 RSVD S1_WE# ADD13 ADD14 S1_RDY#
M17 CAD6/D13 15 WE# READY 16
S1_D6 M18 +S1_VCC 17 18 +S1_VPP
CAD5/D6 +S1_VCC VCC VPP +S1_VPP
S1_D12 N19 A2 S1_A16_C 19 20 S1_A15
S1_D5 CAD4/D12 NC S1_A12 ADD16 ADD15 S1_A7
M15 CAD3/D5 NC A17 21 ADD12 ADD7 22
S1_D11 N17 A18 S1_A6 23 24 S1_A5
S1_D4 CAD2/D11 NC S1_A4 ADD6 ADD5 S1_A3
N18 CAD1/D4 NC B1 25 ADD4 ADD3 26
S1_D3 P19 B2 S1_A2 27 28 S1_A1
CAD0/D3 NC S1_A0 ADD2 ADD1 S1_D0
B3 29 30
NC
B17 +S1_VCC Near to PCMCIA slot. S1_D1 31
ADD0 DATA0
32 S1_D2
S1_REG#
S1_A12
E13
E18
CC/BE3#/REG# PCI 7412 NC
NC B18
B19
S1_WP 33
35
DATA1 DATA2
WP GND 34
36 S1_CD1#
S1_A8 CC/BE2#/A12 NC S1_D11 GND CD1# S1_D12
H18 CC/BE1#/A8 NC C1 1 1 37 DATA11 DATA12 38
S1_CE1# L17 C2 C260 C259 S1_D13 39 40 S1_D14
CC/BE0#/CE1# NC PCMCIA@ PCMCIA@ S1_D15 DATA13 DATA14 S1_CE2#
NC C3 41 DATA15 CE2# 42
S1_A13 H14 C16 10U_0805_10V4Z 0.1U_0402_16V4Z S1_VS1 43 44 S1_IORD#
S1_A23 CPAR/A13 NC 2 2 S1_IOWR# VS1# IORD# S1_A17
E19 CFRAME#/A23 NC C17 45 IOWR# ADD17 46
S1_A22 G15 C18 S1_A18 47 48 S1_A19
S1_A15 CTRDY#/A22 NC S1_A20 ADD18 ADD19 S1_A21
F17 CIRDY#/A15 NC C19 49 ADD20 ADD21 50
S1_A20 G18 D2 +S1_VCC 51 52 +S1_VPP
CSTOP#/A20 NC +S1_VCC VCC VPP +S1_VPP
S1_A21 F19 D3 S1_A22 53 54 S1_A23
S1_A19 CDEVSEL#/A21 NC S1_A24 ADD22 ADD23 S1_A25
H15 CBLOCK#/A19 NC D17 55 ADD24 ADD25 56
S1_A14 G19 D18 S1_VS2 57 58 S1_RST
S1_WAIT# CPERR#/A14 NC +S1_VPP S1_WAIT# VS2# RESET S1_INPACK#
C12 CSERR#/WAIT# NC E5 59 WAIT# INPACK# 60
S1_INPACK# C14 N14 S1_REG# 61 62 S1_BVD2
S1_WE# CREQ#/INPACK# NC S1_BVD1 REG# BVD2 S1_D8
G17 CGNT#/WE# NC P18 63 BVD1 DATA8 64
S1_BVD1 A12 T3 1 1 S1_D9 65 66 S1_D10
R202 S1_WP CSTSCHG/BVD1(STSCHG#/RI#) NC C266 C265 S1_CD2# DATA9 DATA10
A11 CCLKRUN#/WP(IOIS16#) NC T17 67 CD2# GND 68
B S1_A16_C 1 S1_A16 PCMCIA@ PCMCIA@ B
2 F18 CCLK/A16 NC U1 69 GND GND 70
PCMCIA@ 33_0402_5% S1_RDY# E12 U2 10U_0805_10V4Z 0.1U_0402_16V4Z 71 72
CINT#/READY(IREQ#) NC 2 2 GND GND
NC U3 73 GND GND 74
S1_RST C15 U4 75 76
CRST#/RESET NC GND GND
NC U12 77 GND GND 78
S1_BVD2 B12 U16 79 80
CAUDIO/BVD2(SPKR#) NC GND GND
NC U17 81 GND GND 82
S1_CD1# N15 U18 83 84
S1_CD2# CCD1#/CD1# NC GND GND
B11 CCD2#/CD2# NC V1 85 GND GND 86
S1_VS1 A13 V2 87 88
S1_VS2 CVS1/VS1# NC GND GND
B16 CVS2/VS2# NC V3
V4 PCMCIA@
NC FOX_WZ21131-P4-8F_LT
NC V12
E10 A_USB_EN# NC V17
2 1 S1_CD1# V18 C:Symol with wrong Layout Symbol. Update Footprint
C314 PCMCIA@ NC
NC V19 "DC000003D00 (FOX_1CA41121-TC-4F_68P_LT)"
100P_0402_25V8K W2
NC
NC W3
2 1 S1_CD2# W12
C342 PCMCIA@ NC
W18
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
100P_0402_25V8K NC
8412@ PCI7412ZHK_PBGA257
F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9
A A
Security Classification
2007/5/4
Compal Secret Data
2008/5/4 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TI PCI8412/CB socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 23 of 45
5 4 3 2 1
+3VALW_DVD +3VS
1
25 26 R485 @ 0_0603_5% Small/B already had ESD IC R265
<11> PCIE_MRX_C_DVDTX_P0 25 26 3G@
27 28 3G@
27 28 R278 @ 0_0402_5% SMB_CK_CLK0 4.7K_0402_5% JP1
29 29 30 30 SMB_CK_CLK0 <8,9,13,17,28>
<11> PCIE_MTX_C_DVDRX_N0 31 32 R275 @ 0_0402_5% SMB_CK_DAT0 SMB_CK_DAT0 <8,9,13,17,28> 8
31 32 GND
<11> PCIE_MTX_C_DVDRX_P0 33 34 7
2
33 34 +UIM_PWR GND
35 35 36 36 USBP8- <17> +UIM_PWR 6 6
37 38 USBP8+ <17> UIM_RESET 5
37 38 UIM_CLK 5
+3VS 39 39 40 40 MP:Swap USB2+/- and USB8+/- for 1 4 4
41 41 42 42 3G_LED# <32> CAMERA problem. 3 3
43 44 C388 2
43 44 3G@ 0.1U_0402_16V4Z UIM_DATA 2
45 45 46 46 1 1
2
47 47 48 48
49 49 50 50
51 52 ACES_85201-06051
51 52
53 GND1 GND2 54
FOX_AS0B226-S40N-7F
3G@
+3VS_WLAN 1
R294
2
0_1206_5%
Kill SWITCH
1 1 WLAN@ 1 1 1 +3VALW
C461 C543 C495 C469 C386
WLAN@ WLAN@ C467 WLAN@ WLAN@ C487 WLAN@
0.01U_0402_25V4Z 0.1U_0402_16V4Z WLAN@ 0.01U_0402_25V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 4.7U_0805_10V4Z 2 2 2 +3VALW
WLAN@
2
D14
@ DAN217_SC59
2
SW5 R246
5 100K_0402_5%
1
G2
G1 4
+3V_WLAN +1.5VS +3VS_WLAN
1
A: For WLAN Wake up event.
JP7 3
PCIE_WAKE# PCIE_WAKE# 3
1 2 <30> PCIE_WAKE# 1 1 2 2 2 2 KILL_SW# <30>
R323 100K_0402_5% 3 4 1
<29> WLAN_BT_DATA 3 4 1
<29> WLAN_BT_CLK 5 5 6 6
7 8 1BS003-1210L_3P
<13> CLKREQ_WLAN# 7 8
9 10 WLAN@
9 10
<13> CLK_WLAN# 11 11 12 12
<13> CLK_WLAN 13 13 14 14
15 16 +3V_WLAN
15 16
17 17 18 18
19 20 XMIT_OFF# C387 WLAN@ 0.1U_0402_16V4Z
19 20 NB_RST#
21 21 22 22 NB_RST# <11,15,17,25,28,30,34> 1 2
<10> PCIE_MRX_C_WLANTX_N3 23 23 24 24 +3V_WLAN
<10> PCIE_MRX_C_WLANTX_P3 25 25 26 26
5
27 27 28 28
29 30 SMB_CK_CLK0 2 D25
P
29 30 <30> WL_OFF# B
31 32 SMB_CK_DAT0 4 3G_OFF# 1 2 XMIT_OFF#
<10> PCIE_MTX_C_WLANRX_N3 31 32 Y
33 34 KILL_SW# 1
<10> PCIE_MTX_C_WLANRX_P3 33 34 A
G
35 36 USBP3- <17> WLAN@ CH751H-40PT_SOD323-2
35 36 U15
37 38 USBP3+ <17>
3
37 38
39 39 40 40 WLAN@ NC7SZ08P5X_NL_SC70-5
41 41 42 42 A:Add USB I/F with WLAN conn.,
43 43 44 44 reserve to support Realtek WLAN.
45 45 46 46
47 47 48 48
49 49 50 50
51 51 52 52
53 GND1 GND2 54
FOX_AS0B226-S40N-7F
WLAN@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI PCI SLOT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 24 of 45
5 4 3 2 1
1 2 +3V_LAN
R25 +3V_LAN
3.6K_0402_5%
U4
U2
C92 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P2 29 45 4 5 2
<10> PCIE_MRX_C_LANTX_P2 HSOP EEDO DO GND
47 3 6 C47 2 2 2 2 2
C93 EDDI/AUX DI NC
<10> PCIE_MRX_C_LANTX_N2 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N2 30 HSON EESK 48 2 SK NC 7 C468 C450 C436 C475 C481
EECS 44 1 CS VCC 8 +3V_LAN
1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<10> PCIE_MTX_C_LANRX_P2 23 HSIP AT93C46-10SI-2.7_SO8 0.1U_0402_16V4Z 1 1 1 1 1
3
40 Q42 Q6
NC
42 NC
50 22 +LAN_VDD18 +LAN_CTRL18 1 +LAN_CTRL15 1
NC EVDD18 8111B@ 8111B@
51 NC 40mil 40mil
28 Mount for 2SB1188T100R_SC62-3 2SB1188T100R_SC62-3
EVDD18
8101E and
2
8111B@ RTL8111B_QFN64
8111C.
Mount for 8101E Only 40mil 40mil
Mount 1 2 +LAN_VDD18 1 2 +LAN_VDD15
1 L46 0_0603_5% 1 1 L48 0_0603_5% 1
Place Close to Chip for C444 +
8101E@
+
2
C482 +
8101E@
+ C464
1
C473
+LAN_VDD18
8101E@ 8101E 8101E@ C452 C440 8101E@ 8111B@ 8111B@
8101E@ R26 2 1 49.9_0402_1% LAN_MDI0- 22U_A_4VM 22U_A_4VM 0.1U_0402_16V4Z 22U_A_4VM 22U_A_4VM 1000P_0402_25V8J
C449 2 1 R24 2 1 49.9_0402_1% LAN_MDI0+ Only 2 2 1 2 2 2
1 1 1 R345 300_0402_5%
1G@ R84 R81 11
C118 C120 0.5u_GST5009 C565 +3V_LAN Amber LED+
0.01U_0402_25V4Z 0.01U_0402_25V4Z 75_0402_1% 75_0402_1% 68P_0402_50V8J C166 TYCO_1734819-3
1
2 2 2 RJ45_GND LANGND
1 1 1 2
2
R80 R78 1 1
C121 C135 1000P_1206_2KV7K C141 C174
A 75_0402_1% 75_0402_1% A
0.01U_0402_25V4Z 0.01U_0402_25V4Z
2 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2
RJ45_GND 2 2
TST1284 for 10/100 LAN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8111B(1G)/8101E(10/100)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 25 of 45
5 4 3 2 1
5 4 3 2 1
Adjustable Output
HD Audio Codec +5VALW +5VALW_VDDA
U31
B:Need to link SA091820030 +VDDA
L28 1 +VDDA
2 4 VIN VOUT 5 4.75v
0.1U_0402_16V4Z
FBMA-L11-160808-800LMT_0603
2
2 DELAY SENSE or ADJ 6
R221
7 1 69.8K_0603_1%
C376 ERROR CNOISE
C380 8 3 C353
1
SD GND @ 4.7U_0805_10V4Z
4.7U_0805_10V4Z
SI9182DH-AD-T1-E3_MSOP8
B:Set to "@".
1
D C360 D
0.1U_0402_16V4Z R222
24K_0402_1%
<28,30,32,35,40> SYSON 2 1
R219 0_0402_5%
2
<15,28,30,35,38> SUSP# 2 1
R226 @ 0_0402_5%
+3V_DVDD
25
38
9
0.1U_0402_16V4Z U29
100P_0402_25V8K 1 1
AVDD1
AVDD2
DVDD_IO
DVDD
C368 C367
@ 1000P_0402_25V8J @1000P_0402_25V8J
AMP_LEFT 2 2
14 NC LINE_OUT_L 35 AMP_LEFT <27>
AMP_RIGHT
SPK output to AMP
1 2 15 NC LINE_OUT_R 36 AMP_RIGHT <27>
C337 100P_0402_25V8K
+MIC2_VREFO 1 2 INT_MIC 1 2 MIC2_L 16 39
MIC2_L HP_OUT_L AMP_LEFT_HP <27>
C R380 MIC@ 4.7K_0402_5% C338 MIC@ 1U_0402_6.3V4Z HP output to AMP C
JP16 1 2 MIC2_R 17 41
MIC2_R HP_OUT_R AMP_RIGHT_HP <27>
4 2 C346 MIC@ 1U_0402_6.3V4Z
NC2 2
3 NC1 1 1 2 1 1 2 23 LINE1_L NC 45
C591 C345 100P_0402_25V8K
ACES_85204-0200N MIC@ 220P_0402_50V8J 24 46
MIC@ 1U_0402_6.3V4Z LINE1_R DMIC_CLK
C714 1 2 18 43 AZ_BITCLK_HD
CD_L NC
C711 12 20 44
CD_R NC
2
100P_0402_25V8K
C350 100P_0402_25V8K 19 R454
CD_GND AZ_BITCLK_HD @ 10_0402_5%
1 2 BIT_CLK 6 AZ_BITCLK_HD <17>
MIC1_L 1 2 MIC1_C_L 21
<27> MIC1_L MIC1_L
C351 1U_0402_6.3V4Z
1
MIC1_R 1 2 MIC1_C_R 22 8 AZ_SDIN3_HD_R 1 2
<27> MIC1_R MIC1_R SDATA_IN AZ_SDIN3_HD <17>
C356 1 2 1U_0402_6.3V4Z R453 33_0402_5%
C355 100P_0402_25V8K 12 37
<27> MONO_IN PCBEEP MONO_OUT
1 2 1
C707 100P_0402_25V8K 29 C708
LINE1_VREFO @ 10P_0402_50V8J
<17> AZ_RST_HD# 11 RESET#
GPIO1 31
2
<17> AZ_SYNC_HD 10 SYNC
28
10mil
MIC1_VREFO_L +MIC1_VREFO_L
B:Chg. to link w/ SB600 bec'z chg. to KB926.
<17> AZ_SDOUT_HD 5 SDATA_OUT
32
10mil
MIC1_VREFO_R +MIC1_VREFO_R
<17> SPK_SEL 2 GPIO0
3 GPIO3 MIC2_VREFO 30 +MIC2_VREFO
NBA_PLUGR455 39.2K_0402_1% SENSE_A 10U_0805_10V4Z
B <27> NBA_PLUG 2 1
SENSE_B
13
34
SENSE A
27
10mil C720 1 2
B
R456 20K_0402_1% SENSE B VREF
<27> MIC_SENSE 1 2
47 EAPD JDREF 40 1 2
C721 100P_0402_25V8K
1
B:Remove NBA_PLUG on SENSE B. 48 SPDIFO NC 33
R464 1 2 MIC@ 20K_0402_1%
<30> EAPD 4 26 R224
DVSS1 AVSS1 20K_0402_1%
7 DVSS2 AVSS2 42
2
AGND
DGND
C369 C370
DGND To AGND Bypass
Sense Pin Impedance Codec Signals 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2
39.2K PORT-A (PIN 39, 41) R247 0_0603_5%
1 2
R207 0_0603_5%
20K PORT-B (PIN 21, 22) 1
R206
2
0_0603_5%
SENSE A
1 2
10K PORT-C (PIN 23, 24) R233 0_0603_5%
1 2
R218 0_0603_5%
A 5.1K PORT-D (PIN 35, 36) A
DGND AGND
39.2K PORT-E (PIN 14, 15)
HP_EN +5VS
1
Volume Control
1
C325
@ 0.01U_0402_25V4Z +3VS
2 R205
100K_0402_5% +3VS
C:Chang PN to
1
2
R201 DEB00000600 C717 R457
<30> EC_EAPD_R# 2 1 @ 0_0402_5% EC_EAPD# +3VS 1 2 100K_0402_5%
1
1
R463 R460 0.1U_0402_16V4Z
2
5
4 C326 SW6 10K_0402_5% 10K_0402_5% +3VS 4
1
B:1.For 2057 reserve 0.01U_0402_25V4Z @ 1
DIP
2 0.1U_0402_16V4Z
NC
2
2
R198 mount, Q25 unmount +3VS 1 2 +AMP_HVDD 2 4 C710
A Y
1U_0402_6.3V4Z
Add R484 for gain adj R227 0_0603_5% 2 2 1 2
A
G
R461 10K_0402_5% 74LVC1G14GW_SOT353-5 2
+5VS 1 2
2.Remove R198, R484 and Q25 R220 @ 0_0603_5% C365 U32 U28
3
COM 1 1 CD1# VCC 14
+5VS 1
2 D1 CD2# 13
W=40mil 3 CP1 D2 12
C713
B 3 1 2 4 SD1# CP2 11
0.1U_0402_16V4Z
R462 10K_0402_5% 1 1 5 10
Q1 SD2#
0.1U_0402_16V4Z
1U_0402_6.3V4Z
10U_0805_10V4Z
0.01U_0402_25V4Z
0.01U_0402_25V4Z
680P_0402_50V7K
1 2 1 C715 C716 6 09 1
Q1# Q2
DIP
C357 C335 C718 C374 7 08
SW_XRE094_3P GND Q2#
2 2 74LCX74MTC_TSSOP14
4
2 1 2 2
11
19
10
20
ENCODER_DIR <30>
1
U30
ENCODER_PULSE <30>
CVDD
HVDD
PVDD
PVDD
VDD
1 2 AMPR
<26> AMP_RIGHT
C340 0.22U_0402_10V4Z 3 22 SPKR+ D6 PACDN042Y3R_SOT23-3
AMPL INR_A ROUT+ SPKR-
1 2 5 21 2 C:Add in BOM by EMI
<26> AMP_LEFT
C348 0.22U_0402_10V4Z
R208 1 2 100K_0402_5% AMP_EN# 27
INL_A ROUT-
8 SPKL+
Left Speaker Connector 1
3
3
/AMP EN LOUT+ SPKL- L18 JP18 3
LOUT- 9
+5VS R223 1 2 100K_0402_5% HP_EN 24 SPKL+ 1 2 0_0603_5% SPK_L1 1 3
HP_EN HP_R SPKL- SPK_L2 1 NC1
HP_R 17 1 2 2 2 NC2 4
<26> AMP_RIGHT_HP 1 2 AMP_RHPIN R458 1 2 AMP_RHPIN_L 4 INR_H HP_L 18 HP_L L19 0_0603_5% 1 1
C709 2.2U_0603_6.3V4Z 24K_0402_5% 6 ACES_85204-0200N
INL_H C173 C175
<26> AMP_LEFT_HP 1 2 AMP_LHPIN R459 1 2 AMP_LHPIN_L A:sync up with ISKAE to replace L to R.
C712 2.2U_0603_6.3V4Z 24K_0402_5% EC_EAPD# 26 10P_0402_50V8J @ @ 10P_0402_50V8J
SET/SD# CVSS 2 2
15
C333
1 2 AMP_BEEP
1U_0402_6.3V4Z
28 BEEP
CVSS
16
Right Speaker Connector L9 JP6
AMP_CP+ HVSS SPKR+
12 CP+ 1 1 2 0_0603_5% SPK_R1 1 1 NC1 3
2 1 AMP_CP- 14 2 C722 SPKR- 1 2 SPK_R2 2 4
CP- GND 2 NC2
2.2U_0603_6.3V4Z
C719 2.2U_0603_6.3V4Z 23 L10 0_0603_5%
AMP_BIAS PGND ACES_85204-0200N
2 1 25 BIAS PGND 7 3
C344 2.2U_0603_6.3V4Z 2
CGND 13 1
1 2 GND 29 2 C:Add in BOM by EMI
C336 0.1U_0402_16V4Z
Gain HP 0dB APA2057ARI-TRL_TSSOP28 D3 PACDN042Y3R_SOT23-3
1
+3VS
2
10K_0402_5% 4
<26> MIC_SENSE
1
2 2
8
R451 MIC1_R 1 2 L33 MIC1_R_1 3
<26> MIC1_R
2
R446
2
220P_0402_50V8J
220P_0402_50V8J
C702 1 2 1 2 1 1
<30> BEEP#
SM05_SOT23
1U_0402_6.3V4Z 560_0402_5% C706 C383 C384 FOX_JA6033L-5S1-TR
1 2 @ AGND
MONO_IN <26>
1
1U_0402_6.3V4Z 2 2 J2 J3
PCI Beep
1
1 2 JUMP_43X39 JUMP_43X39
1
C701 1 R443 D17
<17> SB_SPKR 2 1 2 R452 @ @
1
2
1U_0402_6.3V4Z 560_0402_5% C
Q60 2.4K_0402_5%
2
2
B MMBT3904_SOT23-3
E
3
JP38
Headphone-Out Jack 5
CardBus Beep R448
C703 1 2 1 2 4
<22> PCM_SPK <26> NBA_PLUG
1U_0402_6.3V4Z 560_0402_5% R245 8
1
1
1
10P_0402_50V8J
10P_0402_50V8J
PCMCIA@ 1 1
2
2
R241 R240 FOX_JA6033L-5S1-TR
@ @ D18 AGND
0_0402_5% 0_0402_5% C381 C382 @
1 2 2 1
2
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP&Audio Jack/MDC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 27 of 45
A B C D E
+5VS
Place Components closely to ODD Conn.
MDC 1.5 Conn. ODD CONN
1 1 1 1 1
+3V_SB C586 C579 C578 C580
C585
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2
1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C569 C563 C562 +3VS
MDC@1000P_0402_25V8J MDC@0.1U_0402_16V4Z MDC@4.7U_0805_10V4Z
2 2 2 +3VS
14
U20C
1 2 IDE_SDIORDY 9
P
<17> SIDERST# A
R382 4.7K_0402_5% 8 SIDE_RST#
NB_RST# O
<11,15,17,24,25,30,34> NB_RST# 10 B
G
SN74LVC08APW_TSSOP14
7
JP14 +3V_SB
1 GND1 RES0 2
3 4 IDE_SDD[0..15]
<17> AZ_SDOUT_MD IAC_SDATA_OUT RES1 <17> IDE_SDD[0..15]
5 GND2 3.3V 6
<17> AZ_SYNC_MD 7 8 JP29
AZ_SDIN0_MD_R IAC_SYNC GND3
9 IAC_SDATA_IN GND4 10 1 1 2 2
<17> AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD <17> 3 3 4 4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SIDE_RST# 5 6 IDE_SDD8 1
C571 5 6
R358 1 1 IDE_SDD7 7 8 IDE_SDD9 1
7 8
2 1 AZ_SDIN0_MD_R 2 1 1 2 IDE_SDD6 9 10 IDE_SDD10 C730
GND
GND
GND
GND
GND
GND
<17> AZ_SDIN0_MD R357 MDC@33_0402_5% C731 C732 IDE_SDD5 9 10 IDE_SDD11 C733 @
11 11 12 12
@ 10_0402_5% @ 10P_0402_50V8J @ @ IDE_SDD4 IDE_SDD12 @ 2
13 13 14 14
MDC@ 2 2 IDE_SDD3 IDE_SDD13 2
15 16
13
14
15
16
17
18
ACES_88018-124G IDE_SDD2 15 16 IDE_SDD14
17 17 18 18
IDE_SDD1 19 20 IDE_SDD15
IDE_SDD0 19 20
Connector for MDC Rev1.5 21 21 22 22 IDE_SDDREQ <17>
23 23 24 24 IDE_SDIOR# <17>
<17> IDE_SDIOW# 25 25 26 26
IDE_SDIORDY 27 28
<17> IDE_SDIORDY 27 28 IDE_SDDACK# <17>
<17> INT_IRQ15 29 29 30 30
31 32 IDE_PDIAG#1 2 R363 +5VS
<17> IDE_SDA1 31 32
+3VS +3V_SB +1.5VS 33 34 100K_0402_5%
<17> IDE_SDA0 33 34 IDE_SDA2 <17>
<17> IDE_SDCS1# 35 35 36 36 IDE_SDCS3# <17>
2 1 37 38 W=80mils
+5VS 37 38 +5VS
B:Set to "@" R374 100K_0402_5% +5VS 39 40
39 40
1 1 1 1 1 1 41 41 42 42
C315 C306 C317 43 44 2 1
NEW@ C305 NEW@ C307 NEW@ C318 43 44
45 45 46 46
0.1U_0402_16V4Z @ 10U_0805_10V4Z 0.1U_0402_16V4Z @ 10U_0805_10V4Z 0.1U_0402_16V4Z @ 10U_0805_10V4Z 2 1 SEC_CSEL 47 48 C584 0.1U_0402_16V4Z
2 2 2 2 2 2 R348 470_0402_5% 47 48
49 49 50 50
1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C735 1 C:Reserve
51
52
C734 C736
@ 0.1U_0402_16V4Z OCTEK_CDR-50JL1G @ C730~C736 by EMI.
51
52
2 2
+3VALW_CARD +3VS_CARD +1.5VS_CARD 2
Imax = 0.275A Imax = 1.35A Imax = 0.75A
A:This symbol is for IALAA
1 1 1 1 1 1
only, to add these two @
C312 C313 C321 C316 C323 C322 pins for Boss Hole.
NEW@ NEW@ NEW@ NEW@ NEW@ NEW@
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
B:relink DC030006O00.
JP20
+3V_SB
1 GND
<17> USBP9- 2 USB_D-
U12 <17> USBP9+ 3 USB_D+
1 2 CP_USB# 60mils CP_USB# 4 CPUSB#
R204 NEW@100K_0402_5% +3VS 5 7 +3VS_CARD 5
3.3Vin1 3.3Vout1 RSV
6 3.3Vin2 3.3Vout2 8 6 RSV
<8,9,13,17,24> SMB_CK_CLK0 7 SMB_CLK
1 2EXP_CPPE# <8,9,13,17,24> SMB_CK_DAT0 8 SMB_DATA
R203 100K_0402_5% 40mil +1.5VS_CARD 9 +1.5V
+3V_SB 21 3.3Vaux_in Aux_out 20 +3VALW_CARD 10 +1.5V
<16,30> EC_SWI# 11 WAKE#
share with USB OC PIN 40mil +3VALW_CARD
PERST#
12 +3.3VAUX
+1.5VS 18 1.5Vin1 1.5Vout1 16 +1.5VS_CARD 13 PERST#
19 1.5Vin2 1.5Vout2 17 +3VS_CARD 14 +3.3V
need always pull high CLKREQ#
15
16
+3.3V
CP_USB# EXP_CPPE# CLKREQ#
14 CPUSB# <17> EXP_CPPE# 17 CPPE#
EXP_CPPE# 15 23 18
CPPE# OC# <13> CLK_NEW# REFCLK-
<15,26,30,35,38> SUSP# 4 STBY# <13> CLK_NEW 19 REFCLK+
3 22 RCLKEN 20
<26,30,32,35,40> SYSON SHDN# RCLKEN GND
NB_RST# 2 9 PERST# <11> PCIE_MRX_C_NEWTX_N1 21
+3VS +3VS SYSRST# PERST# PERn0
<11> PCIE_MRX_C_NEWTX_P1 22 PERp0
23 29
GND
NC1
NC2
NC3
NC4
NC5
GND GND
<11> PCIE_MTX_C_NEWRX_N1 24 PETn0 GND 30
1
1
10
12
13
24
0.1U_0402_16V4Z 27
R183 2 GND
28
2
GND
5
NEW@ U10
10K_0402_5% CLKREQ# 2 FOX_1CH411ASC-MN
G Vcc
B
4 CLKREQ_NEW# <13> NEW@
2
Y
1 A
1
D NC7SZ32P5X_NL_SC70-5
3
C:Chg. PN to SB770020010. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TPM/ ODD CONNECTORS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 28 of 45
Int.Check
Camera
5VS or 3VS
Conn USB CONN. 1
W=20mils
+CAM_VDD
Fingerprint Conn +USB_VCCC
+5VALW 1 2
R484 CAMERA@ 0_0603_5% +3VS W=60mils
1
+5VS 1 2 C566
JP11 R343 @ 0_0603_5% 0.1U_0402_16V4Z 1
1 CAMERA@ 1 1 1
1 USBP7- 2 C598 C681 + C643 C644
2 2 USBP7- <17>
3 USBP7+ USBP7+ <17> FP@ 150U_Y_6.3VM
3 0.1U_0402_16V4Z 1000P_0402_25V8J
4 4
2 JP17 C:Remove R114 and R117, leave 2 2 2
5 5
6 Chock for AMD plateform 0.1U_0402_16V4Z
GND1 5
GND2 7 4 WCM2012F2S-900T04_0805 JP30
<17> USBP5- 3
ACES_88266-05001 <17> USBP5+ 4 3 1 5
2 <17> USBP0- 4 3 VCC GND
CAMERA@ USBP0-_R 2 6
1 USBP0+_R D- GND
3 D+ GND 7
FP@ 1 2 4 8
+5VS <17> USBP0+ 1 2 GND GND
ACES_85201-0505
L21 +5VALW P-TWO_CU304G-A0G1G-P
D32 +3VS
D7
4 2 USBP7-
VIN IO1 D34
4 2 USBP0+_R
USBP7+ USBP5+ VIN IO1
3 IO2 GND 1 4 VIN IO1 2
USBP0-_R 3 1
@ PRTR5V0U2X_SOT143-4 USBP5- IO2 GND
3 IO2 GND 1 +5VALW +USB_VCCC @ PRTR5V0U2X_SOT143-4
@ PRTR5V0U2X_SOT143-4 U7
1 GND OUT 8
2 7
3
IN
IN
OUT
OUT 6 USB CONN.2
4 EN# FLG 5 1
+USB_VCCC
C231 G528P1UF_SO8 C672
W=60mils
CIR +5VALW B:Set to "@"
@ 4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
1
1 1
1
2 IN OUT 7
R347 C557 3 6
BT@ USB_EN# IN OUT
1M_0402_5% 4 EN# FLG 5
BT@ 0.1U_0402_16V4Z
3
S
R346 C705 G528P1UF_SO8
1
G
1 2 2 @4.7U_0805_10V4Z
BT@ 100K_0402_5% Q52 +USB_VCCA
2
D BT@AO3413_SOT23
1
D 1
Q51 JP12 +5VALW 3
<30> BT_PWR 2 4
G BT@ 12 USBP6+
GND2 D12 <17> USBP6+ 5
S 2N7002_SOT23-3 11 USBP6-
<17> USBP6-
3
GND1 USBP6+ 6
4 VIN IO1 2 7
USBP2+
<17> USBP2+ 8
C:Chg. PN to SB770020010. USBP6- 3 1 USBP2-
IO2 GND <17> USBP2- 9
10 10 10
9 @ PRTR5V0U2X_SOT143-4
<17> USBP4+ 9 11
<17> USBP4- 8 8 +5VALW
MP:Swap USB2+/- and USB8+/- for 12
<24> WLAN_BT_CLK 7 7 CAMERA problem.
Pull high at SB600 side 6 ACES_85201-1205
<17> BT_DET# 6 D11
<30> BT_RST# 5 5
4 4 2 USBP2+
<24> WLAN_BT_DATA (MAX=200mA) 4 VIN IO1
Module ID +BT_VCC 3
Indication for polarity of reset BT_DETACH 3 USBP2-
2 2 3 IO2 GND 1
Reset input High Active --> Low , 1
Reset input Low Active --> Open 1 @ PRTR5V0U2X_SOT143-4
1
ACES_87213-1000G
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 29 of 45
5 4 3 2 1
+3VALW
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VALW
1 1 C572 1 1 2 2
C582 B:Chg. U24 from KB910 to KB926.
1 2 C540 C546 C600 C551
C575 0.1U_0402_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J
ECAGND 2 2 2 2 1 1
1 2
111
125
L55 0_0603_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
22
33
96
67
9
U24
BATT_TEMPA 2 1 ECAGND
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
C574 0.01U_0402_25V4Z
D D
CLK_PCI_EC 1 21 R364
<16> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <15>
2 23 100K_0402_5%
<16> EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <27>
1
3 26 ADP_IR 1 2
<16,22,34> SERIRQ SERIRQ# FANPWM1/GPIO12 ENCODER_DIR <27> ADP_I <38>
R339 4 27
<16,34> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <38>
@ 10_0402_5% 5 1 2
<16,34> LPC_AD3 LAD3
7 PWM Output C587 0.22U_0402_10V4Z
<16,34> LPC_AD2 LAD2
8 63 BATT_TEMPA
<16,34> LPC_AD1 BATT_TEMPA <37>
2
LAD1 BATT_TEMP/AD0/GPIO38
1 <16,34> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_IR
BATT_OVP <38> +3VALW
ADP_I/AD2/GPIO3A 65
C553 CLK_PCI_EC 12 AD Input 66 MODE#
<16> CLK_PCI_EC PCICLK AD3/GPIO3B MODE# <32>
@ 22P_0402_50V8J 13 75 MODE# 2 1
2 <11,15,17,24,25,28,34> NB_RST# PCIRST#/GPIO05 AD4/GPIO42 KILL_SW# <24>
ECRST# 37 76 BTN_ID 100K_0402_5% R470
ECRST# SELIO2#/AD5/GPIO43 BTN_ID <32>
<17> EC_SCI# 20 SCI#/GPIO0E
<35> STB_WLAN 38 CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG <15> Analog BTN ID definition,
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 <34> Please see page 3.
+3VALW R340 +3VALW
DA Output IREF/DA2/GPIO3E 71 IREF <38>
47K_0402_5% KSI0 55 72
ECRST# KSI1 KSI0/GPIO30 DA3/GPIO3F BTN_ID
2 1 <32,33> EC_PLAYBTN# 56 KSI1/GPIO31 2 1
KSI2 57 R383 100K_0402_5%
<32,33> EC_STOPBTN# KSI2/GPIO32
2 1 KSI3 58 83
<32,33> EC_FRDBTN# KSI3/GPIO33 PSCLK1/GPIO4A EC_EAPD_R# <27>
C561 0.1U_0402_16V4Z KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <29>
KSI5 60 85
<32,33> EC_REVBTN# KSI5/GPIO35 PSCLK2/GPIO4C WL_BT_LED# <32>
KSI6 61 PS2 Interface 86 +5VS
KSI6/GPIO36 PSDAT2/GPIO4D SATTLATE_LED# <32>
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <33>
KSO0 39 88 TP_DATA TP_CLK 1 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <33>
KSO1 40 4.7K_0402_5% R338
KSO2 KSO1/GPIO21 TP_DATA
41 KSO2/GPIO22 1 2
C KSO3 42 97 STRAP 4.7K_0402_5% R337 C
KSO4 KSO3/GPIO23 SDICS#/GPXOA00
43 KSO4/GPIO24 SDICLK/GPXOA01 98 STB_LAN <35>
KSO5
KSI[0..7] KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 STB_SB <35>
<32,33> KSI[0..7] 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE <42>
KSO7 46 SPI Device Interface STRAP 2 1
KSO[0..17] KSO8 KSO7/GPIO27 R471 4.7K_0402_5%
<32,33> KSO[0..17] 47 KSO8/GPIO28
KSO9 48 119
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <31>
KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <31>
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
KSO11/GPIO2B EC_SPICLK <31>
KSO12 51 128
KSO12/GPIO2C SPICS# SPI_CS# <31>
KSO13 52
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73
KSO15/GPIO2F CIR_RX/GPIO40 CIR_IN <29>
KSO16 81 74
KSO16/GPIO48 CIR_RLC_TX/GPIO41 ENCODER_PULSE <27>
KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <38> +3VALW
BATT_CHGI_LED#/GPIO52 90 BATT_FULL_LED# <32>
+5VALW 91
CAPS_LED#/GPIO53 CAPS_LED# <33>
RP17 EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 2 1
<31,37> EC_SMB_CK1 SCL1/GPIO44 BATT_CHG_LOW_LED# <32>
1 8 EC_SMB_CK1 EC_SMB_DA1 78 93 R341 100K_0402_5%
<31,37> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 POWER_LED# <32>
2 7 EC_SMB_DA1 EC_SMB_CK2 79 SM Bus 95 D33
<6,15> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <26,28,32,35,40>
3 6 EC_SMB_DA2 EC_SMB_DA2 80 121 1 2 ACIN_R
<6,15> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <42> <32,36> ACIN
4 5 EC_SMB_CK2 127 ACIN_R
AC_IN/GPIO59 CH751H-40PT_SOD323-2
4.7K_0804_8P4R_5%
<16> PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# <17>
<16> PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# <17>
<17> EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON <32>
<32> LID_SW# 16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103 EC_SWI# <16,28>
<15,26,28,35,38> SUSP# 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 SB_PWRGD <6,16>
B B
<16> PBTN_OUT# 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <15>
19 GPIO 106 +3VALW
<25> EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <24>
<24> PCIE_WAKE# 25 EC_THERM#/GPIO11 GPXO10 107 ALI/MH# <37,38>
<34> FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 CURSOR_LED <33>
<35> VLDT_EN 29 FANFB2/GPIO15
<34> E51_TXD 30 EC_TX/GPIO16
31 110 IE_BTN# 2 1
<34> E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1 NB_PWRGD <11>
32 112 ENBKL 100K_0402_5% R330
<32> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2
<32> PWR_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EAPD <26>
<33> NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# <17>
R315 116
GPXID5 BT_PWR <29>
C RY1 1 2C RY2 117 BT_RST# <29>
GPXID6 IE_BTN#
GPXID7 118 IE_BTN# <32> 2 1 VGA_ENBKL <15>
@ 20M_0603_5% C RY1 122 0_0402_5% VGA@ R1173
C RY2 XCLK1
123 XCLK0 V18R 124
ENBKL 2 1 UMA_ENBKL <11>
AGND
1 1
C541 C542
1
KB926QFA1_LQFP128_14X14 2 1
11
24
35
94
113
69
15P_0402_50V8J
15P_0402_50V8J
Y5 @ 2K_0402_5% R1175
OUT
IN
2 2
B:Set R1175 with "@".
ECAGND
NC
NC
2
A A
32.768KHZ_12.5P_1TJS125BJ4A421P
MP:ENE's recommend, change C541 and C542 from 10P to 27P.
MP:ENE's recommend, change back C541 and C542 from 27P to 15P.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB910
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomIALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 30 of 45
5 4 3 2 1
+3VALW
+5VALW
C527
+5VALW 2 1
1
0.1U_0402_16V4Z C538
1 2 R318 0.1U_0402_16V4Z
100K_0402_5%
U22
2
8 1 R305
VCC A0 R325
5
7 2 U21 100K_0402_5%
WP A1 R303
6 3 1 2 2 INT_FLASH_EN# 1 2
G Vcc
<30,37> EC_SMB_CK1 SCL A2 B
5 4 INT_SPI_CS# 1 2 4
<30,37> EC_SMB_DA1 SDA GND Y
1 SPI_CS#
AT24C16AN-10SU-2-7_SO8 100K_0402_5% 22_0402_5% A
NC7SZ32P5X_NL_SC70-5
3
SPI Flash (8Mb*1)
B:Chg. to SPI ROM.
+3VALW
1 20mils
C507 U19
8 VCC VSS 4
0.1U_0402_16V4Z
2
3 W
7 HOLD
SPI_CS# 1 2 INT_SPI_CS# 1 S
R472 0_0402_5% @
EC_SPICLK 1 2 SPI_CLK_R 6 C
<30> EC_SPICLK
R473 0_0402_5%
<30> EC_SO_SPI_SI 2 1 EC_SO_SPI_SI_R 5 D Q 2
EC_SI_SPI_SO_R 2 1 EC_SI_SPI_SO <30>
R474 0_0402_5% R475 0_0402_5%
SST25LF080A_SO8-200mil
JP50
C:Chg. PN to LTC00000200
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS& I/O PORT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 31 of 45
5 4 3 2 1
2
3 51_ON# 3 51_ON# B:Remove SW1 from DVT for +3VALW
R228 +3VALW
interfere issue.
DAN202UT106_SC70-3 DAN202UT106_SC70-3
1
100K_0402_5%
SW4 SW1 D13 U14 R236
1
D JP2 2 APX9132ATI-TRL_SOT23-3 47K_0402_5% D
ON/OFFBTN# <30>
ON/OFFBTN_R# 1 1 3 1 3 ON/OFFBTN_R# 1
IEBTN# 1 51_ON#
2 3 51_ON# <36>
2
2
3 2 4 2 4 2 3
GND
<30,33> KSO0 3 VDD VOUT LID_SW# <30>
MODEBTN# 4 DAN202UT106_SC70-3
KSI1 4 TEST@ @ SMT1-05-A_4P
<30,33> EC_PLAYBTN# 5
6
5
6
5
5
1
D
10P_0402_50V8J
0.1U_0402_16V4Z
KSI2 6 SMT1-05-A_4P 1 1 1
<30,33> EC_STOPBTN#
1
KSI3 6 Q38 D19 C378
<30,33> EC_FRDBTN# 7 7 <30> EC_ON 2
KSI5 8 G 2N7002_SOT23-3 C358 RLZ20A_LL34 C377
<30,33> EC_REVBTN# 8
2
9 S 0.01U_0402_25V4Z
<30> BTN_ID
3
9 R251 2 2 2
10
2
10
11 GND 10K_0402_5% C:Chg. PN to SB770020010.
12 GND
1
ACES_85201-1005N
3
B:Chg. to link SC5191NB000 47K
2
Q30 Q27
G
D20 Q37 2N7002_SOT23-3
+5VALW 1 2 2 1 1 3 10K 2 1 3
C R252 120_0402_5% HT-191NB_BLUE_0603 PWR_SUSP_LED <30> C
D
S
C:Chg. PN to SB770020010. C:Chg. PN to SB770020010.
2N7002_SOT23-3
BATT CHARGE/FULL LED DTA114YKAT146_SOT23-3
D21
1
D22 R234 1 2 300_0402_5% 2 1
+5VALW 1 2 2 1 BATT_CHG_LOW_LED# BATT_CHG_LOW_LED# <30> HT-191UD_AMBER_0603
R231 300_0402_5% HT-191UD_AMBER_0603
D27
1
R232
2
120_0402_5%
2 1 BATT_FULL_LED#
HT-191NB_BLUE_0603
BATT_FULL_LED# <30>
+5VALW
POWER LED
B:Chg. to link SC5191NB000 SYSON
3
47K
2
Q31 Q26
G
2N7002_SOT23-3
WL&BT LED 10K 2 1 3 POWER_LED# <30>
S
D38 VF=1.9V C:Chg. PN to SB770020010.
+5VS 1 2 2 1 DTA114YKAT146_SOT23-3
WL_BT_LED# <30>
R250 WLAN@ 300_0402_5% WLAN@ HT-191UD_AMBER_0603
D26
1
1 2 2 1
R235 120_0402_5% HT-191NB_BLUE_0603
B:Chg. to link SC5191NB000
3G LED D37 VF=2.8V
B:Chg. to link SC5191NB000
1 2 2 1
B
+5VS
R249 3G@ 120_0402_5% 3G@HT-191NB_BLUE_0603
3G_LED# <24>
Satellite LED B
+5VS
47K Q33
Q130 SATEL@
HDD LED D23
2N7002_SOT23-3 DTA114YKAT146_SOT23-3
C:Chg. PN to SB770020010. 10K 2 SATTLATE_LED# <30>
D
+5VS 1 2 2 1 1 3
R253
120_0402_5% HT-191NB_BLUE_0603 B:Chg. from 120 to 100 to
make LED more brightness.
G
2
D15
1
D
2 1 1 3
R476 100K_0402_5% VF=2.8V
Q131 1 2 2 1
2N7002_SOT23-3 R238 SATEL@ 100_0402_5%
G
2
HDD_LED# <17>
SATEL@ 12-21-BHC-ZL1M2RY-2C_BLUE
D16
1 2 2 1
R239 SATEL@ 100_0402_5%
A A
SATEL@ 12-21-BHC-ZL1M2RY-2C_BLUE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Comm. SW/ Sub Conn./LEDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomIALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 32 of 45
5 4 3 2 1
5 4 3 2 1
6
5
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/Touch Pad& hibernation
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomIALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 33 of 45
5 4 3 2 1
A B C D E
@ @ @ @ @ @
1
VS C2:Chg. to +5VS
AO3409 for
Fan High Need to link SC1SS355010
8
speed problem
1
S
2 1 FBFAN 5 PU5B R313
P
R309 10K_0402_5% + FAN1_ON
G
D30 CF1 CF8 CF9 CF4 CF3
1
ENFAN 0 7 2 1
100_0402_5%
2
AO3409_SOT23 1SS355_SOD323-2
1
<30> EN_DFAN1 2 1 6 - 1 1 1 1 1
G
R281 10K_0402_5% P@ LM358DT_SO8 Q46 D @ @ @ @ @
1
2
JP8
2
5 CF5 CF10 CF7 CF6 CF2
R308 +FAN1 GND
4 GND 1 1 1 1 1
@ 10K_0402_5% @ @ @ @ @
1
1 3
1
D31 3
2 2
+ BAS16_SOT23-3 1
C508 1
C:Chg. PN to
22U_B_10VM SC1BAS16000 ACES_85205-03001
EMI Shielding Clip PADs
2
2
1 2 2
R314 5.1K_0402_5%
C531 M1 M2 M3 M4 M5
+3VS 1 2 @ 1000P_0402_25V8J R80x100 R80x100 R80x100 R80x100 R80x100
R312 10K_0402_5% 1
B:FAN circuit to PWM like
@ @ @ @ @
SWAP PU5.5, PU5.6 <30> FAN_SPEED1
1
R281 change to 10K 2
Q46 change to IRLML5103PBF C532
R314 conn to +FAN1 @ 1000P_0402_25V8J M6 M7 M8 M9 M10 M11
1 R80x100 R80x100 R80x100 R80x100 R80x100 R80x100
@ @ @ @ @ @
1
R428
@ 0_0402_5%
2 H34 1 2 E51_TXD 2
+3VALW E51_TXD <30>
R449
@ 0_0402_5%
E51_RXD 1 2 6 5 1 2 LPC_DRQ1#
<30> E51_RXD LPC_DRQ1# <16>
R426
0_0402_5%
SERIRQ 1 2 7 4 NB_RST#
<16,22,30> SERIRQ NB_RST# <11,15,17,24,25,28,30>
R450
<16,30> LPC_AD3
0_0402_5%
LPC_AD3 8 3 LPC_AD2
LPC_AD2 <16,30>
Screw Hole
H32 H30 H27 H10 H24
H_C252D118 H_C252D118 H_C252D118 H_C252D118 H_C252D118
LPC_AD1 9 2 LPC_AD0
<16,30> LPC_AD1 LPC_AD0 <16,30>
H6 H7 @ @ @ @ @
H_C276D157 H_C236D146
1
LPC_FRAME# 10 1
<16,30> LPC_FRAME# CLK_PCI_SIO <16>
@ @
H3 H2 H1 H31
1
2
H_C252D118 H_C252D118 H_C252D118 H_C252D118
@ DEBUG_PAD R424
22_0402_5% @ @ @ @
H23 H22
For EC
1
1 H_C276D158 H_C276D158
2
@ @
JP13 C692
1
1 22P_0402_50V8J
1 +5VALW 1
2 E51_RXD
2 E51_TXD H14 H11 H9
3 3
3 H4 H33 H5 H_C236D122 H_C236D122 H_C236D122 3
4 4
H_C118D118N H_O118X197D118X197N H_O197X55D158X16
@ ACES_85205-0400 @ @ @
@ @ @
LPC Debug card
1
1
1
H13 H26 H12 H18
LPC Debug Port H_S315D118 H_S315D118 H_S315D118 H_C236D43
@ @ @ @
+3VS
1
JP10 H29 H28 H37 H8 H17 H35 H36
1 H_O173X59D134X20 H_O173X59D134X20 H_O173X59D134X20 H_C236B73D43 H_C236B73D43 H_C236B73D43 H_C236B73D43
1
2 2
3 @ @ @ @ @ @ @
3
4
1
1
4
5 5
6 6 CLK_14M_SIO <13>
7 LPC_AD0
7 LPC_AD1 H21 H20 H15 H16
8 8
9 LPC_AD2 H25 H19 H_C276BC185D165H_C276BC185D165H_C276BC185D165H_C276BC185D165
9 LPC_AD3 H_O158X59DO118X20 H_O158X59DO118X20
10 10
11 LPC_FRAME# @ @ @ @
11 LPC_DRQ1# @ @
12
1
4 12 4
13 NB_RST#
1
1
13 R85
14 14 1 2 @ 0_0402_5%
15 CLK_PCI_SIO
15 SERIRQ
16 16
17 17
18
18
19 19
Security Classification Compal Secret Data Compal Electronics, Inc.
20 20 Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
@ ACES_85201-2005
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & MDC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomIALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 34 of 45
A B C D E
A B C D E
+1.2VALW TO +1.2V_HT +1.8V TO +1.8VS B:Q18 and Q36, need to link "SB548000310"
C:Q14 and Q41, change part to reduce Rds(on) to improve PWR drop. +5VALW
C:Chg.Q14,Q41 part to reduce low Rdson part. MP: Update R137 and R286 from 22K to 330K and C247 and C457 from 0.1U Y5V
+1.2VALW +1.2V_HT +5VALW
+1.8V +1.8VS to 0.01U X7R to meet PWR SEQ, and update C180 and C385 to 25V to meet PWR
2
request.
2
Q14 1 1 R211
IRF8113PBF_SO8 C181 C178 4.7U_0805_10V4Z R210 10K_0402_5%
470_0805_5%
8 1 Q41 1 2 10K_0402_5%
2
7 2 IRF8113PBF_SO8 C443
1
2 2
470_0805_5%
6 3 R111 8 1 C431 SYSON#
<41> SYSON#
1
2
5 7 2 10U_0805_10V4Z SUSP
<41> SUSP
1
1U_0402_6.3V4Z 2 1 R285 D
6 3
1
D
1 1 R98 2 +VSB 5 <26,28,30,32,40> SYSON 2 Q29 1
4
1
4.7U_0805_10V4Z
2
4.7U_0805_10V4Z
1 2 R286 1 +VSB G 2N7002_SOT23-3 S
3
1
2
D D
0.01U_0402_25V7K
C184 Q13 Q15 1 330K_0402_5% S C:Chg. PN to
3
1
C180 2 VLDT_EN# 2 C462 C:Chg. PN to R212 SB770020010.
1
2 2 G 2N7002_SOT23-3G D Q43 Q44 D R197 R209
2 SB770020010.
S 2N7002_SOT23-3 S C457 2 SUSP 2 10K_0402_5%
1
2 G 2N7002_SOT23-3G 10K_0402_5% 10K_0402_5%
1
S 2N7002_SOT23-3 S
2
VLDT_EN#
1
D +1.5VS +0.9V +2.5VS
+3VALW TO +3VS C:Chg.Q13,Q15,Q16,Q19,Q34,Q35,Q43,Q44 <30> VLDT_EN 2 Q24
+5VALW TO +5VS PN to SB770020010. G 2N7002_SOT23-3
2
+3VALW +3VS S
3
1
+5VALW +5VS C:Chg. PN to R280 R433 R272
4.7U_0805_10V4Z R478 SB770020010. 470_0805_5% 470_0805_5% @ 470_0805_5%
1 1 100K_0402_5%
Q18 C264 C263 4.7U_0805_10V4Z 1 1
1
470_0805_5%
8 1 Q36 C363 C362
2
D S
470_0805_5%
7 D S 2 8 D S 1 C:Chg. PN to SB770020010.
1
2 2 R166 D D D
6 D S 3 7 D S 2
2 2 R237
5 D G 4 6 D S 3 2 SUSP 2 SUSP 2 SUSP
1U_0402_6.3V4Z 5 4 B:Add PD 100K bec'z KB926 is tri-state pin. G G G
SI4800BDY_SO8 D G
2 R137 1 +VSB 1U_0402_6.3V4Z S Q40 S Q57 S Q39
1
3
0.01U_0402_25V7K
4.7U_0805_10V4Z
1
4.7U_0805_10V4Z
0.1U_0402_25V4Z
1 1 10K_0402_5%
1
1
C247 SUSP C379 D D
2 2
2 2 2 G G C385 SUSP B:Chg. to POP material for discharge. 2
2 2
S 2N7002_SOT23-3 2N7002_SOT23-3 S 2 2 G G Q34
3
3
2N7002_SOT23-3
2
B:1.Chg. PWR SW Q132 and Q133 from AO4422 to SI3456BDV +3VALW TO +3V_LAN R32
+3VALW TO +3V_SB 2.Remove Energy Star 4.0 function. +3VALW +3V_LAN STAR@
+3VALW +3V_SB PJ20 100K_0402_5%
1
PJ21 2 1
2 1 STB_LAN#
2 2 1 1 B:Remove Energy Star 4.0 function.
Q132 @ JUMP_43X79
1
Q133 @ JUMP_43X79 D
C:Chg. PN to SB770020010.
D
6 2 Q9
S
<30> STB_LAN
D
6 5 4 G STAR@
S
5 4 2 1 1 S 2N7002_SOT23-3
3
2
1
10U_0805_10V4Z
2 1 1 1 1 1 C85 C86
2
10U_0805_10V4Z
G
C272 C271 STAR@ STAR@ R143 10U_0805_10V4Z STAR@ 10U_0805_10V4Z STAR@ STAR@
G
3
10U_0805_10V4Z STAR@ 10U_0805_10V4Z 1U_0603_10V4Z STAR@ STAR@ STAR@ 2 2
1U_0603_10V4Z 470_0805_5% 100K_0402_5%
3
1 1
2
2 2 SI3456BDV-T1-E3_TSOP6 +5VALW
1 1
D
D Q8 2 STB_LAN#
2
Q17 2 STB_SB# G
G +VSB 2 1 S STAR@ R165
3
+VSB 2 1 S STAR@ R30 STAR@ 2N7002_SOT23-3 STAR@
3
1
3 47K_0402_5% D C87 3
1
1
1
1
2N7002_SOT23-3 2 D
S
3
2 Q21
<30> STB_SB
G STAR@
C:Chg.Q17,Q20,Q7,Q8,Q48,Q49,Q54,Q55 S 2N7002_SOT23-3
+1.2VALW TO +1.2V_SB
3
1
+3VALW TO +3V_WLAN PN to SB770020010. +1.2VALW +1.2V_SB R172
+3VALW +3V_WLAN PJ23 STAR@
PJ22 2 1 100K_0402_5%
2 1 +5VALW
2 1
2
2 1 @ JUMP_43X79
@ JUMP_43X79 Q56
2
D
Q47 6
S
D
6 5 4 R324
S
2
5 4 2 1 1 STAR@
2
1
C518 C525 STAR@ STAR@ STAR@ STAR@ STAR@ STAR@ 10U_0805_10V4Z 470_0805_5% B:Remove STB_12SB# control
G
1
10U_0805_10V4Z SI3456BDV-T1-E3_TSOP6 2 2 2 2
10U_0805_10V4Z
1
to STB_SB#
1
2 2
10U_0805_10V4Z D
1
D Q50
+VSB 2 1 <30> STB_WLAN 2
1
3
1
1
47K_0402_5% G D STAR@
1 S
3
1
4 4
STB_WLAN# 2 Q48 C526 2N7002_SOT23-3 G STAR@ STAR@ STAR@
G STAR@ STAR@ S 2N7002_SOT23-3 0.1U_0603_25V4Z 100K_0402_5%
3
S 2N7002_SOT23-3 0.1U_0603_25V4Z 2
3
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 35 of 45
A B C D E
A B C D
VS
PR1
VIN VIN 1M_0402_1%
PL1 1 2
PF1 HCB4532KF-800T90_1812
DC301001Q00
1
DC_IN_S1 1 2 DC_IN_S2 1 2
1
VS PR2
PJP1 10A_125V_451010MRL PR3 5.6K_0402_5% PR4
1 84.5K_0402_1% 10K_0402_1%
+
1 2 ACIN <30,32>
2
1
1
2 PR5
2
+
8
PC1 PC2 PC3 PC4 22K_0402_1% PU1A
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 3
P
2
2
- + PACIN
1
O 1 PACIN <38> 1
- 4 2 -
G
1
1
@ SINGA_2DW-0005-B03 PR6 LM393DG_SO8
4
PC5 20K_0402_1% PC6 PR7
0.1U_0402_16V7K PD1 10K_0402_1%
2
RLZ4.3B_LL34
2
0.068U_0402_10V6K 2
PR8
1 RTCVREF Vin Detector
10K_0402_1%
VIN 3.3V
High 18.384 17.901 17.430
2
Low 17.728 17.257 16.976
PD2
RLS4148_LL34-2
1
BATT+ 2 1
1
PD3 PR9 PR10
RLS4148_LL34-2 68_1206_5% 68_1206_5%
PQ1 1 2
PR12 PR11
2
200_0603_5% 1K_1206_5%
CHGRTCP 1 2 N1 3 1 VS
1
2 1 N3 1 2
VIN B+
1
1
2
PC8 PR13 2
2
2
<32> 51_ON# 1 2 1 2
PR15 TP0610K-T1-E3_SOT23-3 PR16
22K_0402_1% 1K_1206_5%
RTCVREF
1
PR18 PR19
PR17 100K_0402_1% 2.2M_0402_5%
1
200_0603_5% 1 2 2 1
PR21 PR22 PU2 G920AT24U_SOT89-3 VL PR20
560_0603_5% 560_0603_5% 3.3V 499K_0402_1%
2
1 2 1 2 3 2 N2
+CHGRTC OUT IN
2
1
8
PD6 PU1B
1
GND PD5 2 5
P
<6,37,39> MAINPWON +
PC9 PC10 1 7
10U_0805_6.3V6M 1 1U_0805_25V4Z @ RLZ16B_LL34 O
<38> ACON 3 6 2 1 VL
2
1
G
2
1
RB715F_SOT323-3 LM393DG_SO8 PR23 PR24
4
1
1
34K_0402_1% 499K_0402_1% PC11
1
PC12 PR26 1000P_0402_50V7K
2
1000P_0402_50V7K PC13 PR25 191K_0402_1%
2
1000P_0402_50V7K 66.5K_0402_1%
2
3 3
1
D 47K_0402_1%
+3VALWP 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V
PACIN
@ JUMP_43X118 @ JUMP_43X118 Precharge detector G
2 2 1
(5A,200mils ,Via NO.= 10) (8A,320mils ,Via NO.= 16) 15.97V/14.84V FOR S
3
PJ4 ADAPTOR
1
+5VALWP 2 1 +5VALW PJ5
2 1 +1.5VSP +1.5VS PQ3
2 2 1 1
@ JUMP_43X118 DTC115EUA_SC70-3
(5A,200mils ,Via NO.= 10) @ JUMP_43X118
RHU002N06_SOT323-3 2
PJ6 +5VALWP
(3.0A,120mils ,Via NO.=6)
+VSBP 2 2 1 1 +VSB
PJ7
@ JUMP_43X39 +0.9VP 2 1 +0.9V
3
2 1
(120mA,40mils ,Via NO.= 2) @ JUMP_43X79
(2A,80mils ,Via NO.= 4)
PJ9
+1.2VALWP 2 1 +1.2VALW
2 1
@ JUMP_43X118
PJ11
+2.5VSP 2 1 +2.5VS
2 1
@ JUMP_43X39
(1A,40mils ,Via NO.=2) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 36 of 45
A B C D
A B C D
VL VS VL
2
VMB
PF2 PL2 PR28
1
1 1
1
2 47K_0402_1%
3 3 1 2 1 2 +3VALWP
1
4 PR30 1 2
2
4 47K_0402_1% PR32 PQ4
5 5
8
6 13.7K_0402_1% PU3A DTC115EUA_SC70-3
6 PC15 PC16 PD7
7 1 2 3
P
7 +
1
10 8 1000P_0402_50V7K 0.01U_0402_25V7K 1 2 1 2
2
GND 8 PR33 TM_REF1 O
11 GND 9 9 2 -
G
1K_0402_1% 1SS355_SOD323-2
OCTEK_BTJ-09HA1G LM393DG_SO8
4
2
3
2
0.22U_0805_16V7K
PR35
15.4K_0402_1%
PR34 100_0402_1%
ALI/MH# <30,38>
1
PC17
100_0402_1%
1000P_0402_50V7K
PR36
1
1 2 1 VL
PC18
PR38 PR37
2
6.49K_0402_1% 100K_0402_1%
2
2 1 +3VALWP
1
PR39
100K_0402_1%
1
2
PR40
1K_0402_1%
2 2
2
VL VL
2
PR41
PH2 47K_0402_1%
100K_0603_1%_TH11-4H104FT PR42
47K_0402_1%
1
1 2
PR43
8
13.7K_0402_1% PU3B
PQ5 TP0610K-T1-E3_SOT23-3 1 2 5 PD8
P
+
O 7 2 1
15.4K_0402_1%
TM_REF1 6 -
G
3 3
B+ 3 1 +VSBP 1SS355_SOD323-2
PR44
LM393DG_SO8
4
0.22U_1206_25V7K
0.1U_0603_25V7K
PC19
1
100K_0402_1%
0.22U_0805_16V7K
2
1
1
PR45
PC20
PC21
2
2
PR46
2
22K_0402_1%
VL 1 2
@ @
100K_0402_1%
2
PR47
PR48
1
0_0402_5% D
1 2 2 PQ6
<39,40> POK
G RHU002N06_SOT323-3
0.1U_0402_16V7K
S
3
1
PC22
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 37 of 45
A B C D
A B C D
1
3 1 DCIN PQ51 2 7
P3 S D
1
1 1
DTC115EUA_SC70-3 3 6
S D
2
PC172 PC23 PC25 4 5
G D
1
PC142 0.1U_0603_25V7K 2FSTCHG PC24
2
1
5600P_0402_25V7K PR231 2 1 4.7U_1206_25V6K 4.7U_1206_25V6K
1
100K_0402_1% 4.7U_1206_25V6K FDS4435BZ_SO8
3
2
PQ11 PR50
2
1
3
200K_0402_1% PR230 100K_0402_1% PD19 1 2
SUSP# <15,26,28,30,35> VIN
2
PR52 1 2 RB715F_SOT323-3 PR54 PR51
3
1
47K_0402_1% PR53 6251VDD PU4 47K_0402_1%
2 PC26 0_0402_5% PC105 10K_0402_1% PD14
0.1U_0603_25V7K 2 1 PC27 1 24 DCIN 1 2 BATT+ 1 2
<30> FSTCHG ACOFF <30>
2
2
2.2U_0603_6.3V6K VDD DCIN
1
6251VDD 1 2
1
@ 0.1U_0603_25V7K 1SS355_SOD323-2
1
PR55 2 23 ACOFF#
PR72
2
ACSET ACPRN
1
1
6251_EN 3 22 1 2 CSON
EN CSON
2
DTA144EUA_SC70-3 2 PC30 PC29 PQ14
<30,37> ALI/MH# 200K_0402_1%
2 @ 680P_0402_50V7K 0.047U_0603_25V7M
PQ13 CSON1 2 4 21 1 2 CSOP PD15
1
CELLS CSOP PR56 2 1 2
DTC115EUA_SC70-3 20_0603_5% PQ20
3
1
1
PQ15 D D
1SS355_SOD323-2
1 2 5 20 1 2
3
ICOMP CSIN
5
6
7
8
2 PR58 PC31 6800P_0402_25V7K PC32 PR57 20_0603_5% DTC115EUA_SC70-3 PC109 2 PACIN
G 150K_0402_1% PC33 0.1U_0603_25V7K G
D
D
D
D
2
S 1 2 1 PR59 2 6 19 1 2 0.1U_0603_25V7K S
3
3
RHU002N06_SOT323-3 10K_0402_1% VCOMP CSIP PQ16
2
G
S
S
S
PC34 1 PR60 2 7 18 LX_CHG 2.2_0603_5%
100P_0402_50V8J 100_0402_1% ICM PHASE SI4800BDY-T1-E3_SO8
4
3
2
1
6251VREF PR229 0_0603_5%
1
2
8 17 DH_CHG 2 1 PL3 2
1
PACIN 1 2 2 1 2 0.1U_0402_16V7K 2.2_0603_5% 0.1U_0603_25V7K 2 3
<36> PACIN <30> IREF
2
PR64 G
1
22K_0402_1% S 15.4K_0402_1% 10.7K_0402_1% 10 15 6251VDDP CH751H-40PT_SOD323-2 PR62
3
ACLIM VDDP
5
6
7
8
6251VREF 1 PR66 2 PD10 0.02_2512_1%
10U_1206_25V6M
10U_1206_25V6M
RHU002N06_SOT323-3 PR68 1 26251VDD
D
D
D
D
2
ACON 10K_0402_1% 11 14 4.7_0603_5%
<36> ACON VADJ LGATE
1
1
2 PR69 1 PR67 PQ18
2
G
S
S
S
DTC115EUA_SC70-3 12 13 PC37
2
GND PGND 4.7U_0805_6.3V6K SI4800BDY-T1-E3_SO8 PC39
4
3
2
1
ACOFF 2
ISL6251AHAZ-T_QSOP24 DL_CHG
PR70
6251VREF 3 1 1 2
3
@ 28.7K_0402_1%
PR71
PQ40
@ 47K_0402_1%
BATT Type ALI/MH# Charge Current IREF CC=0.5~3A
2
@ SI2301BDS-T1-E3_SOT23-3
2
VMB
499K_0402_1% 340K_0402_1%
1
VS
PR73
6251VREF
0.01U_0402_25V7K
6251_EN
1
2
1
PC40
PR232
1
@ 100K_0402_1%
PR74
2
2
1
PC173 C
CSON 1 2 2 PQ53
B @ 2SC2411KT146_SOT23-3
2
1
8
@ 0.01U_0402_25V7K E PU5A
PR184
3
P
PR233 +
<30> BATT_OVP 1 2 1 0
@ 20K_0402_1% 2
-
105K_0402_1%
2
10K_0402_1%
0.01U_0402_25V7K
LM358DT_SO8
LI-3S :13.5V----BATT-OVP=1.5V
1
PR75
PC41
LI-4S :18V----BATT-OVP=2V
2
BATT-OVP=0.111*BATT+
2
4 4
IALAA-Minnesota10A LA3631P
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 38 of 45
A B C D
5 4 3 2 1
PJ18
B+ 2 2 1 1
@ JUMP_43X118
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
PC78
1
PC42
PC43
2
1
PC44
PC45
@ 680P_0402_50V7K
+VCC_TPS51120 VL
2
D PR76 D
2
5.1_0603_5%
2 1
1U_0603_10V6K
10U_0805_10V4Z
1
1
PC46
PC47
2
5
6
7
8
0.1U_0603_25V7K
D
D
D
D
PQ21
1
PC48
SI4800BDY-T1-E3_SO8
OCP=8A
8
7
6
5
G
S
S
S
2
PQ22 PR185 +5VALWP
D
D
D
D
4
3
2
1
0_0603_5%
SI4800BDY-T1-E3_SO8 PU6 PL5
OCP=8A 1 2
22 21 PR77 PC49 3.3UH_SIL1045R-3R3PF_8.2A_30%
VIN VREG5
G
S
S
S
0_0603_5% 0.1U_0603_25V7K 1 2
+3VALWP
10.2K_0402_1%
1000P_0402_50V7K
PR186 20 28 1 2 1 2
1
2
3
4
0_0603_5% V5FILT VBST1
5
6
7
8
2
PL6 1 2 PC50 PR79 9 27 DH_5V
EN5 DRVH1
330U_D3L_6.3VM_R25M
PR78
PC51
3.3UH_SIL1045R-3R3PF_8.2A_30% 0.1U_0603_25V7K 0_0603_5% PQ23
D
D
D
D
1000P_0402_50V7K
2
1
330U_D3L_6.3VM_R25M
10K_0402_1%
DH_3V 14 25 DL_5V
12
1
DRVH2 DRVL1
1
8
7
6
5
G
S
S
S
PC53
PC52
+
1
PR128 PQ24 LX_3V 15 24 @
D
D
D
D
4
3
2
1
LL2 PGND1
PR80
2
2
PC54
2.49K_0402_1%
C DL_3V 16 1 @ 680P_0603_50V7K C
2
DRVL2 VO1
1
G
2
S
S
S
PR81
@ 17 3 FB5
PGND2 VFB1
1
PC94 2
1
2
3
4
COMP1
8 7
1
@ 680P_0603_50V7K VO2 COMP2 TPS51120_CS1
23
2
CS1
2
4.22K_0402_1%
FB3 6 18 TPS51120_CS2
VFB2 CS2
VREF2 4
PR82
12 EN2 TONSEL 31
1000P_0402_50V7K
1 2 29 EN1 GND 5
30
1
SKIPSEL
PR105 0_0402_5% PGOOD1
19 VREG3 PGOOD2 11
+VCC_TPS51120
PAD
1
PC55
14.7K_0402_1%
10 EN3
14.7K_0402_1%
32
33
2
VL
2
PR83
TPS51120RHBR_QFN32_5X5
PR84
2
+3.3V_RTC_LDO
0_0402_5%
806K_0603_1%
1
2
PR85
1
10U_0805_6.3V6M
PR86
PR87
10K_0402_1%
1
1
PC56
1
PR88
PD11
2
1
0_0402_5%
2
2 1 1 2 1 PR89 2 +3VALWP
<6,36,37> MAINPWON VS
2.2U_0805_25V6K
100K_0402_1%
1
PC57 10K_0402_1%
2
0.047U_0603_16V7K RLZ5.1B_LL34
1
B B
PC58
PR90
2
1
@
POK <37,40>
A A
PJ14
2 1 B+
2 1
1
@ JUMP_43X118
1
PC59 PC60 PR91
1
4.7U_1206_25V6K 4.7U_1206_25V6K 0_1206_5%
PC61 PC62
2
4.7U_1206_25V6K 4.7U_1206_25V6K
2
1
+5VALWP 1
2
PC63 PD12
1
4.7U_0805_6.3V6K PC64 PR92 PC65
0.1U_0603_25V7K 2.2_0603_5% 2.2U_0805_10V6K
2
8
7
6
5
1
D
D
D
D
PQ25 DAP202U_SOT323-3
3
SI4800BDY-T1-E3_SO8
BST_1.2V-1
+1.8VP
G
S
S
S
BST_1.8V-1
1
2
3
4
PC66 PC67
14
28
+1.8VP 0.01U_0402_25V7K PU7 0.01U_0402_25V7K
5
6
7
8
PL7 2 1 12 SOFT1 17 2 1
VIN
VCC
1.8U_D104C-919AS-1R8N_9.5A_30% SOFT2
D
D
D
D
1 2 LX_1.8V PC68 PC69 PQ26
0.1U_0402_16V7K 0.1U_0402_16V7K SI4800BDY-T1-E3_SO8
<6> VDDIOFB_H
1 2 1 1 2BST_1.8V-2 6 23 BST_1.2V-2
1 2 2 1
BOOT1 BOOT2
+1.2VALWP
G
S
S
S
PR93 PR94
8
7
6
5
PC70 + PR95 0_0603_5% 0_0603_5%
4
3
2
1
1
@ 4.7_1206_5%
D
D
D
D
220U_D2_4VM_R15 @PR187 PR188 1 2 DH_1.8V-1 5 24 DH_1.2V-1 1 2 DH_1.2V-2 PL8 +1.2VALWP
2 0_0402_5% 0_0402_5% PR96 UGATE1 UGATE2 PR97 1.8U_D104C-919AS-1R8N_9.5A_30%
1
0_0603_5% 4 25 0_0603_5% LX_1.2V 1 2
PHASE1 PHASE2
G
S
S
S
PQ27
2
5
6
7
8
2
SI4810BDY-T1-E3_SO8 PR100 PR101
1
2
3
4
2
PC72 2K_0402_1% 2K_0402_1% PR99 2
D
D
D
D
2
ISEN1 ISEN2
1
1
PQ28
1
2 1
LGATE1 LGATE2
1
G
S
S
S
10K_0402_1% 0_0402_5% 0_0402_5% PC74 PR104 220U_D2_4VM_R15
PC71 PC75 0.01U_0402_25V7K 2.21K_0402_1%
2
4
3
2
1
0.01U_0402_25V7K @ 680P_0603_50V8J 2
2
2
3 26
1
PGND1 PGND2 DL_1.2V
9 VOUT1 VOUT2 20
VSE_1.8V 10 19 VSE_1.2V
VSEN1 VSEN2
<26,28,30,32,35> SYSON 1 2 8 EN1 EN2 21 1 2 POK <37,39>
PR107 15 16 PR106
0_0402_5% PG1 PG2/REF 0_0402_5%
GND
DDR
11 OCSET1 OCSET2 18
1
1
2
1
PR108 PR109 PR110
13
1
1
10K_0402_1% PR111 PC76 ISL6227CAZ-T_SSOP28 @ 0_0402_5% 6.49K_0402_1%
@ 0_0402_5% @ 0.1U_0402_16V7K PR113 PR112 PC77
100K_0402_1% 100K_0402_1% @0.1U_0402_16V7K
2
2
1
2
2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V / 1.2V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 40 of 45
A B C D
5 4 3 2 1
D D
PJ19 PU12
+3VS 2 2 1 1 2 VIN VO 3
+2.5VSP
1
@ JUMP_43X79 1 4
EN ADJ
2
PC91 PC92
4.7U_0805_6.3V6K 5 7 PR125 10U_1206_6.3V7K
1
GND GND 22K_0402_1%
1
6 8
2
GND GND
G965-18ADJP1UF_SO8
1
+3VS 1 2
PR126
PR127 20K_0402_1%
10K_0402_1%
2
PC93
0.1U_0402_16V7K
2
C C
+1.8V
1
PJ16
1
@ JUMP_43X79
2
PU9
2
1 VIN VCNTL 6 +3VALW
2 GND NC 5
1
1
PC97 3 7 PC98
4.7U_0805_6.3V6K PR136 VREF NC 1U_0603_6.3V6M
2
1K_0402_1% 4 8
B +3VS VOUT NC B
9
2
TP
1
APL5331KAC-TRL_SO8
PJ10
1
1
@ JUMP_43X79 PR138 +0.9VP
1
0_0402_5% D PR137
<35> SYSON#
2
1 2 2 1K_0402_1% PC99
1
PU10 G
2
2
1
1 6 +5VALW S PC100
2
VIN VCNTL PC101 PQ33 10U_1206_6.3V7K
2
2 5 @ 0.1U_0402_16V7K
2
GND NC
2
1
1
PC79 3 7 PC83
4.7U_0805_6.3V6K VREF NC 1U_0603_6.3V6M 0.1U_0402_16V7K
1
PR115 4 8 RHU002N06_SOT323-3
1.15K_0402_1% VOUT NC
9
2
TP
APL5331KAC-TRL_SO8
PQ29
RHU002N06_SOT323-3 +1.5VSP
1
D
SUSP 1 2 2
1
PC80
@ 0.1U_0402_16V7K
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9V//1.5V/2.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 41 of 45
5 4 3 2 1
5 4 3 2 1
+5VS
CPU_B+
+CPU_CORE
+3VS
B+
1
PL9
HCB4532KF-800T90_1812
PR189 1 2
D
10_0402_5% D
2200P_0402_50V7K
10K_0402_1%
220P_0603_50V8J
2.2U_0603_6.3V6K
0.1U_0603_25V7K
1
220U_25V_M
2.2U_0603_6.3V6K
1
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
PC143
+
1
PR190
PC149
PC144
PC145
PC146
PC147
PC148
2
5
PC151
2
2
2
PC150
PU13
2
MAX8774GTL+_TQFN40
1
8774VCC 19 25 4
PR191 0_0402_5% VCC VDD
2 1 D0 31 5 PR193 PC152 PQ42
<6> VID0 PR192 0_0402_5% D0 THRM 2.2_0603_5% 0.22U_0603_16V7K SI7840DP-T1-E3_SO8
2 1 D1 32 30 8774BST1
1 28774BST1A 1 2
3
2
1
<6> VID1 D1 BST1
PR194 0_0402_5% +CPU_CORE
2 1 D2 33 29 8774DH1 1 2 8774DH1A PL10
<6> VID2 PR196 0_0402_5% D2 DH1 PR195 0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
2 1 D3 34 28 8774LX1 1 2
<6> VID3 PR197 0_0402_5% D3 LX1
2
4.7_1206_5%
FDS6676AS_SO8
FDS6676AS_SO8
2 1 D4 35 26 8774DL1
<6> VID4 D4 DL1
5
6
7
8
D 5
D 6
D 7
D 8
PR198
PR199 0_0402_5%
1
2 1 D5 36 27
D
D
D
D
<6> VID5 D5 PGND1
PQ43
PQ44
PR201 0_0402_5% PR200
1
220P_0603_50V8J
EC31QS04
1 2 8774PWRGD 1 16 8774CSP1 4.22K_0402_1%
1
<30> VGATE PWRGD CSP1
PD17
G
G
S
S
S
S
S
S
+3VS 1 2 8774PHASEGD 17 15 8774CSN1
2
PHASEGD CSN1
1
PR202 PR203 PH3
4
3
2
1
4
3
2
1
1
PR205 100K_0402_1% 8774VCC 37 18 PC154 4700P_0402_25V7K 2.1K_0402_1% 10KB_0603_5%_ERTJ1VR103J
2
TWO-PH GND
PC153
0_0402_5% 1 2 1 2 1 2
2
<30> VR_ON 1 2 8774SHDN# 38 40 PR208 PR204
PR207 71.5K_0402_1% SHDN# IC 2K_0402_1% 10_0402_5%
C C
1 2 2 1 8774TIME 6 11 8774FB 1 2
2
PR206 TIME FB
1 2
@ 100K_0402_1% 2 1 8774CCV 8 9 8774CCI
1 2 N77 1 2 PC155
PC156 CCV CCI PC157 PR209 PR211 0_0402_5% 0.1U_0603_16V7K
1 2 150P_0402_50V8J 8774POUT 3 20 8774BST2 470P_0402_50V8J 20K_0402_1% 1 2
POUT PR210 POUT BST2
1
1 2 10K_0402_1% 1 2 8774REF 10 21 8774DH2
PC158 PC159 REF DH2 PC160 PC161
0.1U_0402_16V7K CPU_B+ 1 2 0.1U_0603_25V7K 8774TON 7 22 8774LX2 @ 220P_0402_25V8K @ 220P_0402_25V8K
2
PR212 TON LX2 PR214 10_0402_1%
8774REF 1 2 200K_0402_1% 8774OFS 2 24 8774DL2 1 2
OFS DL2
2
PR213
2.2_0603_5%
20K_0402_1% 4 23
VRHOT# PGND2
1
CPU_B+
PR215
PR216 PC162 2 18774SKIP# 39 SKIP# CSP2 13 8774CSP2
169K_0603_1% 470P_0402_50V8J
1
8774BST2A 1
1
PR217 14 8774CSN2
CSN2
GNDS
0_0402_5%
1 2
0_0603_5%
PR218
EP
PR219
0_0402_5%
+5VS
SI7840DP-T1-E3_SO8
2 PQ45
41
12
2
1
1
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
G RHU002N06_SOT323-3
PC163
PC164
PC165
S
3
PQ46
0.22U_0603_16V7K
2
1
4
1
1
PR220 PR221
100K_0402_1% 100K_0402_1% PC166
PC167
4700P_0402_25V7K PR222
2
2
10_0402_1%
2
3
2
1
2
B PL11 B
0.36UH_PCMC104T-R36MN1R17_30A_20% CPU_VCC_SENSE <6>
1 2
1
4.7_1206_5%
FDS6676AS_SO8
FDS6676AS_SO8
2 PQ47 PR223
5
6
7
8
D 5
D 6
D 7
D 8
2
PR224
G RHU002N06_SOT323-3 10_0402_5%
S
D
D
D
D
3
1
1
PQ48
PQ49
EC31QS04
PR225
2
220P_0603_50V8J
PD18
<6> PSI# 1 2 2 PQ50 <6> CPU_VSS_SENSE 4.22K_0402_1%
PR226 PMBT2222A_SOT23-3
1 1
1
G
G
S
S
S
S
S
S
0_0402_5%
3
4
3
2
1
4
3
2
1
2
PH4
PC168
PR227 10KB_0603_5%_ERTJ1VR103J
2
2.1K_0402_1%
1 2 1 2
8774DH2A
PC169
0.1U_0603_16V7K
1 2
1 2
PR228
1
0_0402_5%
PC170 PC171
@220P_0402_25V8K @ 220P_0402_25V8K
2
A A
37 Design change PF2 value Change PF2 Fuse from 12A to 15A
DVT
38 Design change PU4 schematic Add PR117,PR118.
Remove PR232,PR233,PC173,PC105
37 Design change PH1 temperature set value Change PR36 from 22K to 15.4K
PVT
Pre-MP 37 Design change PH1 temperature set value Change PR44 from 22K to 15.4K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 43 of 45
5 4 3 2 1
B
Rev 1A LA-3631P Implement items: B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, May 16, 2007 Sheet 44 of 45
5 4 3 2 1
5 4 3 2 1
PJP1
45@ Part
45@ DC-IN JACK
ZZZ
D PCB D
DAZ02500101 LA-3631P
U5 U5 U5 U26
CHIPSET(R1)
UMAR1@ RS690MC UMAR3@ RS690MC VGAR3@ RX690 SBR3@ SB600
U4 C473 U4 L46
LAN
8101E@ RTL8101E 8101E@ 1000P_0402_25V8J 8111C@ RTL8111C 8111C@ 0_0603_5%
C464
8101E@ 22U_A_4VM
R480
C C
8101E@ 0_0603_5%
U23
TRANSFORMER
100M@ TST1284
U11
Card BUS
8402@ PCI8402
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 15, 2007 Sheet 45 of 45
5 4 3 2 1
www.s-manuals.com