VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

EDT INSERTION LAB OBSERVATIONS

Test Case 1: -

Problem Definition: -

Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 2: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 2
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 3: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 3
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 4: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 4
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 5: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 5
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case6: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 6
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case7: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 7
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 8: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 8
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case9: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 9
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 10: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 10
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 11: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 11
VLSIGURU DFT TRAINING EDT INSERTION LAB OBSERVATIONS

Test Case 12: -

Problem Definition: -
Inputs: -

• Scan inserted Netlist

• ATPG Setup Dofiles( Dofile and testproc file from scan inserted step)
• Library Model
• Dofile commands

Outputs: -

• EDT inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?
3) How many resets?
4) Number of internal scan chains and external Scan Channel?
5) Is it top-down or bottom up approach?
6) How many terminal lockup latches are added?
7) Number of scan flops and non-scan flops in the design?
8) Chain length?
9) Number of DRC violations?
10) How many mask registers, hold registers?
11) Basic decoder or X-Decoder?
12) Log file: - please note your observations from the log file

Vlsiguru Confidential 12