1
Protection of Islanded Microgrid Fed by Inverters
Sukumar Brahma, Senior Member, IEEE, Nataraj Pragallapati, Member, IEEE, and Mukesh
Nagpal, Senior Member, IEEE
Abstract—As microgrids evolve and proliferate, with sharp
increase in renewable-fed distributed generation, islanded op-
eration of microgrids that are fed entirely by inverter-interfaced
renewables has become an imminent reality. Commercially avail-
able grid-forming inverters have made it technically possible to
form a stable microgrid island with other inverters following
in a coordinated controlled operation. For reliable operation of
islands, inverters participating in such islands may need to stay
connected during faulted conditions until the fault is isolated.
Though ample literature exists on protection of microgrids,
protection of islands entirely fed by inverters has not been
addressed well. This paper develops a simplified, yet accurate
model for an inverter-interfaced distributed energy resource, and
uses it to explore operation and protection issues in islanded
microgrids that arise due to the control and design of commercial
inverters.
Index Terms—Fault, inverter, island, microgrid, protection.
I. I NTRODUCTION
As penetration of renewable sources increases in power
distribution systems, these sources are expected to provide
substantial load support to microgrids, both in grid-connected
and islanded modes. It is now being conceived that the island
may not include a synchronous generator at all, the island
formed by a commercially available grid-forming inverter [1],
with other inverters following in droop based control to keep
the voltage and frequency at rated values [2], [3]. Such islands
have not been analyzed properly from a protection view-point.
Previous work performed at New Mexico State University
(NMSU) analyzed an actual microgrid on a US military base
with a mix of solar and synchronous (diesel) sources [4]. The
paper illustrated that the coordination of directional overcur-
rent devices achieved in grid-connected mode is not sustained
in islanded mode due to a relatively low fault contribution
from diesel generators, which results in relay operating times
in islanded mode being too large to be practical. The paper
showed that differential protection performs well in both grid-
connected and islanded modes. This conclusion is concurrent
with conclusions drawn by [5]. In the study, however, the
fault currents from diesel units are still large enough to be
detected by the overcurrent principle. Renewables, on the
other hand, connect through inverters that restrict their fault
contribution to values close to the rated load current (1.1 to
1.5 times being typical), thus making even detection of faults
difficult at the point of interconnection. Reference [6] analyzes
three approaches for such detection in grid-connected mode-
S. Brahma and N. Pragallapati are with the Klipsch School of Electrical
and Computer Engineering, New Mexico State University, Las Cruces, NM,
88003, USA (e-mail:{sbrahma;nataraj}@nmsu.edu), and M. Nagpal is with
BC Hydro, Canada (e-mail:Mukesh.Nagpal@bchydro.com).
This work was supported by the Sandia National Laboratories Grant PO
1596832.
978-1-5386-7703-2/18/$31.00 ©2018 IEEE
1) undervoltage, 2) zero-sequence overcurrent, 3) analysis of
transients at the inception of fault. Though largely successful,
the approaches cannot be guaranteed to perform reliably for
line-faults. Therefore, in case where the microgrid is fed just
by inverter-interfaced distributed energy resources (IIDERs),
fault detection, location, and isolation need to be properly
addressed. This paper engages in exploring such microgrids
in islanded conditions, which presents a greater challenge.
Ideally, such study should be performed with renewables
and inverters modeled in time-domain, feeding an islanded
unbalanced distribution network. This would give insight into
off-nominal frequency behavior in case of disturbances, which
may be valuable for control and stability studies. However,
to derive insight into the performance of legacy protection
schemes and principles, it is simpler and convenient to use a
fundamental-frequency model that accurately captures inverter
output during healthy and faulted state. This is the main
purpose of this paper.
The paper first shows behavior of a detailed time-domain
model of an IIDER with current-limiting function and low
voltage ride through (LVRT) capability built into its controls.
Then the paper shows the modeling of a voltage-controlled
current source in time-domain that mimics the behavior of
the IIDER in healthy and faulted state. The LVRT modeling
is important for islanded mode because inverters would be
expected to remain online during faults until the faulted section
is cleared, and provide reactive power for voltage-support
during fault-induced undervoltage conditions. Next, the paper
describes islanded operation of a 8-bus system derived from
the IEEE 13-node distribution feeder [7], using the simplified
IIDER model. Analysis is presented from both operational
and protection view points. Conclusions and future work are
outlined at the end.
II. T HREE PHASE G RID -C ONNECTED I NVERTER
The inverter modeled during previous work performed at
NMSU [6] was modeled as recommended in the National
Renewable Energy Laboratory (NREL) report [8], which de-
scribes the modeling of a commercial GE grid-connected
inverter. The output current was limited to 1.1 pu of the rated
inverter current. However, for the study under consideration,
LVRT feature is needed, which was added by creating a
reactive power reference mapped to the positive-sequence per
unit voltage at the inverter output. The inverter uses 900 V dc
voltage as input, and is rated at 480 V, 100 kW. Main features
of the inverter follow.
1) Voltage vector information at the Point of Common
Coupling (PCC) is extracted by using Phase Locked
Loop (PLL) under balanced and unbalanced PCC volt-
age. Double Synchronous Decoupled Reference based
 2

TABLE I
PLL [9] is used for the positive-sequence voltage vector DATA FOR TEST SETUP SHOWN IN F IG . 1
information at the PCC.
2) Independent control of active and reactive power un- Parameter Value Unit Description
der balanced and unbalanced PCC voltage is achieved Lf 2.6 mH filter inductance of inverter
Cf 20 µF filter capacitance of inverter
using separate positive and negative-sequence current (1)
Z1 3.75+j2.5 Ohm positive-sequence line impedance
controllers in synchronous rotating (dq) reference frame (0)
Z1 7.5+j6.3 Ohm zero-sequence line impedance
[10]. (1)
Z2 1.125+j1.02 Ohm positive-sequence line impedance
3) Fault Ride Through (FRT)/Low Voltage Ride Through (0)
Z2 7.25+j2.53 Ohm zero-sequence line impedance
(LVRT) feature includes fault detector, reactive power XT 0.05 pu transformer reactance
reference generation, maximum current limiter, and in-
jection of balanced currents to the PCC.
after a AG fault. Clearly, the current limiter and LVRT features
3-ϕ VSI Lf 3-ɸ Transformer
PCC are working properly. A simplified time-domain model was
Z1 Z2
Vdc
created in PSCAD as a voltage-controlled current source.
Cf
900V PSCAD allows to create an ideal current source with externally
Δ YG AC Grid
controlled magnitude and phase. The control was implemented
LC filter 0.48kV/4.16kV, Fault
6 100kVA
Pref
in form of a table as shown in TABLE II. The values can
md
SPWM mq
P & Q control with FRT
feature Qref be changed based on the requirements of any particular grid-
code, or any other current-limiter settings. The results using
this model for the system in Fig. 1 are shown in Fig. 3.
Fig. 1. Test setup showing the inverter connected to an ideal AC source.
They closely replicate the output characteristics of the inverter
(fault inception time is different), except for the transients at
fault-inception, which are not of interest in this study. This
simplified model is used in this study.
TABLE II
O UTPUT C HARACTERISTICS OF I NVERTER

Pos. Seq. Terminal Inverter Inverter

Voltage (pu) pf angle Current (pu)
1.0 0 1.0
0.9 0 1.0
0.8 -20 1.1
0.7 -40 1.1
0.6 -50 1.1
0.5 -60 1.1
0.4 -70 1.1
0.3 -80 1.1
0.2 -90 1.1
(a) 0.0 -90 1.1

200
Ia
180 Ib
160 Ic
140 P
120 Q
100
Currents(A), P (kW), Q(kVar)

80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
1.48 1.49 1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58
Time (s)

Fig. 3. Output of voltage-controlled current source for AG fault in Fig. 1.

(b)

Fig. 2. Output of inverter for AG fault in Fig. 1. (a) Currents. (b) Power.
The inverter model was tested by connecting it first to
an infinite bus, as shown in Fig. 1. The parameters of the
circuit are given in TABLE I. Fig. 2 (a) and (b) show the
inverter current and power output, respectively, before and
III. O PERATION OF I SLANDED MICROGRID FED BY
IIDER S
Though inverters can produce reactive power, they are
designed to operate at unity power factor under normal load
conditions. Therefore, the reactive power requirements in the
 3

islanded microgrid should be supplied by capacitors. Distribu-
tion systems are unbalanced, so there should be a negative and
zero-sequence current source available for viable operation.
This requirement is also imposed for faulted conditions, where
the negative and zero-sequence currents drawn may be higher.
This is where careful design is needed. Recall that unless
differently designed, inverters produce only positive-sequence
currents; the negative-sequence currents are forced to zero by
internally generating a negative-sequence voltage that cancels
the negative-sequence voltage imposed at the inverter terminal
from the system side. This changes the negative-sequence
circuit for IIDERs to the one shown in Fig. 4, where there
is a source of negative-sequence voltage that is exactly equal
and opposite to the negative-sequence voltage imposed by
the external system at the inverter terminals. In the figure,
negative-sequence impedance of the interfacing transformer is
included as Z (2) , so the voltages is conceived to be in per
(2)
unit. This forces the negative-sequence current Ia to zero.
the island under normal and faulted conditions, and develop
insight into protection of such islands. IIDERs are modeled as
voltage-controlled current sources, as described in Section II.
Since this paper is aimed at proof-of-concept, the microgrid,
though derived from the 4.16 kV, 13-node IEEE distribution
system test feeder [7], is reduced to a three-phase, 8-node
system, shown in Fig. 5. A source comprising of two voltage-
controlled current sources of 100 kW each is connected to
nodes 1, 5, and 6 (marked in red), placing maximum inverter
output at 600 kW. The loads for balanced and unbalanced cases
are given in TABLE III. The real power load is less than the
inverter capacity. The reactive power load is supplied by a 600
kVar capacitor bank connected to node 6.

- _
( 2)
Va
+ Va
( 2) (a)

Z ( 2) Ia
( 2)

Fig. 4. Sequence circuit of inverter-source.

This poses an interesting question as to the source of the

negative-sequence currents to feed the unbalanced load and
all unbalanced faults. These currents can only be sourced
by capacitor bank. Since the amount of negative-sequence (b)
current is dictated by the type of fault, and the amount of
negative-sequence current that can be sourced by a capacitor
bank depends on the reactance (and hence the size) of the
capacitor bank, design of capacitor bank is an important
consideration in configuration of IIDER-fed islands. In the
absence of a capacitor bank in such an island, the negative-
sequence currents will be forced to flow through the Y G side
of the interfacing transformer, forcing the transformer into
saturation due to absence of the balancing ampere-turns on
the inverter-side of the transformer.
(c)
7 5
1

2 3 4

8 Fault
6

Fig. 5. Test system.

IV. S IMULATION OF I SLANDED MICROGRID FED BY (d)

IIDER S Fig. 6. Test results for a BC fault in the 8-bus test system. (a) Inverter
The purpose of this section is to simulate an islanded currents. (b) Inverter power. (c) Capacitor bank current contribution. (d)
Currents in faulted section.
microgrid fed only by IIDERs, describe the operation of
 4

TABLE III
L OAD DETAILS FOR THE TEST SYSTEM IN F IG . 5

Node Balanced Unbalanced Case (kVA) - Phases

Case (kVA) a, b, c
1 0 0, 0, 0
2 0 0, 0, 0
3 150+j80 50+j26.67, 50+j26.67, 50+j26.67
4 30+j20 10+j6.67, 10+j6.67, 10+j6.67
5 0 0, 0, 0
6 200+j150 130+j45, 65+j25, 5+j80
7 100+j200 70+j80, 20+j90, 10+j45
8 100+j150 65+j45, 35+j25, 15+j80
(a)
Total 580+j600 325+j205, 180+j175, 90+j240

The system is modeled in PSCAD environment, and a

fault is created on the line between nodes 3 and 4. Fig. 6
(a) - (c) show the current and power output of one of the
three sources (other two sources deliver similar output), and
sequence currents from the source as well as from the capacitor
bank for a line-to-line fault between B and C phases, with 10
Ω fault resistance. Notice the currents increase by 10% during
fault, and all the negative-sequence currents are contributed
solely from the capacitor bank. Interestingly, the sources do (b)
not contribute much reactive power during fault, despite the
depressed voltages. This is because the small increase in
currents during fault increases the reactive losses only by a
small amount. Plus, the depressed voltages during fault result
in lower reactive power drawn by the loads. Therefore, the
reactive power demand during fault is met mainly by the
capacitor bank.
Fig. 6 (d) shows the currents at both ends of the faulted
section, and the differential current. Clearly, overcurrent-based
fault detection is impossible at either end, but the differential
current is still large enough to detect the fault. Notice that in a (c)
conventional 4.16 kV system, this fault would have produced
a fault current of about 4160/10 = 416 A, superimposed
on the pre-fault current, which would be easily detectable
by an overcurrent relay. It was also observed that this fault
created significant undervoltage on the faulted phases all over
the system; the voltages at all nodes dropped to between
50-55% of their respective pre-fault values. Comparing the
undervoltage-results with those obtained in the previous study
of grid-connected microgrids described in [6], it is observed (d)
that for the same fault, the voltages in purely IIDER-fed
microgrid are generally more suppressed, compared to a Fig. 7. Test results for a AG fault in the 8-bus test system. (a) Inverter
currents. (b) Inverter power. (c) Capacitor bank current contribution. (d)
microgrid fed by conventional sources, or connected to grid. Currents in faulted section.
This is because the fault will dictate the low voltage at the
faulted point (assume negligible fault resistance to understand
the argument) in either case, but the low fault currents flowing
in the lines in an IIDER-fed microgrid will result in smaller current contribution from one source, sequence current contri-
voltage drops across lines, and hence much lower voltages bution from the capacitor bank, currents at both ends of the
all over the system. This opens up an opportunity to detect faulted section, and differential current for that section. Notice
fault using the undervoltage principle, not just at the faulted the zero-sequence currents are sourced by the Y G winding
line, but even at the point of connection of inverters. Study of the interfacing transformer, and negative-sequence currents
reported in [6] showed that undervoltage settings could fail to are sourced by the capacitor bank. Interestingly, even with the
detect faults at the inverter terminals for remote faults, in the zero-sequence current, the fault currents at both ends do not
grid-connected case. increase substantially, due to the limitation on the positive-
The fault is now changed to AG with 1Ω fault resistance. sequence current-sources. Zero-sequence based overcurrent
The resistance was kept low to maximize the fault currents detection may work, provided the unbalance in load is not
in this case. Fig. 7 shows the currents, power and sequence very high (see next case). However, again, the voltages all over

the system dropped to less than 10% of their respective pre-
fault values (recall low fault resistance for this case), showing
excellent promise for undervoltage based fault detection.
(a)
(b)
Fig. 8. Test results for a AG fault (Rf = 10Ω) in 8-bus test system with
unbalanced load. (a) Inverter currents. (b) Node-3 voltages.
Finally, unbalanced loads are modeled as shown in TA-
BLE III. AG fault is created with 10 Ω fault resistance.
Fig. 8 (a) shows the phase and sequence currents from one
of the sources, and Fig. 8 (b) shows the phase voltages at
node-3. It can be seen that significant zero-sequence current
is contributed before fault as well, but zero-sequence based
fault detection is still possible. Though undervoltage-based
fault detection is found viable in this case, the voltages during
load are highly unbalanced. This is markedly different than the
grid-connected case [6], where the unbalance in load voltages
was within permissible limits due to the balanced firm voltage
source provided by the grid. Fig. 8 (b) clearly shows that the
positive-sequence load voltage is nearly rated (2.22 kV/ph),
but the individual phase voltages rise up to about 1.2 per unit.
This is despite the capacitor bank rating being reduced to 300
kVA (half than the balanced case). Since the capacitor bank
has to be sized to provide adequate negative-sequence currents
as well, the overvoltages create a conflict in the sizing criteria.
It is advisable to keep the loads mostly balanced in IIDER-fed
islands.
V. C ONCLUSION AND F UTURE W ORK
The paper first describes the fault response of an inverter
designed with current limiter and LVRT feature. It is shown
that a voltage-controlled current source implemented in time
domain mimics the characteristics of this inverter at fundamen-
tal frequency. This source is then used to analyze an islanded
microgrid fed exclusively by IIDERs. A 8-bus microgrid is
tested under balanced and unbalanced load-conditions. The
outcome of the analysis from design point of view is that
5
there needs to be a capacitor bank to source the negative-
sequence currents to feed load unbalance and unbalanced
faults. However, under unbalanced operation, due to the lack of
a firm balanced voltage source typically provided by the grid in
grid-connected mode, there is significant voltage unbalance in
the microgrid, leading to marked overvoltages in some phases.
This may introduce a conflicting requirements in sizing the
capacitor bank, unless loads are intentionally kept reasonably
balanced. In terms of protection, as expected, the overcurrent
principle is simply not viable to detect phase faults, but zero-
sequence currents may still provide ground fault detection, if
the interfacing transformer has Y G connection on the grid
side. Undervoltage principle emerges as a promising fault
detection technique, because the low voltage created at the
fault-point pervades the entire microgrid due to unusually low
line currents, resulting in rather small voltage drops in feeders.
Future work will focus on a larger unbalanced microgrid to
further verify the results and analysis presented in this paper,
incorporating protection schemes in the study and evaluating
their performance, and report results from a field test of an
islanded microgrid.
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