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ECE 010
Reginald Phelps Laguna, ECE, ECT
Boylestad, R.& Floyd, T. (2012). Bishop O. (2011). Sabah, N. (2010).
Nashelsky, L. Electronic devices: Electronics: Electronics Basic,
(2013). Electronic Conventional Circuits and Analog & digital
Devices and Circuit current version, Systems, (4th ed.). with Pspice. CRC
Theory, (11th ed.). (9th ed.). Amsterdam :
Upper Saddle Boston:Pearson Elsevier
River, New Jersey:
Pearson Education,
Inc.
 5S
 Attendance
 Syllabus
 Seating Arrangement (Seat Plan)
 EDMODO
CIRCUITS 1 AND ELECS 1
REVIEW
Reginald Phelps Laguna, ECE, ECT
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ECE 402
Reginald Phelps Laguna, ECE, ECT
ILOs & TRANSISTOR MODELLING

TWO-PORT SYSTEMS

BJT & FET MODELING

EFFECT OF SOURCE IMPEDANCE RS

EFFECT OF LOAD IMPEDANCE RL

RL & RS COMBINED EFFECT

BJT & FET NETWORKS

ASSESSMENTs
 ILOs
Students will be able to:

a. Learn to use the equivalent model to find the important ac

parameters for an amplifier.
b. Be able to perform a small-signal ac analysis of a variety of BJT and
FET configurations.
c. Become aware of the general ac characteristics of a variety of
important BJT and FET configurations.
d. Understand the effects of a source resistor and load resistor on the
input impedance, output impedance and overall gain.
e. Begin to appreciate the design sequence applied to BJT and FET
configurations.
 TRANSISTOR MODELLING
A model is a combination of circuit elements properly chosen that
best approximates the actual behavior of a semiconductor device
under specific operating conditions.

RE Hybrid
Equivalent
Model
Model
 TWO-PORT SYSTEMS
Input and Output system.

• Input side - signal is normally applied

• Output side - load is connected

IMPEDANCE
In amplifier it is resistance but in true
nature it is combination of resistance and
reactance. It is has very high impedance
approaches to infinity.
 TWO-PORT SYSTEMS : IMPEDANCEs (Zi, Zo)
Input Impedance, Zi Output Impedance, Zo

s
 IMPEDANCEs (Zi, Zo)
Board Work 1 (BW1):

6.67mV

1.5kΩ

42.5kΩ
TWO-PORT SYSTEMS : GAIN (Av, Ai)
Voltage Gain, Av Current Gain, Ai

RL = ∞Ω
 GAIN
Board Work 1 (BW1):

For the BJT amplifier, determine:

a. Vi
b. Ii R = 1.2 kΩ
s
+
c. Zi BJT
Zi Amplifier Vo = 7.68 V
d. Avs
AVNL = 320
Vi
Vs = 400 mV
-
 GAIN
Board Work 1 (BW1):
 GAIN
Board Work 1 (BW1):
 BJT MODELING
The superposition theorem is applicable for the analysis and design of the dc and ac
components of a BJT network, permitting the separation of the analysis of the dc and
ac responses of the system.

Hybrid Equivalent Networks

• Most frequently employed in the formative years of transistor network analysis.
• Specification sheets included the parameters in their listing, and analysis was simply
a matter of inserting the equivalent circuit with the listed values.
• Drawback: defined for a set of operating conditions that might not match the actual
operating conditions.
re model
• Became a desirable approach since important parameter of the equivalent circuit
was determined by the actual operating conditions rather than using a data sheet
value that in some cases could be quite different.
• Reduced version of hybrid π model.
• Drawback: No feedback term that can be important.
Hybrid π Modeal
• High frequency analysis.
• Has feedback connection to consider output voltage effect to input quantities.
 BJT MODELING: CE
General Steps:
1. Setting all dc sources to
zero and replacing them by
a short-circuit equivalent
2. Replacing all capacitors by
a short-circuit equivalent
3. Removing all elements
bypassed by the short-
circuit equivalents
introduced by steps 1 and
2
4. Redrawing the network in
a more convenient and
logical form
BJT MODELING: CE
BJT MODELING: CE
 BJT MODELING
Draw the equivalent AC model of the following:
BJT MODELING: CE – Fixed Bias
 BJT MODELING: CE – Fixed Bias
a. Determine re .
b. Find Zi (with ro = ∞Ω).
c. Calculate Zo (with ro = ∞Ω).
d. Determine Av (with ro = ∞Ω).
e. Repeat parts (c) and (d) including ro = 50 kΩ in all
calculations and compare results.
BJT MODELING: CE – Voltage Divider Bias
 BJT MODELING: CE – Voltage Divider Bias
a. Determine re .
b. Find Zi.
c. Calculate Zo (with ro = ∞Ω).
d. Determine Av (with ro = ∞Ω).
e. Repeat parts (b) through (d) including ro = 50 kΩ
and compare results.
BJT MODELING: CE – Unbypassed Emitter Bias
 BJT MODELING: CE – Unbypassed Emitter Bias
Effect of ro.
 BJT MODELING: CE – Unbypassed Emitter Bias
Find: re, Zi, Zo, Av.
 BJT MODELING: CE – Unbypassed Emitter Bias
With CE connected, Find: re, Zi, Zo, Av.
BJT MODELING: EMITTER-FOLLOWER
 BJT MODELING: EMITTER-FOLLOWER
Find:
a. re.
b. Zi.
c. Zo.
d. Av.
e. Repeat parts (b) through (d) including ro = 25 kΩ
and compare results.
BJT MODELING: EMITTER-FOLLOWER
BJT MODELING: CB
 BJT MODELING: CB
Find:
a. re.
b. Zi.
c. Zo.
d. Av.
e. Ai.
BJT MODELING: CE – Collector Feedback Bias
 BJT MODELING: CE – Collector Feedback Bias
Effect of ro.
 BJT MODELING: CE – Collector Feedback Bias
Find:
a. re.
b. Zi.
c. Zo.
d. Av.
e. Repeat parts (b) through (d) including ro = 20 kΩ
and compare results.
BJT MODELING: CE – Collector Feedback Bias
 FET MODELING
The gate-to-source voltage controls the drain-to-source current of a JFET.
Shockley’s Equation: Graphically:
JFET, D-MOSFET, & D-MESFET

E-MOSFET & E-MESFET

Effect of ID on gm:
Mathematically:
 FET MODELING
For a JFET with IDSS = 8 mA and VP = -4 V:
a. Find the maximum value of gm .
b. Find the value of gm at VGS = (i) -0.5V, (ii) -1.5V, (iii) -2.5V
FET MODELING: Fixed Bias
 FET MODELING: Fixed Bias
Given: VGSQ = -2V, IDQ = 5.625mA, IDSS = 10mA, VP = -8V,
a. Determine gm .
b. Find rd.
c. Determine Zi.
d. Calculate Zo.
e. Determine the voltage gain Av.
f. Determine Av ignoring the effects of rd.
FET MODELING: Self-Bias (RS Bypassed)
FET MODELING: Self-Bias (RS Unbypassed)
 FET MODELING: Self-Bias
Given: VGSQ = -2.6V, IDQ = 2.6mA, IDSS = 8mA, VP = -6V, gos =20μS
a. Determine gm .
b. Find rd.
c. Find Zi.
d. Calculate Zo with and without rd.
e. Calculate Av with and without rd.
FET MODELING: Self-Bias
FET MODELING: Voltage-Divider
FET MODELING: CG
 FET MODELING: CG
Given: VGSQ = -2.2V, IDQ = 2.03mA,
a. Determine gm .
b. Find rd.
c. Calculate Zi with and without rd.
d. Find Zo with and without rd.
e. Determine Av with and without rd.
FET MODELING: CG
FET MODELING: CD (Source Follower)
 FET MODELING: CD (Source Follower)
Given: VGSQ = -2.86V, IDQ = 4.56mA,
a. Determine gm .
b. Find rd.
c. Determine Zi.
d. Calculate Zo with and without rd.
e. Determine Av with and without rd.
FET MODELING: CD (Source Follower)
 EFFECT OF SOURCE IMPEDANCE RS
• The effect of the internal resistance on the gain of the amplifier,
the parameters Zi and AVNL of a two – port system are
unaffected by an internal resistance of the applied source.

• The output impedance may be affected by the magnitude of RS.

EFFECT OF SOURCE IMPEDANCE RS

Vs – IsRs – Vi = 0 By Voltage divider,

Is = Vs – Vi Vi = Zi Vs (1)
Rs Zi + Rs
Vo = AVNL Vi (2)
Vs – IsRs –IsZi = 0
From eq. (1) to (2)
Vs – Is(Rs + Zi) = 0
Vo = AVNL Zi Vs
Is = Vs
Zi + Rs
Rs + Zi
Avs = Vo = AVNL Zi
Vs Zi + Rs
 EFFECT OF SOURCE IMPEDANCE RS
In the figure, a source with an
internal resistance has been
applied to the fixed bias
transistor amplifier.

a. Determine the voltage

gain Avs = Vo/Vs, what
percent of the applied
signal appears at the input
terminals of the amplifier?
b. Determine the voltage
gain Avs = Vo/Vs, using re
model
 EFFECT OF SOURCE IMPEDANCE RS
a. By dc analysis:
12 V – 470 kΩIB – 0.7 V = 0
IB = 24.04 µA
IE = (β+1)IB
= (100 + 1) 24.04 µA
IE = 2.43 mA
re = 26 mV = 26mV
IE 2.43 mA Vi = Zi Vs
re = 10.71 Ω Zi + Rs
Vi = Zi
Avs = AVNLZi
Vs Zi + Rs
Zi + Rs
= 1.071 kΩ
= (– 280.11)(1.071 kΩ)
1.071 kΩ + 0.5 kΩ
1.068 kΩ + 0.5 kΩ
Vi = 0.6811 or 68.11%
Avs = – 190.96
Vs
 EFFECT OF SOURCE IMPEDANCE RS
b. Using re model
Vs – IbRs – IbZi = 0
Vs – Ib (Rs + Zi) = 0
Ib = Vs
Rs + Zi (1)
Vo = – Rc βIb (2)
Avs = Vo = – Rc β
From eq. (1) to (2), Vs Rs + Zi
Vo = – Rc β Vs = – (3 kΩ)(100)
Rs + Zi 0.5 kΩ + 1.071 kΩ
Avs = – 190.96
 EFFECT OF LOAD IMPEDANCE RL
• For the no-load situation, the current gain is undefined because the
load current is zero. There is, however, a no-load voltage gain equal
to AvNL.

• Ideally, all the parameters of the model are unaffected by changing

loads and levels of source resistance. However, for some transistor
configurations the applied load can affect the input resistance,
whereas for others the output resistance can be affected by the
source resistance.
• In all cases, however, by simple definition, the no-load gain is
unaffected by the application of any load.
• The loaded voltage gain of an amplifier is always less than the no-
load level: AvL << AvNL
 EFFECT OF LOAD IMPEDANCE RL
In the figure, a load has been
applied to the fixed-bias
transistor amplifier

a. Determine the voltage and

current gain using the
two-port systems
approach
b. Determine the voltage and
current gain using the re
model and compare
results.
EFFECT OF LOAD IMPEDANCE RL
 RL & RS COMBINED EFFECT
• A source of RS and a load of RL have been applied to a two –
port system for which the parameters Zi, AVNL and Zo have been
specified V cc

RC
RB
 RL & RS COMBINED EFFECT
The larger the source resistance and/or
smaller the load resistance, the less the
overall gain of an amplifier.

Ai = – Av Zi
RL
Applying Voltage Divider:
At the input side At the output side, Ais = Io
Vi = Vs Zi Vo = AVNL Vi RL Is
Rs + Zi Zo + RL – Vo
Vi = Zi Av = Vo = AVNL RL RL
Vs Rs + Zi Vi Zo + RL = Vs
Avs = Vo = Vo Vi Rs + Zi
Vs Vi Vs Ais = – Avs Rs + Zi
Avs = AVNL RL Zi RL
Zo + RL Rs + Zi
 COMBINED EFFECT OF RL AND RS
For the single stage amplifier
with RL = 4.7 kΩ and RS =
0.3 kΩ determine:
a. Avs
b. Av
c. Ai
d. Ais
 COMBINED EFFECT OF RL AND RS
DC Analysis:
12 V – 470 kΩIB – 0.7 V = 0
IB = 24.04 µA
Zi = RB//βre
IE = (β+1)IB
= 470 kΩ//(100)(10.70 Ω)
= (100 + 1) 24.04 µA
Zi = 1.071 kΩ
IE = 2.43 mA
re = 26 mV AVNL = – Rc
IE re
= 26 mV = – 3 kΩ
2.43 mA 10.7 Ω
re = 10.70 Ω AVNL = – 280.37
 COMBINED EFFECT OF RL AND RS
a. Avs = AVNL RL Zi
Zo + RL Rs + Zi
= (– 280.37)(4.7 kΩ)(1.07 kΩ)
(3 kΩ + 4.7 kΩ)(0.3 kΩ + 1.07 kΩ)
Avs = – 133.66
d. Ais = – Avs Rs + Zi
b. Av = AVNL RL RL
Zo + RL = – (– 133.66)(0.3 kΩ + 1.07 kΩ)
= (– 280.37)(4.7 kΩ) 4.7 kΩ
(3 kΩ + 4.7 kΩ) Ais = 38.96
Av = – 171.13
c. Ai = – Av Zi
RL
= – (– 171.13) (1.07 kΩ)
4.7 kΩ
Ai = 38.96
 BJT NETWORKS : RL & RS Combined Effect
The loaded voltage gain of an amplifier is always less than the no-load gain.

The gain obtained with a source resistance in place will always be less than that
obtained under loaded or unloaded conditions due to the drop in applied voltage
across the source resistance.

For the same configuration AVNL > AVL > AVS.

For a particular design, the larger the level of RL , the greater is the level of ac gain.

For a particular amplifier, the smaller the internal resistance of the signal source, the
greater is the overall gain.

For any network that have coupling capacitors, the source and load resistance do not
affect the dc biasing levels.

When one purchases a packaged amplifier, the listed gain and all the other parameters
are for the unloaded situation. The gain that results due to the application of a load or
source resistance can have a dramatic effect on all the amplifier parameters.
BJT NETWORKS: CE – Fixed Bias
BJT NETWORKS: CE – Fixed Bias

Source Transformation
 BJT NETWORKS: CE – Fixed Bias
With RL = 4.7kΩ and RS = 0.3kΩ, Find:
a. AVL.
b. AVS.
c. Zi
d. Zo
BJT NETWORKS: CE – Voltage Divider Bias
BJT NETWORKS: CE – Voltage Divider Bias
BJT NETWORKS: CE – Unbypassed Emitter Bias
BJT NETWORKS: EMITTER-FOLLOWER
 BJT NETWORKS: EMITTER-FOLLOWER
Given: Zi = 157.54kΩ, Zo = 21.6Ω, AVNL = 0.993, and re = 21.74Ω.
Find:
a. New Zi and Zo as an effect of RS and RL.
b. AV.
c. AVS.
d. Ai.
BJT NETWORKS: EMITTER-FOLLOWER
BJT NETWORKS: CE – Collector Feedback Bias
 BJT NETWORKS: CE – Collector Feedback Bias
Given: AVNL = - 238.94, Zo = 2.66kΩ, Zi = 0.553kΩ, re = 11.3Ω.
Find:
a. AV.
b. AVS.
c. Ai.
BJT NETWORKS: CE – Collector Feedback Bias
BJT NETWORKS: CB
 BJT NETWORKS: CB
Given:
Zi = re = 20Ω
AVNL = 250
Zo = 5kΩ
Find:
a. AV.
b. AVS.
c. Ai.
 FET NETWORKS: RL & RS Combined Effect
All of the two-port equations developed
for the BJT transistor apply to FET
networks also because the quantities of
interest are defined at the input and
output terminals and not the components
of the system.

The greatest gain of an amplifier is the no-load gain.

The loaded gain is always less than the no-load gain.
A source impedance will always reduce the overall gain below the no-load or loaded
level.

Due to the high impedance between the gate terminal and the channel, one can
generally assume that the input impedance is unaffected by the load resistor and the
output impedance is unaffected by the source resistance.

The no-load two-port model for an FET amplifier is unaffected by an applied load or
source resistance.
 FET NETWORKS: Self-Bias
RS Bypassed RS Unbypassed
 FET NETWORKS: Self-Bias
Given: AVNL = -3.18, Zi = 239kΩ, Zo = 2.4kΩ, gm = 2.2mS
a. Using Two-Port model, find AV, and AVS.
b. Calculate loaded gain using the equation.
FET NETWORKS: Source Follower
FET NETWORKS: CG
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ECE 402
Reginald Phelps Laguna, ECE, ECT
ILOs

LOGARITHM

DECIBELS

GENERAL FREQUENCY CONSIDERATIONS

LOW-FREQUENCY ANALYSIS : BODE PLOT

LOW-FREQUENCY RESPONSE - BJT & FET

HIGH-FREQUENCY RESPONSE - BJT & FET

ASSESSMENTs
 ILOs
Students will be able to:

a. Discuss the principles of logarithms

b. Derive the different properties of common logarithm and natural
logarithm
c. Define the concept of decibels and its relationship to amplifier
operations
d. Illustrate the frequency response of the three coupled amplifiers
e. Discuss the frequency response curve for each type of coupled
amplifier
f. Apply skills and techniques in solving common electronic problems
g. Explain the low and high frequency response of audio amplifiers
h. Discuss Bode plotting by solving the involved parameters
i. Analyze the low and high frequency responses of BJT amplifier using
Bode plot.
 LOGARITHM
a = bx
log a = x log b Common Logarithms x = log10 a = log a
x = log a Natural Logarithms y = loge a = ln a
log b loge a = 2.3 log10 a
x = logb a

• Properties s Ex. 1:
• log10 1 = 0
• log10 a = log10 a – log10 b
b
• log10 1 = – log10 b
b
• log10 ab = log10 a + log10 b
LOGARITHM
 LOGARITHM
Board Work 1 (BW1):
Using the calculator, determine the logarithm or antilogarithm of the
following numbers.
(a) log10 64. (a) 1.806
(b) loge 64. (b) 4.159
(c) log10 1600. (c) 3.204
(d) log10 8000. (d) 3.903
(e) log10 106. (e) 6
(f) ln e3. (f) 3
(g) log10 10-2. (g) -2
(h) loge e-1. (h) -1
(i) 1.6 = log10a. (i) 39.81
(j) 0.04 = logea. (j) 1.041
(k) log100.5 (k) -0.3
(l) log10(4000/250) (l) 1.204
(m) log10(0.6*30) (m) 1.255
LOGARITHM [Semi-Log Graph]
 LOGARITHM [Semi-Log Graph]
To determine the logarithmic level at a particular point between known levels using a
ruler or simply estimating the distances:
d1
Value = 10x x 10d1/d2
10x 10x+1
Ex 2: d2
Determine the value of the point appearing in the logarithmic plot below using the
measurements made by a linear ruler.

Sol: 7/16 “
d1/d2 = [7/16”]/[3/4”] = 3.837
Value = 10x x 10d1/d2 = 102 x 103.837
= 383.7
100 1000
3/4 “
 DECIBELS
• The relationship of logarithm to power and audio levels
• logarithm of a gain or loss
• The term bel (B) was derived from the surname of Alexander
Graham Bell
AP = P2 AV = V2 AI = I2 GdBv = 20 log10 V2
P1 V1 I1 V1
G = log10 P2 GdBi = 20 log10 I2
P1 I1
GdB = 10 log10 P2 GdBm = 10 log10 P2
P1 1 mW

AT = A1*A2*…*An
GdBT = GdB1 + GdB2 +…+ GdBn
GT = G1 + G2 + … + Gn
 DECIBELS
BW2:
1. Find the magnitude gain corresponding to a voltage gain of
100dB. 100,000
2. The input power to a device is 10 kW at a voltage of 1 kV. The
output power is 500 W, while the output impedance is 20 Ω.
(a) Find the power gain in dB. (b) Find the voltage gain in dB.
-13.01dB; -20dB
3. An amplifier rated at 40 W output is connected to a 10 Ω
speaker. (a) Calculate the input power required for full power
output if the power gain is 25 dB. (b) Calculate the input
voltage for rated output if the amplifier voltage gain is 40 dB.
126.5mW; 200mV
 GENERAL FREQUENCY CONSIDERATIONS
Analysis so far has been for mid-frequency spectrum.

Low-Frequency Mid-Frequency High-Frequency

• [1μF] Large • Capacitance • [5pF] Small

Capacitance ignored* Capacitance
f (Hz) XC (Ω) f (Hz) XC (Ω)
10 15.91k 10 3,183M*
100 1.59k 100 318.3M*
1k 159 1k 31.83M*
10k 15.9 10k 3.183M*
100k 1.59* 100k 318.3k
1M 0.159* 1M 31.83k
10M 15.9m* *lesser concern: 10M 3.183k
100M 1.59m* Short or Open 100M 318.3
 GENERAL FREQUENCY CONSIDERATIONS
The mid-range frequency
RC-coupled.
range of an amplifier is
called the bandwidth of the
amplifier.

The bandwidth is defined

by the difference between
the upper (f2 or fH) and Transformer-coupled.
lower (f1 or fL) cutoff
frequencies.

Cutoff – any frequency at

which the gain has dropped
by 3 dB. Direct-coupled.

f1 and f2 are generally

called corner, cutoff, band,
break, or half-power
frequencies.
 GENERAL FREQUENCY CONSIDERATIONS
0.707Avmid was chosen for cut-off gain levels since it responds to half midband output
power.

NORMALIZATION:
The gain at each frequency is divided by the midband value.

Normalized gain versus frequency plot.

Decibel plot of the normalized gain versus frequency plot.

 NORMALIZATION PROCESS
BW3:
a. Find the cutoff frequencies fL and fH using the measurements provided.
b. Find the bandwidth
c. Sketch the normalized response
NORMALIZATION PROCESS
 LOW FREQUENCY ANALYSIS
It can be established for each capacitive element and the frequency at which the
output voltage drops to 0.707 of its maximum value.
 LOW FREQUENCY ANALYSIS

Vo = R Vi
R + Xc
Vo = R
Vi (R2 + Xc2) ½ ; Xc = R
Vo = R
Vi (R2 + R2) ½
Vo = R
Vi R(2) ½
Vo = 0.707
Vi
3dB drop in gain from the midband
level when f = f1. An RC network will
determine the low-frequency cut-off
frequency for a BJT transistor
 BODE PLOT
A Bode plot indicates the frequency response of an amplifier.

The horizontal scale indicates the frequency (in Hz) and the vertical scale indicates
the gain (in dB).

Ex:
 BODE PLOT
Av = Vo Vo = 1 Av = 20 log Vo
Vi Vi 1 – jf1 ;f = f1 Vi
Vo = RVi f = 20 log 1
R – jXc Vo = 1 (1) 2 + (f1/f) 2
Vo = 1 Vi 1 – j = 20 log [(1) 2 + (f1/f) 2 ] – ½
Vi 1 – jXc Vo = 1 = – 10 log [(1) 2 + (f1/f) 2 ] – ½
R V1 [(1) 2 + (– 1)2]1/2
= – 10 log (f1/f) 2
Vo = 1 Vo = 1 Av = – 20 log f1
Vi 1 – 1 Vi (2) ½ f
j2𝛑fC Av = 0.707
R
f = f1 = 1; –20log 1 = 0
f = f1/2 = 2; –20log 2 = –6
f = f1/4 = 4; –20log 4 = –12
f = f1/10 = 10; –20log 10 = –20
 BODE PLOT

• The piecewise linear plot of the asymptotes and associated breakpoints is called a
Bode plot of the magnitude versus frequency.
• A change in frequency by a factor of two, equivalent to one octave, results in a 6-dB
change in the ratio, as shown by the change in gain from fL/2 to fL.
• For a 10:1 change in frequency, equivalent to one decade, there is a 20-dB change in
the ratio, as demonstrated between the frequencies of fL/10 and fL.
 BODE PLOT
BW4:
a. Determine the break frequency
b. Sketch the asymptotes and locate the -3dB point.
c. Sketch the frequency response curve.
d. Find the gain at Av(dB) = -6dB
 LOW-FREQUENCY RESPONSE - BJT AMPLIFIER
At low frequencies, coupling capacitor (CS,
CC) and bypass capacitor (CE) reactances
affect the circuit impedances.

CS CC CE
1 1 1
f Ls  f LC  f LE 
2(R s  R i )Cs 2π( R o  R L )Cc 2πR e CE
R
R i  R 1 || R 2 || βre R o  R C || ro R e  R E || ( s  re ) R s  R s || R 1 || R 2
β
 LOW-FREQUENCY RESPONSE - BJT AMPLIFIER

BEFORE Rs …
CS CC CE
1 1
f Ls 
1 f LC  f LE 
2 (R i )C s 2π( R o  R L )Cc 2πR e C E
R
R i  R 1 || R 2 || βre R o  R C || ro R e  R E || ( s  re )
β
R s  R 1 || R 2

… AFTER RS
CS CC CE
1 1 1
f Ls  f LC  f LE 
2(R s  R i )Cs 2π( R o  R L )Cc 2πR e CE
R
R i  R 1 || R 2 || βre R o  R C || ro R e  R E || ( s  re ) R s  R s || R 1 || R 2
β
LOW-FREQUENCY RESPONSE - BJT AMPLIFIER
 LOW-FREQUENCY RESPONSE - BJT AMPLIFIER
The Bode plot indicates that
each capacitor may have a
different cutoff frequency.

It is the device that has the

highest lower cutoff
frequency (fL) that dominates
the overall frequency
response of the amplifier.
The Bode plot not only
indicates the cutoff
frequencies of the various
capacitors it also indicates
the amount of attenuation
(loss in gain) at these
frequencies.

The amount of attenuation is

sometimes referred to as roll-
off, the dB loss-per-octave or
dB loss-per-decade.
 LOW-FREQUENCY RESPONSE - BJT AMPLIFIER
-dB/decade refers to the
attenuation for every 10-fold
change in frequency.

For attenuations at the low-

frequency end, it refers to the
loss in gain from the lower
cutoff frequency to a
frequency one-tenth the
cutoff value.

In this example:

fLS = 9kHz gain is 0dB

fLS/10 = .9kHz gain is –20dB
Thus the roll-off is 20dB/decade
The gain decreases by –20dB/decade
 LOW-FREQUENCY RESPONSE - BJT AMPLIFIER
-dB/octave refers to the
attenuation for every 2-fold
change in frequency.

For attenuations at the low-

frequency end, it refers to the
loss in gain from the lower
cutoff frequency to a
frequency one-half the cutoff
value.

In this example:

fLS = 9kHz gain is 0dB

fLS / 2 = 4.5kHz gain is –6dB
Therefore the roll-off is 6dB/octave.

This is a little difficult to see on this graph because

the horizontal scale is a logarithmic scale.
 LOW-FREQUENCY RESPONSE - FET AMPLIFIER
At low frequencies, coupling capacitor (CG,
CC) and bypass capacitor (CS) reactances
affect the circuit impedances.

CG CC CS
1 1 1
f LG f LC  f LS 
2π (R sig  R i )CG 2π(R o  R L )CC 2 πR eqC S
1
Ri  RG R o  R D || rd R eq  R S || r  Ω
gm d
 LOW-FREQUENCY RESPONSE - FET AMPLIFIER

CG CC CS
1 1 1
f LG f LC  f LS 
2π (R sig  R i )CG 2π(R o  R L )CC 2 πR eqC S
1
Ri  RG R o  R D || rd R eq  R S || r  Ω
gm d
 MILLER CAPACITANCE
Any p-n junction can develop
capacitance. In a BJT amplifier, this
capacitance becomes noticeable
across:
• The base-collector junction at
high frequencies in common-
emitter BJT amplifier
configurations
• The gate-drain junction at high
frequencies in common-source
FET amplifier configurations.

C Mi  (1  A v )C f CMo  Cf
These capacitances are represented
Note that the amount If the gain (Av) is
as separate input and output
of Miller capacitance is considerably
capacitances, called the Miller
dependent on inter- greater than 1,
Capacitances.
electrode capacitance then
from input to output
(Cf) and the gain (Av).
 HIGH-FREQUENCY RESPONSE - BJT

Capacitances that affect the

high-frequency response are
• Junction capacitances
Cbe, Cbc, Cce
• Wiring capacitances
Cwi, Cwo
• Coupling capacitors
CS, CC
• Bypass capacitor
CE

1 1
f Hi  f Ho 
2πR Thi C i 2πR Tho Co
HIGH-FREQUENCY RESPONSE - BJT

1
f Hi 
1 f Ho 
2πR T hiCi 2πR T hoCo

Ci  C W i  Cbe  CMi
Co  C Wo  Cce  C Mo
 C W i  Cbe  (1  A v )Cbc
HIGH-FREQUENCY RESPONSE - BJT

The hfe parameter (or ) of a

transistor varies with
frequency
1
fβ 
2πβ mid r e (Cbe  Cbc )
 GAIN-BANDWIDTH PRODUCT
Figure of Merit applied to amplifiers to initiate the design process of an amplifier by providing
relationship between the gain of the amplifier and the expected operating frequency range.

The gain at the low end of an amplifier is often called the DC gain.
 GAIN-BANDWIDTH PRODUCT
Figure of Merit applied to amplifiers to initiate the design process of an amplifier by providing
relationship between the gain of the amplifier and the expected operating frequency range.
HIGH-FREQUENCY RESPONSE - BJT
Note the highest lower cutoff frequency (fL) and the lowest upper cutoff
frequency (fH) are closest to the actual response of the amplifier.
 HIGH-FREQUENCY RESPONSE - FET

Capacitances that affect the

high-frequency response are
• Junction capacitances
Cgs, Cgd, Cds
• Wiring capacitances
Cwi, Cwo
• Coupling capacitors
CG, CC
• Bypass capacitor
CS

1 1
f Hi  f Ho 
2πR Thi C i 2πR Tho Co
HIGH-FREQUENCY RESPONSE - FET

1 1
f Hi  f Ho 
2πR Thi C i 2πR Tho Co
C i  C Wi  C gs  C Mi Co  C Wo  Cds  C Mo
 1 
C Mi  (1  A v )C gd C Mo   1  C gd
 Av 
 MULTISTAGE FREQUENCY EFFECTS
Once the cutoff frequencies have been determined for each stage (taking into account
the shared capacitances), they can be plotted.

Note the highest lower

cutoff frequency (fL) and
the lowest upper cutoff
frequency (fH) are closest
to the actual response of
the amplifier.

Each stage will have its own frequency response, but the output of one
stage will be affected by capacitances in the subsequent stage. This is
especially so when determining the high frequency response. For
example, the output capacitance (Co) will be affected by the input Miller
Capacitance (CMi) of the next stage.
SQUARE-WAVE TESTING
SQUARE-WAVE TESTING
SQUARE-WAVE TESTING
 SQUARE-WAVE TESTING
BW5:
The application of a 1mV, 5kHz square
wave to an amplifier resulted in the
output waveform to the right.
a. Write the Fourier Series expansion
up to the ninth harmonic
b. Determine the bandwidth and the
low cut-off frequency.