Homework#3 Solution

1. Universal set of gates

i. {AND, NOT}
Ans: Yes. OR function can be implemented with the above two because a+b = (a’b’)’

ii. {NOR} i.e. y=(a+b)’

Ans: Yes.
a. Put b=0 => y=a’ => NOT gate
b. ((a+b)’)’=a+b (NOT can be implemented as shown above) => OR gate
c. AND can be implemented using OR and NOT gate since ab=(a’+b’)’

iii. {XNOR} i.e. y=ab+a’b’

Ans: No.
a. Put b=0 => y=a’ => NOT gate
b. AND, OR gates cannot be implemented
iv. f(x,y)=x+y’
Ans: Yes.
a. x=0 => f(0,y)=y’ => NOT gate
b. From y we can implement y’ using NOT gate as shown above. f(x,y’)=x+(y’)’=x+y => OR
gate
c. AND can be implemented using OR and NOT gate since ab=(a’+b’)’
v. f(x,y,z)=xy+y’z’
Ans: Yes.
a. Put y=0 => f(x,0,z)=z’ => NOT gate
b. Put z=1 => f(x,1,z)=xy => 2-input AND gate can be implemented. We can also get y’ and
z’ from y and z respectively using the NOT functionality (proved above). Therefore
f(0,y’,z’)=yz. Also xyz=(xy).(yz) which can be implemented using 2-input AND gate => 3-
input AND gate can be implemented
c. Using NOT gate and 3-input AND gate we can implement 3-input OR gate since
(a’b’c’)’=a+b+c
vi. f(x,y,z)=xy+yz
Ans: No because NOT gate cannot be implemented

2. Other types of gates:

To prove or disprove an equality we will use the following methodology.
Boolean expressions X and Y can be equal iff X+Y’=1 & XY’=0
If any of the above relation does not hold true then X != Y
Alter: X=Y iff X’+Y=1 & X’Y=0
While trying to solve the expression X+Y’ or XY’, we will try to reduce it to as simplified
form as possible where it can be easily interpreted whether the expression is always
true or false or can be either of the two depending on the values a, b and c take.

a. a XOR(b+c)=(a XOR b)+(a XOR c)

Let X= a XOR (b+c) and Y= (a XOR b)+(a XOR c)
X=ab’c’+a’b+a’c, Y=ab’+a’b+ac’+a’c
X+Y’ = ab’c’+a’b+a’c+(ab+a’b’)(ac+a’c’)
= ab’c’+a’b+a’c+abc+a’b’c’
= b’c’(a+a’)+a’b+a’c+abc
= b’c’+a’b+a’c+abc (a+a’=1)
= (b+c)’+a’(b+c)+abc (b’c’=(b+c)’)
= (b+c)’+a’+abc (X+X’Y=X+Y here X=(b+c)’ Y=a’)
= (b+c)’+a’+bc (X+X’Y=X+Y here X=a’ Y=bc)
= b’c’+a’+bc
= a’+(b XNOR c) which is not always true ex. when a=1 & b!=c.
 X+Y’ is not always 1 => The two expressions are unequal

b. a+(b XOR c)=(a+b) XOR (a+c)

Let X=a+(b XOR c), Y=(a+b) XOR (a+c)
X+Y’ = a+(b XOR c)+((a+b) XNOR (a+c))
= a+bc’+b’c+((a+b)(a+c)+(a’b’c’))
= a+bc’+b’c+a+bc+a’b’c’ ((a+b)(a+c)=a+ab+ac+bc=a(1+b+c)+bc=a+bc)
= (a+a)+b(c’+c)+b’c+a’b’c’
= a+b+b’c+a’b’c’
= a+b+c+a’b’c’ (X+X’Y=X+Y here X=b, Y=c)
= (a+b+c)+(a+b+c)’
=1 (X+X’=1)
XY’ = (a+(b XOR c))((a+b) XNOR (a+c))
= (a+bc’+b’c)(a+bc+a’b’c’)
= a+abc+abc’+ab’c
= a(1+bc+bc’+b’c)
=a which is not always 0
 XY’ is not always 0 even if X+Y’=1
 X != Y
3. SR latch:
The following figure shows SR latch implementation using NAND gate

i. Truth table

Q = (S’y)’ = S+y’ ;

y = (R’Q)’ = R+Q’ ;

Id Q(t) Y(t) S R Q(t1) y(t1) Q(t2) y(t2) Q(t3) y(t3)

0 0 0 0 0 1 1 0 0 1 1
1 0 0 0 1 1 1 0 1 0 1
2 0 0 1 0 1 1 1 0 1 0
3 0 0 1 1 1 1 1 1 1 1
4 0 1 0 0 0 1 0 1 0 1
5 0 1 0 1 0 1 0 1 0 1
6 0 1 1 0 1 1 1 0 1 0
7 0 1 1 1 1 1 1 1 1 1
8 1 0 0 0 1 0 1 0 1 0
9 1 0 0 1 1 1 0 1 0 1
10 1 0 1 0 1 0 1 0 1 0
11 1 0 1 1 1 1 1 1 1 1
12 1 1 0 0 0 0 1 1 0 0
13 1 1 0 1 0 1 0 1 0 1
14 1 1 1 0 1 0 1 0 1 0
15 1 1 1 1 1 1 1 1 1 1

ii. State Diagram:

 11

00
Characteristic equation is given by Q(t+1)=S+R’Q(t)

4.

a.

b.
Q

c.

d.