Nuclear Inst.

and Methods in Physics Research, A 904 (2018) 171–178

Contents lists available at ScienceDirect

Nuclear Inst. and Methods in Physics Research, A

journal homepage: www.elsevier.com/locate/nima

Model to predict the number of transistors in an asymmetrical priority

Address-Encoder and Reset-Decoder readout circuit for monolithic active
pixel sensors for high-energy physics
Yu Zhang a,b ,∗, Yue Zhao c , Ruiguang Zhao c
a
School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, 310018, PR China
b Key Laboratory for RF Circuits and Systems (Hangzhou Dianzi University), Ministry of Education, Hangzhou, 310018, PR China
c Institut Pluridisciplinaire Hubert Curien (IPHC), University of Strasbourg, CNRS/IN2P3, Strasbourg, 67037, France

ARTICLE INFO ABSTRACT

Keywords: The digital circuit layout in the active pixel sensor usually occupies the remaining area of an analog circuit
Monolithic active pixel sensor layout. Thus, the number of transistors in the readout circuit is an important factor that enables the size of
Priority Address-Encoder/Reset-Decoder the implementation area to be predicted, when the digital layout of the readout circuit is placed in the specific
readout circuit
area. Therefore, the requirement of reducing implementation area of the monolithic active pixel sensor in high-
Arithmetic series
energy physics experiment make it is important to find the optimal readout circuit structure with minimum
Geometric series
Transistor number prediction
number of transistors. This study utilizes arithmetic and geometric series to propose a model to predict the
number of transistors based on the Karnaugh map of the priority Address-Encoder and Reset-Decoder readout
circuit. The proposed prediction model can list all the probable architectures of the priority Address-Encoder
and Reset-Decoder readout circuit. In addition, the model is able to highlight the structure that contains the
minimum number of transistors, even when the bit-width of the input states of the basic blocks in every layer
are different, instead of calculating the number of transistors based on the assumption that the bit-width of the
input states of the basic block in every layer are same, like the traditional prediction model. A comparison of
the results obtained with the Cadence post-layout simulation and FPGA implementation shows that the number
of transistors calculated by the proposed model is of the same order of magnitude to that obtained from the
Cadence post-layout simulation and FPGA implementation.

1. Introduction double columns as shown in Fig. 4 of literature [11], which is a common

Monolithic active pixel sensors (MAPSs) have been widely used in
high-energy particle physics experiments to detect particle trajectories
[1–7]. Compared with other readout architectures [8–10], the priority
Address-Encoder and Reset-Decoder (AERD) readout circuit was re-
cently employed in the MAPS chip, because it can reduce the readout
time and power consumption [11]. The traditional and symmetrical
AERD network architecture to decode 16 pixels is shown in Fig. 1. It can
be seen from Fig. 1 that the bit-width of the input states in every basic
priority block of different layers are equal to 4, in both the symmetrical
and traditional AERD circuits.
According to the published calculation of the minimal implemen-
tation area in literature [8], the two main contributors to the area
occupied by a digital circuit are the routing channels and the number
of transistors. Since the digital circuit layout is usually placed in the
remaining area of the analog circuit layout, the AERD circuit layout of an
active pixel sensor is located among the layout of pixels in the layout of
structure of MAPS employed in high-energy particle physics. On the
basis of these published results in literature [8] and literature [11], it
can be concluded that the number of transistors has an important impact
on the size of the implementation area, when the digital circuit layout
is placed in the specific area.
According to the literature [11], when the bit-width of the input
states of the basic block in an AERD circuit is 4, as shown in Fig. 1,
the number of transistors in an AERD circuit reaches a minimum,
accordingly, the implementation area of the AERD circuit is minimized.
However, this conclusion drawn from the literature [11] is made
on the assumption that the AERD circuit is symmetrical, namely that
the bit-width of the input states of the basic block in every layer
are the same. In actual high-energy particle physics experiments, this
assumption will reduce the number of the probable AERD network
architecture, which will miss the AERD network architecture with
minimal number of transistors, especially when the number of input

∗ Corresponding author at: School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, 310018, PR China
E-mail address: yuzhang1978@163.com (Y. Zhang).

https://doi.org/10.1016/j.nima.2018.07.041
Received 18 December 2017; Received in revised form 18 May 2018; Accepted 16 July 2018
Available online 21 July 2018
0168-9002/© 2018 Elsevier B.V. All rights reserved.
Y. Zhang et al. Nuclear Inst. and Methods in Physics Research, A 904 (2018) 171–178

Fig. 1. Symmetrical network of the AERD circuit to decode 16 pixels.

pixels is not an integer power of 2. In order to overcome this defect,

this paper proposes a model to predict the number of transistors in an
asymmetrical priority AERD circuit by employing an arithmetic series, a
geometric series, and a Karnaugh map. An asymmetrical priority AERD
circuit means that the bit-width of the input states of the basic block in
every layer are not the same.
The structure of this paper is as follows: the proposed model to pre-
dict the number of transistors is presented in Section 2, the simulation
results and their comparison with the layout results are provided in Fig. 2. Structure of a basic priority encoder block.
Section 3, and Section 4 concludes the paper.

2. Proposed model for prediction of number of transistors
The model for predicting the number of transistors in AERD circuit
comprises two major parts: predicting the number of transistors in intra-
layer and inter-layer circuits, respectively. The intra-layer circuit is the
circuit in every layer, while the inter-layer circuit is the circuit between
adjacent layers.
2.1. Model for predicting the number of transistors in a basic priority encoder
block
Basic priority encoder block is the main component of intra-layer
circuit of AERD circuit. In the same layer, the bit-width of the input
states of every basic priority encoder block is the same. The structure of
a basic priority encoder block is shown in Fig. 2. The definitions of all
signals in basic priority encoder block are shown in Table 1.
The relationship between 𝑖 and 𝑛 is: 2𝑛 = 𝑖. The structures of standard
CMOS gate are shown in Fig. 3.
The output signals of the basic priority encoder block include three
parts: valid, reset, and address. Three part of circuits produced by these
three output signals and corresponding numbers of transistor are shown
as follows:
(1) valid circuit
Because valid=state[0]+state[1]+⋯state[𝑖 − 1], according to the
structure of a standard CMOS gate, as shown in Fig. 3, one bit input
variable needs a corresponding pair of P-MOS and N-MOS transistors in
the NOR logic gate, and there are two transistors in one Inverter logic
gate. As a result, the NOR logic gate with 𝑖 bit input variables needs 2 ∗ 𝑖

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Table 1
The definitions of all signals in basic priority encoder block.
Signal name Direction Bit-width Function
1 state Input 𝑖 It is high when there is a hit in the corresponding pixel.
2 valid Output 1 It is active if at least one pixel is hit.
3 reset Output 𝑖 It resets the pixel state register on falling edge.
4 addr Output 𝑛 It represents the address of the hit pixel that is being reset.
5 select Input 1 It enables the basic priority block to transport the hit pixel.

Fig. 3. Structure of standard CMOS gate.

After the Karnaugh map simplification, the logic relationship be-

tween the input state and address in Fig. 4 can be obtained by (1).

𝑎𝑑𝑑𝑟[0] = 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0] + 𝑠𝑡𝑎𝑡𝑒[3] + 𝑠𝑡𝑎𝑡𝑒[2] + 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0]

𝑎𝑑𝑑𝑟[1] = 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0] (1)

Fig. 4. Truth table of a 4–2 priority encoder. Fig. 6 is the truth table of an 8–3 priority encoder, and X means the
arbitrary value.
By using the similar Karnaugh map simplification in Fig. 5, the logic
relationship between the input state and address can be obtained by (2).
transistors, and it needs one Inverter gate to realize OR logic, then the
number of transistors of the valid circuit is 2 ∗ 𝑖 + 2. 𝑎𝑑𝑑𝑟[0] = 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0] + 𝑠𝑡𝑎𝑡𝑒[3] + 𝑠𝑡𝑎𝑡𝑒[2] + 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0]
(2) Reset decoder circuit +𝑠𝑡𝑎𝑡𝑒[5] + 𝑠𝑡𝑎𝑡𝑒[4] + 𝑠𝑡𝑎𝑡𝑒[3] + 𝑠𝑡𝑎𝑡𝑒[2] + 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0]
Since, +𝑠𝑡𝑎𝑡𝑒[7] + 𝑠𝑡𝑎𝑡𝑒[6] + 𝑠𝑡𝑎𝑡𝑒[5] + 𝑠𝑡𝑎𝑡𝑒[4] + 𝑠𝑡𝑎𝑡𝑒[3] + 𝑠𝑡𝑎𝑡𝑒[2] + 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0]
𝑎𝑑𝑑𝑟[1] = (𝑠𝑡𝑎𝑡𝑒[2] + 𝑠𝑡𝑎𝑡𝑒[3]) 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0]
reset[0] = select&state[0] = select + state[0]
+𝑠𝑡𝑎𝑡𝑒[5] + 𝑠𝑡𝑎𝑡𝑒[4] + 𝑠𝑡𝑎𝑡𝑒[3] + 𝑠𝑡𝑎𝑡𝑒[2] + 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0]
reset[1] = select&state[1]&state[0] = select + state[1] + state[0]
reset[2] = select&state[2]&state[1]&state[0] 𝑎𝑑𝑑𝑟[2] = 𝑠𝑡𝑎𝑡𝑒[3] + 𝑠𝑡𝑎𝑡𝑒[2] + 𝑠𝑡𝑎𝑡𝑒[1] + 𝑠𝑡𝑎𝑡𝑒[0] (2)

= select + state[2] + state[1] + state[0] The number of the red square in Fig. 5 means the number of items in
reset[3] = select&state[3]&state[2]&state[1]&state[0] the logic expression of addr in Fig. 4, and the corresponding positions of
these items are shown as solid red circles in Fig. 4. The similar regulation
= select + state[3] + state[2] + state[1] + state[0]
can be seen in Fig. 6. According to the Karnaugh map simplification, the
……
conclusion that can be drawn from Fig. 4 to Fig. 6 is that there are 𝑖∕2𝑛+1
reset[𝑖 − 1] = select&state[𝑖 − 1]&state[𝑖 − 2]& ⋯ &state[0] items in the logic expression of addr[𝑛]. As a result, in the light of the
= select + state[𝑖 − 1] + state[𝑖 − 2] + ⋯ + state[0] above linear relationship between the input variable and the number of
transistor in CMOS standard gate circuit, the number of transistors of
According to the structure of the standard CMOS gate, the NOR logic
address[𝑛 − 1:0] can be obtained as follows:
gate with 𝑖 bit input variables needs 2 ∗ 𝑖 transistors, and there are
Firstly, the number of transistors of addr[0]:
two transistors in one Inverter logic gate. As a result, the number of
transistors of the reset signal can be calculated by: 1 + 2𝑛 + 𝑖 𝑖 𝑖 𝑖
× ×2+2× +2× +2
2 2𝑛+1 2𝑛+1 2𝑛+1 (3)
1
3 ∗ 2 + 2 ∗ 2 + 3 ∗ 2 + 2 ∗ 2 + 4 ∗ 2 + 2 ∗ 2 + 5 ∗ 2 + ⋯ 2 ∗ 2 + 2 ∗ (𝑖 + 1) 𝑛 = 0 × 𝑖2 + 3 × 𝑖 + 2
( ) 2
(𝑖 + 1 + 3) [ ]
= 6 + 4 ∗ (𝑖 − 1) + 2∗ ∗ (𝑖 − 1) = 𝑖2 + 7𝑖 − 2 Secondly, the number of transistors of addr[𝑛], 𝑛 ∈ 1, log2 (𝑖) − 2 :
2
( )
(3) Address encoder circuit 𝑖 𝑖 𝑖 𝑖2 + 8𝑖
𝑖× ×2+ −1 ×6+2× +2= −4 (4)
2 𝑛+2 2𝑛+1 2𝑛+1 2𝑛+1
In order to deduce the logic relationship between the input variables
∑log (𝑖)−2
and address of a basic priority encoder, a 4–2 and 8–3 priority encoder It can be deduced from (4), the number of transistors of 𝑛=12
are employed to set as the example used for analysis. Fig. 4 is the truth 𝑎𝑑𝑑𝑟[𝑛] can be obtained by (5).
( )
table of the 4–2 priority encoder, and X means the arbitrary value. The (2 ) 1 1 1 ( )
Karnaugh map of addr[0] and addr[1] in Fig. 4 are shown in Fig. 5. 𝑖 + 8𝑖 + +⋯+ − 4 × log2 (𝑖) − 2
4 8 log
2 2 (𝑖)−1

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Fig. 5. The Karnaugh map of addr[0] and addr[1] in Fig. 4.

Fig. 6. Truth table of an 8–3 priority encoder.

𝑖2 + 4𝑖 following equations can easily be obtained:

= − 4 log2 (𝑖) − 8 (5)
2 {
Since the expression of addr[log2 (𝑖) − 1] is the ‘‘NOT’’ operation of num_bk_l (1) = ⌈𝑁𝑝𝑖𝑥𝑙∕2addr_wid_l(1) ⌉
[ ] (8)
valid signal in the basic priority encoder block, the number of transistor num_bk_l (𝑘) = ⌈num_bk_l(𝑘−1)∕2addr_wid_l(𝑘) ⌉ , 𝑘 ∈ 2, max _layer
caused by addr[log2 (𝑖) − 1] is not calculated repeatedly. According to where num_bk_l(k) is the number of basic priority encoder blocks in
the number of transistors of valid, reset, (3) and (5), the total number layer(k).
of transistors of valid, reset, and address in one basic priority encoder
From (6) and (8), the number of transistors in layer(k) can be
block can be obtained by (6).
obtained as (9).
1 2 𝑖2 + 4𝑖 ( )
2𝑖 + 2 + 𝑖2 + 7𝑖 − 2 + 𝑖 + 3𝑖 + 2 + − 4 log2 (𝑖) − 8 ( )2 ( )
2 2 (6) num_bk_l(𝑘) × 2 × 2addr_wid_l(𝑘) + 14 × 2addr_wid_l(𝑘) − 4 × addr_wid_l (𝑘) − 6
2
= 2𝑖 + 14𝑖 − 4 log2 (𝑖) − 6
(9)
2.2. Model for predicting the number of transistors in the intra-layer circuit
As a result, the sum number of transistors in every layer can be
Three important rules need to be taken into account in an asymmet- obtained as in (10).
rical AERD circuit, as shown in (7), the similar rules can be found in max _layer (
∑ ( ( )2
literature [11]. sum_tran_1(𝑘) = num_bk_l (𝑘) × 2 × 2addr_wid_l(𝑘)
⎧max _layer = ⌈log 𝑁𝑝𝑖𝑥𝑙⌉ = ⌈log10 𝑁𝑝𝑖𝑥𝑙∕log 4⌉ 𝑘=1
))
⎪ 4 10 ( )
+14 × 2addr_wid_l(𝑘) − 4 × addr_wid_l (𝑘) − 6 (10)
⎪addr_wid_t = ⌈log2 𝑁𝑝𝑖𝑥𝑙⌉ = ⌈log10 𝑁𝑝𝑖𝑥𝑙∕log10 2⌉
⎨ max _layer
∑ (7)
⎪addr_wid_t = addr_wid_l (𝑘) where sum_tran_1(k) is the sum of the number of transistors in every
⎪ layer. If the calculated value inside ⌈⌉ in (8) is not the integer, the
⎩ 𝑘=1
input state of the basic priority encoder block in that layer will be
where max_layer is the maximum value of the number of layers in the
compensated by 0.
AERD circuit, Npixl is the number of input pixels, addr_wid_t is the total
address width of the AERD circuit, addr_wid_l(k) is the address width of
layer(k), and k is the number of layers. Further, ⌈𝑥⌉ means the ceiling
2.3. Model for predicting the number of transistors in the inter-layer circuit
function. Namely, if the value of variable 𝑥 is not equal to the integer,
the return value of ⌈𝑥⌉ is the minimum integer which is more than the
value of 𝑥. If the value of variable 𝑥 is equal to the integer, the return In addition to the number of transistors in the intra-layer circuit, the
value of ⌈𝑥⌉ is the same as the value of 𝑥. number of transistors also exists in the inter-layer circuits, as shown in
Different layers contain different number of basic priority encoder Fig. 7. The lower address bits of the current layer are calculated by an
blocks of which the bit-width of the input states differs. From (7), the OR operation of the address bits of the previous layer. The number of

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Fig. 7. Inter-layer circuit.

transistors of the lower address circuit in layer(k) can be obtained from

(11).

(𝑘−1 )
( ) ∑
num_bk_l (𝑘) × 2 × 2addr_wid_l(𝑘) + 2 × addr_wid_l (𝑗) (11)
𝑗=1

2.4. Model for predicting the number of transistors in an AERD circuit

According to (10) and (11), the total number of transistors in an

AERD circuit can be obtained from (12).

sum_tran_t =
max _layer ( (
∑ ( )2
num_bk_l (𝑘) × 2 × 2addr_wid_l(𝑘)
𝑘=1 ( ) ))
+14 × 2addr_wid_l(𝑘) − 4 × addr_wid_l (𝑘) − 6
( ( 𝑘−1 ))
∑
max _layer
( ) ∑
+ num_bk_l (𝑘) × 2 × 2addr_wid_l(𝑘) + 2 × addr_wid_l (𝑗)
𝑘=1 𝑗=1

(12)

3. Simulation and experimental results

3.1. Simulation result of number of transistors in an AERD circuit

Fig. 8 is the flow chart of the proposed model to predict an AERD

circuit. If the number of pixel is given, the number of transistor and
structure of AERD circuit can be obtained by using (7)–(12). The model
to predict an AERD circuit is realized with MATLAB software. The
simulation result of the prediction model with 1024 pixels as the input
states of first layer is shown in Fig. 9. The simulation result of the
prediction model with 484 pixels as the input states of first layer is
shown in Fig. 10.
The results in Figs. 9 and 10 show that the proposed prediction model
is capable of listing all the probable different structures of an AERD
circuit with a different address width for every layer. Where 𝑛t means
the number of transistors of the probable AERD circuit, and addr𝑖 means
the bit-width of the address of the basic priority encoder block in the
layer(𝑖). In addition, it can also indicate the structure that requires the
minimum number of transistors, irrespective as to whether the number
of input pixels is an integer power of 2.
3.2. Comparison result with cadence post-layout simulation
The proposed method is evaluated by conducting a comparison with
Cadence post-layout simulation, which is implemented by Cadence RTL
compiler in the Tower Jazz 180 nm CMOS technology. The total number
of transistors of a Cadence post-layout simulation of optimal AERD
circuit with 1024 input pixels is shown in Table 2. Furthermore, the
results in Fig. 9(b) and Table 2 indicate that the number of transistors
calculated by the proposed prediction model of the optimal AERD circuit
with 1024 input pixels is 30880, and this number is of the same order of
Fig. 8. The flow chart of the proposed model.
magnitude as the actual number of transistors in the Cadence post-layout
simulation of optimal AERD circuit. In Table 2, the number of transistors
of the delay buff approximates 1512, the actual number of transistors of
the post-layout optimal AERD circuit is equal to the difference between
the total number of transistors and the number of transistors in the delay
buff.
In addition, all the possible structures of an AERD network of 64
input pixels are included on the horizontal axis in Fig. 11, where 2_2_2
means there are three layers in the AERD network, and the bit-width of
the address of the basic priority encoder block in every layer is 22 . The
calculation result of the proposed prediction model is compared with
Cadence post-layout simulation results. The results in Fig. 11 indicate
that the variation trend of prediction results of the proposed model
is similar to that of the Cadence post-layout simulation results. The
optimal solutions with the minimum number transistors under proposed
estimation and Cadence post-layout simulation are same, and are 2_2_2
structure. It also can be seen from Fig. 11 that the number of transistors
estimated by the proposed prediction model is of the same order of
magnitude as the number of transistors in the Cadence post-layout
results.

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Fig. 9. Simulation result when the number of input pixels is 1024.

Fig. 10. Simulation result when the number of input pixels is 484.

3.3. Comparison result with FPGA implementation
The proposed method is also assessed by conducting a comparison
with the FPGA implementation, which are simulated in Vivado 2016 and
Artix-7 FPGA of Xilinx, as shown in Fig. 11. The results in Fig. 11 indi-
cate that the variation trend of prediction results of the proposed model
is similar to that of the post-layout simulation results implemented
by Xilinx FPGA. The optimal solutions with the minimum number

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Fig. 11. Comparisons with Cadence post-layout simulation and FPGA implementation.

Table 2
Number of transistors of Cadence post-layout simulation of an AERD circuit with 1024 input pixels.
Circuit components Count Number of transistors in component
Nr23d4 1 1*14=14
Bufbd7 5 5*16=80
Invod1 84 84*2=168
Bufbd3 10 10*8=80
Buffd7 24 24*13=312
Nr02d1 80 80*4=320
An03d1 768 768*8=6144
Buffd3 32 32*6=192
An12d4 1 1*12=12
Or02d1 339 339*6=2034
Bufbda 41 41*20=820
Bufbd4 1 1*9=9
Nd23d4 1 1*14=14
Aor31d4 2 2*14=28
Buffda 1 1*19=19
An02d4 7 7*10=70
An03d2 168 168*10=1680
An12d1 340 340*8=2720
Nd12d2 80 80*10=800
Nr02d7 1 1*16=16
An02d1 424 424*6=2544
Or04d7 224 224*20=4480
Inv0d0 256 256*2=512
Aor31d2 82 82*12=984
Nr02d4 4 4*12=48
An02d2 586 586*8=4688
An03d4 256 256*12=3072
Nr02d0 256 256*4=1024
Or02da 1 1*19=19
Or02d4 2 2*10=20
Ora211d4 256 256*14=3584
Nd12d4 260 260*14=3640
Total number of transistor 40174 − 1512(delay buff)=38635

transistors under proposed estimation and FPGA implementation are
same, and are 2_2_2 structure. According to the literature [12], one LUT
in FPGA equals approximately 21 transistors. As a result, it can be seen
from Fig. 11 that the number of transistors estimated by the proposed
prediction model is of the same order of magnitude as the approximate
number of transistors in the post-layout results of FPGA implementation.
4. Conclusion
This paper proposes a model for predicting the number of transistors
of an asymmetrical priority address-encoder and reset-decoder readout
circuit. This prediction model can output all the different probable
structures of an AERD circuit, and highlight the structure that costs the
minimum number of transistors. The experimental results showed that
the number of transistors obtained by the proposed prediction model
approaches the Cadence post-layout simulation result and FPGA im-
plementation. The proposed prediction model can supply the candidate
reference for an ASIC designer and high-energy physicist to select the
appropriate structure for a digital AERD circuit in MAPS to obtain the
minimum implementation area, according to the number of input pixels
of different high-energy particle physics experiments.

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Acknowledgments
This paper was supported by the China Scholarship Council (CSC)
(Grant No. 201508330049), the National Natural Science Foundation of
China under Grant No. 61372156, and the Natural Science Foundation
of Zhejiang Province under Grant No. LY17F010022. This research
topic was supplied by Chritine Hu-Guo in the Microelectronics group,
when the corresponding author visited the Physics with Integrated
CMOS Sensors and Electron machines (PICSEL) team of the Institute
Pluridisciplinaire Hubert CURIEN in Strasbourg from February 2016
to March 2017. The netlist of the Cadence post-layout simulation of
optimal AERD circuit was supplied by Abdelkader Himmi and Guy
Doziere.
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