Toshiba Satellite c660d - Compal La-6843p Pwwae - Rev 1.0

A B C D E
1 1
Compal confidential
2
LC-Marseille 10AD 2
PWWAE LA-6843P Schematics Document
Mobile AMD S1G4/ RS880M / SB820M

3 3
2010-08-16 Rev. 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6843
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401982 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 01, 2010 Sheet 1 of 40
A B C D E
A B C D E
Compal Confidential Thermal Sensor Fan Control AMD S1G4 CPU

Memory BUS(DDRIII)
200pin DDRIII-SO-DIMM X2
page 5 Dual Channel
ADM1032ARMZ page 7 BANK 0, 1, 2, 3 page 9,10
Model Name : PWWAA uFCPGA-638 Package 1.5V DDRIII 1066/1333MHZ
File Name : LA-6843P page 5,6,7,8
1 Hyper Transport Link 2.6GHz 1
16X16
RTL8105E 10/100M
PCIe port 3 RJ45
page 24
page 24
AMD
CRT
page 16
RS880M
LCD Conn. PCIe 4x

page 17 1.5V 2.5GHz(250MB/s)
WLAN
PCIe port 2
page 23
page 11,12,13,14,15
LAN
PCIe port 3
2 2
A-Link Express II page 24
4X PCI-E
IO/B-- USB Right
USB port 0,1
page 23
USB
5V 480MHz
SATA port 0 SATA HDD
Card Reader Int. Camera 5V 1.5GHz(150MB/s) page 23
USB port 5
page 25
USB port 9
page 17
AMD
SATA port 1 SATA ODD
5V 1.5GHz(150MB/s) page 23
SB820M
WLAN USB
USB port 8 5V 480MHz
page 27
page 18,19,20,21,22
3 3
3.3V 33 MHz
HD Audio 3.3V/1.5V 24MHz
LPC BUS
RTC CKT. HDA Codec
ALC259
page 26
Debug Port ENE KB926 E0
Power On/Off CKT. page 29 page 28
page 30
Power/B
Int.
page 30 MIC CONN MIC CONN HP CONN SPK CONN
page 17 page 27 page 27 page 27
DC/DC Interface CKT. Touch Pad Int.KBD EC ROM
page 30 page 29 page 29
page 31
Power Circuit DC/DC

4 4
page 31,32,33,34,35
36,37,38,39

SCHEMATICS,MB A6843
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401982 B
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
RT8205EGQW DESIGN CURRENT 1A +3VALW
DESIGN CURRENT 3.5A +5VALW
D D
SUSP
N-CHANNEL DESIGN CURRENT 2A +5VS
SI4800
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
DESIGN CURRENT 1.5A +3VS
N-CHANNEL
SI4800
ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO-3413
C C
DESIGN CURRENT 300mA +2.5VS
APL5508
PWWAE LC-Marseille AMD
SUSP#
DESIGN CURRENT 2.5A +1.8VS
MP2121DQ
POK
DESIGN CURRENT 0.3A +1.1VALW
RT8209BGQW
VLDT_EN#
N-CHANNEL DESIGN CURRENT 3.5A +1.1VS
IRF8113
VLDT_EN#
N-CHANNEL DESIGN CURRENT 6A +NB_CORE
VR_ON
IRF8113
B DESIGN CURRENT 18A B
+CPU_CORE0
DESIGN CURRENT 18A +CPU_CORE1
ISL6265A
DESIGN CURRENT 4A +VDDNB
SYSON
DESIGN CURRENT 5A +1.5V
RT8209BGQW SUSP
N-CHANNEL DESIGN CURRENT 1A +1.5VS
IRF8113
SUSP
DESIGN CURRENT 1A +0.75VS
APL5331KAC
VR_ON#
DESIGN CURRENT 1.5A +1.05VS
A A
APL5331KAC

SCHEMATICS,MB A6843
5 4 3 2 1
A B C D E
Voltage Rails
Platform CPU NB VGA SB Comment
O : ON
S1G4 RS880M NA SB820M
X : OFF Danube
+5VS
1
+3VS 1
power @ : just reserve , no build
plane +2.5VS
+1.8VS SB820MR1@ : just reserve for SB820MR1 only
+1.5VS R3@ : just reserve for R3 only
+1.1VS CONN@ : just reserve for Connector only
+B +5VALW CAM@ : just reserve for WebCam only
+1.05VS
+3VL +3VALW +1.5V BT@ : just reserve for Blue Tooth only
+0.75VS
+5VL +1.1VALW 880MR1@: just reserve for 880MR1 only
State +VGA_CORE
+RTCVCC 8105E_VC@: just reserve for 10/100 LAN VC version only
+VDDNB
+CPU_CORE 8105E_VB@: just reserve for 10/100 LAN VBversion only
S0
O O O O
S1
O O O O BTO (Build-To-Order) Option Table
2 2
S3 Function Camera
O O O X
Description (C)
S5 S4/AC
O O X X Explain
S5 S4/ Battery only
O X X X BTO CAM@
S5 S4/AC & Battery

don't exist X X X X
SMBUS Control Table

3
I2C / SMBUS ADDRESSING CPU 3
SOURCE BATT SODIMM CLK LCD
THERMAL GEN WLAN DDC
I / II
DEVICE HEX ADDRESS SENSOR ROM
EC_SMB_CK1
DDR SO-DIMM 0 A0 10100000 KB926
EC_SMB_DA1 V
DDR SO-DIMM 1 A2 10100010
EC_SMB_CK2
KB926
EC_SMB_DA2 V
I2C_CLK
RS880M
I2C_DATA V
DDC_CLK0
RS880M
DDC_DATA0
EC SM Bus1 address EC SM Bus2 address
SCL0
SB820
Device HEX Address Device HEX Address SDA0 V V
Smart Battery 16H 0001 011X b EMC1032-1 CPU 98H 1001 100X b SCL1
SB820
EC KB926E0 EC KB926E0 SDA1 V
4 4

SCHEMATICS,MB A6843
A B C D E
A B C D E
+1.1VS
250 mil VLDT CAP. Near CPU Socket
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
10U_0805_10V6K 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J

2 2 2 2 2 2
1 1
H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>
+1.1VS
+1.1VS
JCPUA
C7
D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2 10U_0805_10V6K < VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT=500mA D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0

H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
2 H_CADIP4 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
< From NB > F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 < To NB >
H_CADIN9 F4 AC5 H_CADON9
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15
<11> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <11>

<11> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <11>
<11> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <11>
<11> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <11>
<11> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <11>

<11> H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 <11>
3 3
<11> H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 <11>
<11> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <11>
FOX_PZ6382A-284S-41F_Champlian
CONN@
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
2
+FAN1
C1119 JFAN +3VS
1
10U_0805_10V4Z +FAN1 1
C1120 1 1
2 2
1
10U_0805_10V4Z 2 3
2 U31 @ 3
1 8 C1121 4 R795
EN GND 1000P_0402_25V8J GND 10K_0402_5%
2 VIN GND 7 5 GND
1
3 6
2
VOUT GND ACES_85204-0300N

<28> EN_DFAN1 4 VSET GND 5
4 CONN@ 4
FAN_SPEED1 <28>
APL5607KI-TRG_SO8 2
@
C1122
0.01U_0402_25V7K
1

SCHEMATICS,MB A6843
A B C D E
A B C D E
+1.5V < DDR2 VREF is 0.5 ratio > < Processor DDR3 Memory Interface >
< Close to CPU >
2
R1
JCPUC
<10> DDR_B_D[63..0]
1K_0402_1% MEM:DATA
DDR_A_D[63..0] <9>
< From/To SO_DIMMB > DDR_B_D0 C11 G12 DDR_A_D0
1
+MCH_REF DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1

A11 MB_DATA1 MA_DATA1 F12 < From/To SO_DIMMA >
DDR_B_D2 A14 H14 DDR_A_D2
MB_DATA2 MA_DATA2
2
1 1 DDR_B_D3 B14 G14 DDR_A_D3

R2 C9 C8 DDR_B_D4 MB_DATA3 MA_DATA3 DDR_A_D4
G11 MB_DATA4 MA_DATA4 H11
DDR_B_D5 E11 H12 DDR_A_D5
1 1K_0402_1% 0.1U_0402_16V7K 1000P_0402_25V8J DDR_B_D6 MB_DATA5 MA_DATA5 DDR_A_D6 1
D12 MB_DATA6 MA_DATA6 C13
2 2 DDR_B_D7 DDR_A_D7
A13 E13
1
DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8

A15 MB_DATA8 MA_DATA8 H15
DDR_B_D9 A16 E15 DDR_A_D9
A19 MB_DATA10 MA_DATA10 E17
DDR_B_D11 A20 H17 DDR_A_D11
C14 MB_DATA12 MA_DATA12 E14
DDR_B_D13 D14 F14 DDR_A_D13
C18 MB_DATA14 MA_DATA14 C17
DDR_B_D15 D18 G17 DDR_A_D15
D20 MB_DATA16 MA_DATA16 G18
DDR_B_D17 A21 C19 DDR_A_D17
D24 MB_DATA18 MA_DATA18 D22
DDR_B_D19 C25 E20 DDR_A_D19
B20 MB_DATA20 MA_DATA20 E18
DDR_B_D21 C20 F18 DDR_A_D21
B24 MB_DATA22 MA_DATA22 B22
DDR_B_D23 C24 C23 DDR_A_D23
E23 MB_DATA24 MA_DATA24 F20
DDR_B_D25 E24 F22 DDR_A_D25
DDR_B_D27 G26 J19 DDR_A_D27
C26 MB_DATA28 MA_DATA28 E21
DDR_B_D29 D26 E22 DDR_A_D29
DDR_B_D31 G24 H22 DDR_A_D31
+1.05VS +1.05VS DDR_B_D32 MB_DATA31 MA_DATA31 DDR_A_D32
AA24 MB_DATA32 MA_DATA32 Y24
JCPUB DDR_B_D33 AA23 AB24 DDR_A_D33
AD24 MB_DATA34 MA_DATA34 AB22
D10 W10 DDR_B_D35 AE24 AA21 DDR_A_D35
VDDR1 MEM:CMD/CTRL/CLK
VDDR5 DDR_B_D36 MB_DATA35 MA_DATA35 DDR_A_D36
C10 VDDR2 VDDR6 AC10 AA26 MB_DATA36 MA_DATA36 W22
Place them close to CPU within 1" B10 AB10 < VTT regulator voltage > DDR_B_D37 AA25 W21 DDR_A_D37
2 VDDR3 VDDR7 DDR_B_D38 MB_DATA37 MA_DATA37 DDR_A_D38 2
AD10 VDDR4 VDDR8 AA10 AD26 MB_DATA38 MA_DATA38 Y22
A10 DDR_B_D39 AE25 AA22 DDR_A_D39
R4 1 VDDR9 MB_DATA39 MA_DATA39
2 39.2_0402_1% MEM_P AF10 MEMZP
DDR_B_D40 AC22 MB_DATA40 MA_DATA40 Y20 DDR_A_D40
+1.5V R5 1 2 39.2_0402_1% MEM_N AE10 Y10 VTT_SENSE DDR_B_D41 AD22 AA20 DDR_A_D41
MEMZN VDDR_SENSE PAD T1 MB_DATA41 MA_DATA41
DDR_B_D42 AE20 AA18 DDR_A_D42
MEM_MA_RST# +MCH_REF DDR_B_D43 MB_DATA42 MA_DATA42 DDR_A_D43
<9> MEM_MA_RST# H16 MA_RESET_L MEMVREF W17 AF20 MB_DATA43 MA_DATA43 AB18
DDR_B_D44 AF24 AB21 DDR_A_D44
DDR_A_ODT0 MEM_MB_RST# DDR_B_D45 MB_DATA44 MA_DATA44 DDR_A_D45
<9> DDR_A_ODT0 T19 MA0_ODT0 MB_RESET_L B18 MEM_MB_RST# <10> AF23 MB_DATA45 MA_DATA45 AD21
< To SO_DIMMA > <9> DDR_A_ODT1 DDR_A_ODT1 V22 DDR_B_D46 AC20 AD19 DDR_A_D46
MA0_ODT1 DDR_B_ODT0 DDR_B_D47 MB_DATA46 MA_DATA46 DDR_A_D47
U21 MA1_ODT0 MB0_ODT0 W26 DDR_B_ODT0 <10> AD20 MB_DATA47 MA_DATA47 Y18
V19 W23 DDR_B_ODT1 < To SO_DIMMB > DDR_B_D48 AD18 AD17 DDR_A_D48
MA1_ODT1 MB0_ODT1 DDR_B_ODT1 <10> MB_DATA48 MA_DATA48
Y26 DDR_B_D49 AE18 W16 DDR_A_D49
DDR_CS0_DIMMA# T20 MB1_ODT0 DDR_B_D50 MB_DATA49 MA_DATA49 DDR_A_D50
<9> DDR_CS0_DIMMA# MA0_CS_L0 AC14 MB_DATA50 MA_DATA50 W14
< To SO_DIMMA > DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
<9> DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# <10> MB_DATA51 MA_DATA51
DDR_CS1_DIMMB# DDR_B_D52 DDR_A_D52
U20 MA1_CS_L0 MB0_CS_L1 W25 DDR_CS1_DIMMB# <10>< To SO_DIMMB > AF19 MB_DATA52 MA_DATA52 Y17
V20 U22 DDR_B_D53 AC18 AB17 DDR_A_D53
MA1_CS_L1 MB1_CS_L0 DDR_B_D54 MB_DATA53 MA_DATA53 DDR_A_D54
AF16 MB_DATA54 MA_DATA54 AB15
DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB DDR_B_D55 AF15 AD15 DDR_A_D55
<9> DDR_CKE0_DIMMA MA_CKE0 MB_CKE0 DDR_CKE0_DIMMB <10> MB_DATA55 MA_DATA55
< To SO_DIMMA > <9> DDR_CKE1_DIMMA DDR_CKE1_DIMMA J20 DDR_CKE1_DIMMB DDR_B_D56 DDR_A_D56
MA_CKE1 MB_CKE1 H26 DDR_CKE1_DIMMB <10>< To SO_DIMMB > AF13 MB_DATA56 MA_DATA56 AB13
DDR_B_D57 AC12 AD13 DDR_A_D57
DDR_A_CLK0 DDR_B_CLK0 DDR_B_D58 MB_DATA57 MA_DATA57 DDR_A_D58
<9> DDR_A_CLK0 N19 MA_CLK_H5 MB_CLK_H5 P22 DDR_B_CLK0 <10> AB11 MB_DATA58 MA_DATA58 Y12
DDR_A_CLK#0 N20 R22 DDR_B_CLK#0 DDR_B_D59 Y11 W11 DDR_A_D59
<9> DDR_A_CLK#0 MA_CLK_L5 MB_CLK_L5 DDR_B_CLK#0 <10> MB_DATA59 MA_DATA59
E16 A17 DDR_B_D60 AE14 AB14 DDR_A_D60
MA_CLK_H1 MB_CLK_H1 DDR_B_D61 MB_DATA60 MA_DATA60 DDR_A_D61
F16 MA_CLK_L1 MB_CLK_L1 A18 < To SO_DIMMB > AF14 MB_DATA61 MA_DATA61 AA14
< To SO_DIMMA > Y16 AF18 DDR_B_D62 AF11 AB12 DDR_A_D62
MA_CLK_H7 MB_CLK_H7 DDR_B_D63 MB_DATA62 MA_DATA62 DDR_A_D63
AA16 MA_CLK_L7 MB_CLK_L7 AF17 AD11 MB_DATA63 MA_DATA63 AA12
DDR_A_CLK1 P19 R26 DDR_B_CLK1
<9> DDR_A_CLK1 MA_CLK_H4 MB_CLK_H4 DDR_B_CLK1 <10> <10> DDR_B_DM[7..0] DDR_A_DM[7..0] <9>
DDR_A_CLK#1 P20 R25 DDR_B_CLK#1 DDR_B_DM0 A12 E12 DDR_A_DM0
<9> DDR_A_CLK#1 MA_CLK_L4 MB_CLK_L4 DDR_B_CLK#1 <10> MB_DM0 MA_DM0
< To SO_DIMMA > <9> DDR_A_MA[15..0] < To SO_DIMMB > < To SO_DIMMB > DDR_B_DM1 B16 C15 DDR_A_DM1 < To SO_DIMMA >
DDR_B_MA[15..0] <10> MB_DM1 MA_DM1
DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM2 A22 E19 DDR_A_DM2
DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM3 MB_DM2 MA_DM2 DDR_A_DM3
M20 MA_ADD1 MB_ADD1 N24 E25 MB_DM3 MA_DM3 F24
DDR_A_MA2 N22 P26 DDR_B_MA2 DDR_B_DM4 AB26 AC24 DDR_A_DM4
3 DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM5 MB_DM4 MA_DM4 DDR_A_DM5 3
M19 MA_ADD3 MB_ADD3 N23 AE22 MB_DM5 MA_DM5 Y19
DDR_A_MA4 M22 N26 DDR_B_MA4 DDR_B_DM6 AC16 AB16 DDR_A_DM6
DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM7 MB_DM6 MA_DM6 DDR_A_DM7
L20 MA_ADD5 MB_ADD5 L23 AD12 MB_DM7 MA_DM7 Y13
DDR_A_MA6 M24 N25 DDR_B_MA6
DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 DDR_B_DQS0 DDR_A_DQS0
L21 MA_ADD7 MB_ADD7 L24 <10> DDR_B_DQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDR_A_DQS0 <9>
DDR_A_MA8 L19 M26 DDR_B_MA8 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
MA_ADD8 MB_ADD8 <10> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <9>
DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS1 D16 G16 DDR_A_DQS1
MA_ADD9 MB_ADD9 <10> DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 <9>
DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
DDR_A_MA11 L22 L26 DDR_B_MA11 DDR_B_DQS2 A24 C22 DDR_A_DQS2
DDR_A_MA12 K20 L25 DDR_B_MA12 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
DDR_A_MA13 V24 W24 DDR_B_MA13 DDR_B_DQS3 F26 G22 DDR_A_DQS3
DDR_A_MA14 K24 J23 DDR_B_MA14 DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
DDR_A_MA15 K19 J24 DDR_B_MA15 DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
<10> DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 <9>
DDR_A_BS#0 R20 R24 DDR_B_BS#0 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
<9> DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 <10> <10> DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 <9>
< To SO_DIMMA > <9> DDR_A_BS#1 DDR_A_BS#1 R23 U26 DDR_B_BS#1 < To SO_DIMMB > DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
MA_BANK1 MB_BANK1 DDR_B_BS#1 <10> <10> DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 <9>
DDR_A_BS#2 J21 J26 DDR_B_BS#2 DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
<9> DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 <10> <10> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <9>
DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
<10> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <9>
DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
<9> DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# <10> <10> DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 <9>
< To SO_DIMMA > DDR_A_CAS# T22 U24 DDR_B_CAS# < To SO_DIMMB > DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
<9> DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# <10> <10> DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 <9>
DDR_A_WE# T24 U23 DDR_B_WE#
<9> DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# <10>
< From/To SO_DIMMB > < From/To SO_DIMMA >
FOX_PZ6382A-284S-41F_Champlian CONN@
CONN@
4 4

SCHEMATICS,MB A6843
A B C D E
A B C D E
JCPUD
< Filtered PLL Supply Voltage > +1.5V
+2.5VDDA F8 M11
VDDA1 VSS
F9 VDDA2 RSVD11 W18
+2.5VS +2.5VDDA CPU_SVC 1K_0402_5% 1 2 R19
VDDA=300mA CPU_CLKIN_SC_P A9 A6 CPU_SVC
L1 1 CLKIN_H SVC CPU_SVC <38>
2 FBM_L11_201209_300L_0805 +2.5VDDA CPU_CLKIN_SC_N A8 CLKIN_L SVD A4 CPU_SVD
CPU_SVD <38>
CPU_SVD 1K_0402_5% 1 2 R20
1 1 1 1
C12 C13 C14 LDT_RST# B7 < Serial VID Interface clock & data >
+ C11 H_PWRGD RESET_L
A7 PWROK
@ 4.7U_0805_10V4Z 3300P_0402_50V7K 0.22U_0603_16V4Z LDT_STOP# F10 AF6 CPU_THERMTRIP#_R +1.5V R11 1 2 300_0402_5%
150U_B2_6.3VM_R45M 2 2 2 LDTSTOP_L THERMTRIP_L
T2 PAD C6 LDTREQ_L PROCHOT_L AC7 CPU_PROCHOT#
2
MEMHOT_L AA8 PAD T3
+1.5V R12 1 2 1K_0402_5% CPU_SIC AF4 CPU_PROCHOT# @ R13 1 2 0_0402_5%
SIC H_PROCHOT# <18>
+1.5V R14 1 2 1K_0402_5% CPU_SID AF5
1 SID THERMDC_CPU 1
AE6 ALERT_L THERMDC W7
W8 THERMDA_CPU
R15 CPU_HTREF0 THERMDA
< 200-MHz PLL Reference Clock > 1 2 44.2_0402_1% R6 HT_REF0
C16 +1.1VS R16 1 2 44.2_0402_1% CPU_HTREF1 P6 HT_REF1
<18> CLK_CPU_BCLK 1 2 3900P_0402_50V7K CPU_CLKIN_SC_P route as differential
CPU_VDD0_RUN_FB_H F6 W9 as short as possible
<38> CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H PAD T15 testpoint under package
<38> CPU_VDD0_RUN_FB_L CPU_VDD0_RUN_FB_L E6 Y9
VDD0_FB_L VDDIO_FB_L PAD T16
1
R10 Y6 H6 CPU_VDDNB_RUN_FB_H
VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H <38>
AB6 G6 CPU_VDDNB_RUN_FB_L
VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L <38>
169_0402_1%
CPU_DBRDY G10
2
C15 CPU_TMS DBRDY CPU_DBREQ#
AA9 TMS DBREQ_L E10
<18> CLK_CPU_BCLK# 1 2 3900P_0402_50V7K CPU_CLKIN_SC_N CPU_TCK AC9 TCK
CPU_TRST# AD9 AE9 CPU_TDO
CPU_TDI TRST_L TDO
Address:100_1100 Place close to CPU wihtin 1.5" AF9 TDI
CPU_TEST23 AD7 J7 R6
TEST23 TEST28_H 10K_0402_5%
TEST28_L H8 +1.5V 1 2
CPU_TEST18 H10
CPU_TEST19 TEST18 CPU_TEST17
G9 TEST19 TEST17 D7 PAD T4
E7 CPU_TEST16 R7
TEST16 PAD T5
CPU_TEST25H E9 F7 CPU_TEST15 1 2 1K_0402_5%
TEST25_H TEST15 PAD T6
2
B
CPU_TEST25L E8 C7 CPU_TEST14 Q1
TEST25_L TEST14 PAD T7
+1.5V
E
CPU_TEST21 AB8 C3 CPU_THERMTRIP#_R 3 1
TEST21 TEST7 H_THERMTRIP# <19>
C
CPU_TEST20 AF7 K8
CPU_TEST24 TEST20 TEST10 MMBT3904_NL_SOT23-3
AE7 TEST24
R22 2 1 510_0402_5% CPU_TEST25H CPU_TEST22 AE8 C4
CPU_TEST27 CPU_TEST12 TEST22 TEST8
2 1 AC8 TEST12
R28 1K_0402_5% CPU_TEST27 AF8 TEST27 CPU_TEST29_H_FBCLKOUT_P
TEST29_H C9
2 R24 CPU_TEST29_L_FBCLKOUT_N 2
1 2 0_0402_5% C2 TEST9 TEST29_L C8 2 1
R27 1 2 510_0402_5% CPU_TEST25L AA6 R25 80.6_0402_1%
TEST6
R29 2 1 1K_0402_5% CPU_TEST12 A3 H18
RSVD1 RSVD10
A5 RSVD2 RSVD9 H19
R30 2 1 1K_0402_5% CPU_TEST18 B3 AA7
RSVD3 RSVD8
B5 RSVD4 RSVD7 D5
R31 2 1 1K_0402_5% CPU_TEST19 C1 C5
RSVD5 RSVD6
R32 2 1 1K_0402_5% CPU_TEST20
R33 2 1 1K_0402_5% CPU_TEST21 CONN@
R34 2 1 1K_0402_5% CPU_TEST22
R265 2 1 1K_0402_5% CPU_TEST23
R35 2 1 1K_0402_5% CPU_TEST24
+1.5VS
2
R17
300_0402_5%
3 3
1
LDT_RST#
<18> LDT_RST#
1
C17
@ < Thermal Sensor >
0.01U_0402_25V7K
2
< HDT Connector > U1
+3VS
JP2
1 8 EC_SMB_CK2 EC_SMB_CK2 <28>
1 2 VDD SMCLK
3 4 1
+1.5VS C20 THERMDA_CPU 2 7 EC_SMB_DA2
5 6 DP SMDATA EC_SMB_DA2 <28>
+1.5V R40 1 2 300_0402_5% CPU_DBREQ# C21
CPU_DBRDY 7 8 0.1U_0402_16V7K THERMDC_CPU
9 10 1 2 3 DN ALERT# 6 1 2 +3VS
2
R39 220_0402_5% CPU_TCK 2 2200P_0402_50V7K R41 10K_0402_5%

1 2 11 12
R21 R38 1 2 220_0402_5% CPU_TMS @ CPU_THERM# 4 5 @
R37 220_0402_5% CPU_TDI 13 14 THERM# GND
1 2 15 16
300_0402_5% +1.5V R36 1 2 220_0402_5% CPU_TRST# R44
CPU_TDO 17 18
+3VS 1 2
1
H_PWRGD 19 20 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8

<18,38> H_PWRGD 21 22 LDT_RST#
1 +1.5V 23 24
C19
@ 26
Address:0100_1100 EMC1402-1
0.1U_0402_16V7K Address:0100_1101 EMC1402-2
2 SAMTEC_ASP-68200-07
CONN@
3/30 Change U1 ADM1032 to EMC1402 for cost down
+1.5VS
4 4
2
R18
300_0402_5%
1
LDT_STOP#
<12,18> LDT_STOP#
1
C18
@
2
0.01U_0402_25V7K
SCHEMATICS,MB A6843
A B C D E
A B C D E
+CPU_CORE JCPUE +CPU_CORE

VDD decoupling : +CPU_CORE G4 P8
+CPU_CORE VDD0_1 VDD1_1
H2 VDD0_2 VDD1_2 P10
+CPU_CORE +CPU_CORE J9 R4
VDD0_3 VDD1_3
J11 VDD0_4 VDD1_4 R7
330U_6.3V_M_R15
J13 VDD0_5 VDD1_5 R9
330U_X_2VM_R6M
330U_X_2VM_R6M
330U_6.3V_M_R15
1 1 1 1 1 1 1 1 1 1 1 J15 VDD0_6 VDD1_6 R11
C35 C34 C28 C29 C36 C37 C38 K6 T2
+ C26 + C90 + C25 + C96 VDD0_7 VDD1_7
K10 VDD0_8 VDD1_8 T6
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J K12 T8
@ @ 2 2 2 2 2 2 2 VDD0_9 VDD1_9
K14 VDD0_10 VDD1_10 T10
2 2 2 2
L4 VDD0_11 VDD1_11 T12
Under CPU Socket Under CPU Socket L7 VDD0_12 VDD1_12 T14
L9 VDD0_13 VDD1_13 U7
1 1
Near CPU Socket L11 VDD0_14 VDD1_14 U9
L13 VDD0_15 VDD1_15 U11
+CPU_CORE +CPU_CORE +CPU_CORE L15 U13
VDD0_16 VDD1_16
M2 VDD0_17 VDD1_17 U15
330U_6.3V_M_R15
330U_6.3V_M_R15 M6 V6
VDD0_18 VDD1_18
330U_X_2VM_R6M
330U_X_2VM_R6M
1 1 1 1 1 1 1 1 1 1 1 M8 VDD0_19 VDD1_19 V8
C30 C31 C32 C33 C39 C40 C41 M10 V10
+ C23 + C89 + C24 + C95 VDD0_20 VDD1_20
N7 VDD0_21 VDD1_21 V12
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J N9 V14
@ @ @ 2 2 2 2 2 2 2 +VDDNB VDD0_22 VDD1_22
N11 VDD0_23 VDD1_23 W4
2 2 2 2
VDD1_24 Y2
Under CPU Socket Under CPU Socket K16 VDDNB_1 VDD1_25 AC4
Near CPU Socket M16 AD2 +1.5V
VDDNB_2 VDD1_26
P16 VDDNB_3
T16 VDDNB_4 VDDIO27 Y25
V16 VDDNB_5 VDDIO26 V25
+1.5V
VDDIO decoupling : DDR SDRAM I/O ring power H25
VDDIO25 V23
V21
+1.5V VDDIO1 VDDIO24
J17 VDDIO2 VDDIO23 V18
K18 VDDIO3 VDDIO22 U17
K21 VDDIO4 VDDIO21 T25
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23
C44 C45 C46 C47 C48 C50 K25 T21
VDDIO6 VDDIO19
L17 VDDIO7 VDDIO18 T18
22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J M18 R17
2 2 2 2 2 2 VDDIO8 VDDIO17
M21 VDDIO9 VDDIO16 P25
Under CPU Socket M23 VDDIO10 VDDIO15 P23
M25 VDDIO11 VDDIO14 P21
N17 VDDIO12 VDDIO13 P18
+1.5V
2 CONN@ 2
1 1 1 1
C54 C51 C52 C53
JCPUF
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z AA4 J6
2 2 2 2 VSS1 VSS66
AA11 VSS2 VSS67 J8
Between CPU Socket and DIMM AA13 VSS3 VSS68 J10
AA15 VSS4 VSS69 J12
AA17 VSS5 VSS70 J14
+1.5V AA19 J16
VSS6 VSS71
AB2 VSS7 VSS72 J18
AB7 VSS8 VSS73 K2
1 1 AB9 VSS9 VSS74 K7
C64 C65 AB23 K9
VSS10 VSS75
AB25 VSS11 VSS76 K11
0.01U_0402_25V7K 0.01U_0402_25V7K AC11 K13
2 2 VSS12 VSS77
AC13 VSS13 VSS78 K15
Between CPU Socket and DIMM AC15 VSS14 VSS79 K17
AC17 VSS15 VSS80 L6
AC19 VSS16 VSS81 L8
AC21 VSS17 VSS82 L10
+1.5V AD6 L12
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch> VSS18 VSS83
AD8 VSS19 VSS84 L14
AD25 VSS20 VSS85 L16
1 1 1 1 AE11 VSS21 VSS86 L18
C66 C67 C68 C69 AE13 M7
VSS22 VSS87
AE15 VSS23 VSS88 M9
180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J AE17 AC6
2 2 2 2 VSS24 VSS89
AE19 VSS25 VSS90 M17
Between CPU Socket and DIMM AE21 VSS26 VSS91 N4
C56 Co-layout with C75 AE23 VSS27 VSS92 N8
B4 VSS28 VSS93 N10
330U_D2E_2.5VM_R6M
+1.5V +1.5V B6 N16

3 VSS29 VSS94 3
B8 VSS30 VSS95 N18
390U_2.5V_M_R10
1 1 B9 VSS31 VSS96 P2
1 1 1 1 B11 VSS32 VSS97 P7
C71 C72 C73 C74 @ + C56 + B13 P9
VSS33 VSS98
B15 VSS34 VSS99 P11
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C75 B17 P17
2 2 2 2 2 2 VSS35 VSS100
B19 VSS36 VSS101 R8
Between CPU Socket and DIMM B21 VSS37 VSS102 R10
B23 VSS38 VSS103 R16
B25 VSS39 VSS104 R18
D6 VSS40 VSS105 T7
D8 VSS41 VSS106 T9
+1.05VS
VDDR decoupling. D9
D11
VSS42 VSS107 T11
T13
VSS43 VSS108
D13 VSS44 VSS109 T15
1 1 1 1 1 1 1 1 C1124 Co-layout with C1125 D15 VSS45 VSS110 T17
C57 C58 C59 C60 C61 C62 C63 C70 D17 U4
VSS46 VSS111
D19 VSS47 VSS112 U6
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J +1.05VS +1.05VS D21 U8
2 2 2 2 2 2 2 2 VSS48 VSS113
D23 VSS49 VSS114 U10
330U_D2E_2.5VM
390U_2.5V_M_R10
Near CPU Socket Right side @ 1 1 D25 U12

+1.05VS VSS50 VSS115
E4 VSS51 VSS116 U14
C1125
C1124
+ + F2 U16
VSS52 VSS117
F11 VSS53 VSS118 U18
1 1 1 1 1 1 1 1 F13 VSS54 VSS119 V2
C76 C77 C78 C79 C80 C81 C82 C83 2 2
F15 VSS55 VSS120 V7
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J F17 V9
VSS56 VSS121
F19 VSS57 VSS122 V11
2 2 2 2 2 2 2 2
Near CPU Socket Left side F23 VSS59 VSS124 V15
H7 VSS61 VSS126 W6
4 4
H9 VSS62 VSS127 Y21
H21 VSS63 VSS128 Y23
+VDDNB decoupling : Northbridge power H23
J4
VSS64 VSS129 N6
+VDDNB VSS65
CONN@
1 1 1
C42 C43 C49 Security Classification Compal Secret Data Compal Electronics, Inc.
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2
SCHEMATICS,MB A6843
A B C D E
A B C D E
+1.5V +1.5V
JDDRL
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
4.7U_0805_10V4Z VSS2 DQ4
0.01U_0402_25V7K
1000P_0402_25V8J
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
7 DQ1 VSS3 8
1 2 1 9 10 DDR_A_DQS#0
VSS4 DQS#0 DDR_A_DQS#0 <6>
C84 C85 C10 DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0 DDR_A_DQS0 <6> DDR_A_D[0..63]
13 VSS5 VSS6 14 DDR_A_D[0..63] <6>
2 1 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 DDR_A_DM[0..7]
17 DQ3 DQ7 18 DDR_A_DM[0..7] <6>
19 VSS7 VSS8 20
1 DDR_A_D8 DDR_A_D12 1
21 DQ8 DQ12 22
DQ9 DQ13 DDR_A_MA[0..15]
25 VSS9 VSS10 26 DDR_A_MA[0..15] <6>
DDR_A_DQS#1 27 28 DDR_A_DM1
<6> DDR_A_DQS#1 DQS#1 DM1
DDR_A_DQS1 29 30 MEM_MA_RST#
<6> DDR_A_DQS1 DQS1 RESET# MEM_MA_RST# <6>
31 VSS11 VSS12 32
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS2 47 48
<6> DDR_A_DQS2 DQS2 VSS17
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29 +1.5V
DDR_A_D25 DQ24 DQ29 +1.5V
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
2
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3 DDR_A_DQS3 <6>
2
65 66 R310
DDR_A_D26 VSS23 VSS24 DDR_A_D30 R48 1K_0402_1%
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31 1K_0402_1%
DQ27 DQ31
71 72
1
VSS25 VSS26
1
+VREF_DQ +VREF_CA
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<6> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6>
75 VDD1 VDD2 76
2
77 78 DDR_A_MA15
NC1 A15
2
2 DDR_A_BS#2 DDR_A_MA14 R315 2
<6> DDR_A_BS#2 79 BA2 A14 80
81 82 R49 1K_0402_1%
DDR_A_MA12 VDD3 VDD4 DDR_A_MA11 1K_0402_1%
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7
1
A9 A7
87 88
1
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
A5 A4
93 VDD7 VDD8 94
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_A_CLK0 101 102 DDR_A_CLK1 < Close to JDDRH & JDDRL >
<6> DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 <6>
DDR_A_CLK#0 103 104 DDR_A_CLK#1
<6> DDR_A_CLK#0 CK0# CK1# DDR_A_CLK#1 <6>
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <6>
DDR_A_BS#0 109 110 DDR_A_RAS#
<6> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <6>
111 VDD13 VDD14 112
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
<6> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <6>
DDR_A_CAS# 115 116 DDR_A_ODT0
<6> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <6>
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDR_A_ODT1
A13 ODT1 DDR_A_ODT1 <6>
DDR_CS1_DIMMA# 121 122
<6> DDR_CS1_DIMMA# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
1000P_0402_25V8J
0.01U_0402_25V7K
4.7U_0805_10V4Z
DDR_A_D32 129 130 DDR_A_D36
131 DQ33 DQ37 132
133 VSS29 VSS30 134 1 1 2
DDR_A_DQS#4 135 136 DDR_A_DM4 C235 C351 +1.5V
DDR_A_DQS4 137 138 C680
139 140 DDR_A_D38 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2 1
141 DQ34 DQ39 142 2 2 2 2 2 2 2 2 2 2
3 DDR_A_D35 3
143 DQ35 VSS33 144
145 146 DDR_A_D44 C87 C88 C640 C641 C642 C643 C644 C645 C646 C647
DDR_A_D40 VSS34 DQ44 DDR_A_D45 0.1U_0402_16V4Z
147 DQ40 DQ45 148
DDR_A_D41 1 1 1 1 1 1 1 1 1 1
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_DM5 153 154 DDR_A_DQS5
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS6 171 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 +0.75VS
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 0.1U_0402_16V4Z
DDR_A_DM7 187 188 DDR_A_DQS7 2 2 1
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62 C665 C664 C961
193 DQ59 DQ63 194
1 1 2
195 VSS51 VSS52 196
197 198 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
SA0 EVENT#
+3VS 199 VDDSPD SDA 200 SMB_CK_DAT0 <10,19>
201 SA1 SCL 202 SMB_CK_CLK0 <10,19>
+0.75VS 203 VTT1 VTT2 204 +0.75VS
1
4 C91 4
205 G1 G2 206
TYCO_2-2013289-1
0.1U_0402_16V4Z 2 CONN@

2010-08-25 2010-08-25 Title
DIMM_A STD H:5.2 mm Issued Date Deciphered Date
SCHEMATICS,MB A6843
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A B C D E
A B C D E
+1.5V +1.5V
JDDRH
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 DQ0 DQ5 6
1000P_0402_25V8J
DDR_B_D1 7 8
DQ1 VSS3
0.1U_0402_16V4Z
4.7U_0805_10V4Z
9 10 DDR_B_DQS#0
VSS4 DQS#0 DDR_B_DQS#0 <6>
1 1 1 DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0 DDR_B_DQS0 <6> DDR_B_D[0..63]
C92 C93 C682 13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6 DDR_B_D[0..63] <6>
15 DQ2 DQ6 16
DDR_B_D3 17 18 DDR_B_D7 DDR_B_DM[0..7]
2 2 2 DQ3 DQ7 DDR_B_DM[0..7] <6>
19 VSS7 VSS8 20
1 DDR_B_D8 DDR_B_D12 1
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13 DDR_B_MA[0..15] <6>
DQ9 DQ13 DDR_B_MA[0..15]
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
<6> DDR_B_DQS#1 DQS#1 DM1
DDR_B_DQS1 29 30 MEM_MB_RST#
<6> DDR_B_DQS1 DQS1 RESET# MEM_MB_RST# <6>
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS2 47 48
<6> DDR_B_DQS2 DQS2 VSS17
49 50 DDR_B_D22
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3 DDR_B_DQS3 <6>
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB
<6> DDR_CKE0_DIMMB CKE0 CKE1 DDR_CKE1_DIMMB <6>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
2 DDR_B_BS#2 NC1 A15 DDR_B_MA14 2
<6> DDR_B_BS#2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_B_CLK0 101 102 DDR_B_CLK1
<6> DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 <6>
DDR_B_CLK#0 103 104 DDR_B_CLK#1
<6> DDR_B_CLK#0 CK0# CK1# DDR_B_CLK#1 <6>
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 <6>
DDR_B_BS#0 109 110 DDR_B_RAS#
<6> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <6>
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDR_CS0_DIMMB#
<6> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <6>
DDR_B_CAS# 115 116 DDR_B_ODT0
<6> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <6>
117 VDD15 VDD16 118
DDR_B_MA13 119 120 DDR_B_ODT1
A13 ODT1 DDR_B_ODT1 <6>
DDR_CS1_DIMMB# 121 122
<6> DDR_CS1_DIMMB# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
1000P_0402_25V8J
4.7U_0805_10V4Z
0.1U_0402_16V4Z
DDR_B_D32 129 130 DDR_B_D36
131 DQ33 DQ37 132
133 VSS29 VSS30 134 1 1 1
DDR_B_DQS4 137 138
<6> DDR_B_DQS4 DQS4 VSS31
139 140 DDR_B_D38 C683 C352 C353
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2 2
141 DQ34 DQ39 142
3 DDR_B_D35 3
143 DQ35 VSS33 144
145 146 DDR_B_D44
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152 DDR_B_DQS#5 <6>
DDR_B_DM5 153 154 DDR_B_DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47 +1.5V
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
165 DQ49 DQ53 166 2 2 2 2 2 2 2 2 2 2
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6 C666 C667 C668 C669 C670 C671 C672 C673 C674 C677
DDR_B_DQS6 171 172
<6> DDR_B_DQS6 DQS6 VSS43 1 1 1 1 1 1 1 1 1 1
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184 C128 Co-layout with C86
185 186 DDR_B_DQS#7
DDR_B_DM7 187 188 DDR_B_DQS7 +0.75VS
189 190 +1.5V +1.5V
DDR_B_D58 VSS49 VSS50 DDR_B_D62 0.1U_0402_16V4Z
191 DQ58 DQ62 192
DDR_B_D59 193 194 DDR_B_D63 2 2 1 1 1
DQ59 DQ63
195 VSS51 VSS52 196
197 198 C676 C675 C925 + C86 + C128
SA0 EVENT# @ 330U_X_2VM_R6M
+3VS 199 VDDSPD SDA 200 SMB_CK_DAT0 <9,19> 1 1 2 390U_2.5V_M_R10
201 SA1 SCL 202 SMB_CK_CLK0 <9,19>
0.1U_0402_16V4Z 4.7U_0603_6.3V6K 2 2
+0.75VS 203 VTT1 VTT2 204 +0.75VS
4 4
205 G1 G2 206
Place near DIMM2
LOTES_AAA-DDR-111-K01
CONN@

DIMM_B STD H:9.2 mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6843
<Address: 01> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401982 B
A B C D E
A B C D E
U3B
D4 GFX_RX0P GFX_TX0P A5
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
A3 GFX_RX1P GFX_TX1P A4
B3 GFX_RX1N GFX_TX1N B4
C2 GFX_RX2P GFX_TX2P C3
C1 GFX_RX2N GFX_TX2N B2
E5 GFX_RX3P GFX_TX3P D1
F5 GFX_RX3N GFX_TX3N D2
G5 GFX_RX4P GFX_TX4P E2
G6 GFX_RX4N GFX_TX4N E1
H5 GFX_RX5P GFX_TX5P F4
H6 GFX_RX5N GFX_TX5N F3
J6 GFX_RX6P GFX_TX6P F1
1 1
J5 GFX_RX6N GFX_TX6N F2
J7 GFX_RX7P GFX_TX7P H4
J8 GFX_RX7N GFX_TX7N H3
L5 GFX_RX8P GFX_TX8P H1
L6 GFX_RX8N GFX_TX8N H2
M8 GFX_RX9P GFX_TX9P J2
L8 GFX_RX9N GFX_TX9N J1
PCIE I/F GFX

P7 GFX_RX10P GFX_TX10P K4
M7 GFX_RX10N GFX_TX10N K3
P5 GFX_RX11P GFX_TX11P K1
M5 GFX_RX11N GFX_TX11N K2
R8 GFX_RX12P GFX_TX12P M4
P8 GFX_RX12N GFX_TX12N M3
R6 GFX_RX13P GFX_TX13P M1
R5 GFX_RX13N GFX_TX13N M2
P4 GFX_RX14P GFX_TX14P N2
P3 N1
T4
GFX_RX14N
GFX_RX15P
GFX_TX14N
GFX_TX15P P1 PCIE PORT LIST
T3 GFX_RX15N GFX_TX15N P2
AE3 AC1
PORT DEVICE
GPP_RX0P GPP_TX0P
AD4
AE2
GPP_RX0N GPP_TX0N AC2
AB4
PCIE-2 WLAN
GPP_RX1P GPP_TX1P
AD3
AD1
GPP_RX1N GPP_TX1N AB3
AA2 PCIE_ITX_PRX_P2 C129 1 2 0.1U_0402_16V7K
PCIE-3 LAN
<23> PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 <23>
< WLAN > AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2 C130 1 2 0.1U_0402_16V7K < WLAN >
<23> PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 <23>
V5 Y1 PCIE_ITX_PRX_P3 C131 1 2 0.1U_0402_16V7K
<24> PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 <24>
< LAN > W6 Y2 PCIE_ITX_PRX_N3 C132 1 2 0.1U_0402_16V7K < LAN >
<24> PCIE_PTX_C_IRX_N3 GPP_RX3N GPP_TX3N PCIE_ITX_C_PRX_N3 <24>
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2
2 2
<18> SB_RX0P AA8 AD7 SB_TX0P_C C133 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P <18>
<18> SB_RX0N Y8 AE7 SB_TX0N_C C134 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N <18>
< From SB820 : x4 PCIE A-link > <18> SB_RX1P AA7 AE6 SB_TX1P_C C135 1 2 0.1U_0402_16V7K
<18> SB_RX1N Y7 AD6 SB_TX1N_C C136 1 2 0.1U_0402_16V7K < To SB820 : x4 PCEI A-link>
<18> SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C137 1 2 0.1U_0402_16V7K
<18> SB_RX2N AA6 AC6 SB_TX2N_C C138 1 2 0.1U_0402_16V7K
<18> SB_RX3P W5 AD5 SB_TX3P_C C139 1 2 0.1U_0402_16V7K
<18> SB_RX3N Y5 AE5 SB_TX3N_C C140 1 2 0.1U_0402_16V7K
AC8 PCIE_CALRP R59 1 2 1.27K_0402_1% < TX Impedance Calibration. Connect to GND >
PCE_CALRP(PCE_BCALRP) PCIE_CALRN R58 2K_0402_1% < RX Impedance Calibration. Connect to VDDPCIE >
PCE_CALRN(PCE_BCALRN) AB8 1 2 +1.1VS
880MR1@ RS780M_FCBGA528
U3A
H_CADOP[0..15] H_CADOP0 Y25 D24 H_CADIP0 H_CADIP[0..15]
H_CADOP[0..15] <5> HT_RXCAD0P HT_TXCAD0P H_CADIP[0..15] <5>
H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
H_CADON[0..15] H_CADOP1 HT_RXCAD0N HT_TXCAD0N H_CADIP1 H_CADIN[0..15]
H_CADON[0..15] <5> V22 HT_RXCAD1P HT_TXCAD1P E24 H_CADIN[0..15] <5>
H_CADON1 V23 E25 H_CADIN1
H_CADOP2 HT_RXCAD1N HT_TXCAD1N H_CADIP2
V25 HT_RXCAD2P HT_TXCAD2P F24
H_CADON2 V24 F25 H_CADIN2
U24 HT_RXCAD3P HT_TXCAD3P F23
H_CADON3 U25 F22 H_CADIN3
T25 HT_RXCAD4P HT_TXCAD4P H23
H_CADON4 T24 H22 H_CADIN4
HT_RXCAD4N HT_TXCAD4N
HYPER TRANSPORT CPU I/F
H_CADOP5 P22 J25 H_CADIP5

H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
P23 HT_RXCAD5N HT_TXCAD5N J24
H_CADOP6 P25 K24 H_CADIP6
P24 HT_RXCAD6N HT_TXCAD6N K25
H_CADOP7 N24 K23 H_CADIP7
N25 HT_RXCAD7N HT_TXCAD7N K22
3 3
< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>
H_CADOP8 AC24 F21 H_CADIP8
AC25 HT_RXCAD8N HT_TXCAD8N G21
H_CADOP9 AB25 G20 H_CADIP9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
U18 HT_RXCAD15N HT_TXCAD15N M18
<5> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <5>

<5> H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 <5>
<5> H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 <5>
<5> H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 <5>
H_CTLOP0 M22 M24 H_CTLIP0
<5> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 <5>
H_CTLON0 M23 M25 H_CTLIN0
<5> H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 <5>
H_CTLOP1 R21 P19 H_CTLIP1
<5> H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 <5>
H_CTLON1 R20 R18 H_CTLIN1
<5> H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 <5>
301_0402_1%1 2 R60 HT_RXCALP C23 B24 HT_TXCALP R61 1 2 301_0402_1% < Transmitter Calibration Resistor to HT_TXCALN >
HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
A24 HT_RXCALN HT_TXCALN B25
0718 Place within 1" 880MR1@ RS780M_FCBGA528 0718 Place within 1"
4 4
layout 1:2 layout 1:2

SCHEMATICS,MB A6843
A B C D E
A B C D E
AVDD=100mA U3C
+3VS +AVDD1 F12 A22 LCD_TXOUT0+
AVDD1(NC) TXOUT_L0P(NC) LCD_TXOUT0+ <17>
L3 E12 PART 3 OF 6 B22 LCD_TXOUT0- LCD_TXOUT0- <17>
AVDD2(NC) TXOUT_L0N(NC)
1 2 BLM18PG121SN1D_0603 +AVDD1 +AVDD2 F14 AVDDDI(NC) TXOUT_L1P(NC) A21 LCD_TXOUT1+ LCD_TXOUT1+ <17>
1 G15 B21 LCD_TXOUT1- LCD_TXOUT1- <17>
C144 +AVDDQ AVSSDI(NC) TXOUT_L1N(NC) LCD_TXOUT2+
H15 AVDDQ(NC) TXOUT_L2P(NC) B20 LCD_TXOUT2+ <17>
H14 A20 LCD_TXOUT- LCD_TXOUT2- <17>
2.2U_0603_6.3V4Z AVSSQ(NC) TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC) A19
2 < LVDS dual channel : channel 1 >
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
CRT/TVOUT
F17 Y(DFT_GPIO2)
+1.8VS F15 B18
COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC)
TXOUT_U0N(NC) A18
L4 0_0603_5% +AVDD2 G18 A17
<16> UMA_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
1 1 G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17
C142 C145 E18 D20
1 <16> UMA_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC) 1
F18 GREENb(NC) TXOUT_U2N(NC) D21
2.2U_0603_6.3V4Z 0.1U_0402_16V7K E19 D18
2 2 <16> UMA_CRT_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) < LVDS dual channel : channel 2 >
F19 BLUEb(NC) TXOUT_U3N(NC) D19
A11 B16 LCD_TXCLK+ LCD_TXCLK+ <17>

<15,16> UMA_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
B11 A16 LCD_TXCLK- LCD_TXCLK- <17>
+1.8VS <15,16> UMA_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
<16> UMA_CRT_CLK F8 DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4) D16
L6 E8 D17
<16> UMA_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) +1.8VS
1 2 BLM18PG121SN1D_0603 +AVDDQ
1 R65 1 2 715_0402_1% G14 L8
C148 DAC_RSET(PWM_GPIO1) +VDDLTP18 +VDDLTP18 BLM18PG121SN1D_0603 1
VDDLTP18(NC) A13 2
+NB_PLLVDD A12 B13 1
2.2U_0603_6.3V4Z +NB_HTPVDD PLLVDD(NC) VSSLTP18(NC) C153
D14 PLLVDD18(NC)
2 +VDDLT18
B12 A15
LVTM
PLLVSS(NC) VDDLT18_1(NC) 2.2U_0603_6.3V4Z
B15
PLL PWR
+VDDA18HTPLL VDDLT18_2(NC) 2
H17 VDDA18HTPLL VDDLT33_1(NC) A14
VDDLT33_2(NC) B14
+1.1VS +VDDA18PCIEPLL D7
L2 VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
1 2 BLM18PG121SN1D_0603 +NB_PLLVDD D15 +1.8VS
VSSLT2(VSS)
1 <15,18,23,24,28,29> PLT_RST#
R66 1 2 0_0402_5% NB_RESET# D8 SYSRESETb VSSLT3(VSS) C16 L10
C141 A10 C18 +VDDLT18 BLM18PG121SN1D_0603 1 2
<19> NB_PWRGD POWERGOOD VSSLT4(VSS)
NB_LDTSTOP# C10 C20 1 1
2.2U_0603_6.3V4Z LDTSTOPb VSSLT5(VSS) C156 C157
C12 E20
PM
2 <18> CPU_LDT_REQ# ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
C25 0.1U_0402_16V7K 4.7U_0805_10V4Z
<18> HT_REFCLKP HT_REFCLKP 2 2
<18> HT_REFCLKN C24 HT_REFCLKN
+1.8VS
L5 NB_REFCLK_P E11
<18> NB_REFCLK_P REFCLK_P/OSCIN(OSCIN)
CLOCKs
1 2 BLM18PG121SN1D_0603 +NB_HTPVDD
<18> NB_REFCLK_N
NB_REFCLK_N F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9 UMA_ENVDD <17>
1 R330 4.7K_0402_5% F7 @R71
@ R71 1 2 0_0402_5%
C146 LVDS_BLON(PCE_RCALRP) UMA_ENBKL
2 1 T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12 UMA_ENBKL <28>
2 2
2 1 T1 GFX_REFCLKN
2.2U_0603_6.3V4Z R331 4.7K_0402_5% UMA_INVT_PWM <17>
2
U1 GPP_REFCLKP
U2 GPP_REFCLKN
<18> CLK_SBSRC_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)

<18> CLK_SBSRC_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)
LCD_EDID_CLK B9
<17> LCD_EDID_CLK I2C_CLK
LCD_EDID_DATA TMDS_HPD
+1.8VS <17> LCD_EDID_DATA A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
PAD T9
T10 PAD DDC_DATA0/AUX0N(NC) HPD(NC)
L7 A8 DDC_CLK0/AUX0P(NC)
1 2 BLM18PG121SN1D_0603 +VDDA18HTPLL B7 DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) D12 SUS_STAT# <15,19>
< Strap option pin or gate side-port memory IO >
1 A7 DDC_DATA1/AUX1N(NC)
C150 AE8
THERMALDIODE_P
T8 PAD B10 STRP_DATA THERMALDIODE_N AD8
2.2U_0603_6.3V4Z
2 R84 1
G11 RSVD TESTMODE D13 2 1.8K_0402_5%
Strap pin
<15> AUX_CAL C8 AUX_CAL(NC)
+1.8VS
L9 880MR1@ RS780M_FCBGA528
1 2 BLM18PG121SN1D_0603 +VDDA18PCIEPLL
1
C154
< Dedicated power for the DAC which can affect display quality >
2.2U_0603_6.3V4Z
2
3 3
+1.8VS
+1.8VS R68 1 2 300_0402_5% NB_PWRGD
2
R366 1 2 1K_0402_1% CPU_LDT_REQ# +1.8VS

R980
C1256
2.2K_0402_5%
1 2
1
0.1U_0402_16V7K
5
U57
2
P
R987 B
1 2 140_0402_1% UMA_CRT_R Y 4 NB_LDTSTOP#
<7,18> LDT_STOP# 1 A
G
R988 1 2 150_0402_1% UMA_CRT_G NC7SZ08P5X_NL_SC70-5

3
R989 1 2 150_0402_1% UMA_CRT_B
1 2
R981 0_0402_5%
@
4 4

SCHEMATICS,MB A6843
A B C D E
2 1
U3D
PAR 4 OF 6
AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19
SBD_MEM/DVO_I/F
AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17 MEM_BA1(NC)
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
AD18 MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
V14 MEM_ODT(NC)
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
W14 MEM_CKN(NC)
B B
IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18
880MR1@
RS780M_FCBGA528
A A

SCHEMATICS,MB A6843
2 1
A B C D E
U3E < Main IO power for PCI-E graphics, SB, and GPP interfaces >
2A < Digital IO power for HyperTransport interface >
+1.1VS 2 1 L11 0_0805_5% +VDDHT J17 A6 +VDDA11PCIE FBMA-L11-201209-221LMA30T_0805 1 2 L44 +1.1VS
VDDHT_1 VDDPCIE_1
1 1 1 1 1 K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6
C1126
C173
C174
C160
C162
C163
C171
C172
C165 C166 C167 C168 C159 L16 C6 VDDA_12=2.5A
VDDHT_3 VDDPCIE_3
M16 VDDHT_4 VDDPCIE_4 D6
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K P16 E6 1 1 1 1 2 2
2 2 2 2 2 VDDHT_5 VDDPCIE_5
R16 VDDHT_6 VDDPCIE_6 F6
T16 VDDHT_7 VDDPCIE_7 G7
2A < IO power for HyperTransport receive interface > VDDPCIE_8 H8
2 2 2 2 1 1
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 1 L13 0_0805_5% +VDDHTRX H18 J9
VDDHTRX_1 VDDPCIE_9
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 G19 VDDHTRX_2 VDDPCIE_10 K9
C179 C164 C169 C170 C161 F20 M9
1 VDDHTRX_3 VDDPCIE_11 1
E21 VDDHTRX_4 VDDPCIE_12 L9
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K D22 P9
2 2 2 2 VDDHTRX_5 VDDPCIE_13
B23 VDDHTRX_6 VDDPCIE_14 R9
A23 VDDHTRX_7 VDDPCIE_15 T9
2A < IO power for HyperTransport transmit interface > VDDPCIE_16 V9
+1.1VS 2 1 L14 0_0805_5% +VDDHTTX AE25 U9
VDDHTTX_1 VDDPCIE_17
1 1 1 1 1 AD24 VDDHTTX_2
C1127 C175 C176 C177 C178 AC23 K12
VDDHTTX_3 VDDC_1
AB22 VDDHTTX_4 VDDC_2 J14
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AA21 U16 +NB_CORE
2 2 2 2 2 VDDHTTX_5 VDDC_3
Y20 VDDHTTX_6 VDDC_4 J11
W19 VDDHTTX_7 VDDC_5 K15 < Core power > VDD_CORE:GM=5A/PM=10A
POWER
V18 VDDHTTX_8 VDDC_6 M12
U17 VDDHTTX_9 VDDC_7 L14 C1129 Co-layout with C189
T17 VDDHTTX_10 VDDC_8 L11
C191
C182
C187
C193
C194
C180
C188
C183
C195
R17 VDDHTTX_11 VDDC_9 M13
C184
C196
C189
P17 M15 1 +NB_CORE
VDDHTTX_12 VDDC_10
M17 VDDHTTX_13 VDDC_11 N12 2 2 2 2 2 2 2 2 2 1 1
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces > N14 +
VDDC_12 1
+1.8VS 2 1 L15 0_0805_5% +VDDA18PCIE J10 P11
VDDA18PCIE_1 VDDC_13 +
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
330U_D2E_2.5VM
1 1 1 1 1 1 P10 P13 C1129
C181 C1128 C185 C190 C186 C192 VDDA18PCIE_2 VDDC_14 1 1 1 1 1 1 1 1 1 2 2 2 @ 330U_2.5V_M
K10 VDDA18PCIE_3 VDDC_15 P14
M10 VDDA18PCIE_4 VDDC_16 R12
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2
L10 VDDA18PCIE_5 VDDC_17 R15
2 2 2 2 2 2
W9 VDDA18PCIE_6 VDDC_18 T11
H9 VDDA18PCIE_7 VDDC_19 T15
T10 VDDA18PCIE_8 VDDC_20 U12
R10 VDDA18PCIE_9 VDDC_21 T14
Y9 VDDA18PCIE_10 VDDC_22 J16
AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
2 2
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
< 1.8V IO transform power > VDD_MEM5(NC) AB10
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10
1 G9 VDD18_2
C197 AE11 H11 < 3.3V IO power >
VDD18_MEM1(NC) VDD33_1(NC)
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12 +3VS
1U_0402_6.3V4Z 1 1
2 880MR1@ RS780M_FCBGA528 C198 C199
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
U3F
A25 VSSAHT1 VSSAPCIE1 A2
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
H19 VSSAHT7 VSSAPCIE7 G2
J22 VSSAHT8 VSSAPCIE8 G4
L17 VSSAHT9 VSSAPCIE9 H7
L22 VSSAHT10 VSSAPCIE10 J4
L24 VSSAHT11 VSSAPCIE11 R7
L25 VSSAHT12 VSSAPCIE12 L1
M20 VSSAHT13 VSSAPCIE13 L2
N22 VSSAHT14 VSSAPCIE14 L4
P20 VSSAHT15 VSSAPCIE15 L7
R19 VSSAHT16 VSSAPCIE16 M6
R22 VSSAHT17 VSSAPCIE17 N4
R24 VSSAHT18 VSSAPCIE18 P6
R25 VSSAHT19 VSSAPCIE19 R1
3 3
H20 VSSAHT20 VSSAPCIE20 R2
U22 VSSAHT21 VSSAPCIE21 R4
V19 VSSAHT22 VSSAPCIE22 V7
GROUND
W22 VSSAHT23 VSSAPCIE23 U4
W24 VSSAHT24 VSSAPCIE24 V8
W25 VSSAHT25 VSSAPCIE25 V6
Y21 VSSAHT26 VSSAPCIE26 W1
AD25 VSSAHT27 VSSAPCIE27 W2
VSSAPCIE28 W4
L12 VSS11 VSSAPCIE29 W7
M14 VSS12 VSSAPCIE30 W8
N13 VSS13 VSSAPCIE31 Y6
P12 VSS14 VSSAPCIE32 AA4
P15 VSS15 VSSAPCIE33 AB5
R11 VSS16 VSSAPCIE34 AB1
R14 VSS17 VSSAPCIE35 AB7
T12 VSS18 VSSAPCIE36 AC3
U14 VSS19 VSSAPCIE37 AC4
U11 VSS20 VSSAPCIE38 AE1
U15 VSS21 VSSAPCIE39 AE4
V12 VSS22 VSSAPCIE40 AB2
W11 VSS23
W15 VSS24
AC12 VSS25 VSS1 AE14
AA14 VSS26 VSS2 D11
Y18 VSS27 VSS3 G8
AB11 VSS28 VSS4 E14
AB15 VSS29 VSS5 E15
AB17 VSS30 VSS6 J15
AB19 VSS31 VSS7 J12
AE20 VSS32 VSS8 K14
AB21 VSS33 VSS9 M11
4 4
K11 VSS34 VSS10 L15
880MR1@ RS780M_FCBGA528

SCHEMATICS,MB A6843
A B C D E
A B C D E
< RS880 VSYNC mux at CRT_VSYNC pull High to 3K > < VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >
Enables the Test Debug Bus using GPIO.

R92
3K_0402_5%
1 : Disable (RX881, RS880)
<12,16> UMA_CRT_VSYNC 2 1 +3VS
0 : Enable (RX881, RS880)
PIN: RS880--> VSYNC#

1 R93 1
@ 2 1 3K_0402_5%
< RS880 use register to control PCI-E configure > < DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011
< SUS_SATA# : LOAD_EEPROM_STRAPS >

< RS880 SUS_STAT# >
Selects Loading of STRAPS from EPROM
R85
1 2 150_0402_1%
<12> AUX_CAL 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
2 2
D1 RS880:SUS_STAT#
<12,19> SUS_STAT# @ 2 1 CH751H-40PT_SOD323-2 PLT_RST# <12,18,23,24,28,29>
< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >

< RS880 use HSYNC to enable SIDE PORT (internal pull high) >
RX881: Enables the Test Debug Bus using PCIE bus
R94
2 1 3K_0402_5%
1 : Disable ( Can still be enabled using nbcfg register access )
<12,16> UMA_CRT_HSYNC +3VS
0 : Enable
RS880: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS880)
0 : Enable (RS880)
3 3
4 4

SCHEMATICS,MB A6843
A B C D E
A B C D E
+5VS
D7 +R_CRT_VCC +CRT_VCC
< CRT CONNECTOR > 2 F1
1 1 2 1.1A_6V_MINISMDC110F-2
3 1
C237
RB491D_SOT23-3 @ 0.1U_0402_16V4Z
2
1
D19 D20 D21
@ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59 JCRT
1 1
6 6
+3VS 11
RED_L 11
1
3
1
7 7
D_DDCDATA 12
GREEN_L 12
2 2
8 8
L22 HSYNC 13 13
<12> UMA_CRT_R 1 2 NBQ100505T-800Y-N_2P RED_L BLUE_L 3 3
+CRT_VCC 9 9
L23 VSYNC 14 16
14 G
<12> UMA_CRT_G 1 2 NBQ100505T-800Y-N_2P GREEN_L 4 4 G 17
10 10
L24 D_DDCCLK 15 15
<12> UMA_CRT_B 1 2 NBQ100505T-800Y-N_2P BLUE_L 5 5
ALLTO_C10532-11505-L_15P-T
1 1 1 1 1 1 CONN@
1
1
C239 C240 C241 C242 C243 C244
R98 R99 R100 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K
140_0402_1% 150_0402_1% 150_0402_1%
2 2 2 2 2 2
2
2
+CRT_VCC
2 R817 2
C245 1 2 0.1U_0402_16V4Z 1 2 10K_0402_5%
5
1
P
OE#
2 4 D_HSYNC L25 1 2 10_0402_5% HSYNC
<12,15> UMA_CRT_HSYNC A Y
G
U5
SN74AHCT1G125GW_SOT353-5 < SYNC SIGNAL >
3
L26 1 2 10_0402_5% VSYNC
+CRT_VCC
1 1
C247 C248
@ 10P_0402_50V8J @ 10P_0402_50V8J
5
1
2 2
P
OE#
2 4 D_VSYNC
<12,15> UMA_CRT_VSYNC A Y
G
U6
SN74AHCT1G125GW_SOT353-5
3 +CRT_VCC
+3VS
3 3
1
1
R824 R825 +3VS
4.7K_0402_5% 4.7K_0402_5% R805 R806
2K_0402_1% 2K_0402_1%
5
2
Q32B
2
<12> UMA_CRT_DATA 4 3 2N7002DW-T/R7_SOT363-6 D_DDCDATA
1
C255
@
33P_0402_50V8K
2
+3VS < Display Data Channel >

2
Q32A
1 6 2N7002DW-T/R7_SOT363-6 D_DDCCLK
<12> UMA_CRT_CLK
1
C256
@ 1 1
33P_0402_50V8K C251 C252
2
@ 470P_0402_50V8J @ 470P_0402_50V8J
2 2
FOR EMI
4 4

SCHEMATICS,MB A6843
A B C D E
A B C D E
+LCD_VDD
+3VS +3VS +LCD_VDD
1
150_0603_5%
LCD/PANEL BD. Conn.
R807
0.1U_0402_16V7K
1
2
R90
6 2
C259
W=20mils CAM@ D84 100K_0402_5% W=60mils
CAM@ 0.1U_0402_16V4Z 2
+3VS_LVDS_CAM 1 1
+3VS 1 2 2 1
3
S
AO3413_SOT23
1 R808 0_0603_5% C265 Q33A 1
3 G
JLVDS 2N7002DW-T/R7_SOT363-6 2 1 2 2
Q4
1 1 2 AZ5125-02S.R7G R91 1
2 LCD_EDID_CLK <12>
0.01U_0402_25V7K
USB20_P9_L 3 3 47K_0402_5%
4 4
D
LCD_EDID_DATA <12>
1
C260
USB20_N9_L 5 5 INT_MIC_CLK
6 6 INT_MIC_CLK <26>
3
7 7 INT_MIC_DATA
8 8 INVT_PWM
INT_MIC_DATA <26> 2
<12> LCD_TXOUT0+ 9 9 10 10 BKOFF#_R R983 2 BKOFF#
W=60mils
<12> LCD_TXOUT0- 11 11 12 12 1 33_0402_5% BKOFF# <28>
Q33B Inrush current = 0A
13 13 ENVDD 5
<12> LCD_TXOUT1+ 14 14 <12> UMA_ENVDD 1
0.1U_0402_16V7K
15 15 R200 1 2 10K_0402_5% 2N7002DW-T/R7_SOT363-6
<12> LCD_TXOUT1- 16 16
C262
<12> LCD_TXOUT2+ 17 17 18 18
4
<12> LCD_TXOUT2- 19 19 20 20 +3VS
1
2
<12> LCD_TXCLK+ 21 21 22 22 2A
23 23 +LCDVDD_R 2 L12
<12> LCD_TXCLK- 24 24 0_0805_5%
1 +LCD_VDD
25 25 26 26 1 1
27 27 R896
28 28 +LCD_INV
C266 C267
1 1
100K_0402_5%
29 29 30 30
2
0.1U_0402_16V4Z 4.7U_0805_10V4Z @ C152 C264
2 2 680P_0402_50V7K 0.1U_0402_16V4Z
31 GND1
EMI 2 2
32 GND2
ACES_87242-3001-09
CONN@
CAM@
1 2
R134 0_0402_5%
@ @
@ L20 C27 2 1 R23 1 2 INT_MIC_CLK
2 +LCD_INV B+ 1 2 USB20_P9_L 2
<19> USB20_P9 1 2
L45 10P_0402_50V8J 10_0402_5%
2 1
1 1 FBMA-L11-201209-221LMA30T_0805 4 3 USB20_N9_L
<19> USB20_N9 4 3
C268 C263 WCM-2012-900T_0805 Reserve C27, R231 for EMI
68P_0402_50V8J 0.1U_0402_25V6
2 2
1 2
R133 0_0402_5%
CAM@
@ R96 1 2 0_0402_5% INVT_PWM

<28> EC_INVT_PWM
1
R897 1 2 0_0402_5% R319
<12> UMA_INVT_PWM
10K_0402_5%
2
3 +3VS 3
LCD_EDID_CLK 2.2K_0402_5% 2 1 R117
LCD_EDID_DATA 2.2K_0402_5% 2 1 R118
4 4

SCHEMATICS,MB A6843
A B C D E
A B C D E
C572 1 2 150P_0402_50V8J U8A
R325 33_0402_5% P1
SB800 Part 1 of 5
W2
A_RST# PCIE_RST# PCICLK0
2 1 L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 <22>
PCI CLKS
PCICLK2/GPO37 W3 PCI_CLK2 <22>
C579 1 2 0.1U_0402_16V7K SB_RX0P_C AD26 W4 PCI_CLK3 <22>
<11> SB_RX0P A_TX0P PCICLK3/GPO38
C573 1 2 0.1U_0402_16V7K SB_RX0N_C AD27 Y1 PCI_CLK4 <22>
<11> SB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39
C574 1 2 0.1U_0402_16V7K SB_RX1P_C AC28
<11> SB_RX1P A_TX1P
C575 1 2 0.1U_0402_16V7K SB_RX1N_C AC29 V2
<11> SB_RX1N A_TX1N PCIRST#
C576 1 2 0.1U_0402_16V7K SB_RX2P_C AB29
<11> SB_RX2P A_TX2P
C580 1 2 0.1U_0402_16V7K SB_RX2N_C AB28
<11> SB_RX2N A_TX2N
C577 1 2 0.1U_0402_16V7K SB_RX3P_C AB26 AA1
<11> SB_RX3P A_TX3P AD0/GPIO0
C578 1 2 0.1U_0402_16V7K SB_RX3N_C AB27 AA4
<11> SB_RX3N A_TX3N AD1/GPIO1
1 AD2/GPIO2 AA3 1
<11> SB_TX0P AE24 A_RX0P AD3/GPIO3 AB1
<11> SB_TX0N AE23 A_RX0N AD4/GPIO4 AA5
<11> SB_TX1P AD25 AB2
PCI EXPRESS INTERFACES

A_RX1P AD5/GPIO5
<11> SB_TX1N AD24 A_RX1N AD6/GPIO6 AB6
<11> SB_TX2P AC24 A_RX2P AD7/GPIO7 AB5
<11> SB_TX2N AC25 A_RX2N AD8/GPIO8 AA6
<11> SB_TX3P AB25 A_RX3P AD9/GPIO9 AC2
<11> SB_TX3N AB24 A_RX3N AD10/GPIO10 AC3
AD11/GPIO11 AC4
R326 2 1 590_0402_1% AD29 AC1
R327 PCIE_CALRP AD12/GPIO12
+1.1VS_PCIE 2 1 2K_0402_1% AD28 PCIE_CALRN AD13/GPIO13 AD1
AD14/GPIO14 AD2
AA28 GPP_TX0P AD15/GPIO15 AC6
AA29 GPP_TX0N AD16/GPIO16 AE2
Y29 GPP_TX1P AD17/GPIO17 AE1
Y28 GPP_TX1N AD18/GPIO18 AF8
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 GPP_TX2N AD20/GPIO20 AF1
W28 GPP_TX3P AD21/GPIO21 AG1
W29 GPP_TX3N AD22/GPIO22 AF2
AD23/GPIO23 AE9 PCI_AD23 <22>
AA22 GPP_RX0P AD24/GPIO24 AD9 PCI_AD24 <20,22>
+3VALW Y21 AC11
C581 GPP_RX0N AD25/GPIO25 PCI_AD25 <22>
AA25 GPP_RX1P AD26/GPIO26 AF6 PCI_AD26 <22>
2 1 AA24 GPP_RX1N AD27/GPIO27 AF4 PCI_AD27 <22>
W23 GPP_RX2P AD28/GPIO28 AF3 PCI_AD28 <22>
5
0.1U_0402_16V4Z U21 V24 AH2 PCI_AD29 <22>

GPP_RX2N AD29/GPIO29
2 W24 AG2
P
B GPP_RX3P AD30/GPIO30
Y 4 PLT_RST# <12,15,23,24,28,29> W25 GPP_RX3N AD31/GPIO31 AH3
A_RST# 1 AA8
A CBE0#
G
PCI INTERFACE
NC7SZ08P5X_NL_SC70-5 AD5
CBE1#
AD8
3
@ CBE2#
2 1 CBE3# AA10
2 R328 8.2K_0402_5% 2
FRAME# AE8
DEVSEL# AB9
<12> CLK_SBSRC_BCLK M23 PCIE_RCLKP/NB_LNK_CLKP IRDY# AJ3
<12> CLK_SBSRC_BCLK# P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
PAR AC5
NB_REFCLK_P U29 AF5
<12> NB_REFCLK_P NB_DISP_CLKP STOP#
NB_REFCLK_N U28 AE6
+3VS <12> NB_REFCLK_N NB_DISP_CLKN PERR#
SERR# AE4
+1.8VS HT_REFCLKP T26 AE11
<12> HT_REFCLKP NB_HT_CLKP REQ0#
HT_REFCLKN T27 AH5
<12> HT_REFCLKN NB_HT_CLKN REQ1#/GPIO40
2
REQ2#/CLK_REQ8#/GPIO41 AH4
R329 V21 AC12
<7> CLK_CPU_BCLK CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42
4.7K_0402_5% <7> CLK_CPU_BCLK# T21 CPU_HT_CLKN GNT0# AD12
2
G
GNT1#/GPO44 AJ5 2/23 Reserve R796 pull-down to CLKRUN#

V23 AH6
1
H_PWRGD SLT_GFX_CLKP GNT2#/GPO45

3 1 H_PWRGD_L <38> T23 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AB12
S
CLKRUN# AB11 1 2 7/15 Add R260 pull up to +3VS

Q21 L29 AD7 R796 10K_0402_5%
<24> CLK_PCIE_LAN GPP_CLK0P LOCK#
FDV301N_NL_SOT23-3 L28
<24> CLK_PCIE_LAN# GPP_CLK0N
INTE#/GPIO32 AJ6 BT_PWR# <23>
N29 AG6 BT_DET#
<23> CLK_PCIE_MCARD2 GPP_CLK1P INTF#/GPIO33
level shift to ISL6265 N28 AG4 BT_DET# 1 2 +3VS
<23> CLK_PCIE_MCARD2# GPP_CLK1N INTG#/GPIO34
AJ4 R260 8.2K_0402_5%
INTH#/GPIO35
M29 GPP_CLK2P
M28 BT_PWR# 1 2 +3VS
GPP_CLK2N R95 100K_0402_5%
ISL6265 PWROK input, TTL level: 0.8V~2.0V
T25
CLOCK GENERATOR
GPP_CLK3P
When this pin is high, the SVI interface is V25 GPP_CLK3N LPCCLK0 H24 CLK_PCI_EC <22,28>
H25 CLK_PCI_SIO <22,29>
active and I2C protocol is running. While this L24
LPCCLK1
J27 LPC_AD0 <28,29>
GPP_CLK4P LAD0
pin is low, the SVC, SVD, and VFIXEN input L23 GPP_CLK4N LAD1 J26 LPC_AD1 <28,29>
LAD2 H29 LPC_AD2 <28,29>
states determine the pre-PWROK metal VID or P25
LPC
H28 LPC_AD3 <28,29>
3 GPP_CLK5P LAD3 3
VFIX mode voltage. This pin must be low prior M25 GPP_CLK5N LFRAME# G28 LPC_FRAME# <28,29>
LDRQ0# J25
to the ISL6265 PGOOD output going high P29 GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 AA18
P28 GPP_CLK6N SERIRQ/GPIO48 AB19 SERIRQ <28,29>
N26 GPP_CLK7P
1 2 25M_CLK_X1 N27
C1254 GPP_CLK7N
ALLOW_LDTSTP/DMA_ACTIVE# G21 CPU_LDT_REQ# <12>
2
27P_0402_50V8J T29 H21 H_PROCHOT# <7>

Y6 GPP_CLK8P PROCHOT#
T28 GPP_CLK8N LDT_PG K19 H_PWRGD <7,38>
CPU
R971 G22 LDT_STOP# <7,12>

1M_0402_5% LDT_STP#
25MHZ_20PF_7A25000012 J24 R26 1 2 0_0402_5% LDT_RST# <7>
1
CLK_48M_CR LDT_RST#
<25> CLK_48M_CR L25
2
25M_CLK_X2 14M_25M_48M_OSC
1 2
C1255 C1 SB_32KHI
27P_0402_50V8J 32K_X1
4/26 Add test point T38 to T64 for debug 7/2 Add Net RTCCLK for EC Crystal cost down
25M_CLK_X1 L26 C2 SB_32KHO +RTCVCC
25M_X1 32K_X2 +RTCBATT
D2 D8
RTC
RTCCLK RTCCLK <28>

INTRUDER_ALERT# B2 2 +3VL
25M_CLK_X2 L27 B1 1 2 1 2 1 R141
25M_X2 VDDBT_RTC_G R333 120_0402_5% R142 120_0402_5% 3 1 2
1
@ R332 20M_0402_5%
@R332 C584 1 1 C585 W=20mils 1K_0402_5%
2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1 2 SB820M_FCBGA605 CHN202UPT SC-70
+
J1 1
2
SB820MR1@ @ JUMP_43X39 C583
C582 2 2 @
1
SB_32KHI for Clear CMOS
1 2
7/21 Change U8 P/N to SA00003IWA0 (A13) 2
1
18P_0402_50V8J Y3
1
4 OSC NC 3
R335 Close to SB 7/22 Change D8 from DAN202U to CHN202UPT
20M_0603_5% 1 2
OSC NC SUYIN_060003HA002G202ZL
4 4
32.768KHZ_12.5PF_Q13MC14610002 @JRTC
@ JRTC
-
C586
2
2
1 2 SB_32KHO
18P_0402_50V8J

SCHEMATICS,MB A6843
A B C D E
A B C D E
7/2 Add D27 for abnormal shutdown RSMRST#

D27
SB_PWRGD 2 1 POK <33,35,36>
CH751H-40PT_SOD323-2
U8D
J2 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC A10 PAD T20
K1 RI#/GEVENT22#
D3 G19 USB_RCOMP 1 2
EC_RSMRST# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP 11.8K_0402_1% R338
1 2 <28> PM_SLP_S3# F1 SLP_S3#
R339 2.2K_0402_5% H1
<28> PM_SLP_S5# SLP_S5#
ACPI / WAKE UP EVENTS

<28> PBTN_OUT# F2 PWR_BTN#
1 1
USB 1.1 USB MISC

<28> SB_PWRGD H5
G6
PWR_GOOD SB800 J10
<12,15> SUS_STAT# SUS_STAT# USB_FSD1P/GPIO186
B3 Part 4 of 5 H11
+3VS
T14
T12
PAD
PAD C4
TEST0
TEST1/TMS
USB_FSD1N
USB PORT LIST
T13 PAD F6 TEST2 USB_FSD0P/GPIO185 H9
<28>
<28>
GATEA20
KB_RST#
AD21
AE21
GA20IN/GEVENT0# USB_FSD0N J8
PORT DEVICE
KBRST#/GEVENT1#
R342 1 2 2.2K_0402_5% SMB_CK_CLK0 <28> EC_SCI# K2
J29
LPC_PME#/GEVENT3# USB_HSD13P B12
A12
USB0 USB0(Right)
<28> EC_SMI# LPC_SMI#/GEVENT23# USB_HSD13N
R343 1 2 2.2K_0402_5% SMB_CK_DAT0 H2
J1
GEVENT5#
F11
USB1 USB1(Right)
R344 1 SYS_RESET#/GEVENT19# USB_HSD12P
2 4.7K_0402_5% SUS_STAT#
USB5
<24> EC_SWI# H6
F3
WAKE#/GEVENT8# USB_HSD12N E11
Card Reader
IR_RX1/GEVENT20#
<7> H_THERMTRIP#
<12> NB_PWRGD
J6
AC19
THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P E14
E12
USB8 WLAN
NB_PWRGD USB_HSD11N
<28> EC_RSMRST# G1 J12

USB9 Int Camera
RSMRST# USB_HSD10P
USB_HSD10N J14
+3VS HDMI_DET AD19 CLK_REQ4#/SATA_IS0#/GPIO64
AA16 CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P A13 USB20_P9 <17>
AB21 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N B13 USB20_N9 <17> USB-9 Int Camera
2
<24> CLKREQ_LAN# AC18 CLK_REQ0#/SATA_IS3#/GPIO60

R105 AF20 D13
SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P USB20_P8 <23>
10K_0402_5%
@
AE19 SATA_IS5#/FANIN3/GPIO59 USB_HSD8N C13 USB20_N8 <23> USB-8 WLAN
<26> PCH_SPKR AF19 SPKR/GPIO66
<9,10> SMB_CK_CLK0 AD22 G12
1
SCL0/GPIO43 USB_HSD7P
USB 2.0
<9,10> SMB_CK_DAT0 AE22 SDA0/GPIO47 USB_HSD7N G14
HDMI_DET <23> SMB_CK_CLK1 F5 SCL1/GPIO227
<23> SMB_CK_DAT1 F4 SDA1/GPIO228 USB_HSD6P G16
2
AH21 CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N G18

R107 AB18
<23> CLKREQ_MCARD2# CLK_REQ1#/FANOUT4/GPIO61
10K_0402_5% E1 D16
GPIO
2 IR_LED#/LLB#/GPIO184 USB_HSD5P USB20_P5 <25> 2
AJ21 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N C16 USB20_N5 <25> USB-5 Card Reader 2 IN 1
H4
1
DDR3_RST#/GEVENT7#
D5 GBE_LED0/GPIO183 USB_HSD4P B14
D7 GBE_LED1/GEVENT9# USB_HSD4N A14
G5 GBE_LED2/GEVENT10#
K3 GBE_STAT0/GEVENT11# USB_HSD3P E18
AA20 CLK_REQG#/GPIO65/OSCIN USB_HSD3N E16
@R135
@ R135
@ C143 2 1 10P_0402_50V8J 2 1 AZ_BITCLK_HD J16
10_0402_5% USB_HSD2P
H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18
<28> EC_LID_OUT# D1 USB_OC6#/IR_TX1/GEVENT6#
E4 USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P B17 USB20_P1 <23>
USB OC
D4 USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N A17 USB20_N1 <23> USB-1 Right side
E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
F7 USB_OC2#/TCK/GEVENT14# USB_HSD0P A16 USB20_P0 <23>
E7 USB_OC1#/TDI/GEVENT13# USB_HSD0N B16 USB20_N0 <23> USB-0 Right side
<23,28> USB_OC#0 F8 USB_OC0#/TRST#/GEVENT12#
R345 1 2 33_0402_5%
<26> AZ_BITCLK_HD
<26> AZ_SDOUT_HD R346 1 2 33_0402_5% M3 D25
AZ_BITCLK SCL2/GPIO193
<22> HDA_SDOUT N1 AZ_SDOUT SDA2/GPIO194 F23
L2 B26 SB_SIC
<26> AZ_SDIN0_HD AZ_SDIN0/GPIO167 SCL3_LV/GPIO195
M2 E26 SB_SID
HD AUDIO
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 +3VALW
M1 AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197 F25
M4 AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198 E22
R351 1 2 33_0402_5% N2 F22
<26> AZ_SYNC_HD AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 GPIO199 <22>
R402 1 2 33_0402_5% P2 E21 STRAP PIN
<26> AZ_RST_HD# AZ_RST# EC_PWM3/EC_TIMER3/GPIO200 GPIO200 <22>
2
G24 GPIO201
GBE_COL KSI_0/GPIO201 GPIO202 @ R919 @ R920
@R920 R921
T1 GBE_COL KSI_1/GPIO202 G25
GBE_CRS T4 E28 GPIO203 +3VALW 10K_0402_5% 10K_0402_5% 10K_0402_5%
3 GBE_CRS KSI_2/GPIO203 GPIO204 3
L6 GBE_MDCK KSI_3/GPIO204 E29
GBE_MDIO L5 D29 GPIO205
1
GBE_MDIO KSI_4/GPIO205 GPIO201
T9 GBE_RXCLK KSI_5/GPIO206 D28
+3VALW U1 C29 GPIO202
GBE_RXD3 KSI_6/GPIO207 GPIO203
U3 GBE_RXD2 KSI_7/GPIO208 C28
T2 GBE_RXD1
GBE LAN
2
1 2 GBE_MDIO U2 B28
R352 10K_0402_5% GBE_RXD0 KSO_0/GPIO209 R922 R923 R924 R925 @ R928
@R928
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
EMBEDDED CTRL
GBE_RXERR V5 B27 10K_0402_5% 10K_0402_5% 1K_0402_1% 1K_0402_1% 10K_0402_5%
GBE_PHY_INTR GBE_RXERR KSO_2/GPIO211 @
1 2 P5 GBE_TXCLK KSO_3/GPIO212 D26
R358 10K_0402_5% M5 A26
1
GBE_TXD3 KSO_4/GPIO213 GPIO204
P9 GBE_TXD2 KSO_5/GPIO214 C26
1 2 GBE_COL T7 A24 GPIO205
R353 10K_0402_5% GBE_TXD1 KSO_6/GPIO215
P7 GBE_TXD0 KSO_7/GPIO216 B25
2
M7 GBE_TXCTL/TXEN KSO_8/GPIO217 A25
1 2 GBE_RXERR P4 D24 R926 R927
R356 10K_0402_5% +3VALW GBE_PHY_PD KSO_9/GPIO218
M9 GBE_PHY_RST# KSO_10/GPIO219 B24 10K_0402_5% 10K_0402_5%
GBE_PHY_INTR V7 C24 @
GBE_CRS GBE_PHY_INTR KSO_11/GPIO220
1 2 B23
1
R354 10K_0402_5% KSO_12/GPIO221 GPIO201 GPIO202 GPIO203
E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
1
E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22

EMBEDDED CTRL
R984 CIR_EN# F21 C22

10K_0402_5% SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224
G29 FC_RST#/GPO160 KSO_16/GPIO225 A22 Nile-M High High High
KSO_17/GPIO226 B22
D27 GPIO204 GPIO205
2
CIR_EN# PS2KB_DAT/GPIO189
F28 PS2KB_CLK/GPIO190 Nile-S High High Low
F29 PS2M_DAT/GPIO191
1
@ E27 Madison LP Low Low

+3VALW R985 PS2M_CLK/GPIO192
Danube Marseille Low Low Low
1K_0402_5%
SB820M_FCBGA605 None Low High
1 2 EC_LID_OUT# SB820MR1@ Danube Hamburg Low Low High
2
4 R357 100K_0402_5% 4
1 2 SB_SIC Park XT High Low
R359 2.2K_0402_5% Danube LC Marseille Low Low High
1 2 SB_SID *
R360 2.2K_0402_5% M92 XTX High High
1 2 H_THERMTRIP#
R361 10K_0402_5%
1 2 SMB_CK_CLK1
R362 2.2K_0402_5%
SMB_CK_DAT1
1 2 Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title
R363 2.2K_0402_5%
SCHEMATICS,MB A6843
A B C D E
A B C D E
U8B
AH9
SB800 AH28
1 <23> SATA_STX_DRX_P0 SATA_TX0P FC_CLK 1
<23> SATA_STX_DRX_N0 AJ9 SATA_TX0N Part 2 of 5 FC_FBCLKOUT AG28
HDD AJ8
FC_FBCLKIN AF26
<23> SATA_SRX_C_DTX_N0 SATA_RX0N
<23> SATA_SRX_C_DTX_P0 AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
FC_AVD#/GPIOD146 AG29
<23> SATA_STX_DRX_P1 AH10 SATA_TX1P FC_WE#/GPIOD148 AG26
<23> SATA_STX_DRX_N1 AJ10 SATA_TX1N FC_CE1#/GPIOD149 AF27
AE29
ODD AG10
FC_CE2#/GPIOD150
AF29
<23> SATA_SRX_C_DTX_N1 SATA_RX1N FC_INT1/GPIOD144
<23> SATA_SRX_C_DTX_P1 AF10 SATA_RX1P FC_INT2/GPIOD147 AH27
AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27

AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
FC_ADQ2/GPIOD130 AH25
AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
FC_ADQ8/GPIOD136 AF21
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22
AF14 AJ23
FLASH
SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17
SERIAL ATA
SATA_RX4P
AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
2 2
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
FANIN1/GPIO57 V9
R364 2 1 1K_0402_1% SATA_CALRP AB14 W8
SATA_CALRP FANIN2/GPIO58
+1.1VS_SATA R365 2 1 931_0402_1% SATA_CALRN AA14 SATA_CALRN
TEMPIN0/GPIO171 B6
A6 R43 1 2 150K_0402_5% +3VALW
TEMPIN1/GPIO172
AD11 SATA_ACT#/GPIO67 TEMPIN2/GPIO173 A5
TEMPIN3/TALERT#/GPIO174 B5
TEMP_COMM C7 2 1 D22 ACIN <28,34>
CH751H-40PT_SOD323-2
VIN0/GPIO175 A3
SATA_X1
HW MONITOR
AD16 SATA_X1 VIN1/GPIO176 B4
VIN2/GPIO177 A4
VIN3/GPIO178 C5
A7 MEM_1V5
VIN4/GPIO179
VIN5/GPIO180 B7
VIN6/GBE_STAT3/GPIO181 B8
SATA_X2 AC16 A8
SATA_X2 VIN7/GBE_LED3/GPIO182
DO J5 G27
DI SPI_DI/GPIO164 NC1
E2 Y2
SPI ROM
CLK SPI_DO/GPIO163 NC2
K4 SPI_CLK/GPIO162
CS# K9 SPI_CS1#/GPIO165
G2 ROM_RST#/GPIO161
SB820M_FCBGA605
3 +3VALW SB820MR1@ 3
20mils U47
8 VCC VSS 4
1
C445 3 W
0.1U_0402_16V4Z 7
2 HOLD
CS# 1 MEM_1V5 is for gating the 2/23 Reserve MEM_1V5 circuit for unsupport DDR-1333
S
CLK
glitch on PCI_AD24
6 C +3VS
DI 5 2 DO @ C688
D Q
2 1
MX25L1605DM2I-12G_SO8-200mil
0.1U_0402_16V4Z
2
5
@ @U23
@U23
R86 MEM_1V5 2
P
B
10_0402_5% Y 4 1 2 VDDR_SW <37>
1 2 1 @ R424 33_0402_5%
<18,22> PCI_AD24 A
G
@R422
@ R422 0_0402_5% 2
1
NC7SZ08P5X_NL_SC70-5
3
@ C689
1 150P_0402_50V8J
@ 1
1 2
C155 PCI_AD24 @ R423 0_0402_5%
2
10P_0402_50V8J 1 : VDDR=1.05V
0 : VDDR=0.9V
For VDDR Voltage Switch, AMD suggest
4 4

SCHEMATICS,MB A6843
A B C D E
4/16 Change U47 from SA00002TO00 to SA00003FO00
A B C D E
+1.1VS_VDDC U8E
510mA
1 2 +1.1VS
U8C R369 0_0805_5%
Part 3 of 5
SB800
131mA SB800 10U_0805_10V4Z C590
Y14 VSSIO_SATA_1 VSS_1 AJ2
+3VS AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13 1 2 Y16 VSSIO_SATA_2 VSS_2 A28
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 AB16 VSSIO_SATA_3 VSS_3 A2
1 2 Y19 N17 1U_0402_6.3V4Z 2 1 C596 AC14 E5
VDDIO_33_PCIGP_3 VDDCR_11_3 VSSIO_SATA_4 VSS_4
CORE S0
C591 22U_0805_6.3V6M AE5 U13 1U_0402_6.3V4Z 2 1 C594 AE12 D23
1 C592 0.1U_0402_16V4Z VDDIO_33_PCIGP_4 VDDCR_11_4 0.1U_0402_16V4Z C597 VSSIO_SATA_5 VSS_5 1
1 2 AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 2 1 AE14 VSSIO_SATA_6 VSS_6 E25
C593 1 2 0.1U_0402_16V4Z AA2 V12 0.1U_0402_16V4Z 2 1 C598 AF9 E6
PCI/GPIO I/O
C599 1 2 0.1U_0402_16V4Z AB4 V18 AF11 F24
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 AF13 VSSIO_SATA_9 VSS_9 N15
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W18 AF16 VSSIO_SATA_10 VSS_10 R13
AA9 VDDIO_33_PCIGP_10 AG8 VSSIO_SATA_11 VSS_11 R17
+1.1VS_CKVDD L69
AF7 VDDIO_33_PCIGP_11 400mA AH7 VSSIO_SATA_12 VSS_12 T10
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 2 1 +1.1VS AH11 VSSIO_SATA_13 VSS_13 P10
K29 FBMA-L11-201209-221LMA30T_0805 AH13 V11
VDDAN_11_CLK_2 VSSIO_SATA_14 VSS_14
VDDAN_11_CLK_3 J28
22U_0805_6.3V6M C595
External Clock, connect to +1.1VS AH16 VSSIO_SATA_15 VSS_15 U15
VDDAN_11_CLK_4 K26 1 2 AJ7 VSSIO_SATA_16 VSS_16 M18
71mA J21 directly, no need thick trace AJ11 V19
CLKGEN I/O
VDDAN_11_CLK_5 1U_0402_6.3V4Z C600 VSSIO_SATA_17 VSS_17
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 2 1 AJ13 VSSIO_SATA_18 VSS_18 M11
FLASH I/O
AE25 K21 1U_0402_6.3V4Z 2 1 C601 check can be removed? AJ16 L12
VDDIO_18_FC_2 VDDAN_11_CLK_7 0.1U_0402_16V4Z C602 VSSIO_SATA_19 VSS_19
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 2 1 VSS_20 L18
1 2 AC22 0.1U_0402_16V4Z 2 1 C603 A9 J7
R371 0_0402_5% VDDIO_18_FC_4 VSSIO_USB_1 VSS_21
B10 VSSIO_USB_2 VSS_22 P3
VDDRF_GBE_S V1 1 2 K11 VSSIO_USB_3 VSS_23 V4
R372 0_0402_5% B9 AD6
POWER VDDIO_33_GBE_S M10 1 2 D10
VSSIO_USB_4
VSSIO_USB_5
VSS_24
VSS_25 AD4
43mA R373 0_0402_5% D12 AB7
VSSIO_USB_6 VSS_26
+VDDPL_3V_PCIE AE28 VDDPL_33_PCIE D14 VSSIO_USB_7 VSS_27 AC9
GBE LAN
D17 VSSIO_USB_8 VSS_28 V8
L70 +1.1VS_PCIE
600mA E9 VSSIO_USB_9 VSS_29 W9
PCI EXPRESS
+1.1VS 2 1 U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 1 2 F9 VSSIO_USB_10 VSS_30 W10
FBMA-L11-201209-221LMA30T_0805 V22 L9 R374 0_0402_5% F12 AJ28
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_11 VSS_31
V26 VDDAN_11_PCIE_3 F14 VSSIO_USB_12 VSS_32 B29
C604 1 2 22U_0805_6.3V6M V27 F16 U4
C605 1U_0402_6.3V4Z VDDAN_11_PCIE_4 VSSIO_USB_13 VSS_33
1 2 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 1 2 C9 VSSIO_USB_14 VSS_34 Y18
C606 1 2 0.1U_0402_16V4Z V29 P8 R375 0_0402_5% G11 Y10
C607 0.1U_0402_16V4Z VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_15 VSS_35
GROUND
1 2 W22 VDDAN_11_PCIE_7 F18 VSSIO_USB_16 VSS_36 Y12
W26 VDDAN_11_PCIE_8 D9 VSSIO_USB_17 VSS_37 Y11
2 2
H12 VSSIO_USB_18 VSS_38 AA11
+VDDPL_3V_SATA H14 VSSIO_USB_19 VSS_39 AA12
+3VALW
93mA H16 VSSIO_USB_20 VSS_40 G4
L71 +1.1VS_SATA
AD14 VDDPL_33_SATA 32mA H18 VSSIO_USB_21 VSS_41 J4
VDDIO_33_S_1 A21 J11 VSSIO_USB_22 VSS_42 G8
+1.1VS 2 1 AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 J19 VSSIO_USB_23 VSS_43 G9
FBMA-L11-201209-221LMA30T_0805 567mA AF18 B21 2.2U_0603_6.3V4Z 1 2 C608 K12 M12
SERIAL ATA
VDDAN_11_SATA_4 VDDIO_33_S_3 2.2U_0603_6.3V4Z C609 VSSIO_USB_24 VSS_44
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10 1 2 K14 VSSIO_USB_25 VSS_45 AF25
3.3V_S5 I/O
C610 1 2 22U_0805_6.3V6M AG19 L10 K16 H7
C611 1U_0402_6.3V4Z VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_26 VSS_46
1 2 AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 K18 VSSIO_USB_27 VSS_47 AH29
C612 1 2 1U_0402_6.3V4Z AD18 T6 +1.1VALW H19 V10
C613 0.1U_0402_16V4Z VDDAN_11_SATA_6 VDDIO_33_S_7 VSSIO_USB_28 VSS_48
1 2 AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 VSS_49 P6
C614 1 2 0.1U_0402_16V4Z N4
VSS_50
Y4 EFUSE VSS_51 L4
check 220ohm bead 113mA C615 2 1 1U_0402_6.3V4Z L8
+AVDD_USB VSS_52
CORE S5
L72 658mA F26 C616 2 1 1U_0402_6.3V4Z D8

VDDCR_11_S_1 VSSAN_HWM
+3VALW 2 1 A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26
FBMA-L11-201209-221LMA30T_0805 A19 TBD M19 M20
VDDAN_33_USB_S_2 VSSXL VSSPL_SYS
A20 VDDAN_33_USB_S_3 VDDIO_AZ_S M8 +VDDIO_AZ
C617 1 2 10U_0805_10V4Z B18 +1.1VALW
C618 10U_0805_10V4Z VDDAN_33_USB_S_4 +VDDCR_USB
C619
1 2
1U_0402_6.3V4Z
B19 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 A11 197mA P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
1 2 B20 B11 2 1 P20 H26
USB I/O
C620 1U_0402_6.3V4Z VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 L73 FBMA-L11-160808-221LMT 0603 VSSIO_PCIECLK_2 VSSIO_PCIECLK_15

1 2 C18 VDDAN_33_USB_S_7 M22 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA21
C621 1 2 0.1U_0402_16V4Z C20 47mA C622 1 2 10U_0805_10V4Z M24 AA23
VDDAN_33_USB_S_8 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +VDDPL_3V M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
D19 62mA C623 2 1 0.1U_0402_16V4Z P22 AD23
VDDAN_33_USB_S_10 C624 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19
D20 VDDAN_33_USB_S_11 VDDPL_11_SYS_S L22 +VDDPL_11V 2 1 0.1U_0402_16V4Z P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26
E19 VDDAN_33_USB_S_12 17mA P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26
PLL
VDDPL_33_USB_S F19 +VDDPL_3V_USB T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20

L74 +1.1V_USB
200mA 5mA +3VALW
T22 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W21
+1.1VALW 2 1 C11 VDDAN_11_USB_S_1 VDDAN_33_HWM_S D6 +3V_HWM T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20
FBMA-L11-160808-221LMT 0603 +VDDLX_3V
3
D11 VDDAN_11_USB_S_2 197mA V20 VSSIO_PCIECLK_12 VSSIO_PCIECLK_25 AE26
3
VDDXL_33_S L20 2 1 J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21
C625 2 1 2.2U_0603_6.3V4Z L75 FBMA-L11-160808-221LMT 0603 K20
C626 2 VSSIO_PCIECLK_27
1 0.1U_0402_16V4Z C627 1 2 2.2U_0603_6.3V4Z
SB820M_FCBGA605 Part 5 of 5
SB820MR1@
SB820M_FCBGA605
+VDDPL_11V +1.1VALW +VDDPL_3V_USB +3VALW +3V_HWM +3VALW

+VDDPL_3V_PCIE +3VS +VDDPL_3V +3VS
L76 L77 L78
L79 L80 2 1 2 1 2 1
2 1 2 1 FBMA-L11-160808-221LMT 0603 0_0603_5% FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603
1 1 1 1 1
1 1 1 C630 C632
C628 C629 C631 C633
C634 C635 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
0.1U_0402_16V4Z 2 2 2 2 2
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
+VDDPL_3V_SATA +3VS +VDDIO_AZ +3VALW
L81
4 4
2 1 1 2
FBMA-L11-160808-221LMT 0603 R376 0_0402_5% +1.5VS
1 2
1 1 1 R52 0_0402_5%
C636 @
C637 C638
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
For 3V AZ device
SCHEMATICS,MB A6843
A B C D E
A B C D E
REQUIRED STRAPS Check Internal PU/PD
AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 GPIO200 GPIO199
PULL LOW POWER ALLOW PCIE WATCHDOG USE Inter CLK EC CLOCKGEN
HIGH MODE GEN2 TIMER DEBUG Gen Mode ENABLE ENABLE H,H = Reserved
ENABLE STRAP Enable
1 1
H,L = SPI ROM (Default )
DEFAULT DEFAULT
PULL Performance FORCE PCIE WATCHDOG IGNORE Inter CLK EC CLOCKGEN L,H = LPC ROM
LOW MODE GEN1 TIMER DEBUG Gen Mode DISABLE DISABLE L,L = FWH ROM
DISABLE STRAP Disable
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
+VDDIO_AZ +3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R385
R377
R378
R379
R380
R381
R382
R383
R384
2
2
@ @ @ @ @
<19> HDA_SDOUT @
<18> PCI_CLK1
<18> PCI_CLK2
<18> PCI_CLK3
<18> PCI_CLK4
<18,28> CLK_PCI_EC
<18,29> CLK_PCI_SIO
<19> GPIO200
2 <19> GPIO199 2
2.2K_0402_5%
2.2K_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
R393
R394
R386
R387
R388
R389
R390
R391
R392
2
2
@ @ @
+3VS +3VS
DEBUG STRAPS
10K_0402_5%
10K_0402_5%
1
1
R395
R396
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
2
USE PCI DISABLE ILA USE FC PLL USE DEFAULT DISABLE PCI <18> PCI_AD29
PULL PLL AUTORUN PCIE STRAPS MEM BOOT <18> PCI_AD28
HIGH <18> PCI_AD27
<18> PCI_AD26
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
<18> PCI_AD25
<18,20> PCI_AD24
<18> PCI_AD23
PULL BYPASS ENABLE ILA BYPASS USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN FC PLL PCIE STRAPS MEM BOOT
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R397
R398
R399
R400
R401
2
2
Check AD29,AD28 strap function @ @ @ @ @
check default
4 4

SCHEMATICS,MB A6843
A B C D E
5 4 3 2 1
SATA HDD Conn. SATA ODD Conn

JODD
Close to JODD
+5VS
Place closely JHDD SATA CONN. GND 1
SATA_STX_C_DRX_P1 C1143 1
1.2A A+ 2 2 0.01U_0402_25V7K SATA_STX_DRX_P1 <20>
3 SATA_STX_C_DRX_N1 C1138 1 2 0.01U_0402_25V7K
A- SATA_STX_DRX_N1 <20>
1 1 1 1 GND 4
C1247 C1248 C1249 C1250 5 SATA_SRX_DTX_N1 C1137 1 2 0.01U_0402_25V7K
B- SATA_SRX_C_DTX_N1 <20>
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 6 SATA_SRX_DTX_P1 C1136 1 2 0.01U_0402_25V7K
B+ SATA_SRX_C_DTX_P1 <20>
GND 7
2 2 2 2
DP 8
+5V 9 +5VS
SSD HDD need 400mA for 3V(PHISON) 10 +5VS Place components closely ODD CONN.
+3VS +5V
D
MD 11 1.1A D
+3VS rail reserve for SSD 15 GND GND 12
14 GND GND 13 1 1 1 1 1
1 1 1 1 C1144 C1145 C1146
C1251 C1159 C1152 C1253 @ C1147 C1148
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z SANTA_206401-1_RV 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ @ @ @ CONN@ 2 2 2 2 2
2 2 2 2
JHDD
Close to JHDD
GND 1
2 SATA_STX_C_DRX_P0 C1153 1 2 0.01U_0402_25V7K
A+ SATA_STX_DRX_P0 <20>
3 SATA_STX_C_DRX_N0 C1154 1 2 0.01U_0402_25V7K
A- SATA_STX_DRX_N0 <20>
GND 4
5 SATA_SRX_DTX_N0 C1155 1 2 0.01U_0402_25V7K
B- SATA_SRX_C_DTX_N0 <20>
6 SATA_SRX_DTX_P0 C1156 1 2 0.01U_0402_25V7K
B+ SATA_SRX_C_DTX_P0 <20>
GND 7
Reserve for EMI request
V33 8
9
+3VS
USB Port 0 & Port1 @ R828 0_0402_5%
1 2
V33 L82
V33 10
11 <19> USB20_P0 4 3 USB20_P0_R
GND 4 3
10
GND 12
9
6
GND 13
D91
W=60mils USB20_N0_R
14 1 2
V5
V5 15
+5VS
RCLAMP0524P.TCT~D +5VALW 1.4A +USB_VCCA
<19> USB20_N0 1 2
16 @ U48 @ For EMI request WCM-2012-900T_0805
V5
GND 17 1 GND VOUT 8 2 1 1 2
18 2 7 C1157 1000P_0402_50V7K @ R829 0_0402_5%
C Reserved VIN VOUT C
GND 19 3 VIN VOUT 6
20 USB_EN# 4 5 USB_OC#0 <19,28> @ R830 0_0402_5%
V12 <28> USB_EN# EN FLG
24 21 1 1 2
8
GND V12 RT9715BGS_SO8 L83

23 22
1
GND V12 C1158 USB20_N1_R

2/23 Reserve D91 for ESD <19> USB20_N1 1 1 2 2
4.7U_0805_10V4Z
SANTA_191201-1 2 @
CONN@ <19> USB20_P1 4 3 USB20_P1_R
4 3
WCM-2012-900T_0805
1 2
@ R831 0_0402_5%
Slot#1 Half PCIe Mini Card-WLAN WLAN&BT Combo module circuits

7/9 Mount L82,L83 ,Reserve R828,R830 for EMI request
BT BT
+3VS 2 2 1 1 +3V_WLAN on module on module
@ PJ27 JUMP_43X79
Enable Disable
Short PJ27 for WLAN BT_CRTL H L
BT_PWR# L H
CLKREQ_MCARD2# 1 2 +3V_WLAN
@ R259 8.2K_0402_5%
+USB_VCCA
**If +3V_WLAN is +3VS, please +USB_VCCA
remove DM2 W=40mils
+1.5VS +3V_WLAN
For SED For SED W=40mils
@ DM2
B 0.1U_0402_16V4Z 47P_0402_50V8J 0.1U_0402_16V4Z 47P_0402_50V8J SUSP# 1 2 BT_CTRL B
<28,31,37> SUSP#
1 1 1 1 1 1
1
CH751H-40PT_SOD323-2 1 1 1
1
CM21 CM18 CM17 CM24 CM20 CM22 CM23 CM19 D

1 1
2 QM1 + C339 C342 C343
<18> BT_PWR#
2
2 2 2 @ 2 2 2 @ G BT@ C340 C341

220U_6.3V_M 0.1U_0402_16V4Z 1000P_0402_50V7K
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z S 2N7002_SOT23-3 2 2
0.1U_0402_16V4Z 1000P_0402_50V7K
3
2 2 2
JUSB1 @ JUSB2 @
+1.5VS +3V_WLAN 7/25 Reserver DM2 for +3V_WLAN is +3VS USB20_N0_R

1 VCC GND 5
USB20_N1_R
1 VCC GND 5
2 D- GND 6 2 D- GND 6
JWLAN 1 A 1 A USB20_P0_R 3 7 USB20_P1_R 3 7
D+ GND D+ GND
1 1 2 2 4 GND GND 8 4 GND GND 8
3 3 4 4
2
BT_CTRL 5 6 BT_CTRL R50 1 2 1K_0402_5% E51_RXD_R ALLTOP C107L8-10405-L ALLTOP C107L8-10405-L
5 6
2
7 8 D10
<19> CLKREQ_MCARD2# 7 8
9 10 D9 @
9 10 @ PJDLC05_SOT23-3
<18> CLK_PCIE_MCARD2# 11 11 12 12 7/25 Add R50 for Intel Rainbow Peak module PJDLC05_SOT23-3
<18> CLK_PCIE_MCARD2 13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20 WL_OFF# <28>
21 22 PLT_RST#
PLT_RST# <12,15,18,24,28,29>
1
21 22
<11> PCIE_PTX_C_IRX_N2 23 24
1
23 24
<11> PCIE_PTX_C_IRX_P2 25 25 26 26
27 27 28 28
29 29 30 30 SMB_CK_CLK1 <19>
<11> PCIE_ITX_C_PRX_N2 31 31 32 32 SMB_CK_DAT1 <19>
<11> PCIE_ITX_C_PRX_P2 33 33 34 34
A
35 35 36 36 USB20_N8 <19> A
WLAN/ WiFi 37 37 38 38 USB20_P8 <19>
+3V_WLAN 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
RM16 1 20_0402_5% 49 50
<28> E51_TXD 49 50
1 2 E51_RXD_R 51 52
<28> E51_RXD
RM15 0_0402_5% 51 52 Security Classification Compal Secret Data Compal Electronics, Inc.
53 GND1 GND2 54 Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title
Debug card using
SCHEMATICS,MB A6843
FOX_AS0B226-S40N-7F Size Document Number Rev
CONN@ B
401982
5 4 3 2 1
A B C D E
UL1
<11> PCIE_PTX_C_IRX_P3 CL1 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 22 31 LL1,CL13 will be changed to

HSOP LED3/EEDO +LAN_VDD10
LED1/EESK 37 2.2uH&4.7uF after EVT test
<11> PCIE_PTX_C_IRX_N3 CL2 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 23 HSON LED0 40
LL1 8105E_VB@
PCIE_ITX_C_PRX_P3 17 30 RL2 2 1 10K_0402_5% +LAN_REGOUT 1 2
<11> PCIE_ITX_C_PRX_P3 HSIP EECS/SCL +3V_LAN
PCIE_ITX_C_PRX_N3 18 32 RL1 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2J-N Close to Pin 27,39,12,47,48
<11> PCIE_ITX_C_PRX_N3 HSIN EEDI/SDA
1 2
Layout Note: LL1 must be CL13 CL9
RL19 0_0402_5% CLKREQ_LAN#_R 16 1 LAN_MDI0+ within 200mil to Pin36, 8105E_VB@ 8105E_VB@ 1 2
<19> CLKREQ_LAN# CLKREQB MDIP0
2 LAN_MDI0- CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL10
PLT_RST# MDIN0 LAN_MDI1+ 200mil to LL1 2 1
<12,15,18,23,28,29> PLT_RST# 25 PERSTB MDIP1 4 1 2
1 YL1 5 LAN_MDI1- +LAN_REGOUT: Width =60mil 0.1U_0402_16V4Z CL4 1
LAN_X1 LAN_X2 CLK_PCIE_LAN MDIN1
1 2 <18> CLK_PCIE_LAN 19 REFCLK_P NC/MDIP2 7 1 2
CLK_PCIE_LAN# 20 8 0.1U_0402_16V4Z CL5
<18> CLK_PCIE_LAN# REFCLK_N NC/MDIN2
25MHZ_20PF_7A25000012 10 1 2
NC/MDIP3 0.1U_0402_16V4Z CL6
1 1 NC/MDIN3 11
LAN_X1 43
CL26 CL27 CKXTAL1
27P_0402_50V8J 27P_0402_50V8J LAN_X2 44 13 +LAN_VDD10
2 2 CKXTAL2 DVDD10 +LAN_VDD10 +LAN_EVDD10
DVDD10 29
DVDD10 41
EC_SWI# 28 2 1
<19> EC_SWI# LANWAKEB 0_0603_5% LL2 1 2
ISOLATEB 26 27 +3V_LAN
ISOLATEB DVDD33 CL18 CL17
DVDD33 39
1U_0402_6.3V4Z 0.1U_0402_16V4Z Close to Pin 3,6,9,13,29,41,45
2 1
14 NC/SMBCLK AVDD33 12 +3V_LAN
15 42 +LAN_VDD10
+3VS RL22 1 NC/SMBDATA AVDD33
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21
AVDD33 48 1 2
0.1U_0402_16V4Z CL19
1
ENSWREG 33 1 2
RL6 ENSWREG 0.1U_0402_16V4Z CL20
EVDD10 21 +LAN_EVDD10
1K_0402_1% +LAN_VDDREG 34 1 2
@ VDDREG 0.1U_0402_16V4Z CL21
35 VDDREG AVDD10 3 +LAN_VDD10
6 1 2
2
ISOLATEB AVDD10 +3V_LAN +LAN_VDDREG 0.1U_0402_16V4Z CL22

RTL8105E RTL8111E AVDD10 9
1 2 46 45 8105E_VB@
RL5 2.49K_0402_1% RSET AVDD10 UL1
Pin14 NC NC 2 1
24 36 +LAN_REGOUT 0_0603_5% LL3 1 2
2 RL7 GND REGOUT CL28 CL29 2
Pin15 NC 10K ohm PD 49 PGND
15K_0402_5% 8105E_VB@ 8105E_VB@
Pin38 1K ohm Pull-high 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
RTL8105E-VB QFN _6X6 2 1
8105E_VB@ 8105E_VC@
+3VALW TO +3V_LAN 7/16 Change UL1 from RTL8105E-VB (SA00003PO10)

+3VALW to RTL8105E-VC (SA00003PO20)
+3V_LAN LAN Conn.
+3VALW
2
Vgs=-4.5V,Id=3A,Rds<97mohm RL4
RL25 7/16 For LDO mode : 8105E_VB@ change connector to w/o LED
100K_0402_5% 2 0_0402_5%
@ CL12 1. Remove RL4, mount RL23. (use NPVAA LAN conn. before LAN symol ready)
1
0.1U_0402_16V7K QL1 ENSWREG

2. Remove LL1, CL13, CL9, LL3, CL28, CL29.
1
S
@ PJ28
1
1 G
<28> WOL_EN# 1 2 2 JUMP_43X39
RL16 47K_0402_5% @ RL23 JLAN CONN@
+3V_LAN
2
@ 1 @ D 8105E_VC@
1
CL14 AO3413_SOT23 0_0402_5% 8

2
0.01U_0402_25V7K +3V_LAN PR4-

@ CLKREQ_LAN#_R @RL10
@ RL10 2 1 10K_0402_5% 7
2 PR4+
RJ45_MIDI1- 6 PR2-
CL7
CL3
4.7U_0805_10V4Z
1U_0402_6.3V4Z
3
1 1 3
EC_SWI# @RL3
@ RL3 2 1 10K_0402_5% 5
CL15 CL8 PR3-
10U_0805_10V4Z
10U_0805_10V4Z
4 PR3+
@ 2 2 @ WOL_EN# ISOLATEB
@ RL11 0_0402_5% RJ45_MIDI1+ 3 PR2+
8/7 Chagne UL4 from NS681680 to NS681695 RJ45_MIDI0-
<28> WOL_EN 2 PR1-
RL12 0_0402_5%
RJ45_MIDI0+ 1 PR1+
SHLD1 9
UL4 10
SHLD2
LAN_MDI1- 1 16 RJ45_MIDI1-
LAN_MDI1+ TD+ TX+ RJ45_MIDI1+ CL42 1000P_0402_50V7K SANTA_130452-C
2 TD- TX- 15
3 CT CT 14 2 1 1 2
4 13 RL15 75_0402_1%
NC NC CL41 1000P_0402_50V7K
5 NC NC 12
6 11 2 1 1 2 RJ45_GND RJ45_GND 1 2 1000P_1808_3KV7K LANGND
LAN_MDI0- CT CT RJ45_MIDI0- RL13 75_0402_1% CL36
7 RD+ RX+ 10 1 1
LAN_MDI0+ 8 9 RJ45_MIDI0+ CL37 CL38
RD- RX-
2
120P_0402_ 50VJ 4.7U_0603_6.3V6K
NS681610 2 2
Place these components 1
colsed to LAN chip CL34
7/23 Chagne UL4 from LF-H1201P-2 to NS681680 D13 @
0.1U_0402_25V6 8/7 Chagne UL4 from NS681680 to NS681695
2 PJDLC05_SOT23-3
4 4
1
SCHEMATICS,MB A6843
A B C D E
A B C D
1 1
@ CC2
1 2 100P_0402_50V8J
RC1
6.19K_0402_1% UC1
2 1 1 REFE
GPIO0 17
USB20_N5 2
+3VS_CR <19> USB20_N5 DM
USB20_P5 3 24 CLK_48M_CR_R 1 2 < 48MHz >
<19> USB20_P5 DP CLK_IN CLK_48M_CR <18>
RC5 0_0402_5%
+3VS 1 2 4 3V3_IN XD_D7 23
RC4 0_0603_5% +VCC_3IN1 5
+V1_8 CARD_3V3
1 1 6 V18 SP14 22
CC1 CC3 1 21 SD_DATA2_MS_DATA5
CC4 SP13 MS_DATA1_SD_DATA3
7 XD_CD# SP12 20
0.1U_0402_16V4Z
4.7U_0805_10V4Z 1U_0402_6.3V4Z 19
2 2 SDWP_MSCLK SP11 SDCMD
8 SP1 SP10 18
2
9 SP2 SP9 16
SD_DATA1 10 15 MS_DATA2_SDCLK 1 2 MS_DATA2_SDCLK_R
SP3 SP8
EPAD
SD_DATA0 11 14 RC6 0_0402_5%
SP4 SP7 SDCD#
12 SP5 SP6 13
RTS5137-GR QFN 24P_4X4
25
2 2
8/6 Change Net name from v1_8 to +V1_8
7/16 Change UC1 from RTS5138 (SA000030600) to RTS5137 (SA000043500)
for EMI request
@CC7
@ CC7 2 1 @RC2
@ RC21 2 MS_DATA2_SDCLK
10P_0402_50V8J 10_0402_5%
@CC8
@ CC8 2 1 @RC3
@ RC31 2 SDWP_MSCLK
10P_0402_50V8J 10_0402_5%
@CC9
@ CC9 2 1 @RC7
@ RC71 2 CLK_48M_CR_R
10P_0402_50V8J 10_0402_5%
3 3
< 2 in 1 Card Reader >
JREAD
1 MS_DATA1_SD_DATA3
D3 SDCMD
CMD 2
VSS1 3
VDD 4 +VCC_3IN1
5 MS_DATA2_SDCLK_R
CLK
VSS2 6 1 1
CC5 CC6
7 SD_DATA0
D0 SD_DATA1 0.1U_0402_16V4Z 1U_0402_6.3V4Z
D1 8
SD_DATA2_MS_DATA5 2 2
D2 9
10 SDWP_MSCLK
WP SDCD#
CD 11
GND1 12
GND2 13
GND3 14
GND4 15
TAITW_PSDAT3-09GLAS1N14N
CONN@
4 4

SCHEMATICS,MB A6843
Size
Document Number Rev
B
401982
A B C D
5 4 3 2 1
Codec 600 mA RA2

+PVDD1 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z +5VS
1 1 0_0603_5% 1 1
CA57 CA44
CA56 CA43
2
JA1 2 2 2 2
2
+3VS 1 2 0.1U_0402_16V4Z +DVDD_IO JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
RA19 0_0603_5%
Beep sound
1
1 1 @ place close to chip
D CA2 CA1 D
1
+1.5VS 1 @ 2
RA20 0_0603_5% 10U_0805_10V4Z +3VS_DVDD RA11
2 2 +PVDD2 1 2 0.1U_0402_16V4Z +5VS
EC Beep RA7
place close to chip 1 1 0_0603_5% 1 1 1 2
<28> EC_BEEP#
CA61 @ CA62 47K_0402_5%
RA1 0.1U_0402_16V4Z 35 mA @ CA63 @ @ CA58
+3VS 2 1 0.1U_0402_16V4Z
0_0603_5% 2 2 2 2
1 1
+AVDD 10U_0805_10V4Z 10U_0805_10V4Z PCI Beep RA8
CA13
CA8 CA7 RA3 1 2 1 2 MONO_IN
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 1 <19> PCH_SPKR
68 mA 2 +5VS 47K_0402_5%
2 2 0_0603_5% 0.1U_0402_16V4Z
39
46
25
38
1 1 1 1
9
UA1 CA3 CA4 CA5 CA6
DVDD_IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
1
2 2 2 2 place close to chip 1
10U_0805_10V4Z 0.1U_0402_16V4Z RA12 CA18
10K_0402_5% 0.1U_0402_16V4Z
2
23 40 SPKL+ <27>
2
LINE1_L SPK_OUT_L+
24 LINE1_R SPK_OUT_L- 41 SPKL- <27>
14 LINE2_L SPK_OUT_R+ 45 SPKR+ <27>
4.7U_0805_10V4Z CA21 15 44
LINE2_R SPK_OUT_R- SPKR- <27>
<27> MIC1_R_L 2 1
Ext. Mic 21 32 RA4 75_0402_1%
MIC1_L HP_OUT_L HP_L <27>
2 1 22 33 RA5 75_0402_1%
<27> MIC1_R_R MIC1_R HP_OUT_R HP_R <27>
C 4.7U_0805_10V4Z CA22 C
16 MIC2_L
17 MIC2_R
SYNC 10 AZ_SYNC_HD <19>
INT_MIC_DATA 2 6
<17> INT_MIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD <19>
INT_MIC_CLK RA48 CAM@ 3
<17> INT_MIC_CLK GPIO1/DMIC_CLK
1 FBMA-10-100505-301T 5 AZ_SDOUT_HD <19>
CA28 SDATA_OUT
27P_0402_50V8J EC_MUTE# 4 8 AZ_SDIN0_HD_R 2 1
<28> EC_MUTE# PD# SDATA_IN AZ_SDIN0_HD <19>
@ RA6 33_0402_5%
2
<19> AZ_RST_HD# 11 RESET# EAPD 47
EC_MUTE# place close to chip
SPDIFO 48
1 2 MONO_IN 12 PCBEEP
1
CA12 100P_0402_50V8J 20
RA22 MONO_OUT
SENSE_A 13
4.7K_0402_5% SENSE A +MIC1_VREFO_R +MIC1_VREFO_L +MIC2_VREFO
MIC2_VREFO 29 +MIC2_VREFO
18
2
SENSE B
MIC1_VREFO_R 30 +MIC1_VREFO_R CA23 10U_0805_10V4Z
1 2 36 CBP LDO_CAP 28 1 2
CA15 1 1 1
EC control EC_MUTE# behavior: 2.2U_0603_6.3V4Z 35 27 AC_VREF @ @ @
CBN VREF CA52 CA51 CA46
High-state / low-state 31 19 AC_JDREF2 RA9 1 20K_0402_1% 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+MIC1_VREFO_L MIC1_VREFO_L JDREF 2 2 2
B
1 1 B
43 PVSS2 CPVEE 34 1 2
42 CA14 2.2U_0603_6.3V4Z CA17 CA16
CA47 1 PVSS1
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 10U_0805_10V4Z
2 2 @
7 DVSS1 AVSS2 37
CA48 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z
ALC259-GR_QFN48_7X7
CA49 1 2 0.1U_0603_50V7K place close to chip
CA50 1 2 0.1U_0603_50V7K
DGND AGND
1 2
RA27 0_0603_5%
Sense Pin Impedance Codec Signals Function

place close to chip
39.2K PORT-I (PIN 32, 33) Headphone out SENSE_A
<27> MIC_SENSE 2 1
RA10 20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A <27> NBA_PLUG
RA21 39.2K_0402_1%
10K PORT-C (PIN 23, 24)
5.1K (PIN 48)

A A
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17)

10K PORT-H (PIN 20) Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title
SCHEMATICS,MB A6843
B
401982
5 4 3 2 1
5 4 3 2 1
Speaker Connector
D D
placement near Audio Codec

RA30
SPKL+ 2 1 SPK_L1
<26> SPKL+
0_0603_5% 1
CA31 @DA5
@ DA5 AZ5125-02S.R7G
@ 10U_0805_10V4Z 2
2 2
CA32
1U_0402_6.3V4Z
1 Ext.MIC/LINE IN JACK
1 3
@
CA33 1 JSPK
RA34 @ 10U_0805_10V4Z SPK_L1 1
SPKL- 2 SPK_L2 SPK_L2 1
<26> SPKL- 2 1 2 2
0_0603_5% SPK_R1 3
SPK_R2 3
4 4 RA33 2 1 RA31 +MIC1_VREFO_R
@DA10
@ DA10 AZ5125-02S.R7G ACES_85204-0400N 1K_0402_5% 2.2K_0402_5%
RA23 3 CONN@ 2 1 MIC1_R
<26> MIC1_R_R
SPKR+ 2 1 SPK_R1 1
<26> SPKR+
0_0603_5% 1 2
2 1 MIC1_L
<26> MIC1_R_L
CA34 1K_0402_5%
@ 10U_0805_10V4Z 2 RA32 2 1 RA29 +MIC1_VREFO_L
2 CA35 2.2K_0402_5%
C 1U_0402_6.3V4Z C
1
@
CA36 1
RA24 @ 10U_0805_10V4Z
SPKR- 2 SPK_R2
<26> SPKR- 2 1
0_0603_5%
HeadPhone/LINE Out JACK JLINE

5 5
<26> NBA_PLUG 4 4 GND 10

GND 9
B
<26> HP_R
LA101 2 HP_R_L 3 3 8 8 B
KC FBM-L11-160808-121LMT 0603 6 7
6 7
<26> HP_L
LA121 2 HP_L_L 2 2
KC FBM-L11-160808-121LMT 0603 1 1
FOX_JA63331-B39S4-7F
1 CONN@
3
1 CA53 CA54 CA11 @
2 100P_0402_50V8J 100P_0402_50V8J
2
DA8 @ 0.1U_0402_16V4Z 7/23 Change JLINE/JEXMIC to FOX_JA6331-B39S4-7F for DFX
PJDLC05_SOT23-3
For EMI
Ext.MIC/LINE IN JACK JEXMIC

5 5
<26> MIC_SENSE 4 4 GND 10

GND 9
MIC1_R LA8 1 2 MIC1_L_R 3 8
3 8
KC FBM-L11-160808-121LMT 0603 6 7
6 7
MIC1_L LA131 2 MIC1_L_L 2 2
KC FBM-L11-160808-121LMT 0603 1 1
FOX_JA63331-B39S4-7F
CONN@
A 1 A
3
1 CA55 CA59 CA30 @
2 100P_0402_50V8J 100P_0402_50V8J
2
DA9 @ 0.1U_0402_16V4Z
PJDLC05_SOT23-3
For EMI
SCHEMATICS,MB A6843
5 4 3 2 1
5 4 3 2 1
+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 2 2 C1188
C1190 1 2
C1191 C1192 C1193 C1194 C1195
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z
2 2 2 2 1 1
111
125
for EMI request 0.1U_0402_16V4Z 1000P_0402_50V7K
22
33
96
67
9
U52
BATT_TEMPA 1 2
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
CLK_PCI_EC C1187 100P_0402_50V8J
D
ACIN_D 1 2 D
1
C1189 100P_0402_50V8J
R855 GATEA20 1 21
<19> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F
@ 10_0402_5% 2 23 EC_BEEP#
<19> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# <26>
SERIRQ 3 26
<18,29> SERIRQ SERIRQ# FANPWM1/GPIO12
LPC_FRAME# 4 27 ACOFF
<18,29> LPC_FRAME# ACOFF <32,34>
2
LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13

1 <18,29> LPC_AD3 5 LAD3
LPC_AD2 7 PWM Output
<18,29> LPC_AD2 LAD2
C1196 LPC_AD1 8 63 BATT_TEMPA
<18,29> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA <33>
@ 10P_0402_50V8J LPC_AD0 R208
2 <18,29> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65 1 2 100K_0402_5% ADP_I <34>
CLK_PCI_EC 12 AD Input 66 ADP_V
<18,22> CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V <34>
PLT_RST# 13 75 C387
<12,15,18,23,24,29> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
ECRST# 37 76 1 2 0.22U_0603_16V4Z
+3VL R859 EC_SCI# ECRST# SELIO2#/AD5/GPIO43
<19> EC_SCI# 20 SCI#/GPIO0E
47K_0402_5% 38
ECRST# CLKRUN#/GPIO1D
2 1 DAC_BRIG/DA0/GPIO3C 68
70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <5>
2 1 DA Output 71 IREF
IREF/DA2/GPIO3E IREF <34>
C1197 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <34>
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI[0..7] KSI3 58 83 EC_MUTE#
<29> KSI[0..7] KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <26>
KSI4 59 84 USB_EN#
KSO[0..17] KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <23>
KSI5 60 85
<29> KSO[0..17] KSI5/GPIO35 PSCLK2/GPIO4C
KSI6 61 PS2 Interface 86
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK +5VS
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK <30>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <30>
KSO1 40
KSO2 KSO1/GPIO21 TP_CLK
41 KSO2/GPIO22 1 2
KSO3 42 97 VGATE R861 4.7K_0402_5%
KSO3/GPIO23 SDICS#/GPXOA00 VGATE <31,38>
KSO4 43 98 WOL_EN# TP_DATA 1 2
C KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# <24> C
KSO5 VLDT_EN R863 4.7K_0402_5%
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
VLDT_EN <31>
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# <29>
KSO7 46 SPI Device Interface
+3VL KSO8 KSO7/GPIO27 +3VALW
47 KSO8/GPIO28
KSO9 48 119 EC_SI_SPI_SO
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <29>
1 2 KSO1 KSO10 49 120 EC_SO_SPI_SI LID_SW# 2 1
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <29>
R862 47K_0402_5% KSO11 50 SPI Flash ROM 126 SPI_CLK 47K_0402_5% R865
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK <29>
1 2 KSO2 KSO12 51 128 SPI_CS#
KSO12/GPIO2C SPICS# SPI_CS# <29>
R864 47K_0402_5% KSO13 52 SYSON 1 2
KSO14 KSO13/GPIO2D R866 4.7K_0402_5%
53 KSO14/GPIO2E
to avoid EC entry ENE test mode KSO15 54 73
KSO16 KSO15/GPIO2F CIR_RX/GPIO40
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
KSO17 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <34>
90 BATT_FULL_LED# R867 330K_0402_5%
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <30>
91 CAPS_LED# +3VL 1 2
CAPS_LED#/GPIO53 CAPS_LED# <29>
RP1 EC_SMB_CK1 77 GPIO 92 BATT_CHG_LOW_LED#
<33> EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# <30>
+3VL 1 8 EC_SMB_CK1 EC_SMB_DA1 78 93 D26
<33> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
2 7 EC_SMB_DA1 EC_SMB_CK2 79 SM Bus 95 SYSON ACIN_D 2 1
<7> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <31,36> ACIN <20,34>
+3VS 3 6 EC_SMB_CK2 EC_SMB_DA2 80 121 VR_ON
<7> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <31,38>
4 5 EC_SMB_DA2 127 ACIN_D CH751H-40PT_SOD323-2
AC_IN/GPIO59
2.2K_0804_8P4R_5%
PM_SLP_S3# 6 100 EC_RSMRST#
<19> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <19>
PM_SLP_S5# 14 101 EC_LID_OUT# 7/27 Change R867 pull up from +3VALW to +3VL
<19> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <19>
EC_SMI# 15 102 EC_ON
<19> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <30,31,35>
<34> 75W_65W 16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103
17 104 SB_PWRGD
<24> WOL_EN SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWRGD <19>
18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <17>
7/7 Change WOL_EN from pin 103 to pin 17 19 GPIO 106 WL_OFF# SUSP# R869 2 1 10K_0402_5%
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <23>
EC_INVT_PWM 25 107 EC_ID
<17> EC_INVT_PWM EC_THERM#/GPIO11 GPXO10
FAN_SPEED1 28 108 VR_ON R462 2 1 10K_0402_5%
<5> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
B 29 FANFB2/GPIO15
7/7 Change ED_ID from pin 108 to pin 107 B
E51_TXD 30
<23> E51_TXD EC_TX/GPIO16
7/6 For Power LED PWM function E51_RXD 31 110
<23> E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1
ON/OFFBTN# 32 112
<30> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 UMA_ENBKL <12>
R872 PWR_LED# 34 114
<30> PWR_LED# PWR_LED#/GPIO19 GPXID3
CRY1 1 2CRY2 NUM_LED# 36 GPI 115
<29> NUM_LED# NUMLED#/GPIO1A GPXID4
116 SUSP#
GPXID5 SUSP# <23,31,37>
10M_0402_5% 117 PBTN_OUT#
GPXID6 PBTN_OUT# <19>
@ 118 USB_OC#0
GPXID7 USB_OC#0 <19,23>
CRY1 @ R991
@R991 0_0402_5% 122
CRY2 @R992
@ R992 0_0402_5% XCLK1 +EC_V18R
123 XCLK0 V18R 124
1 1 R990 0_0402_5%
<18> RTCCLK
AGND
GND
GND
GND
GND
GND
1
C1199 C1200 C448

1
18P_0402_50V8J
@ Y5 @ 4.7U_0805_10V4Z
18P_0402_50V8J
1
OSC
OSC
2 @ 2 R246 @ KB926QFE0_LQFP128_14X14
11
24
35
94
113
69
100K_0402_5% C1206 +3VALW

18P_0402_50V8J
2
NC
NC
2
2
7/2 For EC Crystal cost down R435

100K_0402_5%
EC_ID @
32.768KHZ_12.5PF_Q13MC14610002
H L
1
EC_ID
7/20 PVT reserve C1199,Y5, C1200
2
EC ver. KB926D3 KB926E0
R436
100K_0402_5%
@
A R874 2 1 100K_0402_5% E51_TXD A
1
R783 1 2 100K_0402_5% PLT_RST#
2 1
@C1238
@ C1238 0.1U_0402_16V4Z
For ESD request Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title
SCHEMATICS,MB A6843
Size
Document Number Rev
B
401982
5 4 3 2 1
SPI Flash (256KB) Lid SW LPC Debug Port Please place the PAD under DDR DIMM.
H7
+3VS
+3VALW
7/7 Change U13 from MXIC to WINBOND for EOL
6 5
U54
+3VL APX9132ATI-TRL_SOT23-3
20mils U13 7 4
<18,28> SERIRQ PLT_RST# <12,15,18,23,24,28>
8 4 2 3
GND
VCC VSS VDD VOUT LID_SW# <28>
1
C1201 3 8 3
W <18,28> LPC_AD3 LPC_AD2 <18,28>
1 1
1
0.1U_0402_16V4Z 7
2 HOLD C1202 C1203
<18,28> LPC_AD1 9 2 LPC_AD0 <18,28>
SPI_CS# 1 0.1U_0402_16V4Z 10P_0402_50V8J
<28> SPI_CS# S 2 2
SPI_CLK 6 10 1
<28> SPI_CLK C <18,28> LPC_FRAME# CLK_PCI_SIO <18,22>
<28> EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO <28>
2
W25X20BVSNIG SOIC 8P @ DEBUG_PAD R876
22_0402_5%
@
8/6 Change U13 footprint to M25P10-AVMN6T_SO8
1
2
C1204
SPI_CLK 1 R877 @2 1 2 22P_0402_50V8J
10_0402_5% C1205 @ 10P_0402_50V8J 1 @
reserve for EMI, close to U13

reserve for EMI
KEYBOARD CONN.
KSI[0..7] please close to JKB1
KSI[0..7] <28>
KSO[0..17] KSO16 1 2
KSO[0..17] <28>
C1207 100P_0402_50V8J
KSO17 1 2
C1208 100P_0402_50V8J
KSO2 1 2
C1209 100P_0402_50V8J
KSO1 1 2
C1210 100P_0402_50V8J
KSO0 1 2
JKB C1211 100P_0402_50V8J
JKB34 1 2 +3VS KSO4 1 2
34 KSO16 R881 300_0402_5% C1212 100P_0402_50V8J
33 KSO3
32 1 2
KSO17 C1213 100P_0402_50V8J
31 KSO5
30 1 2
C1214 100P_0402_50V8J
29 KSO2 KSO14
28 1 2
KSO1 C1215 100P_0402_50V8J
27 KSO0 KSO6
26 1 2
KSO4 C1216 100P_0402_50V8J
25 KSO3 KSO7
24 1 2
KSO5 C1217 100P_0402_50V8J
23 KSO14 KSO13
22 1 2
KSO6 C1218 100P_0402_50V8J
21 KSO7 KSO8
20 1 2
KSO13 C1219 100P_0402_50V8J
19 KSO8 KSO9
18 1 2
KSO9 C1220 100P_0402_50V8J
17 KSO10 KSO10
16 1 2
KSO11 C1221 100P_0402_50V8J
15 KSO12 KSO11
14 1 2
KSO15 C1222 100P_0402_50V8J
13 KSI7 KSO12
12 1 2
KSI2 C1223 100P_0402_50V8J
11 KSI3 KSO15
10 1 2
KSI4 C1224 100P_0402_50V8J
9 KSI0 KSI7
8 1 2
KSI5 C1225 100P_0402_50V8J
7 KSI6 KSI2
6 1 2
KSI1 C1226 100P_0402_50V8J
5 JKB4 KSI3
4 2 1 +3VS 1 2
CAPS_LED# R882 300_0402_5% C1227 100P_0402_50V8J
3 CAPS_LED# <28>
KSI4 1 2
2 NUM_LED# C1228 100P_0402_50V8J
1 NUM_LED# <28>
KSI0 1 2
ACES_88170-3400 C1229 100P_0402_50V8J
CONN@ KSI5 1 2
C1230 100P_0402_50V8J
KSI6 1 2
C1231 100P_0402_50V8J
KSI1 1 2
C1232 100P_0402_50V8J
CAPS_LED# 1 2
C1233 100P_0402_50V8J
NUM_LED# 1 2
C1234 100P_0402_50V8J

SCHEMATICS,MB A6843
B
401982
5 4 3 2 1
+3VL < Touch / B Connector >

Power Button
2
debug phase using R883
51_ON# <32>
100K_0402_5%
SW6 DEBUG@
6
1 3 ON/OFFBTN#
BTM side Q163A < Power / B Connector > Right Switch
2 4 1 2N7002DW-T/R7_SOT363-6
C1235 2 SW4
SMT1-05-A_4P 0.1U_0402_25V6 <28,31,35> EC_ON JPOWER TP_SWR 1 3
6
5
2
@ ON/OFFBTN# 1 1
<28> ON/OFFBTN#
1
D 2 R884 JTOUCH D
2 2 2 4
10K_0402_5% 3 3 +5VS 1 1
3
4 4 SMT1-05-A_4P 2
<28> TP_CLK
6
5
2
5 G1 <28> TP_DATA 3
1
TP_SWL 3
For EMI request 6 G2 4 4
D12 TP_SWR 5 7
5 G7
3
@ ACES_85201-0405N
AZ5125-02S.R7G CONN@ Left Switch 6 6 G8 8
1
P-TWO_161021-06021_6P-T
SW1 AZ5125-02S.R7G CONN@
TP_SWL 1 3 D11
1
2 4
SMT1-05-A_4P
6
5
7/13 For ESD request
Screw Hole
POWER/SUSPEND LED DC IN/ BATT CHARGE H5 H6 H8 H9 H10 H11 H12 H13 H14
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
@ @ @ @ @ @ @ @ @
Vf=1.8V(typ),2.0V(max) for amber
1
Vf=1.8V(typ),2.0V(max) for green
Vf=1.9V(typ),2.4V(max) If=20mA(max)
If=20mA(max)
D70
C C
H1 H2 H3 H15 H16
D67 2 R774 1 2 510_0402_5% H_2P7x3P2N H_2P7N H_1P0N H_5P0N H_5P0N
A BATT_CHG_LOW_LED# <28>
+5VALW 1 @ @ @ @ @
+5VALW R768 1 2 510_0402_5% 2 1 PWR_LED# <28>
1
YG 3 R773 1 2 510_0402_5% BATT_FULL_LED# <28>
YG
HT-110UYG5_YELLOW GREEN
3
HT-210UD5-UYG5_AMBER-YEL GRN
CPU MINI CARD -- WLAN

7/23 Change R773 from 120 to 510 ohm H20 H21 H22 H23 H18 H19
H_4P2 H_4P2x4P7 H_4P2x4P7 H_4P9 H_3P3 H_3P3
7/23 Change Net name from+3VALW to +5VALW @ @ @ @ @ @
7/6 For Power LED PWM function
8/6 Add R774 link to BATT_CHG_LOW_LED#
1
7/15 Change D67/D70 to 5mA type
8/6 Change R773 link to BATT_FULL_LED#
7/23 Change R773 from 120 to 510 ohm
7/23 Change Net name from+3VALW to +5VALW
PCB Fedical Mark PAD

FD1 FD2 FD3 FD4
@ @ @ @
1
B B
ESD reserved
+3VS B+ +3VS
+5VS
+1.1VS
ISPD 7/13 Change P/N to DC30100A400
PJP1
ZZZ
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 1 1 PCB DC-IN PJP1
C1257
C1259
C1260
C1261
C1263
C1262
C1258
PCB SKU LA-6843P Rev10 45@
2 2 2 2 2 2 2
@ @ @ @ @ @ @
U3 U8
A NB R3 SB R3 A
Near H5 Near H11 Near H12 Near H8 Near H14 Near H13 Near R972 RS880M SB820M_FCBGA605_A13
R3@ R3@
7/21 Change P/N to SA00003IWB0

SCHEMATICS,MB A6843
B
401982
5 4 3 2 1
A B C D E
+1.5V +1.5VS
< +5VALW TO +5VS > < +1.5V TO +1.5VS >
Q5 Inrush current = 0A
+5VS 8 1
D S
7 D S 2 1 2
+5VALW +5VS 6 3 C462 C463
D S
2
5 D G 4
Q2 Inrush current = 0A R250 1 1U_0402_6.3V4Z 10U_0805_10V4Z
2
C464 SI4800BDY_SO8 2 1
8 D S 1
7 2 1 1 470_0805_5% R305
D S C449 C450 4.7U_0805_10V4Z
6 3
1
D S RUNON 2 R285 470_0805_5%
5 D G 4
1 1U_0402_6.3V4Z 4.7U_0805_10V4Z 1.5VS_ENABLE 1 2 750K_0402_1% +VSB
1
3
C452 SI4800BDY_SO8 2 2
1
1
3
1 4.7U_0805_10V4Z R286 C466 1
2 SUSP 2N7002DW-T/R7_SOT363-6 Q11B
5
Q34B 7/8 Change Q5 from FDS6676AS to SI4800DBY 10M_0402_5% 0.01U_0402_25V7K
2 SUSP 2N7002DW-T/R7_SOT363-6
2 5
2
Q11A
4
2N7002DW-T/R7_SOT363-6
< +3VALW TO +3VS > < +1.1VALW TO +1.1VS > BOOT_ON @

@R45
R45 2 1 0_0402_5% SUSP
+1.1VALW
+3VALW +3VS +1.1VS BOOT_ON R46 2 1 0_0402_5% VLDT_EN#
Q6
Q3 IRF8113PBF_SO8 BOOT_ON @
@R47
R47 2 1 0_0402_5% VGATE#
Inrush current = 0A Inrush current = 0A
8 D S 1 8 1 1
7 D S 2 1 1 7 2 1 1
2
6 3 C468 C469 6 3 C471 C472 + C158
D S R251 @
5 D G 4 5
1 1U_0402_6.3V4Z 4.7U_0805_10V4Z 1U_0402_6.3V4Z 4.7U_0805_10V4Z 390U_2.5V_M_R10
C470 SI4800BDY_SO8 2 2 470_0805_5% 2 2 2
2
R287 1
1
4.7U_0805_10V4Z RUNON 2 1 750K_0402_1% +VSB C475 R290 R300
2 330K_0402_5%
2 1 +VSB
4.7U_0805_10V4Z 470_0805_5%
6
1
2
1
31
6
1 R291 C476
C474 Q14B Q12B
2 SUSP 5 2N7002DW-T/R7_SOT363-6 10M_0402_5% 0.01U_0402_25V7K
0.01U_0402_25V7K 2 BOOT_ON 2N7002DW-T/R7_SOT363-6
2 5
2
2 Q14A
1
4
2 2N7002DW-T/R7_SOT363-6 Q12A 2
4
2N7002DW-T/R7_SOT363-6
< +1.1VALW TO +NB_CORE > < Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
+1.1VALW
+NB_CORE
Q7
IRF8113PBF_SO8 +5VALW +5VALW
Inrush current = 0A +5VALW +5VALW
8 1
7 2 1 1
1
6 3 C479 C478
1
5 R814 R245
1U_0402_6.3V4Z 4.7U_0805_10V4Z R815
2 2 100K_0402_5% 100K_0402_5% R816 @
4
1 100K_0402_5% 100K_0402_5%
2
C480 R306
2
R292 SYSON# SUSP
SUSP <37>
4.7U_0805_10V4Z 2 1 330K_0402_5% +VSB 470_0805_5% VLDT_EN# EC_ON#
2
3 1
1
3
1
6
R293 C481 Q15B Q15A Q16B

Q13B 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
10M_0402_5% 0.01U_0402_25V7K 5 2 VLDT_EN 2 5
2 <28,36> SYSON SUSP# <23,28,37> <28> VLDT_EN EC_ON <28,30,35>
2 BOOT_ON 5 2N7002DW-T/R7_SOT363-6 Q16A
2
2N7002DW-T/R7_SOT363-6
4
Q13A
1
2N7002DW-T/R7_SOT363-6
3 3
< Discharge circuit >
+5VALW +5VALW +1.5V +0.75VS +1.8VS +1.1VALW

1
2
2
2
R802 R803 R253
R257 R258 R254
100K_0402_5% 100K_0402_5% 470_0805_5% @
470_0805_5% 470_0805_5% 470_0805_5%
2
1
1
1
VGATE# VR_ON#
VR_ON# <37>
1
1
D D D D
3
SYSON# 2 Q17 SUSP 2 Q10 SUSP 2 Q23 EC_ON# 2 Q22

Q35B Q35A G G G G @
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3
3
3
<28,38> VGATE 5 2 VR_ON <28,38>
4
4 4

SCHEMATICS,MB A6843
A B C D E
A B C D
PreCHG PQ2 @
VIN BSS84_SOT23-3
PR1 @ PD1
PF1 PL1
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
VIN 1 2 2 1 3 1 B+
0_1206_5%
RLS4148_LL34-2
PJP1 7A_24VDC_429007.WRML SMB3025500YA_2P @ PR2
+ 1 1 2
1000P_0402_50V7K
680P_0402_50V7K
1K_1206_5%
1
1 1
+ 2
1
@ PR5 PR4
PR3
2
PC1
PC17
3 PC2 PC3 PC4 1 2
- 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 100K_0402_5% 100K_0402_5%
1K_1206_5%
2
4 @ @
2
- @ PR6
@SINGA_2DW-0005-B03 1 2
1
1K_1206_5%
@ PR8 PR7 @
1 2 100K_0402_5%
1K_1206_5%
1 2
1
@ PD4
<28,34> ACOFF 2
VIN 1 2 2
<35> +5VALWP 3
2
RB715F_SOT323-3 PQ5 @ PQ3 @
3
PD2 DTC115EUA_SC70-3 DTC115EUA_SC70-3
RLS4148_LL34-2
1
1
1
PR9 PR10
68_1206_5% 68_1206_5%
2
PQ1 2
BSS84_SOT23-3
2
PD3
2 1 N1 3 1 VS
BATT+
RLS4148_LL34-2
1
1
PR12 PC7 PC8
100K_0402_1% 0.22U_0603_25V7K 0.1U_0603_25V7K
2
2
2
<29> 51_ON# 1 2
PR15
22K_0402_1%
@ PJ1 @ PJ2 @ PJ3

+3VALWP 2 2 1 1 +3VALW +1.1VALWP 2 2 1 1 +1.1VALW +3VLP 2 2 1 1 +3VL
JUMP_43X118 JUMP_43X118 JUMP_43X39
(5A,200mils, Via NO.= 10) @ PJ4 (100mA,40mils ,Via NO.= 2)
3 2 2 1 1 3
OCP(min) = 8.33A
JUMP_43X118
(16A,640mils, Via NO.= 32)
@ PJ5 @ PJ9
+5VALWP 2 2 1 1 +5VALW OCP(min) = 18.7A +2.5VSP 2 2 1 1 +2.5VS
JUMP_43X118 JUMP_43X39
(5A,200mils, Via NO.= 10) @ PJ7 (1A,40mils ,Via NO.= 2)
+1.5VP 2 1 +1.5V
2 1
OCP(min) = 8.33A
JUMP_43X118
@ PJ8 (9.5A,380mils ,Via NO.= 20) @ PJ12
+VSBP 2 2 1 1 +VSB +VDDNBP 2 2 1 1 +VDDNB
OCP(min) = 8.7A
JUMP_43X39 JUMP_43X79
(120mA,40mils, Via NO.= 1) (4A,160mils ,Via NO.= 8)
@ PJ10
@ PJ11 +1.8VSP 2 1 +1.8VS @ PJ13
2 1
+0.75VSP 2 2 1 1 +0.75VS +1.05VSP 2 2 1 1 +1.05VS
JUMP_43X79
JUMP_43X79 (2.5A,100mils, Via NO.= 5) JUMP_43X79
(1.5A,60mils, Via NO.= 3) (1.75A,80mils, Via NO.= 4)
4 4
Precharge detector
15.97V/14.84V FOR
ADAPTOR
SCHEMATICS,MB A6843
Size
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401982
A B C D
A B C D
PH1 under CPU botten side :

CPU thermal protection at 95 degree C
Recovery at 56 degree C
Rset = 3 * Rtmh
VMB Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
1
PF2 PL2 1
@ PJP2 10A_125V_451010MRL SMB3025500YA_2P

1 BATT_S1 1 2 1 2
1 BATT+
2 2
3 BATT_P3
Rtmh at 95C = 6.64K, Rtml at 57C = 25.1K
3 +3VLP
BATT_P4
4 4 Rset = 3 * 6.64K = 19.92K ==> 20K
1
5 BATT_P5
5 EC_SMDA PC14 PC15
10
11
GND 6 6
7 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K Rhyst = (20K * 25.1K) / (3 * 25.1K - 20K) = 9.078K ==> 9.09K
2
GND 7
12 GND 8 8
1
13 GND 9 9
PR32 VL
1
SUYIN_200045MR009G171ZR 1K_0402_1%
2
PD6
PJSOT24C_SOT23-3
3
PD8
2
1
1
3
1
PR31
PJSOT24C_SOT23-3 PC16 23.2K_0402_1%
0.1U_0402_16V4Z
2
PR37 PU3
6.49K_0402_1% 1 8
VCC TMSNS1
2 1 +3VLP
2
2
2 GND RHYST1 7
PR38 PR39
100K_0402_1%_NCP15WF104F03RC
100_0402_1% 100_0402_1% <35> VS_ON 3 6 PR33
2 OT1 TMSNS2 10.7K_0402_1% 2
1
4 5
1
1
PR40 OT2 RHYST2
1
1K_0402_1% G718TM1U_SOT23-8
PH1
2
2
BATT_TEMPA <28>
EC_SMB_DA1 <28>
EC_SMB_CK1 <28>
PQ6
BSS84_SOT23-3
B+ 3 1 +VSBP
0.1U_0603_25V7K
100K_0402_1%
0.22U_0603_25V7K
1
3 3
PC20
1
PR43
@ PC19
VL @
2
2
2
PR45
2
1 2
PR47
100K_0402_1% 22K_0402_1%
1
PR48
1
0_0402_5% D
1 2 2 PQ7
<35,36> POK
G SSM3K7002FU_SC70-3
S
3
.1U_0402_16V7K
1
PC22
2
4 4

SCHEMATICS,MB A6843
Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401982 B
A B C D
A B C D
PQ8
10U_1206_25V6M
10U_1206_25V6M
10U_1206_25V6M
AO4435_SO8
P2 1 8
1
PQ9 PQ10 2 7
PC31
PC130
PC132
AO4435_SO8 SI4483ADY-T1-GE3_SO8 3 6
CHG_B+
8 1 1 8 B+ 5
2
7 2 2 7 P3 PR49
6 3 3 6 0.02_1206_1% @ PJ22
4
VIN 5 5 1 4 2 2 1 1
2 3 JUMP_43X79 CSIN
4
1 2 VIN
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
CSIP PR54
2
1 1
47K_0402_1%
VIN PreCHG
1
2
PC23
PC24
PC28
PR56
0.1U_0603_25V7K
PQ13 PR50 PC25 10K_0402_1%
2
1
DTA144EUA_SC70-3 200K_0402_1% 5600P_0402_25V7K
1 1
1
PC26
PR226
2
2 191K_0402_1%
PR52
2
200K_0402_1% PD201
2
1000P_0402_25V8J
RB751V-40_SOD323-2 ACSETIN PQ16
2
DTC115EUA_SC70-3 2
1 1
1
1
1
2200P_0402_25V7K
PC217
6251VDD PR228
1
PR227 14.3K_0402_1%
2.2U_0603_6.3V6K
PC32
BATT_ON 2 PR57 10_1206_5%
2
1
PC27
PQ15 10K_0402_1% PR238
2
DTC115EUA_SC70-3 2 1 PU4 100K_0402_1%
<28> FSTCHG PC29
2
6
D DCIN 2
1 24 1
3
VDD DCIN
1
1
2
G 0.1U_0603_25V7K BATT_ON
PR59 PR60 ACSETIN 2 23
ACSET ACPRN ACPRN <35>
1
PQ20A 150K_0402_1% 100K_0402_1% PR61 D
S
1
DMN66D0LDW-7_SOT363-6 20_0603_5% ACPRN 2

2
2
6251_EN 3 22 1 2 CSON G
EN CSON
2
PC30 S
3
5
6
7
8
0.047U_0603_16V7K PQ18
4 21 1 2 CSOP SSM3K7002FU_SC70-3
1
CELLS CSOP PR62 20_0603_5%
2
PQ20B PC33 1 2 6800P_0402_25V7K 5 20 2 1 2
ICOMP CSIN
3
2
DMN66D0LDW-7_SOT363-6 D PC34 PR63 PQ19
4
5 PC35 PR64 0.1U_0603_25V7K 20_0603_5% AO4466L_SO8
G 1 2 1 2 6 19 1 2
1
VCOMP CSIP
PR66 PR65 2.2_0603_5% PL4 PR67 BATT+
S 0.01U_0402_25V7K 6.81K_0402_1% 47K_0402_1% 10UH_MSCDRI-104A-100M-E_4.6A_20%
0.02_1206_1%
4
3
2
1
PR68 1 2 7 18 LX_CHG 1 2 CHG 1 4
47K_0402_5% <28> ADP_I ICM PHASE
5
6
7
8
PACIN 1 2 1 2 2 3
10U_1206_25V6M
10U_1206_25V6M
10U_1206_25V6M
6251VREF 8 17 DH_CHG
PR71 PC37 VREF UGATE PR70 PC38 PR69
154K_0402_1% .1U_0402_16V7K 2.2_0603_5% 0.1U_0603_25V7K 4.7_1206_5%
1
PC39
PC40
PC48
2 1 9 16 BST_CHG
1 2 BST_CHGA
2 1
<28> IREF CHLIM BOOT
1
1
0.01U_0402_25V7K
PR72 4
1 2
24K_0402_1% PD14
2
1
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40_SOD323-2 PC41 @

ACLIM VDDP
1
PC42
PR73 12.4K_0402_1% 680P_0603_50V7K

1
ACOFF 2 120K_0402_1% 1 26251VDD PQ21

<28,32> ACOFF
3
2
1
2
1
20K_0402_1%
PR193
11 14 DL_CHG AO4466L_SO8
2
VADJ LGATE
2
PR74
2
PR75
PQ22 4.7_0603_5%
DTC115EUA_SC70-3 12 13 PC43
3
1 2
1
GND PGND 4.7U_0805_6.3V6K
2
D
2
<28> 75W_65W G ISL6251AHAZ-T_QSOP24
S
3
PQ39
SSM3K7002FU_SC70-3 6251VDD
3 3
PR76
15.4K_0402_1%
1 2 VADJ
<28> CHGVADJ
1
PR240 1 PR242 PR241 VIN

47K_0402_1% 10K_0402_1% 10K_0402_1%
1
1 2 ACIN <20,28,29>
PR77
1
31.6K_0402_1%
2
@ PR78
PACIN 309K_0402_1%
2
@ PR79
2
10K_0402_1%
Vin Detector 1 2
ADP_V <28>
1
ACPRN 2 PR243
1
14.3K_0402_1% High 18.089V
1
CHGVADJ=(Vcell-4)*9.445 @ PR80
PQ214 Low 17.44V 47K_0402_1% @ PC44
2
Vcell CHGVADJ CC=0.25A~3.6A DTC115EUA_SC70-3 .1U_0402_16V7K

3
2
2
4V 0V IREF=0.9133*Icharge (UMA) Iin = 2.512 ADP_I
4.2V 1.882V IREF=0.228V~3.29V
Vin = 7.57 ADP_V
4.35V 3.2935V VCHLIM need over 95mV
UMA Iada=0~3.421A(65W) CP=3.15A PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=high

4 4
Iada=0~3.947A(75W) CP=3.63A PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=low
CP= 92%*Iada

SCHEMATICS,MB A6843
A B C D
5 4 3 2 1
2VREF_6182
1
PC45
1U_0603_10V6K
2
D D
PR81 PR82
13K_0402_1% 30K_0402_1%
1 2 1 2
PR83 PR84
UP6182_B+
20K_0402_1% 19.1K_0402_1%
UP6182_B+
1 2 1 2
PL3
HCB2012KF-121T50_0805 +3VLP
B+ 2 1
ENTRIP2
ENTRIP1
2200P_0402_50V7K
10U_1206_25V6M
PR85 PR86
2200P_0402_50V7K
10U_1206_25V6M
10U_1206_25V6M
150K_0402_1% 150K_0402_1%
1
1
1 2 1 2
PC46
PC47
5
6
7
8
PC49
PC50
PC51
2
2
8
7
6
5
1
PC52
1
4.7U_0805_10V6K PU5
2
4
VREF
ENTRIP2
VFB2
ENTRIP1
TONSEL
VFB1
4 PQ23
25 P PAD AO4466L_SO8
Ipeak=8.61A
POK <33,36>
C
Imax=6.03A C
3
2
1
1 PQ24 7 24
2
3
VO2 VO1
F=245K
PL6 AO4466L_SO8 PC53 8 23 PC54 PL7
4.7UH_SIL1045R-4R7PF_6.3A_30% 0.1U_0603_25V7K VREG3 PGOOD 0.1U_0603_25V7K 4.7UH_SIL1045R-4R7PF_6.3A_30%
Ipeak = 7.65A 1 2 1 2 1 PR87 2 BST_3V 9 22 BST_5V 1 PR88 2 1 2 1 2 +5VALWP
+3VALWP VBST2 VBST1
Imax = 5.36A 0_0603_5%
UG_3V UG_5V
0_0603_5%
10 DRVH2 DRVH1 21
8
7
6
5
5
6
7
8
F = 305K
1
1
LX_3V 11 20 LX_5V
PR89 LL2 LL1 PR90
1 4.7_1206_5% LG_3V 12 19 LG_5V 4.7_1206_5% 1
DRVL2 DRVL1
SKIPSEL
PC55 + 4 4 + PC56
VREG5
1 2
1 2
VCLK
330U_6.3V_M 330U_6.3V_M
GND
EN0
VIN
PC57 PQ25
2 680P_0603_50V7K PQ26 PC58 2
AO4712L_SO8 TPS51125ARGER_QFN24_4X4 680P_0603_50V7K
2
1
2
3
13
14
15
16
17
18
3
2
1
2
PR91 AO4712L_SO8
499K_0402_1%
B+ 1 2
Total capacitor 220uF
1
100K_0402_1%
1U_0402_6.3V6K
1
ESR = 15mohm Total capacitor 220uF
PR92
PC59
ENTRIP1 ENTRIP2 VL ESR = 15mohm
2
2
1
PC60
B 4.7U_0805_10V6K B
UP6182_B+
2
6
D D
PQ27A 2 5 PQ27B 2VREF_6182
DMN66D0LDW-7_SOT363-6 G G DMN66D0LDW-7_SOT363-6
1
S S PC61
1
0.1U_0603_25V7K
2
VL 2 1
PR94
100K_0402_1%
1
<33> VS_ON
VS 1 2 2
PR95
1
42.2K_0402_1%
2.2U_0603_10V6K
100K_0402_1% PQ29
1
DTC115EUA_SC70-3
SSM3K7002FU_SC70-3
3
PR96
PC370
1
D
PR373
2
PQ362
<34> ACPRN 1 2 2
2
G
A 200K_0402_1% A
S
3
1
2
<28,29,31> EC_ON Security Classification Compal Secret Data Compal Electronics, Inc.
PQ363 Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title
DTC115EUA_SC70-3
SCHEMATICS,MB A6843
3
5 4 3 2 1
5 4 3 2 1
PL151
HCB2012KF-121T50_0805
1.1V_B+ 1 2 B+
2200P_0402_50V7K
10U_1206_25V6M
4.7U_0805_25V6-K
4.7U_0805_25V6-K
68U_25V_M_R0.36
1
1
1
1
PC62
PC63
PC133
PC91
+
PC127
2
2
5
2
2
D D
PR97 4
255K_0402_1%
PR98 1 2 PQ30
Ipeak = 16.1A
0_0402_5% TPCA8030-H_SOP-ADV8-5 Imax = 11.3A
<33,35> POK 1 2 1 2
3
2
1
F = 315K
PR99
0_0603_5% PL9
15
14
1
1
PU6 PC65 1UH_FDUE1040D-1R0M-P3_21.3A_20%
@ PC64 BST_1.1V 1 2 1 2
EN_SKIP
TP
BST
+1.1VALWP
.1U_0402_16V7K
2 2 TON DH 13 DH_1.1V 0.1U_0603_25V7K (+1.1VALW, +1.1VS, NB_CORE)
4.7_1206_5%
MDU2653RH_POWERDFN56-8-5
PR100
PR101 3 12 LX_1.1V
OUT LX
5
100_0603_1% 1
+5VALW 1 2 4 11 1 2 +5VALW
VCC ILIM PR102 +
2
9.1K_0402_1% PC66
5 FB VDD 10 Total capacitor 550uF
PQ31
330U_6.3V_M
1
1
2
680P_0603_50V7K
6 PGOOD DL 9 DL_1.1V 4 ESR = 7.5mohm
AGND
PGND
PC67
PC68
4.7U_0603_6.3V6K
2
2
PC69
G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K
3
2
1
PR103
4.75K_0402_1%
1 2
C C
1
PR104
10K_0402_1%
2
PL152
HCB2012KF-121T50_0805
1.5V_B+ 1 2 B+
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
PC71
PC72
PC79
5
6
7
8
2
PR105
255K_0402_1% 4
1 2
PR106 PQ32
0_0402_5%
1 2 1 2 AO4466L_SO8
<28,31> SYSON Ipeak = 9.5A
3
2
1
PR107 Imax = 6.65A
1
0_0603_5% PL11
15
14
1
B @PC73
@ PC73 PU7 PC74 1.8UH_SIL104R-1R8PF_9.5A_30% F = 315K B
.1U_0402_16V7K BST_1.5V 1 2 1 2
EN_SKIP
TP
BST
+1.5VP
2
2 13 DH_1.5V 0.1U_0603_25V7K
TON DH
1
PR109 LX_1.5V PR108
3 OUT LX 12 Total capacitor 220uF
5
6
7
8
100_0603_1% 4.7_1206_5% 1
+5VALW 1 2 4 VCC ILIM 11 1 2 +5VALW
+
ESR = 15mohm
PR110
2
5 10 20K_0402_1% PC75
FB VDD 330U_6.3V_M
1
1
DL_1.5V 2
6 PGOOD DL 9 4
AGND
PGND
PC76 PC77
1
4.7U_0603_6.3V6K PQ33 680P_0603_50V7K

2
2
PC78
G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K AO4712L_SO8
7
3
2
1
PR111
10K_0402_1%
1 2
1
PR112
10K_0402_1%
2
A A

SCHEMATICS,MB A6843
5 4 3 2 1
5 4 3 2 1
+1.5V
VDDR_SW VDDR
D D
HIGH 1.05V
1
+3VS +5VALW
PJ15
1
@ JUMP_43X79
LOW 0.9V
1
2
PJ16
1
2
@ JUMP_43X79
2
1
1
PC84 +5VALW PC181
2
1
4.7U_0805_6.3V6K 1U_0603_6.3V6M
@ PR148
2
2
1
1
12.4K_0402_1% PC85
PU9 4.7U_0805_6.3V6K
SSM3K7002FU_SC70-3
@ PR167 APL5331KAC-TRL_SO8~N
1 2
2
10K_0402_1% 1
D @ VIN VCNTL 6 +5VALW
6
2
VCNTL
1U_0603_6.3V6M
<34> VDDR_SW 2 2 GND NC 5 5 VIN VOUT 3 +1.8VSP
PC82
G PQ11 PR195 9 4
VIN VOUT
1
22U_0805_6.3V6M
0.01U_0402_25V7K
S 3 7 0_0402_5%
3
VREF NC
1
1 2 8 PR165
2
EN
PC88
PC89
@ PR153 4 8 SUSP# 7 2 3K_0402_1%
GND
10K_0402_1% PR113 VOUT NC POK FB
2
1
6.98K_0402_1% 9
2
2
TP @ PC83
1
0.01U_0402_25V7K PU10
1
.1U_0402_16V7K
APL5930KAI-TRG_SO8
1
SSM3K7002FU_SC70-3
PR115 +1.05VSP PR166
1
1
D
PC86
0_0402_5% 2.4K_0402_1%
<31> VR_ON# 1 2 2
1
G PQ4
2
1
C S PC87 C
3
@ PC90 2 PR117 10U_0805_6.3V6M
2
.1U_0402_16V7K 10.5K_0402_1%
2
+1.5V
1
@ PJ17
1
JUMP_43X79
2
PU11
APL5331KAC-TRL_SO8~N
2
1 VIN VCNTL 6 +3VALW
2 GND NC 5
1
1
PU8 PC92 3 7 PC93
APL5508-25DC-TRL_SOT89-3 4.7U_0805_6.3V6K PR119 VREF NC 1U_0603_6.3V6M
2
+3VS @ PJ14 1K_0402_1% 4 8
VOUT NC
1 1 2 2 2 IN OUT 3 +2.5VSP
B B
9
2
JUMP_43X39 TP
GND
1
.1U_0402_16V7K
PC80 PC81 PR121 +0.75VSP
1
1U_0603_10V6K 4.7U_0805_6.3V6K 0_0402_5% D
2
PC94
1 2 2 PR120
<31> SUSP
1
G 1K_0402_1%
1
S PC95
2
@ PC96 PQ34 10U_0805_6.3V6M
2
.1U_0402_16V7K SSM3K7002FU_SC70-3
A A

SCHEMATICS,MB A6843
5 4 3 2 1
A B C D E
CPU_B+ PL12
HCB4532KF-800T90_1812
PC97 1 2 B+
10U_1206_25V6M
33P_0402_50V8J
68U_25V_M_R0.36
68U_25V_M_R0.36
68U_25V_M_R0.36
2 1 1 1 1
5
6
7
8
1
+ + +
PC101
PC98
PC99
PC128
2 1 2 1
2
PR122 PC100 2 2 2
44.2K_0402_1% 1000P_0402_50V7K UGATE_NB 4
PR123
1 2_0603_5% PQ35 1
+5VALW 1 2 PC102 PL13

1000P_0402_50V7K AO4466L_SO8 4.7UH_SIL1045R-4R7PF_6.3A_30%
3
2
1
2 1 PHASE_NB 1 2 +VDDNBP
PR124
5
6
7
8
1
PC103 PR126 2.2_0603_1%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 PR125 1
2 1 PR191 4.7_1206_5%
2
10_0402_1% PC104 + PC105
1 2 0.22U_0603_10V7K 330U_6.3V_M
+VDDNB
1 2
LGATE_NB 4
PR128 PC106 2
CPU_B+ 1 2
0_0402_5% PQ36 680P_0603_50V7K
PR127 2 1 CPU_VDDNB_RUN_FB_H <7>
2
2_0603_5% PR129 AO4712L_SO8
3
2
1
+3VS +5VS +3VS 11K_0402_1%
2 1 PHASE_NB
1
PC107
0.1U_0603_25V7K LGATE_NB PR192
10_0402_1% CPU_B+
Ipeak = 36A
2
PHASE_NB 1 2
1
1
Imax = 25.2A
1
PR130 @ PR131
@PR131 UGATE_NB
F = 300K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0_0402_5% 105K_0402_1%
5
PR132 @ PR134 2 1
105K_0402_1% 10K_0402_1% PR133
CPU_VDDNB_RUN_FB_L <7> Total capacitor 1320uF
2
1
PC108
PC109
PC129
0_0402_5%
2
ESR = 1.5mohm
2
1
UGATE0 4
48
47
46
45
44
43
42
41
40
39
38
37
<28,31> VGATE @ PR135
@PR135 PU12
2 105K_0402_1% PHASE0 PQ37 PL14 2
FB_NB
COMP_NB
FSET_NB
VSEN_NB
OCSET_NB
LGATE_NB
VIN
VCC
RTN_NB
PGND_NB
PHASE_NB
UGATE_NB
PR137 TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%
2
3
2
1
1 2 0_0603_5%
<7,18> H_PWRGD @ PR136 0_0402_5% 1 36 BOOT_NB BOOT0 1 2 1 2 1 4
OFS/VFIXEN BOOT_NB +CPU_CORE
1 2 2 35 BOOT0 PC110 2 3
PGOOD BOOT0
5
<18> H_PWRGD_L PR138 0_0402_5% 0.22U_0603_10V7K
1
ISL6265_PWROK 3 34 UGATE0
PWROK UGATE0
2
<7> CPU_SVD PR139
2 1 4 33 PHASE0 4.7_1206_5% PR141
<7> CPU_SVC PR140 SVD PHASE0 16.5K_0402_1%
0_0402_5%2 1 5 32 +5VALW LGATE0 4 PQ38
1 2
<28,31> VR_ON PR142 SVC PGND0 MDU2653RH_POWERDFN56-8-5
1
PR143 PR144 0_0402_5% 6 31 LGATE0 PC111 PC112
21.5K_0402_1% 95.3K_0402_1% ENABLE ISL6265CHRTZ-T_TQFN48_6X6 LGATE0 680P_0603_50V7K 2 1
2 1 2 1 7 30
3
2
1
2
RBIAS PVCC 0.1U_0603_16V7K
8 29 LGATE1
OCSET LGATE1
1
PC113 2 1
9 28 1U_0603_10V6K
VDIFF0 PGND1 PR145
ISN0
ISP0
10 27 PHASE1 4.02K_0402_1%
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1
VW0 BOOT1
COMP1
VDIFF1
VSEN0
VSEN1
RTN0
RTN1
ISN0
ISN1
ISP0
VW1
ISP1
FB1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
TP
5
13
14
15
16
17
18
19
20
21
22
23
24
49
2
1
PC114
PC115
PC131
3 ISP0 3
+CPU_CORE 2 1 PC371 ISN0

1
2
ISN1
ISP1
PR189 330P_0402_25V8J UGATE1 4

10_0402_1%
PL15
2200P_0402_25V7K
PHASE1 PQ40 0.36UH_PCMC104T-R36MN1R17_30A_20%

2 1 VSEN0 PR149 TPCA8030-H_SOP-ADV8-5
3
2
1
<7> CPU_VDD0_RUN_FB_H 0_0603_5% 1 4
1
PC218
PR146 BOOT1 1 2 1 2 +CPU_CORE

0_0402_5% 2 3
PC116
2
5
2 1 RTN0 0.22U_0603_10V7K
1
<7> CPU_VDD0_RUN_FB_L PR147
2
0_0402_5% PR150 PR151
PR190 1K_0402_1% 4.7_1206_5% PR152
1
10_0402_1% 16.5K_0402_1%
1
2 1 PC219 LGATE1 4 PQ41
1 2
1000P_0402_50V7K +1.5V MDU2653RH_POWERDFN56-8-5
2
1
PC117 PC118
680P_0603_50V7K 2 1
VSEN0
3
2
1
2
0.1U_0603_16V7K
DIFF_0 VW0 DIFF_1 VW1 2 1
PR155 @ PR156
@PR156 PR154
ISN1
ISP1
255_0402_1% 255_0402_1% 4.02K_0402_1%
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1
PC119 PC120 PC121 @ PC122 @ PC123 @PC124

@ PC124
4700P_0402_25V7K 180P_0402_50V8J 1000P_0402_50V7K 4700P_0402_25V7K 180P_0402_50V8J 1000P_0402_50V7K
4 PR159 @PR162
@ PR162 4
PR158 PC125 6.81K_0402_1% @ PR161 @ PC126 6.81K_0402_1%
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
PR157 54.9K_0402_1% 1200P_0402_50V7K @ PR160 54.9K_0402_1% 1200P_0402_50V7K

1K_0402_5% 1K_0402_5%
1
@ PR163
36.5K_0402_1%
@ PR164
36.5K_0402_1%
SCHEMATICS,MB A6843
2
A B C D E
5 4 3 2 1
PIR (Product Improve Record)

PWWAE LA-6843P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
1 2010/07/20 28 Reserve C1199,Y5,C1200 For design change
2 2010/07/20 28 Reserve R436 for only KB926E0 For design change
2010/07/20 29 Del R875 For SERIRQ direct connect to H7.7
2010/07/20 29 Del C588/C589/Y4/R368 For design change
3 2010/07/21 11~15 Change U8 R1 P/N from A12(SA000032WI40) to A13(SA000032WA0) For SB820 A13 version
2010/07/21 30 Change U8 R3 P/N from A12(SA000032WI50) to A13(SA000032WB0) For SB820 A13 version
4 2010/07/23 18 Change D8 from DAN202U to CHN202UPT For design change
5 2010/07/23 24 Chagne UL4 from LF-H1201P-2 to LFE8456E-R for use 5mA type For design change
D 6 2010/07/23 30 Change R768/R773 from 120 to 510 ohm for use 5mA type For design change D
Change R768.1 pull up from +3VALW to +5VALW for use 5mA type For design change
Change R773.1 pull up from +3VALW to +5VALW for use 5mA type For design change
7 2010/07/23 27 Change JLINE/JEXMIC to FOX_JA6331-B39S4-7F For DFX request
8 2010/07/26 23 Reserve DM2 For +3V_WLAN is +3VS
9 2010/07/26 Add R50 For Intel Rainbow Peak module
2010/07/26 24 Reserve CL39 For EMI request
10 2010/07/27 28 Change R867 pull up from +3VALW to +3VL For design change
REVISION CHANGE: 0.2 TO 1.0
NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
1 2010/08/06 29 Change U13 footprint to M25P10-AVMN6T-SOP For design change
2 2010/08/06 25 Change Net name form V1_8 to +V1_8 For customer request
2010/08/06 29 Add R774 link to BATT_CHG_LOW_LED# For customer request
2010/08/06 29 Change R773 link to BATT_FULL_LED# For customer request
3 2010/08/06 30 Reserve SW6 Del SW5 For debug phase
2010/08/09 30 Chagne UL4 from NS681680 to NS681610 For design change
4 2010/08/09 08 Mount C26/C89,Reserve C24,C90 For design change
5 2010/08/16 18 Del R42/C94 For EMI request
2010/08/16 18 Reserve CC9/RC7 For EMI request
6 2010/08/16 24 Add CL3/CL7 link to +3V_LAN For EMI request
Reserve CL38 For EMI request
Change CL37 from 0.1uF to 120 pF For EMI request
Add D13 link to LANGND For EMI request
C C
B B
A A

SCHEMATICS,MB A6843
Size
Document Number Rev
B
401982
5 4 3 2 1
A B C D E
Version Change List ( P. I. R. List ) for Power Circuit

NO DATE PAGE MODIFICATION LIST PURPOSE Rev.
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1 2010 . 06 . 21 Release 1
2010 . 07.25 modification list
P 33 PC16 change to SE070104Z80 Defore material EOL PVT

P 38 PU12 change to SA000022M80 Before material MP schedule will impact PWWAE MP schedule PVT
P 33 Remove PD6 , PD8 @ ESD test fail PVT
P 34 Add PC132 , remove PC130 , PC131 , PR69 , PC41 @ For EMI fail PVT
P 35 Add PC51 , remove PC49 , PC46 , PC57 , PC58 , PR89 , PR90 @ For EMI fail PVT
P 36 Add PC79 , PC91 , PC133 , remove PR100 , PR108 , PC68 , PC77 @ For EMI fail PVT
P 38 Remove PR125 , PR139 , PR151 , PC106 , PC111 , PC117 @ For EMI fail PVT
2 2010 . 08.10 modification list 2
P 37 Change PU9 , PU11 to SA053310110 UP7711 stop using from now on Pre-MP
P 38 Add PC218 , PC219 , PC371 For VCORE Ripple Pre-MP
P 32 Add PR8 For Precharge rising current Pre-MP
P 32 , P 33 PQ1 , PQ2 , PQ6 change to SB900840003 SB906100210 material delivery had problem Pre-MP
P 35 Change PU5 to SA000020C80 UPI product stop using Pre-MP

P 34 Change PU4 to SA00001EP80 SA00003TK00 stop using Pre-MP

3
P 38 Remove PR127 @ To solve +1.1VALW noise Pre-MP 3
P 34 Remove PR193 , PQ39 @ For PWWAE MP use 25W CPU Pre-MP
4 4

SCHEMATICS,MB A6843
A B C D E

Toshiba Satellite c660d - Compal La-6843p Pwwae - Rev 1.0

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Toshiba Satellite c660d - Compal La-6843p Pwwae - Rev 1.0

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A B C D E

PWWAE LA-6843P Schematics Document

Mobile AMD S1G4/ RS880M / SB820M

2010-08-16 Rev. 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Compal Confidential Thermal Sensor Fan Control AMD S1G4 CPU

File Name : LA-6843P page 5,6,7,8

1 Hyper Transport Link 2.6GHz 1

LCD Conn. PCIe 4x

Power Circuit DC/DC

Security Classification Compal Secret Data Compal Electronics, Inc.

DESIGN CURRENT 0.1A +3VL

Security Classification Compal Secret Data Compal Electronics, Inc.

S5 S4/AC & Battery

SMBUS Control Table

Security Classification Compal Secret Data Compal Electronics, Inc.

250 mil VLDT CAP. Near CPU Socket

10U_0805_10V6K 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J

H_CADIP0 E3 AD1 H_CADOP0

<11> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <11>

<11> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <11>

< FAN Control Circuit : Vout = 1.6 x Vset >

VOUT GND ACES_85204-0300N

Security Classification Compal Secret Data Compal Electronics, Inc.

+MCH_REF DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1

1 1 DDR_B_D3 B14 G14 DDR_A_D3

DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8

Security Classification Compal Secret Data Compal Electronics, Inc.

R34 2 1 1K_0402_5% CPU_TEST22

R265 2 1 1K_0402_5% CPU_TEST23

R35 2 1 1K_0402_5% CPU_TEST24

R39 220_0402_5% CPU_TCK 2 2200P_0402_50V7K R41 10K_0402_5%

H_PWRGD 19 20 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8

+CPU_CORE JCPUE +CPU_CORE

+1.5V +1.5V B6 N16

Near CPU Socket Right side @ 1 1 D25 U12

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

PCIE I/F GFX

<18> SB_RX0P AA8 AD7 SB_TX0P_C C133 1 2 0.1U_0402_16V7K

H_CADOP5 P22 J25 H_CADIP5

<5> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <5>

Security Classification Compal Secret Data Compal Electronics, Inc.

A11 B16 LCD_TXCLK+ LCD_TXCLK+ <17>

<18> CLK_SBSRC_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)

R366 1 2 1K_0402_1% CPU_LDT_REQ# +1.8VS

R988 1 2 150_0402_1% UMA_CRT_G NC7SZ08P5X_NL_SC70-5

R989 1 2 150_0402_1% UMA_CRT_B

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

Enables the Test Debug Bus using GPIO.

PIN: RS880--> VSYNC#

These pin straps are used to configure PCI-E GPP mode.

< SUS_SATA# : LOAD_EEPROM_STRAPS >

< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >

RS880: Enables Side port memory ( RS780 use HSYNC#)

Security Classification Compal Secret Data Compal Electronics, Inc.

+3VS < Display Data Channel >

Security Classification Compal Secret Data Compal Electronics, Inc.

+3VS +3VS +LCD_VDD

@ R96 1 2 0_0402_5% INVT_PWM

LCD_EDID_CLK 2.2K_0402_5% 2 1 R117

LCD_EDID_DATA 2.2K_0402_5% 2 1 R118