DE LA SALLE LIPA

COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING

ELECTRICAL ENGINEERING DEPARTMENT
LOGSWIT – LOGIC CIRCUITS AND SWITCHING THEORY
LABORATORY EXPERIMENT MANUAL

De La Salle Lipa
1962, J.P. Laurel, Mataas na Lupa, Lipa City
Department of Electrical Engineering

Experiment # 8
SUBTRACTERS

Name: Aro, Danilia G. DOP: 12/12/20

Course and Year: BSEE – 3rd Year DOS: 12/19/20
Subject and Section: Logcist – V3B

Grade

Engr. Ramon P. Flores IV, MEO – CoE

Instructor

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 DE LA SALLE LIPA
COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING
ELECTRICAL ENGINEERING DEPARTMENT
LOGSWIT – LOGIC CIRCUITS AND SWITCHING THEORY
LABORATORY EXPERIMENT MANUAL

I. OBJECTIVES

At the end of the experiment, the students should be able to:

1. implement the design of subtracters through the use of logic gates
2. implement a cascaded subtracters circuit

II. DISCUSSION

The full subtractor is a combinational circuit which is used to perform subtraction of three
input bits: the minuend X, subtrahend Y, and borrow in Bin. The full subtractor generates
two output bits: the difference D and borrow out Bout. Bin is set when the previous digit
borrowed from X. Thus, Bin is also subtracted from X as well as the subtrahend Y. Or in
symbols: X – Y - Bin. Like the half subtractor, the full subtractor generates a borrow out
when it needs to borrow from the next digit. Since we are subtracting X by Y and Bin, a
borrow out needs to be generated when X < Y - Bin. When a borrow out is generated, 2
is added in the current digit. (This is similar to the subtraction algorithm in decimal.
Instead of adding 2, we add 10 when we borrow.) Therefore, D = X – Y - Bin + 2 Bout.

The truth table for full subtractors is:

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 DE LA SALLE LIPA
COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING
ELECTRICAL ENGINEERING DEPARTMENT
LOGSWIT – LOGIC CIRCUITS AND SWITCHING THEORY
LABORATORY EXPERIMENT MANUAL

III. COMPONENTS NEEDED

1 Power Supply (w/5V DC source)

1 Logic Probe
1 Connecting Wires
2 Breadboard
4 XOR Gate
4 AND Gate
1 OR Gate

IV. PROCEDURE

1. Illustrated below is a four-bit subtracter circuit. Notice that the circuit employs the
same diagram as that of the four-bit full adder with the addition of the EXOR gate and
the SUB line input.

7486 Pin Configuration

LOGIC DIAGRAM

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 DE LA SALLE LIPA
COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING
ELECTRICAL ENGINEERING DEPARTMENT
LOGSWIT – LOGIC CIRCUITS AND SWITCHING THEORY
LABORATORY EXPERIMENT MANUAL
2. With the given design, implement the circuit. Test for the results of the conditions in the table
on page 2. Write down the result on the space provided in the table

𝑨𝟑 𝑨𝟐 𝑨𝟏 𝑨𝟎 𝑩𝟑 𝑩𝟐 𝑩𝟏 𝑩𝟎 𝑺𝟑 𝑺𝟐 𝑺𝟏 𝑺𝟎
1 0 1 1 0 1 0 1 0 1 1 0
1 1 0 1 1 0 0 1 0 1 0 0
1 0 0 0 0 1 1 1 0 0 0 1
0 1 1 1 0 0 1 1 0 1 0 0
0 1 0 1 0 1 0 0 0 0 0 1
1 1 1 0 1 0 1 0 0 1 0 0
0 1 1 0 0 0 1 1 0 0 1 1
1 0 1 0 0 1 1 0 0 1 0 0

3. From the given logic diagram of the subtracter circuit, draw the implementing circuit on the
space below with the use of AND, OR, and EXOR gates.

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 DE LA SALLE LIPA
COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING
ELECTRICAL ENGINEERING DEPARTMENT
LOGSWIT – LOGIC CIRCUITS AND SWITCHING THEORY
LABORATORY EXPERIMENT MANUAL

V. DATA AND RESULTS

𝑨𝟑 𝑨𝟐 𝑨𝟏 𝑨𝟎 𝑩𝟑 𝑩𝟐 𝑩𝟏 𝑩𝟎 𝑺𝟑 𝑺𝟐 𝑺𝟏 𝑺𝟎
1 0 1 1 0 1 0 1 0 1 1 0
1 1 0 1 1 0 0 1 0 0 1 0
1 0 0 0 0 1 1 1 0 0 0 1
0 1 1 1 0 0 1 1 0 1 0 0
0 1 0 1 0 1 0 0 0 0 0 1
1 1 1 0 1 0 1 0 0 1 0 0
0 1 1 0 0 0 1 1 0 0 1 1
1 0 1 0 0 1 1 0 0 1 0 0

Table 1

VI. CONCLUSION
In this experiment, students were able to understand the design of a subtracter
circuit. This circuit is another type of combinational circuit that includes three inputs: A, B,
and CIN; and produces an output which is the subtraction of binary numbers. To create a
subtractor circuit, a XOR gate must be added on the design of a full-adder circuit as it acts
as an inverter to reverse the input on the circuit design. Also, performing subtraction on
this circuit, the carry input or CIN should be equal to 1. As subtraction is a basic function
of arithmetic operations, this kind of logic circuit is used computers. Overall, students
were able to implement the design of a cascaded subtracter circuit with the usage of logic
gates.