Homework Assignment 2

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Table 1: Process parameters for hand calculation problems.

Transistor µ (cm2/Vs) Cox(F/cm2) Vth(V) γ (V0.5) |φf|(V)

NFET 250 2.5 ×10−6 0.3 0.4 0.3

PFET 200 2.5 ×10−6 -0.4 -0.4 0.3

1
Question A. DC simulation of a CMOS inverter circuit in FreePDK45. Use minimum
channel length for both nFET and pFET. Use VDD=1.0 V.

1. Draw the schematic of a CMOS inverter in CADENCE. Find W p/Wn such that the
switching threshold VMis equal to 0.5VDD.

(Wp/Wn) = 1.66
2. Call the Wp/Wnratio a new variable . Obtain voltage transfer characteristic (VTC) of
the inverter circuit for =0.1, 0.2, 0.5, 1, 2, 5, and 10. Extract VM for each VTC. Plot
VM against . Explain your observation.
 alpha Vm(in mV)
0.1 331
0.2 359
0.5 418
1 457
2 524
5 578
10 634
With increase in alpha value the Vm value increases, because of greater
pull-up strength of PFET (more current), it dominates for longer range of
Vin. Only after reaching sufficient high value of Vin NFET starts
conducting.
3. From the results in part (1), plot the gain (∂V out/∂Vin) versus Vin. Mark on the plot (i)
maximum gain (absolute value), (ii) V iL and (iii) ViH. Create a table and summarize
these parameters.
 Max gain 4.2529
VIL 411.556 mV
VIH 689 mV

4. Reduce the supply voltage of the inverter from 1.0 V to 0.2 V in steps of 0.2 V.
Obtain VTC for each supply voltage. Overlay all VTC curves in one plot. Explain your
observations.

With decrease in VDD value the VTC curve shifts downward. The VM values follow linear
dependency with VDD(0.5 V/V). Only the gain of the inverter decreases as we move to very
low VDD value (0.2) in the plot.

Question B. Hand calculation.

5. Obtain the general expression for the gain of a CMOS inverter at the switching
threshold point (VM) assuming that the pFET and nFET behave as long-channel
transistors.
 6. Use the parameters in Table 1 and design the inverter such that VM=0.5 VDD. Report
the gain of the inverter at VM. Assume that VDD=1.0 V.

Question C.Handcalculation.
For the circuit in Fig. 1, qualitatively plot VTC (i.e., Vout versus Vin). Assume that VDD is bigger
than the threshold voltages of both nFET and pFET. Explain your analysis.

Fig. 1. New logic circuit in Question C.