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  • Ques1-A) Path - B) Snapshot of The Schematic

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    Jitendra Singh
    18 views8 pages
    This document contains three questions regarding op-amp circuit design and analysis. Question 1 provides the schematic, component table, gain and phase plot, and descriptions of unity gain frequency and input common mode range. Question 2 gives another schematic, component table, hysteresis plot, and transient response. Question 3 details a wide-swing output stage schematic shown across two images, extensive component table, descriptions of sweeping the input voltage and measuring gain at different common mode voltages, and transient response.

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    Original Title

    Mixed_Signal_Circuit_Assignment2

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    This document contains three questions regarding op-amp circuit design and analysis. Question 1 provides the schematic, component table, gain and phase plot, and descriptions of unity gain frequency and input common mode range. Question 2 gives another schematic, component table, hysteresis plot, and transient response. Question 3 details a wide-swing output stage schematic shown across two images, extensive component table, descriptions of sweeping the input voltage and measuring gain at different common mode voltages, and transient response.

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    © All Rights Reserved
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    18 views8 pages

    Ques1-A) Path - B) Snapshot of The Schematic

    Uploaded by

    Jitendra Singh
    This document contains three questions regarding op-amp circuit design and analysis. Question 1 provides the schematic, component table, gain and phase plot, and descriptions of unity gain frequency and input common mode range. Question 2 gives another schematic, component table, hysteresis plot, and transient response. Question 3 details a wide-swing output stage schematic shown across two images, extensive component table, descriptions of sweeping the input voltage and measuring gain at different common mode voltages, and transient response.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 8

    Ques1-

    a) Path-

    b) Snapshot of the schematic-

    c) Table-
    TYPE Aspect Ratio/ Values

    M0 PMOS (w/l)=(240nm/500nm), nf=40

    M9 PMOS (w/l)=(240nm/500nm), nf=40

    M10 PMOS (w/l)=(240nm/500nm), nf=40

    M12 PMOS (w/l)=(240nm/500nm), nf=40

    M7 NMOS (w/l)=(240nm/180nm), nf=2

    M8 NMOS (w/l)=(240nm/180nm), nf=2

    M1 NMOS (w/l)=(240nm/500nm), nf=1

    M11 NMOS (w/l)=(240nm/500nm), nf=1

    d) Gain and Phase Plot


    UNITY GAIN FREQUENCY= 100MHZ

    e) Transient Response

    f) ICMR
    Vmin= 1V
    Vmax= Vd + Vthn= 1.6V
    1 < Vcm <1.6

    Ques2:
    a) Path-
    /user_data1/common/group3/umc180_oa/16IE10034/ASSIGNMENT2_Q2/

    b) Screenshot of the schematic-

    c) Table-

    TYPE Aspect Ratio/ Values

    M0 PMOS (w/l)=(240nm/500nm), nf=40

    M9 PMOS (w/l)=(240nm/500nm), nf=40

    M10 PMOS (w/l)=(240nm/500nm), nf=40

    M12 PMOS (w/l)=(240nm/500nm), nf=40

    M7 NMOS (w/l)=(240nm/180nm), nf=2

    M8 NMOS (w/l)=(240nm/180nm), nf=2

    M1 NMOS (w/l)=(240nm/500nm), nf=1

    M11 NMOS (w/l)=(240nm/500nm), nf=1

    M12 PMOS (w/l)=(240nm/500nm), nf=70

    M13 PMOS (w/l)=(240nm/500nm), nf=70


    d) Hysteresis Plot

    e) Transient Response-

    Ques3:(NOTE: I am using wide-swing at the output stage to increase the gain, due to
    which not clear snapshot, 2 snapshot as left and right half)
    a) Path-
    /user_data1/common/group3/umc180_oa/16IE10034/ASSIGNMENT2_Q3/
    b) Snapshot of the schematic-

    Left Half-

    Right Half-

    e) Table-

    TYPE Aspect Ratio/ Values

    M6 NMOS (w/l)=(240nm/240nm), nf=26


    M7 NMOS (w/l)=(240nm/240nm), nf=26

    M8 PMOS (w/l)=(240nm/180nm), nf=50

    M9 PMOS (w/l)=(240nm/180nm), nf=50

    M1 PMOS (w/l)=(240nm/180nm), nf=50

    M2 PMOS (w/l)=(240nm/180nm), nf=50

    M3 PMOS (w/l)=(240nm/180nm), nf=50

    M4 PMOS (w/l)=(240nm/180nm), nf=50

    M0 NMOS (w/l)=(240nm/180nm), nf=2

    M5 NMOS (w/l)=(240nm/180nm), nf=2

    M10 NMOS (w/l)=(240nm/180nm), nf=2

    M11 NMOS (w/l)=(240nm/180nm), nf=2

    M12 NMOS (w/l)=(240nm/180nm), nf=2

    M13 NMOS (w/l)=(240nm/180nm), nf=2

    M14 NMOS (w/l)=(240nm/180nm), nf=2

    M15 NMOS (w/l)=(240nm/180nm), nf=2

    M16 NMOS (w/l)=(240nm/180nm), nf=2

    M19 NMOS (w/l)=(240nm/180nm), nf=2

    M20 PMOS (w/l)=(240nm/180nm), nf=50

    M21 PMOS (w/l)=(240nm/180nm), nf=50

    M22 NMOS (w/l)=(240nm/500nm), nf=16

    M23 NMOS (w/l)=(240nm/500nm), nf=32

    M24 PMOS (w/l)=(480nm/500nm), nf=400

    M25 PMOS (w/l)=(480nm/500nm), nf=120

    M28 PMOS (w/l)=(240nm/480nm), nf=64

    M29 PMOS (w/l)=(240nm/480nm), nf=80

    M27 NMOS (w/l)=(240nm/480nm), nf=24

    M26 NMOS (w/l)=(240nm/480nm), nf=4

    d) Sweep Vin,cm from 0 to VDD


    e) DC_Gain Vcm= 500m

    Unity gain frequency= 100MHz

    DC_Gain Vcm= 900m


    Unity gain frequency= 100Mhz

    DC_Gain Vcm= 1.3V

    Unity gain frequency= 100Mhz

    f) Transient Response

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