The XOR Gate

A Laboratory Report Presented to

Prof. Ramon Cristopher Calam
Faculty DEET
College of Engineering and Technology, MSU-IIT

In Partial Fulfillment for the course

ECE 180.1 – Logic Circuits and Switching Theory

JHOMAR C. MARI
Introduction
The XOR gate (exclusive OR) is a logic gate that produces a logic HI (1) output only
when both input are not on the same logic. This gate offers a very useful function in
digital electronics. It is used to implement various logical applications such as the ifelse
condition. The symbol, truth table, and the pin configuration of the XOR gate IC
are illustrated in Figure 6‐1.

Figure 5‐1. The XOR gate (a) logic symbol, (b) truth table.

Objectives
To demonstrate and simulate the basic function of the XOR gate and its applications.

Materials
• Multisim Live
• DC Voltage Source
• XOR gate
• Resistor (500Ω)
• LED
• Digital Switch
Procedures
1. Construct the circuit shown in Figure 6‐2, MultisimLive. Use a 3.3 V to simulate a
Logic “1” and 0 V to simulate a Logic “0”. The LED in MultisimLive has a forward
voltage of 0.7 V, use a 500 Ohm series resistor.

2. Set the logic switches to LO or logic “0” position. What is the display of the LED
indicators?
All LEDs are turned off.

3. Verify the function of XOR gate based on the truth table. List the possible output of
the given table below.

The table is located in the results and discussions section.

4. What are the required input of D0(S1) and D1(S2) in order to produce logic LO (0) output
in L3?
To produce a logic 0 output in L3, it needs both S1 and S2 to be the same state. If
S1 and S2 are not in the same logic state then L3 will be on.

5. What are the required input of D0 and D1 in order to produce logic HI (1) output in
L3?
To produce a logic 1 output in L3, it only needs a single ‘high’ state from either
S1 or S2. If both S1 and S2 are ‘high’ or both are ‘low’ then L3 is off.

6. The second group of gates is composed of gates C & D. List in the table the
corresponding output of the given input combination in the table below.

The table is located in the results and discussions section.

7. What are the required input of D2(S3) to D4(S5) in order to produce logic LO in L5?
The logic state of L5 is dependent on 3 switches: S3, S4, and S5. For L5 to produce a
logic 0 output it needs an even number of ‘high’ states from either 2 of the 3 switches. If an
odd number of ‘high’ states are present then the L5 is turned off. Meanwhile if all switches
are
‘low’ then L5 is also turned off.

8. What are the required input of D2(S3) to D5(S6) in order to produce logic HI (1) in L6?
For L6 to be ‘high’ it needs an odd number of switches to be ‘high’ otherwise L6
would
not turn on.

9. Based from the above table, what did you observe from the result data?
Based from the table, we can observe that L4 only turns on when either S3 or S4 is
‘high’ if both S3 and S4 are on the same logic levels then L4 is off. L5 is dependent on
switches S3, S4, and S5. If an odd number of switches are ‘high’ then L5 is ‘high’ otherwise
L5 is off. The same statement can be said for S6 with the only exception that it also includes
S6 as one of its inputs. If an odd number of switches are ‘high’ L6 is ‘high’ otherwise L6
would be off.
Results and Discussions

INPUT OUTPUT
S1 S2 L1 L2 L3
0 0 0V 0V 0V
0 1 0V 0.7 V 0.7 V
1 0 0.7 V 0V 0.7 V
1 1 0.7 V 0.7 V 0V
Figure 6.3 – Procedure 3 schematics and logic table
 INPUT OUTPUT
S3 S4 S5 S6 L4 L5 L6
0 0 0 0 0V 0V 0V
0 0 0 1 0V 0V 0.7 V
0 0 1 0 0V 0.7 V 0.7 V
0 0 1 1 0V 0.7 V 0V
0 1 0 0 0.7 V 0.7 V 0.7 V
0 1 0 1 0.7 V 0.7 V 0V
0 1 1 0 0.7 V 0V 0V
1 0 0 0 0.7 V 0.7 V 0.7 V
1 0 0 1 0.7 V 0.7 V 0V
1 0 1 0 0.7 V 0V 0V
1 0 1 1 0.7 V 0V 0.7 V
1 1 0 0 0V 0V 0V
1 1 0 1 0V 0V 0.7 V
1 1 1 0 0V 0.7 V 0.7 V
1 1 1 1 0V 0.7 V 0V
Figure 6.4 – Procedure 6 schematics and logic table

Observation
Summary and Conclusion
The XOR gate is quite unique because it only outputs a ‘high’ state whenever an odd
number of switches are ‘high’. If ever an even number of ‘high’ switches are at the input
terminals of the XOR gate, the output would be ‘low’. And also like the OR gate, the XOR gate
outputs a ‘low’ state if all inputs are ‘low’.