Acer Predator Helios 300 N17C3 Compal LA-F991P DH53F Rev 1.C Схема

A B C D E
1 1
Compal Confidential 2
DH53F MB Schematic Document

LA-F991P
3 3
Rev : 1.C
2018.02.13
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DH53F M/B LA-F991P 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 13, 2018 Sheet 1 of 73
A B C D E
A B C D E
HDMI Conn. eDP

1
Fan Control*2 1
page 50
Interleaved Memory
page 38
page 37 Memory BUS 260 pin DDR4-SO-DIMM X1
BANK 0, 1, 2, 3 page 23
eDP
Dual Channel
CoffeeLake H PROCESSOR
1.2V DDR4 2400/2666 260pin DDR4-SO-DIMM X1
BGA1440 BANK 4, 5, 6, 7 page 24
Nvidia N17E-G1
PEG x16
8GT/s
(42X28) (CFL-H_6+2)
HDMI x 4 lanes
with gDDR5 x6
page 25~36 Processor page 07~14
2 X4 DMI USB 3.0 USB 3.0 x2 CMOS 2

page 41 page 39
NGFF conn x1 Type-C Camera
WLAN PCIE 2.0 PCIE 3.0 x4 USB (port 1) USB (port 2) USB (port 5)
USB port 7 5GT/s 8GT/s
Port 9-12
port 15 Flexible IO
page 40 page 38 Cannonlake PCH - H USBx8
Finger_Print
PCIE 2.0 SATA3.0 FCBGA(25X24) USB (port 8)
5GT/s 6.0 Gb/s
port 14 port 4 page 50
48MHz page 46 page 44,45 page 37

LAN(GbE) SATA Re-Driver
Realtek 8411H PARADE PS8527 874pin FCBGA HD Audio 3.3V 24MHz
page 15~22
Card Reader RJ45 conn. SATA HDD Conn. HDA Codec

LPC/eSPI BUS ALC255
page 42
3 3
CLK=24MHz
page 32. ENE

page 47 KB9022/9032 TPM
page 43 page 49
Int. Speaker Int. DMIC UAJ
SPI
RTC CKT. Sub Board on Sub/B on Sub/B
page 42 page 48 page 48
page 21
LS-E921P Touch Pad Int.KBD
PS2 / I2C
HS/B page 48 SPI ROM x1
Power On/Off CKT.
page 17
page 50
LS-F992P
page 49 page 49
USB2/B page 48
DC/DC Interface CKT.

page 51
4 4
Power Circuit DC/DC
page 52~69
Security Classification Compal Secret Data Compal Electronics, Inc.

2017/07/20 2018/07/20 Title
Issued Date Deciphered Date Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
A B C D E
A B C D E
Board ID Table for AD channel Power State BOARD ID Table

Vcc 3.3V +/- 5% SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock Board ID PCB Revision
Ra 100K +/- 5%
0 0.1 / 28P
Board ID Rb V BID min V BID typ V BID max EC AD S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
1 0.2 / 28P
0 0 0.000 V 0.300 V 0x00 - 0x13 S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF 2 1.0 / 28P
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E
3 1.C / 28P
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
10 0.1 / 32P
1 3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF 11 0.2 / 32P
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A 12 1.0 / 32P
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 BOM Structure Table 13 1.C / 32P
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64 BOM Option Table Voltage Rails
8 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76 Item BOM Structure
Power Plane Description S0 S3 S4 S5
9 100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87 Unpop @ +RTCVCC RTC Battery Power ON ON ON
ON
10 130K +/- 1% 1.849 V 1.865 V 1.881 V 0x88 - 0x96 Connector CONN@ +19V_VIN Adapter power supply N/A N/A N/A
N/A
11 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 UMA only UMA@ +12.6V_BATT Battery power supply N/A N/A N/A N/A
12 200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF CMC CMC@ +19VB AC or battery power rail for power circuit. N/A N/A N/A N/A
13 240K +/- 1% 2.316 V 2.329 V 2.343 V 0xB0 - 0xB7 dGPU VGA@ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON
14 270K +/- 1% 2.395 V 2.408 V 2.421 V 0xB8 - 0xBF DIS only DIS@ +5VALW +5V Always power rail ON ON ON ON
15 330K +/- 1% 2.521 V 2.533 V 2.544 V 0xC0 - 0xC9 TPM TPM@ +3VALW System +3VALW always on power rail ON*
ON ON ON
16 430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4 For Acer IOAC IOAC@ +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON
17 560K +/- 1% 2.791 V 2.800 V 2.808 V 0xD5 - 0xDD No Acer IOAC NIOAC@ +3VALW_PCH_PRIM +3VALW power for PCH power rails ON ON ON ON*
18 750K +/- 1% 2.905 V 2.912 V 2.919 V 0xDE - 0xF0 28P keyboard connector 28P@ +3VALW_SPI +3VALW_PRIM supply for the SPI IO ON ON ON ON
19 NC 3.000 V 3.000 V 0xF1 - 0xFF 32P keyboard connector 32P@ +1.05VALW +1.05V Always power rail ON ON ON ON
Finger Print FP@ +1.2V_VDDQ DDR4 +1.2V power rail
2 ON ON OFF OFF 2
Finger Print for ESD FPESD@ +1.05V_VCCST Sustain voltage for processor in Standby modes
I2C Address Table PBA PBA@ +5VS System +5V power rail
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
Address(8bit)
Thermal sensor TMS@ +3VS System +3V power rail ON OFF OFF OFF
BUS Device Address(7 bit) LAN LDO mode LDO@
Write Read +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF
LAN Switch mode SWR@ +0.6VS_VTT DDR +0.6VS power rail for DDR terminator .
I2C_0 (+3VS) Touch Panel reserved ON OFF OFF OFF
G-Sensor GSEN@ +VCC_CORE Core voltage for CPU
I2C_1 (+3VS) TM-P2969-001 (Touch Pad) ON OFF OFF OFF
EMI requirement EMI@ +VCC_GT Sliced graphics power rail
SB8787-1200 (Touch Pad) ON OFF OFF OFF
EMI require reserve @EMI@ +VCCIO CPU IO +0.95VS power rail
DIMM1 ON OFF OFF OFF
PCH_SMBCLK ESD requirement ESD@ +VCC_SA System Agent power rail
(+3VS) DIMM2 ON OFF OFF OFF
EMI require reserve @ESD@ +1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails)
LIS3DHTR(G-sensor) 0x30 ON OFF OFF OFF
CNVi CNVI@ +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6
N17E-G1 (VGA) 0x9E ON OFF OFF OFF
PCH_SML1CLK UART debug UART@ +VGA_CORE Core voltage for VGA (merge core & core_s)
(+3VS) EC ON OFF OFF OFF
Codec ALC255 255@ +1.35VSDGPU +1.35VS power rail for GPU
CC controller 179F ON OFF OFF OFF
Codec ALC256 256@ +1.0VSDGPU +1.0VS power rail for GPU
TMS ON OFF OFF OFF
Codec ALC256 for ESD 256ESD@ +1.8VALW System +1.8VALW always on power rail ON*
ON ON ON
Codec ALC256 for EMI 256EMI@
EC_SMB_CK1 BQ24780 (Charger IC) 0x12
(+3VLP) G-PAK for GPU sequence GPK@
BATTERY PACK 0x16
3 DIS for GPU sequence NGPK@ 3
W/ SATA re-driver SATARD@

W/O SATA re-driver NORD@ Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
PCH PCH@
CPU i5@/i7@
BOM table
43 Level Description BOM Structure
431AB2BOL05~08
431AB2BOL53_54
431AB1BOL67
X4EAB2BO001
4
X4EAB2BO051 4
X76730BOL56 ALT. GROUP PARTS N17E6G SAM 256M32 DH7VF

X76730BOL57 ALT. GROUP PARTS N17E6G HYN 256M32 DH7VF
X76730BOL58 ALT. GROUP PARTS N17E6G MIC 256M32 DH7VF
Issued Date 2017/07/20 Deciphered Date 2018/07/20 Title
Notes List
A B C D E
5 4 3 2 1
EN:DGPU_PWR_EN
UG27 +1.8VSDGPU_AON
DC_IN GPU
PL101 +1.8VSDGPU_MAIN
PJP101
+19V_VIN EN:1.8VSDGPU_MAIN_EN
GPU
AC CONN.
EN : 1VSDGPU_EN +1.8VS
+12.6V_BATT+ +1.8VDDA
+12.6V_BATT +1.0VSDGPUP +1.0VSDGPU UQ2 RA3
BATTERY PU1801 PJ1802 GPU CODEC
PL201,PL202
PJP201 +3.3V_CC
RS1 DIMM1 +1.8VALW_PRIM
D +1.8VALW D
IMVP8 PJ7107 RH100
+VCC_CORE PU7102 PJ7103 +2.5V DIMM2
PCH
PU8102 CPU DDR4
PU301 +19VB PU8103 PL8101,PL8306,PL8305,PL8106 +1.8VALWP +1.8V_PHVLDO
RH100
PU8104 PU7105 PCH
PU8105 +3VS
EN:VR_ON UQ1 JPQ1
UO1 SATA Re-driver
PQ8105 R19 +3VALW_TPM U5
CHARGER +VCC_GT TPM RZ1 G-SENSOR
+19VB
PU8106 PL8107 CPU +3VS_WLAN
EN:DRON UM1 JNGFF1 WLAN CARD (IOAC) UF1 THERMAL SENSOR
+3V_LAN
UL1 UL2 LAN RM11 +3VS_WLAN JNGFF1
WLAN
PQ8301 +3VALW_DSW
PL8301 +VCC_SA CPU RH99 PCH RM1 +3VS_SSD_NGFF JSSD1
+19VB SSD
EN:DRON
RH97 +3VALW_PCH_PRIM RH98 +3VALW_SPI UH3 +3VS_TPM
SPI R20 U5 TPM
RH101 +3VALW_HDA +TS_PWR
EN:3V_EN +3VALW
PCH RX6 JEDP1
TS
PJ401
PU401 UK1 +3V_PTP JTP1
+19VB TP UX1 +LCDVDD JEDP1
C
EC,LID +3VLP PANEL C
RK14 1.8VSDGPU_MAIN_EN
+1.2V_VDDQ_CPU UG20 +3VSDGPU GPU
+1.2V
JPC1,C2 CPU
+1.2V_VDDQ UK2 JEP1 +3VS_DVDDIO
EN:SYSON PJ501 +FP_VCC FP RA2 +3VS_DVDDIO CODEC
JDIMM1,2
+19VB DIMM +3VS_DVDD
+0.6V_DDRB_VREFCA RA4
PU501 RD19,21,20 +3VS_DVDD CODEC
EN:SM_PG_CTRL +0.6V_B_VREFDQ CPU +3VS_DIMMA
+0.6VSP +0.6VS_VTT
PJ502 +1.05VALW_PCH_PRIM
RH92 PCH
RH93 +1.05VALW _VCCMPHY PCH
PU601 +1.05VALWP +1.05VALW
+19VB PJ601 RH94 +1.05VALW_PCH PCH
EN:+3VALW
+1.05VALW_VCCAZPLL
RH102
+1.05VALW_VCCAMPHYPLL
PCH
RH103
+1.05VALW _XTAL
PCH
RH105
+1.0VS_VCCIOP
PCH
PU7201 PJ7201 +VCCIO CPU UQ2 RQ5 +1.05V_VCCST
+19VB
EN:SUSP# CPU
RK15 +1.05VS_VCCSTG
UC4 RQ6
B B
+5V_CC
US2
US11 +USB3_VCCC JTYPEC1

Type C Conn.
US12 JUSB1 +USB_VCCA USB3.0 Conn.
+5VALWP
PU402 PJ402 +5VALW +5VS
+19VB UQ1 JPQ2 +VCC_FAN1
RF4 FAN1
JIO2,3 RF6 +VCC_FAN2 FAN2

USB/B FPC BTB CONN +VDDA
JPA1 UA1 CODEC
+19VB EN:NVVDD1_EN GPU
PL1303 +19VB_GPU PR1302 +19VB_NVVDD +NVVDD1 U4 +5VS_BL JBL1 KB BackLight
PR1301 PU1302 PL1351
PL1304 +5VS_HDD
UO2 JHDD1
HDD
EN:NVVDD2_EN UY2 +HDMI_5V_OUT JHDMI1
PR1402 +NVVDD2 HDMI
+19VB_NVVDDS PL1401
PQ1401 GPU +TS_PWR
RX7 JEDP1
TP
A A
EN:1.35VSDGPU_EN GPU
PJ1701 +1.35VSDGPU
+19VB_1.35VSDGPUP
PQ1701
+19VB
LX1 +INVPWR_B+
JEDP1
PANEL
2017/07/20
Compal Secret Data
2018/07/20 Title
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
5 4 3 2 1
5 4 3 2 1
DH53F_EVT Power Sequence

BIOS : 0.05 Power On S3 S3 Resume Power Off
AC mode
Plug in
+3VLP
D +3VLP D
EC_ON
EC_ON
+5VALW
→
+5VALW
ON/OFFBTN#
ON/OFFBTN#
→ →
+3VALW 90.77ms 8.969s +3VALW
→ →
+1.8VALW 92.67ms 8.97s +1.8VALW
→ →
+1.05ALW 93.73ms 8.97S +1.05ALW
→ →
EC_RSMRST# 21.45ms 8.497S EC_RSMRST#
→ ←
20ms
→
PBTN_OUT# ← → 8.497S PBTN_OUT#
130.8ms
→ →
17.32ms 439.9us PM_SLP_S4#
PM_SLP_S4#
C → → C
17.36ms 291us → 291.9us PM_SLP_S3#
PM_SLP_S3#
→ 20.16ms → 4.993us SYSON

SYSON
→ →
302.5us 76.22us +1.05V_VCCST
+1.05V_VCCST
→
752.8us → 496.3us +1.2V_VDDQ
+1.2V_VDDQ
→
985us → 1.587ms +2.5V
+2.5V
→
9.797ms → 13.77us → 32.21ms → 13.75us SUSP
SUSP#
→ 8.607us → 44.84us → 8.64us → 53.92us +1.05VS_VCCSTG
+1.05VS_VCCSTG
→ 682.5us → 637.6us → 679.3us → 646.6us +VCCIO
+VCCIO
→ 926us → 516.2us → 929.5us → 659.4us +5VS
+5VS
→ 670.8us → 5.065ms → 677.4us → 4.683ms +3VS
+3VS
→ 438us → 4.447ms → 419.9us → 2.786ms +1.8VS
+1.8VS
→ 20.55ms → 9.382us → 19.97ms → 9.275us EC_VCCST_PG
B B
EC_VCCST_PG
→ 20.5ms → 9.78us → 20.38ms → 9.764us SM_PG_CTRL
SM_PG_CTRL
→ 4us → 2.089ms → 4us → 724us +0.6VS_VTT
+0.6VS_VTT
→ 20.53ms → 28.72us → 20.41ms → 28.57us VR_ON
VR_ON
→ →
1.773ms → 43.75us → 1.776ms 46.27us +VCC_SA
+VCCS_A
→ →
10.15ms → 74.13us → 9.604ms 74.07us PCH_PWROK
PCH_PWROK
→ →
120.9ms → 87.21us → 121.3ms 87.14us SYS_PWROK
SYS_PWROK
→
1.339ms → 1.614ms PLT_RST#
PLT_RST#
→ → →
136.8ms 83.73us → 139.6ms 84.98us +VCC_CORE
+VCC_CORE
→ → →
6.655s 560.8ms → 1.419s 1.837s +VCC_GT
+VCC_GT
A A

Power Map
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
+3VALW_PCH_PRIM
+3VS
2.2K +3VS 2.2K
PCH_SMBCLK D_CK_SCLK
2N7002DW
PCH_SMBDATA D_CK_SDATA SO-DIMM A & B
PCH_SML0CLK 499
G-Sensor
+3VALW_PCH_PRIM 2.2K
D
PCH_SML0DATA 499 D
CannonLake-H 2.2K 1.8K 1.8K
+1.8VSDGPU_AON
PCH 2.2K
+3VALW_PCH_PRIM +1.8VSDGPU_AON
+3VSDGPU
2.2K +1.8VSDGPU_MAIN 1.8K 1.8K
+1.8VSDGPU_MAIN
PCH_SML1CLK VGA_SMB_CK2 I2CC_SCL_R I2CC_SCL
PJT138KA PJT138KA
PCH_SML1DATA VGA_SMB_DA2 N17E-G1 I2CC_SDA_R I2CC_SCL Current Sensor
4.7K
2.2K
+3VLP_EC +3.3V_CC
2.2K 4.7K
+3.3V_CC
EC_SMB_CK1 100 ohm EC_SMB_CK1-1
BATTERY
2N7002DW
EC_SMB_DA1 100 ohm EC_SMB_DA1-1 CONN USB CC EJ179F
KB9022 0 ohm EC_SMB_CK1_CHGR 2.2K

0 ohm EC_SMB_DA1_CHGR Charger
+3VS
+3VS 2.2K
2N7002DW
C THERMAL SENSOR C
B B
A A

N17E-GDDR5_D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.A
5 4 3 2 1
A B C D E
CO-LAY FOR VGA OUTPUT
RG203 1 DIS@ 2 0_0201_5% GPU_EDP_TXP0_R

<27> GPU_EDP_TXP0 TC21 @
RG204 1 DIS@ 2 0_0201_5% GPU_EDP_TXN0_R
<27> GPU_EDP_TXN0 TC22 @
1 RG210 1 DIS@ 2 0_0201_5% GPU_EDP_TXN3_R 1
RG211 1 DIS@ 2 0_0201_5% GPU_EDP_AUXP_R

<27> GPU_EDP_AUXP TC29 @
RG212 1 DIS@ 2 0_0201_5% GPU_EDP_AUXN_R
<27> GPU_EDP_AUXN TC30 @
CFL-H
UC1D
K36 D29 EDP_TXP0

DDI1_TXP_0 EDP_TXP_0 EDP_TXN0 EDP_TXP0 <37>
K37 E29
DDI1_TXN_0 EDP_TXN_0 EDP_TXP1 EDP_TXN0 <37>
J35 F28
J34 E28
DDI1_TXN_1 EDP_TXN_1 EDP_TXP2 EDP_TXN1 <37>
H37 A29
DDI1_TXP_2 EDP_TXP_2 EDP_TXP2 <37>
H36
DDI1_TXN_2 EDP_TXN_2
B29 EDP_TXN2
EDP_TXP3 EDP_TXN2 <37>
eDP
J37 C28
J38 B28
DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <37>
2 D27 C26 EDP_AUXP 2
DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <37>
E27 B26 EDP_AUXN <37>
DDI1_AUXN EDP_AUXN
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 +VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL
ZZZ DDI2_TXN_1
F34
F35 DDI2_TXP_2 D37 DP_RCOMP RC1 1 2 24.9_0402_1%
E37 DDI2_TXN_2 DISP_RCOMP
E36 DDI2_TXP_3 Trace Width/Space: 15 mil/ 20 mil
DDI2_TXN_3 Max Trace Length: 600 mil
PCB@ DAZ29000103 F26

E26 DDI2_AUXP
PCB DH53F LA-F991P LS-F992P/E921P DDI2_AUXN
C34
D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27 CPU_DISPA_BCLK_R
PROC_AUDIO_CLK CPU_DISPA_SDO_R CPU_DISPA_BCLK_R <19>
A27 G25 CPU_DISPA_SDO_R <19>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 CPU_DISPA_SDI RC2 2 1 20_0402_5% CPU_DISPA_SDI_R
DDI3_AUXN 4 ofPROC_AUDIO_SDO
13 CPU_DISPA_SDI_R <19>
3 CFL-H_BGA1440 3
Coffee Lake-H CPU SKU

UC1
UC1
CFL-H_BGA1440
CFL-H_BGA1440
S IC CL8068403373522 SR3Z0 U0 2.3G ABO!
S IC CL8068403359524 SR3YY U0 2.2G ABO!
SA0000BPJ40
SA0000BPZ40
i5@
i7@
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
CFL-H(1/8)DDI/eDP
A B C D E
A B C D E
CHANNEL-A
Interleaved Memory
UC1A
CFL-H
DDR CHANNEL A
1 <23> DDR_A_D[0..63] 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#0 DDR_A_CLK0 <23>
BT6 AG2 DDR_A_CLK#0 <23>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <23>
BR3 AK1 DDR_A_CLK#1 <23>
DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <23>
BL2 AT2 DDR_A_CKE1 <23>
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <23>
BK2 AE2 DDR_A_CS#1 <23>
DDR_A_D16 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <23>
BG2 AE4 DDR_A_ODT1 <23>
DDR_A_D21 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23>
BD1 AH1 DDR_A_BA1 <23>
DDR_A_D26 BC4 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 AU1 DDR_A_BG0
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23>
2 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14_W E# DDR_A_MA16_RAS# <23>
BD4 AG4 DDR_A_MA14_W E# <23>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_A_MA15_CAS#
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <23>
BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <23>
AB2 AP4 DDR_A_MA1 <23>
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2
AA5 AP5 DDR_A_MA3 <23>
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4
DDR_A_D37 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR_A_MA5 DDR_A_MA4 <23>
AB4 AP1 DDR_A_MA5 <23>
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6
DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA7 DDR_A_MA6 <23>
AA1 AN1 DDR_A_MA7 <23>
DDR_A_D40 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8
V2 AT4 DDR_A_MA9 <23>
DDR_A_D42 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10
U2 AN2 DDR_A_MA11 <23>
DDR_A_D44 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12
V4 AE3 DDR_A_MA13 <23>
DDR_A_D46 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1
DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <23>
U4 AU3 DDR_A_ACT# <23>
DDR_A_D48 R2 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT#
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <23>
R4 AU5 DDR_A_ALERT# <23>
DDR_A_D51 P4 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT#
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR_A_D54 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#1 DDR_A_DQS#0 <23>
R1 BL3 DDR_A_DQS#1 <23>
DDR_A_D55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2
3 DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#3 DDR_A_DQS#2 <23> 3
M4 BD3 DDR_A_DQS#3 <23>
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4
L4 U3 DDR_A_DQS#5 <23>
DDR_A_D59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6
M5 L3 DDR_A_DQS#7 <23>
DDR_A_D61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS1 DDR_A_DQS0 <23>
L1 BK3 DDR_A_DQS1 <23>
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS3 DDR_A_DQS2 <23>
LP3/DDR4 BC3 DDR_A_DQS3 <23>
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_A_DQS4
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS5 DDR_A_DQS4 <23>
BA1 V3 DDR_A_DQS5 <23>
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_A_DQS6
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS7 DDR_A_DQS6 <23>
AY5 M3 DDR_A_DQS7 <23>
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 For ECC DIMM
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440
@
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
CFL-H(2/8)DIMMA
A B C D E
A B C D E
CHANNEL-B
Interleaved Memory
UC1B
CFL-H
<24> DDR_B_D[0..63] DDR CHANNEL B

1 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#0 DDR_B_CLK0 <24>
BR11 AN9 DDR_B_CLK#0 <24>
DDR_B_D2 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1
DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK#1 DDR_B_CLK1 <24>
BR8 AM8 DDR_B_CLK#1 <24>
DDR_B_D4 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11
DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_B_D8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_B_D10 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <24>
BL8 AT10 DDR_B_CKE1 <24>
DDR_B_D11 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7
DDR_B_D12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_B_D13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <24>
BJ7 AE7 DDR_B_CS#1 <24>
DDR_B_D16 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10
DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_B_D18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <24>
BF11 AE8 DDR_B_ODT1 <24>
DDR_B_D21 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9
DDR_B_D22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS#
DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14_W E# DDR_B_MA16_RAS# <24>
BC11 AH11 DDR_B_MA14_W E# <24>
DDR_B_D26 BB8 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 AF8 DDR_B_MA15_CAS#
DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# <24>
2 BC8 2
DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <24>
BB10 AH9 DDR_B_BA1 <24>
DDR_B_D30 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9 DDR_B_BG0
DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
BB7
DDR_B_D32 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D33 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA1 DDR_B_MA0 <24>
AA10 AK6 DDR_B_MA1 <24>
DDR_B_D34 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
AC10 AL5 DDR_B_MA3 <24>
DDR_B_D36 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D37 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 DDR_B_MA5 DDR_B_MA4 <24>
AA8 AM6 DDR_B_MA5 <24>
DDR_B_D38 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA7 DDR_B_MA6 <24>
AC7 AN10 DDR_B_MA7 <24>
DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
W7 AR11 DDR_B_MA9 <24>
DDR_B_D42 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
V11 AN11 DDR_B_MA11 <24>
DDR_B_D44 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
W10 AF9 DDR_B_MA13 <24>
DDR_B_D46 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7 DDR_B_BG1
DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <24>
V8 AT9 DDR_B_ACT# <24>
DDR_B_D48 R11 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT#
DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PAR
DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_ALERT# DDR_B_PAR <24>
P7 AR8 DDR_B_ALERT# <24>
DDR_B_D51 R8 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT#
DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS#1 DDR_B_DQS#0 <24>
R7 BL9 DDR_B_DQS#1 <24>
3 DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_B_DQS#2 3
L11 BC9 DDR_B_DQS#3 <24>
DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#4
L7 W9 DDR_B_DQS#5 <24>
DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
L10 M9 DDR_B_DQS#7 <24>
DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS1 DDR_B_DQS0 <24>
L8 BJ9 DDR_B_DQS1 <24>
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_B_DQS2
DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS3 DDR_B_DQS2 <24>
AW11 LP3/DDR4 BB9 DDR_B_DQS3 <24>
AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS4
NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS5 DDR_B_DQS4 <24>
AY8 V9 DDR_B_DQS5 <24>
AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS7 DDR_B_DQS6 <24>
AY10 L9 DDR_B_DQS7 <24>
AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY7 NC/DDR1_ECC_5 AW9
AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9 For ECC DIMM
For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

+0.6V_VREFCA
RC4 1 2 75_0402_1% SM_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
RC5 1 2 100_0402_1% SM_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13 +0.6V_B_VREFDQ
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
Trace Width/Space: 15 mil/ 25 mil CFL-H_BGA1440
Max Trace Length: 500 mil
4 @ 4
2017/07/20
Compal Secret Data
2018/07/20 Title
CFL-H(3/8)DIMMB
A B C D E
A B C D E
PEG&DMI
To DGPU
1 To DGPU PEG Lane Reversed
1
PEG Lane Reversed CFL-H

UC1C
CC6 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 0.22U_0201_6.3V6K 2 1VGA@ CC7
<25> PEG_CRX_C_GTX_P15 PEG_CRX_GTX_N15 PEG_RXP_0 PEG_TXP_0 PEG_CTX_GRX_N15 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P15 <25>
<25> PEG_CRX_C_GTX_N15 CC8 VGA@ 1 2 0.22U_0201_6.3V6K D25 A25 2 1VGA@ CC9
PEG_RXN_0 PEG_TXN_0 PEG_CTX_C_GRX_N15 <25>
<25> PEG_CRX_C_GTX_N14 CC12 VGA@ 1 2 0.22U_0201_6.3V6K F24 C24 2 1VGA@ CC13
<25> PEG_CRX_C_GTX_P9 PEG_CRX_GTX_N9 PEG_RXP_6 PEG_TXP_6 PEG_CTX_GRX_N9 PEG_CTX_C_GRX_P9 <25>
<25> PEG_CRX_C_GTX_N9 CC27 VGA@ 1 2 0.22U_0201_6.3V6K D19 A19 0.22U_0201_6.3V6K 2 1VGA@ CC28
<25> PEG_CRX_C_GTX_N8 CC31 VGA@ 1 2 0.22U_0201_6.3V6K F18 C18 0.22U_0201_6.3V6K 2 1VGA@ CC32
CC33 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 0.22U_0201_6.3V6K 2 1VGA@ CC34
2
<25> PEG_CRX_C_GTX_N7 CC35 VGA@ 1 2 0.22U_0201_6.3V6K E17 B17 0.22U_0201_6.3V6K 2 1VGA@ CC36 2
CC37 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 0.22U_0201_6.3V6K 2 1VGA@ CC38
<25> PEG_CRX_C_GTX_N6 CC39 VGA@ 1 2 0.22U_0201_6.3V6K E16 B16 0.22U_0201_6.3V6K 2 1VGA@ CC40
+VCCIO
RC6 1 2 24.9_0402_1% PEG_RCOMP G2
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
3 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 3
<15> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <15>
<15> DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 <15>
DMI_RXN_0 DMI_TXN_0
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<15> DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1 <15>
DMI_RXN_1 DMI_TXN_1
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 To PCH
<15> DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2 <15>
DMI_RXN_2 DMI_TXN_2
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<15> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 <15>
<15> DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3 <15>
DMI_RXN_3 DMI_TXN_3
CFL-H_BGA1440
@
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
PEG/DMI
A B C D E
A B C D E
CFL-H
UC1E
PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

<16> PCH_CPU_BCLK_P PCH_CPU_BCLK_N BCLKP CFG_0
<16> PCH_CPU_BCLK_N A32 BN27 CFG2 RC8 1 2 1K_0402_5%
BCLKN CFG_1 BN26 CFG2 CFG4 RC9 1 2 1K_0402_5%
PCH_CPU_PCIBCLK_P D35 CFG_2 BN28 CFG5 RC10 1 @ 2 1K_0402_5%
<16> PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N PCI_BCLKP CFG_3
<16> PCH_CPU_PCIBCLK_N C36 BR20 CFG4 CFG6 RC11 1 @ 2 1K_0402_5%
PCI_BCLKN CFG_4 BM20 CFG5 CFG7 RC12 1 @ 2 1K_0402_5%
PCH_CPU_24M_CLK_P E31 CFG_5 BT20 CFG6
<16> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLK24P CFG_6
571391_CFL_H_PDG_Rev0p5 <16> PCH_CPU_24M_CLK_N D31 BP20 CFG7
CLK24N CFG_7 BR23
1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).
2. Route the Alert signal between the Clock and the Data signals. CFG_8 BR22
1 1
3. Place those resistors close CPU side. CFG_9 BT23 The CFG signals have a default value of '1' if not terminated on the board.
CFG_10 BT22 CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
CFG_11 BM19 * 1 = (Default) Normal Operation;
CFG_12 BR19 0 = Stall.
Sensitive CFG_13 BP19 CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
CPU_SVID_ALERT# BH31 CFG_14 BT19 1 = Normal operation
BH32 VIDALERT# CFG_15 * 0 = Lane numbers reversed.
<60,61> CPU_SVID_CLK_R CPU_SVID_DAT_R VIDSCK
BH29 BN23 CFG[4]: eDP enable:
H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 1 = Disabled.
PROCHOT# CFG_16 BP22 * 0 = Enabled.
DDR_PG_CTRL BT13 CFG_19 BN22 CFG[6:5]: PCI Express* Bifurcation:
DDR_VTT_CNTL CFG_18 00 = 1 x8, 2 x4 PCI Express*
01 = reserved
XDP_BPM#0 10 = 2 x8 PCI Express*
BR27 TC1 @ 11 = 1 x16 PCI Express*
BPM#_0 BT27 XDP_BPM#1 *
Sensitive BPM#_1 TC2 @
BM31 XDP_BPM#2 CFG[7]: PEG Training:
BPM#_2 TC3 @
EC_VCCST_PG H13 BT30 XDP_BPM#3 * 1 = (default) PEG Train immediately following RESET# de assertion.
VCCST_PWRGD BPM#_3 TC4 @ 0 = PEG Wait for BIOS for training.
H_CPUPW RGD BT31 *CFG Pin Use CMC debug on DDX03 R02 Schematic.
<19> H_CPUPW RGD H_PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
<18> H_PLTRST_CPU# BP35 BT28
H_PM_SYNC_R BM34 RESET# PROC_TDO BL32 CPU_XDP_TDI CPU_XDP_TDO <19>
<18> H_PM_SYNC_R H_PM_DOW N PM_SYNC PROC_TDI CPU_XDP_TMS CPU_XDP_TDI <19>
BP31 BP28
H_PECI PM_DOWN PROC_TMS CPU_XDP_TCK0 CPU_XDP_TMS <19>
BT34 BR28
<18,43> H_PECI H_THERMTRIP# PECI PROC_TCK CPU_XDP_TCK0 <19>
RC17 1 @ 2 0_0402_5% J31 To be confirm
<18> PCH_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
BP30
PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <22> XDP_PREQ#
@ TC5 SKTOCC# BR33 BL30 TC19 @
SKTOCC# PROC_PREQ# XDP_PRDY# XDP_PRDY# XDP_PREQ# <22>
PROC_SELECT# BN1 BP27 TC20 @
PROC_SELECT# PROC_PRDY# XDP_PRDY# <22>
2
should be unconnected on CFL processor CATERR# BM30 2
@ TC6
EDS1.2 8/21 CATERR# BT25 CFG_RCOMP 1 RC18 2 49.9_0402_1%
AT13 CFG_RCOMP
AW13 ZVM#
MSM# Trace Width/Space: 4 mil/ 12 mil
@ESD@ AU13 Max Trace Length: 600 mil
.1U_0402_16V7K 1 2 CC95 H_PECI AY13 RSVD1
RSVD2
@ESD@ 5 OF 13
.1U_0402_16V7K 1 2 CC65 H_CPUPW RGD +1.05VS_VCCSTG
CFL-H_BGA1440 Place to CPU side
ESD@ @
1000P_0402_50V7K 1 2 CC66 H_PROCHOT#_R RC76 2 CMC@ 1 51_0402_5% CPU_XDP_TMS
@ESD@ RC77 2 CMC@ 1 51_0402_5% CPU_XDP_TDI

.1U_0402_16V7K 1 2 CC67 H_THERMTRIP#
RC78 2 CMC@ 1 51_0402_5% CPU_XDP_TDO
ESD@
1000P_0402_50V7K 1 2 CC68 EC_VCCST_PG_R +3VS Place to CPU side
+1.2V_VDDQ
RC79 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0
1
Near CPU side RC23 RC80 2 @ 1 51_0402_5% PCH_JTAG_TCK1
CC69 PCH_JTAG_TCK1 <19>
follow 1050 Request UC3 330K_0402_5%
1 5 2 1 RC81 2 @ 1 51_0402_5% CPU_XDP_TRST#
8/21 NC VCC
2
+1.05V_VCCST DDR_PG_CTRL 2 .1U_0402_16V7K
RH1 1 2 1K_0402_5% H_THERMTRIP# A 4 SM_PG_CTRL
Y SM_PG_CTRL <56>
3
3 GND 3
PU 330K follow CRB
74AUP1G07GW _TSSOP5
8/21
+1.05VS_VCCSTG
1
RC21 SVID
1K_0402_5%
2
+1.05V_VCCST
RC14 1 2 499_0402_1% H_PROCHOT#_R
<43,54> H_PROCHOT#
+1.05V_VCCST
1
RC19 RC20
1
56_0402_1% 100_0402_1%
RC22
2
1K_0402_5%
2
RC13 1 2 220_0402_5% CPU_SVID_ALERT#

EC_VCCST_PG <60,61> CPU_SVID_ALERT#_R
RC15 1 2 60.4_0402_1%
<43,51> EC_VCCST_PG_R
4 CPU_SVID_DAT_R 4
H_PM_DOW N <60,61> CPU_SVID_DAT_R
RC16 1 2 20_0402_5%
<18> H_PM_DOW N_R
1
RH2
@ 13_0402_5%
2017/07/20
Compal Secret Data
2018/07/20 Title
CFL-H(5/8)CFG,SVID
2
A B C D E
A B C D E
GT
32000mA(Hexa Core GT2) +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE
+VCC_GT CFL-H +VCC_GT CFL-H UC1J
UC1K UC1I
AT14
VCCGT1 VCCGT80
BD35 AA13
VCC1 VCC64
AH13 128000mA(Hexa Core GT2) K14
VCC1 VCC64
W35
AT31 BD36 AA31 AH14 L13 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
1 1
AU14 VCCGT9 VCCGT88 BE38 AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 W13 VCC57
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
BB38 VCCGT62 VCCGT141 BL28 AG36 VCC62 W32 VCC62 10 OF 13
BC29 VCCGT63 VCCGT142 BL36 VCC63 VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15
3 VCCGT66 VCCGT145 @ 3
BC32 BM16 AG37 VCCSENSE
VCCGT67 VCCGT146 VCC_SENSE VCCSENSE <60>
BC35 BM17 9 OF 13 AG38 VSSSENSE
VCCGT68 VCCGT147 VSS_SENSE VSSSENSE <60>
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
BC38 VCCGT70 VCCGT149 BN15
VCCGT71 VCCGT150 @ 1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
BD13 BN16 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD14 VCCGT72 VCCGT151 BN17
BD32 VCCGT76 VCCGT155 BP15
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
VCCGT163 VCCGT168
AH37 VSSGT_SENSE
11 OF VSSGT_SENSE VSSGT_SENSE <60>
13 AH38 VCCGT_SENSE
VCCGT_SENSE VCCGT_SENSE <60>
CFL-H_BGA1440
@ 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
CFL-H(6/8)VCC_CORE/GT
A B C D E
A B C D E
+1.2V_VDDQ_CPU
Max: 3300mA
+VCC_SA CFL-H +1.2V_VDDQ_CPU +1.2V_VDDQ_CPU +1.2V_VDDQ +1.2V_VDDQ_CPU

UC1L 3.3A
@ JPC1
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+VCC_SA J30 AA6 1 2
K29 VCCSA1 VDDQ1 AE12 1 2
Max: 11100mA VCCSA2 VDDQ2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 AF5 JUMP_43X118
VCCSA3 VDDQ3
CC70
CC71
CC72
CC73
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
CC83
CC84
CC85
K31 AF6
K32 VCCSA4 VDDQ4 AG5 @ JPC2
K33 VCCSA5 VDDQ5 AG9 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
K34 VCCSA6 VDDQ6 AJ12 1 2
K35 VCCSA7 VDDQ7 AL11 JUMP_43X118
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13 PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12 +1.2V_VDDQ +1.2V_VCCPLL_OC
M33 VCCSA18 VDDQ18 K6 +VCCIO
M34 VCCSA19 VDDQ19 L12 RC24 1 @ 2 0_0402_5%
+VCC_IO M35 VCCSA20 VDDQ20 L6
Max: 6400mA VCCSA21 VDDQ21
1U_0201_6.3V6M
1U_0201_6.3V6M
M36 R6
VCCSA22 VDDQ22
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
T6 1 1
+VCCIO VDDQ23 W6 @
VDDQ24 1 1 1 1
CC86
CC87
Y12
VDDQ25
CC88
CC89
CC90
CC91
AG12
G15 VCCIO1 +1.2V_VCCPLL_OC 2 2
G17 VCCIO2 +1.2V_VCCPLL_OC 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +1.2V_VCCPLL_OC: 1uF * 2 +0.95VS_VCCIO: 10uF * 12 22uF * 4 2
H21 VCCIO10 VCCSTG2
VCCIO11 +1.05V_VCCSFR
PLACE CAP BACKSIDE
H26 G30
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 +1.05V_VCCST +1.05V_VCCSFR
J20 VCCIO17 M38 VCCSA_SENSE
VCCIO18 VCCSA_SENSE VSSSA_SENSE VCCSA_SENSE <61>
J21 M37 RC25 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSSSA_SENSE <61>
J26 150mA
VCCIO20 VCCIO_SENSE
1U_0201_6.3V6M
1U_0201_6.3V6M
J27 H14
VCCIO21 VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE <59>
J14 1 1
12 OF 13 VSSIO_SENSE VSSIO_SENSE <59>
CC92
CC93
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 2 2
@
2. Maintain 25-mil separation distance away from any other dynamic signals.
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1 571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
PLACE CAP BACKSIDE PLACE CAP BACKSIDE
+1.05VS_VCCSTG
3 3
1U_0201_6.3V6M
1
CC94
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
CFL-H(7/8)VCCSA/VCCIO/VDDQ
A B C D E
A B C D E
CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
VSS_3 VSS_84 VSS_165 VSS_246 VSS_328 VSS_412 Impedance Spectrum Tool Trigger @ TC7
IST_TRIG E3 RSVD_TP5
A18 AL14 AY34 BJ25 BP18 F21 @ TC8
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23 E1 IST_TRIG
VSS_5 VSS_86 VSS_167 VSS_248 VSS_330 VSS_414 @ TC9 RSVD_TP4
A22 AL34 BA10 BJ30 BP24 F25 @ TC10 D1
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP25 VSS_331 VSS_415 F27 RSVD_TP3
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 BR1 BK28
VSS_8 VSS_89 VSS_170 VSS_251 VSS_333 VSS_417 @ TC11 RSVD_TP1 RSVD11
1 A28 AL8 BA37 BJ33 BP29 F3 @ TC12 BT2 BJ28 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 <22> PCH_TRIGOUT_R CPU_TRIGOUT PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC26 1 2 30_0402_5% J23
VSS_29 VSS_110 VSS_191 VSS_272 VSS_354 VSS_438 <22> CPU_TRIGOUT_R PROC_TRIGOUT
AD12 AP9 BD10 BL35 BT29 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC13 @
AF2 AR36 BE4 BM25 C31 J32 C1 TC14 @
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC15 @
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC16 @
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC17 @
AG11 AR5 BF33 BM29 C9 J7 BH30 B2 TC18 @
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
VSS_52 VSS_133 VSS_214 VSS_295 VSS_377 VSS_461 @
AG8 AU12 BG37 BM6 D20 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
CFL-H(8/8)GND/RSVD
A B C D E
A B C D E
CNP-H
UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<10> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P1 USB20_N1 <46>
<10> DMI_CTX_PRX_P0 J35 J2 USB3 MB
UH1 DMI_CRX_PTX_N0 DMI0_RXP USB2P_1 USB20_N2 USB20_P1 <46>
<10> DMI_CRX_PTX_N0 C33 N13
DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <45>
<10> DMI_CRX_PTX_P0 B33 N15 TYPE C
DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <45>
<10> DMI_CTX_PRX_N1 G33 K4
DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <48>
<10> DMI_CTX_PRX_P1 F34 K3
DMI_CRX_PTX_N1 DMI1_RXP USB2P_3 USB20_N4 USB20_P3 <48>
<10> DMI_CRX_PTX_N1 C32 M10 USB2 (SUB/B)
<10> DMI_CRX_PTX_P1 B32 L9
DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 USB20_N5 USB20_P4 <48>
CFL-H_BGA1440 <10> DMI_CTX_PRX_N2 K32 M1
DMI_CTX_PRX_P2 DMI2_RXN USB2N_5 USB20_P5 USB20_N5 <37>
S IC FH82HM370 SR40B B0 BGA 874P PCH-H ABO! <10> DMI_CTX_PRX_P2 J32 L2 Camera
DMI_CRX_PTX_N2 DMI2_RXP USB2P_5 USB20_N6 USB20_P5 <37>
SA0000BVP10 <10> DMI_CRX_PTX_N2 C31 K7
1 PCH@ <10> DMI_CRX_PTX_P2 B31 K6 TS 1
DMI_CTX_PRX_N3 DMI2_TXP USB2P_6 USB20_P6 <37>
<10> DMI_CTX_PRX_N3 G30 L4
DMI_CTX_PRX_P3 F30 DMI3_RXN USB2N_7 L3 +3VALW _PCH_PRIM
<10> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
<10> DMI_CRX_PTX_N3 C29 G4
<10> DMI_CRX_PTX_P3 B29 G5 FingerPrint RPH1
DMI3_TXP USB2P_8 USB20_P8 <50> USB_OC0#
A25 M6 8 1
B25 RSVD USB2N_9 N8 USB_OC1# 7 2
P24 RSVD USB2P_9 H3 USB_OC2# 6 3
R24 RSVD USB2N_10 H2 USB_OC3# 5 4
C26 RSVD USB2P_10 R10
B26 RSVD USB2N_11 P9 10K_0804_8P4R_5%
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
RSVD USB2N_13 FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf
C27 N2
L26 RSVD USB2P_13 E5 USB20_N14
RSVD USB2N_14 USB20_P14 USB20_N14 <41>
M26 F6 BT
RSVD USB2P_14 USB20_P14 <41>
D29
E28 RSVD AH36 USB_OC0#
RSVD GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <44>
K29 AL40 USB_OC1# <46>
M29 RSVD GPP_E10/USB2_OC1# AJ44 USB_OC2#
RSVD GPP_E11/USB2_OC2# AL41 USB_OC3# +3VALW
G17 GPP_E12/USB2_OC3# AV47
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37
1
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN USB2_RCOMP RH3
P21 F4 RH4 1 2 113_0402_1%
PCIE2_RXP/USB31_8_RXP USB2_COMP USB2_VBUS_SENSE RH5 10K_0402_5%
B18 F3 1 @ 2 0_0402_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
2
2 GPD_7 2
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID RH6 1 @ 2 0_0402_5%
PCIE3_RXN/USB31_9_RXN USB2_ID
STRAP
J18
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
1
C19 PCIE3_TXN/USB31_9_TXN GPD7
PCIE3_TXP/USB31_9_TXP RH7
N18 G45
PCIE4_RXN/USB31_10_RXN PCIE24_TXP 10K_0402_5%
R18 G46
PCIE4_RXP/USB31_10_RXP PCIE24_TXN @
D20 Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
2
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48
PCIE5_RXN PCIE23_TXP X'tal Input:
G20 G49 High: Differential
B21 PCIE5_RXP PCIE23_TXN W44 Low: Single ended
A22 PCIE5_TXN PCIE23_RXP W43
K21 PCIE5_TXP PCIE23_RXN H48
J21 PCIE6_RXN PCIE22_TXP H47
D21 PCIE6_RXP PCIE22_TXN U41
C21 PCIE6_TXN PCIE22_RXP U40
B23 PCIE6_TXP PCIE22_RXN F46
C23 PCIE7_TXP PCIE21_TXP G47
J24 PCIE7_TXN PCIE21_TXN R44
L24 PCIE7_RXP PCIE21_RXP T43
F24 PCIE7_RXN PCIE21_RXN
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0
@
3 3
The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes
— A maximum of 16 PCIe* Ports (or devices) can be enabled
‧ When a GbE Port is enabled, the maximum number of PCIe* Ports (or
devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured
2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express * (PCIe*) ” chapt er f or t he P CH PCI e* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
PCH(1/8)DMI/PCIE/USB2
A B C D E
A B C D E
PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H
remove TP as C5PRH UH1G

XTAL_24M_PCH_OUT 1 EMI@ 2 XTAL_24M_PCH_OUT_R BE33
RH11 33_0402_1% GPP_A16/CLKOUT_48
PCH_CPU_24M_CLK_P D7 Y3
<11> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# @ TH2
C6 Y4 @ TH3
XTAL_24M_PCH_IN 1 EMI@ 2 XTAL_24M_PCH_IN_R <11> PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P
1 2
RH8 1M_0402_5% RH9 33_0402_1% PCH_CPU_BCLK_P B8 B6 PCH_CPU_PCIBCLK_N
<11> PCH_CPU_BCLK_P PCH_CPU_BCLK_N CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N <11>
C8 A6
<11> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <11>
YH1
24MHZ_18PF_XRCGB24M000F2P51R0 XTAL_24M_PCH_OUT_R U9 AJ6 CLK_PEG_VGA#
XTAL_24M_PCH_IN_R XTAL_OUT CLKOUT_PCIE_N0 CLK_PEG_VGA CLK_PEG_VGA# <25>
1 U10 AJ7 DGPU 1
XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_VGA <25>
3 1
3 1 XCLK_BIASREF CLK_PCIE_LAN#
33P_0402_50V8J
18P_0402_50V8J
RH10 1 2 60.4_0402_1% T3 AH9
NC NC XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_LAN CLK_PCIE_LAN# <40>
AH10 GLAN
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_LAN <40>
CH5
CH6
XCLK_BIASREF (PDG) BA49
4 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14 CLK_PCIE_W LAN#
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_W LAN CLK_PCIE_W LAN# <41>
8/24 AE15 NGFF WL+BT(KEY E)
VGA_CLKREQ# CLKOUT_PCIE_P2 CLK_PCIE_W LAN <41>
BF31
LAN_CLKREQ# BE31 GPP_B5/SRCCLKREQ0# AE6 CLK_PCIE_NGFF#
<40> LAN_CLKREQ# W LAN_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_NGFF CLK_PCIE_NGFF# <39>
<41> W LAN_CLKREQ# AR32 AE7 M2 SSD
SSD_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_NGFF <39>
<39> SSD_CLKREQ# BB30
BA30 GPP_B8/SRCCLKREQ3# AC2
PCH_RTCX1 AN29 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 AC3
AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4
PCH_RTCX2 AC48 GPP_H0/SRCCLKREQ6# AB2
AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3
1 2 AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5
RH12 10M_0402_5% AC41 GPP_H3/SRCCLKREQ9# W4
AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
AB48 GPP_H6/SRCCLKREQ12# W7
YH2
1 2 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
32.768KHZ_9PF_X1A000141000200 GPP_H9/SRCCLKREQ15# AC14
1 1 CLKOUT_PCIE_N8
10P_0402_50V8J
10P_0402_50V8J
V2 AC15
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15
CH7
CH8
U2
2 Trace Space: 15 mil 2 T2 CLKOUT_PCIE_N9 U3
Max Trace Length: 1000 mil T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 CLKOUT_PCIE_P14 AC9 2
AA1 CLKOUT_PCIE_N10 AC11
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
use same part w C5MMH AC7 CLKOUT_PCIE_N11 AE11
+3VS CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
AC6
CLKOUT_PCIE_P12 7 OF 13 R6 REFCLK_CNV
CLKIN_XTAL REFCLK_CNV <41>
CNP-H_BGA874 Rev1.0
1
RPH2 @ 1
8 1 LAN_CLKREQ# RH14
7 2 VGA_CLKREQ# 10K_0402_5% CH51 @ESD@
W LAN_CLKREQ# VGA_CLKREQ# <25>
6 3 4.7P_0201_50V8B
5 4 SSD_CLKREQ# 2
2
10K_0804_8P4R_5%
CNP-H
UH1M
AW13 BD4 CLK_CNV_PRX_DTX_N

GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_P CLK_CNV_PRX_DTX_N <41>
For DDX03 R02 BE9 BE3 CLK_CNV_PRX_DTX_P <41>
BF8 GPP_G1/SD_DATA0 CNV_WR_CLKP
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
XTAL Frequency Select GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_P0 CNV_PRX_DTX_N0 <41>
BG8 BB4
+1.8VALW _PRIM GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <41>
remove SD signal from PCH BE8 BA3
GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <41>
BD8 BA2
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <41>
AV13
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
3 CNV_BRI_PTX_DRX CNV_WT_CLKN CLK_CNV_PTX_DRX_P CLK_CNV_PTX_DRX_N <41> 3
RH15 1 2 4.7K_0402_5% AP3 BB6 CLK_CNV_PTX_DRX_P <41>
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
This signal has a weak internal pull-down 20K. STRAP GPP_I13/M2_SKT2_CFG2 3.3V CNV_WT_D0N CNV_PTX_DRX_N0 <41>
AM7 BD7 CNV_PTX_DRX_P0
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
remove CPU_C10_GATE# GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6 CNV_PTX_DRX_N1 CNV_PTX_DRX_P0 <41>
CNV_WT_D1N CNV_PTX_DRX_P1 CNV_PTX_DRX_N1 <41>
Notes: AV6 BF6 CNV_PTX_DRX_P1 <41>
1. The internal pull-down is disabled after RSMRST# AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_D1P BA1 CNV_W T_RCOMP RH16 1 2 150_0402_1%
de-asserts.
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
2. This signal is in the primary well. GPP_J11/A4WP_PRESENT PCIE_RCOMPN
AV7 B12 RH17 1 2 100_0402_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH18 1 2 200_0402_1%
+1.8VALW _PRIM CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH19 1 2 200_0402_1%
VCCPSPI Select <41> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
checked CRB
<41> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P8 RH20 1
BA4 BE1 2 200_0402_1%
<41> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
AV3 BE2
<41> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
@ GPP_J9 AW2
RH21 1 2 4.7K_0402_5% GPP_J9 GPP_J8/CNV_MFUART2_RXD
AU9 Y35
The signal has a weak internal pull-down 20K GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
0 = VCCPSPI is connected to 3.3V rail
STRAP RSVD3
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin BC1
+1.8VALW _PRIM 13 OF 13 RSVD1 AL35
strap must be a ‘ 1’ fo r th e prope r functionalit y @ TH4
of the SPI (Flash) I/Os TP
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
CNP-H_BGA874 Rev1.0
Recommend external test point
+1.8VALW _PRIM RH181 1 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX @
M.2 CNV Mode Select
RH182 1 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX
571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
RH22 2 1 10K_0402_5% CNV_RGI_PTX_DRX a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.
4 4
@ STRAP
RH23 2 1 10K_0402_5%
An external pull-up or pull-down is required.

0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
Pulled down by CRF CNVi RGI_DT pin Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
PCH(2/8)CLK/CNVI/SD
A B C D E
A
CNP-H
UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8 DDP[B..F]CTRLDATA
no follow naming GPP_I6/DDPB_CTRLDATA This signal has a weak internal Pull-down.
AT6 AN13
HDMI_HPD_PCH AN10 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK AL10 0 = Port B~D is not detected.
<26,38> HDMI_HPD_PCH GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA 1 = Port B,C,D is detected. (Default)
AP9 AL9 Notes:
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
can remove if no use DP GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA
1. The internal Pull-down is disabled after
AN40 PCH_PWROK de-asserts.
08/18 GPP_F23/DDPF_CTRLDATA AT49 2. This signal is in the primary well.
GPP_F22/DDPF_CTRLCLK
AP41
EDP_HPD AN6 GPP_F14/PS_ON#
<37> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
remove PCH DP SCLK/SDATA M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47
GPP_H23/TIME_SYNC0
CNP-H_BGA874 Rev1.0
remove CIO_PLUG_EVENT#
@
CNP-H
UH1A PLT_RST#
EC_PME#_R PLT_RST# CH9 1 2 100P_0402_50V8J
1 @ 2 BE36 AV29
<40,43> EC_PME# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# <19,26,36,43,49>
RH24 0_0402_5%
@ESD@
R15 Y47
R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
CRB PU 20k RSVD1 GPP_K12/GSXDOUT
#571182_CFL_PCH_EDS_Rev1.0 recommend 100k Y48 provided by the PCH to expand the GPIOs
GPP_K13/GSXSLOAD W46 on a platform that needs more GPIOs than the
GPP_K14/GSXDIN ones provided by the PCH.
+3VALW _SPI PDG P348 quad mode support PH1K 0_0402_5% 1 @ 2 RH186 AL37 AA45
AN35 VSS GPP_K15/GSXSRESET#
TH6 @ TP
RH25 2 1 1K_0402_5% PCH_SPI_IO2 PCH_SPI_SI AU41 AL47 DH1
PCH_SPI_SO BA45 SPI0_MOSI GPP_E3/CPU_GP0 AM45 RB751V-40_SOD323-2
RH26 2 1 1K_0402_5% PCH_SPI_IO3 PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TP_INT# 2 1 +3VS
PCH_SPI_CLK SPI0_CS0# GPP_B3/CPU_GP2 EC_TP_INT# <43,49>
AW47 BC33
<19> PCH_SPI_CLK SPI0_CLK GPP_B4/CPU_GP3 TYPEC_1P5A <44>
AW48
RH27 2 1 1K_0402_5%PCH_SPI_SI SPI0_CS1# AE44 TP_INT# RH28 2 1 100K_0402_5%
PCH_SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46
+3VALW _PCH_PRIM PCH_SPI_IO3 BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H15
RH29 2 1 100K_0402_5% GPP_H15 STRAP SPI0_CS2# GPP_H15/SML3ALERT# AD48
BE19 GPP_H14/SML3DATA AF47
#571182_CNL_PCH_H_EDS_V1_Rev0.7 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK GPP_H12
External pull-up is required. Recommend 100K if pulled BF19 AB47
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# GPP_H12 <20> +RTCVCC
up to 3.3V or 75K if pulled up to 1.8V. BF18 AD47
571007_CFL_MOW_Archive_WW22_2017 BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
STUFF R on GPP_H15 BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER# 1M_0402_5% 2 1 RH30
<47> HDD_PW RGT GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0 RVP: 330K
reserve for Optane Memory A 1 M pull-up is used on the customer reference
1 @ board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.
SPI ROM ( 16MByte )

+3VALW _SPI
+3VALW _SPI
CH10 0.1U_0201_10V6K
UH2 PCH_SPI_CS#0
1 2 1 @ 2
PCH_SPI_CS#0 1 8 RH31 4.7K_0402_5% PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%
PCH_SPI_SO_0_R 2 /CS VCC 7 PCH_SPI_IO3_0_R
PCH_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R +3VS
4 /WP(IO2) CLK 5 PCH_SPI_SI_0_R
GND DI(IO0)
CH11 1 2
W 25Q128FVSIQ_SO8
P/N: SA00005VV20 .1U_0402_16V7K
PCH_SPI_SI_0_R RH107 1 2 49.9_0402_1% PCH_SPI_SI
5
PCH_SPI_SO_0_R RH108 1 2 49.9_0402_1% PCH_SPI_SO UH3
@EMI@ @EMI@ PCH_SPI_IO3_0_R RH109 1 2 49.9_0402_1% PCH_SPI_IO3 PLT_RST# 1
P
PCH_SPI_CLK_0_R 1 2 1 2 PCH_SPI_CLK_0_R RH110 1 2 49.9_0402_1% PCH_SPI_CLK B 4
PCH_SPI_IO2_0_R PCH_SPI_IO2 Y PLT_RST_BUF# <39,40,41>
RH111 1 2 49.9_0402_1% 2
A
G
RH33 CH12
0_0402_5% 68P_0402_50V8J sch checklist 0.7 TC7SH08FU_SSOP5
3
1 device 15 ohm / 2 device 33 ohm
2017/07/20
Compal Secret Data
2018/07/20 Title
PCH(3/8)DDC/SPI
A
A B C D E
#571391_CFL_H_PDG_Rev0p5
‧ eSPI clock and eSPI data mismatched: <500 mils.
‧ eSPI clock and eSPI chip select mismatched: <500 mils.
‧ eSPI signal maximum 9 Vias
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
CNP-H
UH1F
F9 BB39 LPC_AD0
<46> USB3_PTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <43,49>
F7 1.8V AW37 LPC Bus check straps
<46> USB3_PTX_DRX_P1 USB31_1_TXP (eSPI) GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <43,49>
USB3 MB <46> USB3_PRX_DTX_N1 D11 AV37
USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <43,49>
<46> USB3_PRX_DTX_P1 C11 BA38 LPC : +3.3V
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <43,49>
C3
<45> USB3_PTX_DRX_N2 USB31_2_TXN LPC_FRAME#
D4 BE38
<45> USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# TPM_SERIRQ LPC_FRAME# <43,49>
1 USB3 Type C <45> USB3_PRX_DTX_N2 B9 AW35 TPM_SERIRQ <43,49> 1
C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 LPC_PIRQA#
<45> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST#
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <43>
C16
G14 USB31_6_TXP BB36 CLK_LPC RH35 2 1 22_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_TPM CLK_LPC_R <43>
F14 BB34 RH36 2 TPM@ 1 22_0402_5%
USB31_6_RXP GPP_A10/CLKOUT_LPC1 CLK_LPC_TPM_R <49>
C15
<48> USB3_PTX_DRX_N5 USB31_5_TXN
B15 T48
<48> USB3_PTX_DRX_P5 USB31_5_TXP GPP_K19/SMI#
USB3 SUB <48> USB3_PRX_DTX_N5 J13 T47
K13 USB31_5_RXN GPP_K18/NMI#
<48> USB3_PRX_DTX_P5 USB31_5_RXP
G12 AH40
<45> USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2
F11 AH35
<45> USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 SSD_DEVSLP1 <39>
USB3 Type C <45> USB3_PRX_DTX_P3 C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47
<45> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37 +3VS
C14 GPP_F8/SATA_DEVSLP6 AN46
<48> USB3_PTX_DRX_P4 USB31_4_TXP GPP_F7/SATA_DEVSLP5
B14 AR47
<48> USB3_PTX_DRX_N4 USB31_4_TXN GPP_F6/SATA_DEVSLP4
USB3 SUB <48> USB3_PRX_DTX_P4 J15 AP48
K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
<48> USB3_PRX_DTX_N4 USB31_4_RXN TPM_SERIRQ 2 1 RH37
CNP-H_BGA874 Rev1.0
10K_0402_5%
@
LPC_PIRQA# 1 2 RH38
CNP-H 10K_0402_5%
2 UH1C 2
CL_CLK AR2 G36
TH10 @ CL_DATA CL_CLK PCIE9_RXN PCIE_PRX_DTX_N9 <39>
For Intel CLINK TH11 @ AT5 F36 M.2 SSD PCIE L3
CL_RST# AU4 CL_DATA PCIE9_RXP C34 PCIE_PRX_DTX_P9 <39>
TH12 @ CL_RST# PCIE9_TXN PCIE_PTX_DRX_N9 <39>
D34
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <39>
V47 GPP_K8
V48 GPP_K9 K37
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_N10 <39>
GPP_K11 PCIE10_RXP PCIE_PRX_DTX_P10 <39> M.2 SSD PCIE L2
C35
L47 PCIE10_TXN B35 PCIE_PTX_DRX_N10 <39>
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <39>
U48 GPP_K1 F44 PCIE_PRX_DTX_N15
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45 PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <41>
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 PCIE_PRX_DTX_P15 <41> NGFF
N48 B40 .1U_0402_16V7K 1 2 CH1
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_P15 .1U_0402_16V7K 1 2 CH2
PCIE_PTX_C_DRX_N15 <41> WL+BT(KEY E)
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_C_DRX_P15 <41>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41
<39> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<39> PCIE_PTX_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 SSD PCIE L1 <39> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP
G38 K43
<39> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 SATA_PRX_DTX_N4 <47>
AR42 PCIE17_RXP/SATA4_RXP A42 SATA_PRX_DTX_P4 <47>
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN SATA_PTX_DRX_N4 <47>
HDD
AR48 B42
DGPU_PRSNT# AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP SATA_PTX_DRX_P4 <47>
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40
3 CH3 2 1 .1U_0402_16V7K PCIE_PTX_DRX_N14 C39 PCIE18_RXP/SATA5_RXP C42 3
<40> PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
CH4 2 1 .1U_0402_16V7K D39 D42 +3VS
<40> PCIE_PTX_C_DRX_P14 PCIE_PRX_DTX_N14 D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
GLAN <40> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN
C47 AK48
<40> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
B38 AH41
C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43
C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP1 <39>
C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47 RH187 1 PBA@ 2 1K_0402_5%
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46 SATA_GP1 RH39 2 1 10K_0402_5%
E37 GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATA_GP5
<39> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 @ TH13
D38 AM47 M.2 SSD PCIE/SATA select pin
<39> PCIE_PTX_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48
<39> PCIE_PRX_DTX_P12 H42 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
M.2 SSD PCIE L0 <39> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN PCH_BKL_PW M
AU48
GPP_F21/EDP_BKLTCTL PCH_BKL_PW M <26,37>
B44 AV46 ENBKL
PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PCH_ENVDD ENBKL <26,43>
A44 AV44
PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_ENVDD <26,37>
R37 #571391_CFL_H_PDG_Rev0p5.pdf
R35 PCIE20_RXP/SATA7_RXP AD3 PCH_THERMTRIP# RH40 1 2 620_0402_5%
PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI PCH_THERMTRIP#_R <11>
D43 AF2 RH41 1 @ 2 13_0402_5% H_PECI
PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <11,43>
C44 AF3 RH42 1 2 30_0402_5% H_PM_SYNC_R
+3VALW _PCH_PRIM PCIE19_TXN/SATA6_TXN PM_SYNC H_PLTRST_CPU# H_PM_SYNC_R <11>
N42 AG5
PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOW N_R H_PLTRST_CPU# <11>
M44 AE2
PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N_R <11>
1
CNP-H_BGA874 Rev1.0
RH43 @
10K_0402_5% UMA@
2
4 4
DGPU_PRSNT#
1
RH44
GPP_F13 Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% VGA@ DGPU_PRSNT# 2017/07/20 2018/07/20 Title
DIS,Optimus 0 PCIE/SATA/USB3/eSPI
2
UMA 1 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
A B C D E
A B C D E
+1.2V_VDDQ
<43> ME_EN 1 @ 2
2
RPH7 RH45 0_0402_5%
1 8 HDA_RST# RH46
<42> HDA_RST#_R HDA_BIT_CLK
<42> HDA_BIT_CLK_R 2 7 470_0402_1%
3 6 HDA_SDOUT
<42> HDA_SDOUT_R HDA_SYNC
<42> HDA_SYNC_R 4 5
1
DRAM_RESET# 1 @ 2
DDR_DRAMRST#_R <23,24>
33_0804_8P4R_5% RH47 0_0402_5%
2 1
1 CH13 1U_0402_6.3V6K 1
CNP-H
@
UH1D
HDA_BIT_CLK BD11 BF36
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#
<42> HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# PM_CLKRUN# <49>
del RF reserve cap on HDA BF12
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 LAN_DISABLE_N
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC @ TH14
HDA_RST# BE10 BD42 SLP_W LAN#
HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# @ TH15
BF10
BE12 HDA_SDI1/I2S1_RXD BB46 DRAM_RESET#
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
GPP_B1/GSPI1_CS1#/TIME_SYNC1 LAN_GPO TYPEC_3A <44>
BE29
RH48 1 CPU_DISPA_SDO GPP_B0/GSPI0_CS1# PCH_GPP_K17 LAN_GPO <40>
2 30_0402_5% AM2 R47 @ TH19
<7> CPU_DISPA_SDO_R CPU_DISPA_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE PCH_GPP_B11
AN3 AP29 @ TH20
<7> CPU_DISPA_SDI_R RH49 1 CPU_DISPA_BCLK HDACPU_SDI GPP_B11/I2S_MCLK SYS_PW ROK
2 30_0402_5% AM3 AU3 SYS_PW ROK <43,51>
<7> CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK
FOR Jefferson Peak RESET pin is glitch free,it AV18 BB47 W AKE#
AW18 GPP_D8/I2S2_SCLK WAKE# BE40 PM_SLP_A#
is recommended that a pull-down resistor of 75K CLKREQ_CNV# BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 SLP_LAN# @ TH37
ohm on GPP_D5(CNV_RF_RESET#) <41> CLKREQ_CNV# CNV_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# PM_SLP_S0# @ TH21
BE16 BC28
<41> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# <43>
<42> PCH_DMIC_DATA0 BF15 BF42
GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# <43,51>
BD16 BE42
+RTCVCC <42> PCH_DMIC_CLK0 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <43,51>
TH22 @ AV16 BC42 @ TH23
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
PCH_SRTCRST# TH24 @ GPP_D17/DMIC_CLK1/SNDW3_CLK
RH50 1 2 20K_0402_1% BE45 SUSCLK
GPD8/SUSCLK PM_BATLOW # SUSCLK <39,41>
BF44
CH18 1 2 1U_0402_6.3V6K GPD0/BATLOW# BE35 SUSACK#_R
PCH_RTCRST# GPP_A15/SUSACK# @ T207
2 BE47 BC37 1 @ 2 2
<43> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUSPW RDNACK <43>
CLR ME BD46 RH51 0_0402_5%
Delay 18~25 ms SRTCRST#
PCH_PW ROK AY42 BG44 LAN_W AKE#
PCH_RTCRST# <43,51> PCH_PW ROK EC_RSMRST# PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT_R
RH52 1 2 20K_0402_1% <43> EC_RSMRST# BA47 BG42 RH53 1 @ 2 0_0402_5% AC_PRESENT <43>
RSMRST# GPD1/ACPRESENT BD39 SLP_SUS# T208
SLP_SUS# PBTN_OUT#_R @ --No Support Deep Sx
CH19 1 2 1U_0402_6.3V6K BE46 1 @ 2 PBTN_OUT# <43>
PCH_DPW ROK AW41 GPD3/PWRBTN# AU2 SYS_RESET# RH54 0_0402_5%
JCMOS1 1 @ 2 0_0603_5% ECLR CMOS PCH_SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 PCH_SPKR
Delay 18~25 ms <20> PCH_SMBALERT# PCH_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR H_CPUPW RGD PCH_SPKR <20,42>
BE26 AE3
PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPW RGD <11>
BF26
PCH_SML0ALERT# BF24 GPP_C1/SMBDATA AL3 XDP_ITP_PMODE T209
<20> PCH_SML0ALERT# PCH_SML0CLK GPP_C5/SML0ALERT# ITP_PMODE CPU_XDP_TCK0 @
BF25 AH4 CPU_XDP_TCK0 <11>
PCH_SML0DATA BE24 GPP_C3/SML0CLK PCH_JTAGX AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS <11>
<20> PCH_SML1ALERT# PCH_SML1CLK BF27 GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO AH2 CPU_XDP_TDI CPU_XDP_TDO <11> Connect CPU & PCH
+3VALW _DSW GPP_C6/SML1CLK PCH_JTAG_TDI CPU_XDP_TDI <11>
PCH_SML1DATA BE27 4 OF 13 AJ3
GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK1 <11>
CNP-H_BGA874 Rev1.0
@
RH55 2 1 1K_0402_5% W AKE#
RH56 2 1 8.2K_0402_5% PM_BATLOW #
RH57 2 @ 1 100K_0402_5% AC_PRESENT_R

+3VALW _PCH_PRIM +3VALW _DSW
RH58 2 @ 1 100K_0402_5% PBTN_OUT#_R
RPH8
+3VS
8 1 PCH_PW ROK
3 EC_RSMRST# 1 @ 2 PCH_DPW ROK 3
7 2 LAN_W AKE#
+3VS EC_RSMRST# RH59 0_0402_5%
6 3
5 4 SYS_RESET#
5
G
QH7B
PM_CLKRUN# 10K_0804_8P4R_5% +3VALW _PCH_PRIM
RH60 2 1 8.2K_0402_5% 2N7002KDW _SOT363-6
PCH_SMBCLK D_CK_SCLK
(DDR,G-Sensor) PCH_VRALERT# RH62 2
3 4 @ 1 10K_0402_5%
S
D_CK_SCLK <23,24,47>
D
100K_0402_5% 1 @ 2 RH184 SYS_PW ROK

G
QH7A
2N7002KDW _SOT363-6
100K_0402_5% 1 @ 2 RH61 PCH_DPW ROK
+3VS PCH_SMBDATA 6 1 D_CK_SDATA
S
D_CK_SDATA <23,24,47>
@ESD@
D
1 2 D_CK_SDATA 100P_0402_50V8J 1 2 CH50 EC_RSMRST#

RH197 2.2K_0402_5%
1 2 D_CK_SCLK
RH198 2.2K_0402_5% @ESD@ Intel critical net recommend
.1U_0402_16V7K 1 2 CH20 SYS_RESET#
PM_SLP_S3# RH191 1 2 100K_0201_5%
+3VALW _PCH_PRIM @ESD@ PM_SLP_S4# RH192 1 2 100K_0201_5%
.1U_0402_16V7K 1 2 CH21 SYS_PW ROK HDA_BIT_CLK RH193 1 2 100K_0201_5%
RPH11 HDA_RST# RH194 1 2 100K_0201_5%
8 1 PCH_SMBCLK RH195 1 @ 2 100K_0201_5%
PCH_SMBDATA <17> PCH_SPI_CLK
7 2 @ESD@ <17,26,36,43,49> PLT_RST# RH196 1 2 100K_0201_5%
6 3 PCH_SML1CLK .1U_0402_16V7K 1 2 CH22 PCH_PW ROK
PCH_SML1CLK <26,43,44,48>
5 4 PCH_SML1DATA
PCH_SML1DATA <26,43,44,48> (EC, VGA, Thermal Sensor, Type-C)
4 4
2.2K_0804_8P4R_5% Near PCH side
1 2 PCH_SML0CLK From ESD Team Request
RH63 499_0402_1%
1 2 PCH_SML0DATA
RH64 499_0402_1%
2017/07/20
Compal Secret Data
2018/07/20 Title
PCH(5/8)PMU/HDA/SMBUS/DMIC
A B C D E
A B C D E
+3VALW _PCH_PRIM
RPH12
1 8 I2C_1_SCL CNP-H
2 7 I2C_1_SDA UH1K
3 6 I2C_0_SCL
4 5 I2C_0_SDA GSPI1_MOSI BA26 BA20 VGA_ID1
BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 VGA_ID2
2.2K_0804_8P4R_5% EC_SCI# AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16 PROJECT_ID0
<43> EC_SCI# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO PROJECT_ID1
AW26 AN18
+3VS GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GSPI0_MOSI BE30 BF14 +1.8VALW _PRIM
RH66 2 @ 1 10K_0402_5% EC_SCI# GC6_FB_EN3V3 RH67 1 @ 2 0_0402_5% GC6_FB_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
<26,36> GC6_FB_EN3V3 TS_EN GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
BF29 BF17
<37,43> TS_EN GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
1 RH68 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BB26 BE17 SUB_DET SUB_DET RH185 1 @ 2 1K_0402_5% 1
GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH69 2 1 49.9K_0402_1% UART_2_PTXD_DRXD check needed? BB24 Pop for USB3.0 DB.
DGPU_AC_DETECT BE23 GPP_C9/UART0A_TXD
<26,43,54> DGPU_AC_DETECT GPP_C8/UART0A_RXD
RH70 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS AP24
GPU_EVENT# BA24 GPP_C11/UART0A_CTS#
CG11 connect to GPP_B15 <26> GPU_EVENT# GPP_C10/UART0A_RTS#
RH71 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
RH72 1 VGA@ 2 10K_0402_5% DGPU_PW R_EN AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
DGPU_HOLD_RST# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
<26,36> DGPU_HOLD_RST# DGPU_PW R_EN GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL +3VS
AU24 AH48
<26,36> DGPU_PW R_EN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH73 1 VGA@ 2 10K_0402_5% DGPU_HOLD_RST# UART_2_PCTS_DRTS AV21
GPP_C23/UART2_CTS#
2
UART_2_PRTS_DCTS AW21
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34 RH78
<41> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32 @ 10K_0402_5%
+3VALW _PCH_PRIM <41> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34 G_INT
<49> I2C_1_SCL
1
I2C_1_SDA BF21 GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 BD34 CODEC_ID G_INT
RH74 1 @ 2 4.7K_0402_5% GPP_H12 <Touch PAD> <49> I2C_1_SDA I2C_0_SCL BC22 GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 BF35
G_INT <47>
GPP_H12 <17> I2C_0_SDA GPP_C17/I2C0_SCL GPP_A18/ISH_GP0
BF23 BD38
GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
2
This signal has a weak internal pull-down. STRAP
0 = Master Attached Flash Sharing (MAFS) enabled (Default) BE15 RH79
1 = Slave Attached Flash Sharing (SAFS) enabled.
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13 @
Notes: GPP_D23/ISH_I2C2_SCL/I2C3_SCL 100K_0402_5%
1. This signal is in the primary well.
Warning: This strap must be configured to ‘ 0’ i f th e CNP-H_BGA874 Rev1.0
1
eSPI or LPC strap is configured to ‘ 0’
@
2 2
+3VALW _PCH_PRIM
+3VALW _PCH_PRIM
RH112 1 @ 2 4.7K_0402_5%
PCH_SMBALERT# <19> CODEC_ID RH188 1 256@ 2 1K_0402_5%
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default) CODEC_ID / GPP_A19
1 = Enable Intel ME (TLS) 0 = 2 DMIC, 255@ (default)
1 = 4 DMIC, 256@
RH113 1 @ 2 4.7K_0402_5%
PCH_SML0ALERT# <19>
SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected +1.8VALW _PRIM
+1.8VALW _PRIM
RH114 1 2 150K_0402_1% VGA_ID1 RH84 1 @ 2 1K_0402_5% PROJECT_ID0 RH88 1 SATARD@

2 1K_0402_5%
PCH_SML1ALERT# <19>
SML1ALERT# / GPP_B23 has an internal pull-down. RH85 1 2 10K_0402_5% RH89 1 NORD@ 2 10K_0402_5%
0 = Disable IntelR DCI-OOB (Default)
1 = Enable IntelR DCI-OOB
STRAP
VGA_ID2 RH86 1 @ 2 1K_0402_5% PROJECT_ID1 RH90 1 @ 2 1K_0402_5%
+3VS RH87 1 2 10K_0402_5% RH91 1 2 10K_0402_5%

3 3
RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP

The signal has a weak internal Pull-down.
0 = Disable “ No Reboot” mode . (Default) VGA_ID2 VGA_ID1 Project_ID1 Project_ID0
1 = Enable “ No Reboot” mod e (PC H wil l disabl e th e VGA ID Project ID
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
GPP_D10 GPP_D9 GPP_D12 GPP_D11
Notes:
1. The internal Pull-down is disabled after *Default 0 0 DH53F(1060 W/O RD) 0 0
PCH_PWROK is high.
2. This signal is in the primary well. Reserve 0 1 *DH53F(1060 W/ RD) 0 1
Reserve 1 0 DH5VF(1050 W/O RD) 1 0
RH80 1
@
2 150K_0402_1% GSPI1_MOSI STRAP 8 Layer, 1050 1 1 DH5VF(1050 W/ RD) 1 1
This Signal has a weak internal Pull-down.
0: SPI (Default) SCI capability is available on all GPIOs
1: LPC PCH GPIOs that can be routed to generate SMI# or NMI:
Notes: ‧ GPP_B14, GPP_B20, GPP_B23
1. The internal Pull-down is disabled after PCH_PWROK is high. ‧ GPP_C[23:22]
2. This signal is in the primary well. ‧ GPP_D[4:0]
‧ GPP_E[8:0]
‧ GPP_I[3:0]
‧ GPP_G[7:0] (support SMI# only).
RH83 2 @ 1 100K_0402_5% PCH_SPKR
PCH_SPKR <19,42> The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
Top Swap Override except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
0 = Disable “ Top Swap” mode. (Default
)
STRAP
1 = Enable “ Top Swap” mode
. All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
4 The internal Pull-down is disabled after PCH_PWROK is high. The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming. 4
2017/07/20
Compal Secret Data
2018/07/20 Title
PCH(6/8)GPIO/I2C/UART/STRAP
A B C D E
A B C D E
GPIO Group Voltage
GPPA 3.3V
+1.05VALW_PCH_PRIM
+1.05VALW CNP-H +3VALW_PCH_PRIM
+1.05VALW_PCH_PRIM UH1H GPPB
5.95A AA22 AW9 0.182A GPPC 3.3V
AA23 VCCPRIM_1P051 VCCPRIM_3P32
RH92 2 @ 1 0_1206_5% 5.95A AB20 VCCPRIM_1P052 BF47 +VCCRTCEXT
HSIO for DMIU/USB3.1/PCIE=4162mA VCCPRIM_1P053 DCPRTC1 +VCCRTCEXT GPPD 1.8V
AB22 BG47 +VCCRTCEXT
VCCPRIM_1P054 DCPRTC2
1U_0402_6.3V6K
1 AB23
AB27 VCCPRIM_1P055 V23 0.095A +3VALW_SPI
VCCPRIM_1P056 VCCPRIM_3P35
GPPE
CH23
.1U_0402_16V7K
AB28 1 3.3V
AB30 VCCPRIM_1P057 AN44 0.05A GPPF
2 VCCPRIM_1P058 VCCSPI +RTCVCC
CH24
AD20
AD23 VCCPRIM_1P059 BC49
1 GPPG 3.3V 1
AD27 VCCPRIM_1P0510 VCCRTC1 BD49 2
AD28 VCCPRIM_1P0511 VCCRTC2
AD30 VCCPRIM_1P0512 AN21 0.145A GPPH 3.3V
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 GPPK
+1.05VALW_VCCMPHY AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 0.97A
+1.05VALW_VCCMPHY AF30 VCCPRIM_1P0517 VCCPRIM_3P34
VCCPRIM_1P0518
GPPI 3.3V Only
RH93 2 1 0_0805_5% 6.6A AC35 0.262A
6.6A U26 VCCPGPPHK1 AC36
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.174A GPPJ 1.8V Only
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36 +1.8VALW_PRIM
VCCPRIM_1P0525 VCCPGPPEF2
22U_0402_6.3V6M
1U_0402_6.3V6K
1 1 V27
V28 VCCPRIM_1P0526 AN24 0.14A GPD 3.3V Only
VCCPRIM_1P0527 VCCPGPPD +1.8VALW_PRIM
CH25
CH26
V30 AN26
+1.05VALW_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.343A
2 2 VCCPRIM_1P0529 VCCPGPPBC2
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA
4.7U_0402_6.3V6M
1U_0402_6.3V6K
1 1
0.2A AE17 AT44 0.106A
VCCPRIM_1P0515 VCCPRIM_3P31
CH27
CH28
BE48
3-5MM FROM PACKAGE EDGE 0.42A W22 VCCDSW_3P31 BE49 0.113A
VCCDUSB_1P051 VCCDSW_3P32 +3VALW_DSW +3VALW_HDA 2 2
W23
+1.05VALW_PCH +1.05V_VCCDSW VCCDUSB_1P052 BB14 0.00767A
BG45 VCCHDA AG19
RH94 1 @ 2 0_0603_5% BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20 +1.8VALW_PRIM
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 0.766A Close to BB11
+1.05VALW_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PHVLDO +1.8VALW_PRIM
+1.05VALW_VCCAMPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A VCCPHVLDO_1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH95 1 @ 2 0_0402_5% (External VRM mode RH172 unmount)
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
+1.05VALW_PCH +1.05VALW_PCH +1.05V_VCCDSW VCCAMPHYPLL_1P053 AG31 0.193A
+1.05VALW_XTAL VCCPRIM_1P0520 +1.05VALW_PCH
0.00428A P2 AF31 0.0895A
VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05VALW_PCH
P3 AK22
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23 +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY
2 VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_IN 2
1U_0402_6.3V6K
1 W20 Short pins AJ22,AJ23,AK22,AK23 together

VCCA_SRC_1P052
.1U_0402_16V7K
.1U_0402_16V7K
1 1 AJ22 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71

VCCDPHY_1P241
CH31
0.0198A C1 AJ23 Internal LDO RH96 1 @ 2 0_0402_5%

VCCAPLL_1P054 VCCDPHY_1P242
CH29
CH30
C2 BG5
2 VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
0.0085A V19 RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
2 2 VCCA_BCLK_1P05 K47 VCCMPHY_SENSE
VCCMPHY_SENSE VSSMPHY_SENSE @ TH27
0.021A B1 K46 @ TH28
For DDX03 R02
B2 VCCAPLL_1P051 VSSMPHY_SENSE
B3 VCCAPLL_1P052 8 OF 13 +1.24V_PRIM_MAR
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0
place near VCCDUSB 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE EDGE
FOR W22/W23 VCCPRIM_MPHY W31 @
4.7U_0402_6.3V6M
1
CH32
+1.05VALW_PCH +1.05VALW_PCH 2
+1.05VALW_PCH
1U_0402_6.3V6K
.1U_0402_16V7K
1 1
+3VALW_PCH_PRIM
1U_0402_6.3V6K
1
+3VALW_PCH_PRIM +3VALW_PCH_PRIM
CH33
CH34
+3VALW +3VALW_PCH_PRIM +3VALW_PCH_PRIM +3VALW_SPI

CH35
2 2
2
1U_0402_6.3V6K
.1U_0402_16V7K
1 1
.1U_0402_16V7K
RH97 1 @ 2 0_0805_5% RH98 1 @ 2 0_0603_5% 1
.1U_0402_16V7K
CH37
CH38
1
CH36
1-5MM FROM PACKAGE EDGE 1-3MM FROM PACKAGE EDGE 1-5MM FROM PACKAGE EDGE 2 2
CH39
+1.8VALW +1.8VALW_PRIM
FOR VCCAPLL C1/C2 FOR VCCA_BCLK V19 FOR VCCAPLL B1/B2/B3 +3VALW_DSW 2
@ 2
RH99 1 @ 2 0_0402_5% RH100 1 @ 2 0_0603_5% @
.1U_0402_16V7K
1
CH40
3 3
1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE
2 FOR PGPPEF AE35/AE37 FOR PGPPHK AC35/AC36 FOR VCCPRIM AY8/BB7
+1.05VALW_PCH +3VALW_HDA
+1.05VALW_VCCAZPLL 0_0402_5% 2 @ 1 RH101
RH102 1 @ 2 0_0402_5%
1P_0402_50V8
1P_0402_50V8
1 1
1P_0402_50V8
1P_0402_50V8
CH41
CH42
1 1
CH43
CH44
2 2
@ @
2 2
@ @ reserve filter folloe CRB
8/21
1-3MM FROM PACKAGE EDGE
+1.05VALW_VCCAMPHYPLL
RH103 1 @ 2 0_0402_5%
22U_0402_6.3V6M
1U_0402_6.3V6K
1 1
CH45
CH46
2 2 DH2 +RTCVCC +RTCBATT

LC filter colse to pin JRTC1
@ 2
+CHGRTC
1uF 1-3MM FROM PACKAGE EDGE 1 1
RH104 2 1 10K_0402_5% 3 2 1
+RTCBATT 2
4 4
change to 10k BAV70W_SOT323-3 3
GND
1U_0402_6.3V6K
.1U_0402_16V7K
1 1 4
+1.05VALW_XTAL GND
CH47
CH48
ACES_50271-0020N-001
RH105 1 @ 2 0_0402_5% CONN@
2 2
SP02000RO00
22U_0402_6.3V6M
1
CH49
2 Issued Date 2017/07/20 Deciphered Date 2018/07/20 Title
@
PCH(7/8)Power
A B C D E
A B C D E
CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
A28 VSS VSS AL17 BG37 VSS VSS M34 RSVD8 U37
1 1
A3 VSS VSS AL21 BG4 VSS VSS M49 RSVD6 U35
A33 VSS VSS AL24 BG48 VSS VSS M5 RSVD5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD3 R32
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD2 AH14
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <11>
AA20 AN16 D30 P46 AM5 XDP_PRDY# <11>
AA25 VSS VSS AN34 D33 VSS VSS R12 PRDY# AM4 CPU_XDP_TRST#
VSS VSS VSS VSS CPU_TRST# PCH_TRIGOUT RH106 1 PCH_TRIGOUT_R CPU_XDP_TRST# <11>
AA27 AN38 D8 R16 AK3 2 30_0402_5%
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGOUT_R PCH_TRIGOUT_R <14>
AA28 AP4 E10 R26 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGOUT_R <14>
AA30 AP46 E13 R29
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
VSS VSS VSS VSS @
AB19 AR38 E22 R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0
4 4
2017/07/20
Compal Secret Data
2018/07/20 Title
PCH(8/8)GND/RSVD
A B C D E
5 4 3 2 1
CHANNEL-A BOT REVERSE TYPE

<8>
<8>
(4 mm)
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#0
137
139
JDIMM1A
CK0(T)
CK0#(C)
REVERSE
DQ0
DQ1
8
7
DDR_A_D0
DDR_A_D1
DDR_A_CLK1 DDR_A_D2
Interleaved Memory <8> DDR_A_CLK1 138 20

DDR_A_CLK#1 140 CK1(T) DQ2 21 DDR_A_D3
<8> DDR_A_CLK#1 CK1#(C) DQ3 DDR_A_D4
4
DDR_A_CKE0 109 DQ4 3 DDR_A_D5
<8> DDR_A_CKE0 DDR_A_CKE1 110 CKE0 DQ5 16 DDR_A_D6
TOP: JDIMM1 CONN Non-ECC DIMM <8> DDR_A_D[0..15]
<8>
<8>
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#0
DDR_A_CS#1
149
CKE1
S0#
DQ6
DQ7
DQS0(T)
17
13
DDR_A_D7
DDR_A_DQS0
DDR_A_DQS#0 DDR_A_DQS0 <8>
157 11
<8> DDR_A_D[16..31] <8> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <8>
D
162 D
+3VS +3VS +3VS 165 S2#/C0 28 DDR_A_D8
<8> DDR_A_D[32..47] S3#/C1 DQ8 29 DDR_A_D9
DDR_A_ODT0 155 DQ9 41 DDR_A_D10
<8> DDR_A_D[48..63] <8> DDR_A_ODT0 ODT0 DQ10
1
1
DDR_A_ODT1 161 42 DDR_A_D11
<8> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12
RD4 RD1 RD5 24
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
REVERSE <8> DDR_A_BG0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D14
<8> DDR_A_BG1 DDR_A_BA0 BG1 DQ14 DDR_A_D15
111 141 150 37
+1.2V_VDDQ +1.2V_VDDQ <8> DDR_A_BA0
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 112 VDD1 VDD11 142 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <8> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <8>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#1 <8>
VDD4 VDD14 <8> DDR_A_MA0 A0
1
1
123 153 DDR_A_MA1 133 50 DDR_A_D16
VDD5 VDD15 <8> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D17
RD3 RD6 RD2 124 154 132 49
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% 129 159 131 62
130 160 128 63
135 VDD8 VDD18 163 <8> DDR_A_MA4 DDR_A_MA5 126 A4 DQ19 46 DDR_A_D20
<8> DDR_A_MA5
2
2
+3VS 136 VDD9 VDD19 DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21
VDD10 <8> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D22
122 58
<8> DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D23
255 258 125 59
VDDSPD VTT +0.6VS_VTT <8> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
<8> DDR_A_MA9 DDR_A_MA10 A9 DQS2(T) DDR_A_DQS#2 DDR_A_DQS2 <8>
164 257 146 53
2.2U_0402_6.3V6M
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM +0.6V_DDR_VREFCA VREFCA VPP1 +2.5V <8> DDR_A_MA10 DDR_A_MA11 A10_AP DQS2#(C) DDR_A_DQS#2 <8>
.1U_0402_16V7K
2 2 259 120
VPP2 <8> DDR_A_MA11 DDR_A_MA12 A11 DDR_A_D24
CD1
119 70
<8> DDR_A_MA12 DDR_A_MA13 A12 DQ24 DDR_A_D25
CD2
1 99 158 71
VSS VSS <8> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D26
2 102 151 83
1 1 VSS VSS <8> DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE# DQ26 DDR_A_D27
5 103 156 84
SPD ADDRESS FOR CHANNEL A : 6 VSS
VSS
VSS
VSS
106 <8> DDR_A_MA15_CAS#
<8> DDR_A_MA16_RAS#
DDR_A_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66 DDR_A_D28
DDR_A_D29
9 107 67
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<8> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D30
DDR_A_D31
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172 <8> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <8>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 +1.2V_VDDQ RD7 2 <8>1 DDR_A_ALERT#
240_0402_1% DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D32
DDR_A_DQS#3 <8>
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
<19,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D33
DDR_A_D34 C
STRETCH GOAL IS 2133 MT/S 27

30
VSS
VSS
VSS
VSS
184
185 <19,24,47> D_CK_SDATA
254
253 SDA
DQ34
DQ35
186
170
DDR_A_D35
DDR_A_D36
VSS VSS <19,24,47> D_CK_SCLK SCL DQ36 DDR_A_D37
31 188 169
35 VSS VSS 189 SA2_CHA_DIM1 166 DQ37 183 DDR_A_D38
36 VSS VSS 192 SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_A_D39
Layout Note: Layout Note: VSS VSS SA0_CHA_DIM1 SA1 DQ39 DDR_A_DQS4
39 193 256 179
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 <8>
43 VSS VSS 197 DQS4#(C) DDR_A_DQS#4 <8>
44 VSS VSS 201 92 195 DDR_A_D40
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D41
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6VS_VTT 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*2 VSS VSS CB3_NC DQ43 DDR_A_D44
52 209 88 191
1uF*2 1uF*1 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D45
57 VSS VSS 213 For ECC DIMM 100 CB5_NC DQ45 203 DDR_A_D46
VSS VSS CB6_NC DQ46 DDR_A_D47
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 60 214 104 204

61 VSS VSS 217 97 CB7_NC DQ47 200 DDR_A_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_A_DQS#5 DDR_A_DQS5 <8>
CD3
CD4
CD5
CD6
CD7
CD8
CD9
64 218 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <8>
65 222
2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D49
72 VSS VSS 227 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D50
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D51
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <8>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <8>
89 244
VSS VSS
.1U_0402_16V7K
Layout Note: 90 247 2
VSS VSS
CD10
93 248
PLACE THE CAP near JDIMM1. 164 94 VSS VSS 251 237 DDR_A_D56
98 VSS VSS 252 DQ56 236 DDR_A_D57
B VSS VSS 1 DQ57 249 DDR_A_D58 B
@ DQ58 DDR_A_D59
262 261 250
GND GND DQ59 232 DDR_A_D60
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A DQ61 245 DDR_A_D62
2.2uF*1 DQ62 DDR_A_D63
CONN@ 246
0.1uF*1 PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
DQS7(T) 240 DDR_A_DQS#7 DDR_A_DQS7 <8>
2 2 DQS7#(C) DDR_A_DQS#7 <8>
CD11
.1U_0402_16V7K CD12
2.2U_0402_6.3V6M
1 1 LOTES_ADDR0206-P001A
CONN@
+1.2V_VDDQ
DIMM Side CPU Side
2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 2 1K_0402_1%
CD13 @
.1U_0402_16V7K
1
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
1uF*8 1 signals
+1.2V_VDDQ +1.2V_VDDQ 2
2
330uF*1 +1.2V_VDDQ CD14 CD15

RD10 .1U_0402_16V7K 0.022U_0402_16V7K
2
1K_0402_1%
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
A + CD32 RD11 A
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
330U_D2_2V_Y 24.9_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
@ @

DDRIV_CHA: DIMM0
5 4 3 2 1
5 4 3 2 1
CHANNEL-B BOT REVERSE TYPE (8 mm)

TOP: JDIMM3 CONN Non-ECC DIMM Interleaved Memory <9> DDR_B_D[0..15]
<9> DDR_B_CLK0
<9> DDR_B_CLK#0
<9> DDR_B_CLK1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
137
139
138
140
JDIMM2A
CK0(T)
CK0#(C)
CK1(T)
RESERVE
DQ0
DQ1
DQ2
8
7
20
21
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
<9> DDR_B_CLK#1 CK1#(C) DQ3 4 DDR_B_D4
+3VS +3VS +3VS <9> DDR_B_D[16..31] DDR_B_CKE0 109 DQ4 3 DDR_B_D5
<9> DDR_B_CKE0 DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D6
<9> DDR_B_D[32..47] <9> DDR_B_CKE1 CKE1 DQ6 17 DDR_B_D7
DQ7
1
1
DDR_B_CS#0 149 13 DDR_B_DQS0
D <9> DDR_B_D[48..63] <9> DDR_B_CS#0 DDR_B_CS#1 157 S0# DQS0(T) 11 DDR_B_DQS#0 DDR_B_DQS0 <9> D
RD12 RD13 RD14
<9> DDR_B_CS#1 162 S1# DQS0#(C) DDR_B_DQS#0 <9>
0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM2B
@ S2#/C0 DDR_B_D8
RESERVE 165 28
111 141 S3#/C1 DQ8 29 DDR_B_D9
+1.2V_VDDQ +1.2V_VDDQ
2
2
SA0_CHB_DIM3 SA1_CHB_DIM3 SA2_CHB_DIM3 112 VDD1 VDD11 142 DDR_B_ODT0 155 DQ9 41 DDR_B_D11
VDD2 VDD12 <9> DDR_B_ODT0 DDR_B_ODT1 ODT0 DQ10 DDR_B_D15
117 147 161 42
VDD3 VDD13 <9> DDR_B_ODT1 ODT1 DQ11
1
118 148 24 DDR_B_D14

VDD4 VDD14 DQ12
1
1
RD16 123 153 DDR_B_BG0 115 25 DDR_B_D10
124 VDD5 VDD15 154 <9> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D12
RD15 @ 0_0402_5% RD17
VDD6 VDD16 <9> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D13
@ 0_0402_5% @ 0_0402_5% 129 159 150 37
130 VDD7 VDD17 160 <9> DDR_B_BA0 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS1
<9> DDR_B_BA1 DDR_B_DQS1 <9>
2
135 VDD8 VDD18 163 BA1 DQS1(T) 32 DDR_B_DQS#1

DDR_B_DQS#1 <9>
2
2
+3VS 136 VDD9 VDD19 DDR_B_MA0 144 DQS1#(C)
VDD10 <9> DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D16
133 50
<9> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6VS_VTT <9> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
<9> DDR_B_MA3 DDR_B_MA4 A3 DQ18 DDR_B_D20
164 257 128 63
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 +2.5V <9> DDR_B_MA4 DDR_B_MA5 A4 DQ19 DDR_B_D22
.1U_0402_16V7K
2 2 259 126 46
VPP2 <9> DDR_B_MA5 DDR_B_MA6 A5 DQ20 DDR_B_D18
CD33
127 45
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM <9> DDR_B_MA6 DDR_B_MA7 A6 DQ21 DDR_B_D23
CD34
1 99 122 58
VSS VSS <9> DDR_B_MA7 DDR_B_MA8 A7 DQ22 DDR_B_D21
2 102 125 59
1 1 VSS VSS <9> DDR_B_MA8 DDR_B_MA9 A8 DQ23 DDR_B_DQS2
5 103 121 55
VSS VSS <9> DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 <9>
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107 <9> DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 <9>
VSS VSS <9> DDR_B_MA11 DDR_B_MA12 A11 DDR_B_D30
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168 <9> DDR_B_MA12 DDR_B_MA13
119
158 A12 DQ24
70
71 DDR_B_D25
VSS VSS <9> DDR_B_MA13 DDR_B_MA14_WE# A13 DQ25 DDR_B_D26
READ ADDRESS: 0XA3 15
18 VSS VSS
171
172 <9> DDR_B_MA14_WE#
<9> DDR_B_MA15_CAS#
DDR_B_MA15_CAS#
151
156 A14_WE# DQ26
83
84 DDR_B_D24
VSS VSS DDR_B_MA16_RAS# A15_CAS# DQ27 DDR_B_D28
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
<9> DDR_B_MA16_RAS#
152
A16_RAS# DQ28
DQ29
66
67 DDR_B_D27
23 180 DDR_B_ACT# 114 79 DDR_B_D29
DDR4 POR OPERATING SPEED: 1867 MT/S 26 VSS
VSS
VSS
VSS
181 <9> DDR_B_ACT#
DDR_B_PAR
ACT# DQ30
DQ31
80 DDR_B_D31
DDR_B_DQS3
27 184 143 76
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185 <9> DDR_B_PAR
<9> DDR_B_ALERT#
DDR_B_ALERT#
DIMM3_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
<9>
<9>
31 188 2 RD18 1 134
C 35 VSS VSS 189 +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D34 C
VSS VSS <19,23> DDR_DRAMRST#_R RESET# DQ32 DDR_B_D35
Layout Note: Layout Note: 36 192 173
39 VSS VSS 193 DQ33 187 DDR_B_D36
Place near JDIMM3.257,259 Place near JDIMM3.258 40 VSS VSS 196 254 DQ34 186 DDR_B_D32
VSS VSS <19,23,47> D_CK_SDATA SDA DQ35 DDR_B_D39
43 197 253 170
VSS VSS <19,23,47> D_CK_SCLK SCL DQ36 DDR_B_D38
44 201 169
47 VSS VSS 202 SA2_CHB_DIM3 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 SA1_CHB_DIM3 260 SA2 DQ38 182 DDR_B_D33
+2.5V +0.6VS_VTT 51 VSS VSS 206 SA0_CHB_DIM3 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 <9>
52 209 177
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <9>
57 VSS VSS 213 92 195 DDR_B_D40
VSS VSS CB0_NC DQ40 DDR_B_D41
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 60 214 91 194
61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_B_D42
VSS VSS CB2_NC DQ42 DDR_B_D43
CD35
CD36
CD37
CD38
CD39
CD40
CD41
64 218 105 208

2 2 2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190 DDR_B_D45
69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D46
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
77 VSS VSS 231 95 DQS8(T) DQS5(T) 198 DDR_B_DQS#5 DDR_B_DQS5 <9>
VSS VSS DQS8#(C) DQS5#(C) DDR_B_DQS#5 <9>
78 234
81 VSS VSS 235 216 DDR_B_D48
82 VSS VSS 238 12 DQ48 215 DDR_B_D52
85 VSS VSS 239
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D50
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D55
Layout Note: VSS VSS DM6#/DBI6# DQ55 DDR_B_DQS6
98 252 241 221
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 DDR_B_DQS6 <9>
FROM THE JDIMM3 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <9>
262 261
GND GND
B LOTES_ADDR0070-P009A 237 DDR_B_D61 B

DQ56 236 DDR_B_D57
CONN@ DQ57 DDR_B_D60
+0.6V_DDRB_VREFCA 249
2.2uF*1 DQ58 DDR_B_D56
250
0.1uF*1 DQ59 232 DDR_B_D62
DQ60 233 DDR_B_D59
2 2 DQ61 DDR_B_D63
CD42 245
.1U_0402_16V7K CD43 DQ62 246 DDR_B_D58
DQ63 242 DDR_B_DQS7
2.2U_0402_6.3V6M DQS7(T) DDR_B_DQS7 <9>
1 1 +1.2V_VDDQ 240 DDR_B_DQS#7
DQS7#(C) DDR_B_DQS#7 <9>
LOTES_ADDR0070-P009A
CONN@
2
Layout Note: CD44 @
DIMM Side CPU Side
2
.1U_0402_16V7K
Place near JDIMM3 RD19
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD20 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2 CD45 1
signals
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD51 RD21 .1U_0402_16V7K

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 .1U_0402_16V7K 1K_0402_1% CD55

1
CD46
CD47
CD48
CD49
CD50
CD52
CD53
CD54
0.022U_0402_16V7K
1 2
CD56
CD57
CD58
CD59
CD60
CD61
CD62
CD63
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RD22
24.9_0402_1%
@ @
1
DDRIV_CHB: DIMM0
5 4 3 2 1
5 4 3 2 1
UG1 UG1A
1/23 PCI_EXPRESS
+1.0VSDGPU
BB33
DGPU_PEX_RST# DGPU_PEX_RST#_R PEX_DVDD_1
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1 @ 2 BK26 BB35
<26,36> DGPU_PEX_RST# PEX_RST* PEX_DVDD_2
VGA@ CG7
N17E-G1 R1 RG1 0_0402_5% BB36 1 1 1 1 1 1 2 1
PEX_CLKREQ# PEX_DVDD_3
VGA@ CG1
VGA@ CG2
VGA@ CG3
VGA@ CG4
VGA@ CG5
VGA@ CG6
VGA@ CG8
VGA@ BL26 BC33
PEX_CLKREQ* PEX_DVDD_4 BC35
SA00009PM10 PEX_DVDD_5
BM26 BC36
<16> CLK_PEG_VGA BM27 PEX_REFCLK PEX_DVDD_6 BD33 2 2 2 2 2 2 1 2
D <16> CLK_PEG_VGA# PEX_REFCLK* PEX_DVDD_7 BD36 D
BG26 PEX_DVDD_8
+3VSDGPU +3VSDGPU <10> PEG_CRX_C_GTX_P0 BH26 PEX_TX0
<10> PEG_CRX_C_GTX_N0 PEX_TX0*
<10>
<10>
PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0
BL27
BK27 PEX_RX0
PEX_RX0*
Under GPU +1.8VSDGPU_MAIN
2
BF26
<10> PEG_CRX_C_GTX_P1 PEX_TX1
2
BE26 BB26
<10> PEG_CRX_C_GTX_N1 PEX_TX1* PEX_HVDD_1
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VGA@ RG2 RG3 VGA@ BB27
10K_0201_5% 10K_0201_5% BK29 PEX_HVDD_2 BB29
<10> PEG_CTX_C_GRX_P1 PEX_RX1 PEX_HVDD_3 1 1 1 1 1 1 2 2
1
VGA@ CG9
VGA@ CG10
VGA@ CG11
VGA@ CG12
VGA@ CG13
VGA@ CG14
VGA@ CG15
VGA@ CG16
VGA@ CG17
BL29 BB32
<10> PEG_CTX_C_GRX_N1
1 PEX_RX1* PEX_HVDD_4 BC26
1
BF27 PEX_HVDD_5 BC27
2
<10> PEG_CRX_C_GTX_P2 BG27 PEX_TX2 PEX_HVDD_6 BC29 2 2 2 2 2 2 1 1
<10> PEG_CRX_C_GTX_N2 PEX_TX2* PEX_HVDD_7
2
BC30
G
BM29 PEX_HVDD_8 BC32

PEX_CLKREQ# <10> PEG_CTX_C_GRX_P2 PEX_RX2 PEX_HVDD_9
1 3 BM30 BD27
<16> VGA_CLKREQ# <10> PEG_CTX_C_GRX_N2 PEX_RX2* PEX_HVDD_10 BD30
D
QG16
<10>
<10>
PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3
BG29
BH29 PEX_TX3
PEX_TX3*
PEX_HVDD_11
Under GPU
MESS138W-G_SOT323-3 BL30
<10> PEG_CTX_C_GRX_P3 PEX_RX3
VGA@ BK30
<10> PEG_CTX_C_GRX_N3 PEX_RX3*
BF29
<10> PEG_CRX_C_GTX_P4 BE29 PEX_TX4
BK32
BL32
BF30
C <10> PEG_CRX_C_GTX_P5 BG30 PEX_TX5 C
@
<10> PEG_CRX_C_GTX_N5 PEX_TX5* BB30 +PEX_PLL_HVDD 1 2
PEX_PLL_HVDD +1.8VSDGPU_MAIN
BM32 RM20 0_0402_5%
BM33 1
<10> PEG_CTX_C_GRX_N5 PEX_RX5* CG18 VGA@
BG32 0.1U_0201_10V6K
<10> PEG_CRX_C_GTX_P6 BH32 PEX_TX6
<10> PEG_CRX_C_GTX_N6 PEX_TX6* 2
BL33
BK33
BF32
BK35
BL35
BF33
<10> PEG_CRX_C_GTX_P8 BG33 PEX_TX8
BM35
BM36
BG35
BL36
BK36
BF35
<10> PEG_CRX_C_GTX_P10 BE35 PEX_TX10 22uF 10uF 4.7uF 1uF 0.1uF
B BK38 B
BL38
<10> PEG_CTX_C_GRX_N10 PEX_RX10* PEX_DVDD 1 1 2 4
BF36
<10> PEG_CTX_C_GRX_P11
BM38 PEX_HVDD 1 2 2 4
BM39 PEX_RX11
BG38
BL39
BK39
BF38
BK41
BL41
BF39
BM41
BM42
BH41
BL42 BL44 PEX_TERMP 2 1
<10> PEG_CTX_C_GRX_P15 PEX_RX15 PEX_TERMP
BK42
A <10> PEG_CTX_C_GRX_N15 PEX_RX15* A
RG4
2.49K_0402_1%
VGA@
@ N17E-G1_BGA2152~D

N17E-G1(1/8) PCIE
5 4 3 2 1
5 4 3 2 1
UG1W
13/23 MISC 1
NV Carter :Use Main power to prevent Hang issue
+1.8VSDGPU_AON BG5 BJ8 VGA_SMB_CK2 +1.8VSDGPU_MAIN
<36> OVERT# OVERT I2CS_SCL BH8 VGA_SMB_DA2
+1.8VSDGPU_AON I2CS_SDA
1
BF12
RG180 VGA@ TS_VREF BG9 I2CC_SCL_R
10K_0402_5% I2CC_SCL BH9 I2CC_SDA_R +1.8VSDGPU_AON
I2CC_SDA
5
VGA@ CG340 QG3A VGA@
2 1 PJT138KA_SOT363-6
G
2
HDMI_HPD_GPU# BG8 RG5 1 VGA@ 2 1.8K_0402_5% VGA_SMB_CK2 4 3
I2CB_SCL PCH_SML1CLK <19,43,44,48>
D
0.1U_0201_10V6K BF8 RG6 1 VGA@ 2 1.8K_0402_5%
I2CB_SDA
2
QG3B VGA@
D PJT138KA_SOT363-6 D
G
VCC
1
HDMI_HPD_PCH 1 D BJ1 VGA_SMB_DA21 6
<17,38> HDMI_HPD_PCH IN B 4 2 MESS138W-G_SOT323-3 THERMDN PCH_SML1DATA <19,43,44,48>
D
DGPU_PEX_RST# 2 OUT Y G QG5 VGA@ BJ2
GND
IN A S
THERMDP
3
+1.8VSDGPU_AON
3
VGA@ UG28 BD6 DG1 VGA@ +1.8VSDGPU_MAIN
GPIO0 NVVDD1_VID <65>
1.8K_0402_1%
1.8K_0402_1%
VGA@ RG8
VGA@ RG9
NL17SZ08DFT2G_SC70-5 BB5 RB751S40T1G_SOD523-2
GPIO1 GPU_GC6_FB_EN 2 <36>
1
BD1 GPU_EVENT#_1 1
GPIO2 BE4 GPU_EVENT# <20>
GPIO3 BE1 NVVDD2_VID <68>
GPIO4 1.8VSDGPU_MAIN_EN <36>
5
RG198 1 @ 2 0_0402_5% BG2 QG4A VGA@
GPIO5 BD2 PJT138KA_SOT363-6
G
2
2
GPIO6 BD7 GPU_INV_PWM NVVDD1_PSI <65,68> I2CC_SCL_R 4 3
JTAG_TCLK GPIO7 I2CC_SCL <36>
D
@ T38 PAD~D BK24 BH4
JTAG_TCK GPIO8 MEM_VDD_CTL <63>
2
@ T39 PAD~D JTAG_TMS BL23 BJ3 ALERT# QG4B VGA@
@ T40 PAD~D JTAG_TDI BM23 JTAG_TMS GPIO9 BD3 PJT138KA_SOT363-6
G
JTAG_TDO BM24 JTAG_TDI GPIO10 BH3 GPU_ENVDD MEM_VREF <33,34,35> I2CC_SDA_R 1 6
@ T41 PAD~D I2CC_SDA <36>
JTAG_TRST# JTAG_TDO GPIO11 ACIN_BUF
D
BL24 BE6 2 1
JTAG_TRST* GPIO12 BB1 GPU_ENBKL DGPU_AC_DETECT <20,43,54>
DG9 VGA@
GPIO13 BG4 RB751S40T1G_SOD523-2
GPIO14 BG1
+1.8VSDGPU_AON BK23 GPIO15 BE2
NV Carter : ALERT# no function no need
NVJTAG_SEL GPIO16 BH1 GPU_EDP_HPD# DGPU_PEX_RST#
GPIO17
1
BE3
GPIO18
1
1 RG16 VGA@ BD4
CG19 NGPK@ VGA@ RG15 10K_0201_5% GPIO19 BE5
GPIO20
2
G
0.1U_0201_10V6K 10K_0201_5% BA5
GPIO21 BB6
2
2 GPIO22 BG3 GPU_PEX_RST_HOLD# ALERT# 3 1
2
GPIO23 GPU_ALERT <43>
5
BD5
D
C GPIO24 BB2 @ C
VCC
1 GPIO25 BE7
<20,36> DGPU_HOLD_RST# IN B 4 GPIO26 BA4 HDMI_HPD_GPU# QG15
2 OUT Y DGPU_PEX_RST# <25,36> GPIO27 BB4 OC_WARN# MESS138W-G_SOT323-3
GND
<17,19,36,43,49> PLT_RST# IN A GPIO28 BA3 OC_WARN# <36>

UG6 GPIO29 BB3
NL17SZ08DFT2G_SC70-5 GPIO30 BA2 +1.8VSDGPU_AON
3
NGPK@ GPIO31 BA1

GPIO32 GPU_EVENT#_1 RG13 1 VGA@ 2 10K_0201_5%
@ N17E-G1_BGA2152~D DGPU_HOLD_RST# RG17 1 @ 2 10K_0201_5%
+1.8VSDGPU_AON GPU_PEX_RST_HOLD# RG18 1 VGA@ 2 10K_0201_5%

<36> 1.8VSDGPU_MAIN_EN3V3 ACIN_BUF 1 VGA@ 2
1 RG19 100K_0201_5%
+3VS CG920 NGPK@
UG103 NGPK@ 0.1U_0201_10V6K VGA_SMB_CK2 RG20 1 VGA@ 2 1.8K_0402_5%
5
NL17SZ08DFT2G_SC70-5
<36,43> GPU_OVERT# 2 VGA_SMB_DA2 1 VGA@ 2
RG21 1.8K_0402_5%
VCC
1
<20,36> DGPU_PWR_EN IN B
2
4 NVVDD1_PSI RG23 1 VGA@ 2 10K_0201_5%

1 2 2 OUT Y NVVDD2_EN <36,68>
+1.8VSDGPU_AON +1.8VSDGPU_MAIN RG183
GND
DG4 IN A ALERT# RG25 1 @ 2 10K_0201_5%
10K_0201_5%
NGPK@ RB751S40T1G_SOD523-2 DG3 NGPK@
1
RB751S40T1G_SOD523-2 OC_WARN# RG26 1 VGA@ 2 10K_0201_5%
1
3
2
1 2 1 2 RG202
1
RG39 RG182 RG190 DGPU_PEX_RST# RG201 1 GPK@ 2 10K_0201_5%

1 0_0201_5%
10K_0201_5% 100K_0201_5% NGPK@ 16.9K_0402_1% @ RG179 GPK@
VGA@ NGPK@ CG928 NGPK@ 1.8VSDGPU_MAIN_EN RG179 1 NGPK@ 2 2.2K_0402_5%
NGPK@
2
6
0.22U_0402_16V7K
1
2
D
2 1VSDGPU_EN <36,64>
G
QG12B
2
S
PJT138KA_SOT363-6
B NGPK@ GPU_GC6_FB_EN RG27 1 VGA@ 2 10K_0201_5% B
1
10K_0402_5%
3
DG5 MEM_VREF RG28 1 VGA@ 2 100K_0201_5% SD028100280

5
D
OVERT# G
QG12A RB751S40T1G_SOD523-2 Reserve for DIS only. DGPU_PEX_RST# RG30 1 NGPK@ 2 1M_0402_5%
S
PJT138KA_SOT363-6
NGPK@ 2 1
4
NVVDD1_EN <36,65>
NGPK@
+LCDVDD
1 2 +1.8VSDGPU_AON +1.8VSDGPU_AON
+1.8VSDGPU_AON RG191 1
1
+1.8VSDGPU_AON 1.5K_0402_1%
NGPK@ CG929 NGPK@ RG216 RG215
.1U_0402_16V7K 10K_0201_5% 10K_0201_5%
1
2
0.1U_0201_10V6K
1 DIS@ DIS@
2
CG20
NGPK@
RG45 NGPK@
2
DG2 GPU_EDP_HPD#
10K_0201_5%
G
2 GPU_INV_PWM 1 6
<64> 1VSDGPU_PG PCH_BKL_PWM <18,37>
5
2 1
D
2
+3VS GC6_FB_EN3V3 3 1.35VSDGPU_EN <36,63>

QG22B DIS@
VCC
1
DGPU_PEX_RST# D
1 PJT138KA_SOT363-6
IN B 4 5 G
D
QG7A NGPK@ BAV70W_SOT323-3 RG29 NGPK@ 2
OUT Y EDP_HPD_R <37>
1
2 PJT138KA_SOT363-6 100K_0201_5% G
GND
NGPK@
S
IN A RG31 S
4
3
UG8 NGPK@ +3VS 10K_0201_5% GPU_ENVDD RG217 2 DIS@ 1 0_0201_5% QG23 DIS@
2
PCH_ENVDD <18,37>
1 NL17SZ08DFT2G_SC70-5 NGPK@ MESS138W-G_SOT323-3
3
6
@ CG937
2
1
GPU_GC6_FB_EN 2 G
D
0.1U_0201_10V6K +3VS
GC6_FB_EN3V3 <20,36> +1.8VSDGPU_AON
S RG34
2 100K_0201_5%
1
1
NGPK@ QG7B NGPK@
6
PJT138KA_SOT363-6 RG214 GPU_INV_PWM RG218 1 DIS@ 2 100K_0201_5%

2
A 2 A
D
G
QG14B NGPK@ 10K_0201_5%
5
DG7 DIS@ GPU_ENVDD RG219 1 DIS@ 2 100K_0201_5%

S
PJT138KA_SOT363-6
RB751S40T1G_SOD523-2
G
1
2
NGPK@ GPU_ENBKL 4 3 GPU_ENBKL RG220 1 DIS@ 2 100K_0201_5%
ENBKL <18,43>
3
1 2
<36,65> NVVDD1_PG GPU_GC6_FB_EN 5 D
G
QG22A DIS@
S PJT138KA_SOT363-6
<36,68> NVVDD2_PG
NGPK@ QG14A
4
PJT138KA_SOT363-6
N17E-G1(2/8) GPIO
5 4 3 2 1
5 4 3 2 1
UG1N UG1V UG1U

11/23 MIOA 12/23 MIOB
7/23 IFPAB
AN9 AT3
MIOA_D0 AM2 MIOB_D0 AV6
DL-DVI DVI/HDMI DP
MIOA_D1 AN7 MIOB_D1 AT2
MIOA_D2 AN6 MIOB_D2 AT1
BH11 MIOA_D3 AR1 MIOB_D3 AW6
SDA SDA IFPA_AUX_SDA* BG11 MIOA_D4 AR6 MIOB_D4 AV2
SCL SCL IFPA_AUX_SCL MIOA_D5 MIOB_D5
AR5 AV1
RG51 VGA@ MIOA_D6 AM8 MIOB_D6 AV3
1K_0402_1% BF21 MIOA_D7 AN3 MIOB_D7 AW3
2 1 IFPAB_RSET BD23 TXC TXC IFPA_L3* BG21 MIOA_D8 AR8 MIOB_D8 BA8
IFPAB_RSET TXC TXC IFPA_L3 MIOA_D9 AR3 MIOB_D9 AW7
+IFPX_PLLVDD AM5 MIOA_D10 AR2 AV7 MIOB_D10 BB8
D BG23 MIOA_CAL_PD_VDDQ MIOA_D11 MIOB_CAL_PD_VDDQ MIOB_D11 D
TXD0 TXD0 IFPA_L2* BH23 AM6 AV8
TXD0 TXD0 IFPA_L2 MIOA_CAL_PU_GND MIOB_CAL_PU_GND
BD21
IFPAB_PLLVDD
BF23
TXD1 TXD1 IFPA_L1*
0.1U_0201_10V6K
BE23 AM7 AW9
TXD1 TXD1 IFPA_L1 MIOA_VREF MIOB_VREF
1
VGA@ CG21
TXD2 TXD2
BF24
IFPA_L0* BG24
TXD2 TXD2 IFPA_L0
2
AT7 BB7
MIOA_CTL3 AM1 MIOB_CTL3 AV5
MIOA_HSYNC AR7 MIOB_HSYNC BA7
MIOA_VSYNC AN1 MIOB_VSYNC AW2
MIOA_DE MIOB_DE
Under GPU SDA IFPB_AUX_SDA*
BG12
BH12 GP104 GP106
SCL IFPB_AUX_SCL AN2 AW1
MIOA_CLKOUT MIOB_CLKOUT
BL18 AM3 MIOB UNUSED AT6
BB17 TXC IFPB_L3* BK18 MIOA_CLKIN MIOB_CLKIN
+1.0VSDGPU BB15 IFP_IOVDD_2 TXC IFPB_L3
IFP_IOVDD_1 @ N17E-G1_BGA2152~D @ N17E-G1_BGA2152~D
BB18 BK20
IFP_IOVDD_3 TXD3 TXD0 IFPB_L2*
BB20 BL20 UG1O
IFP_IOVDD_4 TXD3 TXD0 IFPB_L2
6/23 IFPF
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
Under GPU
VGA@ CG930
1 1 1 1 1 BM20 DVI/HDMI DP
TXD4 TXD1 IFPB_L1*
VGA@ CG22
VGA@ CG23
VGA@ CG24
VGA@ CG25 TXD4 TXD1

BM21
IFPB_L1 +1.0VSDGPU
BC21 BM9
C 2 2 2 2 2 IFP_IOVDD_11 SDA IFPF_AUX_SDA* C
TXD5 TXD2
BL21 BC23 SCL
BM8
IFPB_L0* BK21 IFP_IOVDD_12 IFPF_AUX_SCL
TXD5 TXD2 IFPB_L0
IFPAB
1U_0402_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
BK11
TXC IFPF_L3*
VGA@ CG924
VGA@ CG931
1 1 1 BL11
TXC IFPF_L3
VGA@ CG26
@ N17E-G1_BGA2152~D BM11
Under GPU 2 2 2
TXD0
TXD0
IFPF_L2*
IFPF_L2
BM12
UG1R BL12
TXD1 IFPF_L1*
RG52 VGA@ 8/23 IFPC BK12
TXD1 IFPF_L1
1K_0402_1%
2 1 IFPCD_RSET BD20 BK14
IFPCD_RSET TXD2 IFPF_L0*
DVI/HDMI DP IFPF TXD2 IFPF_L0
BL14
+IFPX_PLLVDD
BD18 BL9
GPU_DP3_CTRL_DAT <38>
IFPCD_PLLVDD SDA
SCL
IFPC_AUX_SDA*
IFPC_AUX_SCL
BK9
GPU_DP3_CTRL_CLK <38> HDMI 2.0
0.1U_0201_10V6K
@ N17E-G1_BGA2152~D
1 UG1P
VGA@ CG27
BF17 10/23 IFPE

TXC IFPC_L3* GPU_DP3_N3 <38>
BE17
TXC IFPC_L3 GPU_DP3_P3 <38> DVI/HDMI DP
RG53 VGA@
2 BF18 1K_0402_1%
TXD0 IFPC_L2* GPU_DP3_N2 <38> IFPEF_RSET
BG18 2 1 BD17 SDA BL8
TXD0 IFPC_L2 GPU_DP3_P2 <38> IFPEF_RSET IFPE_AUX_SDA* BK8
IFPC BG20 +1.8VSDGPU_MAIN +IFPX_PLLVDD
SCL IFPE_AUX_SCL
TXD1
TXD1
IFPC_L1*
IFPC_L1
BH20
GPU_DP3_N1
GPU_DP3_P1
<38>
<38> Under GPU BG14
Under GPU TXD2 IFPC_L0*
BF20
BE20
GPU_DP3_N0 <38>
1 2 BD15
IFPEF_PLLVDD
TXC
TXC
IFPE_L3*
IFPE_L3
BH14
+1.0VSDGPU TXD2 IFPC_L0 GPU_DP3_P0 <38>
22U_0603_6.3V6M
0.1U_0201_10V6K
4.7U_0402_6.3V6M
LG2 VGA@ BF14
TXD0 IFPE_L2*
VGA@ CG921
B PBY160808T-300Y-N_2P BE14 B
1 1 TXD0 IFPE_L2
VGA@ CG28
VGA@ CG30
BB21
IFP_IOVDD_5 SM01000HU00
1U_0402_6.3V6K
BB23 TXD1 BF15

IFP_IOVDD_6 IFPE_L1*
VGA@ CG934
0.1U_0201_10V6K
0.1U_0201_10V6K
1 TXD1 BG15
2
2 2 IFPE_L1
IFPE
VGA@ CG926
1 1
VGA@ CG29
@ N17E-G1_BGA2152~D BG17
TXD2 IFPE_L0*
TXD2 BH17
2 IFPE_L0
2 2 UG1Q
9/23 IFPD +1.0VSDGPU
BC18
BC20 IFP_IOVDD_9
IFP_IOVDD_10
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
DVI/HDMI DP
VGA@ CG933
Under GPU 1 1 1
VGA@ CG31
VGA@ CG32
BF11 @ N17E-G1_BGA2152~D
SDA IFPD_AUX_SDA* BE11 GPU_EDP_AUXN <7>
SCL IFPD_AUX_SCL GPU_EDP_AUXP <7> 2 2 2
TXC BM14
GPU_EDP_TXN3 <7>
22uF 10uF 4.7uF 1uF 0.1uF
IFPD_L3* BM15
TXC IFPD_L3 GPU_EDP_TXP3 <7>
BL15
TXD0
TXD0
IFPD_L2* BK15
GPU_EDP_TXN2
GPU_EDP_TXP2
<7>
<7> IFPx_IOVDD 3 3 12
IFPD_L2
IFPD
TXD1 IFPD_L1*
BK17
BL17
GPU_EDP_TXN1 <7> Under GPU
TXD1
IFPD_L1 GPU_EDP_TXP1 <7>
IFPx_PLLVDD 1 1 3
BM17
TXD2 IFPD_L0* GPU_EDP_TXN0 <7>
BM18
TXD2 IFPD_L0 GPU_EDP_TXP0 <7>
A
+1.0VSDGPU Under GPU BC15 A
BC17 IFP_IOVDD_7
IFP_IOVDD_8
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
VGA@ CG932
1 1 1
VGA@ CG33
VGA@ CG34
@ N17E-G1_BGA2152~D
2 2 2
N17E-G1(3/8) eDP,HDMI,mDP
5 4 3 2 1
5 4 3 2 1
UG1B
2/23 FBA UG1C
3/23 FBB
U51 Y51
<33> FBA_D0 U48 FBA_D0 FBA_CMD0 Y52 FBA_CMD1 FBA_CMD0 <33> H32 B35
<33> FBA_D1 U50 FBA_D1 FBA_CMD1 Y49 FBA_CMD2 FBA_CMD1 <33> <34> FBB_D0 D32 FBB_D0 FBB_CMD0 A35 FBB_CMD1 FBB_CMD0 <34>
<33> FBA_D2 U49 FBA_D2 FBA_CMD2 AA52 FBA_CMD2 <33> <34> FBB_D1 A33 FBB_D1 FBB_CMD1 D35 FBB_CMD2 FBB_CMD1 <34>
<33> FBA_D3 R51 FBA_D3 FBA_CMD3 AA51 FBA_CMD3 <33> <34> FBB_D2 B32 FBB_D2 FBB_CMD2 A36 FBB_CMD2 <34>
<33> FBA_D4 R50 FBA_D4 FBA_CMD4 AA50 FBA_CMD4 <33> <34> FBB_D3 E32 FBB_D3 FBB_CMD3 B36 FBB_CMD3 <34>
<33> FBA_D5 R47 FBA_D5 FBA_CMD5 AC50 FBA_CMD5 <33> <34> FBB_D4 G32 FBB_D4 FBB_CMD4 C36 FBB_CMD4 <34>
<33> FBA_D6 U46 FBA_D6 FBA_CMD6 AC51 FBA_CMD6 <33> <34> FBB_D5 J30 FBB_D5 FBB_CMD5 C38 FBB_CMD5 <34>
<33> FBA_D7 V46 FBA_D7 FBA_CMD7 AC52 FBA_CMD7 <33> <34> FBB_D6 F32 FBB_D6 FBB_CMD6 B38 FBB_CMD6 <34>
<33> FBA_D8 Y45 FBA_D8 FBA_CMD8 AC49 FBA_CMD8 <33> <34> FBB_D7 H36 FBB_D7 FBB_CMD7 A38 FBB_CMD7 <34>
<33> FBA_D9 Y47 FBA_D9 FBA_CMD9 AD52 FBA_CMD9 <33> <34> FBB_D8 G36 FBB_D8 FBB_CMD8 D38 FBB_CMD8 <34>
<33> FBA_D10 Y46 FBA_D10 FBA_CMD10 AD51 FBA_CMD10 <33> <34> FBB_D9 J36 FBB_D9 FBB_CMD9 A39 FBB_CMD9 <34>
D <33> FBA_D11 V50 FBA_D11 FBA_CMD11 AD50 FBA_CMD11 <33> <34> FBB_D10 F36 FBB_D10 FBB_CMD10 B39 FBB_CMD10 <34> D
<33> FBA_D12 V47 FBA_D12 FBA_CMD12 AF50 FBA_CMD12 <33> <34> FBB_D11 F33 FBB_D11 FBB_CMD11 C39 FBB_CMD11 <34>
<33> FBA_D13 U52 FBA_D13 FBA_CMD13 AF51 FBA_CMD13 <33> <34> FBB_D12 D33 FBB_D12 FBB_CMD12 C41 FBB_CMD12 <34>
<33> FBA_D14 V51 FBA_D14 FBA_CMD14 AF52 FBA_CMD14 <33> <34> FBB_D13 J32 FBB_D13 FBB_CMD13 B41 FBB_CMD13 <34>
<33> FBA_D15 AJ44 FBA_D15 FBA_CMD15 AN50 FBA_CMD15 <33> <34> FBB_D14 G33 FBB_D14 FBB_CMD14 A41 FBB_CMD14 <34>
<33> FBA_D16 AG48 FBA_D16 FBA_CMD16 AN51 FBA_CMD17 FBA_CMD16 <33> <34> FBB_D15 E45 FBB_D15 FBB_CMD15 B49 FBB_CMD15 <34>
<33> FBA_D17 AJ45 FBA_D17 FBA_CMD17 AN52 FBA_CMD18 FBA_CMD17 <33> <34> FBB_D16 D45 FBB_D16 FBB_CMD16 A49 FBB_CMD17 FBB_CMD16 <34>
<33> FBA_D18 AG49 FBA_D18 FBA_CMD18 AM49 FBA_CMD18 <33> <34> FBB_D17 F45 FBB_D17 FBB_CMD17 A48 FBB_CMD18 FBB_CMD17 <34>
<33> FBA_D19 AF46 FBA_D19 FBA_CMD19 AM52 FBA_CMD19 <33> <34> FBB_D18 G45 FBB_D18 FBB_CMD18 D47 FBB_CMD18 <34>
<33> FBA_D20 AF47 FBA_D20 FBA_CMD20 AM51 FBA_CMD20 <33> <34> FBB_D19 D42 FBB_D19 FBB_CMD19 A47 FBB_CMD19 <34>
<33> FBA_D21 AF48 FBA_D21 FBA_CMD21 AM50 FBA_CMD21 <33> <34> FBB_D20 E42 FBB_D20 FBB_CMD20 B47 FBB_CMD20 <34>
<33> FBA_D22 AD47 FBA_D22 FBA_CMD22 AK50 FBA_CMD22 <33> <34> FBB_D21 F42 FBB_D21 FBB_CMD21 C47 FBB_CMD21 <34>
<33> FBA_D23 AD49 FBA_D23 FBA_CMD23 AK51 FBA_CMD23 <33> <34> FBB_D22 H41 FBB_D22 FBB_CMD22 C45 FBB_CMD22 <34>
<33> FBA_D24 AD48 FBA_D24 FBA_CMD24 AK52 FBA_CMD24 <33> <34> FBB_D23 E41 FBB_D23 FBB_CMD23 B45 FBB_CMD23 <34>
<33> FBA_D25 AC46 FBA_D25 FBA_CMD25 AJ49 FBA_CMD25 <33> <34> FBB_D24 F39 FBB_D24 FBB_CMD24 A45 FBB_CMD24 <34>
<33> FBA_D26 AC47 FBA_D26 FBA_CMD26 AJ52 FBA_CMD26 <33> <34> FBB_D25 E39 FBB_D25 FBB_CMD25 D44 FBB_CMD25 <34>
<33> FBA_D27 AA47 FBA_D27 FBA_CMD27 AJ51 FBA_CMD27 <33> <34> FBB_D26 D39 FBB_D26 FBB_CMD26 A44 FBB_CMD26 <34>
<33> FBA_D28 AA46 FBA_D28 FBA_CMD28 AJ50 FBA_CMD28 <33> <34> FBB_D27 F38 FBB_D27 FBB_CMD27 B44 FBB_CMD27 <34>
<33> FBA_D29 AA45 FBA_D29 FBA_CMD29 AG50 FBA_CMD29 <33> +1.35VSDGPU <34> FBB_D28 E38 FBB_D28 FBB_CMD28 C44 FBB_CMD28 <34>
<33> FBA_D30 Y44 FBA_D30 FBA_CMD30 AG51 FBA_CMD30 <33> <34> FBB_D29 D36 FBB_D29 FBB_CMD29 C42 FBB_CMD29 <34> +1.35VSDGPU
<33> FBA_D31 AW51 FBA_D31 FBA_CMD31 AG52 FBA_CMD31 <33> <34> FBB_D30 E36 FBB_D30 FBB_CMD30 B42 FBB_CMD30 <34>
<33> FBA_D32 BA52 FBA_D32 FBA_CMD32 AF49 <34> FBB_D31 M50 FBB_D31 FBB_CMD31 A42 FBB_CMD31 <34>
<33> FBA_D33 AW50 FBA_D33 FBA_CMD33 Y50 1 2 60.4_0402_1% <34> FBB_D32 P48 FBB_D32 FBB_CMD32 D41
RG184 @
<33> FBA_D34 BA51 FBA_D34 FBA_CMD34 AR50 1 2 60.4_0402_1% <34> FBB_D33 M51 FBB_D33 FBB_CMD33 C35 1 2 60.4_0402_1%
RG185 @ RG186 @
<33> FBA_D35 BA50 FBA_D35 FBA_CMD35 <34> FBB_D34 M49 FBB_D34 FBB_CMD34 B50 1 2 60.4_0402_1%
@
<33> FBA_D36 BB50 FBA_D36 <34> FBB_D35 P47 FBB_D35 FBB_CMD35 RG187
<33> FBA_D37 BA49 FBA_D37 <34> FBB_D36 P52 FBB_D36
<33> FBA_D38 AW49 FBA_D38 AA44 <34> FBB_D37 R46 FBB_D37
<33> FBA_D39 AV48 FBA_D39 FBA_DBG_RFU1 AN44 <34> FBB_D38 P46 FBB_D38 J35
<33> FBA_D40 AT49 FBA_D40 FBA_DBG_RFU2 <34> FBB_D39 L50 FBB_D39 FBB_DBG_RFU1 J41
<33> FBA_D41 AT47 FBA_D41 <34> FBB_D40 L51 FBB_D40 FBB_DBG_RFU2
<33> FBA_D42 AT48 FBA_D42 <34> FBB_D41 L52 FBB_D41
C <33> FBA_D43 AT46 FBA_D43 AG45 <34> FBB_D42 L49 FBB_D42 C
<33> FBA_D44 AV51 FBA_D44 FBA_CLK0 AG46 FBA_CLK0 <33> <34> FBB_D43 M46 FBB_D43 H42
<33> FBA_D45 AV52 FBA_D45 FBA_CLK0* AK46 FBA_CLK0# <33> <34> FBB_D44 L47 FBB_D44 FBB_CLK0 G42 FBB_CLK0 <34>
<33> FBA_D46 AV49 FBA_D46 FBA_CLK1 AK45 FBA_CLK1 <33> <34> FBB_D45 M48 FBB_D45 FBB_CLK0* F47 FBB_CLK0# <34>
<33> FBA_D47 AJ48 FBA_D47 FBA_CLK1* FBA_CLK1# <33> <34> FBB_D46 M47 FBB_D46 FBB_CLK1 E47 FBB_CLK1 <34>
<33> FBA_D48 AJ46 FBA_D48 <34> FBB_D47 D48 FBB_D47 FBB_CLK1* FBB_CLK1# <34>
<33> FBA_D49 AJ47 FBA_D49 <34> FBB_D48 C50 FBB_D48
<33> FBA_D50 AK49 FBA_D50 <34> FBB_D49 C48 FBB_D49
<33> FBA_D51 AM47 FBA_D51 <34> FBB_D50 C49 FBB_D50
<33> FBA_D52 AM46 FBA_D52 <34> FBB_D51 E49 FBB_D51
<33> FBA_D53 AN48 FBA_D53 <34> FBB_D52 E50 FBB_D52
<33> FBA_D54 AN49 FBA_D54 <34> FBB_D53 F49 FBB_D53
<33> FBA_D55 AM44 FBA_D55 U45 <34> FBB_D54 F48 FBB_D54
<33> FBA_D56 AM45 FBA_D56 FBA_WCK01 U44 FBA_WCK01 <33> <34> FBB_D55 F50 FBB_D55 J33
<33> FBA_D57 AN45 FBA_D57 FBA_WCK01* V45 FBA_WCK01# <33> <34> FBB_D56 D52 FBB_D56 FBB_WCK01 H33 FBB_WCK01 <34>
<33> FBA_D58 AN46 FBA_D58 FBA_WCKB01 V44 <34> FBB_D57 J50 FBB_D57 FBB_WCK01* G35 FBB_WCK01# <34>
<33> FBA_D59 AR48 FBA_D59 FBA_WCKB01* AC45 <34> FBB_D58 H48 FBB_D58 FBB_WCKB01 H35
<33> FBA_D60 AN47 FBA_D60 FBA_WCK23 AC44 FBA_WCK23 <33> <34> FBB_D59 H51 FBB_D59 FBB_WCKB01* J39
<33> FBA_D61 AR47 FBA_D61 FBA_WCK23* AD46 FBA_WCK23# <33> <34> FBB_D60 J51 FBB_D60 FBB_WCK23 H39 FBB_WCK23 <34>
<33> FBA_D62 AR46 FBA_D62 FBA_WCKB23 AD45 <34> FBB_D61 H49 FBB_D61 FBB_WCK23* F41 FBB_WCK23# <34>
<33> FBA_D63 FBA_D63 FBA_WCKB23* AV47 <34> FBB_D62 H52 FBB_D62 FBB_WCKB23 G41
FBA_WCK45 AV46 FBA_WCK45 <33> <34> FBB_D63 FBB_D63 FBB_WCKB23* L46
U47 FBA_WCK45* AW48 FBA_WCK45# <33> FBB_WCK45 L45 FBB_WCK45 <34>
<33> FBA_DBI0 Y48 FBA_DQM0 FBA_WCKB45 AW47 C32 FBB_WCK45* M44 FBB_WCK45# <34>
<33> FBA_DBI1 AG47 FBA_DQM1 FBA_WCKB45* AR45 <34> FBB_DBI0 E33 FBB_DQM0 FBB_WCKB45 M45
<33> FBA_DBI2 AC48 FBA_DQM2 FBA_WCK67 AR44 FBA_WCK67 <33> <34> FBB_DBI1 E44 FBB_DQM1 FBB_WCKB45* H47
<33> FBA_DBI3 BB51 FBA_DQM3 FBA_WCK67* AT45 FBA_WCK67# <33> <34> FBB_DBI2 G39 FBB_DQM2 FBB_WCK67 H46 FBB_WCK67 <34>
<33> FBA_DBI4 AV50 FBA_DQM4 FBA_WCKB67 AT44 <34> FBB_DBI3 P49 FBB_DQM3 FBB_WCK67* J47 FBB_WCK67# <34>
<33> FBA_DBI5 <34> FBB_DBI4
<33>
<33>
FBA_DBI6
FBA_DBI7
AM48
AR49
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_WCKB67*
Under GPU <34>
<34>
FBB_DBI5
FBB_DBI6
L48
D50
H50
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_WCKB67
FBB_WCKB67*
J46
<34> FBB_DBI7 FBB_DQM7

B R48 B
<33> FBA_EDC0 V48 FBA_DQS_WP0 B33 +1.35VSDGPU
<33> FBA_EDC1 AF44 FBA_DQS_WP1 +FBX_PLLAVDD <34> FBB_EDC0 E35 FBB_DQS_WP0
<33> FBA_EDC2 AA48 FBA_DQS_WP2 <34> FBB_EDC1 G44 FBB_DQS_WP1 +FBX_PLLAVDD
<33> FBA_EDC3 BB52 FBA_DQS_WP3 +1.8VSDGPU_MAIN <34> FBB_EDC2 H38 FBB_DQS_WP2
<33> FBA_EDC4 AT50 FBA_DQS_WP4 <34> FBB_EDC3 P50 FBB_DQS_WP3
<33> FBA_EDC5 AK48 FBA_DQS_WP5 <34> FBB_EDC4 J48 FBB_DQS_WP4
<33> FBA_EDC6 FBA_DQS_WP6 <34> FBB_EDC5 FBB_DQS_WP5
1
AR51 AN42 1 2 D51
<33> FBA_EDC7 FBA_DQS_WP7 FBA_PLL_AVDD <34> FBB_EDC6 F51 FBB_DQS_WP6 L38 RG54 VGA@ RG55 VGA@
<34> FBB_EDC7 FBB_DQS_WP7 FBB_PLL_AVDD
22U_0603_6.3V6M
0.1U_0201_10V6K
LG4 VGA@ 10K_0402_5% 10K_0402_5%

W47 1 PBY160808T-300Y-N_2P
GND_694
1
0.1U_0201_10V6K
VGA@ CG35
VGA@ CG36
W49 Y17
SM01000HU00
2
W51 GND_695 Y18 GND_702 FBB_CMD1
GND_696 GND_703 1
CG37 VGA@
W6 Y19
2
W8 GND_697 2 +1.35VSDGPU Y20 GND_704 FBB_CMD17

Y14 GND_698 Y21 GND_705
Y15 GND_699 Y22 GND_706 2 FBB_CMD2
+FBX_PLLAVDD Y16 GND_700 Y23 GND_707
GND_701 Y24 GND_708 FBB_CMD18
GND_709
1
1
AF42 RG56 VGA@ RG57 VGA@ RG58 VGA@ RG59 VGA@
FB_REFPLL_AVDD0
0.1U_0201_10V6K
0.1U_0201_10V6K
L29 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

FB_REFPLL_AVDD1
1 1
VGA@ CG38
VGA@ CG39
2
2 2
@ N17E-G1_BGA2152~D
FBA_CMD1
FBA_CMD17 @ N17E-G1_BGA2152~D
Under GPU
FBA_CMD2
FBA_CMD18
A A
1
RG60 VGA@ RG61 VGA@

10K_0402_5% 10K_0402_5%
2

N17E-G1(4/8) MEM Interface
5 4 3 2 1
5 4 3 2 1
UG1D UG1E
4/23 FBC 5/23 FBD
C6 C11 AK8 AD2

<35> FBC_D0 D6 FBC_D0 FBC_CMD0 B11 FBC_CMD1 FBC_CMD0 <35> AK4 FBD_D0 FBD_CMD0 AD1
<35> FBC_D1 A6 FBC_D1 FBC_CMD1 A11 FBC_CMD2 FBC_CMD1 <35> AK2 FBD_D1 FBD_CMD1 AD4
<35> FBC_D2 B6 FBC_D2 FBC_CMD2 D11 FBC_CMD2 <35> AK3 FBD_D2 FBD_CMD2 AC1
<35> FBC_D3 B4 FBC_D3 FBC_CMD3 A12 FBC_CMD3 <35> AK5 FBD_D3 FBD_CMD3 AC2
<35> FBC_D4 A4 FBC_D4 FBC_CMD4 B12 FBC_CMD4 <35> AK6 FBD_D4 FBD_CMD4 AC3
<35> FBC_D5 B3 FBC_D5 FBC_CMD5 C12 FBC_CMD5 <35> AK9 FBD_D5 FBD_CMD5 AA3
<35> FBC_D6 C4 FBC_D6 FBC_CMD6 C14 FBC_CMD6 <35> AK7 FBD_D6 FBD_CMD6 AA2
<35> FBC_D7 D9 FBC_D7 FBC_CMD7 B14 FBC_CMD7 <35> AG4 FBD_D7 FBD_CMD7 AA1
<35> FBC_D8 C9 FBC_D8 FBC_CMD8 A14 FBC_CMD8 <35> AF9 FBD_D8 FBD_CMD8 AA4
<35> FBC_D9 E9 FBC_D9 FBC_CMD9 D14 FBC_CMD9 <35> AG6 FBD_D9 FBD_CMD9 Y1
<35> FBC_D10 B9 FBC_D10 FBC_CMD10 A15 FBC_CMD10 <35> AG7 FBD_D10 FBD_CMD10 Y2
D <35> FBC_D11 B8 FBC_D11 FBC_CMD11 B15 FBC_CMD11 <35> AJ4 FBD_D11 FBD_CMD11 Y3 D
<35> FBC_D12 A8 FBC_D12 FBC_CMD12 C15 FBC_CMD12 <35> AJ5 FBD_D12 FBD_CMD12 V3
<35> FBC_D13 F6 FBC_D13 FBC_CMD13 C17 FBC_CMD13 <35> AJ6 FBD_D13 FBD_CMD13 V2
<35> FBC_D14 E6 FBC_D14 FBC_CMD14 B17 FBC_CMD14 <35> AG5 FBD_D14 FBD_CMD14 V1
<35> FBC_D15 F18 FBC_D15 FBC_CMD15 B24 FBC_CMD15 <35> Y6 FBD_D15 FBD_CMD15 L3
<35> FBC_D16 G18 FBC_D16 FBC_CMD16 A24 FBC_CMD17 FBC_CMD16 <35> Y5 FBD_D16 FBD_CMD16 L2
<35> FBC_D17 E18 FBC_D17 FBC_CMD17 D23 FBC_CMD18 FBC_CMD17 <35> V5 FBD_D17 FBD_CMD17 L1
<35> FBC_D18 H18 FBC_D18 FBC_CMD18 A23 FBC_CMD18 <35> Y4 FBD_D18 FBD_CMD18 M4
<35> FBC_D19 D15 FBC_D19 FBC_CMD19 B23 FBC_CMD19 <35> AA6 FBD_D19 FBD_CMD19 M1
<35> FBC_D20 E15 FBC_D20 FBC_CMD20 C23 FBC_CMD20 <35> AA5 FBD_D20 FBD_CMD20 M2
<35> FBC_D21 G17 FBC_D21 FBC_CMD21 C21 FBC_CMD21 <35> AC5 FBD_D21 FBD_CMD21 M3
<35> FBC_D22 H17 FBC_D22 FBC_CMD22 B21 FBC_CMD22 <35> AC4 FBD_D22 FBD_CMD22 P3
<35> FBC_D23 J15 FBC_D23 FBC_CMD23 A21 FBC_CMD23 <35> AD7 FBD_D23 FBD_CMD23 P2
<35> FBC_D24 H15 FBC_D24 FBC_CMD24 D20 FBC_CMD24 <35> AC6 FBD_D24 FBD_CMD24 P1
<35> FBC_D25 E14 FBC_D25 FBC_CMD25 A20 FBC_CMD25 <35> AF6 FBD_D25 FBD_CMD25 R4
<35> FBC_D26 F14 FBC_D26 FBC_CMD26 B20 FBC_CMD26 <35> AD6 FBD_D26 FBD_CMD26 R1
<35> FBC_D27 H11 FBC_D27 FBC_CMD27 C20 FBC_CMD27 <35> AF7 FBD_D27 FBD_CMD27 R2
<35> FBC_D28 G11 FBC_D28 FBC_CMD28 C18 FBC_CMD28 <35> AF8 FBD_D28 FBD_CMD28 R3
<35> FBC_D29 F11 FBC_D29 FBC_CMD29 B18 FBC_CMD29 <35> +1.35VSDGPU AF2 FBD_D29 FBD_CMD29 U3
<35> FBC_D30 E11 FBC_D30 FBC_CMD30 A18 FBC_CMD30 <35> AF3 FBD_D30 FBD_CMD30 U2
<35> FBC_D31 J29 FBC_D31 FBC_CMD31 D17 FBC_CMD31 <35> F4 FBD_D31 FBD_CMD31 U1
<35> FBC_D32 F30 FBC_D32 FBC_CMD32 A17 E1 FBD_D32 FBD_CMD32 V4
<35> FBC_D33 H29 FBC_D33 FBC_CMD33 A9 1 2 60.4_0402_1% F3 FBD_D33 FBD_CMD33 AD3
RG188 @
<35> FBC_D34 G30 FBC_D34 FBC_CMD34 C24 1 2 60.4_0402_1% F5 FBD_D34 FBD_CMD34 J3
RG189 @
<35> FBC_D35 B30 FBC_D35 FBC_CMD35 D2 FBD_D35 FBD_CMD35
<35> FBC_D36 A30 FBC_D36 D1 FBD_D36
<35> FBC_D37 H30 FBC_D37 C3 FBD_D37
<35> FBC_D38 C30 FBC_D38 J14 C2 FBD_D38 AC9
<35> FBC_D39 D27 FBC_D39 FBC_DBG_RFU1 J23 J5 FBD_D39 FBD_DBG_RFU1 P9
<35> FBC_D40 J26 FBC_D40 FBC_DBG_RFU2 J4 FBD_D40 FBD_DBG_RFU2
<35> FBC_D41 F27 FBC_D41 L8 FBD_D41
<35> FBC_D42 G27 FBC_D42 J2 FBD_D42
C <35> FBC_D43 C27 FBC_D43 G15 F1 FBD_D43 Y8 C
<35> FBC_D44 B27 FBC_D44 FBC_CLK0 F15 FBC_CLK0 <35> F2 FBD_D44 FBD_CLK0 Y7
<35> FBC_D45 A27 FBC_D45 FBC_CLK0* H21 FBC_CLK0# <35> H4 FBD_D45 FBD_CLK0* R8
<35> FBC_D46 G29 FBC_D46 FBC_CLK1 J21 FBC_CLK1 <35> H5 FBD_D46 FBD_CLK1 R7
<35> FBC_D47 H20 FBC_D47 FBC_CLK1* FBC_CLK1# <35> V7 FBD_D47 FBD_CLK1*
<35> FBC_D48 D18 FBC_D48 V8 FBD_D48
<35> FBC_D49 G20 FBC_D49 V6 FBD_D49
<35> FBC_D50 E20 FBC_D50 V9 FBD_D50
<35> FBC_D51 F23 FBC_D51 U4 FBD_D51
<35> FBC_D52 E21 FBC_D52 R5 FBD_D52
<35> FBC_D53 D21 FBC_D53 R6 FBD_D53
<35> FBC_D54 E23 FBC_D54 U8 FBD_D54
<35> FBC_D55 G24 FBC_D55 F8 P6 FBD_D55 AJ8
<35> FBC_D56 H26 FBC_D56 FBC_WCK01 G8 FBC_WCK01 <35> R9 FBD_D56 FBD_WCK01 AJ7
<35> FBC_D57 F24 FBC_D57 FBC_WCK01* G9 FBC_WCK01# <35> P4 FBD_D57 FBD_WCK01* AG8
<35> FBC_D58 G26 FBC_D58 FBC_WCKB01 F9 P5 FBD_D58 FBD_WCKB01 AG9
<35> FBC_D59 F26 FBC_D59 FBC_WCKB01* H12 L7 FBD_D59 FBD_WCKB01* AD8
<35> FBC_D60 D26 FBC_D60 FBC_WCK23 G12 FBC_WCK23 <35> L6 FBD_D60 FBD_WCK23 AD9
<35> FBC_D61 B26 FBC_D61 FBC_WCK23* G14 FBC_WCK23# <35> L4 FBD_D61 FBD_WCK23* AC7
<35> FBC_D62 C26 FBC_D62 FBC_WCKB23 H14 L5 FBD_D62 FBD_WCKB23 AC8
<35> FBC_D63 FBC_D63 FBC_WCKB23* J27 FBD_D63 FBD_WCKB23* J6
FBC_WCK45 H27 FBC_WCK45 <35> FBD_WCK45 J7
A5 FBC_WCK45* E29 FBC_WCK45# <35> AJ1 FBD_WCK45* H7
<35> FBC_DBI0 C8 FBC_DQM0 FBC_WCKB45 F29 AG1 FBD_DQM0 FBD_WCKB45 H6
<35> FBC_DBI1 J18 FBC_DQM1 FBC_WCKB45* G23 AA7 FBD_DQM1 FBD_WCKB45* P8
<35> FBC_DBI2 F12 FBC_DQM2 FBC_WCK67 H23 FBC_WCK67 <35> AD5 FBD_DQM2 FBD_WCK67 P7
<35> FBC_DBI3 D29 FBC_DQM3 FBC_WCK67* H24 FBC_WCK67# <35> D3 FBD_DQM3 FBD_WCK67* M7
<35> FBC_DBI4 E27 FBC_DQM4 FBC_WCKB67 J24 H3 FBD_DQM4 FBD_WCKB67 M8
<35> FBC_DBI5
<35>
<35>
FBC_DBI6
FBC_DBI7
F20
E26
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_WCKB67*
Under GPU U5
M9
FBD_DQM5
FBD_DQM6
FBD_DQM7
FBD_WCKB67*
B D5 AJ3 B
<35> FBC_EDC0 D8 FBC_DQS_WP0 AG2 FBD_DQS_WP0
<35> FBC_EDC1 E17 FBC_DQS_WP1 +FBX_PLLAVDD AA9 FBD_DQS_WP1 +FBX_PLLAVDD
<35> FBC_EDC2 E12 FBC_DQS_WP2 AF4 FBD_DQS_WP2
<35> FBC_EDC3 E30 FBC_DQS_WP3 +1.35VSDGPU E3 FBD_DQS_WP3
<35> FBC_EDC4 B29 FBC_DQS_WP4 H2 FBD_DQS_WP4
<35> FBC_EDC5 G21 FBC_DQS_WP5 U6 FBD_DQS_WP5
<35> FBC_EDC6 E24 FBC_DQS_WP6 L17 M5 FBD_DQS_WP6 V11
<35> FBC_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD FBD_DQS_WP7 FBD_PLL_AVDD
1
1
0.1U_0201_10V6K
0.1U_0201_10V6K
Y25 Y33
Y26 GND_710 RG62 VGA@ RG63 VGA@ Y34 GND_0718
GND_711 1 GND_0719 1
CG40 VGA@
CG41 VGA@
Y27 10K_0402_5% 10K_0402_5% Y35
Y28 GND_712 Y36 GND_0720
Y29 GND_713 Y37 GND_0721
2
Y30 GND_714 2 FBC_CMD1 Y38 GND_0722 2

Y31 GND_715 Y39 GND_0723
Y32 GND_716 FBC_CMD17 Y9 GND_0724
GND_717 GND_0725
FBC_CMD2
FBC_CMD18 GP104 GP106

1
FBD UNUSED
@ N17E-G1_BGA2152~D
RG64 VGA@
10K_0402_5%
RG65 VGA@
10K_0402_5%
@ N17E-G1_BGA2152~D
Under GPU
2
A A

N17E-G1(5/8) MEM Interface
5 4 3 2 1
5 4 3 2 1
+1.8VSDGPU_AON
+1.8VSDGPU_AON
+1.8VSDGPU_AON
1
RG213 @
10K_0402_5%
2
UG1T
15/23 MISC 2
2
RG66 RG67 RG68 RG69 VGA@ RG70 RG71 RG72 VGA@ RG73 VGA@ RG74 VGA@
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% BJ4 ROM_CS# 100K_0402_5% 100K_0402_1% 100K_0402_5%
@ @ @ @ @ ROM_CS*
1
1
D BK2 ROM_SI D
ROM_SI BK4 ROM_SO
STRAP0 BL3 ROM_SO BK3 ROM_SCLK
STRAP1 BL4 STRAP0 ROM_SCLK
STRAP2 BM4 STRAP1
STRAP3 BM5 STRAP2
STRAP3
2
STRAP4 BK5
STRAP5 BJ5 STRAP4 RG75 RG76 RG77
STRAP5 100K_0402_1% 100K_0402_5% 100K_0402_1%
@ @ @
2
2
@
1
BF9 GPU_BUFRST# TG1
RG78 RG79 RG80 RG81 RG82 VGA@ RG83 VGA@ BUFRST* PAD~D
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1%
@ @ @ @
1
1
@ N17E-G1_BGA2152~D
C C
UG1S
+IFPX_PLLVDD 14/23 XTAL/PLL
BD12
SP_PLLVDD
BC12
VID_PLLVDD
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CG922 VGA@
1 1 1 1 1 1
CG49 VGA@
CG50 VGA@
CG51 VGA@
CG52 VGA@
CG53 VGA@
B 2 2 2 2 2 2 B
U42
GPCPLL_AVDD0
AF11
GPCPLL_AVDD1
BB24
XS_PLLVDD
Under GPU
BJ6 BK6 XTALOUTBUFF_R

XTAL_SSIN XTAL_OUTBUFF
BL6 BM6
XTAL_IN XTAL_OUT
1
RG84 VGA@ RG85 VGA@

10K_0402_5% @ N17E-G1_BGA2152~D 10K_0402_5%
2
RG86 1 @ 2 10M_0402_5%
1
RG199 VGA@
VGA@ 330_0402_1%
YG1
A 27MHZ_10PF_XRCGB27M000F2P18R0 A
2
XTALIN 1 3
1 3
NC NC
2 2
CG56 VGA@
CG55 VGA@ 2 4 15P_0402_50V8J
15P_0402_50V8J
1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
N17E-G1(6/8) Strap Pin,ROM
5 4 3 2 1
5 4 3 2 1
+NVVDD1 +NVVDD1 +NVVDD2 +NVVDD2 +1.35VSDGPU +1.35VSDGPU

UG1J UG1H
UG1G 23/23 VDDS 20/23 FBVDDQ
19/23 VDD_2/2
AA10 AT43
AP21 BB45 AP27 AC14 AA11 FBVDDQ_01 FBVDDQ_32 K12
AP22 VDD_145 VDD_219 BB46 AP28 VDDS_057 VDDS_001 AC15 AA42 FBVDDQ_02 FBVDDQ_33 K14
AP23 VDD_146 VDD_220 BB47 AP29 VDDS_058 VDDS_002 AC16 AA43 FBVDDQ_03 FBVDDQ_34 K15
AP30 VDD_147 VDD_221 BB48 AP35 VDDS_059 VDDS_003 AC17 AC10 FBVDDQ_04 FBVDDQ_35 K17
AP31 VDD_148 VDD_222 BC38 AP36 VDDS_060 VDDS_004 AC18 AC11 FBVDDQ_05 FBVDDQ_36 K18
AP34 VDD_151 VDD_225 BC41 AP39 VDDS_063 VDDS_007 AC26 AD10 FBVDDQ_08 FBVDDQ_39 K23
D AR13 VDD_152 VDD_226 BC45 AV14 VDDS_064 VDDS_008 AC27 AD11 FBVDDQ_09 FBVDDQ_40 K24 D
AR40 VDD_153 VDD_227 BC47 AV15 VDDS_065 VDDS_009 AC28 AD42 FBVDDQ_10 FBVDDQ_41 K26
AT14 VDD_154 VDD_228 BC49 AV16 VDDS_066 VDDS_010 AC29 AD43 FBVDDQ_11 FBVDDQ_42 K27
AT15 VDD_155 VDD_229 BD39 AV17 VDDS_067 VDDS_011 AC35 AF10 FBVDDQ_12 FBVDDQ_43 K29
AT16 VDD_156 VDD_230 BD41 AV18 VDDS_068 VDDS_012 AC36 AF43 FBVDDQ_13 FBVDDQ_44 K30
AT17 VDD_157 VDD_231 BD46 AV24 VDDS_069 VDDS_013 AC37 AG10 FBVDDQ_14 FBVDDQ_45 K32
AT20 VDD_160 VDD_234 BD49 AV27 VDDS_072 VDDS_016 AF14 AG43 FBVDDQ_17 FBVDDQ_48 K36
AT21 VDD_161 VDD_235 BD50 AV28 VDDS_073 VDDS_017 AF15 AJ10 FBVDDQ_18 FBVDDQ_49 K38
AT22 VDD_162 VDD_236 BD51 AV29 VDDS_074 VDDS_018 AF16 AJ11 FBVDDQ_19 FBVDDQ_50 K39
AT23 VDD_163 VDD_237 BE41 AV35 VDDS_075 VDDS_019 AF17 AJ42 FBVDDQ_20 FBVDDQ_51 K41
AT24 VDD_164 VDD_238 BE42 AV36 VDDS_076 VDDS_020 AF18 AJ43 FBVDDQ_21 FBVDDQ_52 L14
AT25 VDD_165 VDD_239 BE43 AV37 VDDS_077 VDDS_021 AF24 AK10 FBVDDQ_22 FBVDDQ_53 L15
AT28 VDD_168 VDD_242 BE48 R14 VDDS_080 VDDS_024 AG27 AK43 FBVDDQ_25 FBVDDQ_56 L21
AT29 VDD_169 VDD_243 BE49 R15 VDDS_081 VDDS_025 AG28 AM42 FBVDDQ_26 FBVDDQ_57 L23
AT30 VDD_170 VDD_244 BE50 R16 VDDS_082 VDDS_026 AG29 AM43 FBVDDQ_27 FBVDDQ_58 L24
AT31 VDD_171 VDD_245 BE51 R17 VDDS_083 VDDS_027 AG35 AN43 FBVDDQ_28 FBVDDQ_59 L26
AT32 VDD_172 VDD_246 BE52 R18 VDDS_084 VDDS_028 AG36 AR42 FBVDDQ_29 FBVDDQ_60 L27
AT33 VDD_173 VDD_247 BF42 R24 VDDS_085 VDDS_029 AG37 AR43 FBVDDQ_30 FBVDDQ_61 L30
AT34 VDD_174 VDD_248 BF44 R25 VDDS_086 VDDS_030 AG38 R42 FBVDDQ_31 FBVDDQ_62 L32
AT35 VDD_175 VDD_249 BF45 R26 VDDS_087 VDDS_031 AG39 R43 FBVDDQ_76 FBVDDQ_63 L33
AT36 VDD_176 VDD_250 BF47 R27 VDDS_088 VDDS_032 AK14 U10 FBVDDQ_77 FBVDDQ_64 L35
AT39 VDD_179 VDD_253 BG43 R35 VDDS_091 VDDS_035 AK17 V10 FBVDDQ_80 FBVDDQ_67 M10
AT42 VDD_180 VDD_254 BG44 R36 VDDS_092 VDDS_036 AK18 V42 FBVDDQ_81 FBVDDQ_68 M43
AU43 VDD_181 VDD_255 U16 R37 VDDS_093 VDDS_037 AK24 V43 FBVDDQ_82 FBVDDQ_69 P10
AV19 VDD_182 VDD_321 U17 R38 VDDS_094 VDDS_038 AK25 Y10 FBVDDQ_83 FBVDDQ_70 P11
AV20 VDD_183 VDD_322 U18 R39 VDDS_095 VDDS_039 AK26 Y11 FBVDDQ_84 FBVDDQ_71 P42
C AV21 VDD_184 VDD_323 U19 W14 VDDS_096 VDDS_040 AK27 Y42 FBVDDQ_85 FBVDDQ_72 P43 C
AV22 VDD_185 VDD_324 U20 W15 VDDS_097 VDDS_041 AK28 Y43 FBVDDQ_86 FBVDDQ_73 R10
AV23 VDD_186 VDD_325 U21 W16 VDDS_098 VDDS_042 AK29 FBVDDQ_87 FBVDDQ_74 R11
AV30 VDD_187 VDD_326 U22 W17 VDDS_099 VDDS_043 AK35 FBVDDQ_75
AV31 VDD_188 VDD_327 U23 W18 VDDS_100 VDDS_044 AK36
AV34 VDD_191 VDD_330 U26 W26 VDDS_103 VDDS_047 AK39 E52
AV42 VDD_192 VDD_331 U27 W27 VDDS_104 VDDS_048 AP14 FBVDDQ_SENSE FB_VDDQ_SENSE <63>
AV43 VDD_193 VDD_332 U28 W28 VDDS_105 VDDS_049 AP15
AV44 VDD_194 VDD_333 U29 W29 VDDS_106 VDDS_050 AP16
AW13 VDD_195 VDD_334 U30 W35 VDDS_107 VDDS_051 AP17 P45
AW40 VDD_196 VDD_335 U31 W36 VDDS_108 VDDS_052 AP18 FB_VREF
AW42 VDD_197 VDD_336 U32 W37 VDDS_109 VDDS_053 AP24 +1.35VSDGPU
AW43 VDD_198 VDD_337 U33 W38 VDDS_110 VDDS_054 AP25
AW44 VDD_199 VDD_338 U34 W39 VDDS_111 VDDS_055 AP26
AW45 VDD_200 VDD_339 U35 VDDS_112 VDDS_056
AY14 VDD_201 VDD_340 U36 R44 FBCAL_VDDQ RG95 1 VGA@ 2 40.2_0402_1%
AY18 VDD_202 VDD_341 U37 FB_CAL_PD_VDDQ
AY22 VDD_203 VDD_342 U38 P44 FBCAL_GND RG96 1 VGA@ 2 40.2_0402_1%
AY26 VDD_204 VDD_343 U39 FB_CAL_PU_GND
AY27 VDD_205 VDD_344 V13 R45 FBCAL_TERM RG97 1 VGA@ 2 60.4_0402_1%
AY31 VDD_206 VDD_345 V40 BM45 FB_CAL_TERM_GND
AY35 VDD_207 VDD_346 W19 VDDS_SENSE BM44 NVVDD2_VCC_SENSE <68>
AY39 VDD_208 VDD_347 W20 GNDS_SENSE NVVDD2_VSS_SENSE <68>
AY43 VDD_209 VDD_348 W21 @ N17E-G1_BGA2152~D
AY45 VDD_210 VDD_349 W22
BA43 VDD_211 VDD_350 W23 @ N17E-G1_BGA2152~D
BA44 VDD_212 VDD_351 W30
BA45 VDD_213 VDD_352 W31
BA46 VDD_214 VDD_353 W32
BA47 VDD_215 VDD_354 W33
B BB38 VDD_216 VDD_355 W34 B
BB39 VDD_217 VDD_356 +1.35VSDGPU
VDD_218
Place under GPU
CG62
CG63
CG64
CG65
CG66
CG67
CG68
CG69
CG70
CG71
CG72
CG73
CG74
CG75
CG76
CG77
CG78
CG79
CG80
CG81
CG82
CG83
CG84
CG85
CG86
CG87
CG88
CG89
CG90
CG91
CG92
CG93
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
BK45
VDD_SENSE BL45 NVVDD1_VCC_SENSE <65>
GND_SENSE NVVDD1_VSS_SENSE <65>
@ N17E-G1_BGA2152~D
+1.35VSDGPU
CG94
CG95
CG96
CG97
CG98
CG99
CG100
CG101
CG102
CG103
CG104
CG105
CG106
1 1 1 1 1 1 1 1 1 1 1 1 1
470uF 22uF 10uF 4.7uF 1uF 0.1uF
A A
2 2 2 2 2 2 2 2 2 2 2 2 2 FBVDDQ 1 9 13 24
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M

N17E-G1(7/8) Power
5 4 3 2 1
5 4 3 2 1
UG1K UG1L UG1M

+NVVDD1 +NVVDD1 16/23 GND_1/3 17/23 GND_2/3 22/23 GND_3/3
UG1I +1.8VSDGPU_AON
21/23 NC/1V8 UG1F A2 AH6 AR20 B52 BL43 N6
A26 GND_001 GND_122 AH8 AR21 GND_238 GND_361 B7 BL5 GND_482 GND_592 N8
18/21 VDD_1/2
AT9 BA10 A29 GND_002 GND_123 AJ14 AR22 GND_239 GND_362 BA48 BL7 GND_483 GND_593 P14
BA6 NC_1 1V8_AON_1 BB14 AA14 AG22 A3 GND_003 GND_124 AJ15 AR23 GND_240 GND_363 BB49 BM2 GND_484 GND_594 P15
BA9 NC_2 1V8_AON_2 BC14 AA15 VDD_001 VDD_076 AG23 A32 GND_004 GND_125 AJ16 AR24 GND_241 GND_364 BC13 BM3 GND_485 GND_595 P16
BD14 NC_3 1V8_AON_3 AA16 VDD_002 VDD_077 AG40 A50 GND_005 GND_126 AJ17 AR25 GND_242 GND_365 BC16 C1 GND_486 GND_596 P17
BE12 NC_4 AA17 VDD_003 VDD_078 AH14 A51 GND_006 GND_127 AJ18 AR26 GND_243 GND_366 BC19 C29 GND_487 GND_597 P18
BG6 NC_5 AA18 VDD_004 VDD_079 AH15 AA49 GND_007 GND_128 AJ19 AR27 GND_244 GND_367 BC2 C33 GND_488 GND_598 P19
BH6 NC_6 AA19 VDD_005 VDD_080 AH16 AA8 GND_008 GND_129 AJ2 AR28 GND_245 GND_368 BC22 C5 GND_489 GND_599 P20
BJ11 NC_7 +1.8VSDGPU_MAIN AA20 VDD_006 VDD_081 AH17 AB10 GND_009 GND_130 AJ20 AR29 GND_246 GND_369 BC25 C51 GND_490 GND_600 P21
BJ9 NC_8 AA21 VDD_007 VDD_082 AH18 AB14 GND_010 GND_131 AJ21 AR30 GND_247 GND_370 BC28 C52 GND_491 GND_601 P22
BK44 NC_9 AA22 VDD_008 VDD_083 AH19 AB15 GND_011 GND_132 AJ22 AR31 GND_248 GND_371 BC31 D10 GND_492 GND_602 P23
NC_10 AM10 AA23 VDD_009 VDD_084 AH20 AB16 GND_012 GND_133 AJ23 AR32 GND_249 GND_372 BC34 D12 GND_493 GND_603 P24
VDD18_01 AM11 AA24 VDD_010 VDD_085 AH21 AB17 GND_013 GND_134 AJ24 AR33 GND_250 GND_373 BC37 D13 GND_494 GND_604 P25
D VDD18_02 VDD_011 VDD_086 GND_014 GND_135 GND_251 GND_374 GND_495 GND_605 D
AN10 AA25 AH22 AB18 AJ25 AR34 BC4 D16 P26
VDD18_03 AN11 AA26 VDD_012 VDD_087 AH23 AB19 GND_015 GND_136 AJ26 AR35 GND_252 GND_375 BC51 D19 GND_496 GND_606 P27
VDD18_04 AR10 AA27 VDD_013 VDD_088 AH24 AB2 GND_016 GND_137 AJ27 AR36 GND_253 GND_376 BC6 D22 GND_497 GND_607 P28
VDD18_05 AR11 AA28 VDD_014 VDD_089 AH25 AB20 GND_017 GND_138 AJ28 AR37 GND_254 GND_377 BC8 D24 GND_498 GND_608 P29
VDD18_06 AT10 AA29 VDD_015 VDD_090 AH26 AB21 GND_018 GND_139 AJ29 AR38 GND_255 GND_378 BD26 D25 GND_499 GND_609 P30
VDD18_07 AT11 AA30 VDD_016 VDD_091 AH27 AB22 GND_019 GND_140 AJ30 AR39 GND_256 GND_379 BD29 D28 GND_500 GND_610 P31
VDD18_08 AV10 AA31 VDD_017 VDD_092 AH28 AB23 GND_020 GND_141 AJ31 AR4 GND_257 GND_380 BD32 D30 GND_501 GND_611 P32
VDD18_09 AV11 AA32 VDD_018 VDD_093 AH29 AB24 GND_021 GND_142 AJ32 AR52 GND_258 GND_381 BD35 D31 GND_502 GND_612 P33
VDD18_10 AW10 AA33 VDD_019 VDD_094 AH30 AB25 GND_022 GND_143 AJ33 AR9 GND_259 GND_382 BD38 D34 GND_503 GND_613 P34
VDD18_11 AW11 AA34 VDD_020 VDD_095 AH31 AB26 GND_023 GND_144 AJ34 AT4 GND_260 GND_383 BD52 D37 GND_504 GND_614 P35
VDD18_12 AA35 VDD_021 VDD_096 AH32 AB27 GND_024 GND_145 AJ35 AT5 GND_261 GND_384 BE10 D4 GND_505 GND_615 P36
AA36 VDD_022 VDD_097 AH33 AB28 GND_025 GND_146 AJ36 AT51 GND_262 GND_385 BE13 D40 GND_506 GND_616 P37
AA37 VDD_023 VDD_098 AH34 AB29 GND_026 GND_147 AJ37 AT52 GND_263 GND_386 BE15 D43 GND_507 GND_617 P38
@ N17E-G1_BGA2152~D AA38 VDD_024 VDD_099 AH35 AB30 GND_027 GND_148 AJ38 AT8 GND_264 GND_387 BE16 D46 GND_508 GND_618 P39
AA39 VDD_025 VDD_100 AH36 AB31 GND_028 GND_149 AJ39 AU10 GND_265 GND_388 BE18 D49 GND_509 GND_619 P51
AB13 VDD_026 VDD_101 AH37 AB32 GND_029 GND_150 AJ9 AU14 GND_266 GND_389 BE19 D7 GND_510 GND_620 R49
AB40 VDD_027 VDD_102 AH38 AB33 GND_030 GND_151 AK1 AU15 GND_267 GND_390 BE21 E2 GND_511 GND_621 R52
AC19 VDD_028 VDD_103 AH39 AB34 GND_031 GND_152 AK44 AU16 GND_268 GND_391 BE22 E4 GND_512 GND_622 T10
AC20 VDD_029 VDD_104 AK19 AB35 GND_032 GND_153 AK47 AU17 GND_269 GND_392 BE24 E48 GND_513 GND_623 T14
AC21 VDD_030 VDD_105 AK20 AB36 GND_033 GND_154 AL10 AU18 GND_270 GND_393 BE25 E5 GND_514 GND_624 T15
AC30 VDD_033 VDD_108 AK23 AB39 GND_036 GND_157 AL16 AU20 GND_273 GND_396 BE30 F10 GND_517 GND_627 T18
AE14 VDD_038 VDD_113 AK34 AB49 GND_041 GND_162 AL20 AU25 GND_278 GND_401 BE37 F21 GND_522 GND_632 T22
AE15 VDD_039 VDD_114 AL13 AB51 GND_042 GND_163 AL21 AU26 GND_279 GND_402 BE39 F22 GND_523 GND_633 T23
AE16 VDD_040 VDD_115 AL40 AB6 GND_043 GND_164 AL22 AU27 GND_280 GND_403 BE40 F25 GND_524 GND_634 T24
AE17 VDD_041 VDD_116 AM14 AB8 GND_044 GND_165 AL23 AU28 GND_281 GND_404 BF2 F28 GND_525 GND_635 T25
+1.8VSDGPU_AON AE18 VDD_042 VDD_117 AM15 AD14 GND_045 GND_166 AL24 AU29 GND_282 GND_405 BF4 F31 GND_526 GND_636 T26
AE19 VDD_043 VDD_118 AM16 AD15 GND_046 GND_167 AL25 AU30 GND_283 GND_406 BF41 F34 GND_527 GND_637 T27
AE20 VDD_044 VDD_119 AM17 AD16 GND_047 GND_168 AL26 AU31 GND_284 GND_407 BF6 F35 GND_528 GND_638 T28
AE21 VDD_045 VDD_120 AM18 AD17 GND_048 GND_169 AL27 AU32 GND_285 GND_408 BG10 F37 GND_529 GND_639 T29
C AE22 VDD_046 VDD_121 AM19 AD18 GND_049 GND_170 AL28 AU33 GND_286 GND_409 BG13 F40 GND_530 GND_640 T30 C
VDD_047 VDD_122 GND_050 GND_171 GND_287 GND_410 GND_531 GND_641
4.7U_0402_6.3V6M
1U_0402_6.3V4Z
0.1U_0201_10V6K
0.1U_0201_10V6K
AE23 AM20 AD19 AL29 AU34 BG16 F43 T31

CG107 VGA@
CG108 VGA@
CG109 VGA@
CG110 VGA@
1 1 1 1 AE24 AM21 AD20 AL30 AU35 BG19 F44 T32

2 2 2 2 AE28 VDD_052 VDD_127 AM25 AD24 GND_055 GND_176 AL34 AU39 GND_292 GND_415 BG31 G2 GND_536 GND_646 T36
AE29 VDD_053 VDD_128 AM26 AD25 GND_056 GND_177 AL35 AU4 GND_293 GND_416 BG34 G38 GND_537 GND_647 T37
Under GPU AE34
AE35
AE36
VDD_058
VDD_059
VDD_060
VDD_133
VDD_134
VDD_135
AM31
AM32
AM33
AD30
AD31
AD32
GND_061
GND_062
GND_063
GND_182
GND_183
GND_184
AL4
AL43
AL45
AU6
AU8
AV4
GND_298
GND_299
GND_300
GND_421
GND_422
GND_423
BH15
BH18
BH2
G6
H1
H10
GND_542
GND_543
GND_544
GND_652
GND_653
GND_654
T45
T47
T49
AE37 VDD_061 VDD_136 AM34 AD33 GND_064 GND_185 AL47 AV45 GND_301 GND_424 BH21 H13 GND_545 GND_655 T51
AE38 VDD_062 VDD_137 AM35 AD34 GND_065 GND_186 AL49 AV9 GND_302 GND_425 BH24 H16 GND_546 GND_656 T6
AE39 VDD_063 VDD_138 AM36 AD35 GND_066 GND_187 AL51 AW14 GND_303 GND_426 BH27 H19 GND_547 GND_657 T8
AF13 VDD_064 VDD_139 AM37 AD36 GND_067 GND_188 AL6 AW15 GND_304 GND_427 BH30 H22 GND_548 GND_658 U7
AF30 VDD_065 VDD_140 AM38 AD37 GND_068 GND_189 AL8 AW16 GND_305 GND_428 BH33 H25 GND_549 GND_659 U9
AF31 VDD_066 VDD_141 AM39 AD38 GND_069 GND_190 AM4 AW17 GND_306 GND_429 BH36 H28 GND_550 GND_660 V14
+1.8VSDGPU_MAIN AF32 VDD_067 VDD_142 AP19 AD39 GND_070 GND_191 AM9 AW18 GND_307 GND_430 BH39 H31 GND_551 GND_661 V15
AF33 VDD_068 VDD_143 AP20 AD44 GND_071 GND_192 AN14 AW19 GND_308 GND_431 BH42 H34 GND_552 GND_662 V16
AF34 VDD_069 VDD_144 BK52 AE10 GND_072 GND_193 AN15 AW20 GND_309 GND_432 BH5 H37 GND_553 GND_663 V17
AF40 VDD_070 VDD_286 BL46 AE2 GND_073 GND_194 AN16 AW21 GND_310 GND_433 BJ10 H40 GND_554 GND_664 V18
AG13 VDD_071 VDD_287 BL47 AE4 GND_074 GND_195 AN17 AW22 GND_311 GND_434 BJ12 H43 GND_555 GND_665 V19
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
AG19 BL48 AE43 AN18 AW23 BJ13 J1 V20

CG111 VGA@
CG112 VGA@
CG113 VGA@
CG114 VGA@
CG115 VGA@
CG116 VGA@
1 1 1 1 1 1 AG20 BL49 AE45 AN19 AW24 BJ14 J12 V21

AG21 VDD_074 VDD_290 BL50 AE47 GND_077 GND_198 AN20 AW25 GND_314 GND_437 BJ15 J17 GND_558 GND_668 V22
BG45 VDD_075 VDD_291 BL51 AE49 GND_078 GND_199 AN21 AW26 GND_315 GND_438 BJ16 J20 GND_559 GND_669 V23
BG46 VDD_256 VDD_292 BL52 AE51 GND_079 GND_200 AN22 AW27 GND_316 GND_439 BJ17 J38 GND_560 GND_670 V24
2 2 2 2 2 2 BG47 VDD_257 VDD_293 BM47 AE6 GND_080 GND_201 AN23 AW28 GND_317 GND_440 BJ18 J49 GND_561 GND_671 V25
BG48 VDD_258 VDD_294 BM48 AE8 GND_081 GND_202 AN24 AW29 GND_318 GND_441 BJ19 J52 GND_562 GND_672 V26
BG49 VDD_259 VDD_295 BM49 AF1 GND_082 GND_203 AN25 AW30 GND_319 GND_442 BJ20 K13 GND_563 GND_673 V27
BG50 VDD_260 VDD_296 BM50 AF19 GND_083 GND_204 AN26 AW31 GND_320 GND_443 BJ21 K16 GND_564 GND_674 V28
B BG51 VDD_261 VDD_297 BM51 AF20 GND_084 GND_205 AN27 AW32 GND_321 GND_444 BJ22 K19 GND_565 GND_675 V29 B
BG52 VDD_262 VDD_298 N14 AF21 GND_085 GND_206 AN28 AW33 GND_322 GND_445 BJ23 K2 GND_566 GND_676 V30
BH44 VDD_263 VDD_299 N18 AF22 GND_086 GND_207 AN29 AW34 GND_323 GND_446 BJ24 K22 GND_567 GND_677 V31
+1.8VSDGPU_MAIN BH52 VDD_270 VDD_306 P13 AF37 GND_093 GND_214 AN36 AW46 GND_330 GND_453 BJ31 K40 GND_574 GND_684 V38
BJ44 VDD_271 VDD_307 P40 AF38 GND_094 GND_215 AN37 AW5 GND_331 GND_454 BJ32 K45 GND_575 GND_685 V39
BJ45 VDD_272 VDD_308 R19 AF39 GND_095 GND_216 AN38 AW52 GND_332 GND_455 BJ33 K47 GND_576 GND_686 V49
BJ46 VDD_273 VDD_309 R20 AF45 GND_096 GND_217 AN39 AW8 GND_333 GND_456 BJ34 K49 GND_577 GND_687 V52
BJ47 VDD_274 VDD_310 R21 AF5 GND_097 GND_218 AN4 AY10 GND_334 GND_457 BJ35 K51 GND_578 GND_688 W10
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
BJ48 R22 AG14 AN5 AY2 BJ36 K6 W2

CG117 VGA@
CG118 VGA@
CG119 VGA@
CG120 VGA@
CG121 VGA@
CG122 VGA@
CG123 VGA@
1 1 1 1 1 1 1 BJ49 R23 AG15 AN8 AY4 BJ37 K8 W4

BJ50 VDD_277 VDD_313 R30 AG16 GND_100 GND_221 AP10 AY47 GND_337 GND_460 BJ38 M52 GND_581 GND_691 W43
BJ51 VDD_278 VDD_314 R31 AG17 GND_101 GND_222 AP2 AY49 GND_338 GND_461 BJ39 M6 GND_582 GND_692 W45
BJ52 VDD_279 VDD_315 R32 AG18 GND_102 GND_223 AP4 AY51 GND_339 GND_462 BJ40 N10 GND_583 GND_693
2 2 2 2 2 2 2 BK47 VDD_280 VDD_316 R33 AG24 GND_103 GND_224 AP43 AY6 GND_340 GND_463 BJ41 N2 GND_584
BK48 VDD_281 VDD_317 R34 AG25 GND_104 GND_225 AP45 AY8 GND_341 GND_464 BJ42 N4 GND_585
BK49 VDD_282 VDD_318 U14 AG26 GND_105 GND_226 AP47 B1 GND_342 GND_465 BJ43 N43 GND_586
BK50 VDD_283 VDD_319 U15 AG3 GND_106 GND_227 AP49 B10 GND_343 GND_466 BJ7 N45 GND_587
BK51 VDD_284 VDD_320 AG30 GND_107 GND_228 AP51 B13 GND_344 GND_467 BK1 N47 GND_588
VDD_285 AG31 GND_108 GND_229 AP6 B16 GND_345 GND_468 BL1 N49 GND_589
AG32 GND_109 GND_230 AP8 B19 GND_346 GND_469 BL10 N51 GND_590
AG33 GND_110 GND_231 AR14 B2 GND_347 GND_470 BL13 BL40 GND_591
@ N17E-G1_BGA2152~D AG34 GND_111 GND_232 AR15 B22 GND_348 GND_471 BL16 GND_481
AG44 GND_112 GND_233 AR16 B25 GND_349 GND_472 BL19
Under GPU AH10
AH2
AH4
GND_113
GND_114
GND_115
GND_234
GND_235
GND_236
AR17
AR18
AR19
B28
B31
B34
GND_350
GND_351
GND_352
GND_473
GND_474
GND_475
BL2
BL22
BL25
@ N17E-G1_BGA2152~D
AH43 GND_116 GND_237 BL37 B37 GND_353 GND_476 BL28

AH45 GND_117 GND_480 BD24 B40 GND_354 GND_477 BL31
AH47 GND_118 GND_H BC24 B43 GND_355 GND_478 BL34
AH49 GND_119 GND_F B46 GND_356 GND_479 B5
A A
AH51 GND_120 B48 GND_357 GND_359 B51
GND_121 GND_358 GND_360
@ N17E-G1_BGA2152~D @ N17E-G1_BGA2152~D

N17E-G1(8/8) Power,GND
5 4 3 2 1
5 4 3 2 1
GDDR5_A UG13 MF=1 UG12 MF=0

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
A4 A4
DQ24 DQ0 FBA_D24 <28> DQ24 DQ0 FBA_D32 <28>
C2 A2 C2 A2
<28> FBA_EDC3 EDC0 EDC3 DQ25 DQ1 FBA_D25 <28> <28> FBA_EDC4 EDC0 EDC3 DQ25 DQ1 FBA_D33 <28>
C13 B4 C13 B4
R13 B2 R13 B2
R2 E4 R2 E4
E2 E2
<28> FBA_CLK0 DQ29 DQ5 FBA_D29 <28> <28> FBA_CLK1 DQ29 DQ5 FBA_D37 <28>
F4 F4
FBA_D30 <28> FBA_D38 <28>
1
D2 DQ30 DQ6 F2 D2 DQ30 DQ6 F2
<28> FBA_DBI3 DBI0# DBI3# DQ31 DQ7 FBA_D31 <28> <28> FBA_DBI4 DBI0# DBI3# DQ31 DQ7 FBA_D39 <28>
VGA@ RG99 D13 A11 VGA@ RG98 D13 A11
40.2_0402_1% P13 A13 40.2_0402_1% P13 A13
D <28> FBA_DBI1 DBI2# DBI1# DQ17 DQ9 FBA_D17 <28> <28> FBA_DBI6 DBI2# DBI1# DQ17 DQ9 FBA_D41 <28> D
P2 B11 P2 B11
B13 B13
FBA_D19 <28> FBA_D43 <28>
2
J12 DQ19 DQ11 E11 J12 DQ19 DQ11 E11
CK DQ20 DQ12 FBA_D20 <28> CK DQ20 DQ12 FBA_D44 <28>
2 1 J11 E13 2 1 J11 E13
CK# DQ21 DQ13 FBA_D21 <28> CK# DQ21 DQ13 FBA_D45 <28>
CG124 0.01U_0402_16V7K J3 F11 CG125 0.01U_0402_16V7K J3 F11
<28> FBA_CMD1 FBA_D22 <28> <28> FBA_CMD17 FBA_D46 <28>
2
CKE# DQ22 DQ14 F13 CKE# DQ22 DQ14 F13
VGA@ DQ23 DQ15 FBA_D23 <28> VGA@ DQ23 DQ15 FBA_D47 <28>
VGA@ RG100 U11 VGA@ RG101 U11
40.2_0402_1% H11 U13 40.2_0402_1% H11 U13
<28> FBA_CMD12 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D9 <28> <28> FBA_CMD29 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D49 <28>
K10 T11 K10 T11
<28> FBA_CMD14 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D10 <28> <28> FBA_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D50 <28>
K11 T13 K11 T13
<28> FBA_CMD13 FBA_D11 <28> <28> FBA_CMD28 FBA_D51 <28>
1
H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11
<28> FBA_CLK0# <28> FBA_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D12 <28> <28> FBA_CLK1# <28> FBA_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D52 <28>
N13 N13
M11 M11
K4 M13 K4 M13
<28> FBA_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBA_D15 <28> <28> FBA_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBA_D55 <28>
H5 U4 H5 U4
H4 U2 H4 U2
K5 T4 K5 T4
J5 T2 J5 T2
<28> FBA_CMD6 A12/RFU/NC DQ3 DQ27 FBA_D3 <28> <28> FBA_CMD22 A12/RFU/NC DQ3 DQ27 FBA_D59 <28>
N4 N4
A5 N2 A5 N2
+1.35VSDGPU VPP/NC DQ5 DQ29 FBA_D5 <28> VPP/NC DQ5 DQ29 FBA_D61 <28>
U5 M4 U5 M4
VPP/NC DQ6 DQ30 FBA_D6 <28> VPP/NC DQ6 DQ30 FBA_D62 <28>
M2 M2
J1 +1.35VSDGPU J1 +1.35VSDGPU
J10 MF J10 MF
RG106 2 1 121_0402_1% J13 SEN B1 RG107 2 1 121_0402_1% J13 SEN B1
VGA@ ZQ VDDQ D1 VGA@ ZQ VDDQ D1
VDDQ F1 VDDQ F1
J4 VDDQ M1 J4 VDDQ M1
<28> FBA_CMD7 ABI# VDDQ <28> FBA_CMD23 ABI# VDDQ
G3 P1 G3 P1
<28> FBA_CMD0 RAS# CAS# VDDQ <28> FBA_CMD19 RAS# CAS# VDDQ
G12 T1 G12 T1
<28> FBA_CMD10 CS# WE# VDDQ <28> FBA_CMD31 CS# WE# VDDQ
L3 G2 L3 G2
<28>
<28>
FBA_CMD3
FBA_CMD15
L12 CAS#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
L2
B3
D3
+1.35VSDGPU
Near VRAM <28>
<28>
FBA_CMD16
FBA_CMD26
L12 CAS#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
L2
B3
D3
VDDQ F3 VDDQ F3
D5 VDDQ H3 D5 VDDQ H3
<28> FBA_WCK23# WCK01# WCK23# VDDQ <28> FBA_WCK45# WCK01# WCK23# VDDQ
D4 K3 D4 K3
CG126
CG127
CG128
CG129
CG142
CG130
CG178
<28> FBA_WCK23 WCK01 WCK23 VDDQ <28> FBA_WCK45 WCK01 WCK23 VDDQ
M3 1 1 1 1 1 1 1 M3
P5 VDDQ P3 P5 VDDQ P3
<28> FBA_WCK01# WCK23# WCK01# VDDQ <28> FBA_WCK67# WCK23# WCK01# VDDQ
P4 T3 P4 T3
<28> FBA_WCK01 WCK23 WCK01 VDDQ <28> FBA_WCK67 WCK23 WCK01 VDDQ
E5 E5
C VDDQ 2 2 2 2 2 2 2 VDDQ C
N5 N5
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VDDQ VDDQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A10 E10 A10 E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBA_VREFC J14 VREFD VDDQ B12 +FBA_VREFC J14 VREFD VDDQ B12
+1.35VSDGPU VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
1
J2 VDDQ K12 J2 VDDQ K12

<28> FBA_CMD2 RESET# VDDQ <28> FBA_CMD18 RESET# VDDQ
RG108 VGA@ M12 M12
549_0402_1% VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
2
H1 VDDQ L13 H1 VDDQ L13

1 2 +FBA_VREFC W=16mils K1 VSS
VSS
VDDQ
VDDQ
B14 K1 VSS
VSS
VDDQ
VDDQ
B14
B5 D14 B5 D14
1
RG109 VGA@ G5 VSS VDDQ F14 G5 VSS VDDQ F14

VGA@ RG110
VGA@ CG152
VGA@ CG153
820P_0402_25V7
820P_0402_25V7
1.33K_0402_1%
1 1 VSS VDDQ VSS VDDQ

931_0402_1% L5 M14 L5 M14
T5 VSS VDDQ P14 +1.35VSDGPU T5 VSS VDDQ P14
1
D B10 VSS VDDQ T14 B10 VSS VDDQ T14

2 QG8 VGA@ 2 2 D10 VSS VDDQ D10 VSS VDDQ
<26,34,35> MEM_VREF
2
G MESS138W-G_SOT323-3 G10 VSS G10 VSS

L10 VSS A1 L10 VSS A1
CG143
CG144
CG145
CG131
S
3
P10 VSS VSSQ C1 P10 VSS VSSQ C1

VSS VSSQ 1 1 1 1 VSS VSSQ
T10 E1 T10 E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
+1.35VSDGPU K14 VSS VSSQ R1 K14 VSS VSSQ R1
VSS VSSQ U1 2 2 2 2 +1.35VSDGPU VSS VSSQ U1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
H2 H2
G1 VSSQ K2 G1 VSSQ K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
+1.35VSDGPU
Near VRAM R5
C10
R10
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
R3
U3
C4
Under VRAM R5
C10
R10
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
R3
U3
C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 +1.35VSDGPU G11 VDD VSSQ F5
CG164
CG165
CG166
CG176
CG177
CG179
CG180
L11 VDD VSSQ M5 L11 VDD VSSQ M5

1 1 1 1 1 1 1 VDD VSSQ VDD VSSQ
P11 F10 P11 F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
CG140
CG141
CG146
CG147
CG148
CG149
CG150
CG151
CG154
CG155
CG156
CG157
CG158
CG159
CG160
CG161
CG162
CG163
B B
2 2 2 2 2 2 2 VDD VSSQ R11 VDD VSSQ R11
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSSQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VSSQ
VGA@
VGA@
A12 A12
VGA@
VGA@
VGA@
VGA@
VGA@
VSSQ C12 VSSQ C12

VSSQ E12 VSSQ E12
VSSQ N12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VSSQ N12
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
R12 R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
K4G80325FB-HC25 FBGA 170P K4G80325FB-HC25 FBGA 170P
+1.35VSDGPU
Under VRAM @
Under VRAM @
18 x 1uF (0402 X6S)

4 x 10uF (0402 X6S)
CG181
CG167
CG168
CG169
CG170
CG171
CG172
CG173
CG174
CG175
CG132
CG133
CG134
CG135
CG136
CG137
CG138
CG139
CG182
CG183
CG184
CG185
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Near VRAM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2 x 10uF (0402 X6S) 2 GND/PWR vias for each cap.

VGA@
5 x 22uF (0603 X6S) 2 GND/PWR vias for each cap
A A

N17E-GDDR5_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
GDDR5_B UG14 MF=1 UG15 MF=0

A4 A4
DQ24 DQ0 FBB_D24 <28> DQ24 DQ0 FBB_D32 <28>
C2 A2 C2 A2
<28> FBB_EDC3 EDC0 EDC3 DQ25 DQ1 FBB_D25 <28> <28> FBB_EDC4 EDC0 EDC3 DQ25 DQ1 FBB_D33 <28>
C13 B4 C13 B4
R13 B2 R13 B2
R2 E4 R2 E4
E2 E2
<28> FBB_CLK0 DQ29 DQ5 FBB_D29 <28> <28> FBB_CLK1 DQ29 DQ5 FBB_D37 <28>
F4 F4
FBB_D30 <28> FBB_D38 <28>
1
<28> FBB_DBI3 DBI0# DBI3# DQ31 DQ7 FBB_D31 <28> <28> FBB_DBI4 DBI0# DBI3# DQ31 DQ7 FBB_D39 <28>
VGA@ RG111 D13 A11 VGA@ RG112 D13 A11
40.2_0402_1% P13 A13 40.2_0402_1% P13 A13
D <28> FBB_DBI1 DBI2# DBI1# DQ17 DQ9 FBB_D17 <28> <28> FBB_DBI6 DBI2# DBI1# DQ17 DQ9 FBB_D41 <28> D
P2 B11 P2 B11
B13 B13
FBB_D19 <28> FBB_D43 <28>
2
J12 DQ19 DQ11 E11 J12 DQ19 DQ11 E11
CK DQ20 DQ12 FBB_D20 <28> CK DQ20 DQ12 FBB_D44 <28>
2 1 J11 E13 2 1 J11 E13
CK# DQ21 DQ13 FBB_D21 <28> CK# DQ21 DQ13 FBB_D45 <28>
CG186 0.01U_0402_16V7K J3 F11 CG187 0.01U_0402_16V7K J3 F11
<28> FBB_CMD1 FBB_D22 <28> <28> FBB_CMD17 FBB_D46 <28>
2
VGA@ DQ23 DQ15 FBB_D23 <28> VGA@ DQ23 DQ15 FBB_D47 <28>
40.2_0402_1% H11 U13 40.2_0402_1% H11 U13
<28> FBB_CMD12 BA0/A2 BA2/A4 DQ9 DQ17 FBB_D9 <28> <28> FBB_CMD29 BA0/A2 BA2/A4 DQ9 DQ17 FBB_D49 <28>
K10 T11 K10 T11
<28> FBB_CMD14 BA1/A5 BA3/A3 DQ10 DQ18 FBB_D10 <28> <28> FBB_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBB_D50 <28>
K11 T13 K11 T13
<28> FBB_CMD13 FBB_D11 <28> <28> FBB_CMD28 FBB_D51 <28>
1
<28> FBB_CLK0# <28> FBB_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBB_D12 <28> <28> FBB_CLK1# <28> FBB_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBB_D52 <28>
N13 N13
M11 M11
K4 M13 K4 M13
<28> FBB_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBB_D15 <28> <28> FBB_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBB_D55 <28>
H5 U4 H5 U4
H4 U2 H4 U2
K5 T4 K5 T4
J5 T2 J5 T2
<28> FBB_CMD6 A12/RFU/NC DQ3 DQ27 FBB_D3 <28> <28> FBB_CMD22 A12/RFU/NC DQ3 DQ27 FBB_D59 <28>
N4 N4
A5 N2 A5 N2
+1.35VSDGPU VPP/NC DQ5 DQ29 FBB_D5 <28> VPP/NC DQ5 DQ29 FBB_D61 <28>
U5 M4 U5 M4
VPP/NC DQ6 DQ30 FBB_D6 <28> VPP/NC DQ6 DQ30 FBB_D62 <28>
M2 M2
J10 MF J10 MF
RG119 2 1 121_0402_1% J13 SEN B1 RG120 2 1 121_0402_1% J13 SEN B1
VDDQ F1 VDDQ F1
<28> FBB_CMD7 ABI# VDDQ <28> FBB_CMD23 ABI# VDDQ
G3 P1 G3 P1
<28>
<28>
<28>
FBB_CMD0
FBB_CMD10
FBB_CMD3
G12
L3
L12
RAS#
CS#
CAS#
CAS#
WE#
RAS#
VDDQ
VDDQ
VDDQ
T1
G2
L2
+1.35VSDGPU
Near VRAM <28>
<28>
<28>
FBB_CMD19
FBB_CMD31
FBB_CMD16
G12
L3
L12
RAS#
CS#
CAS#
CAS#
WE#
RAS#
VDDQ
VDDQ
VDDQ
T1
G2
L2
<28> FBB_CMD15 WE# CS# VDDQ <28> FBB_CMD26 WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
CG188
CG189
CG190
CG204
CG226
CG192
CG193
D5 VDDQ H3 D5 VDDQ H3
<28> FBB_WCK23# WCK01# WCK23# VDDQ 1 1 1 1 1 1 1 <28> FBB_WCK45# WCK01# WCK23# VDDQ
D4 K3 D4 K3
<28> FBB_WCK23 WCK01 WCK23 VDDQ <28> FBB_WCK45 WCK01 WCK23 VDDQ
M3 M3
<28> FBB_WCK01# WCK23# WCK01# VDDQ 2 2 2 2 2 2 2 <28> FBB_WCK67# WCK23# WCK01# VDDQ
P4 T3 P4 T3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V4Z
<28> FBB_WCK01 WCK23 WCK01 VDDQ <28> FBB_WCK67 WCK23 WCK01 VDDQ
VGA@
E5 E5
C VDDQ VDDQ C
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
N5 N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBB_VREFC J14 VREFD VDDQ B12 +FBB_VREFC J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
J2 VDDQ K12 J2 VDDQ K12
+1.35VSDGPU <28> FBB_CMD2 RESET# VDDQ <28> FBB_CMD18 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
1
VDDQ G13 VDDQ G13

RG121 VGA@ H1 VDDQ L13 +1.35VSDGPU H1 VDDQ L13
549_0402_1% K1 VSS VDDQ B14 K1 VSS VDDQ B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
2
L5 VSS VDDQ M14 L5 VSS VDDQ M14
CG191
CG205
CG206
CG207
1 2 +FBB_VREFC W=16mils T5 VSS
VSS
VDDQ
VDDQ
P14 1 1 1 1 T5 VSS
VSS
VDDQ
VDDQ
P14
B10 T14 B10 T14
1
D10 VSS VDDQ D10 VSS VDDQ

VGA@ RG123
VGA@ CG214
VGA@ CG215
RG122 VGA@
820P_0402_25V7
820P_0402_25V7
1.33K_0402_1%
1 1 VSS VSS
931_0402_1% G10 G10
L10 VSS A1 2 2 2 2 L10 VSS A1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V4Z
1
D VSS VSSQ VSS VSSQ
VGA@
VGA@
VGA@
P10 C1 P10 C1
2 2 VSS VSSQ VSS VSSQ
VGA@
2 QG9 VGA@ T10 E1 T10 E1
<26,33,35> MEM_VREF
2
G MESS138W-G_SOT323-3 H14 VSS VSSQ N1 H14 VSS VSSQ N1

S +1.35VSDGPU K14 VSS VSSQ R1
Under VRAM K14 VSS VSSQ R1
3
VSS VSSQ U1 +1.35VSDGPU VSS VSSQ U1

VSSQ H2 VSSQ H2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 +1.35VSDGPU R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
+1.35VSDGPU
Near VRAM L11
P11
VDD
VDD
VSSQ
VSSQ
M5
F10
L11
P11
VDD
VDD
VSSQ
VSSQ
M5
F10
CG208
CG209
CG210
CG211
CG212
CG213
CG216
CG217
CG218
CG219
CG220
CG221
CG222
CG223
CG224
CG225
CG232
CG233
VDD VSSQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD VSSQ
B L14 C11 L14 C11 B
VDD VSSQ R11 VDD VSSQ R11
CG227
CG228
CG238
CG239
CG240
CG242
CG243
VSSQ A12 VSSQ A12

1 1 1 1 1 1 1 VSSQ VSSQ
C12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C12
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VSSQ E12 VSSQ E12
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
N12 N12
2 2 2 2 2 2 2 VSSQ R12 VSSQ R12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V4Z
VSSQ VSSQ
VGA@
170-BALL U12 170-BALL U12

VSSQ VSSQ
VGA@
H13 H13
VGA@
VGA@
VGA@
VGA@
VGA@

VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
K4G80325FB-HC25 FBGA 170P

@
VSSQ
Under VRAM K4G80325FB-HC25 FBGA 170P
@
VSSQ
18 x 1uF (0402 X6S)

+1.35VSDGPU Under VRAM 4 x 10uF (0402 X6S)
Near VRAM
CG229
CG230
CG231
CG241
CG194
CG195
CG196
CG197
CG198
CG199
CG200
CG201
CG202
CG203
CG234
CG235
CG236
CG237
CG244
CG245
CG246
CG247
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 x 22uF (0603 X6S) 2 GND/PWR vias for each cap
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0402_6.3V4Z
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A A

N17E-GDDR5_B
5 4 3 2 1
5 4 3 2 1
GDDR5_C UG16 MF=1 UG17 MF=0

A4 A4
DQ24 DQ0 FBC_D24 <29> DQ24 DQ0 FBC_D32 <29>
C2 A2 C2 A2
<29> FBC_EDC3 EDC0 EDC3 DQ25 DQ1 FBC_D25 <29> <29> FBC_EDC4 EDC0 EDC3 DQ25 DQ1 FBC_D33 <29>
C13 B4 C13 B4
R13 B2 R13 B2
R2 E4 R2 E4
E2 E2
<29> FBC_CLK0 DQ29 DQ5 FBC_D29 <29> <29> FBC_CLK1 DQ29 DQ5 FBC_D37 <29>
F4 F4
FBC_D30 <29> FBC_D38 <29>
1
<29> FBC_DBI3 DBI0# DBI3# DQ31 DQ7 FBC_D31 <29> <29> FBC_DBI4 DBI0# DBI3# DQ31 DQ7 FBC_D39 <29>
VGA@ RG126 D13 A11 VGA@ RG127 D13 A11
40.2_0402_1% P13 A13 40.2_0402_1% P13 A13
D <29> FBC_DBI1 DBI2# DBI1# DQ17 DQ9 FBC_D17 <29> <29> FBC_DBI6 DBI2# DBI1# DQ17 DQ9 FBC_D41 <29> D
P2 B11 P2 B11
B13 B13
FBC_D19 <29> FBC_D43 <29>
2
J12 DQ19 DQ11 E11 J12 DQ19 DQ11 E11
CK DQ20 DQ12 FBC_D20 <29> CK DQ20 DQ12 FBC_D44 <29>
2 1 J11 E13 2 1 J11 E13
CK# DQ21 DQ13 FBC_D21 <29> CK# DQ21 DQ13 FBC_D45 <29>
CG248 0.01U_0402_16V7K J3 F11 CG249 0.01U_0402_16V7K J3 F11
<29> FBC_CMD1 FBC_D22 <29> <29> FBC_CMD17 FBC_D46 <29>
2
VGA@ DQ23 DQ15 FBC_D23 <29> VGA@ DQ23 DQ15 FBC_D47 <29>
40.2_0402_1% H11 U13 40.2_0402_1% H11 U13
<29> FBC_CMD12 BA0/A2 BA2/A4 DQ9 DQ17 FBC_D9 <29> <29> FBC_CMD29 BA0/A2 BA2/A4 DQ9 DQ17 FBC_D49 <29>
K10 T11 K10 T11
<29> FBC_CMD14 BA1/A5 BA3/A3 DQ10 DQ18 FBC_D10 <29> <29> FBC_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBC_D50 <29>
K11 T13 K11 T13
<29> FBC_CMD13 FBC_D11 <29> <29> FBC_CMD28 FBC_D51 <29>
1
<29> FBC_CLK0# <29> FBC_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBC_D12 <29> <29> FBC_CLK1# <29> FBC_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBC_D52 <29>
N13 N13
M11 M11
K4 M13 K4 M13
<29> FBC_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBC_D15 <29> <29> FBC_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBC_D55 <29>
H5 U4 H5 U4
H4 U2 H4 U2
K5 T4 K5 T4
J5 T2 J5 T2
<29> FBC_CMD6 A12/RFU/NC DQ3 DQ27 FBC_D3 <29> <29> FBC_CMD22 A12/RFU/NC DQ3 DQ27 FBC_D59 <29>
N4 N4
A5 N2 A5 N2
+1.35VSDGPU VPP/NC DQ5 DQ29 FBC_D5 <29> VPP/NC DQ5 DQ29 FBC_D61 <29>
U5 M4 U5 M4
VPP/NC DQ6 DQ30 FBC_D6 <29> VPP/NC DQ6 DQ30 FBC_D62 <29>
M2 M2
J10 MF J10 MF
RG132 2 1 121_0402_1% J13 SEN B1 RG133 2 1 121_0402_1% J13 SEN B1
VDDQ F1 VDDQ F1
<29> FBC_CMD7 ABI# VDDQ <29> FBC_CMD23 ABI# VDDQ
G3 P1 G3 P1
<29> FBC_CMD0 RAS# CAS# VDDQ <29> FBC_CMD19 RAS# CAS# VDDQ
G12 T1 G12 T1
<29> FBC_CMD10 CS# WE# VDDQ <29> FBC_CMD31 CS# WE# VDDQ
L3 G2 L3 G2
<29> FBC_CMD3 CAS# RAS# VDDQ <29> FBC_CMD16 CAS# RAS# VDDQ
L12 L2 L12 L2
<29> FBC_CMD15 WE# CS# VDDQ <29> FBC_CMD26 WE# CS# VDDQ
B3 B3
D5
VDDQ
VDDQ
VDDQ
D3
F3
H3
+1.35VSDGPU
Near VRAM D5
VDDQ
VDDQ
VDDQ
D3
F3
H3
<29> FBC_WCK23# WCK01# WCK23# VDDQ <29> FBC_WCK45# WCK01# WCK23# VDDQ
D4 K3 D4 K3
<29> FBC_WCK23 WCK01 WCK23 VDDQ <29> FBC_WCK45 WCK01 WCK23 VDDQ
M3 M3
CG250
CG251
CG252
CG266
CG288
CG253
CG254
<29> FBC_WCK01# WCK23# WCK01# VDDQ <29> FBC_WCK67# WCK23# WCK01# VDDQ
P4 T3 1 1 1 1 1 1 1 P4 T3
<29> FBC_WCK01 WCK23 WCK01 VDDQ <29> FBC_WCK67 WCK23 WCK01 VDDQ
E5 E5
C VDDQ VDDQ C
N5 N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 2 2 2 2 2 2 2 U10 VREFD VDDQ N10
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.35VSDGPU +FBC_VREFC VREFD VDDQ +FBC_VREFC VREFD VDDQ
VGA@
VGA@
J14 B12 J14 B12
VREFC VDDQ VREFC VDDQ
VGA@
VGA@
VGA@
VGA@
VGA@
D12 D12
VDDQ F12 VDDQ F12
1
VDDQ H12 VDDQ H12

RG134 VGA@ J2 VDDQ K12 J2 VDDQ K12
<29> FBC_CMD2 RESET# VDDQ <29> FBC_CMD18 RESET# VDDQ
549_0402_1% M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
2
VDDQ G13 VDDQ G13

1 2 +FBC_VREFC W=16mils H1
VSS
VDDQ
VDDQ
L13 H1
VSS
VDDQ
VDDQ
L13
K1 B14 K1 B14
1
B5 VSS VDDQ D14 B5 VSS VDDQ D14

VGA@ RG136
VGA@ CG276
VGA@ CG277
RG135 VGA@
820P_0402_25V7
820P_0402_25V7
1.33K_0402_1%
1 1 VSS VDDQ VSS VDDQ

931_0402_1% G5 F14 +1.35VSDGPU G5 F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
1
D T5 VSS VDDQ P14 T5 VSS VDDQ P14

2 QG10 VGA@ 2 2 B10 VSS VDDQ T14 B10 VSS VDDQ T14
<26,33,34> MEM_VREF
2
G MESS138W-G_SOT323-3 D10 VSS VDDQ D10 VSS VDDQ

G10 VSS G10 VSS
CG255
CG267
CG268
CG269
S
3
L10 VSS A1 L10 VSS A1

VSS VSSQ 1 1 1 1 VSS VSSQ
P10 C1 P10 C1
T10 VSS VSSQ E1 T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
+1.35VSDGPU K14 VSS VSSQ R1 2 2 2 2 K14 VSS VSSQ R1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSS VSSQ +1.35VSDGPU VSS VSSQ
VGA@
VGA@
VGA@
VGA@
U1 U1
VSSQ H2 VSSQ H2
L1
G4
L4
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
A3
C3
E3
Under VRAM L1
G4
L4
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
A3
C3
E3
+1.35VSDGPU Near VRAM C5

R5
C10
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
N3
R3
U3
C5
R5
C10
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
N3
R3
U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 +1.35VSDGPU D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
CG289
CG290
CG300
CG301
CG302
CG291
CG292
L11 VDD VSSQ M5 L11 VDD VSSQ M5

1 1 1 1 1 1 1 VDD VSSQ VDD VSSQ
P11 F10 P11 F10
CG264
CG265
CG270
CG271
CG272
CG273
CG274
CG275
CG278
CG279
CG280
CG281
CG282
CG283
CG284
CG285
CG286
CG287
L14 VDD VSSQ C11 L14 VDD VSSQ C11
B
VDD VSSQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD VSSQ B
2 2 2 2 2 2 2 R11 R11
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSSQ VSSQ
VGA@
VGA@
A12 A12
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
C12 C12
VSSQ E12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VSSQ E12
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VSSQ N12 VSSQ N12
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
R12 R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 VSSQ H13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
K4G80325FB-HC25 FBGA 170P
@ Under VRAM K4G80325FB-HC25 FBGA 170P
@
+1.35VSDGPU
Under VRAM 18 x 1uF (0402 X6S)
4 x 10uF (0402 X6S)
CG293
CG303
CG304
CG305
CG256
CG257
CG258
CG259
CG260
CG261
CG262
CG263
CG294
CG295
CG296
CG297
CG298
CG299
CG306
CG307
CG308
CG309
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Near VRAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VGA@
VGA@
VGA@
5 x 22uF (0603 X6S) 2 GND/PWR vias for each cap

VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A A

N17E-GDDR5_C
5 4 3 2 1
A B C D E F G H
+3VSDGPU
1
CG310 VGA@
1.8K_0402_1%
1.8K_0402_1%
VGA@ RG138
VGA@ RG139
0.1U_0201_10V6K
1
2
1 2
<66> CSSN_B+
10U_0603_6.3V6M
VGA@ CG311
RG137 VGA@ 2 UG18 +3VSDGPU
10_0402_1%
2
4 16
VS VPU +1.8VSDGPU_AON
1
RG140 VGA@ 1
10_0402_1% VIN1N 11 13 RG141
1 1 2 VIN1P 12 IN-1 TC 10K_0402_1% 1
<66> CSSP_B+ IN+1 10 VGA@
2
1 2 VIN2N 14 PV
<66> CSSN_NVVDD IN-2
2
10U_0603_6.3V6M
VIN2P 15 9 1 @ 2
G
IN+2 Critical
VGA@ CG312
RG142 VGA@ 2 RG143 0_0402_5%
10_0402_1% VIN3N 1 8 1 3
VIN3P 2 IN-3 Warning OC_WARN# <26>
S
IN+3 5 2 1
RG145 VGA@ 1 6 A0 3
<26> I2CC_SCL SCL GND QG17
665K_0402_1%
665K_0402_1%
665K_0402_1%
VGA@ RG147
VGA@ RG148
VGA@ RG149
10_0402_1% 7 17 RG144
<26> I2CC_SDA SDA ThermalPad
1
1 2 10K_0402_1% MESS138W-G_SOT323-3
<66> CSSP_NVVDD
INA3221AIRGVR_VQFN16_4X4 VGA@ VGA@
1 2 VGA@
<68> CSSN_NVVDDS
10U_0603_6.3V6M
VGA@ CG313
RG146 VGA@ 2
2
10_0402_1%
RG150 VGA@ 1
10_0402_1%
1 2
<68> CSSP_NVVDDS
+3VS
UG104
GPK@
0.1U_0201_10V6K 2 1 CG938 1
VDD PEX_VDD_EN
20
1VSDGPU_EN <26,64> +1.8VALW to +1.8VSDGPU_AON & +1.8VSDGPU_MAIN
2 19
<26,65> NVVDD1_PG NVVDD1_PG FBVDDQ_EN 1.35VSDGPU_EN <26,63>
2 3 18 +1.8VSDGPU_AON 2
<26> OVERT# OVERT# NVVDD1_EN NVVDD1_EN <26,65>
4 DG8
<26,43> GPU_OVERT# GPU_OVERT# 17 DGPU_PWR_EN 3
NVVDD2_EN NVVDD2_EN <26,68> 1V8_AON_EN 1
5 1 @ CG936
<26,68> NVVDD2_PG NVVDD2_PGOOD 2 0.1U_0201_10V6K
6 16 <63> 1.35VSDGPU_PG
<26> GPU_GC6_FB_EN GPU_GC6_FB_EN 1V8_MAIN_EN 1.8VSDGPU_MAIN_EN3V3 <26>
1
BAV70W_SOT323-3 +1.8VALW +1.8VSDGPU_AON 2
7 NGPK@ RG155 NGPK@ UG27
<20,26> GC6_FB_EN3V3 GC6_FB_EN 15 3VSDGPU_EN_R 1 14
100K_0402_5%
8 3V3_SYS_EN 2 VIN1 VOUT1 13
<17,19,26,43,49> PLT_RST# PCH_PLTRST# VIN1 VOUT1
10U_0603_6.3V6M
CG334 VGA@
CG335 220P_0402_50V7K
2
14 1V8_AON_EN 1V8_AON_EN 3 12 1 2
1V8_AON_EN ON1 CT1 1
+5VALW VGA@
9 13 4 11
<20,26> DGPU_HOLD_RST# DGPU_HOLD_RST# GPIO4_1V8_MAIN_EN 1.8VSDGPU_MAIN_EN <26> VBIAS GND CG336 220P_0402_50V7K
12 1.8VSDGPU_MAIN_EN 1 @ 2 1.8VSDGPU_MAIN_EN3V3 5 10 1 2 2
10 DGPU_PWR_EN DGPU_PWR_EN <20,26> ON2 CT2 +1.8VSDGPU_MAIN
RG200 0_0201_5% VGA@
<25,26> DGPU_PEX_RST# DGPU_PEX_RST# +1.8VALW 6 9 +1.8VSDGPU_MAIN
1 VIN2 VOUT2
VGA@ CG337 7 8
VIN2 VOUT2
10U_0603_6.3V6M
@ 11 0.1U_0201_10V6K
GND
22U_0603_6.3V6M
CG338 VGA@
CG939 1 2 0.1U_0201_10V6K OVERT# 15 1 1
2 GPAD
CG339 VGA@
@ @ CG935
1
CG940 1 2 0.1U_0201_10V6K DGPU_PEX_RST# SLG4U41989VTR_STQFN20_3X2 EM5209VF_DFN14_2X3 0.1U_0201_10V6K
@ GPK@ VGA@
CG941 1 2 0.1U_0201_10V6K 1.8VSDGPU_MAIN_EN 2 2
2
Reserve for 1.8V O.D. pin.
3 3
+1.0VSDGPU
+1.8VSDGPU_AON +5VS For Power down sequence

2
RG192 VGA@ +NVVDD1
5
UG19 20_0402_5% +1.35VSDGPU

2
RG151
VCC
DGPU_PWR_EN 1 10K_0402_5% RG193 VGA@

1
IN B
1
4 3VSDGPU_EN_1 1 2 3VSDGPU_EN_R 100K_0402_5% +5VS
1.8VSDGPU_MAIN_EN3V3 2 OUT Y NGPK@ +5VS R40 VGA@ RG194 VGA@
GND
IN A
1
20_0402_5% 1_0603_5%
1
1
RG225
2
NL17SZ08DFT2G_SC70-5 CG315 NGPK@ 1M_0402_5% NVVDD2_EN# 2 G
D
QG18B VGA@
3
2
2
NGPK@ 0.22U_0201_6.3V6K VGA@ S PJT138KA_SOT363-6 VGA@ RG196
2
RG195 VGA@ 100K_0402_5%

2
100K_0402_5% VGA@ QG20B

VGA@ QG18A PJT138KA_SOT363-6
6
PJT138KA_SOT363-6 QG19B VGA@
1
3
3
D 2N7002KDW_SOT363-6 NVVDD1_EN# 2 G
D
NVVDD2_EN 5 G
D
1.35VSDGPU_EN# 5
+3VS/+3VSDGPU
S
S +NVVDD2 G VGA@ QG20A
1
+1.8V/+3.3V level PJT138KA_SOT363-6
4
+3VS
3
S
4
1
NVVDD1_EN 5 G
D
UG20
RG197 VGA@ VGA@ QG19A S
+3VSDGPU
6
1 2N7002KDW_SOT363-6 D
1_0603_5% +1.8V/+3.3V level
4
2 VIN1 1.35VSDGPU_EN 2
1 VIN2
VGA@ CG314 G
2
1U_0402_6.3V6K 7 6
VIN thermal VOUT +3.3V level S
1
1
2 D
3 1 1
+5VALW VBIAS
10U_0603_6.3V6M
CG316
0.1U_0201_10V6K
CG317
4 2 QG21 VGA@ 4
3VSDGPU_EN_R 4 5 G
ON GND L2N7002WT1G_SC-70-3
S SB00001GE00
3
2 2
1
VGA@ CG319 AOZ1334DI-01_DFN8-7_3X3
VGA@
VGA@
0.1U_0201_10V6K VGA@
2
GPU power control
A B C D E F G H
A B C D E
SM01000EJ00 3000ma
220ohm@100mhz
LCD POWER CIRCUIT DCR 0.04
+3VS +LCDVDD +19VB_CPU +INVPW R_B+

Place closed to
UX1 W=60mils JEDP1 +LCDVDD
+3VS
1U_0402_6.3V6K
CX2
5 1 W=60mils W=60mils
IN OUT LX1 EMI@
1 1 1
2 HCB2012KF-221T30_0805
10U_0603_6.3V6M
1 1
0.1U_0201_10V6K
0.1U_0201_10V6K
GND 1 2 CX7 1 1 1
4 3 CX3 CX4 1 @
2 EN OC 0.1U_0201_10V6K CX6 CX8 CX1
2 2 1
SY6288C20AAC_SOT23-5 @ CX5 1000P_0402_50V7K
10U_0603_6.3V6M 68P_0402_50V8J EMI@ 2 2 2
<18,26> PCH_ENVDD 2
@ESD@
1
2
RX1
100K_0402_5%
2
RX3
0_0402_5%
<17> EDP_HPD 1 @ 2 EDP_HPD_R
EDP_HPD_R <26> LED PANEL Conn.
+3VS
1
+INVPW R_B+ JEDP1
RX4
W=60mils 1
100K_0201_5% 1 DIS@ 2 RG221 EDP_AUXN_C 2 1
100K_0402_5% 2
3
100K_0201_5% 1 DIS@ 2 RG222 EDP_AUXP_C 4 3
2
5 4
100K_0201_5% 1 DIS@ 2 RG223 EDP_AUXN PCH_BKL_PW M 6 5
2 BKOFF# 7 6 2
100K_0201_5% 1 DIS@ 2 RG224 EDP_AUXP +LCDVDD EDP_HPD_R 8 7
9 8
10 9
RX10 1 @ 2 100K_0402_5% 11 10
12 11
@ESD@ 13 12
PCH_BKL_PW M CX9 1 2 220P_0402_50V7K EDP_AUXN CX20 1 2 0.1U_0201_10V6K EDP_AUXN_C 14 13
<18,26> PCH_BKL_PW M <7> EDP_AUXN EDP_AUXP CX19 EDP_AUXP_C 14
<7> EDP_AUXP 1 2 0.1U_0201_10V6K 15
@ESD@ 16 15
BKOFF# CX10 1 2 220P_0402_50V7K EDP_TXP0 CX11 1 2 0.1U_0201_10V6K EDP_TXP0_C 17 16
<43> BKOFF# <7> EDP_TXP0 EDP_TXN0 CX12 EDP_TXN0_C 17
1 2 0.1U_0201_10V6K 18
<7> EDP_TXN0 18
19
RX5 1 @ 2 10K_0402_5% EDP_TXP1 CX13 1 2 0.1U_0201_10V6K EDP_TXP1_C 20 19
<7> EDP_TXP1 EDP_TXN1 CX14 EDP_TXN1_C 20
1 2 0.1U_0201_10V6K 21
<7> EDP_TXN1 21
22
EDP_TXP2 CX15 1 2 0.1U_0201_10V6K EDP_TXP2_C 23 22
1 2 0.1U_0201_10V6K 24
<7> EDP_TXN2 24
25
EDP_TXP3 CX17 1 2 0.1U_0201_10V6K EDP_TXP3_C 26 25
1 2 0.1U_0201_10V6K 27
<7> EDP_TXN3 27
28
29 28
USB Touch Screen <15> USB20_P6
<15> USB20_N6
30 29
30
31
+TS_PW R 32 31
Touch +TS_PW R 32
+5VS +3VS 33
Screen TS_EN 33
RX6 1 @ 2 0_0603_5% 34
<20,43> TS_EN 34
+3VS 35
3 RX7 1 2 0_0603_5% USB20_N5_CAMERA 36 35 41 3
USB20_P5_CAMERA 37 36 G1 42
For 37 G2
Camera 38 43
DMIC_CLK_R 39 38 G3 44
<42> DMIC_CLK_R DMIC_DATA_R 39 G4
40 45
Camera <42> DMIC_DATA_R 40 G5
ACES_50398-04041-001
CONN@
RX8 1 @ 2 0_0402_5% USB20_N5_CAMERA
<15> USB20_N5 DMIC_CLK_R SP010013I00
RX9 1 @ 2 0_0402_5% USB20_P5_CAMERA
<15> USB20_P5 DMIC_DATA_R
2
DX1
YSLC05CH_SOT23-3
@ESD@
1
4 4

eDP CONN.
A B C D E
A B C D E
RPY2
HDMI_CLKN 1 8 HDMI_GND
CY22 1 2 .1U_0402_16V7K HDMI_CLKP HDMI_CLKP 2 7
<27> GPU_DP3_P3 HDMI_CLKN HDMI_TX_N0
CY24 1 2 .1U_0402_16V7K 3 6
<27> GPU_DP3_N3 HDMI_TX_P0 4 5
1 CY16 1 2 .1U_0402_16V7K HDMI_TX_P0 1
<27> GPU_DP3_P2 HDMI_TX_N0
CY17 1 2 .1U_0402_16V7K 499_0804_8P4R_1%
<27> GPU_DP3_N2
CY18 1 2 .1U_0402_16V7K HDMI_TX_P1 RPY3
<27> GPU_DP3_P1 HDMI_TX_N1 HDMI_TX_N1
CY19 1 2 .1U_0402_16V7K 1 8
<27> GPU_DP3_N1 HDMI_TX_P1 2 7
CY20 1 2 .1U_0402_16V7K HDMI_TX_P2 HDMI_TX_N2 3 6
<27> GPU_DP3_P0 HDMI_TX_N2 HDMI_TX_P2
CY21 1 2 .1U_0402_16V7K 4 5
<27> GPU_DP3_N0
499_0804_8P4R_1%
+5VS W=40mils +HDMI_5V_OUT
3
D
+3VS 5 QY2B
G UY2
2N7002KDW _SOT363-6
S 3
4
OUT
1
HDMI_CLKP RY15 1 2 6.04_0402_1% HDMI_R_CLKP 1
IN CY23
2 0.1U_0201_10V6K
GND
2
@EMI@ CY26 2
3.3P_0402_50V8
AP2330W -7_SC59-3
1
HDMI_CLKN RY14 1 2 6.04_0402_1% HDMI_R_CLKN
2 2
+HDMI_5V_OUT
HDMI_TX_P0 HDMI_R_TX_P0 RPY1
RY16 1 2 6.04_0402_1%
HDMI_CTRL_DAT 8 1
HDMI_TX_N0 RY17 1 2 6.04_0402_1% HDMI_R_TX_N0 HDMI_CTRL_CLK 7 2 +1.8VSDGPU_AON
DY2 GPU_DP3_CTRL_CLK 6 3
HDMI_R_CLKN 1 1 10 9 HDMI_R_CLKN GPU_DP3_CTRL_DAT 5 4
HDMI_R_CLKP 2 2 9 8 HDMI_R_CLKP 2.2K_0804_8P4R_5%
HDMI_TX_P1 RY18 1 2 6.04_0402_1% HDMI_R_TX_P1
HDMI_R_TX_N04 4 7 7 HDMI_R_TX_N0
HDMI_TX_N1 RY19 1 2 6.04_0402_1% HDMI_R_TX_N1
HDMI_R_TX_P05 5 6 6 HDMI_R_TX_P0
3 3
L05ESDL5V0NA-4 SLP2510P8
HDMI_TX_P2 RY20 1 2 6.04_0402_1% HDMI_R_TX_P2 ESD@
HDMI_TX_N2 RY22 1 2 6.04_0402_1% HDMI_R_TX_N2 SC300003Z00 +HDMI_5V_OUT HDMI connector
DY3 JHDMI1
HDMI_R_TX_N11 1 10 9 HDMI_R_TX_N1 HDMI_HPD 19
18 HP_DET
HDMI_R_TX_P12 2 HDMI_R_TX_P1 +5V
9 8 17
+3VS +3VS HDMI_CTRL_DAT 16 DDC/CEC_GND
3 HDMI_R_TX_N24 4 HDMI_R_TX_N2 HDMI_CTRL_CLK SDA 3
7 7 15
14 SCL
Reserved
2
HDMI_R_TX_P25 5 6 6 HDMI_R_TX_P2 13
HDMI_R_CLKN 12 CEC
RY24 3 3 11 CK-
CK_shield
2
1M_0402_5% HDMI_R_CLKP 10
G
QY2A 8 HDMI_R_TX_N0 9 CK+

1
2N7002KDW _SOT363-6 8 D0-

L05ESDL5V0NA-4 SLP2510P8 HDMI_R_TX_P0 7 D0_shield
1 6 HDMI_HPD ESD@ HDMI_R_TX_N1 6 D0+
S
<17,26> HDMI_HPD_PCH D1-

D
SC300003Z00 5
HDMI_R_TX_P1 4 D1_shield 20
D1+ GND
2
HDMI_R_TX_N2 3 21
RY11 DY1 2 D2- GND 22
RY11 design guide rev2.0 use 20K pull down. 100K_0402_5% HDMI_HPD 6 3 HDMI_CTRL_CLK HDMI_R_TX_P2 1 D2_shield GND 23
I/O4 I/O2 D2+ GND
CCM_C100042GR019M298ZL
1
CONN@
5 2
VDD GND
+1.8VSDGPU_AON ZZZ2
DC232003500
HDMI_CTRL_DAT 4 1
I/O3 I/O1 +HDMI_5V_OUT
AZC099-04S.R7G_SOT23-6
ESD@
5
QY1A HDMI_ROYALTY
PJT138KA_SOT363-6 ROYALTY HDMI W /LOGO+HDCP
G
4 3 HDMI_CTRL_CLK RO0000003HM
4 <27> GPU_DP3_CTRL_CLK 4
S
45@
2
QY1B
PJT138KA_SOT363-6
G
1 6 HDMI_CTRL_DAT
<27> GPU_DP3_CTRL_DAT Security Classification Compal Secret Data Compal Electronics, Inc.
S
3ohm/10pF Issued Date 2017/07/20 Deciphered Date 2018/07/20 Title
HDMI CONN.
A B C D E
5 4 3 2 1
+3VS +3VS_SSD_NGFF
RM1 @
0_0805_5%
1 2
1
10U_0603_6.3V6M
0.1U_0201_10V6K
1 2
+ CM3
CM1 CM2 150U_6.3V_M_D2
2 1 2
SGA00009000
D D
+3VS_SSD_NGFF
M.2 SSD
JSSD1
1 2
3 GND 3P3VAUX 4
5 GND 3P3VAUX 6
<18> PCIE_PRX_DTX_N9 7 PERn3 NC 8
<18> PCIE_PRX_DTX_P9 9 PERp3 NC 10
CM6 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N9 11 GND DAS/DSS# 12
<18> PCIE_PTX_DRX_N9 CM4 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P9 13 PETn3 3P3VAUX 14
<18> PCIE_PTX_DRX_P9 15 PETp3 3P3VAUX 16 ESD@
17 GND 3P3VAUX 18 SSD_RST#_R CM16 2 1 100P_0402_50V8J
<18> PCIE_PRX_DTX_N10 19 PERn2 3P3VAUX 20
CM5 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N10 23 GND NC 24
<18> PCIE_PTX_DRX_N10 CM7 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P10 25 PETn2 NC 26
Place close to JSSD pin 50
<18> PCIE_PTX_DRX_P10 27 PETp2 NC 28
29 GND NC 30
ESD request to reserve.
<18> PCIE_PRX_DTX_N11 31 PERn1 NC 32
<18> PCIE_PTX_DRX_N11 CM9 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P11 37 PETn1 NC 38 RM2 1 @ 2 0_0402_5%
<18> PCIE_PTX_DRX_P11 PETp1 DEVSLP SSD_DEVSLP1 <18>
39 40
41 GND NC 42 RM4 1 @ 2 0_0402_5%
<18> PCIE_PRX_DTX_P12 43 PERn0/SATA-B+ NC 44
C <18> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- NC 46 C
<18> PCIE_PTX_DRX_N12 CM11 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P12 49 PETn0/SATA-A- NC 50 SSD_RST#_R RM6 1 @ 2 0_0402_5%
<18> PCIE_PTX_DRX_P12 PETp0/SATA-A+ PERST# SSD_CLKREQ#_R PLT_RST_BUF# <17,40,41>
51 52 RM7 1 @ 2 0_0402_5% SSD_CLKREQ# <16>
53 GND CLKREQ# 54
<16> CLK_PCIE_NGFF# REFCLKN PEWake#
<16> CLK_PCIE_NGFF 55 56
57 REFCLKP NC 58
GND NC
59 60 SUSCLK_SSD RM8 1 @ 2 0_0402_5%

SSD_DET# NC SUSCLK(32kHz) SUSCLK <19,41>
61 62
63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
65 GND 3P3VAUX 66
GND 3P3VAUX +3VS_SSD_NGFF
67
GND 68
+3VS_SSD_NGFF GND1 69
GND2
BELLW _80159-3221
CONN@
2
RM9 @
SP070018L00
Pull high at PCH side 10K_0402_5%
1
RM10
1 @ 2 SSD_DET#
B <18> SATA_GP1 B
0_0402_5%
1
D
@ QM1 2
BSS138W -7-F_SOT323-3 G SSD_RST#_R 2 @ 1 +3VS
S RM44 10K_0402_5%
3
SSD_CLKREQ#_R 2 @ 1
SSD_DET# RM45 10K_0402_5%
+3VS
SATA Device 0
PCIE Device 1 reserve for Optane Memory
A A

mSATA-SSD
5 4 3 2 1
A B C D E
LAN-RTL8411B
LDO mode
W=60mil RL1 2 @ 1 0_0603_5% W=60mil
+LAN_VDD +3V_LAN
W=60mil
300mA 1.4A
SWR@ IDC=1200mA
+REGOUT LL1 1 2
+3VALW +3V_LAN 2.2UH_HPC252012NF-2R2M_20%
4.7U_0402_6.3V6M
0.1U_0201_10V6K
CL28 SWR@
1U_0402_6.3V6K
CL8
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CL10
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1
CL2
RL2 @ 1 Using for Switch mode 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL1
0.1U_0201_10V6K
CL3
0.1U_0201_10V6K
CL4
0.1U_0201_10V6K
CL5
0.1U_0201_10V6K
CL6
0.1U_0201_10V6K
CL7
CL9
CL11
CL12
CL13
0_0805_5%
1 2 The trace length from
SWR@
SWR@
Lx to PIN48 (REGOUT)
2 2 2 2 2 2 2 2 2 2 2 2 2 2
LDO@
60mil 60mil and from C to Lx must
UL1 < 200mils.
5 1
IN OUT
2
GND Using for Switch mode
Place near Pin 3,8,33,46 Place near Pin 20 Place near Pin 11,32,48
4 3 11/27: P/N change to SH00000RT00
EN OC The trace length
2 ( S COIL 2.2UH +-20%
SY6288C20AAC_SOT23-5 from C to
CL14 HPC252012NF-2R2M 1.3A) PIN34,35(VDDREG)
1U_0402_6.3V6K must < 200mils.
1 LAN_PWR_EN
LAN_PWR_EN <43>
PVT modify 01/06
+3V_LAN UL2 R2534, R2537, R2539, R2535, R2536
RL5 1 2 10K_0402_5% Power Manahement/Isolation change to R-short
From EC ISOLATEB 31
RL3 2 @ 1 0_0402_5% LAN_PME# 39 ISOLATEBPIN
<17,43> EC_PME# LANWAKEB
High active. Card Reader
15 SD_D0 RL6 1 @ 2 0_0402_5% SD_D0_R
EN threshold voltage min:1.2V reserve EC_PME# pull high 100K to +3VALW_EC SD_D0/MS_D1
PCI-Express 14 SD_D1 RL7 1 @ 2 0_0402_5% SD_D1_R
typ:1.6V max:2.0V CLK_PCIE_LAN SD_D1 SD_CLK SD_CLK_R
Current limit threshold 1.5~2.8A <16> CLK_PCIE_LAN 23 16 RL4 1 2 10_0402_1%
CLK_PCIE_LAN# 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD RL8 1 @ 2 0_0402_5% SD_CMD_R
<16> CLK_PCIE_LAN# REFCLK_N SD_CMD/MS_D2 SD_D3 SD_D3_R
+3V_LAN Rising time must >0.5ms and <100ms 18 RL9 1 @ 2 0_0402_5% 2
PLT_RST_BUF# 30 SD_D3/MS_D3 19 SD_D2 RL10 1 @ 2 0_0402_5% SD_D2_R
<17,39,41> PLT_RST_BUF# LAN_CLKREQ# PERSTBPIN SD_D2/MS_CLK SD_WP
29 28 CL16
+3VS <16> LAN_CLKREQ# CLKREQBPIN SD_WP/MS_BS
5P_0402_50V8C
CL15 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P14 25 1
<18> PCIE_PRX_DTX_P14 PCIE_PRX_C_DTX_N14 HSOP @EMI@
CL17 1 2 .1U_0402_16V7K 26
<18> PCIE_PRX_DTX_N14 HSON
1
21 42 SD_CD#
<18> PCIE_PTX_C_DRX_P14 HSIP SD_CD# close to pin17
RL15 <18> PCIE_PTX_C_DRX_N14
22 43
2
1K_0402_5% HSIN MS_CD# 2
Transceiver Interface
LAN_MIDI0+ 1
2
ISOLATEB LAN_MIDI0- 2 MDIP0

LAN_MIDI1+ 4 MDIN0
MDIP1
2
LAN_MIDI1- 5 48 +3V_LAN
RL18 LAN_MIDI2+ 6 MDIN1 AVDD33 11 Protect cotact Card contact
LAN_MIDI2- 7 MDIP2 AVDD33 12
15K_0402_5% MDIN2 DVDD33
1400mA
LAN_MIDI3+ 9 32
LAN_MIDI3- 10 MDIP3 DVDD33 Write protect Write Enable
1
MDIN3
RL14 +LAN_VDD
(Lock) (Unlock)
1K_0402_5% XTLI 44 33
XTLO_R 1 2 XTLO 45 CKXTAL1 Clock DVDD10 3 Card Uninsert Open Open Open
+3V_LAN CKXTAL2 AVDD10 8 300mA
SWR mode
AVDD10 Card insert Open Close Close
Regulator and Reference
RL11 1 SWR@2 0_0402_5% +REGOUT 36 20
35 REG_OUT EVDD10
+3V_LAN VDDREG +CARD_3V3
RL13 1 @ 2 0_0402_5% ENSWREG ENSWREG 34 800mA
46 ENSWREG_H 13
+LAN_VDD AVDD10 Card_3V3
LDO mode LAN_RST
2 RL16 1 47
2.49K_0402_1% RSET 27 +VDD33_18
DV33/18
@ T45
0.1U_0201_10V6K
4.7U_0402_6.3V6M
41
1 @ 2 GPO 38 LED0
<19> LAN_GPO LED1/GPO 1 1 1
+3V_LAN
CL20
CL21
RL17 0_0402_5% 37 LEDs
for disable PHY 40 LED3 CL22
@ T46 LED_CR
RL12 1 @ 2 10K_0402_5% GPO reserve 0 ohm 49 @
@ T47 E_Pad 0.1U_0201_10V6K
2 2 2
YL1
25MHZ_20PF_XRCGB25M000F2P18R0
XTLO_R
Place near Pin 27
3 XTLI 3 1 3
3 1 RTL8411B-CGT_QFN48_6X6
NC NC
CL18
1
4 2
1
CL19 +CARD_3V3 Card Reader Connector
15P_0402_50V8J 15P_0402_50V8J
JSD1
2 2
Close to Card Reader CONN
6
SD_CMD_R 3 VDD
P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0) SD_WP# SD_WP SD_CLK_R CMD
4.7U_0402_6.3V6M
0.1U_0201_10V6K
RL22 1 @ 2 0_0402_5% 7
LAN Connector CLK
CL23
CL24
1 1 5
8 VSS1
TL1 JRJ45 +3V_LAN +3VS VSS2
SD_D0_R 9
LAN_TERMAL1 24 12 2 2 SD_D1_R 10 DAT0
TCT1 MCT1 GND DAT1
2
LAN_MIDI0+ 2 23 RJ45_MIDI0+ RJ45_MIDI3- 8 SD_D2_R 1
TD1+ MX1+ PR4- DAT2
2
LAN_MIDI0- 3 22 RJ45_MIDI0- 11 RL21 RL20 SD_D3_R 2
TD1- MX1- RJ45_MIDI3+ 7 GND 100K_0402_5% @ 100K_0402_5% CD/DAT3
4 21 PR4+ SD_WP 12
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ RJ45_MIDI1- 6 GND 13
1
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- PR2- SD_WP# 11 GND
1
TD2- MX2- W/P
1
RJ45_MIDI2- 5 D SD_CD# 4
7 18 PR3- SD_WP# 2 QL1 CD
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_MIDI2+ 4 G TAITW_PSDATQ09GLBS1NN4H1
TD3+ MX3+ PR3+ L2N7002WT1G_SC-70-3
LAN_MIDI2- 9 16 RJ45_MIDI2- S SB00001GE00 CONN@
3
TD3- MX3- RJ45_MIDI1+ 3
10 15 PR2+ CL26
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ RJ45_MIDI0- 2
40mil 10P_0402_50V8J
40mil SP011611110
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3- PR1- 10 LANGND 2 1 RJ45_GND
TD4- MX4- RJ45_MIDI0+ 1 GND RL19 @EMI@ CL27 @EMI@
PR1+ 9 0_0402_5% 10P_0402_50V8J
1 GND
3
SD_CLK_R 1 2 1 2
4
3
2
1
MESC5V02BD03_SOT23-3
GST5009-E @
CL25 SP050006B10 RPL1 SINGA_2RJ1660-000111F DL1
0.1U_0201_10V6K 2 75_0804_8P4R_1% CONN@ ESD@ JPL1 Close to JREAD1 for EMI
4 Place close to TCT pin JUMP_43X118 4
DC234009H00
5
6
7
8
LANGND
RJ45_GND
1

LAN RTL8411H
A B C D E
A B C D E
Wireless LAN
+3VALW W=60mils +3VS_W LAN
UM1
1U_0402_6.3V6K
CM15
5 1
IN OUT
1
2
@ GND
1 1
4 3
2 <43> W LAN_ON EN OC
SY6288C20AAC_SOT23-5
IOAC@
+3VS 60mil +3VS_W LAN
RM11 1 NIOAC@ 2 0_0805_5%

1 1 1
CM12 @ CM13
4.7U_0402_6.3V6M 0.1U_0201_10V6K CM14
0.1U_0201_10V6K
2 2 2
UART_2_PRXD_R_DTXD RM42 1 UART@ 2 0_0402_5%
UART_2_PTXD_R_DRXD UART_2_PRXD_DTXD <20>
RM43 1 UART@ 2 0_0402_5%
UART_2_PTXD_DRXD <20>
+3VALW 60mil +3VS_W LAN

Co-layout with CNVi PH +3VS at SOC side,
for win7 USB3 debug
RM46 1 @ 2 0_0805_5%
KEY E +3VS_W LAN
JNGFF1
1 2
GND_1 3.3VAUX_2 CNVI@
3 4 1 RM41 2
<15> USB20_P14 USB_D+ 3.3VAUX_4
For BT 5 6 @ T52 75K_0402_1%
<15> USB20_N14 USB_D- LED1#
7 8
2 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RM34 1 @ 2 0_0201_5% 2
<16> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <19>
<16> CNV_PRX_DTX_P1 11 12
13 SDIO_CMD PCM_OUT 14 CLKREQ_CNV#_R RM35 1 @ 2 0_0201_5%
SDIO_DAT0 PCM_IN CLKREQ_CNV# <19>
<16> CNV_PRX_DTX_N0 15 16 @ T53
17 SDIO_DAT1 LED2# 18
<16> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18
19 20
21 SDIO_DAT3 UART_WAKE 22 UART_2_PRXD_R_DTXD RM36 1 CNVI@ 2 0_0402_5%
<16> CLK_CNV_PRX_DTX_N SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <16>
23
<16> CLK_CNV_PRX_DTX_P SDIO_RST
24 UART_2_PTXD_R_DRXD RM37 1 CNVI@ 2 0_0402_5%
UART_RX CNV_RGI_PRX_R_DTX CNV_RGI_PTX_DRX <16>
25 26 RM38 1 @ 2 0_0201_5%
GND_33 UART_RTS CNV_BRI_PTX_R_DRX CNV_RGI_PRX_DTX <16>
27 28 RM39 1 @ 2 0_0201_5% CNV_BRI_PTX_DRX <16>
<18> PCIE_PTX_C_DRX_P15 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
29 30 RM12 2 @ 1 0_0402_5%
<18> PCIE_PTX_C_DRX_N15 PET_RX_N0 CLink_RST E51RXD_P80CLK_R E51TXD_P80DATA <43>
31 32 RM13 2 @ 1 0_0402_5%
NGFF WL+BT (KEY E) (link to PICE Port 15)
PCIE X1
<18> PCIE_PRX_DTX_P15 33
35
GND_39
PER_TX_P0
CLink_DATA
CLink_CLK
34
36
E51RXD_P80CLK <43>
<18> PCIE_PRX_DTX_N15 PER_TX_N0 COEX3

37 38
39 GND_45 COEX2 40
<16> CLK_PCIE_W LAN REFCLK_P0 COEX1 SUSCLK_R
41 42 RM14 1 @ 2 0_0402_5%
<16> CLK_PCIE_W LAN# REFCLK_N0 SUSCLK(32KHz) W L_RST#_R SUSCLK <19,39>
(From PCH CLKOUT2) 43 44 RM15 1 @ 2 0_0402_5%
GND_51 PERST0# BT_ON PLT_RST_BUF# <17,39,40>
PCIE CLK <16> W LAN_CLKREQ# 45 46
CLKREQ0# W_DISABLE2# W L_OFF# BT_ON <43>
47 48
<43> W LAN_PME# PEWAKE0# W_DISABLE1# W L_OFF# <43>
49 50
51 GND_57 I2C_DAT 52
<16> CNV_PTX_DRX_N1 RSVD/PCIE_RX_P1 I2C_CLK
53 54
<16> CNV_PTX_DRX_P1 RSVD/PCIE_RX_N1 I2C_IRQ REFCLK_CNV_R
55 56 RM40 1 CNVI@ 2 0_0201_5% REFCLK_CNV <16>
57 GND_63 RSVD_64 58
<16> CNV_PTX_DRX_N0 RSVD/PCIE_TX_P1 RSVD_66 For CNVi Feature
59 60
<16> CNV_PTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
61 62
3 63 GND_69 RSVD_70 64 3
<16> CLK_CNV_PTX_DRX_N RSVD_71 3.3VAUX_72
65 66
<16> CLK_CNV_PTX_DRX_P RSVD_73 3.3VAUX_74
67
GND_75 68
69 GND1
GND2
BELLW _80152-3221
CONN@ E51TXD_P80DATA_R
SP070013E00
1
RM19
100K_0402_5%
2 1 W LAN_PME#
+3VS_W LAN
RM16 10K_0402_5%
2
2 1 BT_ON
RM47 10K_0402_5%
For CNVi Card
4 4

M.2 Key E (WLAN)
A B C D E
A B C D E
DMIC3/4 Conn. (support on 256)

HD Audio Codec 2000mA 600ohm@100MHz
+3VS
DCR 0.1
+VDDA
40mil +5VS_PVDD
LA1 JDMIC1
FBMA-L11-201209601LMA20T_2P 1
1 2 256EMI@ DMIC_DATA34 2 1
DMIC_CLK 2 1 DMIC_CLK34 3 2
+VDDA +5VS
40mil +VDDA 4 3
PN:SM01000EE00 1 1 1 LA7 BLM15PX221SN1D_2P
4
10U_0402_6.3V6M
CA1
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
+5VS_AVDD JPA1 @ 5
RA1 @ 1 2 6 G5
UA1 20mil 0_0603_5% G6
2 2 2 1 2 JUMP_43X39 ACES_50273-0040N-001
CONN@
DA4 256ESD@ GND
1 1 1 1 (output = 300 mA) DMIC_CLK34 1
0.1U_0201_10V6K
CA4
0.1U_0201_10V6K
CA5
10U_0603_6.3V6M
CA6
6 3
+3VS I/O4 I/O2
ALC256-CG MQFN 48P
S IC ALC256-CG MQFN 48P CODEC 2 2 2
256@ SA000080Q00
near Pin41 near Pin46 5 2
VDD GND
GNDA GND
4 1 DMIC_DATA34
CA7 1 2 0.1U_0201_10V6K
near Pin26 +1.8VS I/O3 I/O1
near Pin9 AZC099-04S.R7G_SOT23-6

CA8 1 2 10U_0603_6.3V6M
+3VS +1.8VS_VDDA 1 @ 2
1 @ 2 +3VS_DVDDIO RA3 0_0402_5%
1 1
0.1U_0201_10V6K
CA11
10U_0603_6.3V6M
CA12
RA2 0_0402_5%
+3VS
20mil +3VS_DVDD
2 2
Int. Speaker Conn.
1 @ 2 GNDA
RA4 0_0402_5% 1 1
10U_0603_6.3V6M
CA9
0.1U_0201_10V6K
CA10
40mil JSPK1
SPKR+ EMI@ 1 LA2 2 HCB1608KF-121T30_0603 SPK_R+ 1
SPKR- EMI@ 1 LA3 2 HCB1608KF-121T30_0603 SPK_R- 2 1
2 2 HDA_BIT_CLK_R SPKL+ EMI@ 1 LA4 2 HCB1608KF-121T30_0603 SPK_L+ 3 2
near Pin1 Place near Pin40 SPKL- EMI@ 1 LA5 2 HCB1608KF-121T30_0603 SPK_L- 4 3
5 4
2
41
46
26
40
6 G1
9
10P_0402_50V8J 2 1 CA27 DMIC_CLK UA1 RA5
G2
0_0402_5%
DVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
@RF@ ACES_50278-00401-001
Reserved for RF SP02000RR00
1
@EMI@
LINE1_L 22 43 SPKL- GND CONN@
LINE1_R LINE1-L(PORT-C-L) SPK-OUT-L- 2
21 42 SPKL+
LINE1-R(PORT-C-R) SPK-OUT-L+ CA13
24 45 SPKR+ 22P_0402_50V8J
2 23 LINE2-L(PORT-E-L) SPK-OUT-R+ 44 SPKR- 1 2
+MICBIAS LINE2-R(PORT-E-R) SPK-OUT-R- @EMI@
31
30 LINE1-VREFO-L 32 HP_LEFT
LINE1-VREFO-R HPOUT-L(PORT-I-L) 33 HP_RIGHT
+3VS RING2 17 HPOUT-R(PORT-I-R)
2 1 SENSE_A SLEEVE 18 MIC2-L(PORT-F-L) /RING
40mil MIC2-R(PORT-F-R) /SLEEVE 10 HDA_SYNC_R
RA13 100K_0402_1%
DMIC_DATA 2 SYNC 6 HDA_BIT_CLK_R HDA_SYNC_R <19>
DMIC_CLK 3 GPIO0/DMIC-DATA BCLK 5 HDA_SDOUT_R HDA_BIT_CLK_R <19>
GPIO1/DMIC-CLK SDATA-OUT 8 HDA_SDIN0_AUDIO 1 2 HDA_SDOUT_R <19>
<43> EC_MUTE#
47
PDB
SDATA-IN RA10 33_0402_5%
DMIC_DATA34
HDA_SDIN0 <19>
Digital MIC
48 1 256@ 2 single net
1 255@ 2 RESETB 11 SPDIF-OUT/GPIO2 RA45 0_0402_5%
<19> HDA_RST#_R
RA42 0_0402_5% RESETB 16 1 2 BEEP#_R MIC BOM upload by Audio Team
MONO_IN 12 MONO-OUT 1U_0402_6.3V6K
PCBEEP +MIC2_VREFO 256@ CA28
Close codec
<48> HP_PLUG# RA12 2 1 200K_0402_1% SENSE_A 13 29
14 HP/LINE1 JD(JD1) MIC2-VREFO
RA17 2 @ 1 20K_0402_5% 15 MIC2/LINE2 JD(JD2)
SPDIFO/FRONT JD(JD3)/GPIO3 7 CA14 1 2 10U_0603_6.3V6M
1 LDO3-CAP GND
37 39 CA16 1 2 10U_0603_6.3V6M TO eDP cable
CA15 35 CBP LDO2-CAP 27 CA17 1 2 10U_0402_6.3V6M DMIC_DATA 2 1 DMIC_DATA_R
GNDA CBN LDO1-CAP DMIC_DATA_R <37>
1U_0402_6.3V6K 10mil RA14 1 2 100K_0402_5% RA7 0_0402_5%
2
3V_1.8V_PVDD 36 CODEC_VREF GNDA PCH_DMIC_DATA0 2
28 CA18 @1 2 10U_0402_6.3V6M <19> PCH_DMIC_DATA0 @ 1
CPVDD VREF RA8 33_0402_5%
CA20 1 2 2.2U_0402_6.3V6M
3V_5V_STB 20 PCH_DMIC_CLK0 2 @ 1
+3VS_DVDD VD33 STB <19> PCH_DMIC_CLK0
CA21 @1 2 0.1U_0201_10V6K RA9 33_0402_5%
1 255@ 2 3V_1.8V_PVDD CA19 1 2 19 34 CPVEE
GNDA MIC CAP CPVEE DMIC_CLK DMIC_CLK_R
1U_0402_6.3V6K
CA22
RA36 0_0402_5% 1 2 1
+1.8VS 10U_0603_6.3V6M LA6 EMI@ BLM15PX221SN1D_2P DMIC_CLK_R <37>
GNDA
1 256@ 2
RA37 0_0402_5% RA19 2 @ 1 0_0402_5% 4 25
SM01000Q500
3 49 DC DET AVSS1 38 2 3
+3VALW Thermal PAD AVSS2
1 255@ 2 3V_5V_STB
RA16 0_0402_5% ALC255-CG_MQFN48_6X6
+5VALW
GND SA000082700
1 256@ 2 GNDA
RA35 0_0402_5% 255@
for ALC256 co-lay Headphone Out

+MIC2_VREFO
TO IO/B
RA15 1 2 2.2K_0402_5% SLEEVE SLEEVE <48>
RA18 1 2 2.2K_0402_5% RING2
I2C for Co-lay ALC256 RING2 <48>
RA22 RA25 1 @ 2 0_0402_5% RA26 1 @ 2 0_0402_5% +3VS_DVDD

22K_0402_5% 255@ CA25 HP_LEFT RA20 1 @ 2 0_0603_5% HPOUT_L_1 HPOUT_L_1 <48>
1U_0402_6.3V6K
2 1 BEEP#_R 1 2 MONO_IN RA29 1 @ 2 0_0402_5% RA30 1 @ 2 0_0402_5% HP_RIGHT RA21 1 @ 2 0_0603_5% HPOUT_R_1
<43> BEEP# HPOUT_R_1 <48>
1
1
256@
2
RA27 RA31 1 @ 2 0_0402_5% RA32 1 @ 2 0_0402_5% RA41 256@ LINE1_L CA23 1 2 4.7U_0402_6.3V6M
1
22K_0402_5% @ESD@ 3.3K_0402_5% RA44
LINE1_R
100P_0402_50V8J
CA26
2 1 RA24 3.3K_0402_5% CA24 1 2 4.7U_0402_6.3V6M

2
<19,20> PCH_SPKR 4.7K_0402_5% RA33 1 @ 2 0_0402_5% RA34 1 @ 2 0_0402_5%

2
2 MONO_IN
1
+MICBIAS DA3
GND GNDA GND GNDA 2 2 RA23 1
RESETB 4.7K_0402_5%
4 GND 1 4
3 2 RA28 1
4.7K_0402_5%
BAT54A-7-F_SOT23-3
PN:SCSBAT54100

HD Audio Codec ALC255
A B C D E
A B C D E
Board ID
+3VLP_EC
+3VLP_EC +3VLP_ECA
2
+3VLP LB1
JPB1 FBMA-L11-160808-800LMT_0603 RB1
1 2 1 2 +3VLP_ECA 100K_0402_1%
1 2 Ra
JUMP_43X39
1
AD_BID
0.1U_0201_10V6K
0.1U_0201_10V6K
@ 1 1 1
CB1
CB2
CB3
2
RB3 32P@ 1
+3VLP_EC @ RB2 0.1U_0201_10V6K RB3 28P@ @ CB4
1 For Power consumption 2 2 2 1
0_0402_5% 20K_0402_1% Rb 0.1U_0201_10V6K
Measurement
RB4 1 @ 2 47K_0402_5% EC_PME# ECAGND 2
ECAGND <53>
1
+3VLP_LPC 240K_0402_1%
SD000001B80
Analog Board ID definition,
111
125
22
33
96
67
Please see page 3.
9
UB1
ESPI Bus Pin : 1~5.7.8.10.12.14
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
LPC Bus Pin : 3~5.7.8.10.12.13
For turn off internal LPC module of KB9032 SUSPWRDNACK 1 21 EC_VCCST_PG_R

<19> SUSPWRDNACK GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R <11,51>
2 23 BEEP#
<46> CHG_CTL3 TPM_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <42>
@ESD@
1 2 100P_0402_50V8J PLT_RST# <18,49> TPM_SERIRQ LPC_FRAME# SERIRQ EC_FAN_PWM/GPIO12 FAN_PWM2 FAN_PWM1 <50>
CB5 4 PWM Output 27
<18,49> LPC_FRAME# LPC_AD3 LPC_FRAME# AC_OFF/GPIO13 FAN_PWM2 <50>
5 near SOC
<18,49> LPC_AD3 LPC_AD2 LPC_AD3 PCH_RTCRST# <19>
7
<18,49> LPC_AD2 LPC_AD2
1
CB6 1 2 100P_0402_50V8J AC_IN LPC_AD1 8 63 BATT_TEMP D
<18,49> LPC_AD1 LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 BATT_TEMP <53,54> EC_CLR_CMOS
10 LPC & MISC 64 2 QB6
<18,49> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 ADP_I CHG_CTL1 <46>
65 G L2N7002WT1G_SC-70-3
ADP_I/AD2/GPIO3A ADP_I <53,54>
1
@EMI@ @EMI@ CLK_LPC_R 12 66 AD_BID
AD Input S SB00001GE00
3
2 1 2 1 CLK_LPC_R <18> CLK_LPC_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 WLAN_PME# RB26
<17,19,26,36,49> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_PME# WLAN_PME# <41> @
CB7 RB6 37 76 10K_0402_5%
<50> EC_RST# EC_SCI# EC_RST# AD5/GPIO43 EC_PME# <17,40>
22P_0402_50V8J 33_0402_5% 20
<20> EC_SCI# WLAN_ON EC_SCI#/GPIO0E
38
<41> WLAN_ON
2
CLKRUN#/GPIO1D
68 LAN_PWR_EN
<49> KSI[0..7] DA0/GPIO3C EC_TP_INT# LAN_PWR_EN <40>
DA Output EN_DFAN1/DA1/GPIO3D 70
VR_PWRGD EC_TP_INT# <17,49>
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN
+3VLP_EC KSI1/GPIO31 DA3/GPIO3F KBL_EN <49>
KSI2 57
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
EC_SMB_CK1 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN EC_MUTE# <42> SYS_PWROK_R
RB10 1 2 2.2K_0402_5% KSI4 59 84 1 @ 2 SYS_PWROK <19,51>
2 1 2 2.2K_0402_5% EC_SMB_DA1 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B EC_TYPEC_EN# USB_EN <48> 2
RB11 KSI5 60 85 RB7 0_0402_5%
KSI5/GPIO35 PSCLK2/GPIO4C EC_TYPEC_EN# <44>
KSI6 61 PS2 Interface 86
KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK CHG_EN <46>
KSI7 62 87
<49> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <49>
KSO0 39 88
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <49> +3VS
KSO1 40
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
KSO3/GPIO23 ENKBL/GPXIOA00 TP_PWR_EN ENBKL <18,26> GPU_ALERT
KSO4 43 98 RB9 1 VGA@ 2 10K_0402_5%
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN TP_PWR_EN <49>
KSO5
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <19> GPU_OVERT# RB12 1 @ 2 10K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <53>
KSO8 47 KSO7/GPIO27
SPOK_3V KSO8/GPIO28 SPI Device Interface SPOK_5V
RB72 1 @ 2 0_0402_5% KSO9 48 119
KSO9/GPIO29 MISO/GPIO5B BT_ON SPOK_5V <55>
KSO10 49 120
KSO10/GPIO2A MOSI/GPIO5C EC_CLR_CMOS BT_ON <41> +3VLP_EC
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
SPOK_5V RB73 1 @ 2 0_0402_5% SPOK_3V5V KSO12 51 KSO11/GPIO2B 128 FP_PWR_EN
KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <50> EC Internal PU
KSO13 52
KSO14 53 KSO13/GPIO2D LID_SW# RB13 1 2 100K_0402_1%
KSO15 54 KSO14/GPIO2E 73 GPU_ALERT
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R GPU_ALERT <26>
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89
KSO17/GPIO49 GPIO50 BATT_BLUE_LED# BATT_4S <54>
90
For abnormal shutdown BATT_CHG_LED#/GPIO52 91 CAPS_LED# BATT_BLUE_LED# <48>
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED# CAPS_LED# <49>
77 GPIO 92
SPOK_3V5V EC_RSMRST# <53,54> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <48>
1 2 78 93
<53,54> EC_SMB_DA1 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# <48>
DB2 RB751V-40_SOD323-2 SYSON
<19,26,44,48> PCH_SML1CLK EC_SMB_CLK2/GPIO46 SYSON/GPIO56 VR_ON SYSON <51,56,58>
80 121
<19,26,44,48> PCH_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 VR_ON <51,59,60,61>
PCH_PWROK DPWROK_EC/GPIO59 CHG_ILMSEL <46>
1 2 PU at CPU side SM Bus
DB3 RB751V-40_SOD323-2
PM_SLP_S3# 6 100 EC_RSMRST#
<19,51> PM_SLP_S3# ESPI_RST# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 DGPU_AC_DETECT EC_RSMRST# <19>
EC_VCCST_PG_R <18> ESPI_RST# SPOK_3V GPIO07 GPXIOA04 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <20,26,54>
1 2 15 102
<55,58> SPOK_3V TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <53>
DB4 RB751V-40_SOD323-2
<49> TP_EN TS_EN GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 MAINPWON
<20,37> TS_EN WL_OFF# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 MAINPWON <50,53,55>
3 BKOFF# 3
<41> WL_OFF# AC_PRESENT GPIO0C BKOFF#/GPXIOA08 THERMAL_ALERT# BKOFF# <37>
19 GPIO GPO 106 For Thermal Portect Shutdown
<19> AC_PRESENT GPU_OVERT# 25 AC_PRESENT/GPIO0D GPXIOA09 107 3V_EN_R THERMAL_ALERT# <48>
<26,36> GPU_OVERT# FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 PM_SLP_S0#
28 108 DB1
<50> FAN_SPEED1 FAN_SPEED2 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 PM_SLP_S0# <19>
29 RB751V-40_SOD323-2
<50> FAN_SPEED2 E51TXD_P80DATA FANFB1/GPIO15 3V_EN
30 MAINPWON 1 2
VCOUT1_PROCHOT <41> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 AC_IN 3V_EN <55>
<41> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON AC_IN <54> 1
32 112 RB14
<19,51> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <55>
2
PWR_SUSP_LED# 34 114 ON/OFFBTN# CB8 3V_EN_R 1 2 RB15 1 2

<48> PWR_SUSP_LED# NUM_LED# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFFBTN# <49>
RB19 36 GPI 115 .1U_0402_16V7K 1M_0402_5%
<49> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <48> 2
@ 0_0402_5% 116 SUSP# @ESD@ 1K_0402_5%
SUSP#/GPXIOD05 117 SW_PROCHOT# SUSP# <51,54,56,59>
GPXIOD06 118 EC_PECI 1 2
H_PECI <11,18>
1
PBTN_OUT# 122 PECI/GPXIOD07 RB16 33_0402_1%

DGPU_AC_DETECT SW_PROCHOT# <19> PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D
123 124 PDG 33ohm, checklist 43ohm.
<19,51> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC
AGND
GND
GND
GND
GND
GND
FOLLOW TD
@ QB1A QB1B @ @ RB74
6
2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 KB9022QD_LQFP128_14X14 0_0402_5%

11
24
35
94
113
ECAGND 69
VCOUT1_PROCHOT 2 5 VCOUT1_PROCHOT 1 2 VR2_HOT#

G G
CO-LAY with KB9032QA (SA000080J00) 20mil VR2_HOT# <61>
CB91 2 BATT_TEMP @ RB17
S S 100P_0402_50V8J 0_0402_5%
1
LB2 2 1 1 2 VR_HOT#
VR_HOT# <60>
FBMA-L11-160808-800LMT_0603
@ RB18
0_0402_5%
H_PROCHOT# 1 2 SW_PROCHOT#
<11,54> H_PROCHOT#
2015/1/9 acer require:

reserved protact circuit when
adaptor 107% happen
RB76 1 @ 2 0_0402_5% VR_PWRGD
<60> VCCCORE_VR_PWRGD
4 4
RB77 1 @ 2 0_0402_5%
<61> VCCSA_VR_PWRGD

EC ENE-KB9012A4/KB9022
A B C D E
5 4 3 2 1
+3.3V_CC +3.3V_CC
2
+5VALW US2 +5V_CC RS103
10K_0402_5% RS105
10K_0402_5%
6 1
2
IN OUT CUR_MODE0
1
1
RS116 1 2 100K_0402_5% 5 2 CUR_MODE1
SET GND CS90
2
+3VALW RS117 1 2 1K_0402_5% 4 3 .1U_0402_16V7K
EN(/EN) FLAG 2 RS106
D D
RS104 10K_0402_5%
1 G527ATP1U_TSOT23-6 10K_0402_5% @
@ @
1
CS101
2.2U_0402_6.3V6M
2
Initial Current mode selection

CUR_MODE0 CUR_MODE1 MODE
+3VALW +3.3V_CC
H L Default Current
L H Medium current
RS1 1 @ 2 0_0603_5% H H High current
+5V_CC
US3
1 10
GPIO2(INT#) VCONN RSET
2 9 +3.3V_CC CS91 1 2 2.2U_0402_6.3V6M
CUR_DR VDD33
1
8 +1.8V_CC CS92 1 2 1U_0402_6.3V6K RS113 RS109 RS110
179F_SMB_DA2 3 VDD18 6.2K_0402_5% 8.2K_0402_5% 4.3K_0402_5%
179F_SMB_CK2 4 SI0(SDA)
+USB3_VCCC SI1(SCL) 11 CC1_VCONN <45>
3 2
VBUS_DC 7 CC1 12
CUR_MODE0 VBUS_DC CC2 CC2_VCONN <45>
C 14 D C
CUR_MODE0
1
CUR_MODE1 15 5
CUR_MODE1 TYPEC_3A <19>
RS101 16 G
39K_0402_1% CC_EN 5
CC_SEL 13 VBUS_EN_179 S QS2B
4
TYPC_CONN_DET 2N7002KDW _SOT363-6
2
6
6 17 D
GND EPAD
1
VBUS_DC 2 TYPEC_1P5A <17>
RS118 G
1
EJ179F_QFN16_4X4 10K_0402_5%
RS102 S QS2A
1
3.01K_0402_1% 2N7002KDW _SOT363-6
2
check bios
1050 is use PCH output
2
G518 MOS Current Limit

Scaled input
for detection of VBUS DC levels GPP_B1 GPP_B4 RSET(kΩ ) MODE limit point
(TYPEC_1P5A) (TYPEC_3A)
L L 6.2 0.9A 1.09A
Remove INT#,
platform doesn't monitor it L H 3.53 1.5A 1.92A
CC_SEL H L 2.54 2A 2.67A
report CC1 or CC2 is connection
*H H 1.94 3A 3.5A
CC_EN
B B
power path control "low active" +5VALW
+USB3_VCCC
150U_D2_6.3VM_R17M
1
.1U_0402_16V7K
1
CS95
CS96
0.1U_0402_25V6
22U_0805_25V6M
22U_0805_25V6M
+
1 1 1
CS97 @
CS98 @
CS99 @
+3.3V_CC
2 2
US11 2 2 2
6 1
IN OUT
1
@ RS108 RS107 @
+3.3V_CC +5VALW
4.7K_0402_5% 4.7K_0402_5% RSET 5 2
SET GND
1
2
VBUS_EN_179 4 3 1 @ 2
EN FLAG USB_OC0# <15>
RS111 @ Initial Current mode selection
5
G518B1TP1U_TSOT23-6 RS112
G
100K_0402_5% 1
QS1B @ 0_0402_5% VBUS_EN_179 EC_TYPEC_EN# V BUS
2
2N7002KDW _SOT363-6 D footprint : G518 CS100

PU on SOC side 5 0.1U_0201_10V6K L H 0
4 3 179F_SMB_CK2 <43> EC_TYPEC_EN# G PN : SA0000BDN00(SILERGY SY6861B1) 2
S
<19,26,43,48> PCH_SML1CLK
D
EC need change to low act i ve QS3B @ L L 0

S 2N7002KDW _SOT363-6
4
6
1 @ 2 D H H 0
RS114 0_0402_5% 2 QS3A @
A A
G H L
2N7002KDW _SOT363-6 1
2
S
G
QS1A @
2N7002KDW _SOT363-6
1 6 179F_SMB_DA2 Security Classification Compal Secret Data Compal Electronics, Inc.

S
<19,26,43,48> PCH_SML1DATA
D
1 @ 2
CC+USB TYPE C
RS115 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
D
USB3.0 (Port 2) D
RS64 1 @ 2 0_0201_5% USB3_PTX_L_DRX_P2 CS58 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_P2

<18> USB3_PTX_DRX_P2 For ESD request
RS65 1 @ 2 0_0201_5% USB3_PTX_L_DRX_N2 CS59 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_N2 DS3 ESD@ DS6 ESD@
<18> USB3_PTX_DRX_N2 USB3_PTX_L_DRX_P2 USB3_PTX_L_DRX_P2 USB20_P2_L USB20_P2_L
1 9 1 9
RS74 1 @ 2 0_0201_5% USB3_PRX_L_DTX_P2
<18> USB3_PRX_DTX_P2 USB3_PTX_L_DRX_N2 USB3_PTX_L_DRX_N2 USB20_N2_L USB20_N2_L
2 8 2 8
RS76 1 @ 2 0_0201_5% USB3_PRX_L_DTX_N2
<18> USB3_PRX_DTX_N2 CC1_VCONN CC1_VCONN USB3_PRX_L_DTX_N3 4 USB3_PRX_L_DTX_N3
4 7 7
TBTA_SBU1 5 6 TBTA_SBU1 USB3_PRX_L_DTX_P3 5 6 USB3_PRX_L_DTX_P3
USB3.0 (Port 3)
RS82 1 @ 2 0_0201_5% USB3_PTX_L_DRX_P3 CS60 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_P3 3 3
<18> USB3_PTX_DRX_P3
RS83 1 @ 2 0_0201_5% USB3_PTX_L_DRX_N3 CS61 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_N3 TVW DF1004AD0_DFN9 TVW DF1004AD0_DFN9
<18> USB3_PTX_DRX_N3
RS84 1 @ 2 0_0201_5% USB3_PRX_L_DTX_P3 SC300003Z00 SC300003Z00
<18> USB3_PRX_DTX_P3
RS85 1 @ 2 0_0201_5% USB3_PRX_L_DTX_N3 DS4 ESD@ DS5 ESD@
<18> USB3_PRX_DTX_N3 CC2_VCONN CC2_VCONN
1 9 1 9
2 8 TBTA_SBU2 2 8 TBTA_SBU2
Change to 0201 for placement. Follow intel #575549. USB3_PTX_L_DRX_N3 4 USB3_PTX_L_DRX_N3 USB3_PRX_L_DTX_N2 4 USB3_PRX_L_DTX_N2
7 7
USB3_PTX_L_DRX_P3 5 6 USB3_PTX_L_DRX_P3 USB3_PRX_L_DTX_P2 5 6 USB3_PRX_L_DTX_P2
C C
LS10 EMI@ 3 3
USB20_P2 2 1 USB20_P2_L
<15> USB20_P2 2 1 TVW DF1004AD0_DFN9 TVW DF1004AD0_DFN9
USB20_N2 3 4 USB20_N2_L SC300003Z00 SC300003Z00
<15> USB20_N2 3 4
DLM0NSN900HY2D_4P
SM070005U00
+USB3_VCCC +USB3_VCCC
USB3_PRX_L_DTX_P2 CS102 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_P2 JTYPEC1

A1 B12
USB3_PRX_L_DTX_N2 CS103 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_N2 GND GND
USB3_PTX_C_DRX_P2 A2 B11 USB3_PRX_C_DTX_P2
USB3_PTX_C_DRX_N2 A3 SSTXP1 SSRXP1 B10 USB3_PRX_C_DTX_N2
SSTXN1 SSRXN1
1
0.1U_0402_25V6 2 1 CS84
B RS119 RS120 A4 B9 CS87 1 2 0.1U_0402_25V6 B
220K_0402_5% VBUS VBUS
220K_0402_5%
A5 B8 TBTA_SBU2
<44> CC1_VCONN CC1 SBU2
1
CS13
2
10U_0805_25V6K USB20_P2_L A6 B7 USB20_N2_L

USB20_N2_L A7 DP1 DN2 B6 USB20_P2_L
2
DN1 DP2
3
TBTA_SBU1 A8 B5
SBU1 CC2 CC2_VCONN <44>
0.1U_0402_25V6
DS19 ESD@ 2 1 CS86 A9 B4 CS85 1 2 0.1U_0402_25V6
MESC5V02BD03_SOT23-3 VBUS VBUS
USB3_PRX_C_DTX_N3 A10 B3 USB3_PTX_C_DRX_N3
USB3_PRX_L_DTX_P3 CS104 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_P3 USB3_PRX_C_DTX_P3 A11 SSRXN2 SSTXN2 B2 USB3_PTX_C_DRX_P3
SSRXP2 SSTXP2
USB3_PRX_L_DTX_N3 CS105 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_N3 A12 B1
GND GND
1
1
1 5
RS121 RS122 2 GND GND 6
220K_0402_5% 3 GND GND 7
220K_0402_5% GND GND
4 8
GND GND
2
LOTES_AUSB0249-P001A
CONN@
Follow intel #575549 for ESD/EOS protection.

A CC1_VCONN & CC2_VCONN need 20miil trace width. A
2017/07/20
Compal Secret Data
2018/07/20 Title
CC+USB TYPE C
5 4 3 2 1
A B C D E
For ESD request

DS1
USB3.0 USB3_PTX_L_DRX_P1
USB3_PTX_L_DRX_N1 2
1
ESD@
9
8
USB3_PTX_L_DRX_P1
USB3_PTX_L_DRX_N1
1 2 USB3_PTX_C_DRX_P1 RS86 1 @ 2 0_0402_5% USB3_PTX_L_DRX_P1
<18> USB3_PTX_DRX_P1 USB3_PRX_L_DTX_P1 USB3_PRX_L_DTX_P1
CS2 .1U_0402_16V7K 4 7
1 2 USB3_PTX_C_DRX_N1 RS89 1 @ 2 0_0402_5% USB3_PTX_L_DRX_N1 USB3_PRX_L_DTX_N1 5 6 USB3_PRX_L_DTX_N1

<18> USB3_PTX_DRX_N1
CS3 .1U_0402_16V7K
1 3 1
TVWDF1004AD0_DFN9
SC300003Z00
USB3_PRX_DTX_P1 RS90 1 @ 2 0_0402_5% USB3_PRX_L_DTX_P1
<18> USB3_PRX_DTX_P1
LS1 EMI@
USB3_PRX_DTX_N1 RS91 1 @ 2 0_0402_5% USB3_PRX_L_DTX_N1 U2DP1 3 4 U2DP1_L
<18> USB3_PRX_DTX_N1 3 4
U2DN1 2 1 U2DN1_L
2 1
DLM0NSN900HY2D_4P
SM070005U00
DS2 ESD@
6 3 U2DP1_L
I/O4 I/O2
+USB3_VCCA
5 2
VDD GND
U2DN1_L 4 1
0904 vendor recommend I/O3 I/O1
+5VALW AZC099-04S.R7G_SOT23-6
2 2
RS8 1 @ 2 0_1206_5%
22U_0603_6.3V6M
.1U_0402_16V7K
1 1
CS9
CS7
+USB3_VCCA
2@ 2 US12
+5VALW_CHG 1 12 +USB3VCCA_CHG RS10 1 @ 2 0_1206_5%
VIN VOUT
2
<15> USB20_N1 3 DM_OUT
RS11
<15> USB20_P1 DP_OUT 10 U2DP1
0_0402_5%
2 @ 1 13 DP_IN 11 U2DN1
<15> USB_OC1# FAULT# DM_IN
1 4
<43> CHG_ILMSEL ILIM_SEL
CS8 5 15
0.1U_0201_10V6K
<43> CHG_EN EN ILIM_L 16 0831 Reserve ILIM_L R as vendor recommend
@ 2 ILIM_HI
1
6
<43> CHG_CTL1 CHG_CTL2 CTL1
22.1K_0402_1%
39K_0402_1%
7 9
CTL2 NC
RS12
RS13
8 14
<43> CHG_CTL3 CTL3 GND 17
Thermal Pad @
2
+5VALW SLGC55544CVTR_TQFN16_3X3
+USB3_VCCA
RS14 1 2 10K_0402_5% CHG_CTL2

W=100mils
3 3
@
ILM R vaule 1 2
EMI@
RS15 1 2 10K_0402_5% CHG_ILMSEL Ios(mA)=50250/R(Kohm) CS5 + CS6
150U_D2_6.3VM_R17M .1U_0402_16V7K
ILIM_Hi=2273mA SGA00009000 1
2
ILIM_L=1288mA(reserve)
USB3.0 Conn.
JUSB1
0831 Rerserve PU, check if SDP1 mode is need, 1
VBUS
just PU if no need U2DN1_L
U2DP1_L
2
D-
3
4 D+
USB3_PRX_L_DTX_N1 5 GND
USB Host Charger USB3_PRX_L_DTX_P1
USB3_PTX_L_DRX_N1
6
7
8
SSRX-
SSRX+
GND
GND
GND
10
11
12
CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note USB3_PTX_L_DRX_P1 SSTX- GND
Setting 9 13
SSTX+ GND
1 1 0 1 SDP1 ILIM_H Data Lines Connected ACON_TARB5-9V1391
CONN@
1 1 1 0 SDP2 ILIM_L Data Lines Connected DC23300NH00
1 1 1 1 CDP ILIM_H Data Lines Connected
0 1 1 1 DCP ILIM_H Data Lines Disconnected
Aut o
4 4

USB3.0 Conn/USB Charger
A B C D E
A B C D E
SATA Re-Driver and cable HDD Conn. +5VS
+3VS +5VS_HDD
1 2 +5VS_HDD
RO4 0_0805_5% 100mils
UO2 @
SATA_PRX_DTX_P4_R
10U_0603_6.3V6M
CO12
1 SATARD@
2 5 1 1 1
<18> SATA_PRX_DTX_P4 IN OUT
1
RO21 1 SATARD@
20_0201_5% SATA_PRX_DTX_N4_R
<18> SATA_PRX_DTX_N4 2
RO22 0_0201_5% CO11 CO13
1 SATARD@
2 SATA_PTX_DRX_N4_R GND 0.1U_0201_10V6K 0.1U_0201_10V6K
<18> SATA_PTX_DRX_N4
2
RO23 1 SATARD@
20_0201_5% SATA_PTX_DRX_P4_R 4 3 2 @ 2 @
1 <18> SATA_PTX_DRX_P4 <17> HDD_PWRGT EN OC 1
RO24 0_0201_5%
reserve for Optane Memory
B_EQ1
A_EQ2
A_EQ1
DEW
+3VS JHDD3
CO1 14
2 1 13 GND
SATARD@ GND
0.01U_0402_16V7K UO1 +5VS_HDD 12
20
19
18
17
16
SATARD@ PS8527CTQFN20GTR2A_TQFN20_4X4 11 12
10 11
DEW
VDD2
B_EQ1
A_EQ2
A_EQ1
G_INT2_R 9 10
8 9
SATA_PTX_DRX_P4_RSATARD@ CO4 2 1 SATA_PTX_C_DRX_P4 0.01U_0402_16V7K 1 15 RDSATA_PTX_DRX_P4 7 8
SATA_PTX_DRX_N4_RSATARD@ CO5 2 1 SATA_PTX_C_DRX_N4 0.01U_0402_16V7K 2 A_INP A_OUTP 14 RDSATA_PTX_DRX_N4 SATA_PRX_DTX_P4 NORD@ CO14 2 1 0.01U_0201_6.3V7K SATA_PRX_DTX_P4_C 6 7
3 A_INN A_OUTN 13 B_EQ2 SATA_PRX_DTX_N4 NORD@ CO15 2 1 0.01U_0201_6.3V7K SATA_PRX_DTX_N4_C 5 6
SATA_PRX_DTX_N4_RSATARD@ CO8 2 1 SATA_PRX_C_DTX_N4 0.01U_0402_16V7K 4 GND1 B_EQ2 12 RDSATA_PRX_DTX_N4 4 5
SATA_PRX_DTX_P4_RSATARD@ CO9 2 1 SATA_PRX_C_DTX_P4 0.01U_0402_16V7K 5 B_OUTN B_INN 11 RDSATA_PRX_DTX_P4 SATA_PTX_DRX_N4 NORD@ CO16 2 1 0.01U_0201_6.3V7K SATA_PTX_DRX_N4_C 3 4
21 B_OUTP B_INP SATA_PTX_DRX_P4 NORD@ CO17 2 1 0.01U_0201_6.3V7K SATA_PTX_DRX_P4_C 2 3
GND2 2
VDD1
REXT
1
B_DE
A_DE
1
EN
ACES_51625-01201-001
CONN@
6
7
8
9
10
+3VS
SP010028W00
SATARD@
RO6 1 @ 2 4.7K_0402_5% A_DE RO7 2 1
+3VS +3VS
0.1U_0201_10V6K
SATARD@ CO10
4.99K_0402_1%
B_DE
A_DE
B_DE 1
RO8 1 @ 2 4.7K_0402_5%
2 1 RO9 @ 2 2
RO10 1 @ 2 4.7K_0402_5% B_EQ1 4.7K_0402_5%
2
RO11 1 @ 2 4.7K_0402_5% A_EQ1
A_EQ2
Cable Type
RO12 1 SATARD@
2 4.7K_0402_5%
JHDD2
RO13 1 @ 2 4.7K_0402_5% B_EQ2 1
USE 8527 re-driver 1
2
RO14 1 @ 2 4.7K_0402_5% DEW SA00007JU10 FFC Type +3VS 3
4
2
3
JHDD1
14 5 4
13 GND 6 5
GND 7 6
RO15 1 @ 2 4.7K_0402_5% A_DE +5VS_HDD 12 8 7
11 12 +5VS_HDD 9 8
RO16 1 @ 2 4.7K_0402_5% B_DE 10 11 10 9
G_INT2_R 9 10 11 10
RO17 1 @ 2 4.7K_0402_5% B_EQ1 JHDD_P8 8 9 G_INT2 1 @ 2 G_INT2_R 12 11
7 8 RO5 0_0402_5% JHDD_P8 13 12
RO18 1 @ 2 4.7K_0402_5% A_EQ1 RDSATA_PRX_C_DTX_P4 6 7 14 13
RDSATA_PRX_C_DTX_N4 5 6 RDSATA_PRX_DTX_P4 SATARD@ CO7 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P4 15 14
RO19 1 @ 2 4.7K_0402_5% A_EQ2 4 5 RDSATA_PRX_DTX_N4 SATARD@ CO6 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N4 16 15
RDSATA_PTX_C_DRX_N4 3 4 17 16
RO20 1 SATARD@
2 4.7K_0402_5% B_EQ2 RDSATA_PTX_C_DRX_P4 2 3 RDSATA_PTX_DRX_N4 SATARD@ CO3 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N4 18 17
1 2 RDSATA_PTX_DRX_P4 SATARD@ CO2 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P4 19 18
1 20 19
ACES_51625-01201-001 21 20
CONN@ 22 G1
23 G2
SP010028W00 24 G3
G4
3 ACES_50406-02071-001 3
CONN@
SP010016L00
+3VS
G-Sensor
1
RZ1
10K_0402_5% +3VS
GSEN@
UZ1 GSEN@
2
1 CZ1 1 2 10U_0603_6.3V6M
8 Vdd_IO
4 CS 14 1 2 GSEN@
<19,23,24> D_CK_SCLK 6 SCLSPC Vdd CZ2 0.1U_0201_10V6K
<19,23,24> D_CK_SDATA 1 2 10K_0402_5% 7 SDA/SDI/SDO
+3VS RZ2 @
RZ3 1 GSEN@ 2 10K_0402_5% SDO/SA0 11 G_INT
16 INT1 9 G_INT2 G_INT <20>
15 ADC1 INT2
13 ADC2 10 INT1/2 all High Active
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
GSEN@
4 LIS3DH 4
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

HDD/ Re-Driver/ G-sensor
A B C D E
A B C D E
To USB/B FPC BTB CONN JIO3

JIO2 HPOUT_L_1
<42> HPOUT_L_1 1
HPOUT_L_1 1 HPOUT_R_1 2 1
HPOUT_R_1 1 <42> HPOUT_R_1 2
2 <42> SLEEVE SLEEVE 3
LS11 EMI@
SLEEVE
RING2
HP_PLUG#
3
4
5
2
3
4
<42>
<42>
RING2
HP_PLUG#
RING2
HP_PLUG#
4
5
6
3
4
5
To Hall sensor/B
USB20_P3_L 5 GNDA SUB_PIN7 6
3 4 GNDA 6 7
<15> USB20_P3 3 4 SUB_PIN7 6 7 +3VLP
7 8
8 7 USB20_P3_L 9 8
2 1 USB20_N3_L USB20_P3_L 9 8 USB20_N3_L 10 9 JHS1
1 <15> USB20_N3 1
2 1 USB20_N3_L 10 9 11 10 1
DLM0NSN900HY2D_4P 11 10 USB20_P4_L 12 11 LID_SW # 2 1
USB20_P4_L 11 USB20_N4_L 12 <43> LID_SW# 2
SM070005U00 12 13 3
USB20_N4_L 13 12 14 13 4 3
14 13 BATT_AMB_LED# 15 14 4
BATT_AMB_LED# 14 <43> BATT_AMB_LED# BATT_BLUE_LED# 15
15 <43> BATT_BLUE_LED# 16 5
BATT_BLUE_LED# 16 15 PWR_SUSP_LED# 17 16 6 GND
PWR_SUSP_LED# 16 <43> PW R_SUSP_LED# PW R_LED# 17 GND
17 <43> PW R_LED# 18
PW R_LED# 18 17 19 18 ACES_51524-0040N-001
LS12 EMI@ 19 18 20 19 CONN@
USB20_P4_L USB_EN 19 <43> USB_EN 20
3 4 20 +5VALW 21 SP010022M00
<15> USB20_P4 3 4 20 21
+5VALW 21 22
22 21 23 22
2 1 USB20_N4_L 23 22 24 23
<15> USB20_N4 2 1 23 24
24 25
DLM0NSN900HY2D_4P 25 24 26 25
26 25 27 26
SM070005U00 27 26 28 27
28 GND 29 28
GND <18> USB3_PRX_DTX_N4 29
<18> USB3_PRX_DTX_P4 30
ACES_51522-02601-001 31 30
CONN@ 32 31
<18> USB3_PTX_DRX_N4 32
SP01001AO00 <18> USB3_PTX_DRX_P4 33
34 33
35 34
<18> USB3_PRX_DTX_N5 35
<18> USB3_PRX_DTX_P5 36 41
37 36 G1 42
38 37 G2 43
<18> USB3_PTX_DRX_N5 38 G3
2
<18> USB3_PTX_DRX_P5 39 44 2
40 39 G4 45
For USB3.0 DB. 40 G5
Pop R227, de-pop R228. ACES_50398-04041-001
R227 1 @ 2 0_0402_5% SUB_PIN7 CONN@
+3VALW
SP010013I00
R228 1 2 0_0402_5%
3 +3VS +3VS THERMAL SENSOR 3
+3VS
Thermal sensor SMBus address
1
1
2.2K_0402_5%
RF9
2.2K_0402_5%
RF10 TMS@
-->100-1_100xb : 0x4C
(x=0)Write Address(0x98h)
0.1U_0201_10V6K
1
+3VS
TMS@
CF4
(x=1)Read Address(0x99h)
TMS@
2
2
5
G
1
TMS@ QF1B 2
2N7002KDW _SOT363-6 UF1 SA000067P00 RF8 TMS@
1 8 TMS_SMB_CLK 10K_0402_5%
3 4 TMS_SMB_CLK VDD SCLK
<19,26,43,44> PCH_SML1CLK
S
H_THERMDA 2 7 TMS_SMB_DATA
D
2
D+ SDATA
2
G
TMS@ QF1A 1 2 TMS@ H_THERMDC 3 6 THERMAL_ALERT#

2N7002KDW _SOT363-6 CF11 2200P_0402_50V7K D- ALERT# THERMAL_ALERT# <43>
+3VS 1 2 CPU_THERM# 4 5
6 1 TMS_SMB_DATA RF7 TMS@ 10K_0402_5% THERM# GND
<19,26,43,44> PCH_SML1DATA
S
D
NCT7718W _MSOP8
TMS@
4 4

FUN/B & LED/B
A B C D E
A B C D E
KSI[0..7]
KSI[0..7] <43>
ON/OFF BTN KB Conn. KSO[0..17]

KSO[0..17] <43>
<43> CAPS_LED#
+5VS
RK1
RK3
1
1 @
2
2
1K_0402_5%
0_0402_5%
1
2
JKB1
1
30
29 GND2
JKB2
KB
<43> NUM_LED#
RK4
RK2
1
1
@ 2
2
0_0402_5%
1K_0402_5%
3
4
5
2
3
4
5
28
ON/OFFBTN# 27
KSO0 26
GND1
28
27
26
BackLight
R17 PVT modify ON/OFFBTN# 6 KSO1 25
+3VLP 100K_0402_5% KSO0 7 6 KSO2 24 25
2 1 KSO1 8 7 KSO3 23 24
KSO2 9 8 KSO4 22 23
KSO3 10 9 KSO5 21 22 +5VS JBL1
1 10 21 1
<43> ON/OFFBTN# ON/OFFBTN# KSO4 11 KSO6 20 U4 1
KSO5 12 11 KSO7 19 20 5 1 +5VS_BL 2 1
KSO6 13 12 KSO8 18 19 IN OUT 3 2
KSO7 14 13 KSO9 17 18 2 4 3
SW1 @ KSO8 15 14 KSO10 16 17 GND 4
EVQPLDA15_4P KSO9 16 15 KSO11 15 16 1 @ 2 4 3 5
Test Only 1 3 KSO10 17 16 KSO12 14 15 <43> KBL_EN EN OC 6 GND
R18 0_0402_5% 1
KSO11 18 17 KSO13 13 14 SY6288C20AAC_SOT23-5 GND
BOT 2 4 KSO12 19 18 KSO14 12 13 C32 @ ACES_51524-0040N-001
KSO13 20 19 KSO15 11 12 0.1U_0201_10V6K CONN@
KSO14 21 20 KSO16 10 11 2
SP010022M00
6
5
KSO15 22 21 KSO17 9 10
KSO16 23 22 KSI0 8 9
KSO17 24 23 KSI1 7 8
KSI0 25 24 KSI2 6 7
KSI1 26 25 KSI3 5 6
KSI2 27 26 33 KSI4 4 5
KSI3 28 27 GND 34 KSI5 3 4
KSI4 29 28 GND KSI6 2 3
KSI5 30 29 KSI7 1 2
KSI6 31 30 1
KSI7 32 31
32 ACES_85201-2805
CONN@
ACES_50596-03201-P01
CONN@ SP01000GO00
TPM Touch Pad +3V_PTP

2 2
+3V_PTP +3VALW 2 @ 1
+3VALW
0_0402_5% RK5
+3VS
2 @ 1
0_0402_5% RK6
UK1
+3VALW +3VALW_TPM +3VS +3VS_TPM +3V_PTP
4.7U_0402_6.3V6M
R19 R20 1 5 @ CK1
0_0603_5% 0_0603_5% OUT IN 0.1U_0201_10V6K JTP1
1
CK2
1 @ 2 1 @ 2 2 2 2 1 1
GND 1
2
TP_CLK 2
TP_DATA 2
10U_0603_6.3V6M
0.1U_0201_10V6K
10U_0603_6.3V6M
0.1U_0201_10V6K
C36
0.1U_0201_10V6K
C37
0.1U_0201_10V6K
C38
3 4 CK3 3
1 1 1 1 1 1 2 OC EN EC PS2 3
C33
C34
C35
1U_0402_6.3V6K RK7 4
SY6288C20AAC_SOT23-5 1 10K_0402_5% I2C_1_SDA_R 5 4
I2C_1_SCL_R 6 5
near PCH I2C
1
2 TPM@ 2 TPM@ 2 TPM@ 2 2
TPM@ 2
TPM@ TPM@ EC_TP_INT# EC_TP_INT# 7 6
pin1 <17,43> EC_TP_INT# TP_EN 8 7
<43> TP_PWR_EN <43> TP_EN 8
9
10 GND
GND
TP_PWR_EN follow SYSON behavior
near ACES_51524-00801-001
CONN@
pin8,14,22
SP01001A910
BADD SELECTION +3V_PTP +3V_PTP
* 1 AEh(write),
AFh(read)
1
+3V_PTP
1
2
RK8 RK9
G
QK1A 2.2K_0402_5% 2.2K_0402_5%
1
U5 TPM@ +3VALW_TPM 2N7002KDW_SOT363-6
2
1 RK10 RK11
2
29 VSB +3VS_TPM 6 1 I2C_1_SCL_R 4.7K_0402_5% 4.7K_0402_5%
S
3 30 XOR_OUT/SDA/GPIO0 8 <20> I2C_1_SCL
D
3
3 SCL/GPIO1 VDD1 14 1 @ 2
2
0_0402_5% 1 @ 2 R21 TPM_BADD 6 GPX/GPIO2 VDD2 22 RK12 0_0402_5%
GPIO3/BADD VDD3
5
G
LPC_AD0 24 2 QK1B TP_CLK
<18,43> LPC_AD0 LPC_AD1 LAD0/MISO NC1 TP_DATA TP_CLK <43>
21 7 2N7002KDW_SOT363-6
<18,43> LPC_AD1 LPC_AD2 18 LAD1/MOSI NC2 10 TP_DATA <43>
<18,43> LPC_AD2 LPC_AD3 15 LAD2/SPI_IRQ# NC3 11 I2C_1_SDA_R
<20> I2C_1_SDA 3 4
S
<18,43> LPC_AD3 LAD3 NC4 25
D
CLK_LPC_TPM_R 19 NC5 26 1 2
<18> CLK_LPC_TPM_R LPC_FRAME# LCLK/SCLK NC6 @ 0_0402_5%
20 31 RK13
<18,43> LPC_FRAME# PLT_RST# 17 LFRAME#/SCS# NC7
<17,19,26,36,43> PLT_RST# TPM_SERIRQ LRESET#/SPI_RST#/SRESET#
27 9
<18,43> TPM_SERIRQ PM_CLKRUN# 13 SERIRQ GND1 16
<19> PM_CLKRUN# CLKRUN#/GPIO4/SINT# GND2
28 23
LPCPD# GND3 32
4 GND4 33
5 PP PGND 12
TEST Reserved
NPCT650LA0YX_QFN32_5X5
SERIRQ PH 10K to +3VS at PCH side P/N:SA00008ELC0 (S IC NPCT650ABBYX QFN 32P TPM2.0 FW 1.3.1.0)
CLKRUN# PH 10K to +3VS at PCH side
LPCPD# had internal PH @EMI@ @EMI@
CLK_LPC_TPM_R R22 1 2 33_0402_5% C39 1 2 22P_0402_50V8J
4 4

KB & TP & TPM Connector
A B C D E
+5VS
1 @ 2 +VCC_FAN1
40mil +5VS
1 @ 2
40mil
+VCC_FAN2
Screw
RF4 0_0603_5%
1 1
RF6 0_0603_5%
1 1
Hole
CF5 CF6 CF8 CF9
4.7U_0603_10V6K 1000P_0402_50V7K 4.7U_0603_10V6K 1000P_0402_50V7K
@EMI@ @EMI@ @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14
2 2 2 2 H_6P4 H_4P0 H_3P8 H_3P8 H_3P8 H_4P0 H_3P8 H_3P8 H_3P8 H_4P0 H_2P0N H_3P0 H_3P0 H_3P0
FD1 FD2
1
@ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ H15 @ H17 @ H18 @ H20 @ H21 @ H22 @ H23 @ H24
H_3P8 H_3P0 H_2P5 H_2P7x2P0N H_6P0 H_2P7x2P0N H_3P2 H_3P2 FD3 FD4
+3VS @ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
RF3
10K_0402_5%
FAN Conn
JFAN1
2
+VCC_FAN1 1
2 1
<43> FAN_SPEED1 FAN_PWM1 3 2
<43> FAN_PWM1 4 3
1
CF7 5 4
1000P_0402_50V7K 6 G1
@EMI@ G2
2 ACES_50278-00401-001
CONN@
SP02000RR00
+3VS
1
RF5 Finger Print

10K_0402_5%
JFAN2 +3VALW FP@

2
+VCC_FAN2 1 RK14 1 2 0_0402_5%

2 1
<43> FAN_SPEED2 FAN_PWM2 2 +5VALW
3
<43> FAN_PWM2 3
1 4 RK15 1 @ 2 0_0402_5%
CF10 5 4
1000P_0402_50V7K 6 G1 +FP_VCC
G2 2
@EMI@ FP@
2 ACES_50278-00401-001 CK4 UK2
CONN@ 1U_0402_6.3V6K 5 1
1 IN OUT
SP02000RR00 2
1
FP@
GND CK5
FP_PWR_EN 4 3 4.7U_0402_6.3V6M
<43> FP_PWR_EN EN OC 2
FP@
DK1 FPESD@
6 3 USB20_N8_L
I/O4 I/O2
+3VLP 1 @ 2 RK16 1 @ 2 0_0402_5% USB20_N8_L

MAINPWON <43,53,55> <15> USB20_N8
R23 0_0402_5% 5 2
Reset Circuit USB20_P8_L
+FP_VCC VDD GND
1 @ 2 <15> USB20_P8 RK17 1 @ 2 0_0402_5%
EC_RST# <43>
2
R24 0_0402_5%
R25 USB20_P8_L 4 1
I/O3 I/O1
10K_0402_5%
AZC099-04S.R7G_SOT23-6
1
Q1A D
BI_GATE# 2
BI_GATE PH to +RTCVCC at PWR G
2N7002KDW_SOT363-6
side S +FP_VCC
1
1
JFP1
PIN ETU801 FA577E-1200
3
Q1B D C40 8
BI_GATE 5 0.1U_0201_10V6K USB20_P8_L 7 8 10
<53> BI_GATE G 2 USB20_N8_L 6 7 G2 9 1 +FP_VCC(5V) +FP_VCC(3V)
5 6 G1
2N7002KDW_SOT363-6 USBP D+
S 4 5 2
4
3 4
2 3 3 USBN D-
1 2
1 4 GND GND
ACES_51522-00801-001
CONN@ 5 NC NC
6 NC NC
BI SW SP01001AE00
@ 7 NC
Reset Button
3 SW2 1
8 NC
SW3
BI_GATE 1 2 BI_GATE
BI_S <53>
4 2
3 4 ATE-2-V-TR_4P
H : 3.8mm
SKRPABE010_4P
Release : Battery Off
Push : Battery ON
SN10000CV00

FAN & FP & Screw Hole
A B C D E
System DC inferface For Power ON/Off Sequence

@
CQ2 1 2 0.1U_0201_10V6K UQ1 @ JPQ1 PM_SLP_S3
1 14 +3VS_OUT 1 2 +3VALW
+3VALW VIN1 VOUT1 1 2 +3VS
2
2 13
G
VIN1 VOUT1
1
JUMP_43X118 Q10A
SUSP# RQ1 1 2 0_0402_5% 3VS_ON 3 12 1 2 R37 2N7002KDW_SOT363-6
ON1 CT1 CQ1 1000P_0402_50V7K 100K_0402_5%
4 11 1 6
S
+5VALW VBIAS GND EC_VCCST_PG_R <11,43>
D
2
1 5VS_ON 1
RQ2 2 @ 1 0_0402_5% 5 10 1 2 MOW14, For tCPU28 200us(max)
ON2 CT2 CQ3 1000P_0402_50V7K SLP_S3# to VCCST_PWRGD deassertion
5
@ 6 9 @ JPQ2
G
+5VALW VIN2 VOUT2 +5VS_OUT 1
CQ4 1 2 0.1U_0201_10V6K 7 8 2
VIN2 VOUT2 1 2 +5VS
Q10B
15 JUMP_43X118 Q11A 2N7002KDW_SOT363-6
GPAD 2N7002KDW_SOT363-6 4 3
S
VR_ON <43,59,60,61>
D
EM5209VF_DFN14_2X3 D
+3VALW +5VALW +3VS_OUT +5VS_OUT 2 MOW14, For tPLT17 200us(max)
<19,43> PM_SLP_S3# G SLP_S3# to IMVP VR_ON deassertion
5
G
2 2 2 2
S
1
CQ7 CQ8 CQ5 CQ6 Q11B
1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 2N7002KDW_SOT363-6
1 1 1 1 4 3 SUSP#
D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable
2
Place CQ7 close UQ1 pin 1&2
G
Q12A @
Place CQ8 close UQ1 pin 6&7 2N7002KDW_SOT363-6
1 6
S
SYS_PWROK <19,43>
D
5
G
+3VALW Q12B @
+5VALW +0.6VS_VTT +5VALW +1.2V_VDDQ 2N7002KDW_SOT363-6
1
4 3
S
PCH_PWROK <19,43>
2
D
R38
2
@ R27 @ R28 R30 R29 100K_0402_5%
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @
2
2
Q13A PM_SLP_S4 2
1
1
2N7002KDW_SOT363-6
5
SUSP +0.6VS_VTT_R SYSON# +1.2V_VDDQ_R D
G
2 Q13B
<19,43> PM_SLP_S4# G 2N7002KDW_SOT363-6
S 4 3 SYSON
S
1
D
@ Q7A Q7B @ @ Q8B Q8A @ MOW14, For tPLT15 200us(max)
6
6
2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 SLP_S4# to VDDQ ramp down
2 5SUSP SYSON 5 2 SYSON#
<43,54,56,59> SUSP# G G <43,56,58> SYSON G G
1
R32 S S S S
1
1
10K_0402_5%
@
2
+1.05VALW TO +1.05V_VCCST /+1.8VALW TO +1.8VS +1.05VALW TO +1.05VS_VCCSTG

+1.05VALW
@ +1.05V_VCCST
2
CQ15 1 2 0.1U_0201_10V6K UQ2
3 1 14 +1.05V_VCCST_OUT RQ5 1 @ 2 0_0603_5% CQ12 3
+1.05VALW VIN1 VOUT1
2 13 1U_0402_6.3V6K
VIN1 VOUT1 1 UC4
SYSON RQ4 1 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 1
ON1 CT1 CQ14 1000P_0402_50V7K +5VALW 2 VIN1 +1.05VS_VCCSTG
4 11 VIN2
+5VALW VBIAS GND +1.05VS_VCCSTG_OUT
7 6 RQ6 1 @ 2 0_0603_5%
SUSP# RQ8 1 2 0_0402_5% EN_1.8VS 5 10 1 2 +1.8VS VIN thermal VOUT
ON2 CT2 CQ16 1000P_0402_50V7K 3
+1.8VS_OUT VBIAS 2
+1.8VALW
6 9 RQ9 1 @ 2 0_0603_5%
@ 7 VIN2 VOUT2 8 SUSP# RQ3 2 1 0_0402_5% EN_1.0V_VCCSTG 4 5 CQ10
CQ20 1 2 0.1U_0201_10V6K VIN2 VOUT2 ON GND
0.1U_0201_10V6K
15 1
GPAD 1
@
EM5209VF_DFN14_2X3 CQ13 AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K
2
+1.0VS_VCCSTG: 60mA
R ON = 4.4m ohm
VDROP= 11mV
Delay time: 9.3us
+1.05VALW +1.05V_VCCST_OUT +1.8VS_OUT

+1.8VALW
2 2 2
2
CQ11 CQ9 CQ22
1U_0402_6.3V6K CQ24 0.1U_0201_10V6K 0.1U_0201_10V6K
1 1 1
1U_0402_6.3V6K
1
4 4


DC Interface
A B C D E
A B C D E
change PL101、、、PL10 3 fro m

PL102
M01000P200 to SM01000U600
@
1
ACES_50290-00801-001
+19V_ADPIN FBMA-L11-201209-800LMA50T
EMI@ PL101 +19V_VIN 1
1 1 2
1 2 EMI@ PL102
2
EMI@ PC104
3
1000P_0402_50V7K
FBMA-L11-201209-800LMA50T
3
1
EMI@ PC102
4 PR103
100P_0402_50V8J
4 5 1 2 PR102
5
1
6 4.7_1206_5% EMI@ PL103
6
1
7 FBMA-L11-201209-800LMA50T 4.7_1206_5%
2
7 8
2
8 1 2
2
1
PJP101
1
PC101 EMI@ EMI@ PC105
99.9
0.1U_0603_25V7K 0.1U_0603_25V7K
2
2 2
3 3
@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC
4 4
2016/11/03
Compal Secret Data
2017/06/14 Title
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
A B C D E
A B C D E
+3VLP
1
1 1
PC205 @
1
0.1U_0603_25V7K
2
@
PR207 100_0402_1% @ PR215 PR214
100K_0402_1%
1 2 26.7K_0402_1% 21.5K_0402_1%
EC_SMB_DA1 <43,54>
PR213
PR205 100_0402_1%
2
1
1 2
EC_SMB_CK1 <43,54>
PU201 @
1 8
VCC TMSNS1
(Common Part)
PR202 2 7 2 1
Battery Bot Side <45,47> SL200002H00
2
200K_0402_1% GND RHYST1
@
1
1 2 MAINPWON 3 6 @ PR216
+3VLP <43,50,55> MAINPWON OT1 TMSNS2
100K_0402_1%_NCP15WF104F03RC
@ PJP201 10K_0402_1% @
PIN1 GND 1 4 5 2 1
1 2 OT2 RHYST2
PIN2 GND 2 3
1 2
BATT_TEMP <43,54>
1
EC_SMB_DA1-1
PH202
G718TM1U_SOT23-8 @ PR218
PIN3 SMD
2
3 4 EC_SMB_CK1-1 PR203 1K_0402_1% 14K_0402_1%
4 5 BATT_TS
100K_0402_1%_NCP15WF104F03RC
PIN4 SMC 5 6 BATT_B/I
6 7
PIN5 TEMP
PH203
(Common Part)
2
7 8
PIN6 BI 8 9 +RTCVCC SL200002H00
GND 10
PIN7 Batt+ GND 2016/09/26 @
PIN8 Batt+ PH3 Near VGA.
CVILU_CI9908M2HR0-NH Change thePQ201 from
1
PR212 SB00000QO00 to SB00001GD00,
100K_0402_5%
1
2 D 2
2 PQ201
<50> BI_GATE G LBSS139LT1G 1N SOT-23-3
S
3
+12.6V_BATT+
EMI@ PL201 2016/11/22 update
FBMA-L11-201209-800LMA50T
1 2 For KB9022
+12.6V_BATT BI_S <50>
sense 5mΩ Active Recovery When PR204=16.9K
EMI@ PL202
1
FBMA-L11-201209-800LMA50T
1 2 PR217 For KB9022
0_0402_5% OTP Active Recovery
2
design reserve VCIN0_PH(V) 89'C, 1V 56'C, 2V
1
PC201 EMI@ PC202 EMI@
1000P_0402_50V7K 0.01U_0402_25V7K
2
PH202(ohm) 7.3092K 26.11K
3/27 thermal PH1 92'C ->89'C

+3VLP_ECA
PR206
10K_0402_1%
1 2
ADP_I <43,54>
1
3 3
PR204
18.7K_0402_1%
VCIN1_ADP_PROCHOT <43>
2
VCIN0_PH <43>
1
PC203 must close to EC pin
1
PR208
10K_0402_1% PH201
2
@ PC203
100K_0402_1%_NCP15WF104F03RC
2
0.1U_0402_25V6
1
T202@ PH201 is Common Part SL200002H00
T201@
ECAGND <43>
T202 T201 must close to PH201
ADP_I=20*I(adapter)*0.01
4
I(adapter)=adapter(W)*130%/19 4
2016/11/03
Compal Secret Data
2017/06/14 Title
BATTERY CONN/OTP
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
5 4 3 2 1
Module model information

ISL95520_Hybrid_Boost_V2.mdd
Protection for reverse input
Vgs = 20V
Vds = 60V
Id = 250mA
1
D D D
2 PQ301 max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W
G L2N7002WT1G_SC70-3 PR339 @
S 0.01_1206_1%
CSR rating: 1W +19VB
3
VCSIP-VCSIN spec < 81mV
1 2 1 2 1 4
PR301 PR302 2 3
1M_0402_1% 3M_0402_5%
PQ311
PQ310 +19V_P1 AON7380_DFN3X3-8-5
Need check the SOA for inrush TPCA8057 1N DFN5X6-8
+19V_P2
PR303
+19VB_CHG
1 1 0.005_1206_1% EMI@ PL704
2 2 FBMA-L11-201209-800LMA50T
5 3 3 5 1 4 1 2
+19V_VIN
EMI@
EMI@
EMI@
2200P_0402_25V7K
2 3 Isat: 10A
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
CSIP_CHG_R
DCR: 14mohm
1
CSIN_CHG_R
PC302
PC303
PC305
PC304
PC324
@ PC322 @ PJP1
2
1 2 1 2
1 2
1000P_0402_25V JUMP_43X118
1
2_0402_5%
Co-lay jump and ISN choke.
PR305
@
PR304
1 0_0402_5%
PR306
2
499K_0402_1%
2
PC306
PQ312
2
4.02K_0402_1%
4.02K_0402_1%
1 2 AON7380_DFN3X3-8-5
1
L->H 0.1U_0402_25V6 2
2.04 vin min w/o 2M =17.41 5 3
C H->L PR309 C
PC307 0.22U_0603_25V7K
2.02 vin min w 2M =17.77 100_0402_1%
4
PR307
PR308
1 2 +12.6V_BATT
1
CMSRC_CHG
2200P_0402_50V7K
66.5K_0402_1%
@ PC308
1
PR310
PC301
1
ASGATE_CHG 1 2
2
BGATE_CHG
2
OPCN_CHG 2
0.1U_0402_25V7K
CSIN_CHG
CSIP_CHG
OPCP_CHG
VBAT_CHG
0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd R s2 = 10m
Ω
1 VDD_CHG
BIT0 = 1.14uA/W PQ305

BIT1 = 0.285uA/W
AON7506_DFN33-8-5
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20m Ω
100K_0402_1%
support Turbo boost : 2200P Support max charge 3.5A
32
31
30
29
28
27
26
25
BIT0 = 2.28uA/W no support Turbo boost : 0.1u PU301
BIT1 = 0.57uA/W Choke 4.7uH SH00000YC00 (Common Part) Power loss: 0.245W
PR311
CSIP
ASGATE
QPCP
BGATE
CSIN
CMSRC
OPCN
VBAT
PC309 4 (Size:6.6 x 7.3 x 3 mm) CSR rating: 1W
Ipsys = KPSYS  x 
( VAD P x IAD P + VBA T T
x IBA ) PR312 0.47U_0402_16V4Z (DCR:28m~33m) VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R
1 2
R_Psys = 1.2V / Ipsys
2
ACIN BOOT PR315

KPSYS = 1.14uA/W UG_CHG
adapter wattage = 45W 2 23 0_0603_5% PL301 0.01_1206_1%
3
2
1
<43> AC_IN @ PR314 0_0402_5% ACOK UGATE 4.7UH_PCMB063T-4R7MS_8A_20% +12.6V_BATT
Battery wattage = 40Wh
1
EC_SMB_DA1_R 3 LX_CHG +17.4V_BATT_CHG 1

158K_0402_1%
1 2 22 1 2 4
Ipsys = 1.14 x (45+40) = 96.9uA <43,53> EC_SMB_DA1 SDA PHASE
PR313
@ PR316 0_0402_5%
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. EC_SMB_CK1_R 4 LG_CHG
4.7_1206_5%
1 2 21 2 3
<43,53> EC_SMB_CK1 SCL LGATE
1
=====================================
EMI@ PR320
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PR317 0_0402_5% PQ306
5
adapter wattage = 65W 1 2 5 20 VDDP_CHG
2
Battery wattage = 40Wh <11,43> H_PROCHOT# PROCHOT# VDDP
AON7506_DFN33-8-5
1
2 1K_0402_1%AMON_ISL95520 6 VDD_CHG
PC310
PC311
PC312
Ipsys = 1.14 x (65+40) = 119.7uA PR318 1 19 1 2
R_Psys = 1.2V / 96.9uA = 10K-ohm. <43,53> ADP_I AMON VDD
2
PR321 1 2 1K_0402_1%BMON_ISL95520 7 ISL88739AHRZ-T_QFN32_4X4 18 PR319 4.7_0402_5%
2
BMON DCIN
680P_0402_50V7K
**Design Notes** 4
BATGONE
Close to EC. 8 17 PC313 PC314
For 45W/65W /90W system, 2S/3S/4S battery NC NTC
1U_0201_6.3V6K 1U_0201_6.3V6K
CCLIM
2
ACLIM
COMP
1
B Maximum Charging current 3.5A
PROG
B
AGND
CSON
CSOP
EMI@ PC315
FSET
PR323
1
Maximum Battery discharge power 55W 100K_0402_1%
3
2
1
1
#Register Setting PC316 PC317
2
0.1U_0402_25V6 0.1U_0402_25V6 PR322 PD1
33
10
11
12
13
14
15
16
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function Follow adapter and 0_0402_5% PR324 10_1206_5% 3
+19V_VIN
2
2. Disable turbo when AC only battery wattage in 1 2 1
2
#Circuit Design Close to Vsys current source. 2
2
2
FSET_CHG
PC318
1U_0603_25V6
EC.
1. ACLIM and CCLIM are devider voltage control. Base on CPU Core VR design. @ VF = 0.38V For 4S per cell 4.35V battery
The resistor is pop on CPU VR schematic. S SCH DIO BAS40CW SOT-323
1
2. Use 7X7 choke and 3X3 H/L side MOSFET @ PR326
1
Charge current 3A PR325 0_0603_5%
ACIN_CHG
10K_0402_1% 1 2
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) VDD_CHG +12.6V_BATT
Power density : 0.61 (23X16) VDD=5V
2
#Protect function
1
CCLIM_CHG
1. ACOVP : VCC voltage > 24V
200K_0402_1%
4S_BATT@ PR342
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
1
ACLIM_CHG 2M_0402_1%
3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
PR328
PR329
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R
4. CHGOCP : based on charge current setting 200K_0402_1%
2
5. BATOVP : 4.6V/Cell +3VS Pull high on HW side COMP_CHG PR330 2_0402_5%
2
1
6. BATLOWV : No.
@ PR331 PR333=0 ohm, Fs=500KHZ ~ +/- 15%
7. TSHUT : 150C PC319 4S_BATT@ PQ308
1
1
100_0402_1%
76.8K_0402_1% 0.1U_0402_25V6
2
PR332
1 2 LTC015EUBFS8TL_UMT3F
1
CSON_CHG CSON_CHG_R
150K_0402_1%
560P_0402_50V7K
@ 1 2
1
1
PR335
@VGA@ @VGA@ OCCP setting PR333
1
PR336 180W@
PC320
PR340 PR341 @ PQ309 0_0402_5% @ PR334 0_0402_5%

2
2
1
D
110K_0402_1%
10K_0402_1% 10K_0402_1%
2
1
AC_IN
0.015U_0402_25V7K
2 PR337 4S_BATT@ PR343

2
G 75K_0402_1% @ BATT_TEMP <43,53> 100K_0402_1%

2
PC321
S 1 2 2
3
<43> BATT_4S
L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP)
2
<20,26,43> DGPU_AC_DETECT logic high: above 2.4V

2
Hybrid boost power mode logic low: under 0.8V

Cell = 4s 4S_BATT@
3
1
PQ315 D
6
D 2
2 <43,51,56,59> SUSP# G
A A
G
@VGA@ @VGA@ @VGA@ 2N7002KW_SOT323-3 S
3
PQ314 PQ313B S PQ313A
1
1
RUM001L02_VMT3 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 ICClimit : 7.73A

Delta I : 1.44A
3
1C charge current :6.48A

D
H_PROCHOT# 2 AC_IN 5
G Battery current limimed by CCLIm ~ 3.89A.
Adapter current limimed by ACLIm ~ 4.33A.
S (PR779 and PQ741 are for change ACLIm when AC in)
4

3
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ) .
CC_LIM = VccLIM / 64 x Rs2 Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
============================================================= PWR_CHARGER
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ) . THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC_LIM = VccLIM / 32 x Rs2
============================================================= MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AC_LIM = Vac_LIM / 32 x Rs1 Date: Tuesday, February 13, 2018 Sheet 54 of 73
5 4 3 2 1
A B C D E
PR402
499K_0402_1%
ENLDO_3V5V 1 2
+19VB
1
150K_0402_1%
PR404
EN1 and EN2 dont't floating
2
@EMI@ PL401
HCB2012KF-121T50_0805
1 2 PU401
1 +19VB SY8286BRAC_QFN20_3X3 PC401 1
PR401
@ PJ403 0.1U_0603_25V7K
+19VB_3V BST_3V
2200P_0402_50V7K
1 2 1 2 1 2 Choke 1.5uH SH000016800 (Common Part)
1 2
(Size:4.9 x 5.2 x 3 mm)
10U_0805_25V6K
EMI@ PC431
@EMI@ PC403
EMI@ PC404
0.1U_0402_25V6
0.1U_0402_25V6
JUMP_43X79
0_0603_5%
1
(DCR:20m~25m)
PC405
BS
IN
IN
IN
IN
PL402
2
LX_3V6 20 LX_3V 1 2
LX LX +3VALWP
7 19 1.5UH_PCMB053T-1R5MS_6A_20%
GND LX
@EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR405
1
1
680P_0402_50V7K 4.7_1206_5%
8 18
+3VALWP GND GND
PC407
PC408
PC409
PC410
@ PC429
@ PC430
9 17
+3VLP
2
PG LDO
1
1 3V_SN
10 16
2
NC NC
1
Check pull up resistor of SPOK at HW side PC411
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
PR406 GND 2
100K_0402_5%
11
12
13
14
15
@EMI@
PC412
2
2
3.3V LDO 150mA~300mA Vout is 3.234V~3.366V
<43,58> SPOK_3V
ENLDO_3V5V PC402 PR403
Ipeak=4.65A
3V_FB
1000P_0402_25V8J1K_0402_5% Imax=3.25A
1 2 1 2
<43> 3V_EN Iocp=10A
@EMI@ PL403
2 HCB2012KF-121T50_0805 2
+19VB 1 2 +19VB_5V
PU402 PC418
PR408
@ PJ404 SY8288CRAC_QFN20_3X3 0.1U_0603_25V7K
1 2 +19VB_5V BST_5V 1 2 1 2
1 2
Choke 1.5uH SH000016700 (Common Part)
1
JUMP_43X79 0_0603_5% (Size:7.3 x 6.6 x 3 mm)
BS
IN
IN
IN
IN
(DCR:14m~15m)
EMI@ PC432
0.1U_0402_25V6
1
LX_5V 6
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
20
LX LX PL404
7 19 LX_5V 1 2 +5VALWP
2
GND LX
1
1
PC414
PC415
EMI@ PC416
@EMI@ PC417
8 18 1.5UH_9A_20%_7X7X3_M
GND GND PC419
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
9 17 1 2
PG VCC
1
PR409
PC420
PC421
PC422
PC423
@ PC424
@ PC425
4.7_1206_5%
+3VLP
@EMI@
10 16 4.7U_0402_6.3V6M
2
NC NC
OUT
LDO
EN2
EN1
21
FF
GND
1
2
11
12
13
14
15
PR413
VL
1 5V_SN
100K_0402_5% 1
5V LDO 150mA~300mA
2
680P_0402_50V7K
PC427
<43> SPOK_5V ENLDO_3V5V 2
4.7U_0402_6.3V6M Vout is 4.998V~5.202V
PC426
@EMI@
Ipeak=9A
2
5V_EN
Imax=6.6A
3 Iocp=10A 3
PC413 PR407
1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2
PR410
2.2K_0402_5%
1 2
<43> EC_ON @ PR411
0_0402_5% @ PJ401
1 2 +3VALWP 1 2 +3VALW
<43,50,53> MAINPWON 1 2
JUMP_43X118
5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
@ PJ402
1
PR412
PC428
+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
2
4 4
2016/11/03
Compal Secret Data
2017/06/14 Title
3.3VALWP/5VALWP
Custom 1.A
A B C D E
A B C D E
1 1
@ PJ503
JUMP_43X79 Pin19 need pull separate from +1.35VP.
1 2
1 2 +19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
1 2 +19VB_1.2VP PR502 Peak Current 1A
+19VB @EMI@ PL501 2.2_0603_5%
HCB2012KF-121T50_0805 BST_1.2VP_R 1 2 BST_1.2VP
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
+1.2VP
1
1
EMI@ PC526
@EMI@ PC502
EMI@ PC503
PC504
PC505
change PL501 from UG_1.2VP +0.6VSP
2
2
SM01000C000 to comm
part SM01000P200 LX_1.2VP
10U_0603_6.3V6M
10U_0603_6.3V6M
5
1
PC506
1
PC507
PC508
0.1U_0603_25V7K
16
17
18
19
20
2
PU501
2
2 2
VLDOIN
PHASE
UGATE
BOOT
VTT
Choke 1uH SH00000YE00 (Common 4 21
PAD
Part) LG_1.2VP 15 1
(Size:6.86 x 6.47 x 3 mm) LGATE VTTGND
(DCR:6.2m~7.2m Ohm) PQ503 IOCP
1
2
3
AON7408L 1N DFN 14 2
PL502 PR503 PGND VTTSNS
1UH_PCMC063T-1R0MN_11A_20% 17.4K_0402_1%
1 2 LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PQ502
PC509 CS RT8207PGQW _W QFN20_3X3 GND
1
5 1U_0201_6.3V6K
AON7506_DFN3X3-8-5 1 2 12 4 VTTREF_1.2VP
@EMI@ PR504 PR505 VDDP VTTREF
4.7_1206_5% 5.1_0603_5% 35.4
1 2 VDD_1.2VP 11 5
PC523
PC522
PC521
PC524
PC525
PC520
1 2
+5VALW VDD VDDQ +1.2VP
1
PGOOD
PC516
1 1 1 1 1 1 4
TON
1
1
@EMI@ PC518 PC517 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K
2
1U_0201_6.3V6K PR511
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10
6
2 2 2 2 2 2 2.2_0402_1%
35.4
1
2
3
FB_1.2VP
TON_1.2VP
EN_1.2VP
Frequency PR506
+5VALW
EN_0.6VSP
6.19K_0402_1%
PR507 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2
3 3
Vout=0.75V* (1+Rup/Rdown)
1
H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A =0.75*(1+(6.19/10))
PR501 PR508
0_0402_5% 10K_0402_1% =1.214V 1.2%
L/S SI7716 Rds(on) :typ:13.5m Ohm, max:16.5m Ohm 1 2
2
Idsm(TA=25)=16A, Idsm(TA=70)=9.5A <43,51,58> SYSON
1
@ PC501
Choke: 7x7x3 0.1U_0402_10V7K
=0.75*(1+(8.2/10))
Rdc=6.2mohm(Typ), 7.2mohm(Max) =1.365V 1.1%
2
Switching Frequency: 530kHz @ PR509
Imax=A, Iocp=A 0_0402_5%
Iocp=10.63~12.76A 1 2
<43,51,54,59> SUSP#
OVP: 110%~120% @ PJ501
VFB=0.607V, Vout=1.214V PR510 JUMP_43X118
0_0402_5% +1.2VP 1 2 +1.2V_VDDQ
1 2 1 2
<11> SM_PG_CTRL
1
@ PC519 @ PJ502
JUMP_43X39
0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS_VTT
2
1 2
4 Mode Level +0.675VSP VTTREF_1.35V 4

S5 L off off
S3 L off on
S0 H on on
Note: S3 - sleep ; S5 - power off Security Classification

2016/11/03
Compal Secret Data
2017/06/14 Title
DDR4
A B C D E
A B C D E
@EMI@ PL601 +19VB_1VALW

1 1
HCB2012KF-121T50_0805 EN pin don't floating @EMI@ PR605 @EMI@ PC602
1 2 4.7_1206_5% 680P_0402_50V7K @ PJ601
If have pull down resistor at HW side, pls delete PR702 1 2 SNUB_1VALW 1 2 JUMP_43X118
PU601 @ PR606 1 2
+19VB_1VALW +1.05VALWP 1 2 +1.05VALW
+19VB 1
1 2
2 2
IN PG
9
0_0603_5%
PC603
0.1U_0603_25V7K
10U_0805_25V6K
0.1U_0402_25V6
@ PJ602 3 1 BST_1VALW 1 2 BST_1VALW_R 1 2 PL602
EMI@ PC616
0.1U_0603_25V7K
2200P_0402_50V7K
IN BS
1
JUMP_43X79 1UH_11A_20%_7X7X3_M
EMI@ PC604
@EMI@ PC605
PC606
LDO_3V LX_1VALW
4
IN LX
6 1 2
+1.05VALWP
220U_B2_4VM_R35M
2
2
5 19 Choke 1uH SH00000YE00 (Common Part) 1
15.4K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
IN LX
(Size:6.86 x 6.47 x 3 mm)
1
PR607 @ 7 20 +
PR608
PC608
PC609
PC610
PC611
PC612
@ PC615
GND LX (DCR:6.2m~7.2m Ohm)
0_0402_5%
8 14 FB_1VALW Rup
2
GND FB 2
2
2
ILMT_1VALW 18 17 LDO_3V
GND VCC
1
1
EN_1VALW 11 10
@ PR609 EN NC PC613
change PL601 FB = 0.6V
1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M
2
SM01000C000 to comm ILMT NC PR610
0_0402_5%
15 16
part SM01000P200 +3VALW Rdown
2
BYP NC 20K_0402_1%
21
2
PAD
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PC614
is pull low, floating or pull high 1U_0402_6.3V6K
2
=0.6*(1+(15.4/20))
Vout=1.062V
2 2
PR611
10K_0402_1%
1 2
+1.8_PG <58>
PR603
10K_0402_1%
EN_1VALW 1 2
+3VALW
@
1
@ PC601
PR601
0.22U_0402_10V6K
2
1M_0402_1%
2
3 3
4 4
2016/11/03
Compal Secret Data
2017/06/14 Title
1V
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.A
A B C D E
A B C D E
PR7123
0_0402_5%
EN_1.8V 1 2
SPOK_3V <43,55>
1
Current limit = 4.7A(min) PR7124 @ PC7118
0.1U_0402_16V7K
2
PR7126 1M_0402_5%
100K_0402_5%
2
2 1
+3VALW
1 1
PU7105 Choke 1uH SH00000YG00 (Common Part)

<57> +1.8_PG 9
1 PGND 8 (Size:3.8 x 3.8 x 1.9 mm)
VIN_1.0VSDGPUP FB SGND (DCR:20m~25m)
2 7
PG EN PL7103
3 6 LX_1.8V 1 2
IN LX 1UH_2.8A_30%_4X4X2_F +1.8VALWP
4 5
20.5K_0402_1%
68P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PGND NC
@EMI@ PR7125
4.7_0603_5%
1
1
PC7127
PR7122
PC7123
1
SY8003ADFC_DFN8_2X2
PC7119
PC7125
@ PC7126
22U_0603_6.3V6M
Rup
2
2
2
2
FB_1.8V
680P_0402_50V7K
1
1
FB=0.6V PR7121
@EMI@ PC7124
Note:Iload(max)=3A
10K_0402_1%
Rdown
2
+3VALW
2 2
+5VALW
2
PJ7105
2
JUMP_43X79
@
1
1
1
PC7210
1U_0402_6.3V6K
2
1
PC7108
FB=0.8V
22U_0603_6.3V6M Note:Iload(max)=4A
2
PU7102 G9661MF11U_SO8
PR7110 4 5
0_0402_5% VIN_2.5V 3 VDD NC 6
<43,51,56> SYSON 1 2 EN_2.5V 2 VIN VOUT 7 +2.5VP
GND
1 EN ADJ 8
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01U_0402_25V7K
PGOOD GND
1
0.1U_0402_16V7K
1
PR7115
PC7109
9
1
1
PR7113
PC7107
PC7110
@ PC7111
21.5K_0402_1%
Rup
2
1M_0402_5%
2
2
@ FB_2.5V
1
PR7116
10K_0402_1%
Rdown Vout=0.8V* (1+Rup/Rdown)
Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.008)
2
3 3
@ PJ7103
JUMP_43X79
1 2
+2.5VP 1 2 +2.5V
@ PJ7107
JUMP_43X79
1 2
+1.8VALWP 1 2 +1.8VALW
4 4
+1.5VSP:
Imax=0.5A Ipeak=0.75A
2016/11/03
Compal Secret Data
2017/06/14 Title
1.5VS/2.5V
A B C D E
5 4 3 2 1
@EMI@ PR7203 @EMI@ PC7203 @ PJ7201

4.7_1206_5% 680P_0402_50V7K 1 2
1 2 SNB_+VCCIOP 1 2 +1.0VS_VCCIOP 1 2 +VCCIO
JUMP_43X118
@EMI@ PL7201
HCB2012KF-121T50_0805
D D
1 2 Choke 0.68uH SH00000Z300 (Common Part)
(Size:4.85 x 4.7 x 2.8 mm) Imax=3.85A, Ipeak=5.5A, Iocp:6.6A
@ PJ7202 PU7201 @ 0_0603_5%
1 2 +VCCIOP_B+ 2 9 PC7202 (DCR:11m~12m)
+19VB 1 2 IN PG PR7202
0.1U_0603_25V7K
JUMP_43X79 3 1 +VCCIOP_BST 1 2+VCCIOP_BST_R 1 2 PL7202
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1
1
1
IN BS 0.68UH_7.9A_20%_5X5X3_M
PC7207
@EMI@ PC7217
PC7208
+VCCIOP_LX
4
IN LX
6 1 2
+1.0VS_VCCIOP
2
2
1
5 19
PC7219
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
1
1
7 20
EMI@
PC7204
PC7205
PC7206
PC7211
PC7212
PC7214
Note:Iload(max)=5.5A
10_0402_1%
2
GND LX @
PR7212
8 14 +VCCIOP_FB
IOCP=7A~8A(typ)
2
2
2
GND FB
2
PR7214
1K_0402_1%
18 17 +VCCIOP_LDO_3V @
2
GND VCC
1
+VCCIOP_EN 11 10 PC7218 @
EN NC 2.2U_0402_6.3V6M
1
+VCCIOP_ILMT 13 12 FB = 0.6V Rup
2
ILMT NC 1 2 =0.6*(1+(12k/20.5k))
15 16
+3VALW BYP NC PR7218 OVP=0.95V*115%=1.0925V
1
21 12K_0402_1%
Vout=0.951 V 2%
1U_0402_6.3V6K
PAD
PC7209
20.5K_0402_1%
1
SY8288RAC_QFN20_3X3
Rdown
2
PR7215
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
2
PR7209 @ 0_0402_5%
VCCIO_SENSE_R 1 2 VCCIO_SENSE
+VCCIOP_LDO_3V VCCIO_SENSE <13>
PR7210 @ 0_0402_5%
1
@ PR7207 1 2 VSSIO_SENSE
VSSIO_SENSE <13>
C 0_0402_5% C
@ PR7213 VR_ON 1 2
0_0402_5% <43,51,60,61> VR_ON
2
+VCCIOP_ILMT PR7208
1K_0402_5%
1
SUSP# 1 2 +VCCIOP_EN
@ <43,51,54,56> SUSP#
0.1U_0402_25V6
PR7217
1M_0402_5%
1
1
PC7201
check delay time with HW
PR7201
0_0402_5%
2
2
2
B B
A A

DH53F M/B LA-F991P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0VS_VCCIO
5 4 3 2 1
5 4 3 2 1
+19VB_CPU +19VB_CPU
90A for ICCMAX=2.2V 76A for ICCMAX=2.2V EMI@ PL8102
FBMA-L11-201209-800LMA50T
+VREF +VREF 1 2
+19VB
PC8104 PC8105 PC8106 PC8107 EMI@ PL8103
100U_25V_NC_6.3X6
confirm with power sequence, EMI@ EMI@ 1 FBMA-L11-201209-800LMA50T
1
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
it need behind +5VS. 1 2
PC8108
+
PR8102 PR8103
2
30.1_0402_1%
8.45K_0402_1% 2
7.5K_0402_1%
4.02K_0402_1%
1
1
+19VB_CPU +19VB_CPU
2
NTC1P NTCGT1P
PR8104
PR8105
1
1
PR8106 PR8101 PC8101 Ta=70=>Id=17.5A
PH8102 PH8101 100_0402_1% 2.2_0603_1% 0.1U_0603_25V7K
Rdson=8.2~10.5 mohm
2
1 2 BOOST_VCC1 1 2BOOST_VCC1_R
1 2 Choke 0.15uH SH00000X700
100K_0402_1%_B25/50 4250K 10K_0402_1%_B25/50 3370K
8.66K_0402_1%
8.66K_0402_1%
PQ8101 (Size:6.59 x 6.6 x 3.0 mm)
1
2.2_0402_1%
2.2_0402_1%
2
PU8102
2
PC8109 PC8110 NTC1N NTCGT1N (DCR:0.9m +-7%)
PR8107
PR8108
PR8109
PR8110
1 2 +VCC_CORE
G1
D1
VSSGT_SENSE <12> VCC_UG1
Fs=400k, LL=1.8m for Core 0.22U_0402_25V6K 0.22U_0402_25V6K 4 3 PL8101
2
@ PR8111 0_0402_5% BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20%
2 RTCPU_TSEN_R 2
2 RTCPU_TSENA_R 2
5 2 VCC_PHASE1 7 VCC_PHASE1 1 4
Fs=400k, LL=2.1m for GT PWM PHASE D2/S1
PR8115
1.8K_0402_1%
5.76K_0402_1%
1
1
D SET1 ICCMAX=128A, OCP=120%, DVIDT=35.7mV. 100_0402_1% PR8112 EN1 1 6 2 3 D
EN PGND
+1.05V_VCCST 1 2 5.1_0402_1%
G2
PR8113
PR8114
S2
S2
S2
57.6K_0402_1%
VCC_LG1
1
SET2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44% 1 2 8 7
57.6K_0402_1%
+5VALW VCC LGATE
1
9
PR8119
402K_0402_1%
442K_0402_1%
0.47U_0402_16V4Z
3
1
1
GND AON6962_DFN5X6D-8-7 @EMI@
SET3 Zero LL disable, VR address Core=0, GT=1.
PR8118
1
220K_0402_5%_B25/50 4700K
220K_0402_5%_B25/50 4700K
PC8112 PR8121
PR8116
PR8117
1
1 2 RT9610CGQW_WDFN8_2X2 4.7_1206_5%
SETA1 ICCMAX=32A, OCP=120%, DVIDT=60mV. VSSSENSE <12>
PC8111
@ PR8122 1U_0201_6.3V6K
1
SETA2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44% @ PR8120 0_0402_5%
PH8103
PH8104
200_0402_1%
2
2
1K_0402_1%
PR8123
SNUB_VCC1
Core offset function disable, GT offset PR8126
2
RTCPU_TONSETA RTCPU_TONSET
100_0402_1% PC8113
RTCPU_TSEN
100K_0402_1%
function disable, PSYS disable.
RTCPU_TSENA 1
1
1 2 0.47U_0402_6.3V6K
VR_HOT# <43>
2
1
1
+VREF @EMI@ 1 2 1 2
PR8124
1_0402_1%
SCLK_CPU PR8129
PC8114
PR8127
SDIO_CPU RTCPU_PS4 1
2
2 EN1 680P_0603_50V8J PR8125 @ PR8131
2
ALERT_CPU
PR8130 200_0402_1% 0_0402_5%
PR8128
0_0402_5%
+19VB_CPU
RTCPU_IBIAS 2
0_0402_5% 1 2
2
RTCPU_EN 1 2 0_0402_5%
VSSGT_SENSE_R VR_ON <43,51,59,61>
@
10K_0402_1%
3.01K_0402_1%
13.3K_0402_1%
13.3K_0402_1%
1
VSSSENSE_R
1
@ Ta=70=>Id=30A AISP1 AVcore1

8.2K_0402_1% 5.1K_0402_1%
+VREF
RT3607CEGQW_WQFN56_6X6 PC8119 PC8120 PC8121 PC8117
Rdson=2.8~3.5 mohm
PR8132
PR8133
PR8134
PR8135
PR8136
EMI@ EMI@
1
PU8101
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
PC8115
57
42
20
21
22
31
16
23
26
25
24
27
32
13
2
1
1U_0201_6.3V6K
VREF
VR_HOT
ALERT
VDIO
GND
TSEN
IMON
NC
EN
RGND
TSENA
IMONA
IBIAS
VCLK
RGNDA
2
1
1
0_0402_5%
2K_0402_1%
24.9_0402_1%
26.7K_0402_1%
@ PR8139 0_0402_5%
PR8137
PR8143
PR8138
PR8140
2 1 56
PR8141
NC 52 RTCPU_PWM1
@ PR8142 0_0402_5%
2 1 44 PWM1 PR8144 PC8122
2
NC 51 RTCPU_PWM2
@ 2.2_0603_1% 0.1U_0603_25V7K Ta=70=>Id=17.5A
RTCPU_TONSET 55 PWM2 BOOST_VCC2 1 2BOOST_VCC2_R
1 2
RTCPU_SET1 TONSET 53 RTCPU_PWM3 Rdson=8.2~10.5 mohm
RTCPU_SET2 RTCPU_TONSETA 43 PWM3
RTCPU_SET3 TONSETA 50 RTCPU_PWM4 PQ8102
RTCPU_SETA1 RTCPU_PS4 PWM4 PU8103
2
49
RTCPU_SETA2 PS4 30
G1
D1
RTCPU_SET1 14 NC 4 3 VCC_UG2
PL8306
SET1 5 PR8150 BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20%
768_0402_1%
402_0402_1%
3.4K_0402_1%
1.02K_0402_1%
300_0402_1% 3.16K_0402_1%
RTCPU_SET2 AISP1 VCC_PHASE2 VCC_PHASE2

1
15 ISEN1P 680_0402_1% 5 2 7 1 4
SET2 4 RTCPU_ISEN1N 1 2 PWM PHASE D2/S1
RTCPU_SET3 ISEN1N AVcore1
17 PR8151 EN2 1 6 2 3
PR8145
PR8146
PR8147
PR8148
PR8149
SET3 5.1_0402_1% EN PGND
G2
S2
S2
S2
RTCPU_SETA1 18 6 1 2 8 7 VCC_LG2
PR8152
GND AISP2 +5VALW
2
SETA1 ISEN2P 680_0402_1% VCC LGATE 9
3
RTCPU_ISEN2N GND
1
7 1 2 AON6962_DFN5X6D-8-7 @EMI@
412_0402_1%
RTCPU_SETA2 19 ISEN2N AVcore2

1
1
PC8123 PR8158
SETA2 RT9610CGQW_WDFN8_2X2 4.7_1206_5%
PR8153
PR8154
PR8155
PR8156
PR8157
0_0402_5%
0_0402_5%
0_0402_5%
2 PR8159 1U_0201_6.3V6K
AISP3
1
ISEN3P 680_0402_1%
200_0402_1%
2
RTCPU_VSENA 33 3 RTCPU_ISEN3N 1 2 PR8161
PR8160
RTCPU_VSENA AVcore3
2
VSENA ISEN3N SNUB_VCC2

@ @ @ 200_0402_1%
C RT3607CE 9
AISP4 PR8162
PC8124
0.47U_0402_6.3V6K C
2
1
ISEN4P 680_0402_1% @EMI@ 1 2 1 2
RTCPU_VSEN 12 8 RTCPU_ISEN4N 1 2 PR8163
RTCPU_VSEN AVcore4 PC8125
VSEN ISEN4N RTCPU_PS4 1 2 EN2 680P_0603_50V8J @ PR8164
2
0_0402_5%
47 RTCPU_PWMA1 1 2
RTCPU_VSEN RTCPU_COMP 11 PWMA1 0_0402_5%
@ PR8165 PR8166 PR8167 COMP 46 @
0_0402_5% 10K_0402_1% 23.2K_0402_1% 10 PWMA2
Ta=70=>Id=30A AISP2 AVcore2
ISENA3N
ISENA2N
ISENA1N
ISENA3P
ISENA2P
ISENA1P
FB
PGOOD
COMPA
2 1 2 1 2 1 48
<12> VCCSENSE PWMA3 Rdson=2.8~3.5 mohm
DVD
VCC
FBA
RTCPU_FB +19VB_CPU
NC
PR8168 PC8126 PC8127

100_0402_1% 330P_0402_50V8J 82P_0402_50V8J
2 1 2 1 2 1 +19VB_CPU
+VCC_CORE
45
28
RTCPU_COMPA 34
35
54
29
40
41
36
37
RTCPU_ISENA1N 39
38
AISPGT1
PC8130 PC8131 PC8132 PC8133
510K_0402_1%
RTCPU_VCC
RTCPU_DVD
1
RTCPU_FBA
VCCCORE_VR_PWRGD EMI@ EMI@
1
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1
PR8171
PR8169
@ PR8170 680_0402_1%
2
0_0402_5% 2 1
AVGT1
2
RTCPU_VCC
100K_0402_1%
RTCPU_VCC
2
1
PR8174 PC8135 Ta=70=>Id=17.5A

1
PC8134 2.2_0603_1% 0.1U_0603_25V7K

PR8172
10_0603_1%
BOOST_VCC3 2BOOST_VCC3_R Rdson=8.2~10.5 mohm

1
PC8136 1 1 2
PR8173
0.1U_0402_25V6
2
2
2.2U_0402_6.3V6M PQ8103
PU8104
2
2
@ PR8175 RTCPU_VSENA
2
0_0402_5% PR8177 PR8176
G1
D1
4 3 VCC_UG3
10K_0402_1% 16.9K_0402_1% PL8305
2 1 2 1 2 1 BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20%
<12> VCCGT_SENSE VCC_PHASE3 VCC_PHASE3
5 2 7 1 4
PR8178 PC8137 PC8138 PWM PHASE D2/S1
+5VALW
100_0402_1% 330P_0402_50V8J 68P_0402_50V8J PR8179 EN3 1 6 2 3
2 1 2 1 2 1 5.1_0402_1% EN PGND
G2
S2
S2
S2
+VCC_GT VCCCORE_VR_PWRGD <43> 1 2 8 7 VCC_LG3
+5VALW VCC LGATE 9
3
GND
1
AON6962_DFN5X6D-8-7 @EMI@
100K_0402_1%
1
1
PC8139 PR8181
RT9610CGQW_WDFN8_2X2 4.7_1206_5%
1U_0201_6.3V6K
PR8180
1
200_0402_1%
2
PR8182
2
SNUB_VCC3
Reserved for RF Team Request
PR8183 PC8140
200_0402_1%
0.47U_0402_6.3V6K
2
1
+1.05V_VCCST confirm with power sequence, PR8184
@EMI@ 1 2 1 2
it need behind +5VS. PC8141
RTCPU_PS4 1 2
@RF@ PC8142 +3VALW EN3 680P_0603_50V8J @ PR8185
2
2.2P_0402_50V8C PR96and PR98 pull high resistor are pop at the end of VR 0_0402_5%
1 2 SVID. 1 2
0_0402_5%
Other VR is unpop. @
B B
PR8186 @ PR8187 PR8188 PC8143 Ta=70=>Id=30A AISP3 AVcore3
+19VB_CPU
Rdson=2.8~3.5 mohm
0.1U_0402_25V6
1
1
100_0402_1%
100_0402_1%
45.3_0402_1%
ENABLE @
Upper Threshold > 0.8V
2
Lower Threshold < 0.3V PC8146 PC8147 PC8148 PC8149

2
EMI@ EMI@
1
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
SCLK_CPU
PR8189 1 2 49.9_0402_1%
CPU_SVID_CLK_R <11,61>
2
ALERT_CPU
@ PR8190 1 2 0_0402_5%
CPU_SVID_ALERT#_R <11,61>
SDIO_CPU
PR8191 1 2 10_0402_1%
CPU_SVID_DAT_R <11,61> PR8192 PC8150 Ta=70=>Id=17.5A
2.2_0603_1% 0.1U_0603_25V7K
BOOST_VCC4 1 2BOOST_VCC4_R
1 2 Rdson=8.2~10.5 mohm
Ta=70=>Id=30A
Rdson=2.8~3.5 mohm PQ8104
PU8105
2
+19VB_CPU
G1
D1
4 3 VCC_UG4
H/S AON6380 Rds(on) :typ:8.2mOhm, max:10.5mOhm PL8106
BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20%
VCC_PHASE4 VCC_PHASE4
Idsm(TA=25)=22A, Idsm(TA=70)=17.5A 5
PWM PHASE
2 7
D2/S1
1 4
PC8151 PC8152 PC8153 PC8154 PC8155 PC8156 PR8193 EN4 1 6 2 3

EMI@ EMI@ 5.1_0402_1% EN PGND
G2
S2
S2
S2
VCC_LG4
1
1
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1 2 8 7
L/S AON6314 Rds(on) :typ:2.8mOhm, max:3.5mOhm +5VALW VCC LGATE 9
1
Idsm(TA=25)=37A, Idsm(TA=70)=30A GND AON6962_DFN5X6D-8-7 @EMI@
2
1
PC8157 PR8194
RT9610CGQW_WDFN8_2X2 4.7_1206_5%
1U_0201_6.3V6K
1
200_0402_1%
2
PR8196 PC8158 Ta=70=>Id=17.5A
PR8195
SNUB_VCC4
2.2_0603_1% 0.1U_0603_25V7K
BOOST_VCCGT1 1 2BOOST_VCCGT1_R
1 2 Rdson=8.2~10.5 mohm PR8197 PC8159
200_0402_1%
0.47U_0402_6.3V6K
2
1
PQ8105 @EMI@ 1 2 1 2
PU8106 PR8198
1
+VCC_GT PC8160
RTCPU_PS4 1 2 EN4 680P_0603_50V8J @ PR8199
G1
D1
2
4 3 VCCGT_UG1
PL8107 0_0402_5%
BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20% 1 2
RTCPU_PWMA1 5 2 VCCGT_PHASE1 7 VCCGT_PHASE1 1 4 0_0402_5%
PWM PHASE D2/S1 @
PR8200 EN5 1 6 2 3 Ta=70=>Id=30A AISP4 AVcore4
5.1_0402_1% EN PGND
G2
S2
S2
S2
1 2 8 7 VCCGT_LG1 Rdson=2.8~3.5 mohm

+5VALW VCC LGATE 9
6
GND AON6962_DFN5X6D-8-7 @EMI@

1
PC8161 PR8201
RT9610CGQW_WDFN8_2X2 4.7_1206_5%
1U_0201_6.3V6K
2
1
182_0402_1%
A A
2
PR8202
SNUB_VCCGT1
PR8203 PC8163
182_0402_1%
0.47U_0402_6.3V6K
2
1
@EMI@ 1 2 1 2
PR8204
PC8162
RTCPU_PS4 1 2 EN5 680P_0603_50V8J @ PR8205
2
0_0402_5%
1 2
0_0402_5%
@
AISPGT1 AVGT1
Security Classification Compal Secret Data

RT3607CE
5 4 3 2 1
5 4 3 2 1
PR902 and PR904 pull high resistor are pop at the end of VR SVID.
+1.05V_VCCST Other VR is unpop.
SVID_ALERT# pull high resistor is at HW side.
1
Confirm HW side.
Don't double pull high. @ PR8302 +1.05V_VCCST confirm with power sequence,
D
it need behind +5VS. D
1K_0402_5%
2
<43> VR2_HOT#
100_0402_1%
0.1U_0402_25V6
0.47U_0402_6.3V6K
1
PR8304
PC8303
PR8303
VREF_VCCSA
1
PC8302
45.3_0402_1%
2
14K_0402_1% 30.9K_0402_1%
2
1
VR_HOT# 90 degreeC PR8306
PR8305
49.9_0402_1%
ALERT# 87.3 degreeC
1
1 2
CPU_SVID_CLK_R <11,60>
PR8307
PH8302 @ PR8308
2
100K_0402_1%_B25/50 4250K 1_0402_1% 0_0402_5%
1 2 1 2
CPU_SVID_ALERT#_R <11,60>
2
1
PR8309
59K_0402_1%
PR8311
1
10_0402_1% Choke 7x7x4 7x7x3
1 2
PR8310
PR8313 CPU_SVID_DAT_R <11,60> Size and DCR 0.67m +-5%0.9m +-5%
1
10K_0402_1%
48.7K_0402_1%
2
TSEN_VCCSA_R
2 1 2 1 +19VB_CPU
PR8312
7.32K_0402_1%
2
1
PR8314 PR813 68.1K 73.2K
PR8315
Vboot=0V 200_0402_1% IMON
1
VREF_VCCSA
2200P_0402_50V7K
PR841 0 1.1K
2.4K_0402_1%
PR8316
EMI@ PC8308
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
@EMI@ PC8307
2
1
ALERT#_VCCSA
PC8304
PC8305
PR832 10K
TSEN_VCCSA
VREF_VCCSA
VCLK_VCCSA
IMON_VCCSA
SDIO_VCCSA
22K_0402_1%
3.6K_0402_1%
COMP
22.6K_0402_1%
2
1
1
2K_0402_1%
@ PC8306 PR833 40.2K 37.4K
2
1
1
+19VB_CPU
PR8318
PR8317
PR8319
PR8320
0.1U_0402_25V6 PR8321 EN: high > 0.7V, Low < 0.3V
2
0_0402_5% PR828 604 665
VCCSA_VR_EN 1 2
VR_ON <43,51,59,60>
2
PR8322 ISEN PR830 243 549
2
1
SET1 connect to 5V is into test mode. 2.2_0805_1%
16
18
17
2
0_0402_5%
120_0402_1%
The output is 1.05V. PR831 10K 1K

1
1
PR8326
300_0402_1%
VRHOT#
VCLK
VDIO
ALERT#
TSEN
IMON
VREF
EN
UG_VCCSA
PR8324
PR8325
PC8309 PR8301
C C
0.22U_0402_25V6K 2.2_0603_5% PH802 10K(3370K) 1K(3650K)
2
1 2 13 BOOST_VCCSA 1 2BOOST_VCCSA_R
@ VIN
2
PSYS_VCCSA 19 PU8301
0.22U_0402_16V7K
PSYS
4
SET1_VCCSA
PC8301
RT3601EAGQW_WQFN28_4X4
SET2_VCCSA PL8301 +VCC_SA
G1
D1
D1
D1
SET3_VCCSA 0.24UH_22A_20%_ 7X7X3_M
7.68K_0402_1%
2
28
PR8329
100_0402_1% 1.78K_0402_1%
1
SET1 LX_VCCSA 9 10 LX_VCCSA 1 4

300_0402_1% 20K_0402_1%
27 D2/S1 D1
PR8327
PR8328
SET2 14 AISP1_R 2 3
26 PWM PQ8301
Local sense, for debug only.
G2
S2
S2
S2
1
SET3 AONH36334_DFN3X3A8-10
4.7_1206_5%
Trace is form output cap that is near choke.
1 2
1 2
1 2
1
11 LG_VCCSA
@EMI@ PR8330
PR8331
5
LGATE
2.2K_0402_1%
10 LX_VCCSA
PR8332
PR8333
PR8334
576_0603_1% PC8310
PR8335 PHASE LG_VCCSA 0.47U_0402_6.3V6K
2
100_0402_1% VSEN_VCCSA 25 9 UG_VCCSA 1 2
1 SNUB_VCCSA 2
2 1 VSEN UGATE PR8336 PR8337
+VCC_SA
2
8 BOOST_VCCSA 255_0402_1% 10K_0402_1%

BOOT 1 2AVcore1_NTC 1 2
@ PR8340
AVcore1_VCCSA
0_0201_5%
2 1 1 2AVcore1_NTC_R
1 2
680P_0402_50V7K
<13> VCCSA_SENSE
AISP1_VCCSA
COMP_VCCSA 23
COMP
PC8311
@ PR8339 @ PR8341 @ PR8342 PR8343 PR8344 PR8345
0_0402_5% 0_0402_5% 10K_0402_1% 300_0402_1% 47.5K_0402_1% FB_VCCSA 24 PH8301
0_0402_5% 2 1 2 1 2 1 2 1 2 1 FB 10K_0402_1%_B25/50 3370K
2
29
GND
1
RGND_VCCSA
@EMI@
PC8312 PC8314 22
@ PC8313 330P_0402_50V8J 100P_0402_50V8J RGND
For NTC trace routing only.
0.1U_0402_25V6 2 1 1 2
VR_READY
2
ISEN1N
ISEN1P
DRVEN
1
PVCC
VCC
@ PC8315
0.1U_0402_25V6
2
+VCC_VCCSA1
12
15
21
20
B B
2 1
<13> VSSSA_SENSE
@ PR8346
+5VALW
1U_0201_6.3V6K
1
AISP1_VCCSA
PC8317
100_0402_1%
0_0402_5% @ PC8316 <43> VCCSA_VR_PWRGD

PR8347
0.1U_0402_25V6
2
2
1
AVcore1_VCCSA
PR8348
0.1U_0402_25V6
2
1
22_0402_1%
Confirm HW side. 100K_0402_5%

1
1
PR8349
PC8319
Don't double pull high. 36.3

PC8318
2
2.2U_0603_10V6K
2
2
2
Local sense, for debug only.

+3VALW
+5VALW
VCCSENSE and VSSSENSE need have
a 100ohm at HW Side
A A
Security Classification Compal Secret Data

RT3601EA VCC_SA
5 4 3 2 1
A
+VCC_CORE
+VCC_CORE
2 1 2 1 2 1 2 1 2 1 2 1 2 1
1
+
PC9139 PC9124 PC9114 PC9093 PC9067 PC9039 PC9009 PC9003
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D2_2V_Y
2 1 2 1 2 1 2 1 2 1 2 1 2 1
5
5
2
1
+
2 1 2 1 2 1 2 1 2 1 2 1 2 1
1
+
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC9142 PC9127 PC9117 @ PC9096 PC9070 PC9042 PC9012 PC9150

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PC9143 PC9128 PC9118 @ PC9097 PC9071 PC9043 PC9013 PC9151

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PC9144 PC9129 PC9119 PC9072 PC9044 PC9014 PC9152

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PC9145 PC9130 PC9120 PC9073 PC9045 PC9015 PC9153

2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PC9146 PC9131 PC9121 PC9074 PC9046 PC9016 PC9154

2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PC9147 PC9132 PC9122 PC9075 PC9047 PC9017 PC9155
24 X 1uF_0201
23 +10 X 22uF_0603_X5R
3 X 330uF
Total VCORE Output Capacitor:+VCC_GT
4
4
2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PC9148 PC9133 PC9123 PC9076 PC9048 PC9018 PC9156

+VCC_GT
2 1 2 1 2 1 2 1
PC9098 PC9077 PC9049 PC9019

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC9099 PC9078 PC9050 PC9020

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
@ PC9100 PC9079 PC9051 PC9021

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1
+
PC9006
2 1 2 1 2 1 2 1 220U_D2_2V_Y
@ PC9101 PC9080 PC9052 PC9022

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1
+
2 1 2 1 2 1 2 1 PC9007
220U_D2_2V_Y
@ PC9102 PC9081 PC9053 PC9023
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
@ PC9103 PC9082 PC9054 PC9024
12 X 1uF_0201
5+13 X 22uF_0603_X5R
2 X 330uF
Total VCCGT Output Capacitor:
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
3
3
2 1 2 1 2 1 2 1
@ PC9104 PC9083 PC9055 PC9025

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Issued Date
2 1 2 1 2 1 2 1
@ PC9105 PC9084 PC9056 PC9026

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
@ PC9106 PC9085 @ PC9057 PC9027

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
@ PC9107 PC9086 @ PC9058 PC9028

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
NA
Compal Secret Data
Deciphered Date
+VCC_SA
2
2
2 1 2 1
1 X 1uF_0201
4+6 X 22uF_0603
Total VCCSA Output Capacitor:
@
PC9108 PC9087
2014/07/04
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC9134 PC9109 PC9088

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@
@ PC9135 PC9110 PC9089

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@ PC9136 PC9111 PC9090

Date:
Size Document Number
Title
Custom
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

DH53F M/B LA-F991P
2 1 2 1 2 1
Tuesday, February 13, 2018
@ PC9137 PC9112 PC9091

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@ PC9138 PC9113 PC9092

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1
1
Sheet
62
of
73
R ev
1.A
D
A B C D E
@ PJ1701 +19VB_GPU
JUMP_43X79
+19VB_1.35VSDGPUP 1 2
+5VALW 1 2
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
EMI@ PC1703
0.1U_0402_25V6
1
1
EMI@ PC1702
PC1704
PC1705
2
PR1701
AON6962 2N DFN5X6D
1 1
2
2.2_0603_5%
1
RT8812_PVCC
PQ1701
Choke 1uH SH00000YE00 (Common Part)
PC1701
(Size:7.6 x 6.6 x 3 mm)
1
2.2U_0603_16V6K
2
PC1706 (DCR:6.7m~7.4m)
D1
G1
1 1.35VSDGPUP_TON_R
2 PL1701
+1.35VSDGPU
18
Frequency PU1701 1UH_11A_20%_7X7X3_M
0.1U_0402_25V6 7 1 2
PVCC
PR1702 PR1703 D2/S1
1
+19VB_1.35VSDGPUP 2.2_0402_1% 383K_0402_1%
2 1 2 1 1.35VSDGPUP_TON 9 2 HGATE1_1.35VSDGPUP
G2
S2
S2
S2
TON UGATE1
220U_D2 SX_2VY_R9M
220U_D2 SX_2VY_R9M
220U_D2 SX_2VY_R9M
PC1707 PR1704 EMI@
PR1705 PR1706 2.2_0603_1% 0.22U_0603_25V7K 4.7_1206_5% 1 1 1
6
2 1 13 1 BST1_1.35VSDGPUP 2 1 BST1_1.35VSDGPUP_R 2 1
+3VS
1 2
PGOOD BOOT1
PC1709
PC1710
PC1722
+ + +
10K_0402_5% PC1708 EMI@
<36> 1.35VSDGPU_PG 1.35VSDGPU_EN_R 3 20 LX1_1.35VSDGPUP 680P_0402_50V7K
EN PHASE1 2 2 2
2
@ PR1707 @
1 2 4 19 LGATE1_1.35VSDGPUP
+3VS PSI LGATE1
1
PR1709
10U_0805_25V6K
10U_0805_25V6K
@ PR1708 PC1711 2 1
0_0402_5% 100K_0402_5% 8.25K_0402_1%
2
<26,36> 1.35VSDGPU_EN
1
PC1712
PC1713
1 2 0.1U_0402_25V6 IOCP Common part
PR1710 5 14 HGATE2_1.35VSDGPUP
AON6962 2N DFN5X6D
SGA0000BT00
1K_0402_1% 1 VID UGATE2 PC1714
2
PR1711 2.2_0603_1% 0.22U_0603_25V7K
1.35VSDGPUP_VREF BST2_1.35VSDGPUP 1 BST2_1.35VSDGPUP_R
2 8
VREF BOOT2
15 2 2 1
2
1
@ PR1721 7 16 LX2_1.35VSDGPUP
R1 REFIN PHASE2
PQ1702
49.9_0402_1% Choke 1uH SH00000YE00 (Common Part)
PR1712
(Size:7.6 x 6.6 x 3 mm)
1
6 17 LGATE2_1.35VSDGPUP
10K_0402_1%
1 2
REFADJ LGATE2 PR1713 (DCR:6.7m~7.4m)
D1
G1
2
@ PC1721 100_0402_5% PL1702

680P_0402_50V7K 1.35VSDGPUP_VREF_SS 11 12 FB_VDDQ_SENSE_R 1 2 1UH_11A_20%_7X7X3_M
SS VSNS 7 1 2
2
D2/S1
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
1
21 10
GND RGND
G2
R2
S2
S2
S2
1
1
PC1715
PC1718
PR1714 EMI@
PC1716
1
@ 4.7_1206_5%
6
P5@ PR1722 PR1715 PC1717 RT8812AGQW-GP PR1716
2
1 2
0_0402_5%
30.9K_0402_1% 35.7K_0402_1% 47P_0402_50V8J 0_0402_5%
OPS
2
PR1717
P55@ PC1719 EMI@
2
680P_0402_50V7K
2
1
52.3K_0402_1%
2
1
68.1K_0402_1%
P5@ PR1723
PR1718
R3 The GND trace need close to

P55@
GPU pin E51 or F52.

Differential with FB_VDDQ_SENSE.
2
2
PC1015.2的GND
單單單 vi a 下下 <31> FB_VDDQ_SENSE
+1.35VSDGPUP
Vout = 1.35V
3 TDC = 16.9A 3
Peak Current = 24.2A
R1 R2 R3 Vout OCP=36.3A
3
Hynix@ Samsung@
PQ1703B
FSW=400kHz
DMN53D0LDW-7 2N SOT363-6
PR1719
2 1 5 10 35.7 NA 1.55 0.8% DaulMOS AON6992 TYP MAX
+3VALW
10 35.7 52.3 1.352 0.7% H/S Rds(on) = 6.8mohm ,8.6mohm
10K_0402_5%
4
6
L/S Rds(on) = 2.0mohm ,2.5mohm

PQ1703A
PR1720 Micron@
<26> MEM_VDD_CTL
2 1 2 10 30.9 NA 1.5 0.7%
10 30.9 68.1 1.36 0.74%
1
0_0402_5%
1
0.1U_0402_25V6
PC1720
4 4
2016/11/03
Compal Secret Data
2017/06/14 Title
VRAM
Custom 1.A
A B C D E
@ PJ1802
JUMP_43X79
1 2
+1.0VSDGPUP 1 2 +1.0VSDGPU
1 1
VIN_1.0VSDGPUP PC1801 Choke 1uH SH00000YG00 (Common Part)

22U_0603_6.3V6M
(Size:3.8 x 3.8 x 1.9 mm)
1 2 (DCR:20m~25m) Imax= 0.7A, Ipeak= 1.1A
PU1801
@ PJ1801 SY8032ABC_SOT23-6 PL1801
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.0VSDGPUP 4 3 LX_1.0VSDGPUP 1 2
+3VALW 1 2 IN LX +1.0VSDGPUP
5 2
<26> 1VSDGPU_PG PG GND Rup
PC1802
68P_0402_50V8J
PR1801 6 1 EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
1 2 FB EN PR1802
+3VALW
1
10K_0402_5% 4.7_0603_5%
PC1803
PC1804
@ PC1805
PR1804 PR1803
VFB=0.6V
2
0_0402_5% 13.7K_0402_1% Vout=0.6V* (1+Rup/Rdown)
2
2 1 1VSDGPU_EN_R
<26,36> 1VSDGPU_EN =0.6V* (1+13.7/20)
2
SNUB_1.0VSDGPUP
Vout=1.011V
1
FB_1.0VSDGPUP
PR1805 PC1806
1M_0402_1% 0.1U_0402_16V7K
Rdown
1
2
PR1806
1
EMI@ 20K_0402_1%
PC1807
2
680P_0402_50V7K
2
Note:
When design Vin=5V, please stuff snubber
2 2
to prevent Vin damage
3 3
4 4
2016/11/03
Compal Secret Data
2017/06/14 Title
1.05VSDGPU
A B C D E
5 4 3 2 1
+19VB_NVVDD <66> NVVDD_ISUMP1

<66> NVVDD_ISUMP2 NVVDD_ISUMP3 <67>
PC1201
0.1U_0402_25V6
1
1 2
0_0402_5%
PR1202
PR1203
PR1204
20K_0402_1%
20K_0402_1%
20K_0402_1%
2
0.1U_0402_25V6
PR1205
PC1202
2
layout 上 :
2
1
91K_0402_1%
請將 Tota l DC R sensin g 的 compon en t
PR1206
@ @
1
PR1201 放靠近Control
近 Control le r .
22.1K_0402_1%
PR1207 for OCP setting
1
NTC_La NTC_Lb
2
D D
PR1207
10K_0402_5% @PR1208 @PR1209
2 1 1 2 1 2 2 1 NVVDD_ISUMN1 <66>
PR1210 1_0402_1%
0_0402_5% 0_0402_5%
2 1
2
NVVDD_ISUMN2 <66>
PC1203 PC1217 1 2 PR1211 1_0402_1%
0.01U_0402_16V7K @ 0.1U_0402_25V6 @ PR1212 0_0402_5% 2 1 NVVDD_ISUMN3 <67>
1 2 1 2 PR1213 1_0402_1%
1 2
For N17E-G1, TDP 60.2W
2 1 2 1
@ PC1204 0.1U_0402_25V6
PR1214 PR1215 1 2 NVVDD1
0_0402_5% 0_0402_5%
TDC = 60A
2
1 2 2 1 @ PC1205 0.1U_0402_25V6 NTC_La NTC_Lb
PC1206 PR1216 PR1217 1 2 Peak Current = 127A
GPU_PROG5
GPU_PROG1
GPU_PROG2
PR1218 PH1201
0.015U_0402_16V7K 2.4K_0402_1% 0_0402_5% @ OCP = 165A
1 2 1 2 PC1207 0.1U_0402_10V6K 1 2
Close to PU1201
EAP 1
VINMON
@ PC1208 2 1 470K_0402_5%_B25/50 4700K
COMP
0_0402_5% 0_0402_5% 0.1U_0402_25V6 PR1219 1K_0402_1%
PR1220
2
<31> NVVDD1_VCC_SENSE
0_0402_5%
PR1221
SS
Close to PL1301
1
1 2
CSNSUM
CSPSUM
PC1209
0.1U_0402_10V6K
2
+NVVDD1
2 1 @
1
PR1222
layout 上 : 請將 RSE N1 ~ 4
100_0402_5% PR1262 放靠近 C o n t r o l l e r.
@ 0_0402_5% @ PC1212
24
23
22
21
20
19
18
17
33
1 2 1 2
0.1U_0402_25V6
PC1211
C C
LDO_VIN
MUX_CTRL
FBA
LDO_OUT
S5_OUT
VSEN_NB_IN
VDDIO
SVT
EPAD
2
0.1U_0402_25V6
2 1 25 16
PR1223 BOOT SVD
1
PR1224 @ 1K_0402_1% 26 15
GPU_PROG6
<31> NVVDD1_VSS_SENSE 0_0402_5% FBRTN UGATE SVC
1 2 27 14 PR1225 2.2K_0402_1%
GPU_PROG3 PHASE PW ROK ISEN1 2 1 GPU_PH1
2 1 28 PU1201 13 PR1226 2.2K_0402_1%
PR1228 GPU_PROG4 PVCC UP9511QQKI_WQFN32_4X4 VCC ISEN2 2 1 GPU_PH2
100_0402_5% 29 12 PR1227 2K_0402_1%
FBRTN GPU_LPC LGATE VREF_PINSET ISEN3 2 1 GPU_PH3
Fsw=300kHz
30 11 PR1264 100K_0402_5%
1 2 NVVDD1_ENP NC IMON ISEN4 2 1
+3VALW 5VCC
PR1263 31 10
PGOOD SET1
1
GPU_PSI 5VCC
30K_0402_5%
10K_0402_5%
PR1230
32 9
VRHOT_L
EN TSEN PR1231 2.2_0603_1% +5VS
ISEN1N
ISEN1P
COMP
RGND
請教 A U TO
VSEN
5VCC 2 1
6
2
VIN
33K_0402_5%
FB
PWM1
PHASE的
PHASE的設定
2
1U_0402_6.3V6K
PQ1201A
PQ1201B
PR1234
1
PC1214
<26,36> NVVDD1_EN
8
2 5
1
@ PR1232 GPU_VID
1
0_0402_5% PR1239 0_0402_5%

1 2 2 1 GPU_PWM1 <66> +5VS
PWM2
+3VS REFADJ
1
6.19K_0402_1%
PR1236
B R1 B
REFIN
@ PR1233 0_0402_5%
GPU_PROG6
2
43K_0402_5%
36K_0402_5%
100K_0402_5%
100K_0402_5%
51K_0402_5%
10K_0402_5%
2 1 PR1245 0_0402_5%
+1.8VS R3 GPU_PWM2 <66>
PR1242
PR1246
PR1243
PR1247
PR1244
PR1248
2 1
PWM3
2
PR1241
NVVDD1_PSI <26,68> @ PR1235 0_0402_5% 2 1
2 1 PR1250 0_0402_5%
1
1
2 1 GPU_PWM3 <67>
309_0402_1% 16.5K_0402_1%
4.32K_0402_1% @
PR1249
GPU_PROG1
GPU_PROG2
GPU_PROG3
GPU_PROG4
GPU_PROG5
1 2
R4
GPU_LPC
@
PR1237 0_0402_5%
2
PR1238
100K_0402_5%
1
+3VS 1 2
PR1256
R5
0_0402_5%
8.2K_0402_5%
8.2K_0402_5%
0_0402_5%
PR1251
PR1252
PR1255
PR1257
<26,36> NVVDD1_PG R2PR1258
2
2 1
1
4700P_0402_50V7K
20.5K_0402_1% @
1
1
PC1215
@
0.01U_0402_16V
@
PR1240 C
2
2
PC1216
1 2
<26> NVVDD1_VID
1
0_0402_5%
FBRTN
A A
Cold Boot = 4-phase

Warm Boot = 4-phase
PWMVID 的 RC BOM
請根據GPU's
據 GPU's config Security Classification Compal Secret Data Compal Electronics, Inc.
設定 Issued Date 2016/11/03 Deciphered Date 2017/01/06 Title
PWR_VGA_UP9511P
5 4 3 2 1
1 2 3 4 5
+19VB +19VB_GPU
EMI@ PL1303
PR1301 PR1302
FBMA-L11-201209-800LMA50T
1 2 1 4 1 4 +19VB_NVVDD
EMI@ PL1304 2 3 2 3
FBMA-L11-201209-800LMA50T
NVVDD (NVVDD1)
1 2
0.005_1206_1% 0.005_1206_1%
Vboot=0.8V
TDC=60A
Peak Current=127A
A
OCP=165A A
+5VS
FSW=300kHz
Dr.MOS SIC632 TYP MAX
0_0402_5%
@ PR1303
<36> CSSP_B+ <36> CSSN_B+ CSSP_NVVDD <36><36> CSSN_NVVDD H/S Rds(on) = 4.8mohm ,5.76mohm
+5VS L/S Rds(on) = 1.3mohm ,1.56mohm
1
PR1304
10K_0402_1%
PR1305 PU1301 1 2
1K_0402_1% 1 28
<65> GPU_PWM1 2 1 2 PW M CGND 27
+5VS 3 ZCD_EN# GL 26 PR1307
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
CGND THW n
@ PR1306
5 24 2 1
6 BOOT VDRV 23
PR1308 NC PGND Choke 0.22uH SH00000QZ00
1
1U_0603_16V7
PC1302
7 22
PHASE GL
1
1U_0603_16V7
PC1304
1 2 8 21
1
9 VIN SW 20 GPU_PH1
2
PC1303 10 VIN SW 19 PL1301
2
0_0402_5% 1 2 11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +NVVDD1
+19VB_NVVDD 12 SW SW 17 GPU_PH1 1 4
0.1U_0603_25V7K 13 SW SW 16
14 SW SW 15 2 3
SW SW
SIC632CDT1GE3_POWERPAK31_5X5
PC1306
PC1307
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
10U_0805_25VAK
10U_0805_25VAK
1
1
PC1308
PC1309
PC1310
PC1311
B EMI@ B
1
PC1327
PC1326
PR1309
4.7_1206_5%
2
2
@EMI@
EMI@
2
<65> NVVDD_ISUMP1
2
@
GPU_SNB1
<65> NVVDD_ISUMN1
1
EMI@
PC1312
680P_0402_50V7K
2
+5VS
2
@ PR1310
0_0402_5%
+5VS
1
PR1311
PR1312 PU1302 1 2
C C
1K_0402_1% 1 28
<65> GPU_PWM2 2 1 2 PW M CGND 27 10K_0402_1%
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
CGND THW n
@ PR1313
5 24 2 1
PR1315 BOOT VDRV
6 23 Choke 0.36uH SH00000R500
NC PGND
1
1U_0603_16V7
PC1313
1 2 7 22
PHASE GL (Size:13.5 x 12.5 x 2.8 mm)
1
1U_0603_16V7
PC1315
8 21
1
PC1314 9 VIN SW 20 GPU_PH2 (DCR:1.5m~1.8m)

2
0_0402_5% 1 2 10 VIN SW 19 PL1302
2
11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +NVVDD1
+19VB_NVVDD 0.1U_0603_25V7K 12 SW SW 17 GPU_PH2 1 4
13 SW SW 16
14 SW SW 15 2 3
SW SW
1
SIC632CDT1GE3_POWERPAK31_5X5 EMI@
PC1318
PC1319
2200P_0402_50V7K
PR1316
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
4.7_1206_5%
1
1
PC1322
PC1323
<65> NVVDD_ISUMP2
2
2
GPU_SNB2
@EMI@
EMI@
1
EMI@
PC1324
680P_0402_50V7K
2
<65> NVVDD_ISUMN2
D D

PWR_+NVVDD1
1 2 3 4 5
5 4 3 2 1
+5VS
D D
2
@ PR1351
0_0402_5%
1 +5VS
PR1352
10K_0402_1%
PR1353 PU1351 1 2
1K_0402_1% 1 28
<65> GPU_PWM3 2 1 2 PW M CGND 27
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
CGND THW n
@ PR1354
5 24 2 1
PR1356 BOOT VDRV
6 23
NC PGND
1
1U_0603_16V7
PC1352
1 2 7 22
PHASE GL
1
1U_0603_16V7
PC1354
8 21
1
PC1353 9 VIN SW 20 GPU_PH3

2
0_0402_5% 1 2 10 VIN SW 19 PL1351
2
11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +NVVDD1
+19VB_NVVDD 0.1U_0603_25V7K 12 SW SW 17 GPU_PH3 1 4
13 SW SW 16
14 SW SW 15 2 3
SW SW
SIC632CDT1GE3_POWERPAK31_5X5
PC1356
PC1357
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
1
EMI@
1
1
PC1358
PC1359
PC1360
PC1361
PR1357
4.7_1206_5%
C C
2
2
@EMI@
EMI@
2
@ @ <65> NVVDD_ISUMP3
GPU_SNB3
1
EMI@ <65> NVVDD_ISUMN3
PC1362
680P_0402_50V7K
2
B B
A A

PWR_+NVVDD1
5 4 3 2 1
1 2 3 4 5
A A
1 2
+3VS +5VS
4.7U_0402_6.3V6M
PR1401 1
2.2_0603_1%
PC1401
2
@ PR1430 2 +19VB_GPU
2
30K_0402_5%
@ PR1431
NVVDDS_LG1 PR1402
30K_0402_1%
1
1 4 +19VB_NVVDDS
PR1404 NVVDDS_SW1
1
100K_0402_1% 2 3
2 1 PC1408
1
0.22U_0603_25V7K PU1401 RT@
RT8816AGQW_WQFN20_3X3 0.005_1206_1%
2 2
+3VS
21
20
19
18
17
16
UPI@
PR1405 PU1401
PHASE1
LGATE1
LGATE2
PHASE2
TPAD
PVCC
2.2_0603_1% UP1666QQKF_WQFN20_3X3
<26,36> NVVDD2_EN
2
+1.8VS <36> CSSP_NVVDDS <36> CSSN_NVVDDS
PR1407
1
NVVDDS_BST1 1 15
BOOT1 BOOT2 10K_0402_5%
1
0.1U_0402_25V6
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
2200P_0402_50V7K
PR1406 NVVDDS_HG1 2 14
@EMI@ PC1404
EMI@ PC1405
1
1
20K_0402_1% UGATE1 UGATE2
PC1406
PC1407
PC1416
PC1417
GND
NVVDD2_EN 3 13 NVVDD2_PG <26,36>
PR1409 EN PGOOD UPI@ PR1410 UPI@ PC1409
2
2
1 2 NVVDD2_PSI_R 4 12 NVVDDS_COMP
2 1 2 1
PR1411 PSI COMP
6,65> NVVDD1_PSI
2
@ 1 2 5 11 51.1K_0402_1% 1000P_0402_25V8J
10K_0402_1%
0_0402_5% VID FB PR1427

PR1412
NVVDDS_HG1
REFADJ
OCS/CB
2 1 1 2
FBRTN
<26> NVVDD2_VID
REFIN
0_0402_5%
VREF
Avoid high dV/dt RT@ PR1432 93.1K_0402_1%
1
0_0603_5% @
PIN12
2
B PQ1401 PQ1402 B
10
RT:93.1K OCP=37A
G1
D1
G1
D1
+NVVDD2
OCP=[[(10uA*93.1k)/12/2.5m]+(12A/2)]*1phase=37A
AON6962_DFN5X6D-8-7
AON6962_DFN5X6D-8-7
NVVDDS_VREF
NVVDDS_SW1 7 7
D2/S1 D2/S1
2
NVVDDS_VIDBUF
PR1413 @ Choke 0.22uH SH000011H00
49.9_0603_1%
G2
G2
S2
S2
S2
S2
S2
S2
(Size:7*7*4 mm)
2
@
PR1414 DCR 0.97
2 1
3
0_0402_5%
PL1401
R1 R3 R4
1
PC1412 @ 1 2
1500P_0402_50V7K
1
PR1415
PR1417
47P_0402_50V8J
6.19K_0402_1%
4.32K_0402_1%
16.5K_0402_1%
1
1
1 2 NVVDDS_LG1
PR1416
+19VB_NVVDD 0.22UH_24A_+-20%_7X7X4_M
PC1413
2
UPI@ PR1418
2
45.3K_0402_1% PR1429
1
100K_0402_5% EMI@
1
1
@ @ RT@ @ PR1408
RT@ PR1420 PR1421 PR1433
R5 4.7_1206_5%
1
PR1434 0_0402_5% 0_0402_5% 2.2_0805_5%
1
432K_0402_1%
309_0402_1%
2
PR1422
2
NVVDDS_SNB1
RT@ PC1418
1
1
1U_0603_25V6K PR1423 100_0402_5% EMI@
2
2 1 +NVVDD2 PC1411
R2 680P_0402_50V7K
2
2
OCP & FS setting
2 1 NVVDD2_VCC_SENSE <31>
PR1424 20.5K_0402_1% Avoid high dV/dt
C
4700P_0402_50V7K
NVVDD2_VSS_SENSE <31>
1
PC1415 PR1425 100_0402_5%

PC1414
NVVDDS (NVVDD2)
1
0.01U_0402_16V 2 1
2
C
Vboot=0.8V C
TDC=18A
Close to PU1201 Peak Current=30.7A
PIN9 OCP=37A
UPI:OCP & FS setting FSW=350kHz
RT:Switching frequency setting:(Ton pin) DaulMOS AON6962 TYP MAX
Fsw=(Vin-0.5)/(2*Vin*432K*3.2p) H/S Rds(on) = 6.8mohm ,8.6mohm
=352Khz L/S Rds(on) = 2.0mohm ,2.5mohm
D D

PWR_+NVVDD2
1 2 3 4 5
D
1.A
22uF_0603 X 2 (unpop 2)
22uF_0603 X 4 (unpop 2)
Rev
4.7uF_0603 X 2
47uF_0805 X 1
22uF_0603 X 2
10uF_0603 X 4
1uF_0402 X 16
73
220uF X 2
560uF X 1
of
+NVVDD2
PWR_VGA DECOUPLING
69
47uF_0805 X 1
10uF_0603 X 4
1uF_0402 X 16
10uF_0603 X 4
1uF_0402 X 16
DH53F M/B LA-F991P

Sheet
220uF X 2
220uF X 2
560uF X 1
560uF X 1
1
1
+NVVDD2
+NVVDD2
PC1609
1U_0402_6.3V6K
Tuesday, February 13, 2018
1 2 PC1629
PC1608 22U_0603_6.3V6M
1U_0402_6.3V6K
1 2
Document Number
1 2 PC1625
PC1607 PC1616 22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K
1 2
1 2 1 2
PC1606 PC1615 PC1624
1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6M
@
1 2 1 2 1 2
Date:
Title
Size
PC1605 PC1614 PC1623

1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6M
@
1 2 1 2 1 2
PC1604 PC1613 PC1622
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
220U_D2 SX_2VY_R9M 1 2 1 2 1 2
PC1626
PC1603 PC1612 PC1621
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M

+
1
1 2 1 2 1 2
2017/01/06
220U_D2 SX_2VY_R9M
PC1602 PC1611 PC1620
PC1627
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2
2
+
1
2
SGA0000BT00
Common part
1 2 1 2 1 2
220U_D2 SX_2VY_R9M
PC1601 PC1610 PC1619
PC1628
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
+
1
1 2 1 2 1 2
+NVVDD2
+NVVDD2
Deciphered Date
Compal Secret Data
10uF_0603X 11(unpop 5)
10uF_0603X 11(unpop 5)
4.7uF_0603 X 9
47uF_0805 X 2
22uF_0603 X 4
10uF_0603X 23
1uF_0402 X 49
47uF_0805 X 2
22uF_0603 X 4
1uF_0402 X 49
22uF_0603 X 8
1uF_0402 X 49
2016/11/03
220uF X 4
560uF X 3
220uF X 4
560uF X 3
220uF X 4
330uF X 2
560uF X 1
+NVVDD1
+NVVDD1
+NVVDD1
3
3
Issued Date
PC1515 PC1530 PC1543 PC1575
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1 2 1 2 1 2 22U_0603_6.3V6M 1 2
PC1557
PC1514 PC1529 PC1545 PC1574
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1
1 2 1 2 1 2 22U_0603_6.3V6M 1 2
PC1556
PC1513 PC1528 PC1544 PC1573
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1 2
1 2 1 2 1 2 1 2
PC1512 PC1527 PC1542 PC1572
22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
PC1547
1 2 1 2 1 2 1 2
PC1511 PC1526 PC1541 2 1 PC1571
22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
PC1555
1 2 1 2 1 2 1 2
PC1510 PC1525 PC1540 2 1 PC1570
220U_D2 SX_2VY_R9M 22U_0603_6.3V6M
SF-OS CON Cap Common
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M

4
4
PC1592 PC1554
1 2 1 2 1 2 1 2
+
1
PC1509 PC1524 PC1539 2 1 PC1569

22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
PC1553
1 2 1 2 1 2 1 2
PC1508 PC1523 PC1538 2 1 PC1568
330U_2.5V_ESR17M_6.3X4.5 22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
PC1552
SF000006S00
PC1593
1 2 1 2 1 2 1 2
PC1507 PC1522 PC1537 2 1 PC1567
+
1
22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
330U_2.5V_ESR17M_6.3X4.5 PC1546
PC1594 1 2 1 2 1 2 1 2
PC1506 PC1521 PC1536 1 2 PC1566
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
+
1
1 2 1 2 1 2 1 2
PC1505 PC1520 PC1535 PC1565 PC1580
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1504 PC1519 PC1534 PC1551 PC1579
PC1591
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
+
1
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1503 PC1518 PC1533 PC1550 PC1578
SGA0000BT00
Common part
PC1590
+
1
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1502 PC1517 PC1532 PC1549 PC1577
PC1589
5
5
+
1
2
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1501 PC1516 PC1531 PC1548 PC1576
PC1588
+ 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1
2
1 2 1 2 1 2 1 2 1 2
@
+NVVDD1
+NVVDD1
D
A
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2 for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
PQ311,PQ312: AON6366E 1N DFN5X6-8SB00001D800->AON7380_DFN3X3-8-5SB00001GM00

PC302,PC303,PC310,PC311,PC312: 10U_0603_25V6MSE00000X200->10U_0805_25V6KSE00000QK00
D
PC323: 10U_0603_25V6MSE00000X200->Del D
Down Size PC315,PC1312,PC1324,PC1362,PC1411: 680P_0603_50V7KSE025681K80->680P_0402_50V7KSE074681K80

10/26 A
01 0.1 PC412,PC426,PC602,PC7203,PC8311: 680P_0603_50V7KSE025681K80->680P_0402_50V7KSE074681K80Unpop
PC102: 100P 50V J NPO 0603SE024101J80->100P 50V J NPO 0402SE071101J80
PC104: 1000P 50V K X7R 0603SE025102K80->1000P 50V K X7R 0402SE074102K80
PQ1401: AON6962_DFN5X6D-8-7SB00001ID00->Unpop
PR1301,PR1302,PR1402: 0.005_2512_1%SD000016U00->0.005_1206_1%SD000017R00
PC1410: 0.1U_0603_16VSE026104K80->Del
PR1432: Add->93.1K_0402_1%SD034931280
02 PR1410: 51.1K_0402_1%SD034511280->un pop
PC1409: 1000P_0402_25V8JSE068102J80->un pop
Down Size & NVVDDS IC COLAY 0.1 PU1401: UP1666QQKF_WQFN20_3X3SA00009SX00 -> RT8816AGQW_WQFN20_3X3 SA00009WE00
PR1414: 10K_0402_5%SD028100280->0_0402_5%SD028000080 10/26 A
PR1418: 45.3K_0402_1%SD034453280->un pop
PR1419: 84.5K_0402_1%SD034845280->Del
PR1433: Add->2.2_0805_5%SD002220B80
PC1418: Add->1U_0603_25V6KSE000006900
PR1434: Add->432K_0402_1%SD034432380
C PC8134: 0.1U_0402_50V7KSE074104K80->0.1U_0402_25V6SE00000G880 C
PU501 _RT8207PGQW_WQFN20_3X3 _-> _RT8207PGQW_WQFN20_3X3-S

PH8103,PH8104_150K_0402_5%_B25/50 4500K_SL200002K00_->_S THERM_ 220K +-5% 0402 B25/50 4700K_SL200002I00
PR8110, PR8109 _8.87K_0402_1%_SD034887180_->_8.66K_0402_1%_SD034866180
03 PR8118, PR8119 _93.1K_0402_1%_SD034931280_->_57.6K_0402_1%_SD034576280
PC8113,PC8124,PC8140,PC8159,PC8163 _0.47U_0402_16V4Z_SE000002F80_->_0.47U_0402_6.3V6K_SE124474K80
PC8310 _0.47U_0402_25V6K_SE00000WA00_->_0.47U_0402_6.3V6K_SE124474K80
PR8114 _6.81K_0402_1%_SD034681180_->_5.76K_0402_1%_SD034576180
PR8113 _2.49K_0402_1%_SD034249180_->_1.8K_0402_1%_SD00000R580
PR8117 _560K_0402_1%_SD034560380_->_442K_0402_1%_SD034442300
PR8116 _510K_0402_1%_SD00000RK80_->_402K_0402_1% _SD034402380
PR8141 _100_0402_1%_SD034100080_->_8.2K_0402_1%_SD000004100
PR8149 _1.05K_0402_1%_SD00000J480_->_3.16K_0402_1%_SD000006580
PR8176 _20K_0402_1%_SD034200280_->_16.9K_0402_1%_SD034169280
CPU TEST 0.1 PR8310 _63.4K_0402_1%_SD03463K280_->_59K_0402_1%_SD034590280
PR8319 _24.9K_0402_1%_SD034249280_->_22K_0402_1%_SD034220280
PR8325 _0_0402_5%_SD028000080_->_300_0402_1%_SD034300080
PR8328 _22K_0402_1%_SD034220280_->_20K_0402_1%_SD034200280 10/26 A
PR8333 _680_0402_1%_SD034680080_->_300_0402_1%_SD034300080
B PC8312_270P_0402_50V7K_SE074271K80_->_330P_0402_50V8J_SE000006I80 B
PR8331 _470_0603_1%_SD014470080_->_576_0603_1%_SD014576080
PR8336 _42.2_0402_1%_SD00000ZN00_->_255_0402_1% _SD034255080
PC9110 PC9108 _22U_0603_6.3V6M_SE00000M000_->_unpop
PC9112 PC9113_unpop _->_22U_0603_6.3V6M_SE00000M000
PC8126,PC8137 _330P_0402_25V8J_SE00000FD80_->_330P_0402_50V8J_SE000006I80
PR8134 _121K_0402_1%_SD034121380_->_13.3K_0402_1%_SD034133280
PR8138 _49.9K_0402_1%_SD034499280_->_26.7K_0402_1%_SD034267280
PR8147 _3.32K_0402_1%_SD034332180_->_768_0402_1% _SD00000TT80
PR8173 _0_0603_5%_SD013000080_->_10_0603_1%_SD014100A80
PU1201 _UP9511PQGJ_VQFN40_5X5_SA00009SW00_->_UPI9511QQKI WQFN 32P _SA0000BK300
down size &CHANGE VGA IC PC8317,PC509,PC517_1U_0402_10V6K_SE00000QL10_->_1U 6.3V K X5R 0201_SE00000YB00 11/08 A
04 0.2
PC8112,PC8115,PC8123,PC8139,PC8157,PC8161_1U_0402_25V6K_SE000010V00_->_1U 6.3V K X5R 0201_SE00000YB00
PQ307_ LMUN5113T1G PNP SOT323-3_SB000013X00_->_Unpop
Unpop reduce charger IC loss extra circuit. PQ308 _ LMUN5236T1G NPN SOT323-3_SB000011K00_->_Unpop
Unpop GPIO12& PROCHOT synchronous 0.2 PQ313 _2N7002KDW 2N SOT-363-6_SB00000EO00_->_Unpop
05 11/15 A
circuit. PQ314_RUM001L02 1N VMT3_SB000012900_->_Unpop
PR340 _10K_0402_1%_SD034100280_->_Unpop
A
PR327 _0_0603_5%_SD013000080_->_Unpop A
PR326 _0_0603_5%_SD013000080_->_SMT
PR310 _51.1K_0402_1%_SD034511280_->_52.3K_0402_1%_SD034523280
PC1709 _220U_D2 SX_2VY_R9M _SGA0000BT00_->_Unpop
PC8147 _10U_0805_25V6K_SE00000QK00_->_Unpop
2016/11/03
Compal Secret Data
2017/06/14 Title
PIR
Custom 1.A
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 2 of 2 for PWR
Item Fixed Issue Rev. PG# Modify List Date Phase

PR326,PR304,PR314,PR316,PR317,PR322,PR333,PR334,PR8111,PR8120,PR8128,PR8129,PR8139,PR8142,
01 PR8143,PR8153,PR8154,PR8155,PR8163,PR8165,PR8170,PR8175,PR8184,PR8190,PR8198,PR8204,PR8308,
0ohm ->R-Short 1.0 PR8339,PR8341,PR8342,PR8346,PR8326,PR1414_SD028000080 chage to _R-Short 0402
D 12/17 A.2 D
PR326 0_0603_5%_SD013000080 ->R-Short 0603_SD013000080
PC313,PC314_1U_0402_16V6K_SE00000OU00_->_1U 6.3V K X5R 0201_SE00000YB00
PC1303,PC1314,PC1353,PC8101,PC8122,PC8135,PC8150,PC8158
02 material shortage 1.0 _0.1U_0603_50V7K_SE025104K80_->_0.1U 25V K X7R 0603_SE042104K80 12/17 A.2
PC305,PC324 _0.1U_0402_25V7K_SE00000W210_->_0.1U_0402_25V6_SE00000G880
PR217 0_0402_5%_SD028000080(unpop) -> SMT 0402_SD028000080 12/17 A.2

Acer SW2 design reserve 1.0
PQ307 _LMUN5113T1G_SOT323-3_SB000013X00_->del
03 PR327unpop_0_0603_5%_SD013000080_->del
1.0 PR342Add _->_2M_0402_1%_SD034200480 12/20 A.2
For 4S per cell 4.35V battery
PR343Add _100K_0402_1%_SD034100380
PQ315Add _2N7002KW_SOT323-3_SB00000ST00
charger boost cap to 0.47uF PC309 _0.22U_0603_25V7K_SE000005Z80_->_0.47U_0402_16V4Z_SE000002F80

but material shortage so down size. 1.0
04 12/21 A.2
C C
ACDET change PR306 _392K_0402_1%_SD034392380_->_499K_0402_1%_SD034499380

05 1.0 PR310 _52.3K_0402_1%_SD034523280_->_66.5K_0402_1%_SD034665280 12/28 A.2
B B
A A
2016/11/03
Compal Secret Data
2017/06/14 Title
PIR
Custom 1.A
5 4 3 2 1
A B C D E
Version change list (P.I.R. List) Page 1 of 2 for HW
Item Page Title Date Issue Description Solution Description Phase Rev.
1 46 USB 10/18 Correct USB charger connection. 1.Change RS15 connection to CHG_ILMSEL. DVT 0.2
1.Remove RPH10, add RH197,RH198.
1
2 19,36 Placement 10/18 Placement 2.UG27 source change to +1.8VALW for +1.8VSDGPU_AON/+1.8VSDGPU_MAIN. DVT 0.2 1
3 41 CNVI 10/18 For CNVI power rail. 1.Co-lay RM46 for CNVI +3VALW power rail. DVT 0.2
4 42 Material 10/18 X1 code issue. 1.LA1 change to SM01000NS00. DVT 0.2
5 48 USB 10/18 redriver verify. 1.Add one USB3.0 port to JIO3. DVT 0.2
1. Change RM36,RM37,RM42,RM43 to 0402 size.
2. Change RH186,RH47,RH98~RH100,RH103,RH105,RD2,RD3,RD6,RD13,RD15,RD17,RM34,RM35
6 Placement 10/21 Placement ,RM38,RM39,RS1,R19,R20,RQ5,RQ6,RQ9 to R-short. DVT 0.2
3. Change RS8,RS10 to 1206 R-short.
4. Change RH97 to 0805 R-short.
7 11 ESD cap. 10/21 Sourcer request. 1.Change CC66,CC68 to SE074102K80. DVT 0.2
8 43 EC 10/21 EC board ID. 1.Change RB3 to 12kohm/28P@ and 160kohm/32P@ DVT 0.2
2 1. Change CA6,CA8,CA9,CA12,CA14,CA16,CA19,CC71~CC81,CC88~CC90,CG130,CG131 2
9 Cap. 10/24 Sourcer request. ,CG143~CG145,CG168,CG169,CG178~CG181,CG193,CG205~CG207,CG229,CG230,CG241,CG243 DVT 0.2

,CG253~CG255,CG267~CG269,CG291,CG292,CG303~CG305,CX1,CX3 from 0402 to 0603 size.
10 50 Screw hole 10/25 Screw hole 1.Change H21 footprint to H_6P0. DVT 0.2
11 48 USB EMI 10/25 EMI issue. 1.Add LS11,LS12. DVT 0.2
12 41,43 CNVI 10/26 For CNVI power rail detect. 1.Add net CNVI_DET#,RB78,RB79. DVT 0.2
13 46 USB 10/26 Correct USB charger connection. 1.Correct USB2.0 connection for US12. DVT 0.2
14 42 DMIC 10/26 Acer request. 1.Change JDMIC1 from 8pin to 4pin. DVT 0.2
15 47 SATA 11/03 Co-layout. 1.Co-lay JHDD3,CO14~CO17,RO21~EO24. DVT 0.2
16 44 SMBus 11/08 Co-layout. 1.Co-lay RS114,RS115. DVT 0.2
3 3
17 49 SW 11/14 Remove debug SW. 1.De-pop SW1. DVT 0.2
18 44 Type-C 11/14 CC logic control by EC SMBus. 1.De-pop QS1,QS3,RS107,RS108,RS111. Pop RS114,RS115. DVT 0.2
19 16 Cap. 11/14 by crystal vendor test result. 1.Change CH7,CH8 to 10pF. DVT 0.2
20 45 Cap. 11/16 For shortage. 1.Change CS84~CS87 to SE00000G880. DVT 0.2
21 43 CNVI 11/16 CNVI detect by SW. 1.De-pop RB78. Pop RB79. DVT 0.2
22 43 CNVI 12/15 Remove CNVI detect. 1.Remove RB78, RB79 and netname CNVI_DET#. PVT 1.0
23 18 PECI 12/15 For PECI issue. 1.De-pop RH41. PVT 1.0
24 50 BI SW 12/15 By customer request. 1.De-pop SW2. PVT 1.0
25 43 EC 12/15 Update EC board ID. 1.Change RB3 to 15kohm/28P@ and 200kohm/32P@ PVT 1.0
4 4
26 42 Inductor 12/15 Change source. 1.Change LA1 to SM01000EE00. PVT 1.0

27 NPI 12/15 For NPI test. 1.Change RB19,RC17,RG143,RG200,RG202,RH101,RH102,RH5,RH6,RH92,RH93,RH94,RH96 PVT 1.0
,RM2,RS114,RS115,RB72,RB76,RL1,RL13,RQ2 to R-short.
PIR-HW1
A B C D E
A B C D E
Version change list (P.I.R. List) Page 2 of 2 for HW
Item Page Title Date Issue Description Solution Description Phase Rev.
28 44 Type-C 12/18 Change current limit solution 1.Change US2 to SA00006Y700. PVT 1.0
2.Add RS116,RS117,RS118. Reserve CS101.
1 29 43 EC 12/20 For PWR BATT_4S 1.Add net BATT_4S to EC pin89. PVT 1.0 1
30 41 WLAN 12/20 For CNVi BT_ON 1.Add RM47. PVT 1.0

31 21 PCH 12/20 For intel sensitive net 1.Pop CH29,CH34,CS100. PVT 1.0
32 45 Type-C 12/21 For intel new topology 1.Change RS64,RS65,RS74,RS76,RS82~RS85 to 0201 size.
2.Add CS102~CS105,RS119~RS122. PVT 1.0
33 36 GPU 12/21 Fine tune GPU sequence 1.Change CG315 to 0.22uF, RG190 to 16.9k ohm, add RG225. PVT 1.0
34 20 12/28 For MB ID 1.De-pop RH86. Pop RH85,RH87. PVT 1.0
35 7,15 CPU,PCH 12/28 Update intel chip to QS PN 1.SA0000BPJ10 for i5@, SA0000BPI10 for i7@, SA0000BPF10 for PCH@. PVT 1.0
36 7 DAZ 12/28 Update MB DAZ PN. 1.DAZ29000100 for PCB@. PVT 1.0
37 37 eDP 12/28 For eDP sequence 1.Pop RX1. PVT 1.0
2 2
38 18,39 PCIE 01/11 For IRST support issue. 1.Change PCIE port17~20 to port 9~12 for PCIE SSD. PVT 1.C
2.Change SATA port0A to port4 for SATA HDD.
3.Change SSD_DEVSLP4 to SSD_DEVSLP1.
4.Change SATA_GP4 to SATA_GP1.
39 45 Type-C 01/11 For intel new topology 1.Place CS58~CS61 close to connector and change net name. PVT 1.C
40 43 EC 01/11 Update EC board ID. 1.Change RB3 to 20kohm/28P@ and 240kohm/32P@ PVT 1.C
41 21 PCH 01/12 For layout routing. 1.Change RH93 to 0ohm footprint. PVT 1.C
42 45 Type-C 01/16 For intel new topology 1.Change CS58~CS61 to 0.22uF. PVT 1.C
43 7 CPU,DAZ 01/27 Update CPU,DAZ PN 1.SA0000BPZ10 for i7@, DAZ29000103 for PCB@. PVT 1.C
44 7,15 CPU,PCH 02/13 Update CPU,PCH PN to MP PN. 1.SA0000BPJ40 for i5@,SA0000BPZ40 for i7@,SA0000BVP10 for PCH@. Pre-MP 1.C
3 3
4 4

PIR-HW2
A B C D E

Acer Predator Helios 300 N17C3 Compal LA-F991P DH53F Rev 1.C Схема

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Acer Predator Helios 300 N17C3 Compal LA-F991P DH53F Rev 1.C Схема

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A B C D E

DH53F MB Schematic Document

HDMI Conn. eDP

2 X4 DMI USB 3.0 USB 3.0 x2 CMOS 2

48MHz page 46 page 44,45 page 37

Card Reader RJ45 conn. SATA HDD Conn. HDA Codec

page 32. ENE

DC/DC Interface CKT.

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID Table for AD channel Power State BOARD ID Table

W/ SATA re-driver SATARD@

X76730BOL56 ALT. GROUP PARTS N17E6G SAM 256M32 DH7VF

US11 +USB3_VCCC JTYPEC1

JIO2,3 RF6 +VCC_FAN2 FAN2

DH53F_EVT Power Sequence

→ 20.16ms → 4.993us SYSON

Security Classification Compal Secret Data Compal Electronics, Inc.

KB9022 0 ohm EC_SMB_CK1_CHGR 2.2K

Security Classification Compal Secret Data Compal Electronics, Inc.

CO-LAY FOR VGA OUTPUT

RG203 1 DIS@ 2 0_0201_5% GPU_EDP_TXP0_R

RG211 1 DIS@ 2 0_0201_5% GPU_EDP_AUXP_R

K36 D29 EDP_TXP0

PCB@ DAZ29000103 F26

Coffee Lake-H CPU SKU

<24> DDR_B_D[0..63] DDR CHANNEL B

RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

PEG Lane Reversed CFL-H

PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

@ESD@ RC77 2 CMC@ 1 51_0402_5% CPU_XDP_TDI

RC13 1 2 220_0402_5% CPU_SVID_ALERT#

+VCC_SA CFL-H +1.2V_VDDQ_CPU +1.2V_VDDQ_CPU +1.2V_VDDQ +1.2V_VDDQ_CPU

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

The 30 HSIO lanes on PCH-H supports the following configurations:

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H

remove TP as C5PRH UH1G

AW13 BD4 CLK_CNV_PRX_DTX_N

An external pull-up or pull-down is required.

SPI ROM ( 16MByte )

PCH_SPI_SI_0_R RH107 1 2 49.9_0402_1% PCH_SPI_SI

RH56 2 1 8.2K_0402_5% PM_BATLOW #

RH57 2 @ 1 100K_0402_5% AC_PRESENT_R

100K_0402_5% 1 @ 2 RH184 SYS_PW ROK

1 2 D_CK_SDATA 100P_0402_50V8J 1 2 CH50 EC_RSMRST#

RH114 1 2 150K_0402_1% VGA_ID1 RH84 1 @ 2 1K_0402_5% PROJECT_ID0 RH88 1 SATARD@

+3VS RH87 1 2 10K_0402_5% RH91 1 2 10K_0402_5%

RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP

GPIO Group Voltage

1 W20 Short pins AJ22,AJ23,AK22,AK23 together

1 1 AJ22 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71

0.0198A C1 AJ23 Internal LDO RH96 1 @ 2 0_0402_5%

+3VALW +3VALW_PCH_PRIM +3VALW_PCH_PRIM +3VALW_SPI

+1.05VALW_VCCAZPLL 0_0402_5% 2 @ 1 RH101

2 2 DH2 +RTCVCC +RTCBATT

2 Issued Date 2017/07/20 Deciphered Date 2018/07/20 Title

CHANNEL-A BOT REVERSE TYPE

Interleaved Memory <8> DDR_A_CLK1 138 20

STRETCH GOAL IS 2133 MT/S 27

1 1 1 1 1 1 1 60 214 104 204

DIMM Side CPU Side

330uF*1 +1.2V_VDDQ CD14 CD15

Security Classification Compal Secret Data Compal Electronics, Inc.

CHANNEL-B BOT REVERSE TYPE (8 mm)

118 148 24 DDR_B_D14