Acer Aspire 5553 Zr8 Zr8a

1 2 3 4 5 6 7 8
PCB STACK UP
SGN@---->Internal CLK GEN.
GN@ ---->External CLK GEN.
IV@ -----> iGPU
ZR8 SYSTEM DIAGRAM RAMP
LAYER 1 : TOP SW@ -----> dGPU
DDR3-SODIMM1 DDR3 channel A
SP@ -----> iGPU & dGPU notice CPU THERMAL
LAYER 2 : GND AMD Champlain
SPE@ ----->Only for dGPU notice
LAYER 3 : IN1 SIDE@ ----> Side port
P5
35mm X 35mm
SENSOR
A LAYER 4 : IN2 S1G4 Processor P4
A
DDR3-SODIMM2 DDR3 channel B

LAYER 5 : VCC
638P (PGA)45W/35W
LAYER 6 : IN3 P6 P2 ~ 4 CPU_CLK
LAYER 7 : GND NBGFX_CLK CLOCK GEN
LAYER 8 : BOT NBGPP_CLK From SB
SBLINK_CLK P11
HT3
l
PCI-Express 16X ATI
PCI-E HDMI HDMI
Madison LP
tia
P25
128-bit M2 Pkg
NORTH BRIDGE 29mm X 29mm
CRT
SIDE port CRT
Mini PCI-E
MUXs P24
LAN RS880
Atheros Card (S.G)
P16 ~ 20 LVDS
PCIE-LAN A12 P7 LVDS
AR8151 (Wireless LAN) DDR3 800MHz P24
B 21mm X 21mm, 528pin BGA P24 B
(10/100/1000)
VRAM
P26 P27 CRT
64MX16X4,64 bit
LVDS
P7 ~ 10 64MX16X8,128 bit
en
P22,23
RJ45
ALINK X4
P26
SATA0 150MB
Charger (ISL88731A) SATA - HDD1 BT
P35 P28 SOUTH BRIDGE P31
SATA1 150MB SB820

DC/DC ( 3VPCU / 5VPCU ) SATA - ODD
id
RT8206B P36 P28 21mm X 21mm, 528pin BGA USB1.1
4.5W(Ext)
C CPU_VCORE ( VCORE ) 4.3W(Int) USB2.0 C
ISL6265A P37
USB2.0 Ports Webcam

DC/DC ( +1.1V_S5 ) P11 ~ 14 CardReader
X1 P31 P24
UP6111AQD
DC/DC ( NB_CORE )
P38
nf LPC Azalia
AU6433/AU6437
P30
UP6111AQD P39
Winbond KBC Codec USB BOARD

DC/DC ( +1.5VSUS ) RTL ALC271X
NPCE781L USB2.0 Ports x 3
RT8207A P40
P31
P29
Co
P34
DC/DC ( GPU_CORE )
MAX8792ETD+T P41
D
DC/DC (+1.8V/+1V/+2.5V ) D
HPA00835RTER / RT9018A / RT9025-25PSP P42

FAN SPI Digital MIC AUDIO CONN Speaker
Keyboard P33 (Phone/ MIC)
DC/DC ( CPU_VDDR ) P31 P33 P34 P24 P29 P29
PROJECT : ZR8
RT9025-25PSP P43 Touch Pad
Quanta Computer Inc.
Size Document Number Rev
Block Diagram 1A
Date: Wednesday, May 27, 2009 Sheet 1 of 49

1 2 3 4 5 6 7 8
5 4 3 2 1
W/S= 15 mil/20mil SB check list tide to CPUVDDIO (+1.5VSUS)
03
+2.5V L40 +CPUVDDA
PBY201209T-221Y-N CPU_PWRGD_SVID_REG 300/F_4 R236
2.5V@250mA CPU_LDT_RST# 300/F_4 R261
+1.1V 1.1V@1.5A +1.1V_VLDT C447
4.7u/6.3V_6
C436
4.7u/6.3V_6
C428
0.22u/6.3V_4
C432
3300P/50V_4
C440
[11] CLK_CPU_BCLKP_PR
CLK_CPU_BCLKP_PR
CLK_CPU_BCLKN_PR
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
300/F_4
*300/F_4
R249
R463
+1.5V
A41 *10U/6.3V_8 [11] CLK_CPU_BCLKN_PR

R124 *SHORT_PAD
Keep trace from resisor to CPU within 0.6"
R121 *SHORT_PAD +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U29D
U29A W/S= 15 mil/20mil
P/N: DG0^8000004 CLK_CPU_BCLKP_C R464 169/F_4 CLK_CPU_BCLKN_C +CPUVDDA F8 VDDA1 VSS M11 S1G4
DG0^8000005 C414 10U/6.3V_8 +1.1V_VLDT D1 VLDT_A0 HT LINK VLDT_B0 AE2 +1.1V_VLDT 10U/6.3V_8 C397 +CPUVDDA F9 VDDA2 RSVD11 W 18
C265 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22u/6.3V_4 C273
D DG0^8000009 C376 0.22u/6.3V_4 +1.1V_VLDT D3
VLDT_A1 VLDT_B1
AE4 +1.1V_VLDT 180P/50V_4 C387 CLK_CPU_BCLKP_PR C704 3900P/25V_4 CLK_CPU_BCLKP_C A9 A6 CPU_SVC D
C274 180P/50V_4 +1.1V_VLDT VLDT_A2 VLDT_B2 +1.1V_VLDT CLK_CPU_BCLKN_PR C703 3900P/25V_4 CLK_CPU_BCLKN_C CLKIN_H SVC CPU_SVD
DG0^80000013 D4 VLDT_A3 VLDT_B3 AE5 A8 CLKIN_L SVD A4
DG0^80000014 HT_CADINP0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUTP0

[11] CPU_LDT_RST#
CPU_LDT_RST# B7 RESET_L
HT_CADINN0 E2 AC1 HT_CADOUTN0 CPU_PWRGD_SVID_REG
A7
HT_CADINP1 L0_CADIN_L0 L0_CADOUT_L0 HT_CADOUTP1 [11,37] CPU_PWRGD_SVID_REG CPU_LDT_STOP# PW ROK CPU_THERMTRIP_L#
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 [9,11] CPU_LDT_STOP# F10 LDTSTOP_L THERMTRIP_L AF6
HT_CADINN1 F1 AC3 HT_CADOUTN1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_CADINP2 L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUTP2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 MEMHOT_L AA8
HT_CADINN2 G2 AA1 HT_CADOUTN2 SideBand Temp sense I2C [4] AF4
HT_CADINP[15..0] L0_CADIN_L2 L0_CADOUT_L2 CPU_SIC SIC
HT_CADINP3 G1 AA2 HT_CADOUTP3 AF5
[7] HT_CADINP[15..0] L0_CADIN_H3 L0_CADOUT_H3 [4] CPU_SID SID
HT_CADINN3 H1 AA3 HT_CADOUTN3 AE6 W7
HT_CADINN[15..0] L0_CADIN_L3 L0_CADOUT_L3 [4] CPU_ALERT ALERT_L THERMDC H_THRMDC [4]
HT_CADINP4 J1 W2 HT_CADOUTP4 W8
[7] HT_CADINN[15..0] L0_CADIN_H4 L0_CADOUT_H4 THERMDA H_THRMDA [4]
HT_CADINN4 K1 W3 HT_CADOUTN4 R207 44.2/F_4 CPU_HTREF0 R6
HT_CLKINP[1..0] L0_CADIN_L4 L0_CADOUT_L4 HT_REF0
l
HT_CADINP5 L3 V1 HT_CADOUTP5 S1G4 R208 44.2/F_4 CPU_HTREF1 P6
[7] HT_CLKINP[1..0] L0_CADIN_H5 L0_CADOUT_H5 +1.1V_VLDT HT_REF1
HT_CADINN5 L2 U1 HT_CADOUTN5 place them to CPU within 1.5"
HT_CLKINN[1..0] HT_CADINP6 L0_CADIN_L5 L0_CADOUT_L5 HT_CADOUTP6 VDDIO_FB_H
L1 L0_CADIN_H6 L0_CADOUT_H6 U2 [37] CPU_VDD0_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 VDDIO_FB_H [40]
[7] HT_CLKINN[1..0] HT_CADINN6 HT_CADOUTN6 VDDIO_FB_L
M1 L0_CADIN_L6 L0_CADOUT_L6 U3 [37] CPU_VDD0_FB_L E6 VDD0_FB_L VDDIO_FB_L Y9 VDDIO_FB_L [40]
HT_CTLINP[1..0] HT_CADINP7 N3 T1 HT_CADOUTP7
L0_CADIN_H7 L0_CADOUT_H7
tia
[7] HT_CTLINP[1..0] HT_CADINN7 HT_CADOUTN7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1 [37] CPU_VDD1_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_FB_H [37]
HT_CTLINN[1..0] HT_CADINP8 E5 AD4 HT_CADOUTP8 AB6 G6
[7] HT_CTLINN[1..0] HT_CADINN8 L0_CADIN_H8 L0_CADOUT_H8 HT_CADOUTN8 [37] CPU_VDD1_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_FB_L [37]
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
HT_CADOUTP[15..0] HT_CADINP9 F3 AD5 HT_CADOUTP9 CPU_DBRDY G10
[7] HT_CADOUTP[15..0] HT_CADINN9 L0_CADIN_H9 L0_CADOUT_H9 HT_CADOUTN9 CPU_TMS DBRDY CPU_DBREQ# R247 *300/F_4
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 AA9 TMS DBREQ_L E10 +1.5V
HT_CADOUTN[15..0] HT_CADINP10 G5 AB4 HT_CADOUTP10 CPU_TCK AC9 R246 300/F_4
[7] HT_CADOUTN[15..0] L0_CADIN_H10 L0_CADOUT_H10 TCK +1.5VSUS
HT_CADINN10 H5 AB3 HT_CADOUTN10 CPU_TRST# AD9 AE9 CPU_TDO
HT_CLKOUTP[1..0] HT_CADINP11 L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUTP11 CPU_TDI TRST_L TDO
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 AF9 TDI
[7] HT_CLKOUTP[1..0] HT_CADINN11 HT_CADOUTN11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 PV stage:add +1.8VSUS option R3114
HT_CLKOUTN[1..0] HT_CADINP12 K3 Y5 HT_CADOUTP12 CPUTEST23 AD7 J7
[7] HT_CLKOUTN[1..0] L0_CADIN_H12 L0_CADOUT_H12 TEST23 TEST28_H for Caspian CPU power leakage issue
HT_CADINN12 K4 W5 HT_CADOUTN12 H8
HT_CTLOUTP[1..0] HT_CADINP13 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUTP13 CPUTEST18 TEST28_L
L5 L0_CADIN_H13 L0_CADOUT_H13 V4 H10 TEST18
C [7] HT_CTLOUTP[1..0] HT_CADINN13 HT_CADOUTN13 CPUTEST19 CPUTEST17 C
M5 L0_CADIN_L13 L0_CADOUT_L13 V3 G9 TEST19 TEST17 D7 T28
HT_CTLOUTN[1..0] HT_CADINP14 M3 V5 HT_CADOUTP14 E7 CPUTEST16
[7] HT_CTLOUTN[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T27
HT_CADINN14 M4 U5 HT_CADOUTN14 R245 510/F_4 CPUTEST25H E9 F7 CPUTEST15
L0_CADIN_L14 L0_CADOUT_L14 +1.5VSUS TEST25_H TEST15 T26
HT_CADINP15 N5 T4 HT_CADOUTP15 R241 510/F_4 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T29
HT_CADINN15 P5 T3 HT_CADOUTN15 place them to CPU within 1.5"
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 C3
en
HT_CLKINP0 HT_CLKOUTP0 CPUTEST20 TEST21 TEST7
J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 AF7 TEST20 TEST10 K8
HT_CLKINN0 J2 W1 HT_CLKOUTN0 CPUTEST24 AE7
HT_CLKINP1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUTP1 CPUTEST22 TEST24
J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 AE8 TEST22 TEST8 C4
HT_CLKINN1 K5 Y3 HT_CLKOUTN1 CPUTEST12 AC8
L0_CLKIN_L1 L0_CLKOUT_L1 R422 1K/F_4 CPUTEST27 TEST12
+1.5VSUS AF8 TEST27
HT_CTLINP0 N1 R2 HT_CTLOUTP0 C9 CPUTEST29H
L0_CTLIN_H0 L0_CTLOUT_H0 TEST29_H T30
HT_CTLINN0 P1 R3 HT_CTLOUTN0 R430 *300/F_4 C2 C8
HT_CTLINP1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CTLOUTP1 TEST9 TEST29_L
P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 AA6 TEST6
HT_CTLINN1 P4 R5 HT_CTLOUTN1 R250
L0_CTLIN_L1 L0_CTLOUT_L1
A3 RSVD1 RSVD10 H18 80.6/F_4
FOX PZ63826-284R-41F A5 RSVD2 RSVD9 H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 CPUTEST29L
RSVD3 RSVD8 T31
+1.5VSUS B5 D5
MLX 47296-4131 [3,4,5,6,37,40,42,43,44,46] +1.5VSUS RSVD4 RSVD7
+1.5V C1 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2) [7,10,27,29,40,43] +1.5V RSVD5 RSVD6
+1.1V
[7,8,9,10,14,38,44] +1.1V
TYC 4-1903401-2 +2.5V S1G4
[42] +2.5V
id
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN
CNTR_VREF [4] +3V

C446 0.1u/10V_4
S1G4 Serial VID VFIX MODE VID Override Circuit
+3V R256 20K/F_4 R251 34.8K/F_4
B R262 B
CNTR_VREF
SVC SVD Voltage Output
4.7K_4
0 0 1.1V
2
Q35 *BSS138_NL/SOT23
0 1 1.0V
2
CPU_LDT_REQ#_CPU 1 3 R238 1K/F_4

+1.5VSUS
R462 *0_4
CPU_LDT_REQ# [9,11]
CPU_LDT_RST# 1
nf Q23
3 CPU_LDT_RST_HTPA#
BSS138_NL/SOT23
+1.5V
+1.5VSUS
R235
R240
*1K/F_4
1K/F_4
1
1
0
1
0.9V
0.8V
1
G1 +1.5V R237 *1K/F_4

The RS880 family does not support CLMC architecture *SHORT_PAD1 S1G4
CPU_SVC
The LDTREQ# connection from the CPU to ALLOW_LDTSTOP CPU_SVC [37]
for debug only CPU_SVD
CPU_SVD [37]
2
of the Northbridge is no longer required. CPU_PWRGD_SVID_REG

CPU_PWRGD_SVID_REG [11,37]
+1.5VSUS R231 *220_4
S1g4 does not support MEMHOT# R232 *220_4
R244 *220_4
3
+1.5VSUS R101 *10K_4

Co
S1G4
2
R100 *1K_4 Q12 2 CPUTEST24 R428 1K/F_4

+1.5VSUS
CPU_MEMHOT_L# 3 1
*MMBT3904
CPU_MEMHOT# [5,6,11]
[34] HWPG
Q8008
FDV301N HDT Connector CPUTEST23
CPUTEST20
CPUTEST22
R426
R427
1K/F_4
1K/F_4
R429 1K/F_4
C01 CPUTEST12 R188 1K/F_4
1
R417 *10K_4 R8191 1K_4 CPUTEST15 R227 *300/F_4

+1.5VSUS
1 2 CPUTEST14 R243 *300/F_4
+1.5VSUS R425 1K_4 3 4 CPUTEST19 R233 1K/F_4
2
A Q32 R8189 CPUTEST18 R230 1K/F_4 A

C01 CPU_DBREQ#
5 6
CPUTEST21
MMBT3904 C01 100K_6 7 8 R139 1K/F_4
CPU_THERMTRIP_L# 1 3 R155 *0_4 CPU_DBRDY 9 10
CPU_THERMTRIP# [12]
CPU_TCK 11 12 S1G4
R420 *10K_4 R309 *Short_4 CPU_TMS 13 14
+1.5VSUS SYS_SHDN# [4,36,43,44] CPU_TDI 15 16
+1.5VSUS R424 300_4 CPU_TRST# 17 18 PROJECT : ZR8
2
A62 Q31 CPU_TDO 19 20

D12 21 22
CPU_PROCHOT_L# 1 3 PM_THERM# [4,12,33]
+1.5VSUS
C398 *0.1u/10V_4 23 24 CPU_LDT_RST_HTPA# Quanta Computer Inc.
*MMBT3904 25
KEY
R138 0_4 Size Document Number Rev
CPU_PROCHOT# [11]
*HDT_CONN S1G4 HT,CTL I/F 1/3 1A
CN7
5 4 3 2 1
A B C D E
04
VDDR=> 0.9V support 1066 / 800 DDR
VDDR=>1.75A VDDR= >1.05V support 1333 / 1066 / 800 DDR
CPU_VDDR D01
[6] M_B_DQ[0..63]
Processor Memory Interface
+1.5VSUS CPU_VDDR U29B CPU_VDDR
PLACE THEM CLOSE TO +SMDDR_VREF

D10 VDDR1 MEM:CMD/CTRL/CLKVDDR5 W 10 C18 U29C
CPU WITHIN 1" C10 VDDR2 VDDR6 AC10 M_A_DQ[0..63] [5,46]
R415 B10 AB10 R189 MEM:DATA
0_4 VDDR3 VDDR7 *0_4 M_B_DQ0 M_A_DQ0
AD10 VDDR4 VDDR8 AA10 C11 MB_DATA0 MA_DATA0 G12
A10 R184 M_B_DQ1 A11 F12 M_A_DQ1
R432 39.2/F_4 M_ZP VDDR9 M_B_DQ2 MB_DATA1 MA_DATA1 M_A_DQ2
AF10 MEMZP *0_4 A14 MB_DATA2 MA_DATA2 H14
R431 39.2/F_4 M_ZN AE10 Y10 CPU_VTT_SENSE C15 D01 M_B_DQ3 B14 G14 M_A_DQ3
4 MEMZN VDDR_SENSE M_B_DQ4 MB_DATA3 MA_DATA3 M_A_DQ4 4
G11 MB_DATA4 MA_DATA4 H11
C660 H16 W 17 MEMVREF_CPU M_B_DQ5 E11 H12 M_A_DQ5
[5,46] M_A_RST# MA_RESET_L MEMVREF MB_DATA5 MA_DATA5
10U/6.3V_8 M_B_DQ6 D12 C13 M_A_DQ6
M_B_DQ7 MB_DATA6 MA_DATA6 M_A_DQ7
[46] M_A_ODT0 T19 MA0_ODT0 MB_RESET_L B18 M_B_RST# [6] A13 MB_DATA7 MA_DATA7 E13
S1G4 V22 M_B_DQ8 A15 H15 M_A_DQ8
[46] M_A_ODT1 MA0_ODT1 MB_DATA8 MA_DATA8
U21 W 26 M_B_DQ9 A16 E15 M_A_DQ9
[5] M_A1_ODT0 MA1_ODT0 MB0_ODT0 M_B_ODT0 [6] MB_DATA9 MA_DATA9
V19 W 23 C347 C346 M_B_DQ10 A19 E17 M_A_DQ10
[5] M_A1_ODT1 MA1_ODT1 MB0_ODT1 M_B_ODT1 [6] MB_DATA10 MA_DATA10
Y26 0.1u/10V_4 1000P/50V_4 M_B_DQ11 A20 H17 M_A_DQ11
MB1_ODT0 M_B_DQ12 MB_DATA11 MA_DATA11 M_A_DQ12
[46] M_A_CS#0 T20 MA0_CS_L0 C14 MB_DATA12 MA_DATA12 E14
U19 V26 M_B_DQ13 D14 F14 M_A_DQ13
[46] M_A_CS#1 MA0_CS_L1 MB0_CS_L0 M_B_CS#0 [6] MB_DATA13 MA_DATA13
U20 W 25 M_B_DQ14 C18 C17 M_A_DQ14
[5] M_A1_CS#0 MA1_CS_L0 MB0_CS_L1 M_B_CS#1 [6] MB_DATA14 MA_DATA14
V20 U22 M_B_DQ15 D18 G17 M_A_DQ15
l
[5] M_A1_CS#1 MA1_CS_L1 MB1_CS_L0 MB_DATA15 MA_DATA15
M_B_DQ16 D20 G18 M_A_DQ16
[5,46] M_A_CKE0 J22 MA_CKE0 MB_CKE0 J25 M_B_CKE0 [6] A21 MB_DATA17 MA_DATA17 C19
J20 H26 M_B_DQ18 D24 D22 M_A_DQ18
[5,46] M_A_CKE1 MA_CKE1 MB_CKE1 M_B_CKE1 [6] MB_DATA18 MA_DATA18
M_B_DQ19 C25 E20 M_A_DQ19
MB_DATA19 MA_DATA19
tia
N19 P22 M_B_DQ20 B20 E18 M_A_DQ20
[46] M_A_CLKP1 MA_CLK_H5 MB_CLK_H5 M_B_CLKP1 [6] MB_DATA20 MA_DATA20
N20 R22 M_B_DQ21 C20 F18 M_A_DQ21
[46] M_A_CLKN1 MA_CLK_L5 MB_CLK_L5 M_B_CLKN1 [6] MB_DATA21 MA_DATA21
E16 A17 M_B_DQ22 B24 B22 M_A_DQ22
[5] M_A_CLKP3 MA_CLK_H1 MB_CLK_H1 MB_DATA22 MA_DATA22
F16 A18 M_B_DQ23 C24 C23 M_A_DQ23
[5] M_A_CLKN3 MA_CLK_L1 MB_CLK_L1 MB_DATA23 MA_DATA23
Y16 AF18 M_B_DQ24 E23 F20 M_A_DQ24
[5] M_A_CLKP4 MA_CLK_H7 MB_CLK_H7 MB_DATA24 MA_DATA24
AA16 AF17 M_B_DQ25 E24 F22 M_A_DQ25
[5] M_A_CLKN4 MA_CLK_L7 MB_CLK_L7 MB_DATA25 MA_DATA25
P19 R26 M_B_DQ26 G25 H24 M_A_DQ26
[46] M_A_CLKP2 MA_CLK_H4 MB_CLK_H4 M_B_CLKP2 [6] MB_DATA26 MA_DATA26
P20 R25 M_B_DQ27 G26 J19 M_A_DQ27
[46] M_A_CLKN2 MA_CLK_L4 MB_CLK_L4 M_B_CLKN2 [6] MB_DATA27 MA_DATA27
M_B_DQ28 C26 E21 M_A_DQ28
M_A_A0 M_B_A0 M_B_DQ29 MB_DATA28 MA_DATA28 M_A_DQ29
N21 MA_ADD0 MB_ADD0 P24 D26 MB_DATA29 MA_DATA29 E22
M_A_A1 M20 N24 M_B_A1 M_B_DQ30 G23 H20 M_A_DQ30
M_A_A2 MA_ADD1 MB_ADD1 M_B_A2 M_B_DQ31 MB_DATA30 MA_DATA30 M_A_DQ31
N22 MA_ADD2 MB_ADD2 P26 G24 MB_DATA31 MA_DATA31 H22
M_A_A3 M19 N23 M_B_A3 M_B_DQ32 AA24 Y24 M_A_DQ32
3 M22 MA_ADD4 MB_ADD4 N26 AA23 MB_DATA33 MA_DATA33 AB24 3
M_A_A5 L20 L23 M_B_A5 M_B_DQ34 AD24 AB22 M_A_DQ34
M24 MA_ADD6 MB_ADD6 N25 AE24 MB_DATA35 MA_DATA35 AA21
M_A_A7 L21 L24 M_B_A7 M_B_DQ36 AA26 W 22 M_A_DQ36
en
L19 MA_ADD8 MB_ADD8 M26 AA25 MB_DATA37 MA_DATA37 W 21
M_A_A9 K22 K26 M_B_A9 M_B_DQ38 AD26 Y22 M_A_DQ38
R21 MA_ADD10 MB_ADD10 T26 AE25 MB_DATA39 MA_DATA39 AA22
M_A_A11 L22 L26 M_B_A11 M_B_DQ40 AC22 Y20 M_A_DQ40
K20 MA_ADD12 MB_ADD12 L25 AD22 MB_DATA41 MA_DATA41 AA20
M_A_A13 V24 W 24 M_B_A13 M_B_DQ42 AE20 AA18 M_A_DQ42
K24 MA_ADD14 MB_ADD14 J23 AF20 MB_DATA43 MA_DATA43 AB18
M_A_A15 K19 J24 M_B_A15 M_B_DQ44 AF24 AB21 M_A_DQ44
[5,46] M_A_A[0..15] MA_ADD15 MB_ADD15 M_B_A[0..15] [6] MB_DATA44 MA_DATA44
+0.75V_DDR_VTT +0.75V_DDR_VTT M_B_DQ45 AF23 AD21 M_A_DQ45
+SMDDR_VREF M_B_DQ46 MB_DATA45 MA_DATA45 M_A_DQ46
[5,46] M_A_BANK0 R20 MA_BANK0 MB_BANK0 R24 M_B_BANK0 [6] [5,6,40] +SMDDR_VREF AC20 MB_DATA46 MA_DATA46 AD19
R23 U26 [43] CPU_VDDR CPU_VDDR M_B_DQ47 AD20 Y18 M_A_DQ47
[5,46] M_A_BANK1 MA_BANK1 MB_BANK1 M_B_BANK1 [6] MB_DATA47 MA_DATA47
J21 J26 [2,4,5,6,37,40,42,43,44,46] +1.5VSUS +1.5VSUS M_B_DQ48 AD18 AD17 M_A_DQ48
[5,46] M_A_BANK2 MA_BANK2 MB_BANK2 M_B_BANK2 [6] MB_DATA48 MA_DATA48
M_B_DQ49 AE18 W 16 M_A_DQ49
[5,46] M_A_RAS# R19 MA_RAS_L MB_RAS_L U25 M_B_RAS# [6] AC14 MB_DATA50 MA_DATA50 W 14
T22 U24 M_B_DQ51 AD14 Y14 M_A_DQ51
[5,46] M_A_CAS# MA_CAS_L MB_CAS_L M_B_CAS# [6] MB_DATA51 MA_DATA51
T24 U23 M_B_DQ52 AF19 Y17 M_A_DQ52
id
[5,46] M_A_WE# MA_W E_L MB_W E_L M_B_WE# [6] MB_DATA52 MA_DATA52
M_B_DQ53 AC18 AB17 M_A_DQ53
AF16 MB_DATA54 MA_DATA54 AB15
SOCKET_638_PIN M_B_DQ55 AF15 AD15 M_A_DQ55
AF13 MB_DATA56 MA_DATA56 AB13
CPU_VDDR M_B_DQ57 AC12 AD13 M_A_DQ57
Place close to socket M_B_DQ58 AB11
MB_DATA57 MA_DATA57
Y12 M_A_DQ58
Y11 MB_DATA59 MA_DATA59 W 11
M_B_DQ60 AE14 AB14 M_A_DQ60
AF14 MB_DATA61 MA_DATA61 AA14
C439 C282 C442 C281 C278 C279 C276 C277 M_B_DQ62 AF11 AB12 M_A_DQ62
2
4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 0.22u/6.3V_4 0.22u/6.3V_4 0.22u/6.3V_4 0.22u/6.3V_4 M_B_DQ63 MB_DATA62 MA_DATA62 M_A_DQ63 2
[6] M_B_DM[0..7] AD11 MB_DATA63 MA_DATA63 AA12 M_A_DM[0..7] [5,46]
CPU_VDDR
nf M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
A12
B16
A22
E25
AB26
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
E12
C15
E19
F24
AC24
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
C431 C434 C345 C275 C427 C435 C437 C430 M_B_DM5 AE22 Y19 M_A_DM5
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 M_B_DM6 MB_DM5 MA_DM5 M_A_DM6
AC16 MB_DM6 MA_DM6 AB16
M_B_DM7 AD12 Y13 M_A_DM7
MB_DM7 MA_DM7
[6] M_B_DQSP0 C12 MB_DQS_H0 MA_DQS_H0 G13 M_A_DQSP0 [5,46]

[6] M_B_DQSN0 B12 MB_DQS_L0 MA_DQS_L0 H13 M_A_DQSN0 [5,46]
[6] M_B_DQSP1 D16 MB_DQS_H1 MA_DQS_H1 G16 M_A_DQSP1 [5,46]
[6] M_B_DQSN1 C16 MB_DQS_L1 MA_DQS_L1 G15 M_A_DQSN1 [5,46]
[6] M_B_DQSP2 A24 MB_DQS_H2 MA_DQS_H2 C22 M_A_DQSP2 [5,46]
Co
[6] M_B_DQSN2 A23 MB_DQS_L2 MA_DQS_L2 C21 M_A_DQSN2 [5,46]
+1.5VSUS R201 0_4 F26 G22
[6] M_B_DQSP3 MB_DQS_H3 MA_DQS_H3 M_A_DQSP3 [5,46]
E26 G21
+3VPCU Reserved for AMD suggest [6] M_B_DQSN3
AC25
MB_DQS_L3 MA_DQS_L3
AD23
M_A_DQSN3 [5,46]
C339 AC26 AC23
[6] M_B_DQSN4 MB_DQS_L4 MA_DQS_L4 M_A_DQSN4 [5,46]
*.1u_4 AF21 AB19
R206 AF22 AB20
[6] M_B_DQSN5 MB_DQS_L5 MA_DQS_L5 M_A_DQSN5 [5,46]
1K/F_4 AE16 Y15
[6] M_B_DQSN6 AD16 MB_DQS_L6 MA_DQS_L6 W 15 M_A_DQSN6 [5,46]
5
U14 AF12 W 12
3 + [6] M_B_DQSN7 AE12 MB_DQS_L7 MA_DQS_L7 W 13 M_A_DQSN7 [5,46]
1 R197 *10_4 MEMVREF_CPU
4 -
2
1 *OPA343NA/3K SOCKET_638_PIN 1
R204 C352
2
1K/F_4 *0.47u/10V_4 R182

1
*10K/F_4
R194 *0_4
R193 *0_4 PROJECT : ZR8

S1G4 DDRIII MEMORY I/F 2/3 1A

A B C D E
5 4 3 2 1
+VCORE U29E +VCORE

AA4
AA11
AA13
AA15
U29F
VSS1
VSS2
VSS3
VSS66
VSS67
VSS68
J6
J8
J10
J12
+VCORE
BOTTOM SIDE DECOUPLING
05
VSS4 VSS69
G4 P8 AA17 J14
H2
VDD_1
VDD_2
VDD_24
VDD_25 P10 B2-TEST AA19
VSS5
VSS6
VSS70
VSS71 J16
J9 R4 PC54 AB2 J18
VDD_3 VDD_26 + *330u/2V_7343 VSS7 VSS72 C360 C351 C371 C413 C354 C355 C356
J11 VDD_4 VDD_27 R7 AB7 VSS8 VSS73 K2
J13 R9 AB9 K7 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22u/6.3V_4 0.01U/25V_4 180P/50V_4
VDD_5 VDD_28 VSS9 VSS74
D
J15 VDD_6 VDD_29 R11 AB23 VSS10 VSS75 K9 D
K6 VDD_7 VDD_30 T2 AB25 VSS11 VSS76 K11
K10 VDD_8 VDD_31 T6 AC11 VSS12 VSS77 K13
K12 VDD_9 VDD_32 T8 Place under CPU bracket side. AC13 VSS13 VSS78 K15
K14 T10 AC15 K17 +VCORE
L4 VDD_11 VDD_34 T12 AC17 VSS15 VSS80 L6
L7 VDD_12 VDD_35 T14 AC19 VSS16 VSS81 L8
L9 VDD_13 VDD_36 U7 AC21 VSS17 VSS82 L10
L11 VDD_14 VDD_37 U9 AD6 VSS18 VSS83 L12
L13 U11 AD8 L14 C357 C388 C364 C399 C370 C378 C383 C368
VDD_15 VDD_38 VSS19 VSS84 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22u/6.3V_4 0.01U/25V_4 180P/50V_4 0.01U/25V_4
L15 VDD_16 VDD_39 U13 AD25 VSS20 VSS85 L16
M2 VDD_17 VDD_40 U15 AE11 VSS21 VSS86 L18
M6 V6 AE13 M7
l
M8 VDD_19 VDD_42 V8 AE15 VSS23 VSS88 M9
M10 VDD_20 VDD_43 V10 AE17 VSS24 VSS89 AC6
N7 V12 AE19 M17 CPU_VDDNB_CORE +1.5VSUS
CPU_VDDNB_CORE VDD_21 VDD_44 VSS25 VSS90
N9 VDD_22 VDD_45 V14 AE21 VSS26 VSS91 N4
tia
N11 VDD_23 VDD_46 W4 AE23 VSS27 VSS92 N8
Y2 B4 N10
3A K16 VDDNB_1
VDD_47
VDD_48 AC4
+1.5VSUS
B6
VSS28
VSS29
VSS93
VSS94 N16
M16 AD2 B8 N18 C358 C406 C366 C415 C372 C367 C404 C369 C396
VDDNB_2 VDD_49 VSS30 VSS95 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22u/6.3V_4 0.22u/6.3V_4 180P/50V_4 180P/50V_4
P16 VDDNB_3 B9 VSS31 VSS96 P2
+1.5VSUS T16 Y25 B11 P7
VDDNB_4 VDDIO27 VSS32 VSS97
V16 V25 B13 P9
VDDNB_5 VDDIO26
VDDIO25 V23 1.5V@2A B15
VSS33
VSS34
VSS98
VSS99 P11
H25 VDDIO1 VDDIO24 V21 B17 VSS35 VSS100 P17
J17 VDDIO2 VDDIO23 V18 B19 VSS36 VSS101 R8
K18 VDDIO3 VDDIO22 U17 B21 VSS37 VSS102 R10
K21 VDDIO4 VDDIO21 T25 B23 VSS38 VSS103 R16
K23 VDDIO5 VDDIO20 T23 B25 VSS39 VSS104 R18
C K25 VDDIO6 VDDIO19 T21 D6 VSS40 VSS105 T7 C
L17 T18 D8 T9
M18
VDDIO7
VDDIO8
VDDIO18
VDDIO17 R17 D9
VSS41
VSS42
VSS106
VSS107 T11 DECOUPLING BETWEEN PROCESSOR AND DIMMs
M21 P25 D11 T13
en
VDDIO9 VDDIO16 VSS43 VSS108
M23 P23 D13 T15
M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D15
VSS44
VSS45
VSS109
VSS110 T17 PLACE CLOSE TO PROCESSOR AS POSSIBLE
N17 VDDIO12 VDDIO13 P18 D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
D21 U8 +1.5VSUS
SOCKET_638_PIN VSS48 VSS113
D23 VSS49 VSS114 U10
D25 VSS50 VSS115 U12
+1.5VSUS E4 U14
VSS51 VSS116
F2 VSS52 VSS117 U16
F11 U18 C394 C425 C426 C405 C384 C359
VSS53 VSS118 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 0.22u/6.3V_4 0.22u/6.3V_4
F13 VSS54 VSS119 V2
F15 VSS55 VSS120 V7
R421 R423 R252 F17 V9
1K/F_4 1K/F_4 1K/F_4 VSS56 VSS121 +1.5VSUS
[2] CNTR_VREF F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
F23 V15
id
VSS59 VSS124
2
F25 VSS60 VSS125 V17

Q19 H7 W6
CPU_SMBCLK VSS61 VSS126 C377 C361 C408 C407 C385
3 1 CPU_SIC [2] H9 VSS62 VSS127 Y21
H21 Y23 0.22u/6.3V_4 0.22u/6.3V_4 0.01U/25V_4 0.01u/25V_4 180P/50V_4
VSS63 VSS128
2
BSS138_NL/SOT23 C17 H23 N6

Q18 VSS64 VSS129
J4 VSS65
CPU_SMBDATA 3 1 CPU_SID [2]
SOCKET_638_PIN
2
BSS138_NL/SOT23
Q17
B B
PM_THERM# 3 1
C17 CPU_ALERT [2]
PROCESSOR POWER AND GROUND

BSS138_NL/SOT23
+3V
nf
+3V R254
*200/F_6
C17
D05 R267
*10K/F_4 D05
Co
C450
C17 *0.1u/10V_4 SYS_SHDN# [2,36,43,44]
U16
[34] CPU_SMBCLK CPU_SMBCLK 8 1 D05

SCLK VCC H_THRMDA [2]
CPU_SMBDATA C344
C02
[34] CPU_SMBDATA 7 SDA DXP 2
*1000P/50V_4 D14
3
R479 6 3 *CH501H-40PT
*0_4 ALERT# DXN PWROK_EC_3904
H_THRMDC [2] 2 2 1 PWROK_EC [15,34]
[2,12,33] PM_THERM# PM_THERM# 4 5
OVERT# GND Q21
1
A C17 MSOP *MMBT3904 R255 *10K/F_4 A

+3V
*G786P8
SMBALERT#
3
R264 *10K/F_4
PROJECT : ZR8
Q22 2
*2N7002K
TEMP_FAIL [17]
ADD VGA TEMP_ FAIL function Size Document Number Rev
M93 is active Hi S1G4 PWR & GND 3/3 1A
1
5 4 3 2 1
5 4 3 2 1
+1.5VSUS
M_A_DQ[63:0] [3,46] CN15B
[3,46] M_A_A[15:0] CN15A
75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ0 76 48
M_A_A1 A0 DQ0 M_A_DQ1 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ4 +1.5VSUS 88 60
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66
M_A_A8 A7 DQ7 M_A_DQ8 R589 VDD9 VSS24
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ9 1K/F_4 105 72
M_A_A10 A9 DQ9 M_A_DQ10 +0.75VSMVREF_SUSA VDD11 VSS26
PC2100 DDR3 SDRAM SO-DIMM

107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ11 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ13 117 134
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ16 VDD17 VSS32

DQ16 39 124 VDD18 VSS33 144
M_A_BANK0 109 41 M_A_DQ17 145
M_A_BANK1 BA0 DQ17 M_A_DQ18 VSS34
108 BA1 DQ18 51 +3V 199 VDDSPD VSS35 150
l
M_A_BANK2 79 53 M_A_DQ19 151
[3,46] M_A_BANK[0..2] BA2 DQ19 VSS36
114 40 M_A_DQ20 R590 77 155
[3] M_A1_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 1K/F_4 122 156
[3] M_A1_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 125 161
[3] M_A_CLKP3 CK0 DQ22 NCTEST VSS39
tia
103 52 M_A_DQ23 162
[3] M_A_CLKN3 CK0# DQ23 VSS40
102 57 M_A_DQ24 MEMHOT_MA# 198 167
[3] M_A_CLKP4 CK1 DQ24 [46] MEMHOT_MA# EVENT# VSS41
104 59 M_A_DQ25 30 168
[3] M_A_CLKN4 CK1# DQ25 [3,46] M_A_RST# RESET# VSS42
R585 *Short_4 R0_CKE0 73 67 M_A_DQ26 172
[3,46] M_A_CKE0 CKE0 DQ26 VSS43
R588 *Short_4 R0_CKE1 74 69 M_A_DQ27 173
[3,46] M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ28 +0.75VSMVREF_SUSA 1 178
[3,46] M_A_CAS# CAS# DQ28 VREF_DQ VSS45
A08 [3,46] M_A_RAS# 110 58 M_A_DQ29 +VREF_CA_A 126 179
RAS# DQ29 M_A_DQ30 VREF_CA VSS46
[3,46] M_A_WE# 113 WE# DQ30 68 VSS47 184
R198 10K_4 DIMM0_SA0 197 70 M_A_DQ31 185
R199 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ32 VSS48
+3V 201 SA1 DQ32 129 2 VSS1 VSS49 189
202 131 M_A_DQ33 3 190
[6,12,26,27,46] PCLK_SMB SCL DQ33 M_A_DQ34 VSS2 VSS50
200 141 8 195
(204P)
[6,12,26,27,46] PDAT_SMB SDA DQ34 M_A_DQ35 +1.5VSUS VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ36 13
[3] M_A1_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
[3] M_A1_ODT1 ODT1 DQ37 +SMDDR_VREF +VREF_CA_A VSS6
en
140 M_A_DQ38 19
M_A_DM0 DQ38 M_A_DQ39 R257 VSS7
11 DM0 DQ39 142 20 VSS8
+1.5VSUS M_A_DM1 28 147 M_A_DQ40 *2K/F_4 25
M_A_DM2 DM1 DQ40 M_A_DQ41 VSS9
46 149 26 203 +0.75V_DDR_VTT
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ42 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ43 R203 *Short_4 32
D08 M_A_DM6
153 DM5 DQ44 146
M_A_DQ45
37 VSS13 GND 205
170 DM6 DQ45 148 38 VSS14 GND 206
M_A_DM7 187 158 M_A_DQ46 R258 43
[3,46] M_A_DM[7:0] DM7 DQ46 VSS15
R584 R259 160 M_A_DQ47 *2K/F_4
*10K_4 *10K_4 M_A_DQSP0 DQ47 M_A_DQ48
12 DQS0 DQ48 163
M_A_DQSP1 29 165 M_A_DQ49 DDR3-DIMM0_H=4.0_RVS
M_A_DQSP2 DQS1 DQ49 M_A_DQ50
47 DQS2 DQ50 175
R0_CKE0 M_A_DQSP3 64 177 M_A_DQ51
R0_CKE1 M_A_DQSP4 DQS3 DQ51 M_A_DQ52
137 164
id
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ54
[3,46] M_A_DQSP[7:0]
M_A_DQSN0
188 DQS7 DQ55 176
M_A_DQ56
A51
10 DQS#0 DQ56 181
M_A_DQSN1 27 183 M_A_DQ57
M_A_DQSN2 DQS#1 DQ57 M_A_DQ58
45 DQS#2 DQ58 191
M_A_DQSN3 62 193 M_A_DQ59
135 DQS#4 DQ60 180
M_A_DQSN5 152 182 M_A_DQ61 +1.5VSUS R123 *2.2K_4
B 169 DQS#6 DQ62 192 B
M_A_DQSN7 186 194 M_A_DQ63
[3,46] M_A_DQSN[7:0] DQS#7
nf
DQ63
2
+1.5VSUS R122 *2.2K_4 Q10
*MMBT3904
MEMHOT_MA# 1 3 CPU_MEMHOT# [2,6,11]
DDR3-DIMM0_H=4.0_RVS
D12
Place these Caps near So-Dimm0.
+1.5VSUS
Co
+VREF_CA_A +0.75VSMVREF_SUSA
C400 C379 C401 C686 C417
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C390 C348 C260 C825 C826
.1u/16V_4 .1u/16V_4
10u/6.3V_6 C411 C380 C416 C402 C455 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4
A A
+0.75V_DDR_VTT
C829
C224
1U/6.3V_4
C9224
1U/6.3V_4 10u/6.3V_6 PROJECT : ZR8
DDR2 SODIMMS: A/B CHANNEL 1A

5 4 3 2 1
5 4 3 2 1
[3] M_B_A[15:0] M_B_DQ[63:0] [3] +1.5VSUS

CN25A CN25B
M_B_A0 98 5 M_B_DQ0 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ4 +1.5VSUS 87 55
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ8 R591 99 66
D
M_B_A9 85
A8 DQ8
23 M_B_DQ9 1K/F_4
2.48A 100
VDD9 VSS24
71
D
M_B_A10 A9 DQ9 M_B_DQ10 +0.75VSMVREF_SUSB VDD10 VSS25

107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ11

84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ16

DQ16 39 123 VDD17 VSS32 139
M_B_BANK0 109 41 M_B_DQ17 124 144
M_B_BANK1 BA0 DQ17 M_B_DQ18 VDD18 VSS33
108 BA1 DQ18 51 VSS34 145
l
M_B_BANK2 79 53 M_B_DQ19 199 150
[3] M_B_BANK[0..2] BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 R592 151
[3] M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 1K/F_4 77 155
[3] M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
[3] M_B_CLKP1 CK0 DQ22 NC2 VSS38
tia
103 52 M_B_DQ23 125 161
[3] M_B_CLKN1 CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ24 162
[3] M_B_CLKP2 CK1 DQ24 VSS40
104 59 M_B_DQ25 MEMHOT_MB# 198 167
[3] M_B_CLKN2 CK1# DQ25 EVENT# VSS41
73 67 M_B_DQ26 30 168
[3] M_B_CKE0 CKE0 DQ26 [3] M_B_RST# RESET# VSS42
74 69 M_B_DQ27 172
[3] M_B_CKE1 CKE1 DQ27 VSS43
A08 115 56 M_B_DQ28 173
[3] M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ29 +0.75VSMVREF_SUSB 1 178
[3] M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ30 +VREF_CA_B 126 179
[3] M_B_WE# WE# DQ30 VREF_CA VSS46
R131 10K_4 DIMM1_SA0 197 70 M_B_DQ31 184
+3V SA0 DQ31 VSS47
R130 10K_4 DIMM1_SA1 201 129 M_B_DQ32 185
SA1 DQ32 M_B_DQ33 VSS48
202 SCL DQ33 131 2 VSS1 VSS49 189
[5,12,26,27,46] PCLK_SMB 200 141 M_B_DQ34 3 190
[5,12,26,27,46] PDAT_SMB SDA DQ34 M_B_DQ35 +1.5VSUS VSS2 VSS50
143 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
[3] M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
[3] M_B_ODT1 ODT1 DQ37 +SMDDR_VREF +VREF_CA_B VSS5
en
140 M_B_DQ38 14
M_B_DM0 DQ38 M_B_DQ39 R118 VSS6
11 DM0 DQ39 142 19 VSS7
M_B_DM1 28 147 M_B_DQ40 *2K/F_4 20
M_B_DM2 DM1 DQ40 M_B_DQ41 VSS8
46 149 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ42 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 R117 *Short_4 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ45 37 205
M_B_DM7 DM6 DQ45 M_B_DQ46 R110 VSS13 GND
[3] M_B_DM[7:0] 187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 *2K/F_4 43
M_B_DQSP0 DQ47 M_B_DQ48 VSS15
12 DQS0 DQ48 163
M_B_DQSP1 29 165 M_B_DQ49
M_B_DQSP2 DQS1 DQ49 M_B_DQ50
47 DQS2 DQ50 175 DDR3-DIMM1_H=4.0_Standard
M_B_DQSP3 64 177 M_B_DQ51
137 164
id
M_B_DQSP6
154 DQS5 DQ53 166
M_B_DQ54
A50
171 DQS6 DQ54 174
M_B_DQSP7 188 176 M_B_DQ55
[3] M_B_DQSP[7:0]
M_B_DQSN0 10
DQS7 DQ55
181 M_B_DQ56
2DIMM--->P/N:DGMK4000109
M_B_DQSN1 DQS#0 DQ56 M_B_DQ57 R202 *2.2K_4
27 DQS#1 DQ57 183 +1.5VSUS
M_B_DQSN2 45 191 M_B_DQ58
DQS#2 DQ58
2
M_B_DQSN3 62 193 M_B_DQ59 R195 *2.2K_4 Q14
M_B_DQSN4 DQS#3 DQ59 M_B_DQ60 *MMBT3904
135 DQS#4 DQ60 180
M_B_DQSN5 152 182 M_B_DQ61 MEMHOT_MB# 1 3
DQS#5 DQ61 CPU_MEMHOT# [2,5,11]
B M_B_DQSN6 169 192 M_B_DQ62 B
M_B_DQSN7 DQS#6 DQ62 M_B_DQ63
186 194 D12
[3] M_B_DQSN[7:0] DQS#7
DDR3-DIMM1_H=4.0_Standard
nf
DQ63
+1.5VSUS Place these Caps near So-Dimm1.

+VREF_CA_B +0.75VSMVREF_SUSB
C409 C690 C821 C689 C820
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
Co
C817 C230 C259 C828 C827
10u/6.3V_6 .1u/16V_4 2.2u/6.3V_6 .1u/16V_4 2.2u/6.3V_6
C819 C818 C822 C418 C454

10u/6.3V_6 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4
+0.75V_DDR_VTT
A C8158 C231 C830 A

1u/6.3V_4 1u/6.3V_4
10u/6.3V_6
PROJECT : ZR8
DDR2 SODIMMS: A/B CHANNEL 1A

5 4 3 2 1
5 4 3 2 1
U28A
SIDE PORT
11/4
HT_CADOUTP0
HT_CADOUTN0
HT_CADOUTP1
HT_CADOUTN1
HT_CADOUTP2
HT_CADOUTN2
HT_CADOUTP3
Y25
Y24
V22
V23
V25
V24
U24
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
D24
D25
E24
E25
F24
F25
F23
HT_CADINP0
HT_CADINN0
HT_CADINP1
HT_CADINN1
HT_CADINP2
HT_CADINN2
HT_CADINP3
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
[2]
[2]
[2]
08
HT_CADOUTN3 HT_RXCAD3P HT_TXCAD3P HT_CADINN3 HT_CLKOUTN[1..0]
U25 HT_RXCAD3N HT_TXCAD3N F22 HT_CLKOUTN[1..0] [2]
HT_CADOUTP4 T25 H23 HT_CADINP4
HT_CADOUTN4 HT_RXCAD4P HT_TXCAD4P HT_CADINN4 HT_CTLOUTP[1..0]
T24 HT_RXCAD4N HT_TXCAD4N H22 HT_CTLOUTP[1..0] [2]
HT_CADOUTP5 P22 J25 HT_CADINP5
HYPER TRANSPORT CPU I/F

HT_CADOUTN5 HT_RXCAD5P HT_TXCAD5P HT_CADINN5 HT_CTLOUTN[1..0]
P23 HT_RXCAD5N HT_TXCAD5N J24 HT_CTLOUTN[1..0] [2]
+1.5V_MEM_VDDQ +1.5V_MEM_VDDQ HT_CADOUTP6 P25 K24 HT_CADINP6
D
HT_CADOUTN6 HT_RXCAD6P HT_TXCAD6P HT_CADINN6 HT_CADINP[15..0] D
P24 HT_RXCAD6N HT_TXCAD6N K25 HT_CADINP[15..0] [2]
HT_CADOUTP7 N24 K23 HT_CADINP7
HT_CADOUTN7 HT_RXCAD7P HT_TXCAD7P HT_CADINN7 HT_CADINN[15..0]
N25 HT_RXCAD7N HT_TXCAD7N K22 HT_CADINN[15..0] [2]
HT_CADOUTP8 AC24 F21 HT_CADINP8 HT_CLKINP[1..0]
C9788 R599 C9789 R600 HT_CADOUTN8 HT_RXCAD8P HT_TXCAD8P HT_CADINN8 HT_CLKINP[1..0] [2]
AC25 HT_RXCAD8N HT_TXCAD8N G21
SIDE@1K/F_4 SIDE@1K/F_4 HT_CADOUTP9 AB25 G20 HT_CADINP9 HT_CLKINN[1..0]
SIDE@0.1u/10V_4 SIDE@0.1u/10V_4 HT_CADOUTN9 HT_RXCAD9P HT_TXCAD9P HT_CADINN9 HT_CLKINN[1..0] [2]
AB24 HT_RXCAD9N HT_TXCAD9N H21
HT_CADOUTP10 AA24 J20 HT_CADINP10 HT_CTLINP[1..0]
HT_CADOUTN10 HT_RXCAD10P HT_TXCAD10P HT_CADINN10 HT_CTLINP[1..0] [2]
AA25 HT_RXCAD10N HT_TXCAD10N J21
SPM_VREFDQ SPM_VREFCA HT_CADOUTP11 Y22 J18 HT_CADINP11 HT_CTLINN[1..0]
HT_CADOUTN11 HT_RXCAD11P HT_TXCAD11P HT_CADINN11 HT_CTLINN[1..0] [2]
Y23 K17
l
HT_CADOUTP12 HT_RXCAD11N HT_TXCAD11N HT_CADINP12
W 21 HT_RXCAD12P HT_TXCAD12P L19
C9790 R601 C9791 R602 HT_CADOUTN12 W 20 J19 HT_CADINN12
HT_CADOUTP13 HT_RXCAD12N HT_TXCAD12N HT_CADINP13
SIDE@1K/F_4 SIDE@1K/F_4 V21 HT_RXCAD13P HT_TXCAD13P M19
SIDE@0.1u/10V_4 SIDE@0.1u/10V_4 HT_CADOUTN13 V20 L18 HT_CADINN13 signals RS880 RX880
HT_RXCAD13N HT_TXCAD13N
tia
HT_CADOUTP14 U20 M21 HT_CADINP14
HT_CADOUTN14 HT_RXCAD14P HT_TXCAD14P HT_CADINN14
U21 HT_RXCAD14N HT_TXCAD14N P21
HT_CADOUTP15 U19 P18 HT_CADINP15 HT_TXCALP
HT_CADOUTN15 HT_RXCAD15P HT_TXCAD15P HT_CADINN15
U18 HT_RXCAD15N HT_TXCAD15N M18 Ra Ra
301 ohm 1% 1.21k ohm 1%
HT_CLKOUTP0 T22 H24 HT_CLKINP0 HT_TXCALN
HT_CLKOUTN0 HT_RXCLK0P HT_TXCLK0P HT_CLKINN0
T23 HT_RXCLK0N HT_TXCLK0N H25
HT_CLKOUTP1 AB23 L21 HT_CLKINP1
HT_CLKOUTN1 HT_RXCLK1P HT_TXCLK1P HT_CLKINN1
AA22 HT_RXCLK1N HT_TXCLK1N L20 HT_RXCALP
Rb Rb
U39 HT_CTLOUTP0 M22 M24 HT_CTLINP0 301 ohm 1% 1.21k ohm 1%
HT_CTLOUTN0 HT_RXCTL0P HT_TXCTL0P HT_CTLINN0
M23 HT_RXCTL0N HT_TXCTL0N M25 HT_RXCALN
SPM_VREFCA M9 E4 SPM_DQ5 HT_CTLOUTP1 R21 P19 HT_CTLINP1
SPM_VREFDQ H2 VREFCA DQL0 SPM_DQ3 HT_CTLOUTN1 HT_RXCTL1P HT_TXCTL1P HT_CTLINN1
C
VREFDQ DQL1 F8 Ra R20 HT_RXCTL1N HT_TXCTL1N R18 Rb C
F3 SPM_DQ4
SPM_A0 DQL2 SPM_DQ0 R183 301/F_4 HT_RXCALP HT_TXCALP R192 301/F_4
N4 A0 DQL3 F9 C23 HT_RXCALP HT_TXCALP B24 RES CHIP 1.21K 1/16W +-1%(0402)
SPM_A1 P8 H4 SPM_DQ6 HT_RXCALN A24 B25 HT_TXCALN P/N : CS21212FB18
en
SPM_A2 A1 DQL4 SPM_DQ1 HT_RXCALN HT_TXCALN
P4 A2 DQL5 H9
SPM_A3 N3 G3 SPM_DQ7 RS880M_A11
SPM_A4 A3 DQL6 SPM_DQ2
P9 A4 DQL7 H8
SPM_A5 P3
SPM_A6 A5
R9 A6
SPM_A7 R3 D8 SPM_DQ14 +1.8V
A7 DQU0 [9,10,15,24,37,42,43,44] +1.8V
SPM_A8 T9 C4 SPM_DQ9 +1.1V
SPM_A9 R4
A8
A9
DQU1
DQU2 C9 SPM_DQ15 This block is for UMA only , Discrete can remove all component [2,8,9,10,14,38,44] +1.1V
SPM_A10 L8 C3 SPM_DQ8
SPM_A11 A10/AP DQU3 SPM_DQ10 U28D +1.5V_MEM_VDDQ
R8 A11 DQU4 A8
SPM_A12 N8 A3 SPM_DQ11 PAR 4 OF 6
SPM_A13 A12/BC DQU5 SPM_DQ13 SPM_A0 SPM_DQ0
T4 A13 DQU6 B9 AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
T8 A4 SPM_DQ12 SPM_A1 AE16 AA20 SPM_DQ1
A14 DQU7 SPM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) SPM_DQ2
M8 A15 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
+1.5V_MEM_VDDQ SPM_A3 AE15 Y19 SPM_DQ3
SPM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) SPM_DQ4 C9792 R605
AA12 V17
id
SPM_BA0 SPM_A5 MEM_A4(NC) MEM_DQ4(NC) SPM_DQ5
M3 BA0 VDD#B3 B3 AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17 SIDE@1K/F_4
SPM_BA1 N9 D10 A09 SPM_A6 AB14 AA15 SPM_DQ6 SIDE@0.1u/10V_4
SPM_BA2 BA1 VDD#D10 SPM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) SPM_DQ7
M4 BA2 VDD#G8 G8 AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
K3 SPM_A8 AD13 AC20 SPM_DQ8
VDD#K3 SPM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) SPM_DQ9 SPM_VREF1
VDD#K9 K9 AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19
SBD_MEM/DVO_I/F
N2 SPM_A10 AC16 AE22 SPM_DQ10
SPM_CLKP VDD#N2 SPM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) SPM_DQ11
J8 CK VDD#N10 N10 AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
R593 *SIDE@100/F_4 SPM_CLKN K8 R2 SPM_A12 AC14 AB20 SPM_DQ12 C9793 R606
SPM_CKE CK VDD#R2 SPM_A13 MEM_A12(NC) MEM_DQ12(NC) SPM_DQ13
K10 CKE VDD#R10 R10 Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22 SP@1K/F_4
+1.5V_MEM_VDDQ AC22 SPM_DQ14 SIDE@0.1u/10V_4
B
SPM_BA0 MEM_DQ14/DVO_D10(NC) SPM_DQ15 B
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21 R606
SPM_ODT K2 A2 SPM_BA1 AE17
ODT VDDQ#A2 MEM_BA1(NC) W/O side port
SPM_CS#
SPM_RAS#
SPM_CAS#
SPM_WE#
L3
J4
K4
L4
CS
RAS
CAS
WE
VDDQ#A9
VDDQ#C2
VDDQ#C10
VDDQ#D3
VDDQ#E10
A9
C2
C10
D3
E10
nf SPM_BA2
SPM_RAS#
SPM_CAS#
SPM_WE#
AD17
W 12
Y12
AD18
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_W Eb(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W 18
AD20
AE21
SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N
A41
-->change to 0 Ohm
CS00002JB38
F2 SPM_CS# AB13 W 17 SPM_DM0

SPM_DQS0P VDDQ#F2 SPM_CKE MEM_CSb(NC) MEM_DM0(NC) SPM_DM1
F4 DQSL VDDQ#H3 H3 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
SPM_DQS1P C8 H10 SPM_ODT V14
DQSU VDDQ#H10 MEM_ODT(NC) IOPLLVDD18_SIDE_PORT L75 PBY160808T-221Y-N
IOPLLVDD18(NC) AE23 +1.8V 15mA
SPM_CLKP V15 AE24 IOPLLVDD_SIDE_PORT L73 PBY160808T-221Y-N +1.1V 26mA
SPM_DM0 SPM_CLKN MEM_CKP(NC) IOPLLVDD(NC)
E8 DML VSS#A10 A10 W 14 MEM_CKN(NC)
SPM_DM1 D4 B4 AD23 IOPLLVDD18 - memory PLL
DMU VSS#B4 R597 SIDE@40.2/F_4 SPM_COMPP IOPLLVSS(NC) C9794
VSS#E2 E2 AE12 MEM_COMPP(NC) not applicable to RX881
G9 +1.5V_MEM_VDDQ R607 SIDE@40.2/F_4 SPM_COMPN AD12 AE18 SPM_VREF1 SIDE@2.2u/6.3V_6
VSS#G9 MEM_COMPN(NC) MEM_VREF(NC)
Co
+1.5V_MEM_VDDQ SPM_DQS0N G4 J3 C9781
SPM_DQS1N DQSL VSS#J3 SIDE@2.2u/6.3V_6
B8 DQSU VSS#J9 J9
M2 RS880M_A11
R603 SIDE@10K/F_4 VSS#M2
VSS#M10 M10
VSS#P2 P2
[12] SP_DDR3_RST# T3 RESET VSS#P10 P10
VSS#T2 T2
VMA_ZQ L9 T10
ZQ VSS#T10
40 mil~50 mil
R604 B2
VSSQ#B2 +1.5V_MEM_VDDQ +1.5V
SIDE@240/F_4 VSSQ#B10 B10
D2 SIDE@0.1u/10V_4 SIDE@1u/6.3V_4
VSSQ#D2 R598 SIDE@0_6
A
VSSQ#D9 D9 A
VSSQ#E3 E3
J2 E9 C9782 C9783 C9784 C9785 C9786 C9787
NC#J2 VSSQ#E9
L2 NC#L2 VSSQ#F10 F10
J10 G2 SIDE@10u/6.3V_6
NC#J10 VSSQ#G2
L10 NC#L10 VSSQ#G10 G10
100-BALL
SIDE@0.1u/10V_4 SIDE@10u/6.3V_6 SIDE@1u/6.3V_4
PROJECT : ZR8
SDRAM DDR3
SIDE@H5TQ1G63AFR-14C Quanta Computer Inc.
RS880M-HT LINK I/F 1/5 1A

5 4 3 2 1
5 4 3 2 1
PEG_RXP15 D4
U28B
A5 PEG_TXP15_C C669 SW@0.1u/10V_4 PEG_TXP15
[16] PEG_RXN[15:0]
PEG_RXN[15:0] PEG_TXN[15:0]
PEG_TXN[15:0] [16]
09
PEG_RXN15 GFX_RX0P GFX_TX0P PEG_TXN15_C C672 SW@0.1u/10V_4 PEG_TXN15 PEG_RXP[15:0] PEG_TXP[15:0]
PEG_RXP14
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
PEG_TXP14_C C662 SW@0.1u/10V_4 PEG_TXP14
[16] PEG_RXP[15:0] PEG_TXP[15:0] [16]
A3 GFX_RX1P GFX_TX1P A4
PEG_RXN14 B3 B4 PEG_TXN14_C C666 SW@0.1u/10V_4 PEG_TXN14
PEG_RXP13 GFX_RX1N GFX_TX1N PEG_TXP13_C C657 SW@0.1u/10V_4 PEG_TXP13
C2 GFX_RX2P GFX_TX2P C3 Close to North Bridge
PEG_RXN13 C1 B2 PEG_TXN13_C C659 SW@0.1u/10V_4 PEG_TXN13
D
PEG_RXP12 GFX_RX2N GFX_TX2N PEG_TXP12_C C652 SW@0.1u/10V_4 PEG_TXP12 D
E5 GFX_RX3P GFX_TX3P D1
PEG_RXN12 F5 D2 PEG_TXN12_C C654 SW@0.1u/10V_4 PEG_TXN12
G5 GFX_RX4P GFX_TX4P E2
PEG_RXN11 G6 E1 PEG_TXN11_C C640 SW@0.1u/10V_4 PEG_TXN11
H5 GFX_RX5P GFX_TX5P F4
PEG_RXN10 H6 F3 PEG_TXN10_C C642 SW@0.1u/10V_4 PEG_TXN10
J6 GFX_RX6P GFX_TX6P F1
PEG_RXN9 J5 F2 PEG_TXN9_C C644 SW@0.1u/10V_4 PEG_TXN9
J7 H4
PEG_RXN8 J8
GFX_RX7P GFX_TX7P
H3 PEG_TXN8_C C624 SW@0.1u/10V_4 PEG_TXN8
INT. HDMI
PCIE I/F GFX

L5 GFX_RX8P GFX_TX8P H1
PEG_RXN7 L6 H2 PEG_TXN7_C C646 SW@0.1u/10V_4 PEG_TXN7
l
PEG_RXP6 GFX_RX8N GFX_TX8N PEG_TXP6_C C627 SW@0.1u/10V_4 PEG_TXP6 PEG_TXP15_C
M8 GFX_RX9P GFX_TX9P J2 PEG_TXP15_C [25]
PEG_RXN6 L8 J1 PEG_TXN6_C C626 SW@0.1u/10V_4 PEG_TXN6 PEG_TXN15_C
GFX_RX9N GFX_TX9N PEG_TXN15_C [25]
PEG_RXP5 P7 K4 PEG_TXP5_C C649 SW@0.1u/10V_4 PEG_TXP5 PEG_TXP14_C
GFX_RX10P GFX_TX10P PEG_TXP14_C [25]
PEG_RXN5 M7 K3 PEG_TXN5_C C648 SW@0.1u/10V_4 PEG_TXN5 PEG_TXN14_C
tia
PEG_RXP4 P5 K1 PEG_TXP4_C C631 SW@0.1u/10V_4 PEG_TXP4 PEG_TXP13_C
PEG_RXN4 M5 K2 PEG_TXN4_C C628 SW@0.1u/10V_4 PEG_TXN4 PEG_TXN13_C
PEG_RXP3 R8 M4 PEG_TXP3_C C630 SW@0.1u/10V_4 PEG_TXP3 PEG_TXP12_C
PEG_RXN3 P8 M3 PEG_TXN3_C C629 SW@0.1u/10V_4 PEG_TXN3 PEG_TXN12_C
PEG_RXP2 R6 M1 PEG_TXP2_C C638 SW@0.1u/10V_4 PEG_TXP2
PEG_RXN2 GFX_RX13P GFX_TX13P PEG_TXN2_C C637 SW@0.1u/10V_4 PEG_TXN2
R5 GFX_RX13N GFX_TX13N M2
PEG_RXP1 P4 N2 PEG_TXP1_C C633 SW@0.1u/10V_4 PEG_TXP1
P3 GFX_RX14N GFX_TX14N N1
PEG_RXP0 T4 P1 PEG_TXP0_C C650 SW@0.1u/10V_4 PEG_TXP0
T3 GFX_RX15N GFX_TX15N P2
AE3 AC1 PCIE_TXP0_C C658 0.1u/10V_4

[26] PCIE_RX1+ GPP_RX0P GPP_TX0P PCIE_TX1+ [26]
AD4 AC2 PCIE_TXN0_C C655 0.1u/10V_4 To LAN
[26] PCIE_RX1- GPP_RX0N GPP_TX0N PCIE_TX1- [26]
C AE2 GPP_RX1P GPP_TX1P AB4 C
AD3 GPP_RX1N GPP_TX1N AB3
AD1 AA2 PCIE_TXP2_C C651 0.1u/10V_4
[27] PCIE_RXP2 GPP_RX2P GPP_TX2P PCIE_TXP2 [27]
AD2 PCIE I/F GPP AA1 PCIE_TXN2_C C653 0.1u/10V_4 TO WLAN-2
en
[27] PCIE_RXN2 GPP_RX2N GPP_TX2N PCIE_TXN2 [27]
V5 GPP_RX3P GPP_TX3P Y1 T107
W6 GPP_RX3N GPP_TX3N Y2 T108
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2
AA8 AD7 A_TXP0_C C676 0.1u/10V_4 A_TXP0 [11]

[11] A_RXP0 SB_RX0P SB_TX0P
Y8 AE7 A_TXN0_C C677 0.1u/10V_4 A_TXN0 [11]
[11] A_RXN0 SB_RX0N SB_TX0N
AA7 AE6 A_TXP1_C C673 0.1u/10V_4 A_TXP1 [11]
Y7 AD6 A_TXN1_C C674 0.1u/10V_4 A_TXN1 [11]
AA5 PCIE I/F SB AB6 A_TXP2_C C668 0.1u/10V_4 A_TXP2 [11]
AA6 AC6 A_TXN2_C C670 0.1u/10V_4 A_TXN2 [11]
W5 AD5 A_TXP3_C C661 0.1u/10V_4 A_TXP3 [11]
Y5 AE5 A_TXN3_C C665 0.1u/10V_4 A_TXN3 [11]
id
AC8 NB_PCIECALRP R154 1.27K/F_4
PCE_CALRP(PCE_BCALRP) NB_PCIECALRN R147 2K/F_4
PCE_CALRN(PCE_BCALRN) AB8 +1.1V
RS880M_A11
B B
RS880 Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3

nf
DP0
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7

DP1
AUX1 and HPD1
Co
A A
PROJECT : ZR8
RS880M-PCIE I/F 2/5 1A

5 4 3 2 1
5 4 3 2 1
10
U28C
110mA +3V_AVDD_NB F12 A22 LA_DATAP0 [24]
AVDD1(NC) TXOUT_L0P(NC)
UMA use 140 ohm 1%. E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 LA_DATAN0 [24]
20mA +1.8V_AVDDDI_NB F14 A21
AVDDDI(NC) TXOUT_L1P(NC) LA_DATAP1 [24]
Discrete use 133 ohm 1%. G15 AVSSDI(NC) TXOUT_L1N(NC) B21 LA_DATAN1 [24]
4mA +1.8V_AVDDQ_NB H15 B20
Note : Only for RS880 series A11 ASIC errata. H14
AVDDQ(NC) TXOUT_L2P(NC)
A20
LA_DATAP2 [24]
AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) LA_DATAN2 [24]
TXOUT_L3P(NC) A19
E17 B19
CRT/TVOUT
R126 4.7K_4 NBGFX_CLKP C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
C05 F17 Y(DFT_GPIO2)
B03 F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
R127 4.7K_4 NBGFX_CLKN A18
INT_CRT_RED TXOUT_U0N(NC)
[24] INT_CRT_RED G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17
R438 IV@140/F_4 G17 B17
INT_CRT_GRE REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2)
[24] INT_CRT_GRE E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20
R440 150/F_4 F18 D21
D
For Check list JTAG [24] INT_CRT_BLU INT_CRT_BLU E19
GREENb(NC)
BLUE(DFT_GPIO3)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5) D18
D
R442 150/F_4 F19 D19

R434 *4.7K_4 NB_PWRGD_IN BLUEb(NC) TXOUT_U3N(NC)
R153 *4.7K_4 INT_EDIDDATA INT_CRT_HSYNC
+3V
R433 *4.7K_4 INT_EDIDCLK
Only for UMA [24] INT_CRT_HSYNC
INT_CRT_VSYNC
A11 DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) B16 LA_CLK [24]
[24] INT_CRT_VSYNC B11 DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 LA_CLK# [24]
R141 *4.7K_4 HDMI_DDC_DATA E8 D16
+3V VGA (Not [24] INT_DDCDATA
F8
DAC_SDA(PCE_TCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
D17
[24] INT_DDCCLK DAC_SCL(PCE_RCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
applicable to
R160 715/F_6 DAC_RSET_NB G14
RX881) DAC_RSET(PWM_GPIO1)
A13 +1.8V_VDDLTP18_NB 15mA
+1.1V_PLLVDD VDDLTP18(NC)
A12 PLLVDD(NC) VSSLTP18(NC) B13
+1.8V_PLLVDD18 D14
For A11 version
LVTM
PLLVDD18(NC) +1.8V_VDDLT_18_NB
B12 PLLVSS(NC) VDDLT18_1(NC) A15 300mA
PLL PWR
+1.8V B15
l
R119 *SP_A11@49.9/F_4 CLK_SBLINKP +1.8V_VDDA18HTPLL VDDLT18_2(NC)
65mA H17 VDDA18HTPLL VDDLT33_1(NC) A14
R116 *SP_A11@49.9/F_4 CLK_SBLINKN B14
+1.8V_VDDA18PCIEPLL VDDLT33_2(NC)
20mA D7 VDDA18PCIEPLL1
B2-TEST R579 E7 C14
300_4 VDDA18PCIEPLL2 VSSLT1(VSS)
VSSLT2(VSS) D15
tia
[11,24,34] A_RST#_SB D8 SYSRESETb VSSLT3(VSS) C16
NB_PWRGD_IN A10 C18
[12,15] NB_PWRGD_IN POWERGOOD VSSLT4(VSS)
NB_LDT_STOP# C10 C20
PM
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
C12 ALLOW_LDTSTOP VSSLT6(VSS) E20
VSSLT7(VSS) C22
[11] CLK_NB_HTREFP_PR C25 HT_REFCLKP
[11] CLK_NB_HTREFN_PR C24 HT_REFCLKN
[11] CLK_NB_REF_CLKP E11 REFCLK_P/OSCIN(OSCIN)
CLOCKs
[11] CLK_NB_REF_CLKN F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9 INT_LVDS_DIGON [24]
LVDS_BLON(PCE_RCALRP) F7 INT_DPST_PWM [24]
B2-TEST NBGFX_CLKP T2 G12
GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) INT_LVDS_BLON [24]
NBGFX_CLKN T1 GFX_REFCLKN
D06 GPP_REFCLKP
T69 U1 GPP_REFCLKP
C GPP_REFCLKN U2 C
T70 GPP_REFCLKN
CLK_SBLINKP V4
[11] CLK_SBLINKP GPPSB_REFCLKP(SB_REFCLKP)
CLK_SBLINKN V3
[11] CLK_SBLINKN GPPSB_REFCLKN(SB_REFCLKN)
en
INT_EDIDDATA A9
[24] INT_EDIDDATA I2C_DATA
INT_EDIDCLK B9 D9
[24] INT_EDIDCLK
HDMI_DDC_DATA B8
I2C_CLK MIS. TMDS_HPD(NC)
D10
INT_HDMI_HPD [25]
[25] HDMI_DDC_DATA DDC_DATA/AUX0N(NC) HPD(NC)
[25] HDMI_DDC_CLK A8 DDC_CLK/AUX0P(NC)
AUX1P B7 D12 SUS_STAT#_NB
T96 AUX1P(NC) TVCLKIN(PWM_GPIO5) SUS_STAT# [12]
A10 AUX1N A7
T72 AUX1N(NC)
THERMALDIODE_P AE8
+NB_CORE_ON B10 AD8 R88
[39] +NB_CORE_ON STRP_DATA THERMALDIODE_N
*3K_4
G11 D13 TEST_EN
RSVD TESTMODE
RS880_AUX_CAL C8 R172
T17 AUX_CAL(NC) 1.82K/F_4
RS880M_A11
A41 A41
RS880M --- ADD AVDD-DAC Analog
not applicable to RX780
id
L27 +3V_AVDD_NB L61 +1.1V_PLLVDD
STRAP_DEBUG_BUS_GPIO_ENABLEb +3V
PBY160808T-221Y-N
+1.1V
PBY160808T-221Y-N PLLVDD - Graphics PLL
C300 C485
C03 C679
not applicable to +1.8V A41
Enables the Test Debug Bus using GPIO. 2.2u/6.3V_6 2.2u/6.3V_6
RX780
1u/6.3V_4
RS880M L33 +1.8V_VDDLTP18_NB

INT_CRT_VSYNC R158 3K_4 +3V PBY160808T-221Y-N
1 Disable VDDLTP18 - LVDS or DVI/HDMI PLL
0 Enable C318 not applicable to RX780
+1.8V 2.2u/6.3V_6
B A41 B
R174 *Short_4 +1.8V_AVDDDI_NB

AVDDI-DAC Digital
RS880M: Enables Side port memory

RS880M:INT_CRT_HSYNC
nf A41
C312
0.1u/10V_4
+1.8V
A41
L32
PBY160808T-221Y-N
+1.8V_PLLVDD18
PLLVDD18 - Graphics PLL
L62
PBY201209T-221Y-N
C683
4.7u/6.3V_6
C680
0.1u/10V_4
+1.8V_VDDLT_18_NB
VDDLT18 - LVDS or DVI/HDMI

digital
L36 +1.8V_AVDDQ_NB not applicable to RX780
PBY160808T-221Y-N AVDDQ-DAC Bandgap Reference
Selects if Memory SIDE PORT is available or not not applicable to RX780 C324 C327
C335 10U/6.3V_8 2.2u/6.3V_6
1 = Memory Side port Not available 2.2u/6.3V_6
0 = Memory Side port available
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]
A09 +1.8V
Co
INT_CRT_HSYNC R168 *SP@3K_4 +1.8V DDR3 based CPU : Level shifted to 1.8 V on the
A41
R166 SIDE@3K_4
+3V
20mils width +1.8V
R85
Northbridge side using an open-drain buffer and
pulled up to 1.8V_S0 through a 2.2k Ohm 5% resistor
2.2K_4
+1.8V_VDDA18PCIEPLL
on the Northbridge side.
L22
5
PBY160808T-221Y-N VDDA18PCIEPLL -PCIE PLL + U8
C268 2 Open 4 NB_LDT_STOP#

[2,11] CPU_LDT_STOP#
2.2u/6.3V_6 Drain
- 74LVC07
3
For extrnal EEPROM Debug only A41
RS780/RX780/RS880
A
+NB_CORE_ON R436 2K/F_4

20mils width R185 1K_4
A
+1.8V
L34 +1.8V_VDDA18HTPLL
PBY160808T-221Y-N VDDA18HTPLL -HT LINK PLL NB_ALLOW_LDTSTOP
[2,11] CPU_LDT_REQ#
A11
C329
2.2u/6.3V_6 [2,11] ALLOW_LDTSTOP
Display Port interface from PCIeGraphics (RS880/rs880M only)
The RS880 family does not support CLMC architecture PROJECT : ZR8
RS880_AUX_CAL R145 *150/F_4 The LDTREQ# connection from the CPU to
ALLOW_LDTSTOP of the Northbridge is no longer Quanta Computer Inc.
required.
RS880M-SYSTEM I/F 3/5 1A

5 4 3 2 1
5 4 3 2 1
11
AE14
AC3
AC4
M11
AA4
AB5
AB1
AB7
AE1
AE4
AB2
D11
E14
E15
K14
L15
J15
J12
W1
W2
W4
W7
W8
M6
G1
G2
G4
G8
D3
D5
H7
R7
N4
R1
R2
R4
U4
A2
B1
E4
P6
V7
V8
V6
Y6
RX881/RS880 POWER DIFFERENCE TABLE
L1
L2
L4
L7
J4
U28F
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
PIN NAME RX881 RS880 PIN NAME RX881 RS880
VDDHT +1.1V +1.1V IOPLLVDD +1.1V +1.1V
VDDHTRX +1.1V +1.1V AVDD GND +3.3V

PART 6/6
D D
GROUND VDDHTTX +1.2V +1.2V AVDDDI GND +1.8V
VDDA18PCIE +1.8V +1.8V AVDDQ GND +1.8V
VDDG18 +1.8V +1.8V PLLVDD GND +1.1V

VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VDD18_MEM GND +1.8V PLLVDD18 GND +1.8V
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VDDPCIE +1.1V +1.1V VDDA18PCIEPLL +1.8V +1.8V
VDDC +1.1V +1.1V VDDA18HTPLL +1.8V +1.8V
l
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VDD_MEM GND +1.8V/1.5V VDDLTP18 GND +1.8V
VDDG33 +3.3V +3.3V VDDLT18 GND +1.8V
tia
IOPLLVDD18 +1.8V +1.8V VDDLT33 NC NC
+1.1V 2A for RS880M

+1.1V 1.3A for RX881
+1.1V
C VDDPCIE - PCIE-E Main power C
0.6A L31 *Short_8 +1.1V_VDDHT

U28E
+1.1V_VDD_PCIE
2.5A R115 *Short_8
J17 VDDHT_1 VDDPCIE_1 A6 +1.1V
K16 PART 5/6 B6
en
VDDHT_2 VDDPCIE_2
L16 VDDHT_3 VDDPCIE_3 C6
C317 C321 C322 C323 M16 D6 C243 C291 C293 C294 C290
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDHT_4 VDDPCIE_4 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 4.7u/6.3V_6
P16 VDDHT_5 VDDPCIE_5 E6
R16 VDDHT_6 VDDPCIE_6 F6
T16 VDDHT_7 VDDPCIE_7 G7
H8
0.7A L37 *Short_8 +1.1V_VDDHTRX H18 VDDHTRX_1
VDDPCIE_8
VDDPCIE_9 J9
G19 VDDHTRX_2 VDDPCIE_10 K9
F20 M9
+1.1V 2A for RS880M C362 C338 C340 C334 E21
VDDHTRX_3
VDDHTRX_4
VDDPCIE_11
VDDPCIE_12 L9
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 D22 P9
+1.2V 0.4A for Rx881 B23
VDDHTRX_5 VDDPCIE_13
R9
A23 T9
L35 *Short_8 2A +1.1V_VDDHTTX

VDDPCIE_16 V9 0.95~1.1V 10A
+1.1V AE25 VDDHTTX_1 VDDPCIE_17 U9
AD24 VDDC - Core Logic power
id
VDDHTTX_2
AC23 VDDHTTX_3 VDDC_1 K12 NB_CORE
C333 C331 C337 C332 C341 AB22 J14
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDHTTX_4 VDDC_2
AA21 U16
B2-TEST Y20
VDDHTTX_5
VDDHTTX_6
VDDC_3
VDDC_4 J11 C315 C311 C310 C307 C314
W 19 K15 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10U/6.3V_8
POWER
VDDHTTX_7 VDDC_5
V18 VDDHTTX_8 VDDC_6 M12
U17 VDDHTTX_9 VDDC_7 L14
T17 L11
+1.8V 1A for RS780M+SB700 R17
VDDHTTX_10
VDDHTTX_11
VDDC_8
VDDC_9 M13
B +1.8V 1A for RX881 A41 P17 VDDHTTX_12 VDDC_10 M15 B
M17 VDDHTTX_13 VDDC_11 N12
N14
0.7A VDDC_12
+1.8V L24
PBY201209T-221Y-N
C299
4.7u/6.3V_6
C297
4.7u/6.3V_6
C292
0.1u/10V_4
C295
0.1u/10V_4
C287
nf
+1.8V_VDDA18PCIE
0.1u/10V_4
C301
0.1u/10V_4
J10
P10
K10
M10
L10
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
P11
P13
P14
R12
R15
C316
0.1u/10V_4
C308
0.1u/10V_4
C306
0.1u/10V_4
C305
10U/6.3V_8
A09
W9 VDDA18PCIE_6 VDDC_18 T11 C831

H9 VDDA18PCIE_7 VDDC_19 T15
T10 U12 W/O side port
VDDA18PCIE_8 VDDC_20
R10 VDDA18PCIE_9 VDDC_21 T14 -->stuff 0 Ohm
Y9 VDDA18PCIE_10 VDDC_22 J16
AA9 SIDE@0.1u/10V_4 CS00002JB38 SIDE@0.1u/10V_4
VDDA18PCIE_11 +1.5V_VDD_MEM L74
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 +1.5V
AD9 AA11 SIDE@0_8
VDDA18PCIE_13 VDD_MEM2(NC) C832 C833 C831 C836
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
Co
U10 AD10 C834
VDDA18PCIE_15 VDD_MEM4(NC) SIDE@4.7u/6.3V_6
AB10
+1.8V R136 *Short_6 25mA +1.8V_VDDG18_NB F9 VDDG18_1(VDD18_1)
VDD_MEM5(NC)
VDD_MEM6(NC) AC10
G9 SIDE@0.1u/10V_4 SP@0.1u/10V_4
VDDG18_2(VDD18_2)
AE11 H11
VDD18-RS880 I/O Transform C286 AD11
VDD18_MEM1(NC) VDDG33_1(NC)
H12 +3V_VDDG33 R169 *Short_4 60mA +3V VDD_MEM For UMA RS780 only
1U/10V_4 VDD18_MEM2(NC) VDDG33_2(NC)
RS880M_A11 VDD33 - 3.3V I/O Not applicable to RX780
C302 C303 memory I/O transform
0.1u/10V_4 0.1u/10V_4 Not applicable to RX780
+1.8V R171 SIDE@0_6 25mA +1.8V_VDD18_MEM A09

A A
C835
SP@1U/10V_4
C835 PROJECT : ZR8

W/O side port
+1.1V
-->stuff 0 Ohm Quanta Computer Inc.
+1.1V [2,7,8,9,14,38,44] CS00002JB38
+1.8V +1.8V [7,9,15,24,37,42,43,44] Size Document Number Rev
NB_CORE NB_CORE [39,44] RS880M-POWER5/5 1A

5 4 3 2 1
5 4 3 2 1
MINI-PCIE,Card reader
NB & EC
[27,30] PCIE_RST#_SB_R
C350 180P/50V_4
R345 33_4 PCIE_RST#_SB

A_RST#_SB
P1
L1
U34A
PCIE_RST#
SB800 Part 1 of 5
PCICLK0 W2
W1
PCI_CLK0
PCI_CLK1
T59
PCI_CLK1 [15]
12
PCI CLKS
[9,24,34] A_RST#_SB A_RST# PCICLK1/GPO36
W3 PCI_CLK2 PCI_CLK2 [15]
C735 0.1u/10V_4 A_RX0P_C PCICLK2/GPO37 PCI_CLK3
[8] A_RXP0 AD26 A_TX0P PCICLK3/GPO38 W4 PCI_CLK3 [15]
PLACE THESE [8] A_RXN0 C736 0.1u/10V_4 A_RX0N_C AD27 Y1 PCI_CLK4 PCI_CLK4 [15]
C732 0.1u/10V_4 A_RX1P_C A_TX0N PCICLK4/14M_OSC/GPO39 +AVBAT
[8] A_RXP1 AC28 A_TX1P
PCIE AC C733 0.1u/10V_4 A_RX1N_C
COUPLING CAPS
[8]
[8]
A_RXN1
A_RXP2 C728 0.1u/10V_4 A_RX2P_C
AC29
AB29
A_TX1N PCIRST# V2
20MIL R582 499/F_4
D
C729 0.1u/10V_4 A_RX2N_C A_TX2P D
CLOSE TO SB820
[8]
[8]
A_RXN2
A_RXP3 C726 0.1u/10V_4 A_RX3P_C
AB28
AB26
A_TX2N
AA1 C792 20MIL
C727 0.1u/10V_4 A_RX3N_C A_TX3P AD0/GPIO0 R573 10_4 +3VRTC_1
[8] A_RXN3 AB27 A_TX3N AD1/GPIO1 AA4
1U/10V_4
[8] A_TXP0 AE24
AD2/GPIO2 AA3
AB1
20MIL D30
A_RX0P AD3/GPIO3 +3VRTC RB500V-40
[8] A_TXN0 AE23 A_RX0N AD4/GPIO4 AA5 +3VPCU
PCI EXPRESS INTERFACES

[8] A_TXP1 AD25 A_RX1P AD5/GPIO5 AB2
AD24 AB6 D23 1 2 PE_GPIO2_R D28
[8] A_TXN1 A_RX1N AD6/GPIO6
AC24 AB5 Change from 0ohm to 1K RB500V-40
[8] A_TXP2 A_RX2P AD7/GPIO7
AC25 AA6 *SW@RB501V-40 for safty issue
[8] A_TXN2 A_RX2N AD8/GPIO8
[8] A_TXP3 AB25 A_RX3P AD9/GPIO9 AC2
AB24 AC3 R559 +VCCRTC_2
l
[8] A_TXN3 A_RX3N AD10/GPIO10 BOARD_ID0 [13]
AC4 1K/F_4
R481 590/F_4 PCIE_CALRP_SB AD29
AD11/GPIO11
AC1
BOARD_ID1
BOARD_ID2
[13]
[13] A13 20MIL 20MIL
R279 2K/F_4 PCIE_CALRN_SB PCIE_CALRP AD12/GPIO12 +BAT
+1.1V_PCIE_VDDR AD28 PCIE_CALRN AD13/GPIO13 AD1 BOARD_ID3 [13]
AD14/GPIO14 AD2 BOARD_ID4 [13]
tia
AA28 GPP_TX0P AD15/GPIO15 AC6
1
+3V_S5 AA29 AE2 BAT1
GPP_TX0N AD16/GPIO16 BAT_CONN
Y29 GPP_TX1P AD17/GPIO17 AE1
C812 0.1u/10V_4 Y28 AF8
GPP_TX1N AD18/GPIO18 +3V +3V
Y26 AE3
2
GPP_TX2P AD19/GPIO19
5
R580 U36 Y27 AF1 AD23 [15]
33_4 A_RST#_SB GPP_TX2N AD20/GPIO20
2 W 28 GPP_TX3P AD21/GPIO21 AG1
A_RST#_SB_AND 4 W 29 AF2
[16,26,27] A_RST#_AND GPP_TX3N AD22/GPIO22
1 AE9 VDDR_1.05_EN R339
SB_GPIO_PCIE_RST# [12] AD23/GPIO23
VGA,LAN& MINI-IPCIE AA22 AD9 AD24 [15] R330 *2.2K_4
GPP_RX0P AD24/GPIO24
3
C813 TC7SH08FU Y21 AC11 AD25 [15] 2.2K_4

100p/50V_4 GPP_RX0N AD25/GPIO25
AA25 GPP_RX1P AD26/GPIO26 AF6 AD26 [15]
2
AA24 AF4 AD27 [15] Q26
GPP_RX1N AD27/GPIO27 *MMBT3904
C W 23 GPP_RX2P AD28/GPIO28 AF3 C
V24 AH2 SB820_MEMHOT# 1 3
GPP_RX2N AD29/GPIO29 CPU_MEMHOT# [2,5,6]
W 24 GPP_RX3P AD30/GPIO30 AG2
W 25 AH3
en
GPP_RX3N AD31/GPIO31
PCI INTERFACE
CBE0# AA8
CBE1# AD5
CBE2# AD8
CBE3# AA10
FRAME# AE8
DEVSEL# AB9
M23 AJ3 +3V
[9] CLK_SBLINKP PCIE_RCLKP/NB_LNK_CLKP IRDY#
[9] CLK_SBLINKN P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
PAR AC5
[9] CLK_NB_REF_CLKP U29 AF5 R524
NB_DISP_CLKP STOP# SW@2K/F_4
[9] CLK_NB_REF_CLKN U28 NB_DISP_CLKN PERR# AE6
SERR# AE4
[9] CLK_NB_HTREFP_PR T26 NB_HT_CLKP REQ0# AE11
[9] CLK_NB_HTREFN_PR T27 AH5 D17 1 2 PE_GPIO2_R
NB_HT_CLKN REQ1#/GPIO40 PE_GPIO2_R [24]
REQ2#/CLK_REQ8#/GPIO41 AH4
V21 AC12 SW@RB501V-40
id
[2] CLK_CPU_BCLKP_PR CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 T46
[2] CLK_CPU_BCLKN_PR T21 CPU_HT_CLKN GNT0# AD12
R594 *10K_4
+3V A26
GNT1#/GPO44 AJ5 PCH_ODD_EN [28]
[16] CLK_PCIE_VGAP RP11 2 1 SGN@0_4P2R_4 SLT_GFX_CLKP V23 AH6 DGPU_VRON [12,40,41]
SLT_GFX_CLKN SLT_GFX_CLKP GNT2#/GPO45
[16] CLK_PCIE_VGAN 4 3 T23 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AB12 T44
AB11 CLKRUN#_R
CLKRUN# CLKRUN# [34]
[26] CLK_PCIE_LOM L29 GPP_CLK0P LOCK# AD7 T55
UMA don't stuff [26] CLK_PCIE_LOM# L28 GPP_CLK0N A12
INTE#/GPIO32 AJ6 dGPU_PWROK [19]
N29 AG6 R331 *8.2K_4 +3V
GPP_CLK1P INTF#/GPIO33
B
N28 GPP_CLK1N INTG#/GPIO34 AG4 B
INTH#/GPIO35 AJ4 PE_GPIO0 [16]
[27] CLK_PCIE_WLANP_2 M29 GPP_CLK2P A58
+3V
A59
[27] CLK_PCIE_WLANN_2
nf M28
T25
V25
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
CLOCK GENERATOR
LPCCLK0
LPCCLK1
H24
H25
LPC_CLK0
LPC_CLK1
R505
R499
22_4
22_4
LPC_CLK0 [15]
LPC_CLK1 [15]
PCLK_DEBUG [27]
CLK_PCI_775 [34]
L24 GPP_CLK4P LAD0 J27 LPC_LAD0 [27,34]
C533 0.1u/10V_4 L23 J26 C747
GPP_CLK4N LAD1 LPC_LAD1 [27,34]
LPC H29 C750 for EMI
LAD2 LPC_LAD2 [27,34]
5
P25 H28 *5.6p/50V_4 *22p/50V_4 suggestion

GPP_CLK5P LAD3 LPC_LAD3 [27,34]
[13] MEM_1V5 2 M25 GPP_CLK5N LFRAME# G28 LPC_LFRAME# [27,34]
4 J25 LDRQ0#_SB
VDDR_OPT [43] LDRQ0# T34
VDDR_1.05_EN 1 P29 AA18 LDRQ1#_SB
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 T42
R317 P28 AB19
GPP_CLK6N SERIRQ/GPIO48 IRQ_SERIRQ [34]
3
U18 33_4 A62

Co
VDDR_1.05_EN: TC7SH08FU N26 GPP_CLK7P *10K/F_4 R286
1 : VDDR =1.05V N27 +3V_S5
R303 *0_4 GPP_CLK7N
0 : VDDR = 0.9V (Default) ALLOW _LDTSTP/DMA_ACTIVE# G21 ALLOW_LDTSTOP [2,9]
T29 GPP_CLK8P PROCHOT# H21 CPU_PROCHOT# [2]
T28 K19
CPU
GPP_CLK8N LDT_PG CPU_PWRGD_SVID_REG [2,37]

LDT_STP# G22 CPU_LDT_STOP# [2,9]
RTC_X1 A16 J24 CPU_LDT_RST# [2]
LDT_RST#
[16] GN_CLK_VGA_27M_NONSS L25 14M_25M_48M_OSC
3 2 C1 RTC_X1
Y8 32K_X1
INTRUDER_ALERT# Left not connected
32.768KHZ C730 SGN@22P/50V_4 25M_X1 L26 C2 RTC_X2 +AVBAT
25M_X1 32K_X2 (Southbridge has 50-kohm internal
RTC
RTC_X2
pull-up to VBAT).
A 4 1 RTCCLK D2 RTC_CLK [34]
A
2
Y5 B2 INTRUDER_ALERT# R545 *1M/F_4

R546 R480 25M_X2 INTRUDER_ALERT#
L27 25M_X2 VDDBT_RTC_G B1 +AVBAT
*20M_6 SGN@25MHZ SGN@1M_4
1
R547 20M_6 G2
1
SB820M_A12 *SHORT_PAD1 C793
C794 C795 C731 SGN@22P/50V_4

0.1u/10V_4 PROJECT : ZR8
2
18P/50V_4 18P/50V_4
SB820-PCIE/PCI/CPU/LPC 1/4 1A

5 4 3 2 1
5 4 3 2 1
+3V_S5
13
NC only ,Can't be install +3V_S5
[11,13,14,15,24,26,31,32,36,44] +3V_S5 USBCLK/41M_25M_48M_OSC pin is CLK input
R352 *2.2K_4 SB_TEST0 +3V pin when EXT CLKGEN mode.
[2,4,5,6,9,10,11,13,14,15,19,24,25,27,29,30,32,33,34,36,37,38,39,41,42,43,44,46] +3V
R350 *2.2K_4 SB_TEST1
It is output CLK source when INT CLKGEN mode.
R347 *2.2K_4 SB_TEST2 U34D

J2 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC A10 T106
K1 RI#/GEVENT22#
D3 G19 USB_RCOMP_SB R293 11.8K/F_6
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
[34] SUSB# F1 SLP_S3#
[34] SUSC# H1 SLP_S5#
ACPI / WAKE UP EVENTS

[34] DNBSWON# F2
USB 1.1 USB MISC

D +3V SCL0/SDATA0 Clock gen/Robson/TV PW R_BTN# D
is 3V tolerance [15] SB_PWRGD_IN H5 PW R_GOOD SB800
AMD datasheet define it tuner [9] SUS_STAT# G6 SUS_STAT# USB_FSD1P/GPIO186 J10
/DDR2/DDR2 SB_TEST0 B3 Part 4 of 5 H11
R288 2.2K_4 PCLK_SMB SB_TEST1 TEST0 USB_FSD1N
thermal/Accelerometer C4 TEST1/TMS
SB_TEST2 F6 H9 USB_FDS12P
TEST2 USB_FSD0P/GPIO185 T47
R287 2.2K_4 PDAT_SMB AD21 J8 USB_FSD12N
[34] SIO_A20GATE GA20IN/GEVENT0# USB_FSD0N T49
[34] SIO_RCIN# AE21 KBRST#/GEVENT1#
LANLINK_STATE# K2 B12
T94 LPC_PME#/GEVENT3# USB_HSD13P USBP13+ [31]
J29 A12
+3V_S5 SCL1/SDATA1 is 3V/S5 tolerance
[34] SIO_EXT_SMI#
H2
LPC_SMI#/GEVENT23# USB_HSD13N USBP13- [31] USB board
[34] SIO_EXT_SCI# GEVENT5#
AMD datasheet define it SYS_RST# J1 F11
T95 SYS_RESET#/GEVENT19# USB_HSD12P USBP12+ [31]
PCIE_WAKE# H6 E11
USB board
l
[26] PCIE_WAKE# W AKE#/GEVENT8# USB_HSD12N USBP12- [31]
R348 10K_4 SB_SMBCLK1 IR_RX1 F3
T58 IR_RX1/GEVENT20#
R346 10K_4 SB_SMBDATA1 SB_THERMTRIP# J6 E14
[2] CPU_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P
[9,15] NB_PWRGD_IN AC19 NB_PW RGD USB_HSD11N E12
tia
[34] ICH_RSMRST# G1 RSMRST# USB_HSD10P J12 USBP10+ [30]
+3V_S5 SCL2/SDATA2 is 3V/S5 tolerance J14
AMD datasheet define it AD19
USB_HSD10N USBP10- [30] USB card reader
CLK_REQ4#/SATA_IS0#/GPIO64
AA16 CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P A13 USBP9+ [31]
R290 10K_4 SB_SCLK2 AB21 B13
R283 10K_4 SB_SDATA2
[11] SB_GPIO_PCIE_RST#
[26] CLK_PCIE_LAN_REQ# AC18
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N USBP9- [31] BLUETOOTH
MXM_PWR_EN CLK_REQ0#/SATA_IS3#/GPIO60
AF20 SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P D13 USBP8+ [31]
SB_GPIO59 AE19 C13
T37
AF19
SATA_IS5#/FANIN3/GPIO59 USB_HSD8N USBP8- [31] USB board
[29] SPKR SPKR/GPIO66
PCLK_SMB AD22 G12
USB 2.0
+3V [5,6,26,27,46] PCLK_SMB SCL0/GPIO43 USB_HSD7P USBP7+ [27]
PDAT_SMB AE22 G14
[5,6,26,27,46] PDAT_SMB
SB_SMBCLK1 F5
SDA0/GPIO47 USB_HSD7N USBP7- [27] WLAN MINI CARD
SB_SMBDATA1 SCL1/GPIO227
F4 SDA1/GPIO228 USB_HSD6P G16 T61
C R338 4.7K_4 SUS_STAT# AH21 G18 C
[27] CLK_PCIE_2_REQ# CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N T105
R306 *0_4 VGA_REQ#_GPIO61 AB18
[17] VGA_REQ# CLK_REQ1#/FANOUT4/GPIO61
GPIO
E1 IR_LED#/LLB#/GPIO184 USB_HSD5P D16
B2-TEST C04 AJ21 C16
en
+3V SMARTVOLT2/SHUTDOW N#/GPIO51 USB_HSD5N
[7] SP_DDR3_RST# H4 DDR3_RST#/GEVENT7# B2-TEST
D5 GBE_LED0/GPIO183 USB_HSD4P B14
D7 GBE_LED1/GEVENT9# USB_HSD4N A14
G5 GBE_LED2/GEVENT10#
dGPU_VRON R307 K3 E18
2ms GBE_STAT0/GEVENT11# USB_HSD3P
SW@4.7K_4 T41 AA20 CLK_REQG#/GPIO65/OSCIN USB_HSD3N E16
MXM_PWR_EN
USB_HSD2P J16
[19] MXM_PWREN [31] OC_7# H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18
D19 D1
[31] OC_6# USB_OC6#/IR_TX1/GEVENT6#
SW@RB501V-40 R149 *Short_4 E4 B17
USB CAMERA
USB OC
[2,4,33] PM_THERM# USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P USBP1+ [24]
MXM_PWR_EN 1 2 C538 D4 A17
[31] OC_4# USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USBP1- [24]
SW@0.1u/10V_4 SB_JTAG_TDO E8
SB_JTAG_TCK USB_OC3#/AC_PRES/TDO/GEVENT15#
1 2 F7 A16
[11,40,41] DGPU_VRON
SB_JTAG_TDI E7
USB_OC2#/TCK/GEVENT14# USB_HSD0P
B16
USBP0+
USBP0-
[31]
[31]
On board USB connect
D18 SB_JTAG_RST# USB_OC1#/TDI/GEVENT13# USB_HSD0N
F8
id
>1mS delay is required between all MXM power rail stable *SW@RB501V-40 USB_OC0#/TRST#/GEVENT12#
and MXM_PWREN(enables the module internal power) HD audio interface is +3VS5 voltage
R555 *10K/F_4 ACZ_BCLK M3 D25 SB_SCLK2
ACZ_SDOUT AZ_BITCLK SCL2/GPIO193 SB_SDATA2
A14 [15] ACZ_SDOUT
R337 *10K/F_4 ACZ_SDIN0
N1 AZ_SDOUT SDA2/GPIO194 F23
SB_GPIO195
L2 B26
HD AUDIO
R336 *10K/F_4 ACZ_SDIN1 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 SB_GPIO196
M2 AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 E26
R571 *10K/F_4 ACZ_SDIN2 M1 F25
R327 *10K/F_4 ACZ_SDIN3 AZ_SDIN2/GPIO169 EC_PW M0/EC_TIMER0/GPIO197
M4 AZ_SDIN3/GPIO170 EC_PW M1/EC_TIMER1/GPIO198 E22
ACZ_SYNC N2 F22 GPIO199 [15]
B
ACZ_RST# AZ_SYNC EC_PW M2/EC_TIMER2/GPIO199 B
P2 AZ_RST# EC_PW M3/EC_TIMER3/GPIO200 E21 GPIO200 [15]
+3V_S5
+3V
A61
R474
R486
8.2K_4
8.2K_4
CLK_PCIE_LAN_REQ#
CLK_PCIE_2_REQ#
nf R553
R322
R558
10K_4
10K_4
10K_4
GBE_COL
GBE_CRS
GBE_MDIO
T1
T4
L6
L5
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
G24
G25
E28
E29
D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 GBE_RXD3 KSI_6/GPIO207 C29
D03 U3 GBE_RXD2 KSI_7/GPIO208 C28
T2
GBE LAN
GBE_RXD1
U2 GBE_RXD0 KSO_0/GPIO209 B28
EMBEDDED CTRL
T5 A27 SB_GPIO195 R489 10K_4
R343 10K_4 GBE_RXERR GBE_RXCTL/RXDV KSO_1/GPIO210
V5 GBE_RXERR KSO_2/GPIO211 B27
P5 D26 SB_GPIO196 R275 10K_4
GBE_TXCLK KSO_3/GPIO212
M5 GBE_TXD3 KSO_4/GPIO213 A26
Co
P9 GBE_TXD2 KSO_5/GPIO214 C26
T7 GBE_TXD1 KSO_6/GPIO215 A24
ACZ_SDOUT R570 33_4 P7 B25
ACZ_SDOUT_AUDIO [29] GBE_TXD0 KSO_7/GPIO216
M7 GBE_TXCTL/TXEN KSO_8/GPIO217 A25
C815 *10P/50V_4 P4 D24
GBE_PHY_PD KSO_9/GPIO218
M9 GBE_PHY_RST# KSO_10/GPIO219 B24
R344 10K_4 GBE_PHY_INTR V7 C24
ACZ_SYNC R552 33_4 GBE_PHY_INTR KSO_11/GPIO220
ACZ_SYNC_AUDIO [29] KSO_12/GPIO221 B23
ADP_PRES0 E23 A23
T35 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
EMBEDDED CTRL
C800 *10P/50V_4 E24 D22

PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
F21 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22
G29 FC_RST#/GPO160 KSO_16/GPIO225 A22
ACZ_BCLK R569 33_4 B2-TEST B22
ACZ_BITCLK_AUDIO [29] +3V_S5 KSO_17/GPIO226
A D27 PS2KB_DAT/GPIO189
A
C814 *10P/50V_4 F28
CN24 PS2KB_CLK/GPIO190
DEL C816 F29 PS2M_DAT/GPIO191
1 E27 PS2M_CLK/GPIO192
ACZ_RST# R554 33_4 SB_JTAG_TCK
ACZ_RST#_AUDIO [29] 2 SB_JTAG_TDO
3
ACZ_SDIN0 ACZ_SDIN0 [29] 4
SB_JTAG_TDI
SB_TEST1 SB820M_A12 PROJECT : ZR8
5
If the VDDIO_AZ_S power rail is configured for 1.5V_S5
then AZ_SDIN[3:0] can not be connected to 3.3-V devices.
6
7
SB_JTAG_RST# Quanta Computer Inc.
8 Size Document Number Rev
SB820-ACPI/GPIO/USB 2/4 1A
*S/W_JTAG_DEBUG SB JTAG
5 4 3 2 1
5 4 3 2 1
14
SATA PORT 0,1,2,3
can support AHCI +1.1V_AVDD_SATA
[14] +1.1V_AVDD_SATA
mode U34B +3V_S5
[11,12,14,15,24,26,31,32,36,44] +3V_S5
C777 0.01u/16V_4 SATA_TX0+_C AH9

SB800 AH28
[28] SATA_TX0+ SATA_TX0P FC_CLK T80
C775 0.01u/16V_4 SATA_TX0-_C AJ9 Part 2 of 5 AG28
SATA1 [28] SATA_TX0- SATA_TX0N FC_FBCLKOUT
AF26
T81
FC_FBCLKIN T78
[28] SATA_RX0- AJ8 SATA_RX0N
[28] SATA_RX0+ AH8 SATA_RX0P FC_OE#/GPIOD145 AF28 T75
FC_AVD#/GPIOD146 AG29 T77
[28] SATA_TX1+ C774 0.01u/16V_4 SATA_TX1+_C AH10 AG26
D SATA_TX1P FC_W E#/GPIOD148 T82 D
[28] SATA_TX1- C769 0.01u/16V_4 SATA_TX1-_C AJ10 AF27
SATA_TX1N FC_CE1#/GPIOD149 T76
AE29
SATA ODD [28] SATA_RX1- AG10
FC_CE2#/GPIOD150
AF29
T74
TEMPIN0 R519 10K_4
SATA_RX1N FC_INT1/GPIOD144 T79
[28] SATA_RX1+ AF10 SATA_RX1P FC_INT2/GPIOD147 AH27 T84 IF THERE IS NO IDE, TEST
TEMPIN1 R511 10K_4
AG12 AJ27
POINTS FOR DEBUG BUS
SATA_TX2P FC_ADQ0/GPIOD128 T83
AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26 T33 IS MANDATORY MB_THRMDA_SB R521 10K_4
FC_ADQ2/GPIOD130 AH25 T86
AJ12 AH24 SB_GPIO174 R313 10K_4
SATA_RX2N FC_ADQ3/GPIOD131 T85
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23 T90
AH23 SB_GPIO175 R526 10K_4
FC_ADQ5/GPIOD133 T88
AH14 AJ22
l
SATA_TX3P FC_ADQ6/GPIOD134 T91
AJ14 AG21 SB_GPIO176 R523 10K_4
SATA_TX3N FC_ADQ7/GPIOD135 T93
FC_ADQ8/GPIOD136 AF21 T92
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22 T87
FLASH
Signal Name Explanation AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23 T89
tia
FC_ADQ11/GPIOD139 AF23 T97
SB800 A11: 800 ohm 1% resistor to GND. AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24 T98
P/N:CS18062FB00(806 Ohm) AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25 T99
SATA_CALRP SB800 A12: 1k ohm 1% resistor to GND. FC_ADQ14/GPIOD142 AG25 T101
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26 T102
SERIAL ATA
AH17 SATA_RX4P
SB800 A11: 931-? 1% resistor to VDDAN_11_SATA.
AJ18 SATA_TX5P
SATA_CALRN SB800 A12: TBD-? 1% resistor to VDDAN_11_SATA. AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
W7 WWAN_DET#
+1.1V_AVDD_SATA FANIN0/GPIO56 T52
C V9 CPPE_NC1# C
FANIN1/GPIO57 T48
R300 SP_A12@1K/F_4 SATA_CALRP AB14 W8 CRD_REQ1#
SATA_CALRP FANIN2/GPIO58 T54
R298 SP_A12@931/F_4 SATA_CALRN AA14 SATA_CALRN TEMPIN0
B6
en
TEMPIN0/GPIO171 TEMPIN1
TEMPIN1/GPIO172 A6
AD11 A5 MB_THRMDA_SB
[32] SATA_ACT# SATA_ACT#/GPIO67 TEMPIN2/GPIO173
B5 SB_GPIO174
R302 10K_4 TEMPIN3/TALERT#/GPIO174
+3V TEMP_COMM C7
PLACE SATA_CAL
A3 SB_GPIO175
HW MONITOR
RES VERY CLOSE C760 GN@22P/50V_4 SATA_X1 AD16
VIN0/GPIO175
B4 SB_GPIO176
SATA_X1 VIN1/GPIO176
TO BALL OF SB820 VIN2/GPIO177 A4 SIDE_PORT_ID0
2
C5 SIDE_PORT_ID1
Y7 R507 VIN3/GPIO178
A60 GN@25MHZ GN@1M_4 VIN4/GPIO179 A7 MEM_1V5 [11]
VIN5/GPIO180 B7
B8
1
VIN6/GBE_STAT3/GPIO181
AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8
SATA_X2
C754 GN@22P/50V_4 BOARD_ID0 BOARD_ID0 [11]
BOARD_ID1
id
BOARD_ID1 [11]
BOARD_ID2 BOARD_ID2 [11]
SB_GPIO164 J5 G27 BOARD_ID3 BOARD_ID3 [11]
T53 SPI_DI/GPIO164 NC1
SB_GPIO163 E2 Y2 BOARD_ID4
SPI ROM
T60 SPI_DO/GPIO163 NC2 BOARD_ID4 [11]
SB_GPIO162 K4 A55
T56 SPI_CLK/GPIO162
SB_GPIO165 K9
T45 SPI_CS1#/GPIO165
SB_GPIO161 G2
T57 ROM_RST#/GPIO161
+3V R311 10K_4 BOARD_ID0 R314 *10K_4
SB820M_A12
B B
R324 SW@10K_4 BOARD_ID1 R323 *IV@10K_4
A05
nf HYX
ID1
0
ID0
0
A04
R517
R273
SP@10K_4
*SP@10K_4
BOARD_ID2 R304
BOARD_ID3 R274
*SP@10K_4
SP@10K_4
+3V_S5 R528 SP@10K_4 SIDE_PORT_ID0 R316 SP@10K_4
R437 *10K_4 SIDE_PORT_ID1 R320 10K_4 SAM 0 1 R272 *10K_4 BOARD_ID4 R271 10K_4
B2-TEST
ATI 1 0
Board ID
Co
DDR3 Sideport Memory Device BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0
GPIO14 GPIO13 GPIO12 GPIO11 GPIO10
BOARD_ID2 SIDE_PORT_ID1 SIDE_PORT_ID0
Vendor Vendor P/N STN B/S P/N Size GPIO12 GPIO178 GPIO177 JV51-DN
N/A (3-DIMM)
0 (Default) WO/Sideport UMA 14"
(Default)
AKD5LZGTW04 0
Hynix H5TQ1G63BFR-12C (64M*16) 1GB (WO/Sideport) 0 0
JM51-DN W/Sideport Discrete
A 1 N/A (2-DIMM) (Default) (Default) 15.6" (Default) A
AKD5LGGT506 1
Samsung K4W1G1646E-HC12 (64M*16) 1GB (W/Sideport) 0 1
PROJECT : ZR8
SATA/IDE/HWM/SPI 3/4 1A

5 4 3 2 1
5 4 3 2 1
PLACE ALL THE DECOUPLING CAPS ON
15
THIS SHEET CLOSE TO SB AS POSSIBLE.
VDD-- S/B CORE power

VDDQ--3.3V I/O power U34C
131mA SB800 Part 3 of 5 510mA
+3V R325 *Short_8 +3V_VDDIO_PCIGP AH1 N13 +1.1V_VDDCR R295 *Short_6 +1.1V
VDDIO_33_PCIGP_1 VDDCR_11_1 U34E
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15
Y19 N17
CORE S0
VDDIO_33_PCIGP_3 VDDCR_11_3 C526 C527 C522 C525 C517
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13 SB800
C544 C543 C535 C534 C539 AC21 U17 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 Y14 AJ2
*10U/6.3V_8 10U/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDIO_33_PCIGP_5 VDDCR_11_5 VSSIO_SATA_1 VSS_1
AA2 V12 Y16 A28
PCI/GPIO I/O
D VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_2 VSS_2 D
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 AB16 VSSIO_SATA_3 VSS_3 A2
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W 12 A41 AC14 VSSIO_SATA_4 VSS_4 E5
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W 18 AE12 VSSIO_SATA_5 VSS_5 D23
AA9 VDDIO_33_PCIGP_10 AE14 VSSIO_SATA_6 VSS_6 E25
AF7 VDDIO_33_PCIGP_11 xx mA +1.1V_VDDAN_CLK L48
AF9 VSSIO_SATA_7 VSS_7 E6
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 +1.1V AF11 VSSIO_SATA_8 VSS_8 F24
K29 UPB201212T-121Y-N_8 AF13 N15
VDDAN_11_CLK_2 VSSIO_SATA_9 VSS_9
VDDAN_11_CLK_3 J28 AF16 VSSIO_SATA_10 VSS_10 R13
K26 C496 C488 C497 C489 C458 C457 AG8 R17
CLKGEN I/O
VDDAN_11_CLK_4 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 *10U/6.3V_8 VSSIO_SATA_11 VSS_11
VDDAN_11_CLK_5 J21 AH7 VSSIO_SATA_12 VSS_12 T10
AF22 J20 AH11 P10
FLASH I/O
VDDIO_18_FC_1 VDDAN_11_CLK_6 VSSIO_SATA_13 VSS_13
AE25 K21 AH13 V11
l
VDDIO_18_FC_2 VDDAN_11_CLK_7 VSSIO_SATA_14 VSS_14
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 AH16 VSSIO_SATA_15 VSS_15 U15
AC22 VDDIO_18_FC_4 AJ7 VSSIO_SATA_16 VSS_16 M18
AJ11 VSSIO_SATA_17 VSS_17 V19
A41 VDDRF_GBE_S V1 AJ13 VSSIO_SATA_18 VSS_18 M11
tia
AJ16 L12
POWER VDDIO_33_GBE_S M10
VSSIO_SATA_19 VSS_19
VSS_20 L18
L46
43mA A9 VSSIO_USB_1 VSS_21 J7
AE28 B10 P3
GBE LAN
+3V VDDPL_33_PCIE VSSIO_USB_2 VSS_22
PBY160808T-221Y-N K11 V4
C490 C487 VSSIO_USB_3 VSS_23
A41 SB820 without GBE: Connected to GND plane. B9 AD6
PCI EXPRESS
2.2u/6.3V_6 *0.1u/10V_4 VSSIO_USB_4 VSS_24
U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 D10 VSSIO_USB_5 VSS_25 AD4
+1.1V_PCIE_VDDR V22 L9 D12 AB7
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_6 VSS_26
L45
600mA V26 VDDAN_11_PCIE_3 D14 VSSIO_USB_7 VSS_27 AC9
+1.1V V27 VDDAN_11_PCIE_4 D17 VSSIO_USB_8 VSS_28 V8
UPB201212T-121Y-N_8 V28 M6 E9 W9
C495 C502 C479 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 VSSIO_USB_9 VSS_29
V29 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 P8 F9 VSSIO_USB_10 VSS_30 W 10
C478 C477 C481 W 22 F12 AJ28
*10U/6.3V_8 10U/6.3V_8 1U/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDAN_11_PCIE_7 VSSIO_USB_11 VSS_31
C W 26 VDDAN_11_PCIE_8 F14 VSSIO_USB_12 VSS_32 B29 C
F16 VSSIO_USB_13 VSS_33 U4
C9 VSSIO_USB_14 VSS_34 Y18
93mA G11 Y10
en
L54 +3V_VDDPL_SATA VSSIO_USB_15 VSS_35
32mA
GROUND
+3V AD14 VDDPL_33_SATA F18 VSSIO_USB_16 VSS_36 Y12
PBY160808T-221Y-N A21 +3V_VDDIO R292 *Short_6 +3V_S5 D9 Y11
VDDIO_33_S_1 VSSIO_USB_17 VSS_37
AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 H12 VSSIO_USB_18 VSS_38 AA11
C523 C524 AF18 B21 H14 AA12
SERIAL ATA
2.2u/6.3V_6 *0.1u/10V_4 VDDAN_11_SATA_4 VDDIO_33_S_3 C505 C504 C506 VSSIO_USB_19 VSS_39
A41 A41 AH20 K10 H16 G4
3.3V_S5 I/O
VDDAN_11_SATA_2 VDDIO_33_S_4 *0.1u/10V_4 2.2u/6.3V_6 2.2u/6.3V_6 VSSIO_USB_20 VSS_40
AG19 VDDAN_11_SATA_3 VDDIO_33_S_5 L10 H18 VSSIO_USB_21 VSS_41 J4
+1.1V_AVDD_SATA AE18 J9 J11 G8
VDDAN_11_SATA_5 VDDIO_33_S_6 VSSIO_USB_22 VSS_42
L49
567mA AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6 J19 VSSIO_USB_23 VSS_43 G9
+1.1V AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 K12 VSSIO_USB_24 VSS_44 M12
UPB201212T-121Y-N_8 K14 AF25
VSSIO_USB_25 VSS_45
K16 VSSIO_USB_26 VSS_46 H7
C510 C512 C516 C514 C513 113mA K18 AH29
CORE S5
10U/6.3V_8 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 +1.1V_VDDCR_11 R278 *Short_6 +1.1V_S5 VSSIO_USB_27 VSS_47
VDDCR_11_S_1 F26 H19 VSSIO_USB_28 VSS_48 V10
A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26 VSS_49 P6
A19 VDDAN_33_USB_S_2 xx mA C498 C493 VSS_50 N4
A41 A20 M8 Y4 L4
id
VDDAN_33_USB_S_3 VDDIO_AZ_S +VDDIO_AZ EFUSE VSS_51
B18 197mA 1U/10V_4 1U/10V_4 L8
+3.3V_VDDAN_USB VDDAN_33_USB_S_4 VSS_52
B19 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 A11 D8 VSSAN_HW M
658mA B20 B11
USB I/O
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 +1.1V_USB_PHY_R
+3V_S5 L67 C18 M19 M20
PBY160808T-221Y-N VDDAN_33_USB_S_7 VSSXL VSSPL_SYS
C20 VDDAN_33_USB_S_8
C753 C531 C511 C518
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +3V_VDDPL 47mA
For support USB D19 VDDAN_33_USB_S_10 P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
wakeup-->3V_S5 10U/6.3V_8 10U/6.3V_8 1U/10V_4 1U/10V_4 D20 L22 +1.1V_VDDPL 62mA P20 H26
VDDAN_33_USB_S_11 VDDPL_11_SYS_S VSSIO_PCIECLK_2 VSSIO_PCIECLK_15
E19 VDDAN_33_USB_S_12 PLL M22 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA21
B VDDPL_33_USB_S F19 VDDPL_33_USB_S 17mA A41 M24 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17 AA23 B
A41 M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
xx mA C11 VDDAN_11_USB_S_1 VDDAN_33_HW M_S D6 +3V_HWM_VDDAN 5mA P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23
If the VDDIO_AZ_S
+1.1V_S5 L52
PBY160808T-221Y-N
+1.1V_VDDAN_USB
C528
2.2u/6.3V_6
C532
0.1u/10V_4
nf D11 VDDAN_11_USB_S_2
VDDXL_33_S L20
C509 C515
L51
PBY160808T-221Y-N
+3V_S5
P24
P26
T20
T22
T24
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
AA26
AC26
Y20
W 21
W 20
power rail SB820M_A12 *0.1u/10V_4 2.2u/6.3V_6 V20 AE26
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
is configured for J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21
VSSIO_PCIECLK_27 K20
1.5V_S5
then AZ_SDIN[3:0] +3V_VDDPL Part 5 of 5
+3V
A41
can not be
connected to 3.3-V +VDDIO_AZ +1.1V_S5 +1.1V_USB_PHY_R SB820M_A12
devices. L43
Co
PBY160808T-221Y-N
+3V_S5 R315 *Short_6 L53 0_6
C507 C468
*0.1u/10V_4 2.2u/6.3V_6
C521 C520 C530
C541 0.1u/10V_4 0.1u/10V_4 10U/6.3V_8
2.2u/6.3V_6
+3V_S5 A41 +3V_HWM_VDDAN A41

+1.1V_S5 +1.1V_VDDPL +3V_S5 VDDPL_33_USB_S +3V
D04 [2,4,5,6,9,10,11,12,13,15,19,24,25,27,29,30,32,33,34,36,37,38,39,41,42,43,44,46] +3V
+1.1V
A A
[2,7,8,9,10,38,44] +1.1V
+3V_S5
[11,12,13,15,24,26,31,32,36,44] +3V_S5
L56 L47 R289 0_4 +1.1V_S5
[38] +1.1V_S5
PBY160808T-221Y-N PBY160808T-221Y-N
C553 C550 C501 C499

0.1u/10V_4 2.2u/6.3V_6 *0.1u/10V_4 2.2u/6.3V_6 C623
0.1u/10V_4
C469
2.2u/6.3V_6 PROJECT : ZR8
SB820-PWR/DECOUPLING 4/4 1A

5 4 3 2 1
5 4 3 2 1
16
OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.
REQUIRED STRAPS For
internal
SB820M is clock GEN.
supported Gen1
mode only.
D +3V_S5 +3V +3V +3V +3V +3V_S5 +3V_S5 D
A15
R556 R342 R550 R340 R341 R500 R277
*10K_4 *10K_4 *10K_4 *10K_4 10K_4 10K_4 10K_4
[12] GPIO199
[12] GPIO200
[11] LPC_CLK1
[11] LPC_CLK0
l
[11] PCI_CLK4
[11] PCI_CLK3
[11] PCI_CLK2
[11] PCI_CLK1
tia
[12] ACZ_SDOUT
R294 R291
R557 R334 R551 R332 R333 R501 R498 2.2K_4 *2.2K_4
10K_4 10K_4 10K_4 10K_4 *10K_4 10K_4 *GN@10K_4
AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 GPIO200 GPIO199

D02
C This is required as ALLOW Watchdog USE non_Fusion EC INT. CLKGEN H, H=Reserved C
PULL
HIGH the low power mode PCIE Gen2 Timer Enable DEBUG CLOCK MODE ENABLED ENABLED
H, L=SPI ROM
is not supported on STRAPS
en
the SB8xx DEFAULT DEFAULT
PULL FORCE Watchdog IGNORE Fusion EC EXT. CLKGEN L,H=LPC ROM DEFAULT
LOW PERFORMANCE PCIE Gen1 Timer Disable DEBUG CLOCK MODE DISABLED ENABLE
MODE L, L=FWH ROM
STRAPS
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
internal have
pull Hi 10K
+3V_S5
[11,12,13,14,24,26,31,32,36,44] +3V_S5
+1.8V
DEBUG STRAPS [7,9,10,24,37,42,43,44] +1.8V
id
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
B
[11] AD23 B
[11] AD24
[11] AD25
[11]
[11]
AD26
AD27
R549
*2.2K_4
R312
*2.2K_4
R305
*2.2K_4
nf
R310
*2.2K_4
R301
*2.2K_4
NB_PWRGD_IN:
RS880/RX881 = 1.8V;
Do NOT share it with SB_PWRGD when use Internal Clk Gen (Need SB PLL initialize firstly)
+3V_S5 R567 10K_4 POWERGOOD_EC_CPU R568 *Short_4

SB_PWRGD_IN [12]
C809
*2.2U/6.3V_6 NB/SB POWER GOOD CIRCUIT
+1.8V
U38
Co
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 *BAS316 D29 1 5 C802 *0.1u/10V_4
[37,39] CPU_COREPG NC VCC
2
A
USE PCI DISABLE ILA USE FC DISABLE I2C DISABLE PCI
PULL BAS316 D24 3 4 R581 *33_4
PLL AUTORUN PLL ROM MEM BOOT [4,34] PWROK_EC GND Y NB_PWRGD_IN [9,12]
HIGH *NL17SZ17DFT2G
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT SOT-353
A63 AL17SZ17000 IC(5P) NL17SZ17DFT2G(SOT-353) SOT-353

PULL BYPASS ENABLE ILA BYPASS FC ENABLE I2C ROM ENABLE PCI
B2-TEST ALUC1G17000 IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5) SOT23-5
LOW PCI PLL AUTORUN PLL use REQ3# as SDA MEM BOOT
A use GNT3# as SCL A
PROJECT : ZR8
SB820-STRAPS 1A

5 4 3 2 1
5 4 3 2 1
17
D D
Park XT U23A +3V_D

+3V_D [17,19,21,24,25]
+1V
+1V [17,19,20,42]
P/N:AJ077400T08
AA38 Y33 PEG_RXP0_C C139 SW@0.1u/10V_4

[8] PEG_TXP0 PCIE_RX0P PCIE_TX0P PEG_RXN0_C PEG_RXP0 [8]
Y37 Y32 C155 SW@0.1u/10V_4
[8] PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 [8]
PEG_RXP1_C C131 SW@0.1u/10V_4
l
[8] PEG_TXP1 Y35 W33 PEG_RXP1 [8]
PCIE_RX1P PCIE_TX1P PEG_RXN1_C C137 SW@0.1u/10V_4
[8] PEG_TXN1 W36 W32 PEG_RXN1 [8] Add extra OSC for use SB clock.
PCIE_RX1N PCIE_TX1N
W38 U33 PEG_RXP2_C C129 SW@0.1u/10V_4

V37 U32 C120 SW@0.1u/10V_4
tia
R62 *SPE@10K_4
PEG_RXP3_C [17] GPIO24_TRSTB
V35 U30 C116 SW@0.1u/10V_4
U36 U29 C111 SW@0.1u/10V_4 R71 *SW@10K_4 +3V_D
[8] PEG_TXN3 PCIE_RX3N PCIE_TX3N PEG_RXN3 [8] [17] GPIO27_TMS
R109 *SPE@0_4
PEG_RXP4_C [17] GPIO26_TCK GN_CLK_VGA_27M_NONSS [11]
U38 T33 C109 SW@0.1u/10V_4
T37 T32 C103 SW@0.1u/10V_4 R33 *SW@10K_4 +3V_D
[8] PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 [8] [18] TESTEN
PCI EXPRESS INTERFACE

T35 T30 PEG_RXP5_C C99 SW@0.1u/10V_4 B2-TEST
R36 T29 C94 SW@0.1u/10V_4
JTAG SIGNAL STUFF OPTION FOR OPTION2
R38 P33 PEG_RXP6_C C89 SW@0.1u/10V_4
P37 P32 C83 SW@0.1u/10V_4
C SIGNALS NORMAL MODE JTAG MODE (DEBUG) C
P35 P30 PEG_RXP7_C C82 SW@0.1u/10V_4
N36 P29 C76 SW@0.1u/10V_4
GPIO24_TRSTB "0" (PD) "1" (PU)
N38 N33 PEG_RXP8_C C70 SW@0.1u/10V_4
[8] PEG_TXP8 PCIE_RX8P PCIE_TX8P PEG_RXP8 [8]
en
M37 N32 PEG_RXN8_C C68 SW@0.1u/10V_4
GPIO27_TMS "1" (PU) "1" (PU)
M35 N30 PEG_RXP9_C C67 SW@0.1u/10V_4
L36 N29 C60 SW@0.1u/10V_4
GPIO26_TCK CLK "1" (PU)
L38 L33 PEG_RXP10_C C58 SW@0.1u/10V_4
K37 L32 C55 SW@0.1u/10V_4
TESTEN "1" (PU) "1" (PU)
K35 L30 PEG_RXP11_C C53 SW@0.1u/10V_4
J36 L29 C50 SW@0.1u/10V_4
J38 K33 PEG_RXP12_C C43 SW@0.1u/10V_4

H37 K32 C48 SW@0.1u/10V_4
H35 J33 PEG_RXP13_C C40 SW@0.1u/10V_4

G36 J32 C42 SW@0.1u/10V_4
id
+3V_D
G38 K30 PEG_RXP14_C C34 SW@0.1u/10V_4
F37 K29 C36 SW@0.1u/10V_4
R73
F35 H33 PEG_RXP15_C C38 SW@0.1u/10V_4
E37 H32 C37 SW@0.1u/10V_4 SW@10K_4
dGPU_PCIE_RST# D2 2 1 BAS316
CLOCK A_RST#_AND [11,26,27]
[11] CLK_PCIE_VGAP AB35

B PCIE_REFCLKP D3 2
B
AA36 1 BAS316
[11] CLK_PCIE_VGAN PCIE_REFCLKN For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V PE_GPIO0 [11]
For Broadway, Madison and Park CALIBRATION

AJ21 Y30 R26 SW@1.27K/F_4
B2-TEST
the PWRGOOD ball must be conneccted to ground
[24] dGPU_PCIE_RST#
R38 SW@10K_4
dGPU_PCIE_RST#
AK21
AH16
AA30
NC#1
NC#2
PWRGOOD
PERSTB
nf PCIE_CALRP
PCIE_CALRN
Y29 R23 SW@2K/F_4 +1V +1.0V FORM RB501 CHANGE TO BAS316
SPE@Madison/Broadway_M2
Co
A A
PROJECT : ZR8
Madison/Broadway-PCIE I/F 1A

5 4 3 2 1
5 4 3 2 1
[19,20,21,43] +1.8V_GPU
+1.8V_GPU
+1V
U23B
TXCAP_DPA3P
AU24 EXT_HDMICLK+ [25]
U23G
LVDS CONTROL
VARY_BL
AK27
R44
R51
SW@10K_4
SW@10K_4
EV_LVDS_BRIGHT [24]
18
[16,19,20,42] +1V AV23 EXT_HDMICLK- [25] AJ27 EV_LVDS_VDDEN [24]
+3V_D TXCAM_DPA3N DIGON
[16,19,21,24,25] +3V_D
AT25 EXT_HDMITX0P [25]
MUTI GFX TX0P_DPA2P
AR24 EXT_HDMITX0N [25]
DPA TX0M_DPA2N
AU26 EXT_HDMITX1P [25] AK35
TX1P_DPA1P TXCLK_UP_DPF3P
AV25 EXT_HDMITX1N [25] AL36
TX1M_DPA1N TXCLK_UN_DPF3N
AR8 AT27 EXT_HDMITX2P [25] AJ38
DVPCNTL_MVP_0 TX2P_DPA0P TXOUT_U0P_DPF2P
AU8 AR26 EXT_HDMITX2N [25] AK37
DVPCNTL_MVP_1 TX2M_DPA0N TXOUT_U0N_DPF2N
D For Park-M2 NC pin AP8
DVPCNTL_0 DPF D
AW8 AR30 AH35
DVPCNTL_1 TXCBP_DPB3P TXOUT_U1P_DPF1P
AR3
DVPCNTL_2 TXCBM_DPB3N
AT29
TXOUT_U1N_DPF1N
AJ36 For dual link panel
AR1
GPU Power-on sequence [21] RAM_STRAP0 AU1
DVPCLK
DVPDATA_0 TX3P_DPB2P
AV31
TXOUT_U2P_DPF0P
AG38
A17 [21] RAM_STRAP1 AU3
DVPDATA_1 DPB TX3M_DPB2N
AU30
TXOUT_U2N_DPF0N
AH37
AW3
1 => +3V_D [21] RAM_STRAP2
AP6
DVPDATA_2
AR32
TXOUT_U3P
AF35
T16 AW5 AT31 AG36
2 => +VGPU_CORE AU5
AR6
DVPDATA_4
DVPDATA_5
TX4M_DPB1N
AT33
TXOUT_U3N
3 => +VGPU_IO 1.8V GPIO AW6
AU6
DVPDATA_7 TX5M_DPB0N
AU32 LVTMDP
DVPDATA_8
4 => +1V AT7
AV7
DVPDATA_9
DVPDATA_10
TXCCP_DPC3P
TXCCM_DPC3N
AU14
AV13 T64 TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AP34
AR34
EV_TXLCLKOUT+ [24]
EV_TXLCLKOUT- [24]
AN7 T62
5 => +1.5V_GPU AV9
DVPDATA_11
DVPDATA_12 TX0P_DPC2P
AT15
TXOUT_L0P_DPE2P
AW37 EV_TXLOUT0+ [24]
T65
l
AT9 AR14 AU35 EV_TXLOUT0- [24]
6 => +1.8V_GPU AR10
AW10
DVPDATA_13
DVPDATA_14 DPC
TX0M_DPC2N
AU16
T63 TXOUT_L0N_DPE2N
AR37
DVPDATA_15 TX1P_DPC1P TXOUT_L1P_DPE1P EV_TXLOUT1+ [24]
7 => dGPU_PWROK AU10
AP10
DVPDATA_16 TX1M_DPC1N
AV15 T66
T67
DPE
TXOUT_L1N_DPE1N
AU39 EV_TXLOUT1- [24] For Singal link panel
DVPDATA_17
AV11 AT17 AP35 EV_TXLOUT2+ [24]
DVPDATA_18 TX2P_DPC0P T68 TXOUT_L2P_DPE0P
tia
For Park-M2 NC pin AT11
DVPDATA_19 TX2M_DPC0N
AR16
T71 TXOUT_L2N_DPE0N
AR35 EV_TXLOUT2- [24]
AR12
DVPDATA_17 ~ DVPDATA_23 DVPDATA_20
AW12 AU20 AN36
DVPDATA_21 TXCDP_DPD3P TXOUT_L3P
AU12 AT19 AP37
DVPDATA_22 TXCDM_DPD3N TXOUT_L3N
AP12
+3V_D DVPDATA_23
AT21
TX3P_DPD2P
AR20
TX3M_DPD2N
DPD
DP Channel D is NC on PARK
AU22
TX4P_DPD1P SPE@Madison/Broadway_M2
AV21
R66 *SW@10K_4 EV_LVDS_BLON R37 R57 TX4M_DPD1N
+3V_D
SW@10K_4 SW@10K_4 I2C AT23
R65 *SW@10K_4 TX5P_DPD0P
AR22
TX5M_DPD0N
AK26
SCL
AJ26
SDA
A36
AD39 EXT_CRT_RED [24]
GENERAL PURPOSE I/O R
C AD37 C
RB
[21] GPU_GPIO0 AH20
GPIO_0
[21] GPU_GPIO1 AH18 AE36 EXT_CRT_GRE [24]
GPIO_1 G
[21] GPU_GPIO2 AN16 AD35
GPIO_2 GB
[21] GPIO3_SMBDAT AH23
GPIO_3_SMBDATA
[21] GPIO4_SMBCLK AJ23 AF37 EXT_CRT_BLU [24]
GPIO_4_SMBCLK B
en
T100 AH17 AE38
GPIO_5_AC_BATT DAC1 BB
A18EV_LVDS_BLON
T36 AJ17
GPIO_6
AK17 AC36 R399 R398 R397
[24] EV_LVDS_BLON GPIO_7_BLON HSYNC EXT_HSYNC [21,24]
[21] SOUT_GPIO8 AJ13 AC38 EXT_VSYNC [21,24] SW@150/F_4 SW@150/F_4 SW@150/F_4
GPIO_8_ROMSO VSYNC
[21] SIN_GPIO9 AH15
GPIO_9_ROMSI
[21] SCLK_GPIO10 AJ16
GPIO_10_ROMSCK R34 SW@499/F_4
[21] GPU_GPIO11 AK16 AB34
GPIO_11 RSET
[21] GPU_GPIO12 AL16
GPIO_12 AVDD +1.8V_GPU
[21] GPU_GPIO13 AM16
GPIO_13 AVDD
AD34 A41
T10 AM14 AE34
+3V_D GPIO_14_HPD2 AVSSQ
[41] GPU_VID1 AM13
GPIO_15_PWRCNTL_0 (1.8V@70mA AVDD)
A18 AK14 AC33 VDD1DI 120 ohm/300mA
T14 GPIO_16_SSIN VDD1DI
AG30 AC34 AVDD L8 SW@BLM15BB121SS1
[21] ALT#_GPIO17 GPIO_17_THERMAL_INT VSS1DI
T12 AN14
R409 GPIO_18_HPD3
A21 [4] TEMP_FAIL AM17
GPIO_19_CTF
*SW@10K/F_4 AL13 AC30 C184 C178 C169
[41] GPU_VID2 GPIO_20_PWRCNTL_1 R2
A18 T11 AJ14 AC31 SW@0.1u/10V_4 SW@1U/6.3V_4 SW@10U/6.3V_6
GPIO_21_BB_EN R2B
[21] SCS#_GPIO22 AK13
GPIO_22_ROMCSB A41
[12] VGA_REQ# AN13 AD30
GPIO24_TRSTB GPIO_23_CLKREQB G2
[16] GPIO24_TRSTB AM23
JTAG_TRSTB G2B
AD31 (1.8V@100mA VDD1DI)
GPIO25_TDI AN23 120 ohm/300mA
T104 JTAG_TDI
R403 GPIO26_TCK AK23 AF30 VDD1DI L3 SW@BLM15BB121SS1
id
[16] GPIO26_TCK GPIO27_TMS JTAG_TCK B2
*SW@10K/F_4 AL24 AF31
[16] GPIO27_TMS GPIO28_TDO JTAG_TMS B2B
JTAG DEBUG PORT AM24
+3V_D JTAG_TDO C134 C119 C102
AJ19
GENERICA SW@0.1u/10V_4 SW@1U/6.3V_4 SW@10U/6.3V_6
AK19 AC32
R78 *SW@10K_4 GPIO24_TRSTB GENERICB C
AJ20 AD32
GENERICC Y
R77 *SW@10K_4 GPIO26_TCK
For Park-M2 is NC pin AK20
GENERICD COMP
AF32
AJ24
GENERICE_HPD4 DAC2
AH26
R75 *SW@10K_4 GPIO27_TMS GENERICF T5
[25] EXT_HDMI_HPD AH24 AD29
GENERICG H2SYNC
AC29 V2SYNC [21]
R63 *SW@10K_4 GPIO25_TDI V2SYNC
AK24
B
R76 *SW@10K_4 GPIO28_TDO +1.8V_GPU HPD1 VDD1DI B
AG31
VDD2DI
AG32
VSS2DI
R104 AG33 +3V_D (3.3V@130mA A2VDD)
R61 SW@10K_4
A41
GPIO26_TCK
nf SW@499/F_4
R105 C226
VREFG AH13
VREFG
A2VDD
A2VDDQ
A2VSSQ
AD33
AF33
AA29
A2VDDQ
R29
C158
SW@0.1u/10V_4
SW@249/F_4 SW@0.1u/10V_4 R2SET SW@715/F_4

+1.8V(75mA)
120 ohm/300mA
L10 SW@BLM15BB121SS1 DPLL_PVDD DDC/AUX AM26
+1.8V_GPU DDC1CLK EV_HDMI_DDCCK [25]
PLL/CLOCK AN26
DPLL_PVDD AM32
DPLL_PVDD
DDC1DATA EV_HDMI_DDCDAT [25]
HDMI
C200 C201 C185 AN32 AM27 A41
SW@10U/6.3V_6 SW@1U/10V_4 SW@0.1u/10V_4 DPLL_PVSS AUX1P +1.8V_GPU
AL27
AUX1N
(1.8V@2mA A2VDDQ)
A41 DPLL_VDDC AN31 AM19 120 ohm/300mA
C617 SW@18P/50V_4 DPLL_VDDC DDC2CLK A2VDDQ L7 SW@BLM15BB121SS1
AL19
DDC2DATA
+1.0V(125mA)
Co 2
120 ohm/300mA XTALI_27M AV33 AN20

L12 SW@BLM15BB121SS1 DPLL_VDDC Y3 R404 XTALO_27M XTALIN AUX2P C135 C187
+1V AU34 AM20
SW@1M/F_4 XTALOUT AUX2N SW@0.1u/10V_4 SW@1U/6.3V_4
SW@27MHZ AL30
1
C205 C211 C186 DDCCLK_AUX3P T13

AM30
SW@10U/6.3V_6 SW@1U/10V_4 SW@0.1u/10V_4 DDCDATA_AUX3N T15
C616 SW@18P/50V_4 AL29
DDCCLK_AUX4P
A41 [21] GPU_D+ AF29
DPLUS THERMAL DDCDATA_AUX4N
AM29 DDCXX_AUX4X is NC on PARK
[21] GPU_D- AG29
DMINUS
+1.8V(5mA) DDCCLK_AUX5P
AN21 EV_LVDS_DDCCLK [24]
+1.8V_GPU L6
120 ohm/300mA
SW@BLM15BB121SS1 TS_VDD T7 AK32
DDCDATA_AUX5N
AM21 EV_LVDS_DDCDAT [24] LVDS
TS_VDD TS_FDO
AJ32 AJ30 EV_CRTDCLK [24]
TSVDD DDC6CLK
C180 C181
AJ33
TSVSS DDC6DATA
AJ31 EV_CRTDDAT [24] CRT
A SW@10U/6.3V_6 SW@0.1u/10V_4 AK30 A
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
AK29 DDCXX_AUX7X is NC on PARK and M9X
PROJECT : ZR8
Madison/Broadway-HOST I/F 1A

5 4 3 2 1
5 4 3 2 1
19
VMA_DQ[63..0] VMB_DQ[63..0]
[22] VMA_DQ[63..0] [23] VMB_DQ[63..0]
VMA_DM[7..0] VMB_DM[7..0]
[22] VMA_DM[7..0] [23] VMB_DM[7..0]
U23C U23D
VMA_RDQS[7..0] DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
[22] VMA_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3 [23] VMB_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3
VMA_WDQS[7..0] DDR3 DDR3 VMB_WDQS[7..0] DDR3 DDR3
[22] VMA_WDQS[7..0] VMA_DQ0 VMA_MA0 [23] VMB_WDQS[7..0] VMB_DQ0 VMB_MA0
C37 G24 C5 P8
VMA_DQ1 DQA0_0/DQA_0 MAA0_0/MAA_0 VMA_MA1 VMB_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMB_MA1
C35 J23 C3 T9
MEMORY INTERFACE A
VMA_DQ2 DQA0_1/DQA_1 MAA0_1/MAA_1 VMA_MA2 VMB_MA[13..0] VMB_DQ2 DQB0_1/DQB_1 MAB0_1/MAB_1 VMB_MA2
A35 H24 E3 P9
MEMORY INTERFACE B
D VMA_MA[13..0] VMA_DQ3 DQA0_2/DQA_2 MAA0_2/MAA_2 VMA_MA3 [23] VMB_MA[13..0] VMB_DQ3 DQB0_2/DQB_2 MAB0_2/MAB_2 VMB_MA3 D
[22] VMA_MA[13..0] E34 J24 E1 N7
G32 H26 F1 N8
D33 J26 F3 N9
F32 H21 F5 U9
E32 G21 G4 U8
D31 H19 H5 Y9
F30 H20 H6 W9
C30 L13 J4 AC8
A30 G16 K6 AC9
F28 J16 K5 AA7
VMA_DQ13 DQA0_12/DQA_12 MAA1_4/MAA_12 VMA_BA2 VMB_DQ13 DQB0_12/DQB_12 MAB1_4/MAB_12 VMB_BA2
C28 H16 VMA_BA2 [22] L4 AA8 VMB_BA2 [23]
VMA_DQ14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 VMA_BA0 VMB_DQ14 DQB0_13/DQB_13 MAB1_5/BA2 VMB_BA0
A28 J17 VMA_BA0 [22] M6 Y8 VMB_BA0 [23]
VMA_DQ15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 VMA_BA1 VMB_DQ15 DQB0_14/DQB_14 MAB1_6/BA0 VMB_BA1
E28 H17 VMA_BA1 [22] M1 AA9 VMB_BA1 [23]
VMA_DQ16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 VMB_DQ16 DQB0_15/DQB_15 MAB1_7/BA1
D27 M3
VMA_DQ17 DQA0_16/DQA_16 VMA_DM0 VMB_DQ17 DQB0_16/DQB_16 VMB_DM0
F26 A32 M5 H3
VMA_DQ18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 VMA_DM1 VMB_DQ18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 VMB_DM1
C26 C32 N4 H1
VMA_DQ19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 VMA_DM2 VMB_DQ19 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 VMB_DM2
l
A26 D23 P6 T3
F24 E22 P5 T5
C24 C14 R4 AE4
A24 A14 T6 AF5
E24 E10 T1 AK6
C22 D9 U4 AK5
VMA_DQ25 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 VMB_DQ25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
tia
A22 V6
VMA_DQ26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 VMA_RDQS0 VMB_DQ26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 VMB_RDQS0
F22 C34 V1 F6
VMA_DQ27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 VMA_RDQS1 VMB_DQ27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 VMB_RDQS1
D21 D29 V3 K3
A20 D25 Y6 P3
F20
DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3
E20 QSA[7..0] Y1
DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3
V5 QSB[7..0]
VMA_DQ30 D19 E16 VMA_RDQS4 VMB_DQ30 Y3 AB5 VMB_RDQS4
E18 E12 Y5 AH1
C18 J10 AA4 AJ9
A18 D7 AB6 AM5
VMA_DQ34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQ34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
F18 AB1
VMA_DQ35 DQA1_2/DQA_34 VMA_WDQS0 VMB_DQ35 DQB1_2/DQB_34 VMB_WDQS0
D17 A34 AB3 G7
VMA_DQ36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 VMA_WDQS1 VMB_DQ36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 VMB_WDQS1
A16 E30 AD6 K1
F16 E26 AD1 P1
D15
DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3
C20 QSA#[7..0] AD3
DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3
W4 QSB#[7..0]
VMA_DQ39 E14 C16 VMA_WDQS4 VMB_DQ39 AD5 AC4 VMB_WDQS4
F14 C12 AF1 AH3
D13 J11 AF3 AJ8
C F12 F8 AF6 AM3 C
VMA_DQ43 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 VMB_DQ43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 AG4
VMA_DQ44 DQA1_11/DQA_43 VMB_DQ44 DQB1_11/DQB_43
D11 J21 VMA_ODT0 [22] AH5 T7 VMB_ODT0 [23]
VMA_DQ45 DQA1_12/DQA_44 ADBIA0/ODTA0 VMB_DQ45 DQB1_12/DQB_44 ADBIB0/ODTB0
F10 G19 VMA_ODT1 [22] AH6 W7 VMB_ODT1 [23]
VMA_DQ46 DQA1_13/DQA_45 ADBIA1/ODTA1 VMB_DQ46 DQB1_13/DQB_45 ADBIB1/ODTB1
A10 AJ4
C10 H27 VMA_CLKP0 [22] AK3 L9 VMB_CLKP0 [23]
DQA1_15/DQA_47 CLKA0 DQB1_15/DQB_47 CLKB0
en
VMA_DQ48 G13 G27 VMB_DQ48 AF8 L8
VMA_DQ49 DQA1_16/DQA_48 CLKA0B VMA_CLKN0 [22] VMB_DQ49 DQB1_16/DQB_48 CLKB0B VMB_CLKN0 [23]
H13 AF9
J13 J14 VMA_CLKP1 [22] AG8 AD8 VMB_CLKP1 [23]
VMA_DQ51 DQA1_18/DQA_50 CLKA1 VMB_DQ51 DQB1_18/DQB_50 CLKB1
H11 H14 VMA_CLKN1 [22] AG7 AD7 VMB_CLKN1 [23]
VMA_DQ52 DQA1_19/DQA_51 CLKA1B VMB_DQ52 DQB1_19/DQB_51 CLKB1B
G10 AK9
G8 K23 VMA_RAS0# [22] AL7 T10 VMB_RAS0# [23]
VMA_DQ54 DQA1_21/DQA_53 RASA0B VMB_DQ54 DQB1_21/DQB_53 RASB0B
K9 K19 VMA_RAS1# [22] AM8 Y10 VMB_RAS1# [23]
VMA_DQ55 DQA1_22/DQA_54 RASA1B VMB_DQ55 DQB1_22/DQB_54 RASB1B
K10 AM7
G9 K20 VMA_CAS0# [22] AK1 W10 VMB_CAS0# [23]
+1.5V_GPU VMA_DQ57 DQA1_24/DQA_56 CASA0B VMB_DQ57 DQB1_24/DQB_56 CASB0B
A8 K17 VMA_CAS1# [22] AL4 AA10 VMB_CAS1# [23]
VMA_DQ58 DQA1_25/DQA_57 CASA1B +1.5V_GPU VMB_DQ58 DQB1_25/DQB_57 CASB1B
C8 AM6
E8 K24 VMA_CS0# [22] AM1 P10 VMB_CS0# [23]
VMA_DQ60 DQA1_27/DQA_59 CSA0B_0 VMB_DQ60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
VMA_DQ61 DQA1_28/DQA_60 CSA0B_1 VMB_DQ61 DQB1_28/DQB_60 CSB0B_1
C6 AP3
R382 VMA_DQ62 DQA1_29/DQA_61 VMB_DQ62 DQB1_29/DQB_61
Ra E6
DQA1_30/DQA_62 CSA1B_0
M13 VMA_CS1# [22] AP1
DQB1_30/DQB_62 CSB1B_0
AD10 VMB_CS1# [23]
SW@40.2/F_4 VMA_DQ63 A5 K16 Ra R28 VMB_DQ63 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 SW@40.2/F_4 DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 U10
MVREFSA MVREFDA CKEA0 VMA_CKE0 [22] MVREFDB CKEB0 VMB_CKE0 [23]
L20 J20 VMA_CKE1 [22] Y12 AA11 VMB_CKE1 [23]
C575 MVREFSA CKEA1 MVREFSB MVREFDB CKEB1
AA12
R16 SPE@243/F_4 L27 MVREFSB
K26 VMA_WE0# [22] N10 VMB_WE0# [23]
R381 SW@0.1u/10V_4 R22 *SPE@243/F_4 N12 MEM_CALRN0 WEA0B C118 WEB0B
Rb +1.5V_GPU L15 Rb AB11
id
MEM_CALRN1 WEA1B VMA_WE1# [22] WEB1B VMB_WE1# [23]
R36 SPE@243/F_4AG12 R27 SW@0.1u/10V_4
SW@100/F_4 MEM_CALRN2 SW@100/F_4
VMA_MA13 VMB_MA13
GDDR5
R17 *SPE@243/F_4 M12 H23 AD28 T8
GDDR5
MEM_CALRP1 MAA0_8 [16] TESTEN TESTEN MAB0_8
R20 SPE@243/F_4 M27 J19 A19 W8
R81 SPE@243/F_4 AH12 MEM_CALRP0 MAA1_8 MAB1_8
AK10
MEM_CALRP2 R30 CLKTESTA DRAM_RST
AL10 AH11
+1.5V_GPU SW@10K_4 CLKTESTB DRAM_RST
Default Madison
+1.5V_GPU
AL31 B2-TEST R83 R82
RSVD
*SW@0_4 *SW@0_4
Ra R379 +1.5V_GPU
B B
SW@40.2/F_4 SPE@Madison/Broadway_M2 Ra R102 SPE@Madison/Broadway_M2 A19
SW@40.2/F_4
Re Default Madison
For PARK For Madison MVREFSB R108
Rd *SW@4.7K_4
Rb R380
SW@100/F_4
C574
SW@0.1u/10V_4 MEM_CALRNP0
MEM_CALRNP1 stuff
stuff
nf Rb R103
SW@100/F_4
C225
SW@0.1u/10V_4
DRAM_RST
Ca
R107 SPE@51/F_4
C229
R106
SW@10K/F_4
MEM_RST# [22,23]
SPE@68P/50V_4
MEM_CALRNP2 stuff Rc
For M97,Broadway,madison & PARK only.
Designator For M97-M2 For Mannhatton

DDR3/GDDR3 Memory Stuff Option
+1.5V_GPU
Co
+1.5V_GPU [19,22,23,40,43]
GDDR5 GDDR3 DDR3(Default) Rc 10K 10K
+1.5V_VGA 1.5V 1.8V/1.5V 1.5V Rd 0R/Short 51R
Ra 40.2R 40.2R 40.2R Re DNI DNI
Rb 100R 100R 100R Ca 2.2nF 68pF
For SSTL-1.8/SSTL-2/DDR1/GDDR1: 0.5 * VDDR1.

For DDR3/GDDR3/GDDR4/GDDR5: 0.7 * VDDR1. This basic topology should be used for DRAM_RST for
A DDR3/GDDR3/GDDR5.These Capacitors and Resistor values A
Broadway no daul rank support for GDDR5 are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.
PROJECT : ZR8
Madison/Broadway-MEM I/F 1A

5 4 3 2 1
5 4 3 2 1
20
+1.5V_GPU
+1.8V_GPU +1.5V_GPU [18,22,23,40,43]
+1V +1.8V_GPU [17,20,21,43]
+1V [16,17,20,42]
+VGPU_CORE
+3V +VGPU_CORE [41,44]
+1.8V_GPU
+3V [2,4,5,6,9,10,11,12,13,14,15,24,25,27,29,30,32,33,34,36,37,38,39,41,42,43,44,46]
U23F
U23E 180 ohm/1.5A
L4
+1.5V_GPU MEM I/O SW@HCB1608KF-181T15_6
For DDR3, MVDDQ = 1.5V (7.5A) PCIE (1.8V@400mA PCIE_VDDR) AB39 A3
PCIE_VDDR PCIE_VSS#1 GND#1
AC7 AA31 E39 A37
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#2 GND#2
AD11 AA32 F34 AA16
AF7 AA33 F39 AA18
C591 C66 C590 C594 C593 VDDR1#3 PCIE_VDDR#3 C122 C97 C112 C108 C133 C98 C96 C121 PCIE_VSS#4 GND#4
AG10 AA34 G33 AA2
SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 VDDR1#4 PCIE_VDDR#4 SW@0.1u/10V_4 SW@0.1u/10V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@10U/6.3V_6 PCIE_VSS#5 GND#5
AJ7 V28 G34 AA21
AK8 W29 H31 AA23
AL9 W30 H34 AA26
D VDDR1#7 PCIE_VDDR#7 PCIE_VSS#8 GND#8 D
G11 Y31 H39 AA28
G14 J31 AA6
VDDR1#9 PCIE_VSS#10 GND#10
G17 J34 AB12
VDDR1#10 +1V PCIE_VSS#11 GND#11
G20 G30 K31 AB15
C56 C49 C62 C165 C157 C57 VDDR1#11 PCIE_VDDC#1 PCIE_VSS#12 GND#12
G23
VDDR1#12 PCIE_VDDC#2
G31 (1.0V@1.1A PCIE_VDDC) K34
PCIE_VSS#13 GND#13
AB17
SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 G26 H29 K39 AB20
VDDR1#13 PCIE_VDDC#3 PCIE_VSS#14 GND#14
G29 H30 L31 AB22
H10 J29 L34 AB24
VDDR1#15 PCIE_VDDC#5 C84 C194 C65 C221 C95 C59 C80 C199 PCIE_VSS#16 GND#16
J7 J30 M34 AB27
VDDR1#16 PCIE_VDDC#6 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@10U/6.3V_6 PCIE_VSS#17 GND#17
J9 L28 M39 AC11
K11 M28 N31 AC13
K13 N28 N34 AC16
K8 R28 P31 AC18
C54 C149 C150 C25 C64 C63 VDDR1#20 PCIE_VDDC#10 PCIE_VSS#21 GND#21
L12 T28 P34 AC2
SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 VDDR1#21 PCIE_VDDC#11 PCIE_VSS#22 GND#22
L16 U28 P39 AC21
VDDR1#22 PCIE_VDDC#12 +VGPU_CORE PCIE_VSS#23 GND#23
L21 R34 AC23
VDDR1#23 PCIE_VSS#24 GND#24
l
L23
VDDR1#24 (30A or more) T31
PCIE_VSS#25 GND#25
AC26
L26 AA15 T34 AC28
VDDR1#25 CORE VDDC#1 PCIE_VSS#26 GND#26
L7 AA17 T39 AC6
VDDR1#26 VDDC#2 PCIE_VSS#27 GND#27
M11 AA20 U31 AD15
VDDR1#27 VDDC#3 C87 C113 C88 C138 C86 PCIE_VSS#28 GND#28
N11 AA22 U34 AD17
C136 C51 C24 C81 C47 VDDR1#28 VDDC#4 SW@1U/6.3V_4 C90 SW@1U/6.3V_4 C115 SW@1U/6.3V_4 C152 SW@1U/6.3V_4 C85 SW@1U/6.3V_4 C128 PCIE_VSS#29 GND#29
P7 AA24 V34 AD20
SW@1U/6.3V_4 SW@0.1u/10V_4 SW@0.1u/10V_4 SW@0.1u/10V_4 SW@0.1u/10V_4 VDDR1#29 VDDC#5 PCIE_VSS#30 GND#30
tia
R11 AA27 V39 AD22
VDDR1#30 VDDC#6 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 PCIE_VSS#31 GND#31
U11 AB16 W31 AD24
U7 AB18 W34 AD27
Y11 AB21 Y34 AD9
Y7 AB23 Y39 AE2
AB26 AE6
VDDC#11 GND#36
AB28 AF10
VDDC#12 C176 C140 C167 C146 C145 GND#37
A41 VDDC#13
AC17
GND#38
AF16
AC20 SW@1U/6.3V_4 C175 SW@1U/6.3V_4 C123 SW@1U/6.3V_4 C159 SW@1U/6.3V_4 C101 SW@1U/6.3V_4 C160 AF18
LEVEL VDDC#14 GND#39
AC22 AF21 GND#61/ PX_EN
120 ohm/300mA (1.8V@110mA VDD_CT) TRANSLATION VDDC#15
VDDC#16
AC24 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 GND GND#40
GND#41
AG17 PowerXpress control signal for Madsion
POWER
L58 VDDC_CT AF26 AC27 F15 AG2
+1.8V_GPU VDD_CT#1 VDDC#17 GND#100 GND#42 and Park only
SW@BLM15BB121SS1 AF27 AD18 F17 AG20
VDD_CT#2 VDDC#18 GND#101 GND#43
AG26
VDD_CT#3 VDDC#19
AD21 F19
GND#102 GND#44
AG22 If not used, can be disconnected.
C615 C166 C153 AG27 AD23 F21 AG6 PX_EN = LOW, turn on
SW@10U/6.3V_6 SW@1U/6.3V_4 SW@0.1u/10V_4 VDD_CT#4 VDDC#20 GND#103 GND#45
AD26 F23 AG9
VDDC#21
AF17 C132 C125 C144 C100 C127 C110 C93 F25
GND#104 GND#46
AH21 PX_EN = HIGH, turn off
I/O VDDC#22 SW@1U/6.3V_4 C154 SW@1U/6.3V_4 C168 SW@1U/6.3V_4 C104 SW@1U/6.3V_4 SW@1U/6.3V_4 GND#105 GND#47 PX_EN is used to turn ON/OFF some
C (3.3V@60mA)) VDDC#23
AF20 F27
GND#106 GND#48
AJ10 C
R609 +3V_D_VDDR3 AF23 AF22 F29 AJ11 regulators for PowerXpress mode. An
+3V_D VDDR3#1 VDDC#24 GND#107 GND#49
SW@0_6 AF24 AG16 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 F31 AJ2
AG23
VDDR3#2 VDDC#25
AG18 F33
GND#108 GND#50
AJ28
output high ‘3.3V’ will turn the regulators
C202 C161 C191 C198 VDDR3#3 VDDC#26 GND#109 GND#51 OFF. An output low ‘0V’ will turn the
AG24 AG21 F7 AJ6
SW@10U/6.3V_6 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 VDDR3#4 VDDC#27 GND#110 GND#52
VDDC#28
AH22 F9
GND#111 GND#53
AK11 regulators ON. PX_EN outputs low (0V)
en
A41 VDDC#29
AH27 G2
GND#112 GND#54
AK31 by default.
AF13 AH28 C126 C105 C124 C106 C77 C107 G6 AK7
VDDR4#4 VDDC#30 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 GND#113 GND#55 If this signal is unused, it can be NC (not
AF15 M26 H9 AL11
VDDR4#5 VDDC#31 GND#114 GND#56
120 ohm/300mA AG13
VDDR4#7 VDDC#32
N24 J2
GND#115 GND#57
AL14 connected) or connected to ground.
L17 VDDR4 AG15 N27 J27 AL17
+1.8V_GPU VDDR4#8 VDDC#33 GND#116 GND#58
SW@BLM15BB121SS1 R18 J6 AL2
VDDC#34 GND#117 GND#59
VDDC#35
R21 BIF_VDDC should be connected to VDDC if BACO feature not used. J8
GND#118 GND#60
AL20
C228 C227 AD12 R23 K14 AL21
SW@1U/6.3V_4 SW@0.1u/10V_4 VDDR4#1 VDDC#36 For BACO, refer to the databook GND#119 GND#61
AF11 R26 K7 AL23
VDDR4#2 VDDC#37 (Separate Core power for PCIe bus macros GND#120 GND#62
AF12 T17 L11 AL26
VDDR4#3 VDDC#38 GND#121 GND#63
AG11
VDDR4#6 VDDC#39
T20 Connector to VDDCin non-ower-Xpress desingns ZR8 L17
GND#122 GND#64
AL32 R64
T22 L2 AL6 SPE@0_4
T24 L22 AL8
VDDC#42
T27 PIN different between Broadway and Madison L24
GND#125 GND#67
AM11
U16 L6 AM31
T2 M20
NC_VDDRHA VDDC#44
U18 Pin Broadway Madison M17
GND#127 GND#69
AM9 Pin AL21 to Ground for Broadway
T1 M21 U21 M22 AN11
NC_VSSRHA VDDC#45 GND#128 GND#70
U23 M24 AN2
VDDC#47
U26 VDDC#32 / BIF_VDDC (N27) VDDC BIF_VDDC N16
GND#130 GND#72
AN30
T4 V12 V17 N18 AN6
T3 NC_VDDRHB VDDC#48 GND#131 GND#73
U12 V20 N2 AN8
NC_VSSRHB VDDC#49 GND#132 GND#74
V22 VDDC#42 / BIF_VDDC (T27) VDDC BIF_VDDC N21 AP11
id
A41 VDDC#51
V24 N23
GND#134 GND#76
AP7
V27 N26 AP9
VDDC#53
Y16 GND#61 / PX_EN (AL21) GND PX_EN N6
GND#136 GND#78
AR5
120 ohm/300mA (1.8V@40mA PCIE_PVDD) PLL Y18 R15 AW34
L57 PCIE_PVDD VDDC#54 GND#137 GND#79
+1.8V_GPU AB37 Y21 R17 B11
PCIE_PVDD VDDC#55 GND#138 GND#80
SW@BLM15BB121SS1
VDDC#56
Y23 (AL31) TS_A NC_TS_A R2
GND#139 GND#81
B13
MPV18 H7 Y26 A34 R20 B15
C610 C608 C606 MPV18#1 VDDC#57 GND#140 GND#82
H8 Y28 R22 B17
SW@10U/6.3V_6 SW@1U/6.3V_4 SW@0.1u/10V_4 MPV18#2 VDDC#58 GND#141 GND#83
A41 (GDDR5 1.12V@16A VDDCI)
+VGPU_CORE
R24
GND#142 GND#84
B19
R27 B21
SPV18 GND#143 GND#85
AM10
SPV18 (DDR3 1.12V@4A VDDCI) or more R6
GND#144 GND#86
B23
120 ohm/300mA (1.8V@150mA MPV18) AA13 T11 B25
B
L1 SPV10 VDDCI#1 GND#145 GND#87 B
+1.8V_GPU AN9 AB13 T13 B27
SW@BLM15BB121SS1 SPV10 VDDCI#2 GND#146 GND#88
AC12 T16 B29
VDDCI#3 C79 C114 C92 C71 C148 C78 GND#147 GND#89
AN10 AC15 T18 B31
C44 C52 C46 SPVSS VDDCI#4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 GND#148 GND#90
AD13 T21 B33
SW@10U/6.3V_6 SW@1U/6.3V_4 SW@0.1u/10V_4 VDDCI#5 GND#149 GND#91
AD16 T23 B7
+1.8V_GPU
A41
L13
120 ohm/300mA
SW@BLM15BB121SS1
(1.8V@75mA SPV18)
T9 AF28
VOLTAGE
SENESE
FB_VDDC
nf VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
M15
M16
M18
M23
N13
N15
N17 C151 C117 C130 C73 C91 C75 C72
T26
U15
U17
U2
U20
U22
U24
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
B9
C1
C39
E35
E5
F11
F13
C213 C208 VDDCI#13 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 GND#158 GND#99
N20 U27
SW@10U/6.3V_6 SW@0.1u/10V_4 VDDCI#14 GND#159
T6 AG28 N22 U6
FB_VDDCI ISOLATED VDDCI#15 GND#160
A41 CORE I/O VDDCI#16
R12 V11
GND#161
R13 V16
VDDCI#17 GND#163
T8 AH29 R16 V18
120 ohm/300mA FB_GND VDDCI#18 GND#164
(1.0V@120mA SPV10) VDDCI#19
T12 V21
GND#165
+1V L14 T15 V23
SW@BLM15BB121SS1 VDDCI#20 +3V +3V GND#166
V15 V26
VDDCI#21 GND#167
Y13 W2
C214 C209 VDDCI#22 GND#168
W6
SW@10U/6.3V_6 SW@0.1u/10V_4 GND#169
Y15
GND#170
1
SPE@Madison/Broadway_M2 R133 Y17

GPU +3V power
Co
GND#171
SW@4.7K_4 Y20
R113 GND#172
Y22 A39
*SW@0_6 GND#173 VSS_MECH#1
2 Y24 AW1
GND#174 VSS_MECH#2
Y27 AW39
Q13 GND#175 VSS_MECH#3
U13
GND#152
3
R98 SW@0_4 SW@AO3413 V13

[12] MXM_PWREN GND#162
0.5A
3
+3V 2 SPE@Madison/Broadway_M2
+3V_D
GPU all PWROK +1.5V_GPU R111 *SW@0_4 Q11
DTC144EUA C248 C261 C262
1
R95 SW@10U/6.3V_6 SW@1U/10V_4 SW@0.1u/10V_4

SW@10K_4 C223
R97 *SW@1U/10V_4
SW@10K_4 +3V
B2-TEST
A A
dGPU_PWROK [11]
A20
3
R595
1
*SW@0_6
C_G 2 Q9 R596
SW@2N7002K 2 *SW@0_6
3
+1.8V_GPU 2 Q7 SW@AO3413 0.5A

1
SW@PDTC143TT Q37
3
+3V_D_EXT PROJECT : ZR8

1
C9778 C9779 C9780

SW@10u/6.3V_6 SW@1u/10V_4 SW@.1u/10V_4
Madison/Broadway (PWR/GND) 1A

5 4 3 2 1
5 4 3 2 1
+1.8V_GPU
21
+1V +1.8V_GPU [17,19,21,43]
+1V [16,17,19,42]
D D
U23H
DP C/D POWER DP A/B POWER
A41 DPC_VDD18 AP20 AN24 DPA_VDD18

+1.8V_GPU DPC_VDD18#1 DPA_VDD18#1 +1V
AP21
DPC_VDD18#2 DPA_VDD18#2
AP24 A41
120 ohm/300mA (1.8V@130mA DPA_VDD18)
L23 DPA_VDD18 120 ohm/300mA
l
(1.0V@110mA DPA_VDD10)
SW@BLM15BB121SS1 DPC_VDD10 AP13 AP31 DPA_VDD10 DPA_VDD10 L15
DPC_VDD10#1 DPA_VDD10#1 SW@BLM15BB121SS1
AT13 AP32
C270 C269 C271 DPC_VDD10#2 DPA_VDD10#2
SW@10U/6.3V_6 SW@1u/10V_6 SW@0.1u/10V_4 C204 C210 C219
AN17 AN27 SW@10U/6.3V_6 SW@1U/6.3V_4 SW@0.1u/10V_4
DPC_VSSR#1 DPA_VSSR#1
C A
tia
AP16 AP27
AP17 AP28
AW14 AW24
AW16 AW26
(1.8V@130mA DPC_VDD18) (1.0V@110mA DPC_VDD10)
R617 *Short_4 DPC_VDD18 DPC_VDD10 R618 *Short_4
DPC_VDD18 AP22 AP25 DPA_VDD18

DPD_VDD18#1 DPB_VDD18#1
B01 AP23
AP26 B01
D B
DPC_VDD10 AP14 AN33 DPA_VDD10
AP15 AP33
C AN19 AN29 C
DPD_VSSR#1 DPB_VSSR#1
AP18 AP29
AP19 AP30
AW20 AW30
AW22 AW32
en
A41
+1.8V_GPU
R410 SW@150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR R402 SW@150/F_4
DPCD_CALR DPAB_CALR 120 ohm/300mA
(1.8V@20mA DPA_PVDD)
DPA_PVDD L18
DP E/F POWER DP PLL POWER SW@BLM15BB121SS1
AH34 AU28
DPE_VDD18 DPE_VDD18#1 DPA_PVDD C234 C249 C240
AJ34 AV27
DPE_VDD18#2 DPA_PVSS SW@10U/6.3V_6 SW@1U/6.3V_4 SW@0.1u/10V_4
AL33 AV29 DPB_PVDD R608 *SW@0_4

DPE_VDD10 DPE_VDD10#1 DPB_PVDD
AM33 AR28
DPE_VDD10#2 DPB_PVSS
E
+1.8V_GPU (1.8V@400mA DPE/F_VDD18) AN34 AU18 DPC_PVDD R612 *SW@0_4
180 ohm/1.5A DPE_VSSR#1 DPC_PVDD
AP39 AV17
L5 DPE_VDD18 DPE_VSSR#2 DPC_PVSS
AR39
SW@HCB1608KF-181T15_6 DPE_VSSR#3
AU37
DPE_VSSR#4
AW35
C164 C163 C170 DPE_VSSR#5 DPD_PVDD R613 *SW@0_4
AV19
id
SW@0.1u/10V_4 SW@1U/6.3V_4 SW@10U/6.3V_6 DPD_PVDD
AR18
DPD_PVSS
DPE_VDD18
AF34
DPF_VDD18#1 A42
AG34
DPF_VDD18#2
AM37
DPE_PVDD
F DPE_PVSS
AN38
AK33
DPE_VDD10 DPF_VDD10#1
AK34
DPF_VDD10#2
AL38
NC_DPF_PVDD
AM35
+1V NC_DPF_PVSS
B
180 ohm/1.5A
(1.0V@400mA DPE/F_VDD10) A41 B
AF39 +1.8V_GPU
L9 DPE_VDD10 DPF_VSSR#1
AH39
SW@HCB1608KF-181T15_6 DPF_VSSR#2 120 ohm/300mA
AK39
DPF_VSSR#3 (1.8V@40mA DPE/F_PVDD)
AL34 DPE_PVDD L59
C193 C183 C192 DPF_VSSR#4 SW@BLM15BB121SS1
AM34
SW@0.1u/10V_4 SW@1U/6.3V_4 SW@10U/6.3V_6
R54
nf
SW@150/F_4 DPEF_CALR AM39
DPF_VSSR#5
DPEF_CALR
C618
SW@10U/6.3V_6
C634
SW@1U/6.3V_4
C622
SW@0.1u/10V_4
Co
A A
PROJECT : ZR8
Madison/Broadway (DP_PWR/GND) 1A

5 4 3 2 1
5 4 3 2 1
PIN STRAPS
CONFIGURATION STRAPS
22
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, ZR8
THEY MUST NOT CONFLICT DURING RESET
+3V_D Memory Aperture size
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK
R55 *SPE@10K_4
[17] GPU_GPIO0 GPIO[13:11] Size TX_PWRS_ENB GPIO0 0 = 50% TX OUTPUT SWING 0
R43 *SPE@10K_4 1 = FULL TX OUTPUT SWING
D [17] GPU_GPIO1 D
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0

R39 *SW@10K_4
000 128MB 0 = TX DE-EMPHASIS DISABLED
[17] GPIO3_SMBDAT
1 = TX DE-EMPHASIS ENABLED
R50 *SW@10K_4 001 256MB ENABLE EXTERNAL BIOS ROM
[17] GPIO4_SMBCLK
BIOS_ROM_EN GPIO_22_ROMCSB 0 = DISABLE 0
1 = ENABLE
Unconnected if no external BIOS ROM is used 010 64MB
ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 000
SCS#_GPIO22 R148 *SPE@10K_4 NUMONYX M25P10A : 101 See ROM table
011 32MB
(Recommended setting as 5.0
R67 *SPE@10K_4 BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0 GT/s capability will be
[17] GPU_GPIO13
1 = PCIE DEVICE AS 5GT/S CAPABLE controlled by software.)
R80 **SPE@10K_4
l
[17] GPU_GPIO12
GPIO_8_ROMSO GPIO8
[17] GPU_GPIO11
R79 *SPE@10K_4 Function Table H2SYNC H2SYNC Reserved Only 0
GPIO_21_BB_EN GPIO21
EXT_HSYNC EXT_VSYNC Discription
R416 *SPE@10K_4 AUD[1:0]
[17] GPU_GPIO2
tia
00: NO AUDIO FUNCTION.
AUD[1] HSYNC 01: AUDIO FOR DISPLAYPORT AND HDMI IF
R396 SW@10K_4 0 0 No Audio See Audio table
[17,24] EXT_HSYNC ADAPTER IS DETECTED. 11
AUD[0] VSYNC 10: AUDIO FOR DISPLAYPORT ONLY.
R395 SW@10K_4
[17,24] EXT_VSYNC
0 1 Any one by dectec 11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
SIN_GPIO9 R128 *SPE@10K_4

1 0 DP only
R418 *SPE@10K_4 GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable 0
[17] V2SYNC
1 = VGA controller capacity disenable
1 1 Both DP & HDMI (The device will not be recognized as the system's VGA controller.)
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET. 0
1 = DRIVER would use the value sample on VHAD_0 during RESET.
C C
en
SERIAL ROM DDR3 Memory Aperture size
U12
DDR3 Memory Aperture size
SIN_GPIO9 5 2 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
[17] SIN_GPIO9 D Q SOUT_GPIO8 [17]
Vendor Vendor P/N STN B/S P/N GPU
[17] SCLK_GPIO10 6
C DVPDATA_2 DVPDATA_1 DVPDATA_0
SCS#_GPIO22 1
[17] SCS#_GPIO22 S
+3V_D_EXT 7
HOLD
Park 1 1 0
R142 *SW@10K_4 3 Hynix AKD5LZGTW04
W
H5TQ1G63BFR-12C Madison
A20 8
VCC VSS
4 (64M*16) 1 0 0
id
R134
C283 *SW@M25P10-AVMN6P
*SW@10K_4
*SW@0.1U/10V_4 2Gb 1 1 1
C14
D10 Park 0 1 0
AKD5LGGT506
K4W1G1646E-HC12 Madison
Samsung (64M*16) 0 0 0
B B
K4W2G1646B-HC12 AKD5MGGT500 2Gb 0 0 1
Thermal Sensor
nf AMD
Park 0 1 1
23EY2387MA12-SZ AKD5LGGT700 Madison 1 0 1
A20
Vendor P/N
WINDBOND AL83L771K02
GMT AL000780003 +1.8V_GPU
+3V_D_EXT +1.8V_GPU [17,19,20,43]
+3V_D
Co
+3V_D [16,17,19,24,25]
A20
A37 +1.8V_GPU
Samsung-1GB (Default)
+3V_D_EXT
R137 R611
SW@10K_4 *SW@10K_4 R406 *SPE@10K_4
[17] RAM_STRAP2
C244 SW@0.1u/10V_4
R400 SPE@10K_4 RAM_STRAP2 SET DDR3 Vendor
U11
RAM_STRAP[1:0] SET SIZE.
[34] MXM_SMCLK12 8 1 GPU_D+ [17]
SCLK VCC R408 *SPE@10K_4
[17] RAM_STRAP1
[34] MXM_SMDATA12 7 2 C252
SDA DXP R405 SPE@10K_4
6 3 SW@2200P/50V_4
[17] ALT#_GPIO17 ALERT# DXN
GPU_D- [17] R407
OVERT# 4 5 *SPE@10K_4
OVERT# GND
A A
R401 SPE@10K_4
[17] RAM_STRAP0
SW@G780P81U
ADDRESS: 9AH
B2-TEST
PROJECT : ZR8
Strip/Thermal 1A

5 4 3 2 1
5 4 3 2 1
VMA_DQ[63..0]
CHANNEL A: 512MB DDR3 (64M*16*4pcs)

23
[18] VMA_DQ[63..0]
VMA_DM[7..0]
[18] VMA_DM[7..0]
VMA_RDQS[7..0] QSA[7..0]
[18] VMA_RDQS[7..0]
VMA_WDQS[7..0] QSA#[7..0]
[18] VMA_WDQS[7..0]
U19 U1 U20 U2
VREFC_VMA1 M8 E3 VMA_DQ10 VREFC_VMA2 M8 E3 VMA_DQ6 VREFC_VMA3 M8 E3 VMA_DQ54 VREFC_VMA4 M8 E3 VMA_DQ40

VREFD_VMA1 VREFCA DQL0 VMA_DQ11 VREFD_VMA2 VREFCA DQL0 VMA_DQ0 VREFD_VMA3 VREFCA DQL0 VMA_DQ53 VREFD_VMA4 VREFCA DQL0 VMA_DQ44
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMA_DQ9 VREFDQ DQL1 VMA_DQ7 VREFDQ DQL1 VMA_DQ55 VREFDQ DQL1 VMA_DQ45
F2 F2 F2 F2
VMA_MA0 DQL2 VMA_DQ12 VMA_MA0 DQL2 VMA_DQ1 VMA_MA0 DQL2 VMA_DQ50 VMA_MA0 DQL2 VMA_DQ42
[18] VMA_MA0 N3 F8 N3 F8 N3 F8 N3 F8
VMA_MA1 A0 DQL3 VMA_DQ13 VMA_MA1 A0 DQL3 VMA_DQ4 VMA_MA1 A0 DQL3 VMA_DQ49 VMA_MA1 A0 DQL3 VMA_DQ46
[18] VMA_MA1 P7 H3 P7 H3 P7 H3 P7 H3
[18] VMA_MA2 P3 H8 P3 H8 P3 H8 P3 H8
[18] VMA_MA3 N2 G2 N2 G2 N2 G2 N2 G2
D
D
[18] VMA_MA4 P8 H7 P8 H7 P8 H7 P8 H7
VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
[18] VMA_MA5 P2 P2 P2 P2
VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5
[18] VMA_MA6 R8 R8 R8 R8
VMA_MA7 A6 VMA_DQ20 VMA_MA7 A6 VMA_DQ25 VMA_MA7 A6 VMA_DQ63 VMA_MA7 A6 VMA_DQ32
[18] VMA_MA7 R2 D7 R2 D7 R2 D7 R2 D7
VMA_MA8 A7 DQU0 VMA_DQ19 VMA_MA8 A7 DQU0 VMA_DQ31 VMA_MA8 A7 DQU0 VMA_DQ59 VMA_MA8 A7 DQU0 VMA_DQ36
[18] VMA_MA8 T8 C3 T8 C3 T8 C3 T8 C3
[18] VMA_MA9 R3 C8 R3 C8 R3 C8 R3 C8
[18] VMA_MA10 L7 C2 L7 C2 L7 C2 L7 C2
VMA_MA11 A10/AP DQU3 VMA_DQ22 VMA_MA11 A10/AP DQU3 VMA_DQ24 VMA_MA11 A10/AP DQU3 VMA_DQ60 VMA_MA11 A10/AP DQU3 VMA_DQ35
[18] VMA_MA11 R7 A7 R7 A7 R7 A7 R7 A7
[18] VMA_MA12 N7 A2 N7 A2 N7 A2 N7 A2
VMA_MA13 A12/BC DQU5 VMA_DQ21 VMA_MA13 A12/BC DQU5 VMA_DQ26 VMA_MA13 A12/BC DQU5 VMA_DQ61 VMA_MA13 A12/BC DQU5 VMA_DQ34
[18] VMA_MA13 T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMA_DQ17 A13 DQU6 VMA_DQ29 A13 DQU6 VMA_DQ57 A13 DQU6 VMA_DQ38
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2

[18] VMA_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
l
VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9
[18] VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7
[18] VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
N1 N1 N1 N1
VMA_CLKP0 VDD#N1 VMA_CLKP0 VDD#N1 VMA_CLKP1 VDD#N1 VMA_CLKP1 VDD#N1
[18] VMA_CLKP0 J7 N9 J7 N9 [18] VMA_CLKP1 J7 N9 J7 N9
tia
VMA_CLKN0 CK VDD#N9 VMA_CLKN0 CK VDD#N9 VMA_CLKN1 CK VDD#N9 VMA_CLKN1 CK VDD#N9
[18] VMA_CLKN0 K7 R1 K7 R1 [18] VMA_CLKN1 K7 R1 K7 R1
VMA_CKE0 CK VDD#R1 VMA_CKE0 CK VDD#R1 VMA_CKE1 CK VDD#R1 VMA_CKE1 CK VDD#R1
[18] VMA_CKE0 K9 R9 K9 R9 [18] VMA_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_ODT1 K1 A1 VMA_ODT1 K1 A1

[18] VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 [18] VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_CS1# L2 A8 VMA_CS1# L2 A8
[18] VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 [18] VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_RAS1# J3 C1 VMA_RAS1# J3 C1
[18] VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 [18] VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_CAS1# K3 C9 VMA_CAS1# K3 C9
[18] VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [18] VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_WE0# L3 D2 VMA_WE0# L3 D2 VMA_WE1# L3 D2 VMA_WE1# L3 D2
[18] VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 [18] VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMA_RDQS1 VDDQ#F1 VMA_RDQS0 VDDQ#F1 VMA_RDQS6 VDDQ#F1 VMA_RDQS5 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2 VMA_RDQS4 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM1 E7 A9 VMA_DM0 E7 A9 VMA_DM6 E7 A9 VMA_DM5 E7 A9

VMA_DM2 DML VSS#A9 VMA_DM3 DML VSS#A9 VMA_DM7 DML VSS#A9 VMA_DM4 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMA_WDQS1 VSS#G8 VMA_WDQS0 VSS#G8 VMA_WDQS6 VSS#G8 VMA_WDQS5 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMA_WDQS2 DQSL VSS#J2 VMA_WDQS3 DQSL VSS#J2 VMA_WDQS7 DQSL VSS#J2 VMA_WDQS4 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
en
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
[18,23] MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R376 VSSQ#B9 R1 VSSQ#B9 R369 VSSQ#B9 R10 VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
SW@243/F_4 D8 SW@243/F_4 D8 SW@243/F_4 D8 SW@243/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SPE@VRAM_DDR3 SPE@VRAM_DDR3 SPE@VRAM_DDR3 SPE@VRAM_DDR3
id
TOP Left BOT Left BOT Right TOP Right
Group-A0 VREF Group-A1 VREF
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R378 R365 R3 R7 R367 R383 R8 R4

SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4
R377
SW@4.99K/F_4
VREFC_VMA1
C573
SW@0.1u/10V_4
R366
SW@4.99K/F_4
VREFD_VMA1
C565
SW@0.1u/10V_4
R2
SW@4.99K/F_4
nf
VREFC_VMA2
C3
SW@0.1u/10V_4
R6
SW@4.99K/F_4
VREFD_VMA2
C22
SW@0.1u/10V_4
R368
SW@4.99K/F_4
VREFC_VMA3
C566
SW@0.1u/10V_4
R375
SW@4.99K/F_4
VREFD_VMA3
C576
SW@0.1u/10V_4
R9
SW@4.99K/F_4
VREFC_VMA4
C28
SW@0.1u/10V_4
R5
SW@4.99K/F_4
VREFD_VMA4
C13
SW@0.1u/10V_4
Group-A0 decoupling CAP Group-A1 decoupling CAP MEM_A1 CLK

MEM_A0 CLK
+1.5V_GPU +1.5V_GPU
Co
VMA_CLKP1
VMA_CLKP0
VMA_CLKN1
VMA_CLKN0 C578 C569 C564 C571 C561 C8 C560 C559 C567 C563 C14 C27 C31 C29 C16 C568
SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
R370 R371
R364 R363 SW@56.2/F_4 SW@56.2/F_4
SW@56.2/F_4 SW@56.2/F_4
+1.5V_GPU +1.5V_GPU
C555
C558 C579 C9 C21 C572 C30 C23 C7 C20 C12 C15 C11 C10 C26 C6 C19 C580 SW@0.01u/25V_4
SW@0.01u/25V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
A A
+1.5V_GPU +1.5V_GPU
C562 C18 C2 C5 C17 C4 C570 C1 C556 C557

SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6
PROJECT : ZR8
MEMORY 1 channel A 1A

5 4 3 2 1
5 4 3 2 1
CHANNEL B: 512MB DDR3 (64M*16*4pcs)

[18] VMB_DQ[63..0]
[18] VMB_DM[7..0]
[18] VMB_RDQS[7..0]
VMB_DQ[63..0]
VMB_DM[7..0]
VMB_RDQS[7..0]
VMB_WDQS[7..0]
QSA[7..0]
24
[18] VMB_WDQS[7..0] QSA#[7..0]
U3 U22 U24 U5
VREFC_VMB1 M8 E3 VMB_DQ4 VREFC_VMB2 M8 E3 VMB_DQ17 VREFC_VMB3 M8 E3 VMB_DQ36 VREFC_VMB4 M8 E3 VMB_DQ54

VREFD_VMB1 VREFCA DQL0 VMB_DQ2 VREFD_VMB2 VREFCA DQL0 VMB_DQ21 VREFD_VMB3 VREFCA DQL0 VMB_DQ39 VREFD_VMB4 VREFCA DQL0 VMB_DQ51
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMB_DQ6 VREFDQ DQL1 VMB_DQ18 VREFDQ DQL1 VMB_DQ33 VREFDQ DQL1 VMB_DQ53
F2 F2 F2 F2
VMB_MA0 DQL2 VMB_DQ0 VMB_MA0 DQL2 VMB_DQ16 VMB_MA0 DQL2 VMB_DQ34 VMB_MA0 DQL2 VMB_DQ50
[18] VMB_MA0 N3 F8 N3 F8 N3 F8 N3 F8
VMB_MA1 A0 DQL3 VMB_DQ7 VMB_MA1 A0 DQL3 VMB_DQ20 VMB_MA1 A0 DQL3 VMB_DQ35 VMB_MA1 A0 DQL3 VMB_DQ52
[18] VMB_MA1 P7 H3 P7 H3 P7 H3 P7 H3
[18] VMB_MA2 P3 H8 P3 H8 P3 H8 P3 H8
[18] VMB_MA3 N2 G2 N2 G2 N2 G2 N2 G2
D
D
[18] VMB_MA4 P8 H7 P8 H7 P8 H7 P8 H7
VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7
[18] VMB_MA5 P2 P2 P2 P2
VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5
[18] VMB_MA6 R8 R8 R8 R8
VMB_MA7 A6 VMB_DQ24 VMB_MA7 A6 VMB_DQ15 VMB_MA7 A6 VMB_DQ60 VMB_MA7 A6 VMB_DQ40
[18] VMB_MA7 R2 D7 R2 D7 R2 D7 R2 D7
VMB_MA8 A7 DQU0 VMB_DQ31 VMB_MA8 A7 DQU0 VMB_DQ10 VMB_MA8 A7 DQU0 VMB_DQ59 VMB_MA8 A7 DQU0 VMB_DQ46
[18] VMB_MA8 T8 C3 T8 C3 T8 C3 T8 C3
[18] VMB_MA9 R3 C8 R3 C8 R3 C8 R3 C8
[18] VMB_MA10 L7 C2 L7 C2 L7 C2 L7 C2
VMB_MA11 A10/AP DQU3 VMB_DQ26 VMB_MA11 A10/AP DQU3 VMB_DQ12 VMB_MA11 A10/AP DQU3 VMB_DQ62 VMB_MA11 A10/AP DQU3 VMB_DQ44
[18] VMB_MA11 R7 A7 R7 A7 R7 A7 R7 A7
[18] VMB_MA12 N7 A2 N7 A2 N7 A2 N7 A2
VMB_MA13 A12/BC DQU5 VMB_DQ25 VMB_MA13 A12/BC DQU5 VMB_DQ13 VMB_MA13 A12/BC DQU5 VMB_DQ61 VMB_MA13 A12/BC DQU5 VMB_DQ43
[18] VMB_MA13 T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMB_DQ29 A13 DQU6 VMB_DQ8 A13 DQU6 VMB_DQ58 A13 DQU6 VMB_DQ47
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

[18] VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
l
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
[18] VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
[18] VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
K8 K8 K8 K8
N1 N1 N1 N1
VMB_CLKP0 VDD#N1 VMB_CLKP0 VDD#N1 VMB_CLKP1 VDD#N1 VMB_CLKP1 VDD#N1
[18] VMB_CLKP0 J7 N9 J7 N9 [18] VMB_CLKP1 J7 N9 J7 N9
tia
VMB_CLKN0 CK VDD#N9 VMB_CLKN0 CK VDD#N9 VMB_CLKN1 CK VDD#N9 VMB_CLKN1 CK VDD#N9
[18] VMB_CLKN0 K7 R1 K7 R1 [18] VMB_CLKN1 K7 R1 K7 R1
VMB_CKE0 CK VDD#R1 VMB_CKE0 CK VDD#R1 VMB_CKE1 CK VDD#R1 VMB_CKE1 CK VDD#R1
[18] VMB_CKE0 K9 R9 K9 R9 [18] VMB_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

[18] VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 [18] VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
[18] VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 [18] VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
[18] VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 [18] VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
[18] VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [18] VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
[18] VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 [18] VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMB_RDQS0 VDDQ#F1 VMB_RDQS2 VDDQ#F1 VMB_RDQS4 VDDQ#F1 VMB_RDQS6 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMB_RDQS3 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM0 E7 A9 VMB_DM2 E7 A9 VMB_DM4 E7 A9 VMB_DM6 E7 A9

VMB_DM3 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM7 DML VSS#A9 VMB_DM5 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMB_WDQS0 VSS#G8 VMB_WDQS2 VSS#G8 VMB_WDQS4 VSS#G8 VMB_WDQS6 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMB_WDQS3 DQSL VSS#J2 VMB_WDQS1 DQSL VSS#J2 VMB_WDQS7 DQSL VSS#J2 VMB_WDQS5 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
en
M1 M1 M1 M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
[18,22] MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMB_ZQ1 VSS#T1 VMB_ZQ2 VSS#T1 VMB_ZQ3 VSS#T1 VMB_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R15 VSSQ#B9 R386 VSSQ#B9 R393 VSSQ#B9 R59 VSSQ#B9
D1 D1 D1 D1
SW@243/F_4 D8 SW@243/F_4 D8 SW@243/F_4 D8 SW@243/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SPE@VRAM_DDR3 SPE@VRAM_DDR3 SPE@VRAM_DDR3 SPE@VRAM_DDR3
id
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R19 R14 R388 R385 R32 R391 R40 R69

SW@4.99K/F_4
VREFC_VMB1
SW@4.99K/F_4
VREFD_VMB1
SW@4.99K/F_4
VREFC_VMB2
nf SW@4.99K/F_4
VREFD_VMB2
SW@4.99K/F_4
VREFC_VMB3
SW@4.99K/F_4
VREFD_VMB3
SW@4.99K/F_4
VREFC_VMB4
SW@4.99K/F_4
VREFD_VMB4
R18 C61 R12 C45 R387 C592 R384 C584 R41 C172 R392 C602 R53 C182 R58 C195
SW@4.99K/F_4 SW@0.1u/10V_4 SW@4.99K/F_4 SW@0.1u/10V_4 SW@4.99K/F_4 SW@0.1u/10V_4 SW@4.99K/F_4 SW@0.1u/10V_4 SW@4.99K/F_4 SW@0.1u/10V_4 SW@4.99K/F_4 SW@0.1u/10V_4 SW@4.99K/F_4 SW@0.1u/10V_4 SW@4.99K/F_4 SW@0.1u/10V_4
Group-B0 decoupling CAP Group-B1 decoupling CAP

MEM_B0 CLK MEM_B1 CLK
Co
+1.5V_GPU +1.5V_GPU
VMB_CLKP1
VMB_CLKP0 VMB_CLKN1
C588 C69 C583 C577 C215 C587 C33 C597 C604 C632 C620 C598 C614 C216 C156
VMB_CLKN0 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
R45 R52
SW@56.2/F_4 SW@56.2/F_4
R13 R11
SW@56.2/F_4 SW@56.2/F_4 +1.5V_GPU +1.5V_GPU
A C179 A
C35 C595 C603 C581 C596 C173 C143 C582 C609 C177 C601 C605 C611 C171 C607 SW@0.01u/25V_4
C41 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4 SW@1U/6.3V_4
SW@0.01u/25V_4
+1.5V_GPU +1.5V_GPU
PROJECT : ZR8
C589 C141 C32 C39 C74 C142 C217 C600 C599 C636
SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 SW@10U/6.3V_6 Quanta Computer Inc.
MEMORY 2 channel B 1A

5 4 3 2 1
1 2 3 4 5 6 7 8
CRT +5V
25
OPTION SIGNAL FROM NB to LVDS/CRT for UMA OPTION SIGNAL FROM NB to CRT for UMA
RP19 *IV@0_4P2R_4 INT_CRT_RED R412 *IV@0_4 VGA_RED_SYS
UMA use 140 ohm 1%. B2-TEST C246 .22u_4
1A/30V
INT_DDCCLK 3 4 CRTDCLK INT_CRT_GRE R411 *IV@0_4 VGA_GRN_SYS Discrete use 150 ohm 1%. C05 D5
C612 INT_DDCDATA 1 2 CRTDDAT INT_CRT_BLU R394 *IV@0_4 VGA_BLU_SYS F1
U25 Note : Only for RS880 series A11 ASIC errata. CRTVDD5
16
+5V 2 1 2 1
SW@.22u_4 16 8 RP17 *IV@0_4P2R_4 RSX101M-30 CN13
VCC GND INT_EDIDCLK LCD_EDIDCLK INT_CRT_HSYNC HSYNC SMD1206P100TF CRT
1 2 3 4
INT_EDIDDATA 3 4 LCD_EDIDDATA INT_CRT_VSYNC 1 2 VSYNC 6
2 VGA_RED_SYS L26 BLM18BA470SN1_6 CRT_R1 1 11 CRT_11 T73
[17] EXT_CRT_RED IA0 RP1 *IV@0_4P2R_4
5 4 VGA_RED_SYS 7
[17] EXT_CRT_GRE IB0 YA
11 VGA_GRN_SYS L25 BLM18BA470SN1_6 CRT_G1 2 12 DDCDAT_1
[17] EXT_CRT_BLU IC0
14 7 VGA_GRN_SYS Follow AMD reference schematic change OPTION Back Light SIGNAL FROM NB to LVDS for UMA 8
ID0 YB VGA_BLU_SYS L21 BLM18BA470SN1_6 CRT_B1 CRTHSYNC
3 13
[9] INT_CRT_RED 3 9 VGA_BLU_SYS for reduce leakage to VDDR3 BUS. 9
IA1 YC INT_LVDS_BLON R93 *IV@0_4 LVDS_BLON CRTVSYNC
[9] INT_CRT_GRE 6 4 14
IB1 R414 SW@4.7K_4 EV_CRTDDAT R163 R143 R132 C304 C285 C264 C266 C284 C298
[9] INT_CRT_BLU 10 12 +3V_D 10
A IC1 YD R92 SW@4.7K_4 EV_CRTDCLK IV@140/F_4 DDCCLK_1
A
13
ID1 OPTION LCDVCC SIGNAL FROM NB to LVDS for UMA B03 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
5 15
S Yn PE_GPIO2 1 15 INT_LVDS_DIGON R94 *IV@0_4 LVDS_VDDEN
17
S OE +3V
0 SW(EV) SW@SN74CBT3257CPWR 140ohm P/N: CS11402FB19
+5V R419 SW@4.7K_4 INT_DDCDATA
+5V R86 R413 SW@4.7K_4 INT_DDCCLK
1 IV
*SW@10K_4
+3V
[16] dGPU_PCIE_RST# +5V
C613 PE_GPIO2_SW C667 R165 *Short_4 CRTVSYNC
U26 R164 *Short_4 CRTHSYNC
3
SW@.22u_4 16 8 0.1u/10V_4 U27
VCC GND +3V
l
Q2 CRTVDD5 1 16 CRT_VSYNC1
C188 +3V VCC_SYNC SYNC_OUT2 CRT_HSYNC1
*SW@2N7002E U7
14
EV_CRTDDAT SYNC_OUT1
[17] EV_CRTDDAT 2 2 7
EV_CRTDCLK IA0 CRTDDAT SW@.22u_4 C664 .22u/25V_6 CRT_BYP VCC_DDC
[17] EV_CRTDCLK 5
IB0 YA
4 16
VCC GND
8 8
BYP VSYNC
A23 CRTVDD5 C245 *.1u_4 CRTVDD5
[17,21] EXT_VSYNC 11 15
IC0 CRTDCLK SYNC_IN2 HSYNC R135 R144
[17,21] EXT_HSYNC 14 7 +3V 2 13
tia
ID0 YB VCC_VIDEO SYNC_IN1 2.7K_4 2.7K_4 C656 *10p/50V_4 CRTVSYNC
2
1
[17] EV_LVDS_BLON IA0
INT_DDCDATA 3 9 VSYNC 5 4 LVDS_BLON R56 C678 R129 R140
[9] INT_DDCDATA IA1 YC [17] EV_LVDS_VDDEN IB0 YA
INT_DDCCLK 6 11 R42 2.2K_4 CRT_R1 3 10 CRTDCLK 4.7K_4 4.7K_4 C663 *10p/50V_4 CRTHSYNC
[9] INT_DDCCLK IB1 [17] EV_LVDS_DDCDAT IC0 VIDEO_1 DDC_IN1
10 12 HSYNC 14 7 LVDS_VDDEN_YB 2.2K_4 0.1u/10V_4 CRT_G1 4 11 CRTDDAT
[9] INT_CRT_VSYNC IC1 YD [17] EV_LVDS_DDCCLK ID0 YB VIDEO_2 DDC_IN2
13 CRT_B1 5 C671 10p/50V_4 DDCCLK_1
[9] INT_CRT_HSYNC ID1 VIDEO_3
3 9 LCD_EDIDDATA 9 DDCCLK_1
[9] INT_LVDS_BLON IA1 YC DDC_OUT1
6 6 12 DDCDAT_1 C675 10p/50V_4 DDCDAT_1
[9] INT_LVDS_DIGON IB1 GND DDC_OUT2
PE_GPIO2 1 15 10 12 LCD_EDIDCLK
S OE [9] INT_EDIDDATA IC1 YD
[9] INT_EDIDCLK 13 CM2009-02QR
SW@SN74CBT3257CPWR ID1
CRT DDCCLK ,DDCDATA pull high resistor to +3v or +5v.
PE_GPIO2 R87 SW@0_4 PE_GPIO2_SW 1 15 Due to RS880M and Madison DDC can support 5V tolerance
S OE
SW@SN74CBT3257CPWR
B B
+3V
A22 VIN +3V LCD Power
B02 CN5 +3V
en G_0
LCDVCC 1
C06 C254 C147 C162 C233 C222 2 LCDVCC
+3V 3 G_1
SW@.22u_4 U10
4.7u/25V_8 1000p/50V_4 .1u/50V_6 1000p/50V_4 LCD_EDIDCLK 4 C174
U4 LCD_EDIDDATA 5 LCDVCC_R R112 *Short_8
1U/10V_4 6 1
6 IN OUT
R263 SW@0_4 PE_GPIO2 TXLOUT0- 7
[34] CONTRAST 5
VCC S
6
TXLOUT0+ 8 A35 4
IN GND
2
C257 C256 C255 C237
9 LVDS_VDDEN 3 5
R159 *SW@0_4 LVDS_BRIGHT +3V TXLOUT1- 10 ON/OFF GND 1U/10V_4 *.1u_4 0.01u/25V_4 22u_8
[17] EV_LVDS_BRIGHT 3 4
B0 YA TXLOUT1+ 11
12 IC(5P)_G5243T11U
INT_DPST_PWM TXLOUT2- 13 R96
[9] INT_DPST_PWM 1 2
B1 GND R285 TXLOUT2+ 14
15 G_2 100K_4
SW@74LVC1G3157GW
S Yn SW@10K/F_4
TXLCLKOUT- 16
TXLCLKOUT+ 17
PE_GPIO2 18
0 SW(EV) 19
OPTION DPST SIGNAL FROM NB to LVDS for UMA
id
[34] PANEL_COLOR 20
21
INT_DPST_PWM R239 *IV@0_4 LVDS_BRIGHT
1 IV R282 22
23
3
*SW@0_4 LVDS_BRIGHT +3V_S5 C238

BL_ON 24 *SW@0.1u/10V_4
25
[34] PANEL_ENG 26
2 Q24
[11] PE_GPIO2_R 27
5
SW@2N7002E
28 G_4
[9,11,34] A_RST#_SB 2
R31 *SHORT_PAD INVCC0 29 LVDS_VDDEN
4
DGPU_Channel-A VIN
G_3
U6 30 LVDS_VDDEN_YB 1
1
C C
3
46 6 TXLOUT2+ LVD-A30SFYG+ U9
[17] EV_TXLOUT2+ A2P C2P
45 7 TXLOUT2- *SW@TC7SH08FU
[17] EV_TXLOUT2- A2N C2N
44 9 TXLOUT1+
[17] EV_TXLOUT1+
[17] EV_TXLOUT1-
[17] EV_TXLOUT0+
[17] EV_TXLOUT0-
[17] EV_TXLCLKOUT+
43
41
40
39
A1P
A1N
A0P
A0N
ACLKP
IN_A OUT_C
C1P
C1N
C0P
C0N
CCLKP
10
15
16
18
TXLOUT1-
TXLOUT0+
TXLOUT0-
TXLCLKOUT+
TXLCLKOUT-
nf +3V R21 *Short_6 CCD_POWER
USBP1-_R
USBP1+_R
8
7
6
CN3
A25
10
9
R91 SW@0_4
[17] EV_TXLCLKOUT- 38 19 5
ACLKN CCLKN
4
3
R536 BEAD_4 DMIC_CLK 2
IGPU_Channel-A [29] DMIC_CLK_R
[29] DMIC_DAT_R R525 BEAD_4 DMIC_DAT 1
35 R47
[9] LA_DATAP2 B2P
34 13 PE_GPIO2_SEL PE_GPIO2 8P CON
[9] LA_DATAN2 B2N SEL SW@8.25K/F_4
33 C787 C776
[9]
[9]
LA_DATAP1
LA_DATAN1 32
B1P
B1N
R74 22p/50V_4 22p/50V_4 Backlight Control
1 SW@10K/F_4
VSS
30 3 A24
Co
[9] LA_DATAP0 B0P VSS +3V
[9] LA_DATAN0 29 5
B0N IN_B VSS
8
VSS
[9] LA_CLK 28 11
BCLKP VSS
27 14
[9] LA_CLK# BCLKN VSS
VSS
17 CAMERA Module(CCD)
+1.8V R90 *Short_6 +1.8V_LVDS 48 20
VDD VSS R120
36 22
VDD VSS 10K_4
25 24
C218 VDD VSS BL_ON D4
23 26 2 1 BAS316 LID591# [31,34]
SW@2.2u/6.3V_6 C189 C206 VDD VSS R114
21 31
SW@0.1u/10V_4 VDD VSS 10K_4
12 37
SW@0.1u/10V_4 VDD VSS
4 42
VDD VSS
3
2 47
VDD VSS
2~3pin share one cap
3
D SW@PI3HDMI412 BL# 2 D
2 EC_FPBACK# [34]
3
Q6
2N7002K Q8
DTC144EUA
1
LVDS_BLON 2
PE_GPIO2 Output OPTION SIGNAL FROM NB to LVDS for UMA Q1
LA_CLK# RP5 1 2 *IV@0_4P2R_4 TXLCLKOUT- 2N7002K
L EV_LVDS LA_CLK 3 4 TXLCLKOUT+ R24 *Short_4 USBP1+_R R70
1
[12] USBP1+
LA_DATAN0
LA_DATAP0
RP4 1
3
2
4
*IV@0_4P2R_4 TXLOUT0-
TXLOUT0+
[12] USBP1-
R25 *Short_4 USBP1-_R 100K_4
PROJECT : ZR8
H INT_LVDS LA_DATAN1 RP3 1 2 *IV@0_4P2R_4 TXLOUT1-
LA_DATAP1
LA_DATAN2 RP2
3 4
*IV@0_4P2R_4
TXLOUT1+
TXLOUT2-
1 2
LA_DATAP2 3 4 TXLOUT2+ VIN Size Document Number Rev
[35,37,38,39,40,41,44] VIN
CRT/LVDS/LID 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
+3V_D
HDMI HPD SENSE

26
UMA use +3V for the detect pin R444 +3V
Dis use +3V_DELAY for the detect pin SW@10K_4
R187
UMA/DISCRETE select for HDMI [17] EXT_HDMI_HPD
10K/F_4
3
Q33
SW@2N7002K
D
From RS880M D
for Layout concern ,placement for Layout concern 2
close north bridge ,placement close HDMI conn
3
+3V Q16
2N7002K
R177
1
C280 *IV@0.1U/10V_4 TX2_HDMI-L RP10 1 2 *IV@0_4P2R_4 TX2_HDMI- 2 HDMI_DET_R HDMI_DET
[8] PEG_TXN15_C
C272 *IV@0.1U/10V_4 TX2_HDMI+L 3 4 TX2_HDMI+ R186
[8] PEG_TXP15_C
10K_4 R176
C267 *IV@0.1U/10V_4 TX1_HDMI-L RP9 TX1_HDMI- 200K/F_4
[8] PEG_TXN14_C 1 2 *IV@0_4P2R_4 200K/F_4
C263 *IV@0.1U/10V_4 TX1_HDMI+L 3 4 TX1_HDMI+
1
[8] PEG_TXP14_C
[9] INT_HDMI_HPD
C253 *IV@0.1U/10V_4 TX0_HDMI-L 1 2 TX0_HDMI-
[8] PEG_TXN13_C
3
C247 *IV@0.1U/10V_4 TX0_HDMI+L 3 4 TX0_HDMI+
[8] PEG_TXP13_C RP8 *IV@0_4P2R_4
C239 *IV@0.1U/10V_4 TXC_HDMI-L 1 2 TXC_HDMI-
[8] PEG_TXN12_C
l
C232 *IV@0.1U/10V_4 TXC_HDMI+L 3 4 TXC_HDMI+ 2
[8] PEG_TXP12_C RP7 *IV@0_4P2R_4 HDMI_HPD_EC# [34]
Q15
2N7002K
1
From dGPU
tia
C698 SW@0.1u/10V_4 TX2_HDMI-
[17] EXT_HDMITX2N
C697 SW@0.1u/10V_4 TX2_HDMI+
[17] EXT_HDMITX2P
C696 SW@0.1u/10V_4 TX1_HDMI-
[17] EXT_HDMITX1N
C695 SW@0.1u/10V_4 TX1_HDMI+ for Layout concern
[17] EXT_HDMITX1P
[17] EXT_HDMITX0N
C694 SW@0.1u/10V_4 TX0_HDMI- ,placement close HDMI conn Close to HDMI Connector
C693 SW@0.1u/10V_4 TX0_HDMI+
[17] EXT_HDMITX0P
C692 SW@0.1u/10V_4 TXC_HDMI- *IV@0_4P2R_4
[17] EXT_HDMICLK-
C691 SW@0.1u/10V_4 TXC_HDMI+ RP20 3 4 HDMI_SDATA
[17] EXT_HDMICLK+ [9] HDMI_DDC_DATA
1 2 HDMI_SCLK
[9] HDMI_DDC_CLK
C R457 SP_715@499/F_4 TX2_HDMI+

UMA C
R459 SP_715@499/F_4 TX2_HDMI-

+5V
UMA RS880M
3
Q34 R454 SP_715@499/F_4 TX1_HDMI+

2N7002K 上 715 ohm CS17152FB17
en
R456 SP_715@499/F_4 TX1_HDMI- +3V
2 +5V
R451 SP_715@499/F_4 TX0_HDMI+
DIS Park-M2 DIS
R453 SP_715@499/F_4 TX0_HDMI- 上 499 ohm CS14992FB24 R443
SW@4.7K_4
1
2
R460 R448 SP_715@499/F_4 TXC_HDMI+
R450 SP_715@499/F_4 TXC_HDMI- 1 3 HDMI_SCLK

[17] EV_HDMI_DDCCK
100K/F_4
Q41
Close to HDMI Connector SW@2N7002K
R445
*SW@0_4
+3V
+5V A54
id
R614
SW@4.7K_4
2
1 3 HDMI_SDATA
[17] EV_HDMI_DDCDAT
EMI reserve for HDMI(HDM) Q42
SW@2N7002K
R534
Close connector *SW@0_4
B B
TX2_HDMI+
TX2_HDMI-
TX1_HDMI+
R458
*100/F_4
nf HDMI PORT
+5V +5V
R455 CN17
*100/F_4 20
SHELL1
2
TX1_HDMI- TX2_HDMI+ 1
D2+ D21 D22
2
TX0_HDMI+ TX2_HDMI- D2 Shield
3 CH501H-40PT
TX1_HDMI+ D2-
4
R452 D1+
5
1
*100/F_4 TX1_HDMI- D1 Shield CH501H-40PT
6
TX0_HDMI- TX0_HDMI+ D1-
7
D0+ R446 R447
8
Co
TXC_HDMI+ TX0_HDMI- D0 Shield 2K/F_4 2K/F_4
9 23
TXC_HDMI+ D0- GND
10
R449 CK+ HDMI_SCLK HDMI_SDATA
11 22
*100/F_4 TXC_HDMI- CK Shield GND
12
TXC_HDMI- CK-
13
CE Remote
B2-TEST D6 HDMI_SCLK
14
NC
15
RSX101M-30 HDMI_SDATA DDC CLK
16
F2 DDC DATA
17
GND
+5V 2 1 2 1+5V_HDMI 18
+5V
19
SMD1206P100TF HP DET
21
HDMI_DET SHELL2
SP@HDMI
A C363 A
0.22u/6.3V_4
P/N: AOP---->DFHD19MR083
LTS---->DFHD19MR085
A49
PROJECT : ZR8
HDMI 1A

5 4 3 2 1
5 4 3 2 1
Giga-LAN AR8151 27
+3V_LAN
+3V_S5
close Pin1
R270 *Short_6 U31
C482 C483 C471 C474 C473

D D
10U/6.3V_8 10U/6.3V_8 1u/6.3V_4 0.1u/10V_4 *1000p/50V_4 1 22 AVDDH C713 0.1u/10V_4
VDD33 AVDDH
2 23 LED2 T32
[11,16,27] A_RST#_AND PERSTn CLKREQn/LED2
3 24 DVDDL C717 0.1u/10V_4
[12] PCIE_WAKE# WAKEn DVDDL
4 25 SMCLK_8151 R476 *0_4
[12] CLK_PCIE_LAN_REQ# CLKREQn SMCLK PCLK_SMB [5,6,12,27,46]
C721 0.1u/10V_4 +VDDCT 5
VDDCT
AR8151
5X5mm SMDATA
26 SMDATA_8151 R477 *0_4
PDAT_SMB [5,6,12,27,46]
C460 1u/6.3V_4 AVDDL 6 40-Pin QFN 27
AVDDL_REG TESTMODE
C459 0.1u/10V_4 XTLO 7 28
XTLO TEST_RST
XTLI 8 29 PCIE_RXN6_C C734 0.1u/10V_4
XTLI TX_N PCIE_RX1- [8]
l
C718 1u/6.3V_4 AVDDH 9 30 PCIE_RXP6_C C737 0.1u/10V_4
AVDDH_REG TX_P PCIE_RX1+ [8]
C714 0.1u/10V_4 R475 2.37K/F_4 RBIAS_LAN 10 31 AVDDL C484 0.1u/10V_4
RBIAS AVDDL
TX0P 11 32 CLK_PCIE_LOM# [11]
tia
TRXP0 REFCLK_N
Wake# and CLKREQ# PU at SB side already TX0N 12 33
TRXN0 REFCLK_P CLK_PCIE_LOM [11]
C462 0.1u/10V_4 AVDDL 13 34 AVDDL C470 0.1u/10V_4
NC/AVDDL AVDDL
TX1P 14
TRXP1 RX_P
35 PCIE_TX1+ [8]
RJ45(LAN)
TX1N 15 36
TRXN1 RX_N PCIE_TX1- [8]
C463 0.1u/10V_4 AVDDH 16 37 DVDDL C475 1u/6.3V_4
C719 33p/50V_4 XTLO NC/AVDDH DVDDL_REG C476 0.1u/10V_4
TX2P 17 38 LAN_ACTLED R487 5.1K_4
1
NC/TRXP2 LED0 CN18

1.2H Y4 TX2N 18 39 LAN_LINKLED# 9
25MHz NC/TRXN2 LED1 LAN_ACTLED R221 220_8 LAN_ACTLED_R YELLOW_N
10
C461 0.1u/10V_4 AVDDL LX L65 4.7uH/1A_2X2 YELLOW_P
19 40 +VDDCT
2
C712 33p/50V_4 XTLI NC/AVDDL LX

C 14 C
TX3P C741 C742 C743 X-TX0P GND2
20 41 1 13
NC/TRXP3 GND X-TX0N 0+ GND1
2
TX3N *1000p/50V_4 0.1u/10V_4 10U/6.3V_8 X-TX1P 0-
21 3
NC/TRXN3 X-TX2P 1+
4
X-TX2N 2+
en
5
X-TX1N 2-
AR8151-AL1A-R1 6
X-TX3P 1-
7
X-TX3N 3+
8
3-
+3V_LAN
B05 LAN_LINKLED# 11
R465 220_8 LAN_LNK_LED_PWR 12 GREEN_N
GREEN_P
RJ45
LAN_ACTLED_R
LAN_LINKLED#
id
C699 C709
TRANSFORMER(LAN) *0.1u//50V_8 *0.1u//50V_8
TX0P
TX1P
TX0N
TX1N
R472
R473
R468
R469
Close Transformer
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
B B
AVDD_CEN L41
A41
+VDDCT
PBY160808T-181Y-N_6
nf
LAN_N1
LAN_N2
reverse 1000p*4 for EMI C448 1U/10V_4
U30
Closed to LAN chip C708 C705 C429 0.1u/10V_4 1 24
TX0P TCT1 MCT1 X-TX0P
2 23
0.1u/10V_4 0.1u/10V_4 C433 *1000p/50V_4 TX0N TD1+ MX1+ X-TX0N
3 22
TD1- MX1-
C438 0.1u/10V_4 4 21
5 20
C700 *1000p/50V_4 TX1N TD2+ MX2+ X-TX1N
6 19
TD2- MX2-
C444 0.1u/10V_4 7 18
8 17
C701 *1000p/50V_4 TX2N TD3+ MX3+ X-TX2N
9 16
TD3- MX3-
TX2P
TX3P
TX2N
TX3N
C449 0.1u/10V_4 10 15
11 14
Co
TD4+ MX4+
R470
R471
R466
R467
C702 *1000p/50V_4 TX3N 12 13 X-TX3N

TD4- MX4-
TRANSFORMER
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
A01 R228 R234 R242 R253

75/F_8 75/F_8 75/F_8 75/F_8
Delta LFE9276D-R (DB0ZY8LAN00)

LAN_N3
LAN_N4
C706 C707 C452

1500p/3KV_18
A 0.1u/10V_4 0.1u/10V_4 A
PROJECT : ZR8
LAN (AR8151) 1A

5 4 3 2 1
5 4 3 2 1
28
D
MINI-CARD WLAN(MPC) D
+3.3V: 1000mA H=5.6mm +3V
+3.3Vaux:330mA A33 +WL_VDD

R530 *Short_8
CN23 LTS_AAA-PCI-046-K01
+1.5V:500mA
51 Reserved +3.3V 52 +WL_VDD
49 50 +WL_VDD R527 *10K_4 C785 C779 C781 C783
Reserved GND 10u/10V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
[11,30] PCIE_RST#_SB_R 47 Reserved +1.5V 48 +1.5V_WL
[11] PCLK_DEBUG 45 Reserved LED_WPAN# 46
43 Reserved LED_WLAN# 44 RF_LED# [32,34]
41 42
l
+WL_VDD Reserved LED_WWAN#
39 Reserved GND 40
37 Reserved USB_D+ 38 USBP7+ [12]
35 GND USB_D- 36 USBP7- [12]
33 34
tia
[8] PCIE_TXP2 PETp0 GND
31 32 RP32 2 1 *0_4P2R_4 +1.5V
[8] PCIE_TXN2 PETn0 SMB_DATA PDAT_SMB [5,6,12,26,46]
29 GND SMB_CLK 30 4 3 PCLK_SMB [5,6,12,26,46]
27 GND +1.5V 28 +1.5V_WL
[8] PCIE_RXP2 25 PERp0 GND 26 C16 R99
[8] PCIE_RXN2 23 PERn0 +3.3Vaux 24 +WL_VDD
21 GND PERST# 22 A_RST#_AND [11,16,26] *Short_6
19 UIM_C4 W_DISABLE# 20 RF_EN [34]
C 17 18 +1.5V_WL C
UIM_C8 GND
15 16 R89 *Short_4
GND UIM_VPP LPC_LFRAME# [11,34]
13 14 R190 *Short_4 C782 C780 C789
[11] CLK_PCIE_WLANP_2 REFCLK+ UIM_RST LPC_LAD3 [11,34]
11 12 R191 *Short_4 1000p/50V_4 0.1u/10V_4 10U/6.3V_8
[11] CLK_PCIE_WLANN_2 REFCLK- UIM_CLK LPC_LAD2 [11,34]
9 10 R226 *Short_4
GND UIM_DATA LPC_LAD1 [11,34]
7 8 R229 *Short_4
[12] CLK_PCIE_2_REQ# CLKREQ# UIM_PWR LPC_LAD0 [11,34]
5 6
en
Reserved +1.5V +1.5V_WL
3 4
GND
GND
Reserved GND
1 WAKE# +3.3V 2 +WL_VDD B2-TEST,量量量量量量
C10
53
54
A01
id
B B
nf
Co
A A
PROJECT : ZR8
Mini-Card/WL/3G/SIM 1A

5 4 3 2 1
1 2 3 4
SATA HDD(HDD)
CN20
23
SATA ODD (ODD)
29
GND23 CN14
GND1 1 GND14 14
RXP 2 SATA_TX0+ [13]
RXN 3 SATA_TX0- [13] GND 1
A GND2 4 A+ 2 SATA_TX1+ [13] A
5 SATA_RX0-_C C752 0.01u/16V_4 3 SATA_TX1- [13]
TXN SATA_RX0- [13] A-
6 SATA_RX0+_C C751 0.01u/16V_4 4
TXP SATA_RX0+ [13] GND
7 5 SATA_RX1-_C C688 0.01u/16V_4
GND3 B- SATA_RX1- [13]
6 SATA_RX1+_C C685 0.01u/16V_4
B+ SATA_RX1+ [13]
GND 7
3.3V 8
9 +5V_ODD
3.3V SATA_DP R179 1K/F_4
3.3V 10 DP 8
GND 11 5V 9
GND 12 5V 10
l +
13 11 C682 C681 C326 C325 C684
GND MD C296
5V 14 GND 12
15 +5V_HDD 13 0.01u/16V_4 0.01u/16V_4 *0.1u/10V_4 *0.1u/10V_4 *10U/6.3V_8 100u/6.3V_3528
5V GND
5V 16
tia
GND 17 GND15 15
RSVD 18
19 R478 *Short_8 SP@SATA_ODD
GND +5V
20 +5V_HDD
12V
12V 21
12V 22
GND24 24 JM51(2-DIMM)-->CN14 P/N:DFHS13FR075

+
C725 C715 C716 C464 C465

MAIN_SATA C480 JV51(3-DIMM)-->CN14 P/N:DFHS13FR017
100u/6.3V_3528 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 0.01u/16V_4 0.01u/16V_4 DFHS13FR022
DFHS13FR005
B B
DFHS13FR006
en
HOLE(OTH)
ODD POWER(ODD)
A26
id
Q38
+3VPCU +5V AO6402A +5V_ODD +5V
6 R435
5 4
2
1
1 *0_8
C
R531 C
100K R529
nf
3
+15V 2 1 MOD_EN_5V
100K
3
2
3
Q39
1
DMN601K-7
C619
1
[34] EC_ODD_EN R532 0_4 ODD_EN 2 0.1u/25V_6
2
1
R533 *0_4 Q40

Co
[11] PCH_ODD_EN
DMN601K-7
R535
1
*100K_4
2
D D
PROJECT : ZR8
SATA-HDD/ODD 1A

1 2 3 4
5 4 3 2 1
HPR
Codec(ADO) LINE-OUT/SPDIFO(AMP)
R541
R539
*0_4
HPL
*Short_4
ADOGND
MIC1-VREFO-L
+3V 1
Q25
+3V_SPD
ME2347
C554
29
2
MIC1-VREFO-R A32 0.22u/6.3V_4
ADOGND
MIC1-VREFO-L
B2-TEST
R542 *0_4 A41 ADOGND CN22
HP_JD
MIC1-VREFO-L_R
C11 1
C790 10u/6.3V_6 ADOGND 2
HPL HPL-1 HPL_SYS
MIC1-VREFO
C784 R538 68_4 L69 SBK160808T-121Y-N_6 3
Place next to pin 27 HPR R548 68_4 HPR-1 L70 SBK160808T-121Y-N_6 HPR_SYS 4
+
2.2u/6.3V_6 VREF 5
ADOGND
R560 R537 C791 C786
D CBN 7 D
LED
CPVEE
C799 C796 *1K_4 *1K_4 2200p/50V_4 2200p/50V_4 SPDIF_OUT 8 Drive
C778 ADOGND +5VA 6 IC
+5VA + 10u/6.3V_6 0.1u/10V_4
SPDIF_BLACK
2.2u/6.3V_6 ADOGND
ADOGND
C768 C773 C807
10u/6.3V_6 0.1u/10V_4
36
35
34
33
32
31
30
29
28
27
26
25
U35
C803 +5VA
0.1u/10V_4
CBP
CPVEE
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
LDO-CAP
AVSS1
AVDD1
CBN
HP-OUT-R
MIC1-VREFO-R
VREF
10u/6.3V_6
LINEOUT_JD
ADOGND ADOGND
ANALOG
Place next to pin 38 R349
3
Spilt by AGND 37 24 ADOGND +5VA
AVSS2 LINE1-R
Place next to pin 25 10K_4
HP_JD
l
38
AVDD2 LINE1-L
23 Close to JACK connect
LINE_JD# 2
R512 *Short_6 +5VPVDD1 39 22 MIC1_R1 R351 Q36
+5V PVDD1 MIC1-R
1
L_SPK+ 40 21 MIC1_L1 22K_4 2N7002K D20 B2-TEST
C761 C757 C765 C770 SPK-L+ MIC1-L
1
L_SPK- HP_JD VPORT_6
tia
41 20 2
2
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 SPK-L- MONO-OUT Q27
GND_EARTH 42 19 R574 20K/F_4
PVSS1 (Vista Premium Version) JDREF ADOGND
2N7002K ADOGND
43 18 ADOGND
1
PVSS2 Sense-B
Place next to pin 39 R_SPK- 44 17
SPK-R- MIC2-R Placement near Audio Codec ADOGND
R_SPK+ 45 16
SPK-R+ MIC2-L
Spilt by PGND
R513 *Short_6 +5VPVDD2 46 15 C07 HPL_SYS
+5V PVDD2 LINE2-R
GPIO0/DMIC-DATA
3
GPIO1/DMIC-CLK
EAPD# 47 14
SPDIFO2/EAPD LINE2-L EAPD_HP
C762 C758 C766 C771 Spilt by DGND 2 Q46
SPDIF_OUT_R48 SENSEA R575 39.2K/F_4 LINEOUT_JD
SDATA-OUT
13 *MMBT3904
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 SPDIFO Sense A
SDATA-IN
DVDD-IO
1
PCBEEP
RESET#
BIT-CLK
49 R576 20K/F_4 MIC1_JD
DVDD1
DVSS2
PGND
SYNC
ANALOG
C PD# ADOGND C
Place next to pin 46 ALC271X-GR HPR_SYS
1
10
11
12
PCBEEP dont coupling any signals if possible
3
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion
en
2 Q47
1.6Vrms *MMBT3904
+3V R514 *Short_6 +3V_DVDD1
1
PCBEEP C808 1u/16V_6 BEEP_1 R578 47K_4
SPKR [12]
C804 R577
C772 C767 4.7K_4 If either HDA device io power use +1.5V, ADOGND
0.1u/10V_4 10u/6.3V_6 100p/50V_4 all device IO power change to +1.5V
R564 *0_6 +1.5V

R565 0_6 +3V
[24] DMIC_DAT_R 09/30 SB side tide to +3.3V_SUS
[24] DMIC_CLK_R C805 *100p/50V_4 Near CODEC C797 C798
PD# ACZ_RST#_AUDIO 0.1u/10V_4 10u/6.3V_6

0V : Power down Class D SPK amplifer
ACZ_RST#_AUDIO [12]
MIC(AMP)
3.3V : Power up Class D SPK amplifer ACZ_SYNC_AUDIO [12]
ACZ_SDIN0_R R543 22_4
id
ACZ_SDIN0 [12] MIC1-VREFO-R
MIC1-VREFO-L
B2-TEST
ACZ_SDOUT_AUDIO [12]
Place next to pin 9 CHANGE TO BLACK
ACZ_BITCLK_AUDIO_R R544 22_4
ACZ_BITCLK_AUDIO [12]
R321 R297
C788 *22p/50V_4 4.7K/F_4 4.7K/F_4 A41
CN21 BLACK
8/17 reserve for EMI 1 7
A40 MIC1_L1 C546 4.7u/6.3V_6 MIC1_L2 R319 1K/F_4 MIC1_L3 L55 MIC1_L 2
SBK160808T-121Y-N_6 6
GND_EARTH don't coupling AGND and SPK signals MIC1_R1 C519 4.7u/6.3V_6 MIC1_R2 R296 1K/F_4 MIC1_R3 L50 MIC1_R 3
A41 SBK160808T-121Y-N_6 MIC1_JD 4
8
A40 GND_EARTH R520 0_6 5
MIC
B SPDIF_OUT SPDIF_OUT_R B
L68 BLM15BB121SS1 R522 0_6 C508 C537 Normal OPEN Jack
R518 0_6 470p/50V_4 470p/50V_4
C763
*33p/50V_4
R355
R491
R508
nf 0_6
0_6
0_6
Tied at one point only under the
ALC269 or near the ALC269
Max. 100mVrms input for Mic-IN
MIC1_JD
ADOGND ADOGND
1
R354 0_6
R353 0_6 A40 D16 Close to JACK connect
R504 0_6 D31
Power (ADO) R506 0_6 VPORT_6 *VPORT_6
2
1 2
C756 *1000p/50V_4
Demodulation Filter L65 Place close to Codec C755 *1000p/50V_4 D32
VPORT_6
1 2
+5VA ADOGND
DIGITAL ANALOG ADOGND D33
ADOGND VPORT_6
Co
L71 TI201209U220/6A/22ohm_8 1 2
+5V
U37 Internal Speaker(AMP)

3 4
IN OUT
2
GND
1 5 R562 *29.4K/F_4
SHDN SET Mute(ADO)
*G923-330T1UF
R561 + C801 C810 CN8
*10K/F_4 R_SPK- R225 0_6 R_SPK-_1
10u/10V_3216 0.1u/10V_4 +5VA R_SPK+ R224 0_6 R_SPK+_1 1
C811 C806 L_SPK- R223 0_6 L_SPK-_1 25
R509 *0_4 L_SPK+ R222 0_6 L_SPK+_1 36
+
4
0.1u/10V_4 10u/10V_3216 +3V +5V
C07 C07
ramp change to +5V R653 C423 C424 C422 C421 SPEAKER-CONN
A
ADOGND D11 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 A
*10K_4
ADOGND R540 R572
*10K_4 1K_4 EAPD_HP

3
C730, C787 close U37 pin3 and L65 PD# BAS316 D27 ACZ_RST#_AUDIO Q45
*2N7002K
*BAS316 D25 EAPD# 2
BAS316 D26
AMP_MUTE# [34] PROJECT : ZR8
1
Vset =1.25V Quanta Computer Inc.

Vout =Vset[1+AR(1,2)/AR(2,GND)] ADOGND Size Document Number Rev
ALC271X / AMP / SPK 1A

5 4 3 2 1
A B C D E
30
4
4 IN 1 CARD READER (MMC) 4
CN10
XD_RDY 1 20 MS_DATA1
XD_RE# XD-R/B MS-DATA1 MS_BS
2 21
XD_CE# XD-RE MS-BS
3 22
XD_CLE XD-CE 4IN1-GND2 VCC_XD
4 23 VCC_XD
XD_ALE XD-CLE SD-VCC SD_CLK
5 24
XD_WE# XD-ALE SD-CLK SD_DAT0
6 25
XD_WP# XD-WE SD-DAT0 XD_D2
7 26
XD_D0 XD-WP XD-D2 XD_D3
8 27
XD_D1 XD-D0 XD-D3 DATA4
9 28
SD_DAT2 XD-D1 XD-D4 SD_DAT1
10 29
SD_DAT3 SD-DAT2 SD-DAT1 DATA5
11 30
SD_CMD SD-DAT3 XD-D5 DATA6
12 31
SD-CMD XD-D6
l
13 32 DATA7
4IN1-GND1 XD-D7
VCC_XD 14 33
MS_SCLK MS-VCC XD-VCC XD_CD#
15 34
MS_DATA3 MS-SCLK XD-CD-SW SD_WP
16 35
MS_INS# MS-DATA3 SD-WP-SW SD_CD#
17 36
MS_DATA2 MS-INS SD-CD-SW
18
tia
MS_DATA0 MS-DATA2
19
MS-DATA0 Close to Connect pin 14 & pin23
37 4.7u CAP close to pin23
SHIELD1-GND VCC_XD
38
SHIELD2-GND
41
SHIELD3-GND
42
SHIELD4-GND R280 C486 C492
CONN_CARDREADER *5.1K_4 4.7u/10V_6 0.1u/16V_4
3 3
SD_DAT0
en
+1.8V_VDD
T51
T50
DATA0 MS_DATA0
+3V_VDD XD_D0
R308 SP@0_4 XTALSEL C540 C542
Main DFHD36MS006 SD_DAT1
Clock input selection 0.1u/16V_4 0.1u/16V_4
XTALSEL
CRMD_N
DATA1 MS_DATA1
'1' for 48MHz input [Default]
DATA1
DATA0
DATA7
DATA6
CTRL1
CTRL3
NBMD
'0' for 12MHz input Second DFHD36MS012 XD_D1
SD_DAT2
DATA2 MS_DATA2
48
47
46
45
44
43
42
41
40
39
38
37
U17
XTALSEL CTRL0, CRTL 1 trace length shorter , XD_D2
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
GND
VDD
NBMD
TRIST
VDDHM
R329 *100K_4 +3V_VDD and surround with GND.

R326 0_4 SD_DAT3
[11,27] PCIE_RST#_SB_R
C547 *0.47u/10V_4 1 36 CTRL0 DATA3 MS_DATA3
GPON7 CTRL0 DATA5
2 35
id
EXT48IN DATA5 CTRL2 XD_D3
3 34
R516 330_4 RSTN CTRL2
4 33
R515 *Short_6 +3V_VDD REXT GPI4 DATA4
+3V 5 32
VD33P DATA4 DATA3
C764
[12] USBP10+ 6
7
DP AU6437-GBL DATA3
31
30 DATA2
Close to connector
[12] USBP10- DM DATA2
8 29 XD_WP#
4.7u/10V_6 C552 C551 XI VS33P XDWPN GPI2 R276 *Short_4 SD_CLK
9 28
XO XI GPI2 XD_CE# T40
10 27
*5p/50V_4 *5p/50V_4 XO XDCEN EEPDATA CTRL0 XD_ALE
+1.8V_VDD 11 26
VDD EEPDATA GPI1 T39 C494
12 25
VDD GPI1 T38 MS_BS *10p/50V_4
SDWPEN
AGND5V
EEPCLK
VDDHM
CF_V33
XDCDN
VCC33
CTRL4
2 2
SD_WP
GND
VDD
V18
V33
CTRL1 XD_CLE
nf
13
14
15
16
17
18
19
20
21
22
23
24
R281 *Short_4 MS_SCLK

crystal trace width needs at least 10 mils.
pin13 output 20mils EEPCLK T43 SD_CMD
C545 C491
C548 18p/50V_4 XI CAP close PIN11,12 CTRL2 XD_RDY *10p/50V_4
4.7u/10V_6
SD_CD#
Y2 R328
12MHz 270K_4 CTRL3 XD_WE#
*SP@0_4 R299
VCC_XD
C549 18p/50V_4 XO XD_CD# MS_INS#

pin14 output 15mils CTRL4 SD write protect
A01 +1.8V_VDD 1:decided by SDWP[Default] CTRL4 XD_RE#
0:letting SD always
+3V_VDD +3V_VDD write-able
C536 C529
Co
4.7u/10V_6 0.1u/16V_4
1 1
PROJECT : ZR8
AU6437 CardReader 1A

A B C D E
5 4 3 2 1
USB PORT(USB)
+5V_S5
USBPWR1
C723 +
USB BOARD CONN(USB)
31
100u/6.3V_3528 +5V_S5 CN11
C738
D U33 D
1
1u/10V_6 2 8 USBPWR1 CN19 2
IN1 OUT3 C837
3 IN2 OUT2 7 1 1 8 8 3
6 R269 *Short_4 USBP0-_R 2 7 4
OUT1 [12] USBP0- 2 7
USBON# 4 R268 *Short_4 USBP0+_R 3 6 1u/10V_6 5
[34] USBON# EN# [12] USBP0+ 3 6
1 GND 4 4 5 5 6
OC# 5 7
USB_MB 8
1
G547F2P81U USBON# 9
RV2 RV1 [12] OC_7# 10
[12] OC_6# [12] OC_4# 11
4.7P_0402
4.7P_0402
12
l
+3VPCU
2
13
[24,34] LID591#
14
15
16
tia
[12] USBP12-
[12] USBP12+ 17
18
[12] USBP8- 19
[12] USBP8+ 20
21
[12] USBP13- 22
[12] USBP13+ 23
C 24 C
Aces_88501-240N
en
BLUETOOTH CONN(BTM) TOUCHPAD BOARD CONN(TPD)
A41
30mil
1 3 BT_POWER +5V +5V
+3V_S5
20mil
id
Q20 L28 PBY201209T-300Y-N_8 +TPVDD
C445 R248 + C443 C441
2
B .33u/10V_6 47K_4 AO3413 C328 B

2.2u/6.3V_6 1000p/50V_4 R161 R162
10K_4 10K_4 0.1u/10V_4 CN6
1
2
L29 LZA10-2ACB104MT/100mA_6 TPDATA_R 3
[34] TPDATA
L30 LZA10-2ACB104MT/100mA_6 TPCLK_R 4
[34] TPCLK
[34] BT_POWERON# 5
6
nf
A25
A02
C319
*0.01u/16V_4
C320 RIGHT#
*0.01u/16V_4
7
8
9
10 13
CN9 11 14
BT_POWER LEFT# 12
5
R265 *Short_4 USBP9+_R 4 SW3 POWER/B
[12] USBP9+ 3
[12] USBP9- R266 *Short_4 USBP9-_R LEFT# 3 2
2 7
1 6 1 4
BT_CONN SWITCH_1.5
C451
Co
*0.01u/16V_4
A SW2 A
BT_LED
RIGHT# 3 2
1 4
SWITCH_1.5 PROJECT : ZR8

eSATA/USB 1A

5 4 3 2 1
5 4 3 2 1
+3V_S5
POWER BOARD CONN(UIF) LED(UIF) Amber
32
D09
LED3
Power LED R362 715_4 SUSLED#_R 4 2
[34] SUSLED#
R361 20_4 PWRLED#_R 3 1
[34] PWRLED#
+3V_S5 LED_A/B
Blue
1
D +3VPCU +3V_S5 D
A27 +3VPCU
1
PWRLED# 2 R358 *1M_4 +3VPCU
R357 *1M_4
Amber
1
R372 SUSLED# 2 Q28 LED1
*100K_4 BSS84 R359 715_4 BATLED1#_R 4 2
[34] BATLED1#
3
Q29 Battery LED
2 *BSS84 +3V R356 20_4 BATLED0#_R 3 1
[34] ACPRN [34] BATLED0#
CN1
l
3
PWR_LED
12 D09 LED_A/B
Q30
*BSS84 SUS_LED
11
10
14
13
Blue
3
PIPE_LED 9
tia
D1 BAS316 8 B04 RF_LED_EN#
[34] NBSWON#
7
2
NUMLED# 6 A56 *BSS84
[34] NUMLED#
CAPSLED# 5 Communcation LED Q43
[34] CAPSLED#
SATA_LED#_R 4 3 1 +3V
3
2
[27,34] RF_LED# WLAN / Amber
LED4
1
+3V R645 *0_4 R360 715_4 WLAN_LED#_R R646 0_4
[34] RF_LED_EN#
SB side have pull-up POWER/B
C D09 LED C
R374
5
*10K_4 1 B2-TEST
en
4 SATA_LED#_R
[13] SATA_ACT# 2
U21
3
*TC7SH08FU
R373 0_4 CAPSLED# NUMLED#

1
1
D35 D34 LED BOARD CONNECTOR(UIF) +3V
*VPORT_6 *VPORT_6
2
2
C197
0.1u/10V_4
id
SATA_LED#_R
1
D36
B +3V +3V B
*VPORT_6
2
D09 CN4
1
nf B2-TEST 1
Q5
3 R84 2.2K_4
[34] ODD_EJ
[34] POWER_SAVE
P_SAVE_LED
ODD_EJ
POWER_SAVE
2
3
4
5
1
2
3
4 7 7
2
BSS84 5 8
6 6 8
[34] P_SAVE_LED# R644 R643
100K_4 100K_4 SW/LED
A27
ODD_EJ POWER_SAVE
Co
1
D37 D38
*VPORT_6 *VPORT_6
2
A
B2-TEST A
PROJECT : ZR8
POWER/USB/BT/TP/MDC 1A

5 4 3 2 1
5 4 3 2 1
K/B(KBC) CN2
7
5
3
1
CP6
8
6
4
2
MX3
MX2
MX1
MX0
*100p/50V_8P4C
MX7
[34]
[34]
[34]
[34]
[34]
[34]
MY0
MY1
MY2
MY3
MY4
MY5
MY0
MY1
MY2
MY3
MY4
MY5
MY6
1
2
3
4
5
6
+3VPCU
RP16 10K_10P8R CPU FAN(THM)

33
7 8 [34] MY6 7
5 6 MX6 MY7 8 10 1 MX3
[34] MY7
3 4 MX5 MY8 9 MX4 9 2 MX2
D [34] MY8 +5V +5V D
1 2 MX4 MY9 10 MX5 8 3 MX1 +3V +3V +3V
[34] MY9
CP5 *100p/50V_8P4C MY10 11 MX6 7 4 MX0
[34] MY10
7 8 MY0 MY11 12 MX7 6 5
[34] MY11
5 6 MY1 MY12 13
[34] MY12
3 4 MY2 MY13 14 R60 R389 R390 R610
[34] MY13
1 2 MY3 MY14 15 R72 R68 *Short_6
[34] MY14
CP1 *100p/50V_8P4C MY15 16 10K_4 10K_4 10K_4
[34] MY15
MY4 MY16 *10K_4 10K_4
+5V_FAN
7 8 [34] MY16 17
5 6 MY5 MY17 18
[34] MY17
3 4 MY6 MX7 19 FAN_PWM_E
[34] MX7
1 2 MY7 MX6 20 CN12
[34] MX6 [34] FANSIG
CP2 *100p/50V_8P4C MX5 21
l
[34] MX5 1
2
7 8 MY8 MX4 22
[34] MX4 2
3
5 6 MY9 MX3 23
[34] MX3 3
3 4 MY10 MX2 24 27 2 Q4 1 3 FAN_PWM_CN
[34] MX2 [2,4,12] PM_THERM# 4
1 2 MY11 MX1 25 28 MMBT3904
tia
[34] MX1
CP3 *100p/50V_8P4C MX0 26 Q3 30mil FAN_CONN
[34] MX0
1
7 8 MY12 MMBT3904
MY13 KB [34] CPUFAN#
5 6
3 4 MY14
1 2 MY15
CP4 *100p/50V_8P4C
C585 *100p/50V_4 MY16
C
C586 *100p/50V_4 MY17 C
en
id
B B
nf
Co
A A
PROJECT : ZR8
KB/FAN/EE RETURN CAP 1A

5 4 3 2 1
5 4 3 2 1
A41
EC(KBC) L38 PBY160808T-220Y-N_6
30mil C375
0.1u/10V_4
+A3VPCU
C382
4.7u/10V_6
+3V
I/O ADDRESS SETTING(KBC)

34
+3VPCU R209 E775AGND
2.2/F_6 D7 C342 C343
+3VPCU_EC 0.03A(30mils)
BAS316 4.7u/10V_6 0.1u/10V_4
C374 C313 C373 C349 C309 C288 SHBM=0: Enable shared memory with host BIOS
115
102
19
46
76
88
4
4.7u/10V_6 0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 U13 Take care of power side
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
D D
E775AGND C392 10U/6.3V_8 ICMNT
C391 0.01u/16V_4
3 97 SHBM SHBM_R R196 10K_4
[11,27] LPC_LFRAME# LFRAME GPIO90/AD0 TEMP_MBAT [35]
126 98 WL_SW T22
[11,27] LPC_LAD0 LAD0 GPIO91/AD1
127 99 TPD_TRIP
[11,27] LPC_LAD1 LAD1 GPIO92/AD2
128 A/D 100 ICMNT 1/13 Comfirm by vendor mail :
[11,27] LPC_LAD2 LAD2 GPIO93/AD3 ICMNT [35]
[11,27] LPC_LAD3 1 108 Disabled ('1') if using FWH device on LPC.
CLK_PCI_775 CLK_PCI_775 LAD3 GPIO05
[11] CLK_PCI_775 2 96
LCLK GPIO04 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
[11] CLKRUN# 8
GPIO11/CLKRUN
101 POWER_SAVE [32]
R205 GPIO94/DA0
[12] SIO_A20GATE 121 105
GPIO85/GA20 GPI95/DA1 TP_LED#
*22_4
D/A GPI96/DA2
106
TP_SW#
T23
[12] SIO_RCIN# 122 107 T25
KBRST/GPIO86 GPI97
l
[12] SIO_EXT_SCI# 29
ECSCI/GPIO54 LPC
64 ACIN [35]
C365 GPIO01/TB2 NBSWON#
[24] EC_FPBACK# 6 95 NBSWON# [32]
GPIO24/LDRQ GPIO03
*10p/50V_4 93 LID591# [24,31]
NOCIR# GPIO06/IOX_DOUT
124 94 SUSB# [12]
SM BUS PU(KBC) B2-TEST
tia
GPIO10/LPCPD GPIO07
119 MXM_SMCLK12 [21]
GPIO23/SCL3 MBCLK R156 2.2K_4
[9,11,24] A_RST#_SB 7
LREST GPIO30/CIRTX2
109 ACPRN [32] 3'rd SMBUS for dGPU MBDATA R150 2.2K_4
+3VPCU
120 MXM_SMDATA12 [21]
GPIO31/SDA3 thermal sensor MXM_SMCLK12 R214 SW@2.2K_4
[31] USBON# 123 65 BATLED0# [32] +3V_D_EXT
NOCIR# GPIO67/PWUREQ GPIO32/D_PWM MXM_SMDATA12 R215 SW@2.2K_4
GPIO33/H_PWM
66 BATLED1# [32] A20
[11] IRQ_SERIRQ 125 15 VRON [37,43]
SERIRQ GPIO36
16 SUSLED# [32]
R210 GPIO40/F_PWM AC_OFF
[12] SIO_EXT_SMI# 9 17 T20
*10K_4 GPIO65/SMI GPIO42/TCK
GPIO GPIO43/TMS
20 AMP_MUTE# [29]
21 VR2.5_ON [42]
GPIO44/TDI
[33] MX0 54 22 CPUFAN# [33]
KBSIN0 GPIO45/E_PWM CPU_SMBCLK R151 10K_4
[33] MX1 55 23 PANEL_COLOR [24] +3V
KBSIN1 GPIO46/CIRRXM/TRST CPU_SMBDATA R157 10K_4
[33] MX2 56 24 VIN_ON [35]
KBSIN2 GPO47/SCL4 EC_ODD_EN R170 10K_4
[33] MX3 57 25 D/C# [35]
KBSIN3 GPIO50/TDO 1.2V_ON R181 *10K_4
[33] MX4 58 26 S5_ON [36,38,43,44]
With CIR module – floating KBSIN4 GPIO51
[33] MX5 59 27 HDMI_HPD_EC# [25]
Without CIR module – pull KBSIN5 GPIO52/CIRTX2/RDY EC_ODD_EN
C
down 10K [33] MX6 60
KBSIN6 GPIO53/SDA4
28 EC_ODD_EN [28] A26 C
[33] MX7 61 91 DNBSWON# [12]

KBSIN7 GPIO81 EC_GPIO82
110 T24
MY0 GPO82/TEST
[33] MY0 53
KBSOUT0/JENK GPO84/TRIST
112 RF_LED_EN# [32] A56 B04
[33] MY1 52 80 PANEL_ENG [24]
KBSOUT1/TCK GPIO41
en
[33] MY2 51
KBSOUT2/TMS
[33] MY3 50
KBSOUT3/TDI ODDLED
[33] MY4 49
KBSOUT4/JEN0 KB GPIO56/TA1
31 T18
[33] MY5 48 117 SUSON [40]
KBSOUT5/TDO GPIO20/TA2/IOX_DIN
[33] MY6 47 63 FANSIG [33]
KBSOUT6/RDY GPIO14/TB1
[33] MY7 43
KBSOUT7
[33] MY8 42
KBSOUT8 TIMER GPIO15/A_PWM
32 CONTRAST [24]
[33] MY9 41 118 NUMLED# [32]
KBSOUT9/SDP_VIS GPIO21/B_PWM
[33] MY10 40 62 PWRLED# [32]
KBSOUT10/P80_CLK GPIO13/C_PWM
[33] MY11 39 81 CAPSLED# [32]
KBSOUT11/P80_DAT GPIO66/G_PWM
38
[33]
[33]
MY12
MY13 37
KBSOUT12/GPIO64
KBSOUT13/GPIO63 ODD_EJ
SPI FLASH(KBC)
[33] MY14 36
KBSOUT14/GPIO62 GPIO77/SPI_DI
84
SHBM_R
ODD_EJ [32] A56
[33] MY15 35
KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM
83
RF_LED_R R615 *0_4
U15 Change to 1M ==>AKE5GFK0Z09 / AKE3GZN0N00 / AKE3GZP0801
[33] MY16 34 82 RF_LED# [27,32]
GPIO60/KBSOUT16 GPIO75/SPI_SCK +3VPCU
[33] MY17 33
GPIO57/KBSOUT17
75 RSMRST#_uR R173 *Short_4 U15
GPIO72/IRRX1/SIN2 ICH_RSMRST# [12]
MBCLK 70 73 SPI_SDI_uR R220 22_4 SPI_SDI_uR_R 2 8
[35] MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# [12] SO VDD
1'st SMBUS for Smart Battery / Charger MBDATA 69 74 PWROK_EC_uR R167 *Short_4
[35] MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC [4,15]
[4] CPU_SMBCLK CPU_SMBCLK 67 SMB IR 113 R219 100K_4 SPI_SDO_uR 5 7 C420
id
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN [27] SI HOLD
CPU_SMBDATA CIRR_X2
2nd SMBUS for CPU thermal sensor. [4] CPU_SMBDATA 68
GPIO74/SDA2 GPIO34/CIRRXL
14
HWPG
T21
SPI_SCK_uR 0.1u/10V_4
114 6 3
GPIO16/CIRTX SCK WP
111 P_SAVE_LED# [32]
GPO83/SOUT_CR/XORTR R218 10K_4 SPI_CS0#_uR
[31] TPCLK 72 +3VPCU 1 4
GPIO37/PSCLK1 CE VSS
[31] TPDATA 71
1.2V_ON GPIO35/PSDAT1 SPI_SDI_uR W25X16AVSSIG
[38] 1.2V_ON 10 86
GPIO26/PSCLK2 F_SDI SPI_SDO_uR_R R212 22_4 SPI_SDO_uR
[31] BT_POWERON# 11
GPIO27PSDAT2 PS/2 F_SDO
87
SPI_CS0#_uR
[40,42,43] MAINON 12
GPIO25/PSCLK3 FIU F_CS0
90 1/13 Comfirm by vendor mail :
13 92 SPI_SCK_uR_R R213 22_4 SPI_SCK_uR
GPIO12/PSDAT3 F_SCK If the Southbridge enables 'Long Wait Abort' by
R175 781@0_4 E775_32KX1 77 30 ECDB_CLOCK default, the flash device should be 50MHz (or faster)
[11] RTC_CLK GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN T19
B B
85 VCC_POR# R216 47K/F_4 +3VPCU
VCC_POR
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R178 *775@20M_6 E775_32KX2 79 104 VREF_uR R211 *Short_4 +A3VPCU

GPIO02 VREF
R180 NPCE781
nf
5
18
45
78
89
116
103
VCORF_uR 44
*775@33K/F_4 SM BUS ARRANGEMENT TABLE

Y1 A41
1 4 T103 SM Bus 1 Battery
L39 PBY160808T-220Y-N_6
C330 +3V
*775@15P/50V_4 C336 C289 SM Bus 2 PCH HWPG(KBC)
*32.768KHz *775@15P/50V_4
E775AGND 1u/6.3V_4
SM Bus 3 MMB3 and EEPROM R217
10K_4
E775AGND SM Bus 4 HDMI Controller, MMB1, MMB2 and VGA Thermal

D12 BAS316
[40] HWPG_1.5V
D13 *BAS316 HWPG
Co
[39] HWPG_0.95V
D11 BAS316
[36] SYS_HWPG
D10 BAS316
[38] HWPG_1.1V
D9 BAS316
Palm Rest Thermal Sensor(THM) POWER-ON Switch(KBC) [38,42] HWPG_1.8V
INTERNAL KEYBOARD STRIP SET(KBC)
+3V
+3VPCU
R284
Near TP on TOP side and MY0 R146 10K_4
[2] HWPG
47K_6 only for AMD platform
A
Palm Rest use. C01 A
TPD_TRIP NBSWON#
1
G3
RT1 *SHORT_PAD1
100K/F/NTC_4
2
t
E775AGND PROJECT : ZR8
WPCE775C_0DG & FLASH 1A

5 4 3 2 1
5 4 3 2 1
A01
A41
D VA1 D
PL4 PD6 PR197
PJ2 UPB201212T-121Y-N_8 SBR1045SP5-13 PQ37 0.01/F_7520 VIN_SRC PQ39
POWER_JACK 1 FDD6685 FDD6685
1 VA 3 VA2 3 4 1 2 3 4
2 2
1
3 PL3
4 UPB201212T-121Y-N_8
1
PC115 PC109 PR186 VIN_SRC PC124 PC117 PR27
0.1u/50V_6 PD7 0.1u/50V_6 220K/F_6 0.1u/50V_6 2200p/50V_6 33K_6
SMAJ20A
2
CSIP_1
PC116 PC118
0.1u/50V_6 2200p/50V_6
1 6
PD1 PR28
l
B2-TEST SW1010CPT PR174 2 5 PR2 *Short_6 10K_6
D/C# [34]
220K/F_6
VA 3 4
3
PQ36
tia
C13 IMD2AT108
EC54 EC55 VIN_SRC 2
22U/25V_1210 22U/25V_1210
PQ6
CSIP_1 DMN601K-7
1
VIN_SRC
CLOSE TO PJ2 PIN 1,2 B2-TEST
PC32
1u/16V_6
PR44 PR45
10/F_6 10/F_6
PC129
PC31 PC35 EC4 EC41 EC53
0.1u/50V_6 PR41 2200p/50V_6 0.1u/50V_6 4.7u/25V_8 *22U/25V_1210 *22U/25V_1210
4.7_6 PC29
1u/16V_6
27 CSIN
28 CSIP
C ISL88731_VDDP C
5
6
7
8
33
32
31
30
26
21
1
+3VPCU PD8
en
*RB500V-40 4
NC
GND
GND
GND
GND
CSSN
VCC
CSSP
VDDP
PC21 PR42 PC127
0.1u/50V_6 2.7_6 0.1u/50V_8
+3VPCU 11 25 88731B_2 88731B_1 PQ45
VDDSMB BOOT AO4468 PR200
PL7 0.01_3720
3
2
1
[34] MBDATA 9 24 ISL88731_UGATE 6.8uH/6.5A
PR30 SDA UGATE BAT-V
1 2
100K_6
5
6
7
8
[34] MBCLK 10 23 ISL88731_PHASE
SCL PHASE
13 20 ISL88731_LGATE 4 PR46
[34] ACIN ACOK LGATE 2.2_6
B2-TEST
PR43 PC33 19
49.9/F_6 0.1u/50V_6 PGND PQ46
DCIN 22 AO4710 PC34
DCIN PR38 2200p/50V_6 PC8 PC126 PC125
3
2
1
id
PR40 10/F_6 2200p/50V_6 10u/25V_1206 10u/25V_1206
82.5K_6 PU4 18 CSOP CSOP_1
PC4 88731ACSET ISL88731A CSOP CSOP_1
2
0.1u/50V_6 ACIN
2 1 PC23
3 0.1u/50V_6 BAT-V
PC2 PR39 VREF
A41 17 CSON BAT-V
100p/50V_6 PL1 22K/F_6 CSON
UPB201212T-121Y-N_8 4 PR33 PR36
ICOMP 10/F_6
16
MBAT+ BAT-V NC
A53 5 *Short_4
PJ1 PL2 NC
UPB201212T-121Y-N_8 15 BAT-V
B 10 1 VBF B
6
2 VCOMP PR32
29
3 TEMP_MBAT_C
nf GND 100_4
GND
4 TEMP_MBAT [34]
ICM
NC
NC
5 PR4
6 100_4 PR34
+3VPCU
7
14
12
7 2.21K/F_6
9 8 PR1 PR10
Batt_Conn *Short_4 100K/F_6 VIN_SRC VIN
PC1 PC3 PQ42
47p/50V_6 47p/50V_6 PC22 AOL1413
0.01u/50V_6
ISL88731 thermal pad 1
tie to Pin12 2 5
ICMNT [34] 3
PR178 PR177
100_4 100_4 PC27 PC26 PC24
4
*1u/16V_6 0.01u/50V_6 *0.01u/50V_6 A01 A39 PC111 PR37
MBCLK [34] 1U/25V_6 150K_6
Co
MBDATA [34] A46 A47
PU1
CM1293A-04SO PR35
1 6 MBDATA 39K_6
CH1 CH4
2 5 +3VPCU A48
3
VN VP
TEMP_MBAT_C 3 4 MBCLK
CH2 CH3
[34] VIN_ON 2
Add ESD diode base on EC FAE suggestion
PQ5
DMN601K-7
1
A A
PROJECT : ZR8
CHARGER (ISL88731) 1A

5 4 3 2 1
5 4 3 2 1
MAIND
MAIND [40,43]
PR241 VL
[2,4,43,44] SYS_SHDN# A28
A28 *Short_4
D B2-TEST D
VIN_SRC VIN_SRC
PR138
39K/F_4 D07
1
+
A29 + PD12 PR181 PR253 B2-TEST
*ZD5.6V 0_4 PC186 *0_6
3V5V_EN PC98 0.01u/16V_4
0.1u/50V_6
2
PR256
PR147 PR146 VL
*Short_4 *Short_4 PR255
PR257 PC97 *Short_4 *0_4 EC17 PC95 PC188
PC193 PC101 PC187 EC19 390K/F_4 1u/16V_6 0.1u/50V_6 2200p/50V_4 PC185 *100u/25V_6.3*5.8
5V_EN
3V_EN
100u/25V_6.3*5.8 2200p/50V_6 4.7u/25V_8 0.1u/50V_6 PC99 4.7u/25V_8 OCP : 8A
l
5
6
7
8
4.7u/10V_8
5.03A
8206_ONLDO REF 3V_DH 4
PR160 +3VPCU
8
7
6
5
tia
OCP: 10A PC96 *Short_4
PR161 0.1u/50V_6
150K/F_4 PQ66
6.15A
8
7
6
5
4
3
2
1
4 5V_DH AO4468 A28
+5VPCU PL14
NC1
LDOREFIN
VIN
VCC
TON
LDO
ONLDO
REF
3
2
1
B2-TEST 2R2uH-5.8mR/14A
A28 3V_LX
PQ67 PR158
5
6
7
8
AO4468 9 32 REFIN2 191K/F_6
PL16 BYP REFIN2
10 31
1
2
3
2R2uH-5.8mR/14A OUT1 PU10 ILIM2 PD11 PR154
B2-TEST 5V_LX
11
FB1 OUT2
30
SKIP
12 29 4 SX34 2.2_6
PR156 DDPWRGD_R 13 ILIM1 RT8206B SKIP# DDPWRGD_R
28
8
7
6
5
220K/F_6 5V_EN PGOOD1 PGOOD2 3V_EN PC89 + PC183
14 27
EN1 EN2 PR254 0.1u/50V_6 330u/6.3V_6X5.7
15 26
PR252 PR163 DH1 DH2 PQ65 PC92 0_6
16 25
+ *0_4 2.2_6 PD14 5V_DL LX1 LX2 AO4710 2200p/50V_6
4 37
PC198 PC203 PC105 SX34 Pad5
C 36 C
3
2
1
Pad4
PGND
PVCC
GND1
*10u/25V_1206 330u/6.3V_6X5.7 0.1u/50V_6
BST1
BST2
Pad3
Pad2
Pad1
NC2
DL1
DL2
PC88 PC86 PR157
PC103 PQ68 0.1u/50V_6 0.1u/50V_6 *0_4
en
2200p/50V_6 AO4710 PR132
35
34
33
17
18
19
20
21
22
23
24
PR250 1 PR137 1/F_6 +3VPCU_OUT PR155 *Short_4
2
3
0_4 1/F_6
3V_DL
VL SKIP REF PR251

+5VPCU_FB PR234 *0_6
*0_6 PR133 *Short_4 PR159
2 PC83 *0_6
PD5 1u/16V_6
1PS302 3
PC102 PR162
1 0.1u/50V_6 0_6 +3VPCU
PC189 PR233 *Short_4

PC100 2 0.1u/50V_6
0.1u/50V_6 PD13
OCP:10A 1PS302 3 OCP:8A
L(ripple current) L(ripple current) PR135
1
id
*100K_4
=(19-5)*5/(2.2u*0.4M*19) =(19-3.3)*3.3/(2.2u*0.5M*19)
~4.18A +15V_ALWP RT8206B_PIN20 ~2.48A PR152
+15V
DDPWRGD_R
SYS_HWPG [34]
Iocp=10-(4.18/2)=7.91A PR258 PR259 Iocp=8-(2.48/2)=6.67A
22_8 *200K/F_4 PR242 *Short_4
Vth=7.91A*14.2mOhm=112.322mV PC190 *39K/F_4 Vth=6.67A*15mOhm=94.714mV
R(Ilim)=(112.322mV*10)/5uA 0.1u/50V_6 R(Ilim)=(94.714mV*10)/5uA
~220K ~191K
B B
nf
VIN_SRC +3V_S5 +5V_S5 +15V VIN_SRC +5VPCU +5VPCU +3VPCU +3VPCU
Co
PR167 PR170 PR166 PR165 PR164
3
1M_6 22_8 22_8 1M_6 *1M_6
5
6
7
8
5
6
7
8
5
6
7
8
S5D 2
S5D 4
MAIND 4 MAIND 4
3
PQ64
PQ30 AO3404
1
2 AO4468 PQ31 PQ62
[34,38,43,44] S5_ON
AO4468 AO4468
2 2 2 +3V_S5 1.3A
3
2
1
PR171 PQ35 PQ33

1
3
2
1
3
2
1
PQ34 1M_6 DMN601K-7 DMN601K-7 PC104

DTC144EUA PQ32 *2200p/50V_4
+5V_S5
1
DMN601K-7
A
3A +5V +3V
A
3.15A 3.2A
PROJECT : ZR8
SYSTEM 5V/3V (RT8206) 1A

5 4 3 2 1
A B C D E
3A B2-TEST
PL13
2.2uH/8A B2-TEST
LGATE_NB
CPU_VDDNB_CORE VIN
Offset &
OFS/VFIXEN Droop SVI VFIX
[2] CPU_VDDNB_FB_H
A01 + PC69
GND O O X
1
0.1u/50V_6
D1
D1
S2
G2
+3.3V X X O PR127
10/F_6 + PC167
+5V X O X 10u/25V_1206
PQ57 PC173 PC175
2
[2] CPU_VDDNB_FB_L AO4932 100u/25V_6.3*5.8 *10u/25V_1206
S1/D2
PR126
G1
Metal VID Codes 10/F_6
+5VPCU
8
4 4
SVC SVD Output PC168
PR240 330u/2V_7343
0 0 1.1 10/F_6 UGATE_NB
PC182
0 1 1.0 1u/25V_8
PR235 PC82
1 0 0.9 22.1K/F_4 1000p/50V_6
PR128 *Short_8
1 1 0.8
PC84
33p/50V_4
VFIXEN VID Codes VIN
l
SVC SVD Output PR246 PC85 B2-TEST
10/F_6 1200p/50V_4
VIN
0 0 1.4
PC91 PR123 LGATE_NB PC176
0 1 1.2 0.1u/50V_6 11.3K/F_4 +
tia
PR136 4.7u/25V_8
1 0 1.0 44.2K/F_4 PHASE_NB A30
5
1 1 0.8 20A
UGATE_NB PC78 PC172 PC178 EC13 PC179
0.1u/50V_6 *10u/25V_1206 0.1u/50V_6 *2200p/50V_4 100u/25V_6.3*5.8
+3V UGATE_0 4
49
48
47
46
45
44
43
42
41
40
39
38
37
+5VPCU
B2-TEST PR247 0_4 PQ56
1
2
3
PR117 AOL1448
GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
+3V 1/F_6 PL11
PR265 PR248 *0_4 0.36uH/25A
10K_4 1 2 +VCORE
1 36
PR144 PR249 *10K/F_4 OFS/VFIXEN BOOT_NB PR118 PC75 A06 A06
4
*Short_4 1/F_6 0.1u/50V_6 PR94
2 35 1_6
[15,39] CPU_COREPG PGOOD BOOT_0
5
3 + + + 3
PR131 PR130
+1.8V +3V PR145 *Short_4 3 34 UGATE_0 *Short_6 *Short_6
PWROK UGATE_0 PC65
Pin 49 is GND Pin 4 4
en
1000p/50V_4
PR142 *Short_4 4 33 PHASE_0 PQ54 PQ70 PC56 PC58 PC59
1
2
3
1
2
3
[2] CPU_SVD
2
PQ63 SVD PHASE_0 AOL1718 AOL1718 330u/2V_7343 330u/2V_7343 *330u/2V_7343

*DTC144EU PR245
*10K/F_6 PR143 *Short_4 5 32 A45 ISP_0
[2] CPU_SVC SVC PGND_0
B2-TEST
1 3 ISN_0
[2,11] CPU_PWRGD_SVID_REG
PR148 *0_4 6265_EN 6 PU9 31 LGATE_0 B2-TEST
[34,43] VRON ENABLE LGATE_0
2 1 ISL6265A +5VPCU
[42,43] HWPG_2.5V
PR243 0_4 PR179 0_4 A31 VIN
6265_EN 7 30
RBIAS RBIAS PVCC PC171
VDIFF_RC PC73 +
PR149 PR140 OCSET 8 29 LGATE_1 2.2u/10V_8 4.7u/25V_8
5
PR150 PC93 19.6K/F_4 97.6K/F_4 OCSET LGATE_1
PR153 255/F_4 4700p/25V_4
A30
A43
100K_4 VDIFF 9 28
VDIFF_0 PGND_1 UGATE_1 PC174 PC177 EC25 PC180
4
B2-TEST PR141 *10u/25V_1206 0.1u/50V_6 *2200p/50V_4 100u/25V_6.3*5.8
1K/F_4 FB_ISL6265A 10 27 PHASE_1 PQ58
1
2
3
FB_0 PHASE_1
id
AOL1448
ISL6265A_COMP_R ISL6265A_COMP 11
COMP_0 UGATE_1
26 UGATE_1 20A
PL12
PR151 PC94 0.36uH/25A B2-TEST +VCORE
54.9K/F_4 1200p/50V_4 ISL6265A_VW 12 25 1 2
VW_0 BOOT_1
COMP_1
VDIFF_1
VSEN_0
VSEN_1
PC90 PC184 PR244 PR119 PC76 A06 A06
RTN_0
RTN_1
4
ISN_0
ISN_1
ISP_0
VW_1
ISP_1
180p/50V_4 1000p/50V_6 6.81K/F_4 1/F_6 0.1u/50V_6 PR95
FB_1
5
1_6
+ + +
PR120 PR115
13
14
15
16
17
18
19
20
21
22
23
24
LGATE_1 4 4 *Short_6 *Short_6
PC64
2 2
PQ55 PQ71 1000p/50V_4
1
2
3
1
2
3
AOL1718 AOL1718 PC55 PC204 PC205
+VCORE
PR134
10/F_6
Close to
CPU socket
ISP_0
PR139
18.2K/F_4
ISP_0_R
PR238
3.92K/F_4
PC87
0.1u/50V_6
nf PC77
0.1u/50V_6
PR116
3.92K/F_4
ISN_1 A45
ISP_1
ISN_1
*330u/2V_7343 330u/2V_7343 330u/2V_7343
ISN_0 ISP_1
PR121
[2] CPU_VDD0_FB_H PC181 18.2K/F_4
*1000p/50V_6
[2] CPU_VDD0_FB_L
PR239 +1.5VSUS PR231

10/F_6 Parallel *6.81K/F_4
PR232
1K/F_4
Co
PR236 D14
D14 Close to *0_4
CPU socket
PC81 PC79
*4700p/25V_4 *1200p/50V_4
PR237
*10/F_6
[2] CPU_VDD1_FB_L
PR125 PC80
[2] CPU_VDD1_FB_H *1K/F_4 *180p/50V_4
PR129
10/F_6
1 PR122 1
+VCORE
PR124 *54.9K/F_4
*255/F_4
PROJECT : ZR8
CPU_CORE 1A

A B C D E
5 4 3 2 1
D D
VIN
+5VPCU
B2-TEST
PR215 PC156
10/F_6
5
6
7
8
PD2 4.7u/25V_8 OCP: 10A
RB500V-40
l
PR67 PR218 6A
1M_6 2.2/F_6 PC42 4
1u/16V_6 +1.1V_S5
PR77 EC9 PC48
PU6 *Short_6 0.1u/50V_6 2200p/50V_4
tia
UP6111AQDD PQ51
PC45 AO4468
PR73 *Short_4 S5_ON_+1.1V_S5 15 13 0.1u/50V_6
3
2
1
[34,36,43,44] S5_ON EN/DEM BOOT
+3V 16 12 UGATE-1.1V PL9
PC149 TON UGATE 1R0uH-3mR/15A
*0.1u/50V_6 1 11 PHASE-1.1V
VOUT PHASE
2 10 PR78
VDD OC
5
6
7
8
PR68 7.15K/F_6
*10K/F_6 3 9 PC44 PR80
FB VDDP 1u/16V_6 1_6
4 8 LGATE-1.1V 4 +
[34] HWPG_1.1V PGOOD LGATE
6 7
GND PGND PC47
5 17 1000p/50V_4
NC TPAD PQ50
C C
14 AO4710
3
2
1
NC PC157 PC151 PC150
PC41 PC148 A45 560u/2.5V_6X5.7 *10u/10V_8 0.1u/50V_6
en
1u/16V_6 *1000p/50V_6
B2-TEST
Rds*OCP=RILIM*20uA
PR66
5.1K/F_6 PC147
R1 *33p/50V_6
1.1V_FB
VOUT=(1+R1/R2)*0.75
PR216
10K/F_6
TON=3.85p*RTON*Vout/(Vin-0.5) AO4710 Rdson=11.7~14.2mOhm R2 PR75
id
0_6
L(ripple current)
Frequency=Vout/(Vin*TON) =(19-1.1)*1.1/(1u*272k*19)
~3.81A
TON=3.85p*1M*1/(Vin-0.5)
14.2m*10=RILIM*20uA
Frequency=1/(0.0036767)=272K RILIM=7.1K--- 7.15K
B B
nf
VIN_SRC +1.1V +15V +1.1V_S5
PR99 *0_4
[43] HWPG_0.9V
PR52 PR65 PR62
Co
5
6
7
8
1M_6 22_8 1M_6
PR86 *0_4 4
[34] 1.2V_ON
3
B2-TEST
3
PQ19
PR57 AO4468
PR87 0_4 1M_6 2 2
[34,42] HWPG_1.8V
2 3
2
1
PQ13 PQ7
PQ8 DMN601K-7 DMN601K-7 PC39
PR60 DMN601K-7 *2200p/50V_4
1
+1.1V
100K_6
1
5.5A
"HWPG_0.9V"=CPU_COREPG
A A
PROJECT : ZR8
VCCP 1.1V(UP6111A) 1A

5 4 3 2 1
5 4 3 2 1
D D
VIN
+5V_S5
B2-TEST
l
PR91 PC158
10/F_6 PD3
5
6
7
8
RB500V-40 4.7u/25V_8 OCP: 10A
PR221 B2-TEST PR93 7.5A
tia
1M_6 2.2/F_6 PC53 4
PR266 1u/16V_6 NB_CORE
100K_4 PR222 EC10 PC50
*Short_6 0.1u/50V_6 2200p/50V_4
PU14 PQ53
UP6111AQDD PC162 AO4468
PR220 *Short_4 15 13 0.1u/50V_6
[15,37] CPU_COREPG
3
2
1
EN/DEM BOOT
+3V UP6111AQDD_PIN16 16 12 UGATE-NB PL10
PC160 TON UGATE 1R0uH-3mR/15A
*0.1u/50V_6 1 11 PHASE-NB
VOUT PHASE
UP6111AQDD_PIN2 2 10 PR224
5
6
7
8
PR227 VDD OC 7.15K/F_6
*10K/F_6 3 9 PC166 PR89
FB VDDP 1u/16V_6 1_6
4 8 LGATE-NB 4 +
[34] HWPG_0.95V PGOOD LGATE
C C
6 7
GND PGND PC51
5 17 PQ52 1000p/50V_4
NC TPAD
en
AO4710
14
3
2
1
NC PC164 PC159 PC52
PC163 PC161 A45 560u/2.5V_6X5.7 *10u/10V_8 0.1u/50V_6
1u/16V_6 *1000p/50V_6
VOUT=(1+R1/R2)*0.75 Rds*OCP=RILIM*20uA
PR225 PC165
PR226 R1 2.74K/F_4 *33p/50V_6 PR92 +5VPCU
13.3K/F_4
NB_CORE_FB NB_CORE_FB
*Short_6
3
id
PR85
PR223 10K/F_4
10K/F_6
R2 2
PQ21
DMN601K-7 PC49
0.01u/25V_4 PR90 PR84
HI --- 0.95V
1
100_4 *0_4
LOW ---1.1V
3
B B
TON=3.85p*RTON*Vout/(Vin-0.5) 2 +NB_CORE_ON [9]
AO4710 Rdson=11.7~14.2mOhm
Frequency=Vout/(Vin*TON)
nf
L(ripple current)
PQ20
DMN601K-7
PR88
1
=(19-1.05)*1.05/(1u*272k*19) *100K_4
TON=3.85p*1M*1/(Vin-0.5) ~3.646A
14.2m*10=RILIM*20uA
Frequency=1/(0.0036767)=272K RILIM=7.1K--- 7.15K
Co
A A
PROJECT : ZR8
NB_CORE(UP6111A) 1A

5 4 3 2 1
5 4 3 2 1
[PWM]
PC132
10u/10V_8
D D
PR201 PC133 A28

0_6 0.1u/50V_6
8207A_VBST
+0.75V_DDR_VTT
VIN
8207A_DH
PC131 PC135
1.71A 10u/10V_8 10u/10V_8 8207A_LX PC136
+
5
8207A_DL 4.7u/25V_8
B2-TEST
4
EC5 PC130 PC134
25
24
23
22
21
20
19
OCP 22A
l
PQ49 0.1u/50V_6 2200p/50V_6 *100u/25V_6.3*5.8
1
2
3
AOL1448
18A
LL
DRVL
GND
VLDOIN
DRVH
VTT
VBST
PL8
0.56uH/25A
C15 1 18 +1.5VSUS
VTTGND PGND
tia
2
VTTSNS CS_GND
17 A28
5
3 RT8207A 16 PR48 PR47
GND PU11 CS 4.02K/F_6 1_6
+1.5VSUS 4 15 4 4 + +
MODE V5IN +5V_S5
PQ47 PQ48 PC36
1
2
3
1
2
3
5 14 AOL1718 AOL1718 1000p/50V_4
+SMDDR_VREF VTTREF V5FILT
PC37 PR203 PC137
VDDQSNS
VDDQSET
PC138 +5V_S5 1u/6.3V_4 5.1/F_6 1u/6.3V_4
0.75A 0.033u/50V_6
6
COMP PGOOD
13
PC139 PC143 PC144
A45 10u/10V_8 560u/2.5V_6X5.7 *560u/2.5V_6X5.7
NC
NC
C C
S3
S5
PR204 +3VPCU
100K/F_6
7
10
11
12
FOR DDR III
en
HWPG_1.5V [34]
PR202
PR49 (For RT8207A 400KHZ )
VIN
620K/F_4
S5_1.8V PR207
*Short_6 0_6 SUSON [34]
S3_1.8V PR208
*0_6 MAINON [34,42,43]
PR59 +5V_S5
*0_6
[2] VDDIO_FB_H
PR206
*0_4
PC38 PR205
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
AO1718 Rdson=3.8~4.3mOhm
id
8207A_SET
L(ripple current)
=(9-1.5)*1.5/(0.56u*400k*9)
PR54
0_6 ~5.58A +1.5VSUS
PR58 S5_1.8V S3_1.8V
10K/F_4
Vtrip= (22-2.79)(*4.3mohm/2)=0.0413V
RILIM=Vtrip/10uA~4.13K
[2] VDDIO_FB_L
5
6
7
8
PR61
*0_4
B B
MAIND 4
[36,43] MAIND
nfVIN_SRC +1.5V_GPU +15V +1.5VSUS
PQ29
AO4468
OK
3
2
1
PR50 PR64
5
6
7
8
SW@1M/F_6 SW@22_8 PR63
SW@1M/F_6
+1.5V
DGPU_1.5V_ON_R
PR51 SW@0_6
B2-TEST 4
[42,43] PG_1.5V_EN 3.62A
3
PQ9
SW@AO4468
PR56 *SW@0_6 2 2 2
[11,12,41] DGPU_VRON
3
2
1
PR55 PQ11
Co
PQ10 SW@1M/F_6 SW@DMN601K-7 PQ12 +1.5V_GPU
PR53 SW@DMN601K-7 SW@DMN601K-7
1
SW@100K_4
PC40 5.63A
*SW@2200p/50V_4
A A
PROJECT : ZR8
DDR 1.5V(TPS51116) 1A

5 4 3 2 1
1 2 3 4 5
A A
+5V_S5
B2-TEST
VIN
OCP=33A
C08
PR188 PC121
A21 +3V +3V_D_EXT A20 *SW@0_4 PU3 SW@10u/25V_1206 22.5A
SW@MAX8792ETD+T PR21
5
SW@200K/F_4 +VGPU_CORE
B2-TEST PC108 SW@1u/10V_6 8792TON
2 7
VDD TON
PR14 PR13 5 8792DH 4
l
*SW@10K_4 SW@10K_4 PC7 SW@1u/10V_6 8792VCC DH PQ44 EC1 PC20 PC119 PC120
13
VCC SW@AOL1448 SW@0.1u/50V_6 SW@2200p/50V_4 *SW@10u/25V_1206 SW@10u/25V_1206
1
2
3
6 8792BST
BST
[42] PG_GPUIO_EN 14
PGOOD PR196 PC110 PL6
tia
8792_EN 1 SW@1_6 SW@0.22u/25V_6 SW@0.36uH/25A
[11,12,40] DGPU_VRON EN 8792LX
4
PR7 LX
*SW@0_4 PR190 8792SKIP# 12
*SW@0_4 SKIP# 8792DL
3
5
DL
+3V_D_EXT
A20 8792REFIN 10
PR185 REFIN PR31
8
SW@0_4 FB SW@1_6 + + +
4 4
PR187 REF-2V
SW@100K_4 8792REF 11 9 8792ILIM
1
2
3
1
2
3
PC6 REF ILIM
SW@0.1u/10V_4
EP
PC19
SW@1000p/50V_4
Rc
15
PR193
SPE@44.2K/F_4 PC30 PC25 PC128 PC28
B PR18 PR22 SW@0.1u/50V_6 *SW@330u/2V_7343 SW@330u/2V_7343 SW@330u/2V_7343 B
SW@75K/F_4 SW@0_6 PC15 PQ40 PQ41
*SW@4700p/25V_4 SW@AOL1718 SW@AOL1718
Ra Place near GND pin15
en
PC9
PR173 SW@1000p/50V_4
3
SPE@470K/F_4
PR19
2 SW@100K_4
[17] GPU_VID1
Frequency(PR220=200K) 300K
PQ1
SW@DMN601K-7
PR175 PR195
1
SW@100K_4
Rd SPE@49.9K/F_4
PC106
SW@0.01u/16V_4
Rb
id
PR172
3
SPE@220K/F_4
2
[17] GPU_VID2
PQ2
SW@DMN601K-7
PR176
1
SW@100K_4
C C
PC107
SW@0.01u/16V_4
nf D13
VIN_SRC
PR3
+VGPU_CORE
PR5
*SW@1M_6 *SW@22_8
3
Madison -Pro Park -XT
3
GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE 2
8792_EN 2
0 0 1.05V 0 0 1.12V PQ3
PR12 *DMN601K-7
Co
PQ4 *SW@1M_6
1 0 1.0V 1 0 1.05V
1
PR16 *SW@DTC144EU
0 1 0.95V 0 1 0.95V *SW@100K_4
1 1 0.9V 1 1 0.9V
Ra Rb Rc Rd VREF Ra Rb Rc Rd VREF
470K 220K 44.2K 49.9K 2V 332K 130K 39.2K 49.9K 2V
A03
Rc --> 39.2K/F_4 (CS33922FB15)
D D
Ra --> 332K/F_4 (CS43322FB15)
Rb --> 130K/F_4 (CS41302FB00)
PROJECT : ZR8
GPU CORE(MAX8792) 1A

1 2 3 4 5
5 4 3 2 1
D D
A28
+3VPCU
1.95A
+1.8V
PC195 PC197 A28

10u/10V_8 0.1u/25V_4
PU15 HPA00835RTER A01
16 10 PH10_11_12
VIN PH
l
1 11 PL15
VIN PH 1uH_7X7X3/11A
2 12
VIN PH
PR261 *Short_4 15 13 PR262 *Short_6
[34,40,43] MAINON EN BOOT
tia
54418-1.8_VFB 6 14 PC199
VSNS PWRGD 0.1u/50V_6
PC196 COMP_PIN7 7 3
1000p/50V_4 COMP GND
8 4 R1 PR168
RT/CLK GND 100K/F_4
PAD
PAD
PAD
PAD
PAD
PAD
HWPG_1.8V [34,38]
9 5 PR260 PC194 PC191 PC192
PR264 SS AGND 0.1u/25V_4 10u/10V_8 10u/10V_8
100K/F_4
15K/F_6 PR263 +3V
22
21
20
19
18
17
182K/F_4 54418-1.8_VFB
PC201
*100p/50V_4 PC200
0.01u/25V_4
PC202
1200p/50V_4 PR169
V0=0.8*(R1+R2)/R2
R2 78.7K/F_4
C C
en
PC74 B2-TEST
+3V *0.1u/50V_6
B2-TEST HWPG_2.5V=VRON
B2-TEST PR112
B2-TEST 10K_4
PC154 PR217 +5VPCU
+5VPCU
A44 C12 +3V
id
SW@0.1u/50V_6 SW@10K_4 PR113 0_4 PC68 PU8
[34,40,43] MAINON 1u/16V_6 RT9025-25PSP
DEL PR189
PC152 PU13 4 1
VPP PGOOD HWPG_2.5V [37,43]
PR219 SW@0.1u/50V_6 SW@RT9018A
SW@100K_4 4 1 PR114 *0_4 2 6 +2.5V
VPP PGOOD PG_1.5V_EN [40,43] [34] VR2.5_ON VEN VO
[41] PG_GPUIO_EN
2
VEN VO
6 +1V 1.5A +3VPCU 3
VIN 0.2A
PR108
8
GND R1
ADJ
+1.5VSUS 3 9 5 73.2K/F_4
VIN GND NC
8
GND
ADJ
9 5 PC145 PC67
7
GND NC SW@22u/10V_1206 10u/10V_8
PR213
7
SW@9.1K/F_6
B 0.8V PR109
B
0.8V
PC71 PC70
R2 34K/F_6
PC155
SW@10u/10V_8
PC153
SW@0.1u/50V_6
Vout =0.8(1+R1/R2)
1V_ADJ
nf PR214
SW@34K/F_6 VGA
10u/10V_8 0.1u/50V_6
Vout =0.8(1+R1/R2)
=2.5V
=1V
Co
A A
PROJECT : ZR8
Discharge (2.5V/1.8V) 1A

5 4 3 2 1
5 4 3 2 1
+3V
VRON=HWPG_2.5V
CPU_VDDR (0.9V)
PC63
*0.1u/50V_6 +5VPCU PR98
PC57 PU7 100K_4
PR83 *0_4 0.1u/50V_6 RT9025-25PSP
[34,37] VRON
4 1 HWPG_0.9V [38]
VPP PGOOD
D D
PR100 0_4 2 6 CPU_VDDR
[37,42] HWPG_2.5V VEN VO
+1.5VSUS 3
VIN
8
GND 0.75A
ADJ
9 5 PR96
GND NC 4.02K/F_6
0.8V PC61
7
10u/10V_8
PC62 PC60 PR97

10u/10V_8 0.1u/50V_6 PR107 30.1K/F_6
22.1K/F_4
Vout =0.8(1+R1/R2)
l
3
=0.9V
[11] VDDR_OPT 2
tia
PQ23
DMN601K-7
VIN_SRC
PC72
1
220P/50V_4
PD4
SW1010CPT
PR228
1
1M_6
C PQ61 C
AO3409
2
en 3
3
S5_ON 2
B2-TEST
[34,36,38,44] S5_ON Thermal protection
VIN_SRC +1.8V_GPU +15V +1.8V
PQ59
1
DTC144EUA
VL VL PR229
PR82 PR76 PR79 *Short_6
3
PR180 SW@1M/F_6 SW@22_8 SW@1M/F_6
SW@0_4
[40,42] PG_1.5V_EN
2
B2-TEST
3
3
3
PR74 PQ15 C09 PR69 PR70 LM393_PIN8

SYS_SHDN# [2,4,36,44]
*SW@0_4 SW@AO3404 680/F_4 200K/F_4
1
+1.5V_GPU 2 2 +1.8V_GPU
2 PR81 PC169
0.1u/50V_6
id
SW@1M/F_6 PQ17 PQ18 PC46
0.96A
3
SW@DMN601K-7 SW@DMN601K-7 *SW@2200p/50V_4 PR230
8
PC43 200K_6
1
*SW@1U/10V_4 PR72 2.469V 3

1
PQ16 THERMISTOR_10K_6(NTC) +
1 2
SW@DMN601K-7 LM393_PIN2 2
- PQ60
PU5A DMN601K-7
VGA
4
LM393 PC170
1
0.1u/50V_6
PR71
3
200K/F_4
B B
S5_ON 2
nf PQ14
DMN601K-7
1
VIN_SRC +3V +5V +1.8V +1.5V +15V
PR106 PR105 PR103 PR104 PR102 PR101 5

+
1M_6 22_8 22_8 22_8 22_8 1M_6 7
6
-
MAINON_ON_G MAIND PU5B
MAIND [36,40] LM393
3
3
3
PR110
2 PQ22 1M_6 2 2 2 2 2
Co
[34,40,42] MAINON DTC144EUA PC66
PQ24 PQ25 PQ26 PQ27 PQ28 *2200p/50V_4
DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7
For EC control thermal protection (output 3.3V)
1
PR111
1
*100K_6
B2-TEST
A A
PROJECT : ZR8
Discharge /Thermal protection 1A

5 4 3 2 1
1 2 3 4 5 6 7 8
7
8
9
HOLE26
*H-C276D110P2-8
6
5
4
7
8
9
HOLE21
*H-CT236B315D110P2
6
5
4
7
8
9
HOLE7
*O-ZR8-10
6
5
4
7
8
9
HOLE17
*H-C276D110P2-8
6
5
4
7
8
9
HOLE1
*H-C276D110P2-8
6
5
4
8
9
HOLE27
*HG-C315D110P2
7 6
5
4
44
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
NB_CORE +VGPU_CORE +5VA +5VPCU
HOLE11 HOLE12 HOLE15 HOLE16

A
*H-C236D142PB *H-C236D142PB *H-C236D142PB *H-C236D142PB HOLE3 HOLE2 HOLE22 For EMI A
*H-C276D110P2-8 *HG-C315D110P2 *H-C91D91N EC11 EC3 EC32 EC18

7 6 7 6 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4
CPU 8 5 8 5
9 4 9 4
B2-TEST
1
1
2
3
1
2
3
1
VIN_SRC +1.8V
HOLE25 HOLE19 HOLE13 HOLE18 VIN VIN +3V_S5 +3V_S5 +3V
l
* H-C276D110P2-8 *H-C236D161PB *H-C236D161PB *H-C236D161PB
7 6
8 5 HOLE14 HOLE28 HOLE30
9 4 *hg-c355d110p2 *hg-c394d110p2 *hg-c236d110p2 EC52 EC51 EC26 EC20 EC12 EC31 EC21 EC22 EC6
7 6 7 6 7 6 0.1u/25V_4 0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
tia
8 5 8 5 8 5
1
2
3
1
9 4 9 4 9 4
1
2
3
1
2
3
1
2
3
HOLE9 HOLE10 HOLE4 HOLE5 +3V +3V
*H-C236D157P2 *H-TC197BC122D122P2
*H-C197D122PB *H-TC197BC122D122P2
+1.1V +1.5VSUS
VGA EC43 EC42

*0.1u/10V_4 *0.1u/10V_4
1
B EC8 EC23 EC14 EC7 B

*0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4
B2-TEST
en
HOLE23 HOLE8 HOLE20 HOLE6
*H-C236D161PB *H-C236D157P2 *H-C91D91N * H-C236D142P2
+5V +3VPCU
+5V +5V +5V +5V +5V +5V +5V
1
EC50 EC49 EC48 EC47 EC46 EC45 EC44 EC40 EC30 EC24 EC28 EC35 EC39 EC29
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4
HOLE29 HOLE24
*H-C157D79PT *H-C157D102PT
id
+3V
1
HOLE32 EC16 EC15 EC38 EC36 EC34 EC27 EC37 EC33

HOLE31 *H-C276D110P2-8 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4
*H-TC236BC161D161P2 7 6
C 8 5 C
9 4
nf
1
2
3
1
POWER TEST
Co
2
PD10 PR211
PD9 3 *1PS302 *22_8 +15V
+5VPCU +5VPCU *SW 1010CPT
1
PC140 PC141 PC142

PC146 PR212 1 8 *0.1u/25V_4 *0.1u/25V_4 *0.1u/25V_4
*0.1u/25V_4 *1.2K/F_4 VCC CLK
D D
2 GND -CLK 7
3 TMSNS -OT 6 SYS_SHDN# [2,4,36,43]

4 5 S5_ON_EN
TMGND EN S5_ON [34,36,38,43]
PR210 PU12
PR209 *0_4
PROJECT : ZR8
*RT9025-25PSP
*THERMISTOR_10K_6(NTC) Quanta Computer Inc.
Hole, Nuts 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
ZR8 Power tree
+5VPCU (6.15A)
<Alway ON>
AO4468 +5V_S5 (3A)

<S5_ON--->S5D> USB/B
<S5D>
AO4468 (3.15A)
<MAINON--->MAIND> +5V
D D
<MAIND>
ADAPTER Smart +3VPCU (4.72A)

Charger <Alway ON>
ISL88731A RT8206B BT
BATTERY PU1 PU0001 AO3404
<S5_ON--->S5D> +3V_S5 (1.287A)
<S5D> LAN
AO4468 +3V (3.22A)

VIN_SRC <MAINON--->MAIND>
<MAIND>
l
+3V_D (3.15A)
--<EC>-- AO3413
<dGPU_VRON>
RT9025 DNI<+1.5V_GPU>
tia
--<EC>--
DNI<VR2.5_ON> PU7005 (0.1875A)
+2.5V
<MAINON>
HPA00835RTER +1.8V (1.95A)

--<EC>-- PU7004
<MAINON>
+1.8V_GPU (0.96A)
DNI<dGPU_VRON> AO3404
C <+1.5V_GPU> C
+1.5V_GPU (2.42A)
en
<PG_1V_EN--->PG_1.5V_EN> AO3404
<PG_1.5V_EN>
--<EC>-- AO1413 +1.5VSUS (18.71A) +1.5VSUS

<VIN_ON>
G9018A +1V (1.5A)

<PG_GPUIO_EN-->PG_1V_EN>
<PG_1V_EN> PU7002
--<EC>-- RT9025 CPU_VDDR

<SUSON> (0.75A)
<VR2.5_ON-->HWPG_2.5V>
<HWPG_2.5V> PU7003
PU9 --<EC>--
DNI<VRON>
id
RT8207A
VIN
AO4468 +1.5V (7.87A)

--<EC>--
<MAINON>
B B
+0.75V_DDR_VTT (1.71A)
nf
+SMDDR_VREF (0.75V) (0.75A)
UP6111A +1.1V_S5 (5.92A)

--<EC>-- PU7000
<S5_ON>
<MAINON--->HWPG_1.8V>
DNI<HWPG_1.8V>
--<EC>-- AO4468 +1.1V (5.54A)
DNI<1.2V_ON>
<HWPG_2.5V--->HWPG_0.9V>
Co
<HWPG_0.9V>
UP6111A NB_CORE (7.5A)

<VRON-->CPU_COREPG>
<CPU_COREPG> PU6000
MAX8792 +VGPU_CORE (22.5A)

--<EC>-- PU7001
<dGPU_VRON>
A ISL62872 +VGPU_IO (4.5A)

A
<dGPU_VRON-->PG_GPUIO_EN> PU5000
<PG_GPUIO_EN>
+VCC_CORE (27A)
<VR2.5_ON-->HWPG_2.5V> ISL6265 CPU_VDDNB_CORE

<HWPG_2.5V> (3.54A)
--<EC>-- PU1001
<VRON> PROJECT : ZR8
Power Tree 1A

5 4 3 2 1
5 4 3 2 1
DDR3 (DDR)
17
M_A_DQ[63:0] [3,5]
[3,5] M_A_A[15:0] CN16A
D D
M_A_A0 98 5 M_A_DQ0
M_A_A1 A0 DQ0 M_A_DQ1
97 A1 DQ1 7
M_A_A2 96 15 M_A_DQ2
95 A3 DQ3 17
M_A_A4 92 4 M_A_DQ4
91 A5 DQ5 6
M_A_A6 90 16 M_A_DQ6
86 A7 DQ7 18
M_A_A8 89 21 M_A_DQ8
85 A9 DQ9 23
M_A_A10 107 33 M_A_DQ10
M_A_A11 A10/AP DQ10 M_A_DQ11 +1.5VSUS
84 35
l
83 A12/BC# DQ12 22
M_A_A13 119 24 M_A_DQ13
80 A14 DQ14 34 CN16B
M_A_A15 78 36 M_A_DQ15
A15 DQ15
tia
M_A_DQ16

DQ16 39 75 VDD1 VSS16 44
M_A_BANK0 109 41 M_A_DQ17 76 48
M_A_BANK1 BA0 DQ17 M_A_DQ18 VDD2 VSS17
108 BA1 DQ18 51 81 VDD3 VSS18 49
M_A_BANK2 79 53 M_A_DQ19 82 54
[3,5] M_A_BANK[0..2] BA2 DQ19 VDD4 VSS19
114 40 M_A_DQ20 87 55
[3] M_A_CS#0 S0# DQ20 VDD5 VSS20
121 42 M_A_DQ21 88 60
[3] M_A_CS#1 S1# DQ21 VDD6 VSS21
101 50 M_A_DQ22 93 61
[3] M_A_CLKP1 CK0 DQ22 VDD7 VSS22
103 52 M_A_DQ23 94 65
[3] M_A_CLKN1 CK0# DQ23 VDD8 VSS23
102 57 M_A_DQ24 99 66
[3] M_A_CLKP2 CK1 DQ24 VDD9 VSS24
104 59 M_A_DQ25 100 71
[3] M_A_CLKN2 CK1# DQ25 VDD10 VSS25
R260 *Short_4 R1_CKE0 73 67 M_A_DQ26 105 72
[3,5] M_A_CKE0 CKE0 DQ26 VDD11 VSS26
R587 *Short_4 R1_CKE1 74 69 M_A_DQ27 106 127

[3,5] M_A_CKE1 CKE1 DQ27 VDD12 VSS27
A08 115 56 M_A_DQ28 111 128
[3,5] M_A_CAS# CAS# DQ28 VDD13 VSS28
C 110 58 M_A_DQ29 112 133 C
[3,5] M_A_RAS# RAS# DQ29 VDD14 VSS29
113 68 M_A_DQ30 117 134
[3,5] M_A_WE# W E# DQ30 VDD15 VSS30
R200 10K_4 DIMM2_SA0 197 70 M_A_DQ31 118 138
R125 10K_4 DIMM2_SA1 SA0 DQ31 M_A_DQ32 VDD16 VSS31
201 129 123 139
en
SA1 DQ32 M_A_DQ33 VDD17 VSS32
202 SCL DQ33 131 124 VDD18 VSS33 144
[5,6,12,26,27] PCLK_SMB 200 141 M_A_DQ34 145
[5,6,12,26,27] PDAT_SMB SDA DQ34 M_A_DQ35 VSS34
DQ35 143 +3V 199 VDDSPD VSS35 150
116 130 M_A_DQ36 151
[3] M_A_ODT0 ODT0 DQ36 VSS36
120 132 M_A_DQ37 77 155
[3] M_A_ODT1 ODT1 DQ37 NC1 VSS37
140 M_A_DQ38 122 156
M_A_DM0 DQ38 M_A_DQ39 NC2 VSS38
11 DM0 DQ39 142 125 NCTEST VSS39 161
+1.5VSUS M_A_DM1 28 147 M_A_DQ40 162
46 149 198 167
(204P)
DM2 DQ41 [5] MEMHOT_MA# EVENT# VSS41

M_A_DM3 63 157 M_A_DQ42 30 168
DM3 DQ42 [3,5] M_A_RST# RESET# VSS42
M_A_DM4 136 159 M_A_DQ43 172
D08 M_A_DM6
153 DM5 DQ44 146
M_A_DQ45 VSS44 173
170 DM6 DQ45 148 +0.75VSMVREF_SUSA 1 VREF_DQ VSS45 178
M_A_DM7 187 158 M_A_DQ46 +VREF_CA_A 126 179
[3,5] M_A_DM[7:0] DM7 DQ46 VREF_CA VSS46
R583 R586 160 M_A_DQ47 184
*10K_4 *10K_4 M_A_DQSP0 DQ47 M_A_DQ48 VSS47
12 163 185
id
M_A_DQSP1 DQS0 DQ48 M_A_DQ49 VSS48
29 DQS1 DQ49 165 2 VSS1 VSS49 189
M_A_DQSP2 47 175 M_A_DQ50 3 190
R1_CKE0 M_A_DQSP3 DQS2 DQ50 M_A_DQ51 VSS2 VSS50
64 177 8 195
(204P)
R1_CKE1 M_A_DQSP4 DQS3 DQ51 M_A_DQ52 VSS3 VSS51
137 DQS4 DQ52 164 9 VSS4 VSS52 196
M_A_DQSP5 154 166 M_A_DQ53 13
M_A_DQSP6 DQS5 DQ53 M_A_DQ54 VSS5
171 DQS6 DQ54 174 14 VSS6
M_A_DQSP7 188 176 M_A_DQ55 19
[3,5] M_A_DQSP[7:0] DQS7 DQ55 VSS7
M_A_DQSN0 10 181 M_A_DQ56 20
M_A_DQSN1 DQS#0 DQ56 M_A_DQ57 VSS8
27 DQS#1 DQ57 183 25 VSS9
M_A_DQSN2 45 191 M_A_DQ58 26 203 +0.75V_DDR_VTT
B
M_A_DQSN3 DQS#2 DQ58 M_A_DQ59 VSS10 VTT1 B
62 DQS#3 DQ59 193 31 VSS11 VTT2 204
M_A_DQSN4 135 180 M_A_DQ60 32
DQS#4 DQ60 VSS12
[3,5] M_A_DQSN[7:0]
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
152
169
186
DQS#5
DQS#6
DQS#7
DQ61
DQ62
DQ63
nf
182
192
194
M_A_DQ61
M_A_DQ62
M_A_DQ63
37
38
43
VSS13
VSS14
VSS15
205
206
205
206
DDR3-DIMM1_H=8.0_RVS DDR3-DIMM1_H=8.0_RVS
Place these Caps near So-Dimm0. A52

2DIMM--->P/N:DGMK4000145
Co
+1.5VSUS
+VREF_CA_A +0.75VSMVREF_SUSA
C419 C687 C386 C403 C412
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C456 C381 C353 C824 C823
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C410 C395 C389 C393 C453 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4
A A
+0.75V_DDR_VTT
C9777
C9775
1U/6.3V_4
C258
1U/6.3V_4 10u/6.3V_6 PROJECT : ZR8
DDR3 DIMM-1(H=9.2) 1A

5 4 3 2 1
5 4 3 2 1
ZR8 Schematic EC Tracking Record A ( For A TEST ) Nov.17 , 2009

EC / Page / Item / Description
A01 Page25/27/28/31/32/36/38/44 Change footprint , due to SMT open issue highlight.

A02 Page32 Change T/P switch P/N, due to SMT open issue highlight.
A03 Page42 Modify Madison-Pro & Park-XT VID table.
A04 Page14 Modify board ID table and R517,R304 support Side-port function.
D A05 Page14 Add R528 support different Side-port VRAM type. D
A06 Page44 Support CPU 45W solution.

A07 Page02 Change clock gen to no stuff, due to use internal clock source.
A08 Page06/07/48 Change SO-DIMM SMBUS address.
A09 Page08/10/11 Add Side-port function.
A10 Page10 Chane HDMI DDC CLK/DATA port.
l
A11 Page10 Stuff R190.
A12 Page12 Change dGPU_PWROK from GPIO1 to GPIO32.
tia
A13 Page12 Change board ID GPIO pin.
A14 Page13 1. Stuff D19,R307,C538 and no stuff D18. 2. Change pull high power rail from +3V_D to +3V.
A15 Page16 Change R500 from 0ohm to 10k.
A16 Page12 Connect 25Mhz for GPU workaround design.
A17 Page18 Modify GPU Power-on sequence table.
A18 Page18 Remove GPU_IO VID contron pin and change GPU_CORE GPIO pin to GPIO15/20.
C A19 Page19 Change R107 from 680ohm to 51 ohm and modify design of MEM_RST#. Also change R30 to no stuff. C
A20 Page20/22/35/42 Reserve +3V_D_ZR8 power rail for GPU leakage issue.
en
A21 Page18 Reserve VGA_REQ# pin.
A22 Page25 Delete brightness switch IC control and change to 0ohm solution.
A23 Page25 Stuff R135,R144 ,due to some CRT monitor can't display.
A24 Page25 Stuff C776,C787 for EMI request.
A25 Page25/32 Change connect footprint and P/N.
A26 Page29/35 Add ODD power switch design and stuff R170.
A27 Page33 Change Q29,Q30 to no stuff.
A28 Page37/41/44 Remove jmuper.
id
A29 Page37 Change PC193 P/N to low highlimit, due to ME thermal door impact.
A30 Page38 Change PC179,PC180 from 22uF/25V to 100uF/25V.
A31 Page38 Change CPU_CORE enable from VRON to HWPG_2.5V.
A32 Page30 Change R538,R548 from 48ohm to 68ohm for audio performance.
A33 Page28 Change R572,R563 to short pad for debug use.
B B
A34 Page20 Change +VGPU_IO power rail to +VGPU_CORE.
A35
A36
Page25
Page18
Connect CN5 LCD connect shielding pin to GND for ESD issue.
Change R65 to no stuff.
nf
A37 Page22 Reserve OVERT# pull high resistor prevent noise.
A38 Page33 Add pull low 100k ohm for ODD_EJ,POWER_SAVE signal.
A39 Page36 Reserve cap for power team request.
A40 Page30 Stuff 0 ohm resistor for ESD protect use.
Co
A41 Page02/03/10/11/15/18/20/21/27/30/32/35/36 Change bead P/N for EMI request, the reason is cost down and not STD parts.
A42 Page21 Reserve 0 ohm for PLL power use.
A43 Page38 Remove PR153 & change to 0402 package
A44 Page44 Change PR113 from 0 to 10K Ohm & Change enable source to +3V
A45 Page38/39/40/41 Stuff PR80,PR89,PR94,PR95,PR47 to 1 Ohm & PC47,PC51,PC64,PC65,PC36 of value to 1000p for EMI request
A46 Page36 Change PC111 of value to 1U/25V
A47 Page36 Change PR37 of value, from 33K to 150K
A A
A48 Page36 Change PR35 of value, from 10K to 39K
A49 Page26 Change HDMI connector PN
A50 Page7 Change P/N for 3-DIMM H=4.0 STD
A51 Page6 Change P/N for 3-DIMM H=4.0 RVS
PROJECT : ZR8
A52 Page48 Change P/N for 3-DIMM H=8.0 RVS Quanta Computer Inc.
A53 Page36 Change battery connector P/N to DFHD08MR099 Size Document Number Rev
A Change List - 1 1A
A54 Page26 Modify HDMI's I2C for DIS. Date: Wednesday, May 27, 2009 Sheet 47 of 49
5 4 3 2 1
5 4 3 2 1
ZR8 Schematic EC Tracking Record A ( For A TEST ) Nov.17 , 2009

A55 Page14 Change board ID power rail from +3V_S5 to +3V.

A56 Page33/35 Modify WLAN RF_LED control design.
A57
D A58 Page12 Remove R331 only for A11 version. D
A59 Page12 Add U18,C533 & remove R303 for power sequence.
A60 Page14 Remove C760,C754,R507& Y7, due to it's for external clock use.
A61 Page2 Stuff R474,R486 for LAN & WLAN of REQ#.
A62 Page3/12 Stuff R424 and no stuff R286, due to CPU_PRPCHOT# is +1.5VSUS level.
A63 Page16 Change D29 package & Add D24.
l
Note : Change 0ohm to short pad
tia
R276,R281,R415,R443,R445,R531,R532,R533,R534,R535,R539,R566,R174,R512,R513,R263,R437,R439,R441,R99
ZR8 Schematic EC Tracking Record B1 ( For B1 TEST ) Dec.09 , 2009

C C
B01 Page21 Remove DP/TMDS Output Driver Analog Supply from port C&D. Due to it's don't to use.
en
B02 Page25 Stuff R48 for Discrete platform use.
B03 Page/10/25 Modify R signal pull low resistor value to 140ohm, due to keep 70 ohm trace impedance.
B04 Page33 Modify WLAN LED design and change from GPIO82 to GPIO84.
B05 Page27 Change LAN layout footprint for "SAW" new package.
B06 Page13/25 Reserve CCD USB host from for Port2, due to CCD issue.
B07 Page33 Reserve blue LED power source to 5V, due to White/Blue LED max Vf is more than Green/Orange LED.
id
ZR8 Schematic EC Tracking Record C ( For C TEST ) Jan.28 , 2010
C01 Page02/34 Remove "CPU_THERMTRIP#" control from SB820, due to BIOS don't support this function. Add another "SYS_SHDN#" for H/W shutdown function and add HWPG shutdown design.
B B
C02 Page04 No stuff Q21,D14,R255 for thermal sensor Alert fnction and change to EC or H/W shutdown function.
C03
C04
Page09
Page12
Add 1uF for monitor test noise issue.
nf
Add 0ohm to separate VGA_REQ function, due to it's don't support the function and cause by leakage current concern.
C05 Page24 Modify VGA note text for R signal impedance control.
C06 Page24 Add brightness switch control by iGPU switch mode. Due to BIOS for C test already support.
C07 Page29 Reserve EAPD# audio design for "Bo" sound.
C08 Page41 Change PG_GPUIO_EN pull high power rail from +3V to +3V_D_EXT. For Park GPU SG mode hang up issue.
Co
C09 Page43 Change PR69 FROM 1.2K to 680ohm , the reason is for SDA high temperature (40 degree/20% humidity) auto shutdown issue.
C10 Page27 Short LPC signal for debug card use.
C11 Page29 Change R538,R548 from 56ohm to 68ohm for audio performance test FSOV spec requirement.
C12 Page42 Change PR113 from 10k to 0ohm.
C13 Page35 Change EC54,EC55 to stuff for ISN issue.
C14 Page21 Modify DDR3 Memory Aperture size table.
C15 Page03/40 Reserve VDDR_SENSE signal to controller IC.
A A
C16 Page27 Change RP32 to no stuff.
C17 Page04 Modify CPU thermal control design from EC or BIOS control and change U16,R254 to no stuff ,Q17,Q18,Q19 to stuff.
C18 Page03 No stuff R189.
PROJECT : ZR8
Note : Change 0ohm to short pad Quanta Computer Inc.
R124,R121,R174,L31,L37,L35,R136,R115,R169,R325,R315,R295,R292,R278,R31,R90,R21,R112,R24,R25,R270,R530,R99,R478,R512,R513,R514,R326,R269,R268,R265,R266,R610,PR73,PR220,PR261 Size Document Number Rev
,PR229
5 4 3 2 1
5 4 3 2 1
ZR8 Schematic EC Tracking Record A ( For Ramp ) Feb.25 , 2010

D01 Page03 Change CPU VDDR_SENSE pull high power rail to CPU_VDDR and remove trace connect to controller IC.
D02 Page15 Modify text note.
D D03 Page12 Change "GBE_COL" ,"GBE_CRS" ,"GBE_RXERR" to GND follow SCL V1.04 version. D
D04 Page14 Change USB PLL power rail source to separate VDDPL_33_USB_S follow SCL V1.04 version.
D05 Page04 No stuff R267,C450,C344.
D06 Page09 Delete R149,R152 layout pad.
D07 Page36 No stuff PD12 and add PR181, change PR257 from 1k to 390k. The purpose is for panasonic battery low power protect issue.
D08 Page05/46 No stuff R584,R259,R583,R586 for CKE signal.
l
D09 Page32 Change LED current sense resistor value for LED light measure requirement. (Follow ZR7B)
D10 Page21 Modify VRAM table.
tia
D11 Page05/06 Change R123,R122,Q10,R202,R195,Q14 to no stuff, due to S1g4 don't support MEMHOT function.
D12 Page02 Reserve prochot# for FAN control.
D13 Page41 No stuff PR16,PQ4,PR3,PR12,PR5,PQ3. Due to MAX8792 had integrate discharge design.
D14 Page37 Change some component to no stuff, dut to for S1g4 use the same VDD power don't need to compensation difference voltage.
Note : Change 0ohm to hort pad.

C R203,117,R585,R588,R260,R587,PR1,PR2,PR33,PR241,PR147,PR146,PR160,PR256,PR133,PR233,PR152,PR155,PR128,PR142,PR143,PR144,PR145,PR130,PR131,PR115,PR120,PR77,PR226,PR222,PR202,PR262. C
en
B
id B
nf
Co
A A
PROJECT : ZR8

5 4 3 2 1

Acer Aspire 5553 Zr8 Zr8a

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Acer Aspire 5553 Zr8 Zr8a

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DDR3-SODIMM2 DDR3 channel B

SATA1 150MB SB820

USB2.0 Ports Webcam

Winbond KBC Codec USB BOARD

HPA00835RTER / RT9018A / RT9025-25PSP P42

Date: Wednesday, May 27, 2009 Sheet 1 of 49

W/S= 15 mil/20mil SB check list tide to CPUVDDIO (+1.5VSUS)

A41 *10U/6.3V_8 [11] CLK_CPU_BCLKN_PR

DG0^80000014 HT_CADINP0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUTP0

CNTR_VREF [4] +3V

CPU_LDT_REQ#_CPU 1 3 R238 1K/F_4

G1 +1.5V R237 *1K/F_4

of the Northbridge is no longer required. CPU_PWRGD_SVID_REG

+1.5VSUS R101 *10K_4

R100 *1K_4 Q12 2 CPUTEST24 R428 1K/F_4

R417 *10K_4 R8191 1K_4 CPUTEST15 R227 *300/F_4

A Q32 R8189 CPUTEST18 R230 1K/F_4 A

A62 Q31 CPU_TDO 19 20

PLACE THEM CLOSE TO +SMDDR_VREF

[6] M_B_DQSP0 C12 MB_DQS_H0 MA_DQS_H0 G13 M_A_DQSP0 [5,46]

1K/F_4 *0.47u/10V_4 R182

R193 *0_4 PROJECT : ZR8

Date: Wednesday, May 27, 2009 Sheet 3 of 49

+VCORE U29E +VCORE

F25 VSS60 VSS125 V17

BSS138_NL/SOT23 C17 H23 N6

PROCESSOR POWER AND GROUND

[34] CPU_SMBCLK CPU_SMBCLK 8 1 D05

A C17 MSOP *MMBT3904 R255 *10K/F_4 A

Date: Wednesday, May 27, 2009 Sheet 4 of 49

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

Place these Caps near So-Dimm0.

C390 C348 C260 C825 C826

10u/6.3V_6 C411 C380 C416 C402 C455 2.2u/6.3V_6 2.2u/6.3V_6

Date: Wednesday, May 27, 2009 Sheet 5 of 49

[3] M_B_A[15:0] M_B_DQ[63:0] [3] +1.5VSUS

M_B_A10 A9 DQ9 M_B_DQ10 +0.75VSMVREF_SUSB VDD10 VSS25

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

+1.5VSUS Place these Caps near So-Dimm1.

10u/6.3V_6 .1u/16V_4 2.2u/6.3V_6 .1u/16V_4 2.2u/6.3V_6

C819 C818 C822 C418 C454

A C8158 C231 C830 A

Date: Wednesday, May 27, 2009 Sheet 6 of 49

HYPER TRANSPORT CPU I/F

F2 SPM_CS# AB13 W 17 SPM_DM0

Date: Wednesday, May 27, 2009 Sheet 7 of 49

PCIE I/F GFX

AE3 AC1 PCIE_TXP0_C C658 0.1u/10V_4

AA8 AD7 A_TXP0_C C676 0.1u/10V_4 A_TXP0 [11]

RS880 Display Port Support (muxed on GFX)

GFX_TX0,TX1,TX2 and TX3

GFX_TX4,TX5,TX6 and TX7

Date: Wednesday, May 27, 2009 Sheet 8 of 49

R442 150/F_4 F19 D19

[11] CLK_NB_REF_CLKP E11 REFCLK_P/OSCIN(OSCIN)

RS880M L33 +1.8V_VDDLTP18_NB

R174 *Short_4 +1.8V_AVDDDI_NB

RS880M: Enables Side port memory

VDDLT18 - LVDS or DVI/HDMI

C268 2 Open 4 NB_LDT_STOP#

+NB_CORE_ON R436 2K/F_4

R417 10K_4 R8191 1K_4 CPUTEST15 R227 300/F_4

A C17 MSOP MMBT3904 R255 10K/F_4 A

P25 H28 5.6p/50V_4 22p/50V_4 suggestion