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DESIGN PROCEDURE OF A PUSH PULL CURRENT-FED DC-DC CONVERTER

Conference Paper · June 2010

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DESIGN PROCEDURE OF A PUSH PULL CURRENT-FED DC-DC
CONVERTER
D. Maiti, N. Mondal, S. K. Biswas (Sr. Member, IEEE)
Dept. of Electrical Engg., Jadavpur University, Kolkata 700032, India
Abstract— Some of the major drawbacks of Voltage-
fed converter can be resolved by its Current-fed
counterpart with its certain practical advantages. The
recent increase in interest and use of current-fed
converters calls for establishing a systematic design
methodology. While some papers have provided useful
insights to these converters, elaborate design steps are
not available in literature. This paper presents complete
design process of a push-pull current-fed converter.
Index Terms — Current-fed Converter, DC-DC Converter,
Push-pull Converter, Boost-derived Converter.
INTRODUCTION
Voltage-fed isolated converter topologies have
some serious drawbacks. They invariably consist
of input capacitor to lower input voltage ripple &
spikes and output low-pass filter to reduce output
voltage ripple. This low-pass filter consists of an
inductor in series with the secondary rectifier
assembly, along with the shunt capacitor. For
multi-output converter there would be inductors
for each output. With increased number of
outputs, size and cost of multiple inductors
becomes a serious concern, while the presence
of inductor at the output can make cross-
regulation poor. Voltage-fed converter requires
non-zero dead time between the turn-on of the
switch sets. During this dead time the secondary
diodes free-wheel to continue the inductor
current. This freewheeling current must be
nullified on the following turn-on. This can create
a low impedance path across the voltage source
due to diode turn-off time during this nullification
duration. The low impedance may lead to
transformer saturation. Flux imbalance is a major
problem in voltage-fed converters. It can cause
serious damage if proper preventive steps are
not taken.
Most of the problems of voltage-fed converters
can be resolved or restricted by bringing the
output inductor to the primary. This series
connected input inductor, provides an
instantaneous high impedance, thereby
restricting sudden change in current. The
inductor, as in Weinberg circuit, can be brought
in the form of a flyback transformer, feeding
either the input or the output. This flyback
1
NPEC-2010
transformer feeds its secondary when the push-
pull transformer operates in non-overlapping
mode. However, in the overlapping mode of
operation, no energy is transferred through this
transformer.
If it can be ensured that the push-pull switches
(Q1 and Q2) are operating in the overlapping
mode, an inductor can be safely connected in
series with the input as shown in Figure 1. This
topology can also be derived from boost
converter by inserting a transformer. Thus, this is
a boost-derived topology.
The very presence of series inductor at the input
reduces turn-on and turn-off current transients,
limits flux imbalance and restricts transformer
saturation by providing instantaneous high
impedance at the input. Further, there is no need
of filter capacitors at the input, making the
system compact and simple. There is no problem
arising from long lead lengths of the input supply
as this will merely add to the input inductance.
Figure 1 : Current-fed Push-Pull DC-DC
converter
OPERATION
As stated earlier, the push-pull switches (Q1 and
Q2) are operating in the overlapping mode, i.e.,
the duty cycle of each switch D, is greater than
0.5. As depicted in Figure 2, during interval [(D-
1/2)T], (with T as the time period of one switching
cycle), both Q1 and Q2 remain on. The flux in the
transformer is cancelled by the simultaneous
conduction of its two primary windings in mutually
opposite directions. The transformer thus cannot
sustain any voltage across its primary and will
 NPEC-2010

appear shorted. The total input voltage, Vin is DESIGN ASPECTS

thus impressed across the inductor. Due to this
Duty Ratio Determination
applied voltage, current through the inductor
rises in linear fashion. As there is no emf induced The voltage appearing across any switch in its off
in the transformer secondary there is no energy state, is twice the voltage across half of the
transfer to the output side during this interval. primary. So the voltage level at the primary side
Hence, from this perspective, this can be called of the transformer should not be boosted to a
as off period. Hence, very high level, which would otherwise overstress
(
t o ff = D − 1
2 )T (1) the switches. Thus, for optimum voltage boost,
the transformer center-tap voltage may be set as:
During this interval, the load is supplied by the
Vct ≃ 1.05×Vin,max (3)
energy stored in the output capacitor. Switches
Q1 and Q2 each carry half the inductor current. When both the switches are on, there is no
During next interval upto T/2, only one switch, energy transfer to secondary. Transformer
say Q2, remains on. The voltage across L primary cannot sustain any voltage across it and
reverses its polarity, to maintain the current level so it is short circuited. Current through the
constant. Inductor current decreases linearly, inductor increases linearly during this interval.
transferring energy to the transformer through the Thus,
2 L∆I
upper primary. As a result, the lower secondary V in = (4)
t off
conducts and supplies energy to the output
capacitor Co and load. From the point of view of Now, when only one switch is on i.e. for ton
energy transfer to secondary, this interval can be duration, energy is fed to transformer secondary,
called as the on period. Hence, when,
2L ∆I
t on = T − ( D − 1 )T = (1 − D )T (2) V = V +       (5)  
2 2 ct in t on
For the next toff period, both Q1 and Q2 remain Hence,
on. During the next ton interval, Q1 is turned on, V in ×t off 1
thereby repeating a process as earlier for Q2,
Vct = V in +   t on
=  V in ×
2 1− D
      (6)
transferring energy to the secondary.
The output voltage can be controlled through Transformer Turns Ratio
pulse width modulation (PWM), as in voltage fed The transformer primary voltage is known and
converters, except that the pulse width applied to secondary voltage is the rated output voltage.
a switch should lie between duty cycle above 0.5 Thus, the transformer turns ratio can be
to below 1.0, to ensure operation in the overlap expressed as :
mode. Operation below 0.5 duty cycle implies Np Vct
discontinuous mode of operation. n= Ns
= 
V0
(7)

Inductor Design
Considering an efficiency of η, the average input
current can be expressed as:
P
I i = η ×V0 (8)
d
Now, a low value of inductance may cause the
current to become discontinuous whereas a very
high value of inductance will compromise size
and weight constraints. Hence, putting a limit on
the allowable current ripple magnitude,
∆I = xI i (9)
where, 0.05 ≤ x ≤ 0.3 for optimal operation.
With output voltage Vo being constant and
V
n = Vct (which is already fixed), it implies that Vct
0
is constant.
Figure 2 : Voltage & Current waveforms for
However,
the current-fed converter

2
 NPEC-2010

V in =  V ct × 2 1‐ D   =   2t L ∆I (10) I i2
off I p ,rms = 12
3 + x 2 × 3 − 2D (21)
Rearranging (10),
This is maximum when D is minimum.
1
L ∆I   =  Vct × 2 1‐ D × D ‐ 2 T Here also, peak current magnitude, I i , pk = I i + ∆I

= 
Vct
× 3D − 1 − 2D 2 (11) The rms current through half of the secondary
2f s center-tapped winding of transformer is equal to
Vct the rms current through a diode, which is given
From (11), ∆I = , from which,
max 16Lf s by :
Vct 1
L   =   16×f (12) I s2,rms = 3 I i + ∆I 2 + I i − ∆I 2 + I i2 − ∆I 2 × 1 − D × n2
s × ∆I max
Input rms ripple current is given by : 1
= 3I i2 + ∆I 2 × 1 − D × n 2 (22)
1 3
I 2
= I i + ∆I 2
+ I i − ∆I 2
+ I i − ∆I
2 2
× 2D − 1
i ,rms 3 Again, with, ∆I = xI i ,
1
              + I i + ∆I 2
+ I i ‐ ∆I 2
+ I i2 ‐ ∆I 2 ×2 1‐D nI i
3
I s ,rms = 3+ x 2 × 1−D (23)
1 3
=  3I i + ∆I
2 2
(13)
3 Secondary peak current is given by :
With ∆I = xI i , I = I + ∆I × n (24)
s , pk i
Ii2
I i ,rms = (3 + x 2 ) (14) The voltage induced at the center tap of
3
transformer primary is given by :
Here, primary peak current magnitude, N p Φm − −Φm 2N p Ac Bm 2N p Ac Bm f s
I i , pk = I i + ∆I = I i (1 + x) (15) Vct = 1−D Ts
= 
1−D Ts
 = 
1−D
(25)
With L, Ii,rms, Ip,pk available, the inductor can be Similarly voltage induced at the secondary of
designed using standard methodologies. transformer is given by :
Maximum energy handled by the inductor, is : 2N s Ac Bm f s
Vo = (26)
E = 1 2 LI i2, pk (16) 1− D

Hence, Area Product is given by : The Primary turns is given by :

V 1− D
Ap = Aw Ac =
2E
mm 4 (17) N p = 2ctA B (27)
K w Kc JBm c mf s
Here, Aw= window area in mm2, Ac= core cross- The Secondary turns is given by :
sectional area in mm2, Kw= window utilization V 1− D
N s = 2Ao     (28)
factor, Kc= crest factor, J= current density in A/ c Bm f s
mm2, Bm= maximum flux density in Wb/ m2. To calculate Area Product required,
Number of turns is given by : Aw K w J = 2 I p ,rms N p + 2 I s ,rms N s
LIi , pk
N=   (18) = 2.I p ,rms .
Vct 1−D
+ 2.I s ,rms .
Vo 1−D
Ac Bm 2Ac B m f s 2Ac B m f s
The length of air gap to be provided (neglecting 1− D
Fringing), is given by : = V × I p ,rms +Vo × I s ,rms (29)
Ac Bm f s ct
µ0 N 2 Ac 1− D
lg = mm         (19) or, Aw Ac = V × I p ,rms +Vo × I s ,rms
L Kw JB m f s ct
Transformer Design Thus,
1− D
The rms current through half of the primary push- Ap = Kw JBm f s
V ct × I p ,rms +Vo × I s ,rms (30)
pull winding of transformer is equal to the rms Referring to cores with known Area Product data,
current through a switch, which is given by : the proper core can be selected and with known
1 I i +∆I 2 I i −∆I 2 I i2 −∆I 2 rms currents, conductors of required size can be
I p2,rms = 3 + + × 2D − 1
1
4 4 4 selected. The actual primary and secondary turns
                    +
3
I i + ∆I + I i − ∆I + I i − ∆I 2 × 1 − D
2 2 2
can be calculated from (27) and (28).
1 3−2D
=  3I i2 + ∆I 2 × (20) Output Capacitor Selection
3 4
With ∆I = xI i , Rms current at the output of the common
cathode diode pair is given by :

3
 NPEC-2010

I o2,rms = 13 I i + ∆I 2 + I i −∆I 2 + I i2 −∆I 2 ×2 1 − D × n2 V DS ,max = 2 ×Vct           (44)

2
Maximum current through switches is given by:
=  3I i2 + ∆I 2 × 1 − D × n 2 (31) I D ,max = I p , pk = I i + ∆I = I i × 1 + x     (45)
3
The Average or output DC current is given by :
I i +∆I + I i −∆I Secondary diodes
Io = 2
× 2× 1 − D × n Peak reverse voltage across diodes is given by:
= 2 1 − D nI i (32) PIV = 2Vo (46)
The rms ripple current through capacitor is: The peak current through diodes is given by:
I d2,cap = I o2, rms − I o2 I D ,max = I s , pk = I i + ∆I × n = I i 1 + x × n   (47)
For all the semiconductor components, an
= ⎡2 1 − D 2D − 1 × I i2 + 1 − D × ∆I 2 ⎤ × n 2
2
(33) appropriate Safety Factor (SF) should be used.
⎣⎢ 3 ⎦⎥
Hence, all the right hand side values in (44) to
Substituting, ∆I = xI i , the rms ripple current is (47) must be multiplied by SF.
given by :
I d ,cap =  nI i  2 1−D 2D −1  + 1x 2   (34) CONTROLLER DESIGN
3
This current causes the pre-dominant ripple in In case of voltage-fed DC-DC converter, non-
the output voltage by virtue of the voltage drop zero dead-time must be provided between turn-
across the ESR of the capacitor. Hence, the ESR on of alternate switches. This is mandatory to
of the capacitor should be less than : prevent the occurrence of dead short across a
voltage source with low impedance.
ESR = ∆V/Id,cap (35)
However, in current-fed converters, overlapping
At the instant when capacitor starts discharging, of the on duration of its switches is necessary for
energy in the capacitor is : its operation. The instantaneous high impedance
E 1 =  0.5CV d2,max    Joules (36) provided by the input inductor prevents current
overshoot during overlapped operation.
At the end of the discharge period, i.e. at
The PWM controller can be realized by using a
(
t o ff = D − 1
2 )T , energy stored in the suitable combination of standard integrated
capacitor is : circuits.
E 2 =  0.5CVd2,min    Joules (37) Transfer Function
Thus, for constant output power Po, from (36) The transfer function of the converter power
and (37) : stage can be derived by using state space
1
average technique. The transfer function can be
2 2
E − E =  0.5C V
1 2
−V
d ,max d ,min
  =  P D − T
0
(38) given as :
2
Rearranging, the Capacitance value is given by : v% s
T ps s   =   %
C =
Po 2 D − 1
(39) d s
V d2 ,m ax −V d2 ,min × f s iL L
−  s   +  1
Vo 2n 1−D Vo
Considering allowable output ripple voltage peak = ×   (48)
1−D LCo L
to peak as : s 2  +  s   +  1
4n 2 1− D 2 4 n 2 1− D 2 R
∆V p − p = y ×Vo (40)
In the above model, the ESR of the output
V
d ,max
=  V + ∆V
o p −p
(41) capacitor is neglected while R is the load
resistance.
V =  V − ∆V (42)
d ,min o p −p From (48), it can be seen that like other boost
Hence, the Capacitance value is given by : derived converter this converter also exhibit a
P 2D − 1 right half plane zero (RHPZ) in small signal
C= o (43) model. This can be attributed to the presence of
4 y ×Vo2 × f s the input inductor, which is used to store energy
Semiconductor Selection first and then feed to the secondary at a later
instant, thereby producing a delay.
Primary Switches The right half plane zero (RHPZ) is a serious
Maximum voltage across switches is given by: issue with these converters, as it limits the loop
bandwidth and can cause instability, if not dealt

4
 NPEC-2010

properly. Thus, it is very important to locate the The Ferrite core selected is EE 42/21/15 which
position of the RHPZ and design the has :
compensation network. From (48), the angular Aw= 2.56×100mm2, Ap= 4.569×104mm4, Ac=
frequency of RHPZ is : 1.82×100mm2, lm= mean magnetic length=
2n 1− D V
97.2mm
ωz = i L
o
          (49) Number of turns :
L
90.63×10−6 ×8.8
N= = 22
DESIGN EXAMPLE 1.82×100×10−6 ×0.2
With current density, J = 3A/mm2, conductor area
Design Specification
is ac = 8.01/3 = 2.67 mm2. Selected wire size is
Here a current-fed converter is designed with the SWG 14.
following specifications: Air gap length, lg = 1.22mm
Input Voltage Range, Vin = 42 to 55 V DC The actual air gap length needed will be higher
Output Voltage, Vo = 110 V DC due to Fringing effect.
Maximum output power, Po = 300 W
Transformer Design
Switching frequency, fs = 50 kHz
The maximum rms current of transformer half
Duty Ratios Determination
primary push-pull winding (for Dmin = 0.525) is :
Here, Vct ≃ 1.05×55 = 57.75 ≈ 58V 82
With V in ,min = 42V , maximum duty cycle of a I p .rms = 12
3 + 0.12 × 3 − 2 × 0.525 = 5.6 A

switch is given by : The maximum rms current of transformer half

V
secondary center-tap winding is given by :
Dmax =  1 − in ,min
2V
  =  1 − 0.362  =  0.637
I s ,rms = 0.5273×8 3 + 0.12 × 1 − 0.525 = 2.9A
ct

With V in ,min = 55V , minimum duty cycle of a switch Secondary peak current Is,pk = 8.8×0.527 = 4.64 A
is given by : Dmin = 1 − 0.474 = 0.525 Window area is calculated as :
1−0.525 4 4
Ap = 6 3
58 × 5.6 + 110 × 2.9 = 2.5 × 10 mm
Transformer turns ratio 0.4×3×10 ×0.2×50×10
N V
Core selected is EE 42/21/15 with specification
n =   Np  = 
V
ct
 = 
58
110
  =  0.527 mentioned earlier.
s o
Number of primary turns is :
Inductor Design 2×58× 1−0.525
2N p = ≈ 16
Considering 90% efficiency, maximum average 2×1.82×100×10−6 ×0.2×50×103
input current can be calculated as: Secondary turns is calculated :
2×110× 1−0.525
I i ,max = η ×V
Po
=
300
= 7.94 ≈ 8A 2N s = ≈ 30
in ,min 0.9×42 2×1.82×100×10−6 ×0.2×50×103
Allowing 20% ripple in input current (i.e. x=0.1 for Primary conductor size is given by :
20% peak to peak ripple) maximum input current α p = 5.6 3 = 1.87mm 2 . Selected wire is SWG 16.
ripple magnitude is : Secondary conductor size is given by :
( ∆I ) = 0.1 × 8 = 0.8A
max α s = 2.9 3 = 0.97mm 2 . Selected wire is SWG 18.
So, minimum inductance required is given by :
58 Output Capacitor Selection
Lmin = = 90.63µH
16×50×103×0.8 With 3% allowable ripple in DC output voltage i.e.
Input ripple current rms is calculated as : y = 0.015,  the output capacitor is calculated as :
300× 2×0.637−1
82 C= =  2.26µF
I i ,rms = 3
3 + 0.12 = 8.01A 4×0.015×1102×50×103
Primary peak current magnitude, Ii,pk = 8.8A The ripple current through the capacitor is :
Maximum energy that must be handled by the I d ,cap = 0.527 × 8 2 1 − 0.525
1
2 × 0.525 − 1 + × 0.12
inductor, E = 0.5×90.63×8.82 = 3.5 ×10-3 Joules 3
Thus, Area Product is given by : = 0.948 A
2×3.5×10−3 Thus maximum permissible ESR of capacitor is
Ap = = 2.9 × 104   mm4 0.03×110
0.4×1×3×106 ×0.2 given by: ESR =   =  3.48Ω
0.948

5
 NPEC-2010

Semiconductor Selection
Consider Safety Factor, SF = 2.
Primary Switches:
Maximum voltage across the switches is:
VDS,max = 2×58×2 = 232 V
Maximum current though the switches is:
ID,max = 8.8×2 = 17.6A
Secondary diodes:
Peak reverse voltage across diodes is given by:
PIV = 2×110×2 = 440V
The peak current through diodes is given by:
ID,max = 8.8×0.527×2 = 9.27 A

MATLAB SIMULATION
Based on the designed values, MATLAB
simulation was carried out for the converter
system. The waveforms matched the
theoretically predicted curve shapes, except for
the starting transients.
In the simulation model the switches were
considered ideal, and transformer was Figure 4 : MATLAB simulation result for (a)
considered to have zero leakage inductance and output voltage, (b) current of diode D1 and (c)
zero winding resistance. output current at the common cathode of the
The source voltage was varied randomly diodes
between the limits specified in the design.
The simulation results are shown in Figure 3 & 4. LEAKAGE ENERGY RECOVERY BY CLAMP
One of the drawbacks of current fed topology is
the generation of high voltage spikes across the
switches due to the energy stored in transformer
leakage inductance. Usually snubber/clamp
circuits are used to protect the switches, thereby
dissipating the stored energy. Alternatively, an
energy recovery clamp can be used to recover
this stored energy as depicted in Figure 5. This
clamp should start to feed the energy back to the
source when the voltage across the switches
crosses a predetermined threshold.

Figure 5 : Use of an energy recovery clamp to

Figure 3 : MATLAB simulation waveforms for
(a) inductor current and (b) & (c) switch
currents or transformer primary winding
currents
6
recover trapped energy in leakage inductance
back to the source
EXPERIMENTAL RESULTS
An experimental prototype was fabricated in the
laboratory using the above design and tested for

its performance. The set-up is shown in Figure 6.
The control circuit is assembled onto a PCB. The
power semiconductors are mounted on the
heatsink with wire connections upto PCB and
transformer. The transformer is visible in the
middle and the inductor on the right hand side.
Figure 6 : Experimental prototype for
laboratory testing
CONCLUSION
A detailed step-by-step design process of a
push-pull current-fed DC-DC converter is
presented in this paper. The theoretical design is
supported by simulation and experimental
verification. As further work, the design process
can be extended to current-fed full bridge
topology.
View publication stats
NPEC-2010
REFERENCES
[1] R. Redl and N. O. Sokal, “Push-Pull Current-Fed
Multiple-Output DC/DC Power Converter with Only
One Inductor and with 0 to 100% Switch Duty Ratio”,
IEEE 1980.
[2] R. Redl, N. O. Sokal, “Push-Pull Current-Fed
Multiple-Output Regulated Wide-Input-Range DC/DC
Power Converter With Only One Inductor and With 0
to 100% Switch Duty Ratio: Operation at Duty Ratio
Below 50%”, IEEE 1981.
[3] V. J. Thottuvelil, T. G. Wilson, H. A. Owen Jr.,
“Analysis and Design of a Push-Pull Current-fed
Converter”, IEEE 1981.
[4] L. A. Flores, A. Soto, P. Alou, O. Garcia and J. A.
Cobos , “Current Fed Push-Pull Topology with Self
Driven Synchronous Rectification Applied to Low
Voltage”, IEEE- 2004
[5] A. I. Pressman, Switching Power Supply Design,
2nd ed., New York: McGraw-Hill, 1999.
[6] N. Mohan, T. M. Undeland, W. P. Robbins, Power
Electronics Converters, Applications, and Design 2nd
edition, John Willey and sons.
[7] R. W. Erickson, D. Maksimovic, Fundamentals of
Power electronics, 2nd edition, Kluwer A.P.
[8] L. Umanand, S. R. Bhat, Design of Magnetic
Components for Switched Mode Power Converters,
1992, Wiley Eastern Ltd.