1.      Explain the features of 8085

Ans.
8085 is an 8 bit microprocessor who performs arithmetic and logical operations, manufactured
with n-type Metal Oxide Semiconductor technology implemented with 6200 transistors. It is a 16 bit
program counters and a 16 bit stack pointer.

This type of microprocessor has 16-bit address lines - A0-A15 (to point the memory locations)
and hence can point up to 2^16 = 65535 bytes (64KB) memory locations. It requires a signal +5V power
supply and operates at 3.2 MHZ single phase clock with maximum clock frequency 6 MHz and minimum
clock frequency 500 kHz. 8085 microprocessor provides 74 instructions and status for advanced control
signals, On chip clock generator.

2.      Give the clock frequency and state time T, of an 8085A operating with each of the following
frequency crystals: 6.25 MHz, 6.144 MHz and 4 Mhz.
3.      List the internal registers in 8085A, their abbreviations and lengths. Describe the primary
function of each register.

Ans:
a. General Purpose Registers –

These general purpose registers are used to hold data like any other registers. The general
purpose registers in 8085 processors are B, C, D, E, H, and L. Each register can hold 8-bit data.
Apart from the above function these registers can also be used to work as register pairs – BC,
DE, and HL, to hold 16-bit data.

b. Specific Purpose Registers –

 Accumulator:
The accumulator is an 8-bit register (can store 8-bit data) that is the part of the
arithmetic and logical unit (ALU). After performing arithmetical or logical
operations, the result is stored in accumulator. Accumulator is also defined as
register A.

 Flag registers-
It is an 8 bit register and consists of individual flipflops. The content of
the flag register gives the status of the current result processed by ALU. It
consists of various flags which listed below. Flags are nothing but a group of
individual Flip-flops. The flags are mainly associated with arithmetic and logic
operations.

S- Sign flag –
The sign flag occupies the seventh bit of the flag register, which is
also known as the most significant bit. It helps the programmer to know
whether the number stored in the accumulator is positive or negative. If the
sign flag is set, it means that number stored in the accumulator is negative,
and if reset, then the number is positive.

Z- Zero Flag –
The zero flag occupies the sixth bit of the flag register. It is set, when
the operation performed in the ALU results in zero (all 8 bits are zero),
otherwise it is reset. It helps in determining if two numbers are equal or not. 

AC- Auxillary Carry Flag –

The auxillary carry flag occupies the fourth bit of the flag register. In
an arithmetic operation, when a carry flag is generated by the third bit and
 passed on to the fourth bit, then Auxiliary Carry flag is set. If not, flag is
reset. This flag is used internally for BCD (Binary-Coded decimal Number)
operations.

P- Parity Flag –
The parity flag occupies the second bit of the flag register. This flag
tests for number of 1’s in the accumulator. If the accumulator holds even
number of 1’s, then this flag is set and it is said to even parity. On the other
hand, if the number of 1’s is odd, then it is reset and it is said to be odd
parity.

CY- Carry Flag –

The carry flag occupies the zeroth bit of the flag register. If the
arithmetic operation results in a carry (if result is more than 8 bit), then Carry
Flag is set; otherwise, it is reset.

c. Memory Registers –
There are two 16-bit registers used to hold memory addresses. The size of these registers
is 16 bits because the memory addresses are 16 bits. They are :

 Program Counter:  used to sequence the execution of the instructions. It

stores the address of the next instruction to be executed. This register keeps
track of the memory address of the instructions that are being executed by the
microprocessor.
 Stack Pointer: It is used as a memory pointer. It points to a memory location
in read/write memory, called the stack. It is always incremented/decremented
by 2 during push and pop operation.

4.      Give the format of flag register in 8085. Explain each flag.

Ans:

o Sign Flag (7th bit): It is reset(0), which means number stored in the
accumulator is positive.
o Zero Flag (6th bit): It is reset(0), thus result of the operations performed in the
ALU is non-zero.
 o Auxiliary Carry Flag (4th bit): We can see that b3 generates a carry which is
taken by b4, thus auxiliary carry flag gets set (1).
o Parity Flag (2nd bit): It is reset(0), it means that parity is odd. The accumulator
holds odd number of 1’s.
o Carry Flag (0th bit): It is set(1), output results in more than 8 bit.

5.      Draw the functional block diagram of microprocessor 8085 and explain in brief.

8085 Bus Structure:

Address Bus:
 The address bus is a group of 16 lines generally identified as A0 to A15.
 The address bus is unidirectional: bits flow in one direction-from the MPU
to peripheral devices.
 The MPU uses the address bus to perform the first function: identifying a
peripheral or a memory location.

Data Bus:
 A data bus is a group of eight lines used for data flow.
 These lines are bi-directional – data flow in both directions between the
MPU and memory and peripheral devices.
 The MPU uses the data bus to perform the second function: transferring
binary information.
  The eight data lines enable the MPU to manipulate 8-bit data ranging from
00 to FF (28 = 256 numbers).
 The largest number that can appear on the data bus is 11111111.
 
Control Bus:
 The control bus carries synchronization signals and providing timing
signals.
 The MPU generates specific control signals for every operation it
performs. These signals are used to identify a device type with which the
MPU wants to communicate.
 
Registers of 8085:
 
 The 8085 have six general-purpose registers to store 8-bit data during program
execution.
 These registers are identified as B, C, D, E, H, and L.
 They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.
 
Accumulator (A):
 The accumulator is an 8-bit register that is part of the arithmetic/logic unit
(ALU).
 This register is used to store 8-bit data and to perform arithmetic and
logical operations.
 The result of an operation is stored in the accumulator.
 
Flags:
 The ALU includes five flip-flops that are set or reset according to the result of an
operation.
 The microprocessor uses the flags for testing the data conditions.
 They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC)
flags. The most commonly used flags are Sign, Zero, and Carry.
 
Temporary Register: It is used to hold the data during the arithmetic and logical operations.
 
Instruction Register:  When an instruction is fetched from the memory, it is loaded in the
instruction register.
 
Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.
 
Serial I/O Control:  It has two control signals named SID and SOD for serial data transmission.

Interrupt Control Unit: It receives hardware interrupt signals and sends an acknowledgment for
receiving the interrupt signal.
Arithmetic and Logic Unit (ALU):
 It is used to perform the arithmetic operations like addition, subtraction,
multiplication, division, increment and decrement and logical operations like
AND, OR and EX-OR.
 It receives the data from accumulator and registers.
 According to the result, it set or reset the flags.
 
Program Counter (PC):
 This 16-bit register sequencing the execution of instructions.
 It is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a 16-bit register.
 The function of the program counter is to point to the memory address of the next
instruction to be executed.
 When an opcode is being fetched, the program counter is incremented by one to
point to the next memory location.
Stack Pointer (Sp):
 The stack pointer is also a 16-bit register used as a memory pointer.
 It points to a memory location in R/W memory, called the stack.
 The beginning of the stack is defined by loading a 16-bit address in the stack
pointer (register).

6.      Explain different control signals used by 8085.

Answer:
 RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
 WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
 ALE − is a positive going signal generated every time during the beginning of the
Operation. This indicates that the bits present in the lower order address lines are
address bit. The latch is open and the bits are sent to the address bus. When the ALE
signal undergoes a transition from high to low, the latch is closed and the bits on the
lower order address bus are data bits.

7.      Why AD – AD lines are multiplexed?

0 7

Ans:
The major reason of multiplexing address and data bus is to reduce the number of pins for
address and data and dedicate those pins for other several functions of microprocessor. In other
words, for 8085, if we don't multiplex the 8 lines of data (D0-D7) with lower byte of address(A0-
A7), then we would need to provide total of 24 pins for memory accesses alone out of 40 in total.
8.      What is the use of ALE signal?

Answer:
ALE stands for Address Latch Enable. It is the 30th pin of 8085 which is used to enable
or disable the address bus. The address bus will be enabled during the 1st clock cycle as the ALE
pin goes high (logic '1') during the first half cycle. During 2nd and 3rd clock cycles it goes low
(logic '0') indicating the address & data bus (AD0-AD7) is for data. Hence it disables the address
& data bus during the 2nd and 3rd clock cycles.

9.      What is the use of CLKOUT and RESET OUT signals of 8085 microprocessor?

Ans:
CLKOUT − This signal is used as the system clock for devices connected with the
microprocessor.
RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.

10.  Describe the functions of following pins in 8085.

Ans:
a.      READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
b.      ALE - It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.
c.    IO/M - This signal is used to differentiate between IO and Memory operations, i.e.
when it is high indicates IO operation and when it is low then it indicates memory
operation.
d.      HOLD - This signal indicates that another master is requesting the use of the
address and data buses.
e. RESET IN – When the signal on this pin is low(0), the program-counter is set to
zero, the buses are tristate and the microprocessor unit is reset.
RESET OUT – This signal indicates that the MPU is being reset. The signal can be
used to reset other devices.

11.  Explain the signals used in DMA operation in 8085.

Ans:
HOLD – It indicates that another device is requesting the use of the address and data
bus. Having received HOLD request the microprocessor relinquishes the use of the
buses as soon as the current machine cycle is completed. Internal processing may
continue. After the removal of the HOLD signal the processor regains the bus.
 HLDA – It is a signal which indicates that the hold request has been received after the
removal of a HOLD request, the HLDA goes low.

12.  Draw and explain typical 8085 configuration.

Ans:

Address Bus (A8-A15)

The address bus pins are ranges from A8 to A15 and these are mainly applicable to the
most considerable memory address bit.

Address Bus (or) Data Bus (AD0-AD7)

The address bus pins or data bus pins are ranges from AD0 to AD7, and these pins are
applicable for LSB (least significant bits) of the address bus in the primary apparatus
CLK cycle as well as employed as a data bus for second clock cycle & third clock cycle.

Address Latch Enable (ALE)

Basically, ALE assists in de-multiplexing the data bus as well as low order address. This
will go high throughout the primary clock cycle as well as allows the address bits with
low order. The address bus with low order is added for memory otherwise any exterior
latch.

Status Signal (IO/M)

The status signal IO/M resolves whether the address is intended for memory or
input/output. When the address is high then the address of the address bus is used for the
devices of input/output devices. When the address is low then the address of the address
bus is used for the memory.

Status Signals (S0-S1)

The status signals S0, S1 gives different functions as well as status based on their status.
 When the S0, S1 are 01 then the operation will be HALT.
 the S0, S1 is 10 then the operation will be WRITE
 When the S0, S1 is 10 then the operation will be READ
 When the S0, S1 are 11 then the operation will be FETCH

Active Low Signal (RD)
The RD is an energetic low signal and an operation is executed whenever the indication
goes small, and it is used for controlling the microprocessor READ operation. When RD
pin goes small then the 8085 microprocessor understands the information from I/O device
or memory.

Active Low Signal (WR)

This is an energetic low signal, and it controls the microprocessor’s write operations.
Whenever WR pin goes small, then the information will be written to the I/O device or
memory.

READY
The READY pin is employed with the 8085 microprocessor for ensuring whether a
device is set for accepting or transferring data. A device may be an A/D converter or
LCD display, etc. These devices are associated with the 8085 microprocessor with the
READY-pin. When this pin is high, the device is prepared for transferring the
information, if it is not then the microprocessor stays until this pin goes high.

HOLD
The HOLD pin specifies when any device is demanding the employ of address as well as
a data bus. The two devices are LCD as well as A/D converter.

HLDA
This is the response signal of HOLD, and it specifies whether this signal is obtained or
not obtained. After the implementation of HOLD demand, this signal will go low.

INTR
This is an interrupt signal, and the priority of this among the interrupts is low. This signal
can be allowed or not allowed by the software. When INTR pin goes high then the 8085
microprocessor completes the instruction of current which is being executed and then
recognizes the INTR signal and progresses it.

INTA
When the 8085 microprocessor gets an interrupt signal, then it should be recognized. This
will be done by INTA. As a result, when the interrupt will be obtained then INTA will go
high.

RST 5.5, RST 6.5, RST 7.5

These pins are the restart maskable interrupts or Vectored Interrupts, used to insert an
inner restart function repeatedly. All these interrupts are maskable, they can be allowed
or not allowed by using programs.

TRAP
Along with the 8085 microprocessor interrupts, TRAP is a non-maskable interrupt, and it
doesn’t allow or stopped by a program. TRAP has the maximum precedence between the
interrupts. The priority order from maximum to low includes TRAP, RST 5.5, RST 6.5,
RST 7.5, and INTR.

RESET IN
RESET IN pin is used to reset the program counter toward zero and rearranges interrupt
enable as well as HLDA flip-flops (FFs). The central processing unit is detained in RST
condition till this pin is high. But the registers as well as flags won’t get damaged apart
from instruction register.

RST (RESET) OUT

RESET OUT pin specifies that the central processing unit has been rearranged with RST
IN.

X1 X2
X1, X2 terminals that are associated with the exterior oscillator for generating the
required as well as appropriate operation of a clock.

CLK
Sometimes it is compulsory to generate CLK o/PS from 8085 microprocessors so they
can be used in favor of other peripherals or else other digital integrated circuits. This is
offered with CLK pin. Its frequency is continually similar because the frequency at which
the microprocessor works.

SID
This is a serial i/p data, and the information on this pin is uploaded into the 7th-bit of the
accumulator while RIM (Read Interrupt Mask) instruction is performed. RIM verifies the
interrupt whether it is covered or not covered.
 SOD
This is the serial o/p data, and the data on this pin sends its output toward the 7th-bit of
the accumulator whenever an instruction of SIM is performed.

VSS and VCC

VSS is a ground pin whereas Vcc is +5v pin.

13.  Define
a.      Instruction Cycle:
The time period during which one instruction is fetched from memory and
executed when a computer is given an instruction in machine language. There are
typically four stages of an instruction cycle that the CPU carries out:
1. Fetch the instruction from memory. This step brings the instruction into
the instruction register, a circuit that holds the instruction so that it can be
decoded and executed.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect
address.
4. Execute the instruction.
b.      Machine Cycle:
The processor cycle or machine cycle is the basic operation performed by the
processor. To execute an instruction, the processor will run one or more machine cycles
in a particular order.
c.       T-State:
For any instruction cycle, Opcode fetch is the first machine cycle. We know that
each machine cycle may have 3 to 6 T-states. This Opcode fetch machine cycle consists
of 4 T-states.
T1 State: During the T1 state, the contents of the program counter are placed on the 16 bit
address bus.
T2 State: Opcode is placed on D0-D7 of the Address/Data bus.
T3 State: The Opcode of the A/D bus is transferred to the instruction register of the
microprocessor.
T4 State: In this state the Opcode which was fetched from the memory is decoded.

14.  What is the necessity to have two status line S and S in 8085?
1 0

Ans:
Status signals (S0 and S1): These are output status signals used to give information of
operation performed by microprocessor. The S0 and S1 lines specify 4 different conditions of
8085 machine cycle: opcode, read, write, and halt.
15.  Show the representation of single signal.

Ans:

16.  Show the representation of group of signals

Ans:

17.  In which T – cycle the ALE signal is activated?

Ans:
ALE signal is active high signal. It is activated in the beginning of the T 1 state of
each machine cycle, except bus idle machine cycle, and it remains active in the T 1 state .
18.  Explained how the multiplexed data/address bus is shared for data and address.

Ans:
The main reason of multiplexing address and data bus is to reduce the number of pins for
address and data and dedicate those pins for other several functions of microprocessor. These
multiplexed set of lines used to carry the lower order 8-bit address as well as data bus.

How It Reduces Number of Pins:

 (MUX 2:1)-That is 2Inputs 1 Output
 Multiplexer Combines Many Signals to One Signal
 So Here 1st Input is Address A0-A7 and second input is Data D0-D7
 And with help of selector Line (ALE Pin) I can use one at a time
 For Example, ALE =0 Data is Selected
 ALE =1 Address is Selected
 Hence with help of multiplexing we reduce from 16 pins to 8pins

19.  Draw and explain the timing diagram of opcode fetch machine cycle.

Ans:

 The MP places the 16-bit memory address from the program counter on address bus. At
time period T1, the higher order memory address is placed on the address lines A15 – A8.
When ALE is high, the lower address is placed on the bus AD7 – AD0. The status signal
 IO/M(bar) goes low indicating the memory operation and two status signals S1 = 1, S0 =
1 to indicate op-code fetch operation.
 At time period T2, the MP sends RD (bar) control line to enable the memory read. When
memory is enabled with RD (bar) signal, the op-code value from the addressed memory
location is placed on the data bus with ALE low.
 The op-code value is reached at processor register during T3 time period. When data (op-
code value) is arrived, the RD (bar) signal goes high. It causes the bus to go into high
impedance state.
 The op-code byte is placed in instruction decoder of MP and the op-code is decoded and
executed. This happens during time period T4.

20.  Draw and explain the timing diagram of memory read machine cycle.

Ans:

 The MP places the 16-bit memory address from the program counter on address bus. At
time period T1, the higher order memory address is placed on the address lines A15 – A8.
When ALE is high, the lower address is placed on the bus AD7 – AD0. The status signal
IO/M(bar) goes low indicating the memory operation and two status signals S1 = 1, S0 =
0 to indicate memory read operation. 
 At time period T2, the MP sends RD (bar) control line to enable the memory read. When
memory is enabled with RD (bar) signal, the data from the addressed memory location is
placed on the data bus with ALE low. 
  The data is reached at processor register during T3 state. When data is arrived, the RD
(bar) signal goes high. It causes the bus to go into high impedance state.

21.  Draw and explain the timing diagram of memory write machine cycle.

Ans:

 The MP places the 16-bit memory address from the program counter on address bus. At
time period T1, the higher order memory address is placed on the address lines A15 – A8.
When ALE is high, the lower address is placed on the bus AD7 – AD0. The status signal
IO/M(bar) goes low indicating the memory operation and two status signals S1 = 0, S0 =
1 to indicate memory write operation.
 At time period T2, the MP sends WR(bar) control line to enable the memory write. When
memory is enabled with WR(bar) signal, the data from the processor is placed on the
addressed location with ALE low.
 The data is reached at memory location during T3 state. When data is reached, the
WR(bar) signal goes high. It causes the bus to go into high impedance state.
22.  Draw and explain the timing diagram for I/O read and I/O write machine cycles.

Ans:

I/O Read Machine Cycle:

 It is used to fetch one byte from an IO port.
 It requires 3 T-States.
 During T1, The Lower Byte of IO address is duplicated into higher order address bus A8-
A15.
 ALE is high and AD0-AD7 contains address of IO device.
 IO/M (bar) goes high as it is an IO operation.
 During T2, ALE goes low, RD (bar) goes low and data appears on AD0-AD7 as input
from IO device.
 During T3 Data remains on AD0-AD7 till RD (bar) is low.
I/O write machine cycle:
 It is used to writ one byte into IO device.
 It requires 3 T-States.
 During T1, the lower byte of address is duplicated into higher order address bus A8-A15.
 ALE is high and A0-A7 address is selected from AD0-AD7.
 As it is an IO operation IO/M (bar) goes low.
 During T2, ALE goes low, WR (bar) goes low and data appears on AD0-AD7 to write
data into IO device.
 During T3, Data remains on AD0-AD7 till WR(bar) is low.

23.  Explain the interrupt acknowledge cycle for RST instruction.

Ans:
The figure above shows the timing diagram of the interrupt acknowledge machine cycle and
execution of RST instruction. The interrupt acknowledge cycle is similar to the opcode fetch
cycle, with two exceptions.

1. The INTA signal is activated instead of the RD signal.

2. The status lines (IO/M, S0 and S1) are 111 instead of 011:
During interrupt acknowledge machine cycle (M1), the RST is decoded, which initiates 1 byte
CALL instruction to the specific vector location. The machine cycles M2 and M3 are memory
write cycles that store the contents of the program counter on the stack, and then a new
instruction cycle begins.

24.  Explain the interrupt acknowledge cycle for CALL instruction.

Ans:
 The figure shows the timing diagram of the Interrupt Acknowledge Cycle of 8085 and
execution of a CALL instruction. For CALL instruction, it is necessary to fetch the two bytes of
the CALL address through two additional interrupts acknowledge machine cycles (M2 and M3 in
the 1.21). The machine cycles M4 and M5 are memory write cycles that store the contents of the
program counter on the stack, and then a new instruction cycle begins.