PKG, SCH, WORKSTATION, 9900 document information

Document Information for 00-887907-03 Rev 1
Part Number 00-887907-03

Revision 1
Description PKG, SCH, WORKSTATION, 9900
Contents:
Drawing Rev Description
00-879054DDW E2 SCH, PCB, SYSTEM INTERFACE
00-885794DDW 6 SCH, PCB, VORTEX IMAGE PROCESSOR
00-885899DDW 26 INTERCONNECT DIAGRAM, WKSTN, 9900
00-887453DDW A1 SCH, PCB, ISOLATED INTERFACE
00-888918-01SCH 3 PCB, SCHEMATIC, VIDEO CONTROL
5262582SCH 1 PC BOARD SCH, GPOS MULTI BRACKET, RoHS
5265289SCH 1 PC BOARD SCH, VORTEX DISPLAY ADAPTER, RoHS
5304538SCH 1 PC BOARD SCH, X-RAY LED LAMP, RoHS
5309879SCH 1 PC BOARD SCH, CINE BRIDGE 2ND GEN, RoHS
5316910SCH 1 SCH, PCB, ISD-PC2
5340094SCH 4 PC BOARD SCH, SURGE SUPPRESSOR, RoHS
5340097SCH 1 PC BOARD SCH, IR RECEIVER, RoHS
Document Information for: 00-879054DDW
Type Drawing Print

Name 00-879054DDW
Revision E2
State Release
Description SCH, PCB, SYSTEM INTERFACE

Originator Information not available
File List
00-879054DDW_rE2.pdf
State: RELEASE - Document is released and under formal Change Control. Changes are subject to the ECR/ECO Process.
Approval Information
Person Action Date and Time
Information not available Approved Information not available
See the GEHC ePDM System to determine the status of this document.
This page is generated automatically by the GEMS ePDM System

Printed documents are for Reference Only and may be out-of-date.
Check the database to ensure you have the correct revision.
Approved Document - 00-879054DDW_rE2.pdf Page 1 of 12

Numbered references on this document MAY have been updated to include the suffix "-OEC" and or
"-NAV". Please refer to ESOP 6.2.1 PART NUMBERING CONVENTIONS for proper procedure.
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
1
REV
6 1
REVISION HISTORY
REV EFFECTIVE DATE CHANGE NUMBER DESCRIPTION OF CHANGE ORIGINATOR OR AUTHOR
A 12-16-04 FC16 CHANGED PER ECO FC16 S. BROWN
6 10-22-08 DCN07164 CHANGED PER DCN G. POPE
V3.3
V3.3
D L1
1UH C217 C218
D
1 2 0.01 0.01
C216 C214 C215

2.2 0.01 0.1
D
U1
49FCT3805
D FPDP_CLK_BUF_OE* 12 OEB
IN
CINE_CLK_BUF_OE* 9 OEA
IN
V3.3
4
V3.3 13 OSC_40M
MON OUT
1
EN CLK 3 40M 11 INB OB4 14 FPSTROB
OUT
OB3 15
R205 17
OB2
10K Y1 18
OB1
40MHZ 19
OB0
10 INA OA4 7 CINE_PIXCLK_B
OUT
OA3 6
OA2 4
OA1 3 R262
OA0 2 75
C C135
220P
C
CLOCKS
V3.3 L3
1UH
1 2 V3.3
C474 C475 C145

U17
2.2 0.1 0.01
49FCT3805 C146 C473 C472
R115 12 OEB 2.2 0.01 0.01
10K 66M_OE* 9 OEA
D 13
MON
D 11 INB OB4 14
D
B OB3
OB2
15
17 00-885795-01 PCB, IP VORTEX A/F
B
V3.3 Y2 66MHZ OB1 18
4 OB0 19 00-885794-01 SCH, PCB, IP VORTEX
V3.3
1
EN CLK 3 66M 10 INA OA4 7 CLK_CONF_66M
OUT
OA3 6 OSC_66M_PLX ASM_U14
OUT
R311 4 OSC_66M_AP
OA2 OUT 00-886109-01 ASM, FW, CPLD, VORTEX-IP
10K 3 OSC_66M_GP
OA1 OUT
OA0 2 ASM_U15
00-886113-01 ASM, FW, PLX, VORTEX-IP
PACK_TYPE=QSOP
00-885796-60 SPEC, PERF, VORTEX IMAGE PROCESSOR

R204 R208
R284 R289
75 75
75 75
00-886513-01 RETAINER, LOWER, I/P, & D/A, PCI
C20 C15 C119 C115

00-901420-01 BRKT, PCI, RECT CUTOUT
220P 220P 220P 220P
12-225104-05 SCR,SEMS SPR,PAN,TRX,4-40,5/16,SZC

4
66-899854-00 HT SK,BGA,35MM X 35MM,AL
2
D
DRAWING NO. PART NO. CORRELATION MATRIX
DRAWING NO. PART NO. PART REV. -01 SHOWN
A 00-885794DDW 00-885794-01 A A
FORMAT PER PR12001
THIS DOCUMENT AND THE INFORMATION

CONTAINED HEREIN IS CONFIDENTIAL AND
PROPERTY OF OEC MEDICAL SYSTEMS, INC.,
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN INCHES
TOLERANCES ARE:
ORIGINAL DRAWN BY: DATE:
GE HEALTHCARE - SURGERY
A UNIT OF GE HEALTHCARE AND WHOLLY- F. FARRINGTON 10-29-03
OWNED SUBSIDIARY OF GENERAL ELECTRIC. FRACTIONS: +/- DWG TITLE
IT IS DISCLOSED TO YOU FOR THE
DATE:
SCH, PCB, VORTEX IP
SOLE PURPOSE OF YOUR PERFORMANCE DECIMALS: X +/- ORIGINAL RESPONSIBLE ENGINEER:
UNDER THE CONTRACT WITH OEC MEDICAL
SYSTEMS. IT IS NOT TO BE COPIED OR .X +/-
IN ANY WAY DISCLOSED TO THIRD PARTIES. S. BROWN 10-30-03
IT SHALL BE RETURNED TO OEC MEDICAL .XX +/-
SYSTEMS UPON DEMAND. YOU HEREBY
AGREE TO THESE RESTRICTIONS AND .XXX +/- SIZE DWG NO. REV
INDEMNIFY OEC MEDICAL SYSTEMS FOR
ALL LOSS OR DAMAGE ARISING FROM
BREACH OF THIS OBLIGATION BY YOU
ANGLES: +/- G. POPE 10-31-03
B 00-885794DDW 6
OR ENTITIES OR AGENTS UNDER YOUR DO NOT SCALE DRAWING SCALE:
CONTROL. NONE SHEET 1 OF 23
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
2
REV
6
1
P9 A1 TRST* (NC)
P9 B2 TCK (NC) U16
P9 A3 TMS (NC)
TDI PCI9656_JMODE PCI9656_JMODE
P9 A4 AD<63..0> LB_LAD<31..0>
TDO SPEED=66_MHZ BI
P9 B4
SECTION 1 OF 2 SECTION 2 OF 2
P9 B68 63 63 T4 AD63 GNT1 N3 NC 31 N18 LAD31 LB_DACK<1..0>*
P9 A40 SDONE (NC) OUT
P9 A68 62 62 U3 AD62 GNT2 R1 NC 30 N19 LAD30 DACK0 A13 0
P9 A41 SBO* (NC)
P9 B69 61 61 W1 AD61 GNT3 R2 NC 29 N20 LAD29 DACK1 C13 1 LB_DREQ<1..0>*
P9 B49 M66EN* IN
P9 A70 60 60 V3 AD60 GNT4 P4 NC 28 M17 LAD28 DREQ0 B13 0
P9 B9 PRSNT1* P9 B71 59 59 Y2 AD59 GNT5 U11 NC 27 M18 LAD27 DREQ1 A14 1
D C536
P9 A71 58 58 W4
V4
AD58 GNT6 W12 NC V3.3 26 M19
M20
LAD26 DMPAF/EOT D14 LB_DMPAF_EOT*
LB_DP<3..0>
BI D
C541 P9 B72 57 57 AD57 25 LAD25 BI
0.01 0.01 P9 A73 56 56 U5 AD56 24 L19 LAD24 DP3 D18 3 V3.3
P9 B74 55 55 Y3 AD55 REQ1 P1 23 L18 LAD23 DP2 B20 2
V3.3
6
5
7
P9 B11 PRSNT2*
P9 A74 54 54 Y4 AD54 REQ2 P2 D 22 L20 LAD22 DP1 C18 1 R112
C551 P9 B75 53 53 V5 AD53 REQ3 T1 21 K20 LAD21 DP0 B19 0 10K
W5 R3
R300 K19
2.2 D P9 A76 52 52 AD52 REQ4 20 LAD20 R113
Y5 Y12
10K K18 D12 LB_CCS*
P9 B77 51 51 AD51 REQ5 19 LAD19 CCS IN 10K
-12V (NC) P9 A77 V6 REQ6 V12 PLX_REQ K17 LAD18
4
AD50
3
1
50 50 18
P9 B1 E1 REF U7 J20 D20 OSC_66M_PLX
P9 B78 49 49 AD49 17 LAD17 LCLK IN
+12V_PCI 1 2 W6 J19
P9 A2 P9 A79 48 48 AD48 16 LAD16
P9 B80 47 47 Y6 AD47 MODE1 A19 PCI_MODE1 15 J18 LAD15 PMEREQ B10
P9 A80 46 46 V7 AD46 MODE0 A20 PCI_MODE0 14 J17 LAD14 LRESET A16 LB_LRESET*
V5_PCI P9 B81 45 45 W7 AD45 HOSTEN C15 LB_HOSTEN* 13 H20 LAD13 USERI_LLOCKI B14 CPLD_NSTATUS
IN
B P9 A82 44 44 Y7 AD44 V3.3 12 H19 LAD12 USERO_LLOCKO C14 PLX_NCONFIG
OUT
P9 A5 P9 B83 43 43 V8 AD43 11 H18 LAD11 WAIT B16 LB_WAIT*
BI
P9 B5 P9 A83 42 42 W8 AD42 CPCISW Y14 CPCISW 8 1 10 G20 LAD10
P9 B6 P9 B84 41 41 Y8 AD41 CPCI64EN U12 CPCI64EN* 7 2 9 G19 LAD9 PRESENT_DET A11
C162 C163 C524 C171 V2.5
P9 A8 P9 A85 V9 AD40 BD_SEL C9 BD_SEL* 6 3 F20 LAD8
0.01 0.01 0.01 0.01
40 40 8
D
P9 A61 P9 B86 39 39 W9 AD39 ENUM Y13 5 4 7 G18 LAD7 VAUX_2V5 D10
P9 A62 P9 A86 38 38 Y9 AD38 LED_ON V13 6 F19 LAD6

W10
R298 D E20 C11
C443 C494 C486 C496 C527 C532 C528 C456 C442 C491 C441
P9 B61 P9 B87 37 37 AD37 5 LAD5 VCORE
V10
10K G17 C19
0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.1 0.1 0.1 2.2
P9 B62 P9 A88 36 36 AD36 4 LAD4 VCORE
V3.3_PCI D P9 B89 35 35 Y10 AD35 EESK A12 PLX_EESK 3 F18 LAD3 VCORE E2
A P9 A89 34 34 Y11 AD34 EECS B12 PLX_EECS 2 E19 LAD2 VCORE P3
P9 A21 P9 B90 W11 AD33 EEDI/EEDO B11 PLX_EED E18 LAD1 VCORE U9
33 33 1
D
C P9 B25 P9 A91 32 32 V11
A5
AD32 0 D19 LAD0 VCORE U19
V3.3
V3.3
C
P9 A27 P9 B20 31 31 AD31 L210
C167 C168 C169 D7 D9 TRST* LB_DTR* W14 C10
P9 B31 P9 A20 30 30 AD30 TRST IN OUT DIR VAUX_CARD 1
1UH 2
0.01 0.01 0.01 C6 A8 TCK LB_DEN* Y15
P9 A33 P9 B21 29 29 AD29 TCK IN OUT DEN
P9 B36 P9 A22 28 28 B5 AD28 TDI A7 CONF_TDO LB_ALE V14 ALE VDDA W2 C523 C522 C521 C520 C519 C518
IN BI
P9 A39 P9 B23 27 27 A4 AD27 TDO C8 R114 22.1 PLX_TDO NC W15 LA28 0.01 0.01 0.01 0.01 0.1 2.2
OUT
P9 B41 P9 A23 26 26 C5 AD26 TMS B8 TMS NC Y16 LA27 VRING A1
IN
P9 B43 C537 C170 C489 P9 B24 25 25 B4 AD25 V2.5 NC U14 LA26 VRING D4
P9 A45 0.01 0.01 0.01 P9 A25 24 24 A3 AD24 NC V15 LA25 VRING D6
P9 A53 P9 B27 23 23 B3 AD23 NC W16 LA24 VRING D8 D

P9 B54 P9 A28 22 22 B2 AD22 R285 NC Y17 LA23 VRING D11
P9 A14 NC P9 B29 21 21 A2 AD21 0 NC V16 LA22 VRING D13 C531 C530 C483 C447 C446 C455 C495 C482 C490 C497 C488
V_I/O_PCI D P9 A29 20 20 C3 AD20 REF NC W17 LA21 VRING D15 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.1 0.1 0.1
D P9 B30 19 19 B1 AD19 C141 D NC Y18 LA20 VRING D17
P9 A10 P9 A31 18 18 C2 AD18 REF 2.2 NC U16 LA19 VRING F4
2
P9 A16 P9 B32 17 17 D2 AD17 Q1 NC V17 LA18 VRING F17
P9 B19 C166 C499 C143 P9 A32 16 16 D3 AD16 PME B9 TN2106 1 NC W18 LA17 VRING H4 D
PWR_SEQ
P9 A59 0.01 0.01 0.01 P9 A44 15 15 H3 AD15 NC Y19 LA16 VRING H17
P9 B59 P9 B45 14 14 H2 AD14 NC V18 LA15 VRING K4 C529 C481 C445 C448 C453 C122 C493 C440 C478 C487 C534 C525
P9 A66 P9 A46 H1 IDSEL C4 PCI_IDSEL P9 A26 NC W19 VRING L17 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.1 0.1 0.1
3
13 13 AD13 LA14
P9 B70 P9 B47 12 12 J4 AD12 FRAME C1 PCI_FRAME* P9 A34 REF NC Y20 LA13 VRING N4
P9 A75 P9 A47 11 11 J3 AD11 DEVSEL E1 PCI_DEVSEL* P9 B37 R299 NC W20 LA12 VRING N17
C172 C173 C174 J2 G4 PCI_LOCK* V3.3 V19 R4
P9 B79 P9 B48 10 10 AD10 LOCK P9 B39 10K NC LA11 VRING
0.01 0.01 0.01 J1 D1 PCI_IRDY* U18 R17 D
P9 A84 P9 A49 9 9 AD9 IRDY P9 B35 NC LA10 VRING
P9 B88 P9 B52 8 8 K2 AD8 IDQEN A10 IDQEN* NC T17 LA9 VRING U4
P9 B53 7 7 K1 AD7 NC V20 LA8 VRING U6 C533 C484 C485 C452 C454 C492 C450 C526 C477 C476 C501 C451
B P9 B3
D
P9 A54 6 6 L2
L3
AD6
L1 PCI_CLK
NC U20
T18
LA7 VRING U8
U10
0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.1 0.1 0.1 B
P9 B15 P9 B55 5 5 AD5 PCLK P9 B16 NC LA6 VRING
P9 B17 P9 A55 4 4 L4 AD4 NC T19 LA5 VRING U13
P9 B22 P9 B56 3 3 M1 AD3 NC T20 LA4 VRING U15
P9 B28 P9 A57 2 2 M2 AD2 INTA B7 PCI_INTA* P9 A6 NC R18 LA3 VRING U17 D

P9 B34 P9 B58 1 1 M3 AD1 RST A6 PCI_RST* P9 A15 LB_LBE<3..0>* NC P17 LA2
BI
+
M4 G3 PCI_SERR* J9
C179 C480 C535 C479 C498 C123 C500 C439 C142
P9 B38 P9 A58 0 0 AD0 SERR P9 B42 VSS
R20 J10
68 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
P9 B46 3 LBE3 VSS
CBEN<7..0> P18 J11
6.3V
P9 B57 2 LBE2 VSS
P9 B64 TRDY E3 PCI_TRDY* P9 A36 1 P19 LBE1 VSS J12
P9 B67 P9 A64 T2 CBE7 STOP F3 PCI_STOP* P9 A38 P20 LBE0 VSS K9

7 7 0
U15 D
P9 B73 P9 B65 6 6 U1 CBE6 IN
LB_BIGEND* C12 BIGEND VSS K10 V3.3
P9 B76 P9 A65 5 5 T3 CBE5 LB_LSERR* D16 LSERR VSS K11 FM93CS56L
OUT
P9 B82 P9 B66 4 4 U2 CBE4 PERR F2 PCI_PERR* P9 B40 LB_LINTI* B15 LINTI VSS K12 8 VCC SK 2 PLX_EESK
IN OUT
P9 B85 P9 B26 3 3 D5 CBE3 PAR64 V1 PCI_PAR64* P9 A67 V3.3 OUT
LB_LINTO* A15 LINTO VSS L9 6 PE CS 1 PLX_EECS
P9 B91 P9 B33 2 2 E4 CBE2 PAR G2 PCI_PAR P9 A43 PLX_LHOLD B18 LHOLD VSS L10 7 PRE DI 3 PLX_EED
V_I/O_PCI OUT
C503 C502 OUT
P9 B94 P9 B44 1 1 G1 CBE1 PLX_LHOLDA B17 LHOLDA VSS L11 DO 4
D R304 IN
0.1 0.01
P9 A18 P9 A52 0 0 K3 CBE0 LB_BLAST* A18 BLAST VSS L12
BI
N1 PCI_ACK64* 10K LB_BTERM* C20 M9
P9 A24 ACK64 P9 B60 BI BTERM VSS
R122 N2 PCI_REQ64* PLX_BREQI C16 M10
P9 A30 200 REQ64 P9 A60 IN BREQI VSS
P9 A35 A9 VIO PLX_BREQO A17 BREQO VSS M11 PRE
OUT
P9 A37 F1 VIO LB_ADS* C17 ADS VSS M12 PE
R123 BI D
P9 A42 C177 C175 C165 C164 C176 C178 V2 VIO GNT0/REQ C7 PCI_REQ* P9 B18 LB_READY* E17 READY VSSA Y1 REF
6
5
7
200 BI
P9 A48 2.2 0.1 0.01 0.01 0.01 0.01 W13 VIO REQ0/GNT B6 PCI_GNT* P9 A17 LB_LWR R19 LWR VBB W3 R301
BI
V3.3 R111
P9 A56 1K
R124 PBGA 1K
P9 A63 200
A P9 A69 D 0.06W
A
P9 A72
4
3
1
R125 D
P9 A78
P9 A81
200 PCI
D
P9 A87
FORMAT PER PR12001
P9 A90
P9 A93 DGND
D
SIZE DWG NO. REV
B 00-885794DDW 6
Tue Oct 21 07:02:01 2008 SCALE: N/A SHEET 2 OF 23
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
3
REV
6
1
D D
V3.3
6
5
7
R308
10K
U14 67P
CLK_CONF_66M CLK_CONF_66M
4
3
1
IN
CLK_10HZ CLK_10HZ CF_READY CF_READY
IN
VTM_INT* VTM_INT
CF_BYTE*
IN
CF_WP*
OUT
PLX_LHOLDA PLX_LHOLDA V3.3
PLX_LHOLD U13
IN PLX_LHOLD
LB_LAD<31..0> LB_LAD<31..0> CF_CE CF_CE* 29LV640
BI
PLX_BREQI PLX_BREQI CF_OE CF_OE* SPEED=120_NS
OUT
PLX_BREQO PLX_BREQO CF_WE CF_WE* VCC 43
IN
AP_INTR* AP_INTR 32 CE
IN
LB_LINTI* LB_LINTI LB_LRESET* 34 OE
OUT IN
LB_LBE<1..0>* LB_LBE<1..0> 13 WE NC/VIO 29
IN
LB_ADS* LB_ADS CF_ADR<23..0> CF_ADR<23..0> 16 WP
IN
LB_BLAST* LB_BLAST ACC
IN
LB_LWR CF_READY
C IN
LB_READY*
LB_LWR
LB_READY 53
14 RESET
BYTE
RY
BY
17
C
OUT
PLX_NCONFIG PLX_NCONFIG
IN
PLX_EESK PLX_DCLK
IN
PLX_EED PLX_DATAO
IN V3.3
23 1 NC/A23
AP_HOLD AP_HOLD 22 2 NC/A22
IN
AP_HOLDA AP_HOLDA 21 15 A21
IN
AP_BREQI C470 C468 C469 C516
OUT AP_BREQI CONFIG_CPLD 20 12 A20
AP_BREQO 11
0.01 0.01 0.01 2.2
IN AP_BREQO 19 A19
V2.5 18 18 A18
APGP_NCONFIG APGP_NCONFIG 17 19 A17
OUT
APGP_DCLK R286 22.1 APGP_DCLK 54 A16
OUT
16
D
APGP_DATAO APGP_DATAO 15 3 A15 DQ15/A-1 51 15
OUT
R292 R94 APGP_NSTATUS 4 49
IN APGP_NSTATUS 14 A14 DQ14 14
10K 10K CPLD_NSTATUS 5 47
OUT CPLD_NSTATUS 13 A13 DQ13 13
APGP_CONF_DONE APGP_CONF_DONE 12 6 A12 DQ12 45 12

IN
11 7 A11 DQ11 42 11
AP_INIT_DONE 10 8 A10 DQ10 40 10
AP_INIT_DONE GP_INIT_DONE 9 9 A9 DQ9 38 9

IN
GP_INIT_DONE 8 10 A8 DQ8 36 8
IN
CONF_LED* CONF_LED 7 20 A7 DQ7 50 7
OUT
LB_ACTIVE* LB_ACTIVE 6 21 A6 DQ6 48 6
OUT
5 22 A5 DQ5 46 5
V3.3
4 23 A4 DQ4 44 4
B 3
2
24
25
A3
A2
DQ3
DQ2
41
39
3
2
B
R312 R303 26 37
1 A1 DQ1 1
10K 10K 31 35
0 A0 DQ0 0
CONF_DEV_OE DEV_OE
LB_LRESET* DEV_CLR PACK_TYPE=TSOP
IN
TMS TMS
IN
TCK TCK LB_LAD<15..0>
IN BI
GP_TDO TDI
IN
CONF_TDO 1 2 TDO
OUT
SEE SHEET 12
R287
22.1
A A
CONFIGURATION
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
4
REV
6
1
C237 330P R3 75
268P
U7
1 8 1 8 OSC_40M OSC_40M
IN
2 7 2 7 OSC_66M_A LB_CCS LB_CCS*
OUT JTAG HEADER P2 6 TRST*
3 6 3 6 OSC_66M_AP OSC_66M_B CLOCK LB_BIGEND LB_BIGEND*
IN OUT
INPUTS
AP_BREQI V3.3
10
4 5 4 5 OSC_66M_C AP_BREQI OUT
LB_DREQ<1..0> LB_DREQ<1..0>* U6
OUT
C234 330P R5 75 LB_ADS* LB_ADS AP_HOLDA AP_HOLDA P2 4 P2 5 9 8 TMS
BI OUT
PLX PCI9656
1 8 1 8 LB_ALE LB_ALE INTERFACE AP_INTR AP_INTR* P2 2 74LCX125
BI OUT
2 7 2 7 LB_DEN* LB_DEN P2 10
IN
AVREF1_1.25V AVREF1_1.25V
LB_BLAST* OUT
13
3 6 3 6 LB_BLAST
BI
AVREF2_1.25V AVREF2_1.25V
4 5 4 5 AP_BREQO AP_BREQO OUT
U6
OUT
LB_BTERM* ATSDX_REF_CLK D TCK
D
12 11
D C233 330P R7 75
BI
IN
LB_DTR*
LB_BTERM
LB_DTR
ATREF_SD_CLK
P2 7 NC
P2 1
74LCX125
1 8 1 8 LB_DMPAF_EOT* LB_DMPAF/EOT ATSD1_CLK ATSD1_CLK P2 8 NC
BI OUT
2 7 2 7 LB_DP<3..0> LB_DP<3..0> ATSD1_CLK* ATSD1_CLK* R302
4
BI OUT
3 6 3 6 LB_DACK<1..0>* LB_DACK<1..0> ATSD1_CKE ATSD1_CKE U6 75
IN OUT
4 5 4 5 ATSD1_CAS ATSD1_CAS* 5 6 TDI
OUT
LB_LAD<31..0> ATSD1_RAS* P2 9
BI LB_LAD<31..0> ATSD1_RAS OUT 74LCX125
C231 330P R8 75 LB_LBE<3..0>* LB_LBE<3..0> ATSD1_WE ATSD1_WE* C507
BI OUT
R37 V3.3
1 8 1 8 AP_HOLD AP_HOLD ATSD1_CS ATSD1_CS* 220P
OUT OUT
2 7 2 7 LB_LINTO* ATSD1_DQM<3..0> 1K R217
IN LB_LINTO ATSD1_DQM<3..0> OUT 1 8
3 6 3 6 LB_LRESET* ATSD1_A<13..0> 10K TS_BUF_JTAG
BI LB_LRESET ATSD1_A<13..0> OUT 2 7
4 5 4 5 LB_LSERR* LB_LSERR ATSD1_BA<1..0> ATSD1_BA<1..0>
IN OUT 3 6
LB_LWR LB_LWR ATSD1_DQS<3..0> ATSD1_DQS<3..0> D
BI BI 4 5
C230 330P R9 75 LB_READY* LB_READY ATSD1_D<31..0> ATSD1_D<31..0>
BI BI
1 8 1 8 LB_WAIT* LB_WAIT D
1
BI
2 7 2 7 ATSD2_CLK ATSD2_CLK
OUT
3 6 3 6 VC_FIELD ATSD2_CLK* ATSD2_CLK* P2 3 3 2 TDO
OUT
4 5 4 5 VC_D<11..0> VC_VID<11..0> ATSD2_CKE ATSD2_CKE 74LCX125
OUT R36
VC_PIXCLK ATSD2_CAS ATSD2_CAS* U6
OUT 22.1
D VC_VSYNC ATSD2_RAS ATSD2_RAS*
OUT
V3.3
VC_HSYNC ATSD2_WE ATSD2_WE*
OUT
VC_SPARE<3..1> ATSD2_CS ATSD2_CS*
OUT
ATSD2_DQM<3..0> ATSD2_DQM<3..0> C200
P4 40 VC_FIELD OUT
ATSD2_A<13..0> ATSD2_A<13..0> 0.1
P4 38 VC_D<0> 0 OUT
ATSD2_BA<1..0> ATSD2_BA<1..0>
P4 36 VC_D<1> 1 OUT
ATSD2_D<31..0> ATSD2_D<31..0>
P4 34 VC_D<2> 2 BI
ATSD2_DQS<3..0>
C P4 32 VC_D<3> 3
ATSD2_DQS<3..0> BI
D C
P4 30 VC_D<4> 4
VC_SPARE<3..1>
VC_D<5> ABSDX_REF_CLK
P4 28 5
VC_D<6> ABREF_SD_CLK
P4 26 6
P4 24 VC_D<7> 7 AP ABSD1_CLK ABSD1_CLK

P4 22 VC_D<8> 8 (AQUISITION PROCESSOR) OUT
ABSD1_CLK* ABSD1_CLK*
P4 20 VC_D<9> 9 OUT
ABSD1_CKE ABSD1_CKE
P4 18 VC_D<10> 10 OUT
ABSD1_CAS ABSD1_CAS*
P4 16 VC_D<11> 11 OUT
P4 13 VC_PIXCLK ABSD1_RAS ABSD1_RAS*

OUT
+5V NS TEST HEADER AP TEST HEADER
ABSD1_WE ABSD1_WE* R92 REF
P4 10 VC_VSYNC* OUT
ABSD1_CS ABSD1_CS* 0
P4 8 VC_HSYNC* OUT
ABSD1_DQM<3..0> ABSD1_DQM<3..0>
P4 6 VC_SPARE<1> 1 OUT
P8 1 REF P3 1 REF
ABSD1_A<13..0> ABSD1_A<13..0>
P4 4 VC_SPARE<2> 2 OUT 19 P8 19 19 P3 19
ABSD1_BA<1..0> ABSD1_BA<1..0>
P4 2 VC_SPARE<3> 3 OUT 18 P8 18 18 P3 18
ABSD1_D<31..0> ABSD1_D<31..0>
VC
BI
APGP_CTL_AD<31..0> ABSD1_DQS<3..0>
17 P8 17 17 P3 17
P4 39 (VIDEO CONTROL) OUT APGP_CTL_AD<31..0> ABSD1_DQS<3..0> BI
APGP_CTL_MCNTL<2..0>
16 P8 16 16 P3 16
P4 37 OUT APGP_CTL_MCNTL<2..0>
NOTE: CONNECOR PINOUT IS PER WIRE NUMBER, NOT SCSI.
APGP_CTL_SCNTL<1..0> ABSD2_CLK
15 P8 15 15 P3 15
P4 35 OUT APGP_CTL_SCNTL<1..0> ABSD2_CLK OUT
SEE HRS FOR PINOUT X-REF.
APGP_CTL_BE<3..0> ABSD2_CLK*
14 P8 14 14 P3 14
P4 33 OUT APGP_CTL_BE<3..0> ABSD2_CLK* OUT
ABSD2_CKE
13 P8 13 13 P3 13
P4 31 GPTOAP_CINE_OE ABSD2_CKE OUT
OUT GPTOAP_CINE_OE ABSD2_CAS*
12 P8 12 12 P3 12
P4 29 GPTOAP_CLK_SPARE ABSD2_CAS OUT
R270 OUT GPTOAP_CLK_SPARE ABSD2_RAS*
11 P8 11 11 P3 11
P4 27 GP_ERR_LED* GPTOAP_SPARE<3..0> ABSD2_RAS OUT
IN 75 IN GPTOAP_SPARE<3..0> ABSD2_WE*
10 P8 10 10 P3 10
P4 25 APTOGP_SPARE<3..0> ABSD2_WE OUT
OUT APTOGP_SPARE<3..0> ABSD2_CS*
9 P8 9 9 P3 9
P4 23 V3.3 DS1 ABSD2_CS OUT
C120 AP_SW_RST ABSD2_DQM<3..0>
8 P8 8 8 P3 8
P4 21 TOP OUT AP_SW_RST ABSD2_DQM<3..0> OUT
220P GP_INTR ABSD2_A<13..0>
7 P8 7 7 P3 7
B P4
P4
19
17
4 RED 3 IN GP_INTR
PXL_CLK
ABSD2_A<13..0>
ABSD2_BA<1..0> ABSD2_BA<1..0>
OUT 6 P8 6 6 P3 6 B
OUT
PXL_CLK_OUT ABSD2_D<31..0>
5 P8 5 5 P3 5
P4 15 OUT PXL_CLK_OUT ABSD2_D<31..0> BI
BOT D 4 P8 4 4 P3 4
P4 14 RED GP_COMP_FAULT GP_COMP_FAULT ABSD2_DQS<3..0> ABSD2_DQS<3..0>
2 1 IN BI 3 P8 3 3 P3 3
P4 12
AP_VID<15..0>
2 P8 2 2 P3 2
P4 11 AP_VID<15..0> OUT
GP_VID<15..0> AP_GP VID INTERFACE
AP_SYNC<2..0> P8 20 P3 20
P4 9 IN GP_VID<15..0> AP_SYNC<2..0> OUT
DS2 GP_SYNC<2..0> AP_CINE_VID<11..0>
P4 7 7 8 IN GP_SYNC<2..0> AP_CINE_VID<11..0> BI
0
P4 5 AP_CINE_SYNC<2..0> AP_CINE_SYNC<2..0>
5 6 1 OUT D D
P4 3 3 4 AP_ERR_LED* NS_TP<19..2>
AP_ERR_LED NS_TP<19..2>
P4 1 1 2 AP_LED<1..0>* AP_TP<19..2>
AP_LED<1..0> AP_TP<19..2>
GRN CLK_10HZ CLK_10HZ
OUT
FPDP_NRDY FPDP_NRDY*
D BI
CONF_LED* FPDP_TX_CLK FPDP FPDP_DIR FPDP_DIR*
IN BI LCLKH P5 2
LB_ACTIVE* FPSTROB FPDP_RX_CLK FPDP_SUSP FPDP_SUSP*
IN BI BI LCLKL P5 3
FPDP_DVALID FPDP_DVALID* P5 1
BI 0 LS<0> P5 5
FPDP_SYNC FPDP_SYNC* P5 4
BI 1 LS<1> P5 7
AP_INIT_DONE INIT_DONE FPDP_PIO<2..1> FPDP_PIO<2..1> P5 6
OUT BI 0 LD<0> P5 9
TRST* APGP_NCONFIG NCONFIG FPDP_D<31..0> FPDP_D<31..0> P5 8
OUT IN BI 1 LD<1> P5 10
TMS APGP_NSTATUS NSTATUS FPDP_CLK_BUF_OE FPDP_CLK_BUF_OE* P5 11
OUT OUT BI 2 LD<2> P5 12
TCK APGP_DCLK DCLK P5 14
OUT IN 3 LD<3> P5 13
APGP_DATAO DATAO P5 17
BI 4 LD<4> P5 15
PLX_TDO R305
1 02 APGP_CONF_DONE CONFIG_DONE DA_LCLK LCLKH P5 18
IN OUT 5 LD<5> P5 16
CONF_TDO R3061 02 AP_NCEO NCEO DA_LCLK* LCLKL P5 21
IN OUT
GP_TDO REF 1 2 NCE LS<1..0>
IN NCE DA_LS<1..0> P5 23
R291 0 LD<5..0>
R251 DA_LD<5..0> P5 25
REF
A TDO
D
10K DA_RCLK
DA_RCLK*
RCLKH
RCLKL
RCLKH
RCLKL
P5
P5
19
20
P5
P5
28
31
A
2
REF R307 DA_RS<1..0> RS<1..0> P5 34

0 DA_RD<5..0> RD<5..0>
0 RS<0> P5 22
RS<1> AP (AQUISITION PROCESSOR)
FORMAT PER PR12001
TRST*
1 P5 24 D
TRST
1
0 RD<0> P5 26
DA
TMS TMS
1 RD<1> P5 27
TCK TCK
2 RD<2> P5 29
TDI TDI
3 RD<3> P5 30
(DISPLAY ADAPTOR) GE HEALTHCARE - SURGERY
AP_TDO TDO
OUT
SEE SHEETS 13, 14, & 15 4 RD<4> P5 32
SIZE DWG NO. REV
R96
22.1
5 RD<5> P5 33
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
5
REV
6
1
136P
U8
GTSDX_REF_CLK
OSC_40M OSC_40M GTREF_SD_CLK
IN
V3.3 GVREF1_1.25V GVREF1_1.25V
OUT
OSC_66M_A GVREF2_1.25V GVREF2_1.25V
OUT
V3.3 IN
OSC_66M_GP OSC_66M_B GTSD1_CLK GTSD1_CLK
OUT
OSC_66M_C GTSD1_CLK* GTSD1_CLK*
OUT
C471 GTSD1_CKE
GTSD1_CKE OUT
0.1 GTSD1_CAS*
R297 GTSD1_CAS OUT
U18 GTSD1_RAS*
1K GTSD1_RAS OUT
ADM1025 GTSD1_WE GTSD1_WE*
OUT
D 4 VCC SDA 1 VTM_SDA GTSD1_CS GTSD1_CS*
OUT D
SCL 2 VTM_SCL GTSD1_DQM<3..0> GTSD1_DQM<3..0>
OUT
V1.5 V2.5 V3.3 +5V D 3 GND GTSD1_A<12..0> GTSD1_A<13..0>
OUT
C R309 8 GTSD1_BA<1..0>
VID3 VTM_TEMPGP_N GTSD1_BA<1..0> OUT
511 VM_V5 12 7 GTSD1_DQS<3..0>
5VIN VID2 REF VTM_TEMPGP_P GTSD1_DQS<3..0> BI
R310 511 VM_V3.3 13 3.3VIN VID1 6 C517 GTSD1_D<31..0> GTSD1_D<31..0>
BI
R295 511 VM_V2.5 14 2.5VIN VID0 5 1000P
VM_V1.5 15 VCCIN GTSD2_CLK GTSD2_CLK
OUT
R294 D-/NTI 9 VTM_TEMPGP_N V3.3 GTSD2_CLK* GTSD2_CLK*
OUT
511 16 ADD/NTO GTSD2_CKE GTSD2_CKE
OUT
C147 C148 C180 C181 RST/INT D+ 10 VTM_TEMPGP_P GP GTSD2_CAS GTSD2_CAS*
OUT
2.2 2.2 2.2 2.2 12VIN/VID4 11 R296 (GDRM IMAGE PROCESSOR) GTSD2_RAS GTSD2_RAS*
OUT
10K GTSD2_WE GTSD2_WE*
OUT
VOLTAGE & TEMP MON (VTM) GTSD2_CS GTSD2_CS*
OUT
VTM_INT* VTM_INT GTSD2_DQM<3..0> GTSD2_DQM<3..0>
OUT
GTSD2_A<12..0> GTSD2_A<13..0>
OUT
D VTM_INT* GTSD2_BA<1..0> GTSD2_BA<1..0>
OUT OUT
GTSD2_D<31..0> GTSD2_D<31..0>
BI
LB_LRESET* LB_LRESET GTSD2_DQS<3..0> GTSD2_DQS<3..0>
IN BI
GBSDX_REF_CLK
APGP_CTL_AD<31..0> APGP_CTL_AD<31..0> GBREF_SD_CLK
BI
APGP_CTL_MCNTL<2..0> APGP_CTL_MCNTL<2..0>
IN
APGP_CTL_SCNTL<1..0> APGP_CTL_SCNTL<1..0> GBSD1_CLK GBSD1_CLK
IN OUT
APGP_CTL_BE<3..0> APGP_CTL_BE<3..0> GBSD1_CLK* GBSD1_CLK*
IN OUT
GBSD1_CKE GBSD1_CKE
OUT
C IN
GPTOAP_CINE_OE GPTOAP_CINE_OE GBSD1_CAS GBSD1_CAS*
OUT C
GPTOAP_CLK_SPARE GPTOAP_CLK_SPARE GBSD1_RAS GBSD1_RAS*
OUT OUT
GPTOAP_SPARE<3..0> GBSD1_WE*
OUT
APTOGP_SPARE<3..0>
GPTOAP_SPARE<3..0>
APTOGP_SPARE<3..0>
GBSD1_WE
GBSD1_CS GBSD1_CS*
OUT
CINE
IN OUT
GBSD1_DQM<3..0> GBSD1_DQM<3..0> NOTE: CONNECTOR PINOUT IS PER WIRE NUMBER, NOT SCSI.
OUT
PXL_CLK_OUT PXL_CLK GBSD1_A<12..0> GBSD1_A<13..0> SEE HRS FOR PINOUT X-REF.
IN OUT
R261 GP_COMP_FAULT GP_COMP_FAULT GBSD1_BA<1..0> GBSD1_BA<1..0>
OUT OUT
75 GP_INTR GP_INTR GBSD1_D<31..0> GBSD1_D<31..0> P6 40
OUT BI
AP_SW_RST AP_SW_RST GBSD1_DQS<3..0> GBSD1_DQS<3..0> P6 39
IN BI
CINE_CLK_BUF_OE* CINE_CLK_BUF_OE P6 38
OUT
C377 GBSD2_CLK GBSD2_CLK 1 CINE_D1 P6 37
OUT
220P GBSD2_CLK* GBSD2_CLK* P6 36
OUT
GBSD2_CKE GBSD2_CKE 0 CINE_D0 P6 35
OUT
GBSD2_CAS GBSD2_CAS* P6 34
OUT
D GBSD2_RAS GBSD2_RAS* CINE_TAG* P6 33
OUT
GBSD2_WE GBSD2_WE* P6 32
OUT
GBSD2_CS GBSD2_CS* CINE_VDRV* P6 31
OUT
GBSD2_DQM<3..0> GBSD2_DQM<3..0> P6 30
OUT
GBSD2_A<12..0> GBSD2_A<13..0> CINE_HDRV* P6 29
OUT
GBSD2_BA<1..0> GBSD2_BA<1..0> P6 28
OUT
GBSD2_D<31..0> GBSD2_D<31..0> 11 CINE_D11 P6 27
BI
GBSD2_DQS<3..0> GBSD2_DQS<3..0> P6 26
BI
10 CINE_D10 P6 25
IN
AP_VID<15..0> AP_VID<15..0> GP_VID<15..0> GP_VID<15..0>
OUT P6 24 GP TEST HEADER
AP_SYNC<2..0> AP_SYNC<2..0> AP_GP VID GP_SYNC<2..0> GP_SYNC<2..0> 9 CINE_D9 P6 23
IN OUT
INTERFACE P6 22 +5V
B BI
AP_CINE_VID<11..0> AP_CINE_VID<11..0> 8 1 8 1 11 8 CINE_D8 P6 21
R110 REF
B
AP_CINE_SYNC<2..0> AP_CINE_SYNC<2..0> 7 2 7 2 10 R126 P6 20
IN
6 3 6 3 CINE_D7 0
D C190 9 75 7 P6 19
330P 5 4 5 4 8 P6 18 P7 1 REF
8 1 8 1 7 6 CINE_D6 P6 17 19 P7 19
APGP_NCONFIG NCONFIG C191 7 2 7 2 6 R127 P6 16 18 P7 18
IN
APGP_NSTATUS NSTATUS 330P 6 3 6 3 5 75 5 CINE_D5 P6 15 17 P7 17
OUT
APGP_DCLK DCLK 5 4 5 4 4 P6 14 16 P7 16
IN
APGP_DATAO DATAO 8 1 8 1 3 4 CINE_D4 P6 13 15 P7 15
BI
APGP_CONF_DONE C192 7 2 7 2
OUT CONFIG_DONE 2 R128 P6 12 14 P7 14
GP_INIT_DONE 330P 6 3 6 3 CINE_D3
OUT INIT_DONE 1 75 3 P6 11 13 P7 13
AP_NCEO NCE 5 4 5 4 0 P6 10 12 P7 12
IN
NC NCEO CINE_TAG 2 CINE_D2 P6 9 11 P7 11
CINE_VDRV P6 8 10 P7 10
CINE_HDRV 9 P7 9
TRST* TRST CINE_D_OE* P6 7 8 P7 8
IN
TMS TMS 7 P7 7
IN
TCK TCK CINE_D<11..0> CINE_D<11..0> P6 6 6 P7 6
IN
AP_TDO TDI CINE_D_OE P6 5 5 P7 5
IN
GP_TDO TDO CINE_PIXCLK CINE_PIXCLK P6 4 4 P7 4
OUT
R293 0 R26 REF P6 3 3 P7 3
22.1 CINE_PIXCLK_B R25 P6 2 2 P7 2
R129 OUT
P6 1 P7 20
10K 0
D
D D
A GP_TP<19..2> GP_TP<19..2> A
GP_ERR_LED* GP_ERR_LED
OUT
BRD_ID<3..0> BRD_ID<3..0>*
0
1
GP (GDRM IMAGE PROCESSOR)
FORMAT PER PR12001
REF REF REF REF

SEE SHEETS 16, 17, & 18 R27 R30 R28 R29
BOARD REV
1K 1K 1K 1K PULL-UP'S INTERNAL TO GP
SIZE DWG NO. REV
B 00-885794DDW 6
D
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
6
REV
6
1
V3.3
R210 R211 R212 R213

221 221 221 221
R13 R12 R11 R10

332 332 332 332
D D D D D D
FPSTROB FPSTROB P1 2
IN
FPDP_NRDY* FPDP_NRDY* P1 7
IN
FPDP_DIR* FPDP_DIR* P1 9
IN
FPDP_SUSP* FPDP_SUSP* P1 13
IN
FPDP_PIO<2..1>
IN
R14 27
1 1 8 FPPIO1 P1 19
2 2 7 FPPIO2 P1 17
FPDP_SYNC* 3 6 FPSYNC* P1 29
IN
FPDP_DVALID* 4 5 FPDVALID* P1 31
IN
R16 27
1 8
PSTROB (NC) P1 25
31 31
2 7
PSTROB* (NC) P1 27
30 30
29 3 6 29
4 5
NC P1 11
28 28
NC P1 21
NC P1 23
R17 27
27 1 8 27
2 7
31 P1 33
26 26
3 6
30 P1 34
25 25
4 5
29 P1 36
24 24
28 P1 37
27 P1 39
C 23 1
R18 27
8 23
26 P1 40 C
2 7
25 P1 42
22 22
3 6
24 P1 43
21 21
4 5
23 P1 45
20 20
22 P1 46
21 P1 48
R19 27
1 8
20 P1 49
19 19
2 7
19 P1 51
18 18
3 6
18 P1 52
17 17
4 5
17 P1 54
16 16
16 P1 55
15 P1 57
R20 27
1 8
14 P1 58
15 15
2 7
13 P1 60
14 14
3 6
12 P1 61
13 13
4 5
11 P1 63
12 12
10 P1 64
9 P1 66
R21 27
1 8
8 P1 67
11 11
2 7
7 P1 69
10 10
3 6
6 P1 70
9 9
4 5
5 P1 72
8 8
4 P1 73
3 P1 75
R22 27
1 8
2 P1 76
7 7
1 P1 78
B 6
5
2
3
7
6
6
5
0 P1 79 B
4 5
P1 1
4 4
P1 3
P1 4
R23 27
1 8
P1 5
3 3
2 7
P1 6
2 2
3 6
P1 8
1 1
4 5
P1 10
0 0
P1 12
FPDP_D<31..0> FPDP<31..0> P1 14
IN
P1 15
P1 16
P1 18
P1 20
P1 22
P1 24
P1 26
P1 28
P1 30
P1 32
P1 35
P1 38
P1 41
P1 44
P1 47
P1 50
A P1 53 A
P1 56
P1 59
P1 62 FPDP
FORMAT PER PR12001
P1 65 (FRONT PANEL DATA PORT)

P1 68
P1 71
P1 74
P1 77
P1 80 SIZE DWG NO. REV
B 00-885794DDW 6
D
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
7
REV
6
1
ATSD1 U202
ATSD2 U207
R43 100 SDRAM_256MBIT V2.5 R280 100 SDRAM_256MBIT V2.5

SPEED=75 SPEED=75
ATSD1_CLK 45 CK VDD 1 ATSD2_CLK 45 CK VDD 1
IN IN
ATSD1_CLK* 46 CK VDD 18 ATSD2_CLK* 46 CK VDD 18
IN IN
ATSD1_CKE 44 CKE VDD 33 ATSD2_CKE 44 CKE VDD 33
IN IN
VDDQ 3 VDDQ 3
D IN
ATSD1_RAS*
ATSD1_CAS*
23
22
RAS VDDQ 9
15
IN
ATSD2_RAS*
ATSD2_CAS*
23
22
RAS VDDQ 9
15
D
IN CAS VDDQ IN CAS VDDQ
ATSD1_WE* 21 WE VDDQ 55 ATSD2_WE* 21 WE VDDQ 55
IN IN
ATSD1_CS* 24 CS VDDQ 61 ATSD2_CS* 24 CS VDDQ 61
IN IN
ATSD1_DQM<3..0> VSS 66 ATSD2_DQM<3..0> VSS 66

IN IN
3 47 UDM VSS 48 3 47 UDM VSS 48
ATSD1_DQS<3..0> 20 LDM VSS 34 ATSD2_DQS<3..0> 20 LDM VSS 34
IN
2
D IN
2
D
R245 22.1 VSSQ 64 VSSQ 64
ATSD1_A<13..0> 51 58 ATSD2_A<13..0> R281 22.1 51 58
IN
3 UDQS VSSQ IN
3 UDQS VSSQ
2 16 LDQS VSSQ 52 2 16 LDQS VSSQ 52
ATSD1_BA<1..0> VSSQ 12 ATSD2_BA<1..0> VSSQ 12
IN IN
R229 22.1 6
R266 22.1 6
VSSQ VSSQ
ATSD1_D<31..0> ATSD2_D<31..0>
BI BI
VREF 49 AVREF2_1.25V VREF 49 AVREF2_1.25V
IN
C436
13 17 NC/A13 DQ15 65 1 8 31 C330 13 17 NC/A13 DQ15 65 1 8 31 0.01
42 63 2 7
R247 42 63 2 7
R283
12 A12 DQ14 30 0.01 12 A12 DQ14 30
41 62 3 6
22 41 62 3 6
22
11 A11 DQ13 29 11 A11 DQ13 29
10 28 A10 DQ12 60 4 5 28 10 28 A10 DQ12 60 4 5 28
40 A9 DQ11 59 1 8 40 A9 DQ11 59 1 8 D
9 27
R246 D 9 27
R282
8 39 A8 DQ10 57 2 7 26 8 39 A8 DQ10 57 2 7 26
38 56 3 6
22 38 56 3 6
22
7 A7 DQ9 25 7 A7 DQ9 25
6 37 A6 DQ8 54 4 5 24 6 37 A6 DQ8 54 4 5 24
5 36 A5 DQ7 13 1 8 23 5 36 A5 DQ7 13 1 8 23
R230 R267
C 4 35
32
A4 DQ6 11
10
2
3
7
6
22
22
4 35
32
A4 DQ6 11
10
2
3
7
6
22
22 C
3 A3 DQ5 21 3 A3 DQ5 21
2 31 A2 DQ4 8 4 5 20 2 31 A2 DQ4 8 4 5 20
1 30 A1 DQ3 7 1 8 19 1 30 A1 DQ3 7 1 8 19
29 5 2 7
R231 29 5 2 7
R268
0 A0 DQ2 18 0 A0 DQ2 18
27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 17 1 BA1 DQ1 17
0 26 BA0 DQ0 2 4 5 16 0 26 BA0 DQ0 2 4 5 16
U3 U11
SDRAM_256MBIT V2.5 SDRAM_256MBIT V2.5

SPEED=75 SPEED=75
45 CK VDD 1 45 CK VDD 1
44 CKE VDD 33 44 CKE VDD 33
VDDQ 3 VDDQ 3
23 RAS VDDQ 9 23 RAS VDDQ 9
22 CAS VDDQ 15 22 CAS VDDQ 15
21 WE VDDQ 55 21 WE VDDQ 55
V2.5
24 CS VDDQ 61 24 CS VDDQ 61
VSS 66 VSS 66
1 47 UDM VSS 48 1 47 UDM VSS 48
+
C22 C272 C331 C332 C275 C276 C273 C277 C274 20 34 20 34

0 LDM VSS 0 LDM VSS
68 2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01 64 64
VSSQ VSSQ
6.3V R42 22.1 R84 22.1
B 1 51
16
UDQS VSSQ 58
52
1 51
16
UDQS VSSQ 58
52
B
0 LDQS VSSQ 0 LDQS VSSQ
VSSQ 12 D VSSQ 12 D
R66 22.1 6
R100 22.1 6
D VSSQ VSSQ
V2.5
17 65 1 8
C36 17 65 1 8
C100
13 NC/A13 DQ15 15 13 NC/A13 DQ15 15
C329 C34 C66 C65 C68 C67 C35 C69 42 63 2 7
R40 0.01 42 63 2 7
R82 0.01
12 A12 DQ14 14 12 A12 DQ14 14
2.2 0.01 0.01 0.01 0.01 1000P 0.01 0.01 41 62 3 6
22 41 62 3 6
22
11 A11 DQ13 13 11 A11 DQ13 13
10 28 A10 DQ12 60 4 5 12 10 28 A10 DQ12 60 4 5 12
40 A9 DQ11 59 1 8 40 A9 DQ11 59 1 8
9 11
R41 D 9 11
R83 D
8 39 A8 DQ10 57 2 7 10 8 39 A8 DQ10 57 2 7 10
38 56 3 6
22 38 56 3 6
22
D 7 A7 DQ9 9 7 A7 DQ9 9
6 37 A6 DQ8 54 4 5 8 6 37 A6 DQ8 54 4 5 8
V2.5
5 36 A5 DQ7 13 1 8 7 5 36 A5 DQ7 13 1 8 7
35 11 2 7
R65 35 11 2 7
R99
4 A4 DQ6 6 4 A4 DQ6 6
32 10 3 6
22 32 10 3 6
22
3 A3 DQ5 5 3 A3 DQ5 5
2 31 A2 DQ4 8 4 5 4 2 31 A2 DQ4 8 4 5 4
C394 C438 C437 C399 C398 C396 C397 C395 30 7 1 8 30 7 1 8
1 A1 DQ3 3 1 A1 DQ3 3
2.2 0.01 0.01 0.01 0.01 0.01 1000P 0.01 29 5 2 7
R64 29 5 2 7
R98
0 A0 DQ2 2 0 A0 DQ2 2
27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 1 1 BA1 DQ1 1
0 26 BA0 DQ0 2 4 5 0 0 26 BA0 DQ0 2 4 5 0
ATSD1_D<31..0> ATSD2_D<31..0>
V2.5 D
A A
C435 C98 C99 C126 C125 C127 C128 C124

TSD1 AND TSD2 MEMORY FOR AP_FPGA
FORMAT PER PR12001
2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01
D
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
8
REV
6
1
ABSD1 U203
ABSD2 U205

SPEED=75 SPEED=75
ABSD1_CLK 45 CK VDD 1 ABSD2_CLK 45 CK VDD 1
IN IN
ABSD1_CLK* 46 CK VDD 18 ABSD2_CLK* 46 CK VDD 18
IN IN
ABSD1_CKE 44 CKE VDD 33 ABSD2_CKE 44 CKE VDD 33
IN IN
VDDQ 3 VDDQ 3
ABSD1_RAS* 23 RAS VDDQ 9 ABSD2_RAS* 23 RAS VDDQ 9
IN IN
ABSD1_CAS* 22 CAS VDDQ 15 ABSD2_CAS* 22 CAS VDDQ 15
IN IN
ABSD1_WE* 21 WE VDDQ 55 ABSD2_WE* 21 WE VDDQ 55
IN IN
D IN
ABSD1_CS* 24 CS VDDQ 61
IN
ABSD2_CS* 24 CS VDDQ 61 D
ABSD1_DQM<3..0> VSS 66 ABSD2_DQM<3..0> VSS 66
IN IN
3 47 UDM VSS 48 3 47 UDM VSS 48
ABSD1_DQS<3..0> 20 LDM VSS 34 ABSD2_DQS<3..0> 20 LDM VSS 34
IN
2
D IN
2
D
R253 22.1 VSSQ 64 R290 VSSQ 64
ABSD1_A<13..0> 51 58 ABSD2_A<13..0> 22.1 51 58
IN
3 UDQS VSSQ IN
3 UDQS VSSQ
ABSD1_BA<1..0> VSSQ 12 ABSD2_BA<1..0> R252 VSSQ 12
IN IN
R214 22.1 6
22.1 6
VSSQ VSSQ
ABSD1_D<31..0> ABSD2_D<31..0>
BI BI
IN
17 65 1 8 17 65 1 8
C424
13 NC/A13 DQ15 31 13 NC/A13 DQ15 31
42 63 2 7
R256 42 63 2 7
R273 0.01
12 A12 DQ14 30 C356 12 A12 DQ14 30
41 62 3 6
22 41 62 3 6
22
11 A11 DQ13 29 0.01 11 A11 DQ13 29
10 28 A10 DQ12 60 4 5 28 10 28 A10 DQ12 60 4 5 28
9 40 A9 DQ11 59 1 8 27 9 40 A9 DQ11 59 1 8 27 D
39 57 2 7
R254 39 57 2 7
R272
8 A8 DQ10 26
D 8 A8 DQ10 26
38 56 3 6
22 38 56 3 6
22
7 A7 DQ9 25 7 A7 DQ9 25
6 37 A6 DQ8 54 4 5 24 6 37 A6 DQ8 54 4 5 24
5 36 A5 DQ7 13 1 8 23 5 36 A5 DQ7 13 1 8 23
35 11 2 7
R215 35 11 2 7
R255
4 A4 DQ6 22 4 A4 DQ6 22
32 10 3 6
22 32 10 3 6
22
3 A3 DQ5 21 3 A3 DQ5 21
2 31 A2 DQ4 8 4 5 20 2 31 A2 DQ4 8 4 5 20
C 1 30 A1 DQ3 7 1 8 19
R216
1 30 A1 DQ3 7 1 8 19
R257
C
0 29 A0 DQ2 5 2 7 18 0 29 A0 DQ2 5 2 7 18
27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 17 1 BA1 DQ1 17
0 26 BA0 DQ0 2 4 5 16 0 26 BA0 DQ0 2 4 5 16
U2 U9

SPEED=75 SPEED=75
VDDQ 3 VDDQ 3
VSS 66 VSS 66
1 47 UDM VSS 48 1 47 UDM VSS 48
0 20 LDM VSS 34 0 20 LDM VSS 34
VSSQ 64 R58 VSSQ 64

R4 22.1 51 58
22.1 51 58
1 UDQS VSSQ 1 UDQS VSSQ
V2.5 0 16 LDQS VSSQ 52 0 16 LDQS VSSQ 52
VSSQ 12 D R93 VSSQ 12 D

B R59 22.1
VSSQ 6
22.1
VSSQ 6 B
C297 C298 C238 C236 C235 C232 C358 C360 VREF 49 AVREF1_1.25V VREF 49 AVREF1_1.25V
2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01
13 17 NC/A13 DQ15 65 1 8 15 C9 13 17 NC/A13 DQ15 65 1 8 15 C58

42 63 2 7
R1 42 63 2 7
R54
12 A12 DQ14 14 0.01 12 A12 DQ14 14 0.01
V2.5 41 62 3 6
22 41 62 3 6
22
11 A11 DQ13 13 11 A11 DQ13 13
D 10 28 A10 DQ12 60 4 5 12 10 28 A10 DQ12 60 4 5 12
9 40 A9 DQ11 59 1 8 11 9 40 A9 DQ11 59 1 8 11
39 57 2 7
R2 39 57 2 7
R56
8 A8 DQ10 10
D 8 A8 DQ10 10
D
38 56 3 6
22 38 56 3 6
22
C30 C54 C57 C55 C59 C29 C7 C8 7 A7 DQ9 9 7 A7 DQ9 9
2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01 6 37 A6 DQ8 54 4 5 8 6 37 A6 DQ8 54 4 5 8
5 36 A5 DQ7 13 1 8 7 5 36 A5 DQ7 13 1 8 7
35 11 2 7
R57 35 11 2 7
R79
4 A4 DQ6 6 4 A4 DQ6 6
32 10 3 6
22 32 10 3 6
22
3 A3 DQ5 5 3 A3 DQ5 5
2 31 A2 DQ4 8 4 5 4 2 31 A2 DQ4 8 4 5 4
V2.5 D 1 30 A1 DQ3 7 1 8 3 1 30 A1 DQ3 7 1 8 3
29 5 2 7
R55 29 5 2 7
R78
0 A0 DQ2 2 0 A0 DQ2 2
27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 1 1 BA1 DQ1 1
C423 C426 C425 C359 C357 C361 C355 C362 0 26 BA0 DQ0 2 4 5 0 0 26 BA0 DQ0 2 4 5 0
2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01

ABSD1_D<31..0> ABSD2_D<31..0>
V2.5
A D A
BSD1 AND BSD2 MEMORY FOR AP FPGA
C60 C53 C56 C92 C88 C90 C91 C89
FORMAT PER PR12001
2.2 0.01 0.01 0.01 0.01 1000P 0.01 0.01
D SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
9
REV
6
1
GTSD1 U200
GTSD2 U204

SPEED=75 SPEED=75
GTSD1_CLK 45 CK VDD 1 GTSD2_CLK 45 CK VDD 1
IN IN
GTSD1_CLK* 46 CK VDD 18 GTSD2_CLK* 46 CK VDD 18
IN IN
GTSD1_CKE 44 CKE VDD 33 GTSD2_CKE 44 CKE VDD 33
IN IN
VDDQ 3 VDDQ 3
GTSD1_RAS* 23 RAS VDDQ 9 GTSD2_RAS* 23 RAS VDDQ 9
IN IN
GTSD1_CAS* 22 CAS VDDQ 15 GTSD2_CAS* 22 CAS VDDQ 15
IN IN
GTSD1_WE* 21 WE VDDQ 55 GTSD2_WE* 21 WE VDDQ 55
D
IN IN
D IN
GTSD1_CS* 24 CS VDDQ 61
IN
GTSD2_CS* 24 CS VDDQ 61
GTSD1_DQM<3..0> VSS 66 GTSD2_DQM<3..0> VSS 66

IN IN
3 47 UDM VSS 48 3 47 UDM VSS 48
GTSD1_DQS<3..0> 20 LDM VSS 34 GTSD2_DQS<3..0> 20 LDM VSS 34
IN
2
D IN
2
D
R202 22.1 VSSQ 64 R238 22.1 VSSQ 64
GTSD1_A<13..0> 3 51 UDQS VSSQ 58 GTSD2_A<13..0> 3 51 UDQS VSSQ 58
IN IN
GTSD1_BA<1..0> VSSQ 12 GTSD2_BA<1..0> VSSQ 12
IN IN
R239 22.1 6
R260 22.1 6
VSSQ VSSQ
GTSD1_D<31..0> GTSD2_D<31..0>
BI BI
VREF 49 GVREF2_1.25V VREF 49 GVREF2_1.25V
IN
C301
13 17 NC/A13 DQ15 65 1 8 31 13 17 NC/A13 DQ15 65 1 8 31 0.01
42 63 2 7
R200 42 63 2 7
R236
12 A12 DQ14 30 C203 12 A12 DQ14 30
41 62 3 6
22 41 62 3 6
22
11 A11 DQ13 29 0.01 11 A11 DQ13 29
28 A10 DQ12 60 4 5 28 A10 DQ12 60 4 5

10 28 10 28
D
9 40 A9 DQ11 59 1 8 27 9 40 A9 DQ11 59 1 8 27
39 57 2 7
R201 39 57 2 7
R237
8 A8 DQ10 26
D 8 A8 DQ10 26
38 56 3 6
22 38 56 3 6
22
7 A7 DQ9 25 7 A7 DQ9 25
6 37 A6 DQ8 54 4 5 24 6 37 A6 DQ8 54 4 5 24
5 36 A5 DQ7 13 1 8 23 5 36 A5 DQ7 13 1 8 23
35 11 2 7
R219 35 11 2 7
R259
4 A4 DQ6 22 4 A4 DQ6 22
32 10 3 6
22 32 10 3 6
22
3 A3 DQ5 21 3 A3 DQ5 21
2 31 A2 DQ4 8 4 5 20 2 31 A2 DQ4 8 4 5 20
C 1 30 A1 DQ3 7 1 8 19
R218
1 30 A1 DQ3 7 1 8 19
R258
C
0 29 A0 DQ2 5 2 7 18 0 29 A0 DQ2 5 2 7 18
27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 17 1 BA1 DQ1 17
0 26 BA0 DQ0 2 4 5 16 0 26 BA0 DQ0 2 4 5 16
PACK_TYPE=TSOPII PACK_TYPE=TSOPII
U5 U10

SPEED=75 SPEED=75
VDDQ 3 VDDQ 3
V2.5
VSS 66 VSS 66
1 47 UDM VSS 48 1 47 UDM VSS 48
0 20 LDM VSS 34 0 20 LDM VSS 34
VSSQ 64 D VSSQ 64
D
+
C144 C51 C241 C243 C242 C244 C240 C202 R74 22.1 51 58
R89 22.1 51 58
68 2.2 0.01 0.01 1000P 0.01 0.01 0.01 16 52 16 52
6.3V 12 12
VSSQ VSSQ
B R33 22.1
VSSQ 6
R73 22.1
VSSQ 6 B
D
V2.5
17 65 1 8
C80 17 65 1 8
13 NC/A13 DQ15 15 13 NC/A13 DQ15 15
42 63 2 7
R52 0.01 42 63 2 7
R91 C111
12 A12 DQ14 14 12 A12 DQ14 14
41 62 3 6
22 41 62 3 6
22 0.01
11 A11 DQ13 13 11 A11 DQ13 13
C239 C48 C49 C23 C50 C27 C25 C26 C201 28 60 4 5 28 60 4 5
10 A10 DQ12 12 10 A10 DQ12 12
2.2 0.01 0.01 0.01 0.01 0.01 0.01 1000P 0.01 40 59 1 8 40 59 1 8
9 A9 DQ11 11 9 A9 DQ11 11
39 57 2 7
R51 D 39 57 2 7
R90
8 A8 DQ10 10 8 A8 DQ10 10
38 56 3 6
22 38 56 3 6
22 D
7 A7 DQ9 9 7 A7 DQ9 9
6 37 A6 DQ8 54 4 5 8 6 37 A6 DQ8 54 4 5 8
36 A5 DQ7 13 1 8 36 A5 DQ7 13 1 8
D 5 7
R34
5 7
R75
4 35 A4 DQ6 11 2 7 6 4 35 A4 DQ6 11 2 7 6
V2.5 22 22
3 32 A3 DQ5 10 3 6 5 3 32 A3 DQ5 10 3 6 5
2 31 A2 DQ4 8 4 5 4 2 31 A2 DQ4 8 4 5 4
1 30 A1 DQ3 7 1 8 3 1 30 A1 DQ3 7 1 8 3
29 5 2 7
R35 29 5 2 7
R76
0 A0 DQ2 2 0 A0 DQ2 2
C114 C300 C299 C366 C367 C368 C365 C364 27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 1 1 BA1 DQ1 1
2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01 26 2 4 5 26 2 4 5
0 BA0 DQ0 0 0 BA0 DQ0 0
GTSD1_D<31..0> PACK_TYPE=TSOPII GTSD2_D<31..0> PACK_TYPE=TSOPII
D
V2.5
A A
TSD1 AND TSD2 MEMORY FOR GP FPGA
C363 C112 C113 C82 C81 C83 C84 C79
FORMAT PER PR12001
2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01
D SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
10
REV
6
1
GBSD1 U201
GBSD2 U206

SPEED=75 SPEED=75
GBSD1_CLK 45 CK VDD 1 GBSD2_CLK 45 CK VDD 1
IN IN
GBSD1_CLK* 46 CK VDD 18 GBSD2_CLK* 46 CK VDD 18
IN IN
GBSD1_CKE 44 CKE VDD 33 GBSD2_CKE 44 CKE VDD 33
IN IN
VDDQ 3 VDDQ 3
GBSD1_RAS* 23 RAS VDDQ 9 GBSD2_RAS* 23 RAS VDDQ 9
IN IN
GBSD1_CAS* 22 CAS VDDQ 15 GBSD2_CAS* 22 CAS VDDQ 15
D IN
IN
GBSD1_WE* 21 WE VDDQ 55
IN
IN
GBSD2_WE* 21 WE VDDQ 55 D
GBSD1_CS* 24 CS VDDQ 61 GBSD2_CS* 24 CS VDDQ 61
IN IN
GBSD1_DQM<3..0> VSS 66 GBSD2_DQM<3..0> VSS 66

IN IN
3 47 UDM VSS 48 3 47 UDM VSS 48
GBSD1_DQS<3..0> 20 LDM VSS 34 GBSD2_DQS<3..0> 20 LDM VSS 34
IN
2
D IN
2
D
R227 22.1 VSSQ 64 R265 22.1 VSSQ 64
GBSD1_A<13..0> 3 51 UDQS VSSQ 58 GBSD2_A<13..0> 3 51 UDQS VSSQ 58
IN IN
GBSD1_BA<1..0> VSSQ 12 GBSD2_BA<1..0> VSSQ 12
IN IN
R244 22.1 6
R279 22.1 6
VSSQ VSSQ
GBSD1_D<31..0> GBSD2_D<31..0>
BI BI
IN
C393
17 65 1 8
C271 17 65 1 8
13 NC/A13 DQ15 31 13 NC/A13 DQ15 31 0.01
42 63 2 7
R225 0.01 42 63 2 7
R263
12 A12 DQ14 30 12 A12 DQ14 30
41 62 3 6
22 41 62 3 6
22
11 A11 DQ13 29 11 A11 DQ13 29
28 A10 DQ12 60 4 5 28 A10 DQ12 60 4 5

10 28 10 28
D
40 A9 DQ11 59 1 8 40 A9 DQ11 59 1 8
9 27
R226 D 9 27
R264
8 39 A8 DQ10 57 2 7 26 8 39 A8 DQ10 57 2 7 26
38 56 3 6
22 38 56 3 6
22
7 A7 DQ9 25 7 A7 DQ9 25
6 37 A6 DQ8 54 4 5 24 6 37 A6 DQ8 54 4 5 24
5 36 A5 DQ7 13 1 8 23 5 36 A5 DQ7 13 1 8 23
35 11 2 7
R243 35 11 2 7
R278
4 A4 DQ6 22 4 A4 DQ6 22
32 10 3 6
22 32 10 3 6
22
3 A3 DQ5 21 3 A3 DQ5 21
C 2 31 A2 DQ4 8 4 5 20 2 31 A2 DQ4 8 4 5 20 C
1 30 A1 DQ3 7 1 8 19 1 30 A1 DQ3 7 1 8 19
29 5 2 7
R242 29 5 2 7
R277
0 A0 DQ2 18 0 A0 DQ2 18
27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 17 1 BA1 DQ1 17
0 26 BA0 DQ0 2 4 5 16 0 26 BA0 DQ0 2 4 5 16
U4 U12

SPEED=75 SPEED=75
VDDQ 3 VDDQ 3
VSS 66 VSS 66
V2.5
1 47 UDM VSS 48 1 47 UDM VSS 48
0 20 LDM VSS 34 0 20 LDM VSS 34
VSSQ 64 VSSQ 64
R67 22.1 51 58
R102 22.1 51 58
+
C6 C37 C270 C328 C326 C327 C325 C324 16 52 16 52

B 68 2.2 0.01 0.01 1000P 0.01 0.01 0.01
VSSQ 12 D VSSQ 12 D B
6.3V R44 22.1 6
R85 22.1 6
VSSQ VSSQ
D
V2.5 C71
13 17 NC/A13 DQ15 65 1 8 15 13 17 NC/A13 DQ15 65 1 8 15
42 63 2 7
R69 0.01 42 63 2 7
R104
12 A12 DQ14 14 12 A12 DQ14 14
41 62 3 6
22 41 62 3 6
22
11 A11 DQ13 13 11 A11 DQ13 13 C130
10 28 A10 DQ12 60 4 5 12 10 28 A10 DQ12 60 4 5 12 0.01
C70 C72 C73 C42 C38 C39 C40 C41 C269 40 59 1 8 40 59 1 8
9 A9 DQ11 11
D 9 A9 DQ11 11
2.2 0.01 0.01 0.01 0.01 0.01 1000P 0.01 0.01 39 57 2 7
R68 39 57 2 7
R103
8 A8 DQ10 10 8 A8 DQ10 10
38 56 3 6
22 38 56 3 6
22
7 A7 DQ9 9 7 A7 DQ9 9
6 37 A6 DQ8 54 4 5 8 6 37 A6 DQ8 54 4 5 8 D
5 36 A5 DQ7 13 1 8 7 5 36 A5 DQ7 13 1 8 7
35 11 2 7
R45 35 11 2 7
R86
D 4 A4 DQ6 6 4 A4 DQ6 6
32 10 3 6
22 32 10 3 6
22
V2.5
3 A3 DQ5 5 3 A3 DQ5 5
2 31 A2 DQ4 8 4 5 4 2 31 A2 DQ4 8 4 5 4
1 30 A1 DQ3 7 1 8 3 1 30 A1 DQ3 7 1 8 3
29 5 2 7
R46 29 5 2 7
R87
0 A0 DQ2 2 0 A0 DQ2 2
27 4 3 6
22 27 4 3 6
22
1 BA1 DQ1 1 1 BA1 DQ1 1
C101 C392 C431 C432 C433 C434 C430 C391 26 2 4 5 26 2 4 5
0 BA0 DQ0 0 0 BA0 DQ0 0
2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01
GBSD1_D<31..0> GBSD2_D<31..0>
A D
A
V2.5
BSD1 AND BSD2 MEMORY FOR GP FPGA

FORMAT PER PR12001
C129 C103 C104 C105 C106 C102 C132 C131

2.2 0.01 1000P 0.01 0.01 0.01 0.01 0.01
SIZE DWG NO. REV
D B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
11
REV
6
1
V5_PCI
B
TP2 TP4
V3.3 TP1
CB2 CB1
+5V BLK BLK
3.0A 1.25A RED
VR1
R130
MIC29152BU 1K
D 2
1
IN OUT
4
5
D
CB3 EN ADJ
R53 R77
+
3.0A C86 GND D
10K 1.33K
100
3 6
16V C52
R275 0.01
+
332 C87
D D 100
16V
R274 +5V
1K
C185 C186 C187 C545 C546 C547

D D 0.01 0.01 0.01 0.01 0.01 0.01
TP3
D
RED
U19
C153 V1.5
TPS54613 R131
REFERENCE DESIGNATIONS 20 5
0.047 C
VIN BOOT 1K V3.3
HIGHEST UNUSED 21
L4
VIN 50V
C550 C190-C199 22 6 1
6.4UH 2
VIN V1.5
CB5 23 VIN V1.5 7
C152 C188 C189 C548 C549 C550
C DS2
C
+
C183 24 VIN V1.5 8 C161
L210 L5-L199 10 9
0.01 0.01 0.01 0.01 0.01
100 V1.5 R118 0.01
P9 16V V1.5 10 1
Q1 R119 C150
+
27 FSEL V1.5 11 C149 C136
R312 R121-R199 75K 28 12
330
RT V1.5 0.01 1000P
TP5 26 13
10V D
SS/ENA V1.5 C151
U207 U20-U199 25 VBIAS V1.5 14 2200P
VR1 C154 4 PWRGD
Y2 0.1 2 SENSE GND 15
D V1.5
GND 16
C
1 AGND GND 17
GND 18
29 PWR_PAD GND 19
C134 C182 C10 C28 C4 C85

0.01 0.01 0.01 0.01 0.01 0.01
D D
V1.5
C D
C1 C24 C3 C5 C160 C117

0.01 0.01 0.01 0.01 0.01 0.01
B B
TP5 D
CB4 RED
U20
3.0A V2.5
C140
TPS54615 R132
20 5
0.047
VIN BOOT 1K
21
L2
VIN 50V
22 6 1
6.4UH 2
VIN V2.5
23 VIN V2.5 7
C158 24 VIN V2.5 8

+
C184 9
R120
10 V2.5
100 10
1 R117
V2.5 1 8
16V R121 C156 R116
+
27 FSEL V2.5 11 C155 C139
75K 330 2 7 100
28 RT V2.5 12 0.01 1000P
C157 10V 3 6
26 SS/ENA V2.5 13
2200P 4 5
25 VBIAS V2.5 14
C159 4 PWRGD 22
0.1 2 SENSE GND 15
16
TEST VIAS ADDED FOR ICT
GND
1 AGND GND 17
D
GND 18
29 PWR_PAD GND 19
D D
A A
REGULATION
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885794DDW 6
SCALE: N/A SHEET 11 OF 23
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
12
REV
6
1
V3.3
D D
V3.3
LB_LAD<31..0>\I
BI
U14
EPM3256ATC144 EPM3256ATC144
SPEED=7.5_NS
CLK_10HZ\I 1 P1 P37 37 CF_ADR<11>\I V3.3 73 VCCIO P109 109 LB_LAD<8>\I
IN
LB_LINTI\I 2 P2 P38 38 CF_ADR<12>\I 31 LB_LAD<31>\I 74 P74 P110 110 LB_LAD<7>\I
OUT
3 GNDIO P39 39 CF_ADR<13>\I NC 75 P75 P111 111 LB_LAD<6>\I
TDI\I 4 IO-TDI P40 40 CF_ADR<14>\I V3.3 76 VCCIO P112 112 LB_LAD<5>\I
IN
CF_ADR<16>\I 5 P5 P41 41 CF_ADR<15>\I 77 GNDIO P113 113 LB_LAD<4>\I
CF_ADR<23..0>\I CF_OE\I 6 42 LB_LAD<30>\I 78
OUT OUT P6 P42 NC 30 P78 GNDIO 114
CF_CE\I 7 P7 P43 43 NC 29 LB_LAD<29>\I 79 P79 VCCIO 115 V3.3
OUT
0 CF_ADR<0>\I 8 P8 P44 44 VTM_INT\I 28 LB_LAD<28>\I 80 P80 P116 116 LB_LAD<3>\I
IN
1 CF_ADR<1>\I 9 P9 P45 45 GP_INIT_DONE\I 27 LB_LAD<27>\I 81 P81 P117 117 LB_LAD<2>\I
IN
2 CF_ADR<2>\I 10 P10 P46 46 NC 26 LB_LAD<26>\I 82 P82 P118 118 LB_LAD<1>\I
3 CF_ADR<3>\I 11 P11 P47 47 NC 25 LB_LAD<25>\I 83 P83 P119 119 LB_LAD<0>\I
NC 12 P12 P48 48 NC 24 LB_LAD<24>\I 84 P84 P120 120 AP_INTR\I
IN
13 GNDIO P49 49 NC 85 GNDIO P121 121 LB_ACTIVE\I
OUT
4 CF_ADR<4>\I 14 P14 VCCIO 50 V3.3 23 LB_LAD<23>\I 86 P86 P122 122 NC
CF_ADR<5>\I V3.3 LB_LAD<22>\I V3.3
C
15 VCC 51 87 VCC 123
C P15 P87
5 22
6 CF_ADR<6>\I 16 P16 GND 52 21 LB_LAD<21>\I 88 P88 GND 124

17 GNDIO P53 53 PLX_NCONFIG\I TCK\I 89 IO-TCK IN/GCLK1 125 CLK_CONF_66M\I
IN IN IN
7 CF_ADR<7>\I 18 P18 P54 54 PLX_DCLK\I 20 LB_LAD<20>\I NC 90 P90 IN/OE1 126 DEV_OE\I
IN IN
NC 19 P19 P55 55 PLX_DATAO\I CONF_LED\I 91 P91 IN/GLCRn 127 DEV_CLR\I
IN OUT IN
TMS\I 20 IO-TMS P56 56 PLX_BREQO\I 19 LB_LAD<19>\I 92 P92 IN/OE2/GCLK2 128 AP_HOLD\I
IN IN IN
CF_ADR<17>\I 21 P21 GND 57 18 LB_LAD<18>\I 93 P93 GND 129
CF_ADR<18>\I 22 P22 VCC 58 V3.3 94 GNDIO VCC 130 V3.3
CF_READY\I 23 P23 GNDIO 59 V3.3 95 VCCIO P131 131 AP_BREQI\I
IN OUT
V3.3 24 VCCIO P60 60 PLX_BREQI\I 17 LB_LAD<17>\I 96 P96 P132 132 AP_BREQO\I
IN
CF_ADR<21>\I 25 P25 P61 61 PLX_LHOLDA\I 16 LB_LAD<16>\I 97 P97 P133 133 AP_HOLDA\I
OUT
26 GNDIO P62 62 PLX_LHOLD\I 15 LB_LAD<15>\I 98 P98 P134 134 AP_INIT_DONE\I
IN IN
CF_WE\I 27 P27 P63 63 LB_BLAST\I 14 LB_LAD<14>\I 99 P99 GNDIO 135
OUT IN
CF_ADR<20>\I 28 P28 GNDIO 64 13 LB_LAD<13>\I 100 P100 P136 136 APGP_CONF_DONE\I
IN
CF_ADR<19>\I 29 P29 P65 65 LB_ADS\I 12 LB_LAD<12>\I 101 P101 P137 137 APGP_DATAO\I
IN OUT
CF_ADR<8>\I LB_LBE<1..0>\I LB_LAD<11>\I
8 30 P30 P66 66 NC IN
11 102 P102 P138 138 APGP_DCLK\I OUT
9 CF_ADR<9>\I 31 P31 P67 67 LB_LWR\I NC 103 P103 P139 139 APGP_NCONFIG\I
IN OUT
10 CF_ADR<10>\I 32 P32 P68 68 LB_READY\I TDO\I 104 IO-TDO P140 140 APGP_NSTATUS\I
OUT IN
11 CF_ADR<11>\I 33 GNDIO P69 69 LB_LBE<1>\I 1 105 GNDIO P141 141 CPLD_NSTATUS\I
OUT
12 CF_ADR<12>\I NC 34 P34 P70 70 LB_LBE<0>\I 0 10 LB_LAD<10>\I 106 P106 P142 142 CF_ADR<23>\I
13 CF_ADR<13>\I NC 35 P35 P71 71 NC 9 LB_LAD<9>\I 107 P107 P143 143 CF_ADR<22>\I
14 CF_ADR<14>\I NC 36 P36 P72 72 LB_LAD<20>\I 8 LB_LAD<8>\I NC 108 P108 VCCIO 144 V3.3
15 CF_ADR<15>\I 7 LB_LAD<7>\I
CF_ADR<16>\I PACK_TYPE=TQFP LB_LAD<6>\I
16 6
CF_ADR<19>\I LB_LAD<3>\I
B 19
20 CF_ADR<20>\I
3
2 LB_LAD<2>\I B
23 CF_ADR<23>\I
V3.3
C515 C542 C540 C538 C505 C504 C459 C462 C464 C467 C544
0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01
144 109 V3.3

NOTE-1: 1 108 NOTE-2: D
USE THIS BODY THIS FIGURE
REPRESENTATION REPRESENTS C514 C512 C509 C539 C511 C506 C460 C461 C465 C466 C543
ONLY AT THE LOGIC COMPONENT 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
SUB-LEVEL OF A 73 PINOUT
36
HIERARCHICAL ( TOP VIEW )
37 72 V3.3
DRAWING. ( REF-ONLY ).
D
NOTE-3: VCC PINS ARE 3.3V
NOTE-4: VCCIO PINS ARE 2.5V OR 3.3V C513 C510 C508 C463
2.2 2.2 2.2 2.2
A A
D
CONFIG CPLD
FORMAT PER PR12001
LOWER LEVEL
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
13
REV
6
1
U7
EP1S40_1020 EP1S40_1020 EP1S40_1020
SPEED=7 SECTION 2 OF 9 SECTION 3 OF 9
SECTION 1 OF 9 G1 G1
DA_LD<1>\I
G2 G2
DGND
G3 G3 N1 N1
AP_CINE_VID<2>\I
G4 G4 N2 N2
AP_CINE_VID<3>\I
DA_LCLK\I G5 G5 N3 N3
AP_CINE_VID<4>\I
DA_LCLK*\I G6 G6 N4 N4
AP_CINE_VID<5>\I
NC G7 G7 N5 N5
AP_VID<2>\I
D A4 A4
NC G8
G9
G8
G9
AP_VID<3>\I
N6
N7
N6
N7
D
ATSD1_D<0>\I DGND AP_VID<4>\I
A5 A5 G10 G10 N8 N8
ATSD1_D<8>\I DGND AP_VID<5>\I
A6 A6 NC G11 G11 N9 N9
ATSD1_D<10>\I R39 AP_VID<6>\I
A7 A7 G12 G12 K2 K2 N10 N10
ATSD1_DQS<2>\I 261 DGND DA_RD<0>\I AP_VID<7>\I
A8 A8 V2.5 G13 G13 K3 K3 NC N11 N11
ATSD1_D<16>\I DA_RD<1>\I
A9 A9 G19 G19 K4 K4 NC N22 N22
ATSD1_D<24>\I ATSD2_A<9>\I DA_RD<2>\I
A11 A11 G20 G20 K5 K5 N23 N23
ATSD1_A<13>\I ATSD2_A<10>\I DA_RD<3>\I GP_VID<6>\I
A13 A13 G21 G21 K6 K6 N24 N24
ATSD1_A<0>\I DGND DA_RD<4>\I GP_VID<5>\I
A14 A14 D4 D4 G22 G22 K7 K7 N25 N25
DGND ATSD1_D<5>\I DGND DA_RS<0>\I GP_VID<4>\I
A15 A15 D5 D5 G23 G23 K8 K8 N26 N26
DGND ATSD1_D<6>\I ATSD2_A<13>\I DA_RS<1>\I GP_VID<3>\I
ATSD1_CLK*\I A16 A16 D6 D6 G24 G24 K9 K9 N27 N27
ATSD1_D<13>\I DGND DGND GP_VID<2>\I
ATSD2_CLK*\I A17 A17 D7 D7 G25 G25 K10 K10 NC N28 N28
ATSD1_D<14>\I NC GP_VID<1>\I
A18 A18 D8 D8 G26 G26 K11 K11 N29 N29
DGND ATSD1_D<20>\I NC DGND GP_VID<0>\I
A20 A20 D9 D9 G27 G27 K12 K12 N30 N30
ATSD2_A<0>\I ATSD1_D<22>\I APGP_CTL_AD<2>\I GP_SYNC<2>\I
A22 A22 D10 D10 G28 G28 K13 K13 N31 N31
DGND ATSD1_D<28>\I APGP_CTL_AD<3>\I GP_SYNC<1>\I
A24 A24 D11 D11 G29 G29 K14 K14 ATSD1_RAS\I N32 N32
ATSD2_D<6>\I ATSD1_DQS<3>\I APGP_CTL_AD<4>\I GP_SYNC<0>\I
A25 A25 D12 D12 G30 G30 K15 K15 ATSD1_CAS\I
ATSD2_D<11>\I ATSD1_A<6>\I APGP_CTL_AD<5>\I
A26 A26 D13 D13 G31 G31 K18 K18 P1 P1
ATSD2_D<15>\I ATSD1_A<3>\I APGP_CTL_AD<6>\I ATSD2_BA<1>\I AP_CINE_VID<6>\I
A27 A27 D14 D14 G32 G32 K19 K19 ATSD2_CAS\I P2 P2
ATSD2_D<19>\I DGND APGP_CTL_AD<7>\I AP_CINE_VID<7>\I
A28 A28 D17 D17 K20 K20 ATSD2_RAS\I P3 P3
ATSD2_D<22>\I AP_CINE_VID<8>\I
A29 A29 D18 D18 H1 H1 K21 K21 P4 P4
ATSD2_D<26>\I DA_LD<2>\I DGND AP_CINE_VID<9>\I
D19 D19 H2 H2 K22 K22 P5 P5
DA_LS<0>\I AP_VID<8>\I
B3 B3 D20 D20 H3 H3 K23 K23 P6 P6
ATSD1_D<1>\I ATSD2_A<6>\I DGND AP_VID<9>\I
B4 B4 D21 D21 H4 H4 K24 K24 P7 P7
ATSD1_D<2>\I ATSD2_CS\I AP_VID<10>\I
B5 B5 D22 D22 H5 H5 K25 K25 P8 P8
ATSD1_D<9>\I ATSD2_DQS<0>\I APGP_CTL_AD<24>\I AP_VID<11>\I
C ATSD1_D<11>\I
B6
B7
B6
B7
D23
D24
D23
D24
ATSD2_D<5>\I
DA_RCLK\I
H6
H7
H6
H7
K26
K27
K26
K27
APGP_CTL_AD<25>\I AP_VID<12>\I
P9
P10
P9
P10
C
ATSD1_D<18>\I ATSD2_D<9>\I APGP_CTL_AD<26>\I AP_VID<13>\I
B8 B8 D25 D25 DA_RCLK*\I H8 H8 K28 K28 NC P11 P11
ATSD1_D<17>\I ATSD2_D<14>\I APGP_CTL_AD<27>\I
B9 B9 D26 D26 H9 H9 K29 K29 NC P22 P22
ATSD1_D<25>\I ATSD2_D<17>\I DGND APGP_CTL_AD<28>\I
B10 B10 D27 D27 H10 H10 K30 K30 AP_SW_RST\I P23 P23
ATSD1_D<26>\I ATSD2_D<21>\I NC APGP_CTL_AD<29>\I
B11 B11 D28 D28 H11 H11 K31 K31 P24 P24
ATSD1_D<30>\I ATSD2_D<24>\I DGND APGP_CTL_AD<30>\I GP_VID<15>\I
B12 B12 D29 D29 H12 H12 P25 P25
DGND ATSD2_D<29>\I DGND GP_VID<14>\I
B13 B13 H13 H13 L1 L1 P26 P26
ATSD1_A<1>\I ATSD1_A<12>\I DA_LD<4>\I GP_VID<13>\I
B14 B14 E1 E1 NC H14 H14 L2 L2 P27 P27
ATSD1_A<4>\I ATSD1_BA<0>\I AP_CINE_SYNC<0>\I GP_VID<12>\I
ATSD1_CLK\I B16 B16 E2 E2 NC H19 H19 L3 L3 P28 P28
ATSD2_A<11>\I AP_CINE_SYNC<1>\I GP_VID<11>\I
ATSD2_CLK\I B17 B17 E4 E4 NC H20 H20 L6 L6 P29 P29
ATSD2_A<12>\I AP_CINE_SYNC<2>\I GP_VID<10>\I
B18 B18 E5 E5 H21 H21 L7 L7 P30 P30
ATREF_SD_CLK\I ATSD1_D<7>\I DGND AP_SYNC<0>\I GP_VID<9>\I
B19 B19 E7 E7 H22 H22 L9 L9 P31 P31
DGND ATSD1_DQS<1>\I DGND GP_VID<8>\I
B20 B20 E9 E9 H23 H23 L10 L10 NC P32 P32
ATSD2_A<1>\I ATSD1_D<23>\I GP_VID<7>\I
B21 B21 E11 E11 H25 H25 L11 L11 DGND
ATSD2_A<4>\I ATSD1_D<29>\I APGP_CTL_AD<8>\I R234
B22 B22 E13 E13 H26 H26 L12 L12 DGND R1 R1
ATSD2_D<0>\I ATSD1_A<8>\I APGP_CTL_AD<9>\I 10K AP_CINE_VID<10>\I
B23 B23 E20 E20 H27 H27 L13 L13 DEV_OE V2.5 R2 R2
ATSD2_D<3>\I ATSD2_A<3>\I APGP_CTL_AD<10>\I AP_CINE_VID<11>\I
B24 B24 E22 E22 H28 H28 L14 L14 ATSD1_CKE\I GPTOAP_CINE_OE\I R3 R3
ATSD2_D<7>\I ATSD2_D<2>\I APGP_CTL_AD<11>\I
B25 B25 E24 E24 H29 H29 L15 L15 ATSD1_WE\I R4 R4
ATSD2_D<12>\I ATSD2_D<10>\I APGP_CTL_AD<12>\I R248 DGND
B26 B26 E26 E26 H30 H30 L18 L18 ATSD2_WE\I R5 R5
ATSD2_DQS<1>\I ATSD2_D<18>\I APGP_CTL_AD<13>\I 261 AP_VID<14>\I
B27 B27 E28 E28 H31 H31 L19 L19 DGND R6 R6
ATSD2_DQS<2>\I ATSD2_D<25>\I APGP_CTL_AD<14>\I AP_VID<15>\I
B28 B28 E29 E29 H32 H32 L20 L20
DGND RST_DISABLE R7 R7
ATSD2_D<23>\I NC APGP_CTL_AD<15>\I DGND
B29 B29 E31 E31 L21 L21 R8 R8
ATSD2_D<27>\I NC APTOGP_SPARE<0>\I
B30 B30 E32 E32 J1 J1 L22 L22 R9 R9
ATSD2_D<30>\I NC DA_LD<3>\I APTOGP_SPARE<1>\I
J2 J2 L23 L23 R10 R10
DA_LS<1>\I APTOGP_SPARE<2>\I
C3 C3 F1 F1 J3 J3 L24 L24 ATSD2_CKE\I NC R11 R11
ATSD1_D<3>\I DGND DA_LD<0>\I
B ATSD1_D<4>\I
C4
C5
C4
C5
F2
F3
F2
F3 NC
DGND DGND
J4
J5
J4
J5
L26
L27
L26
L27
APGP_CTL_BE<3>\I NS_TP<19>\I
R23
R24
R23
R24
B
ATSD1_DQS<0>\I APGP_CTL_BE<2>\I NS_TP<18>\I
C6 C6 F4 F4 NC DA_RD<5>\I J6 J6 L30 L30 R25 R25
ATSD1_D<12>\I APGP_CTL_BE<1>\I GP_INTR\I
C7 C7 F5 F5 NC DGND J7 J7 L31 L31 R26 R26
ATSD1_D<15>\I APGP_CTL_BE<0>\I DGND
C8 C8 F7 F7 DA_LD<5>\I J8 J8 L32 L32 R27 R27
ATSD1_D<19>\I ATSD1_DQM<0>\I APGP_CTL_AD<31>\I CLK_10HZ\I
C9 C9 F8 F8 DGND J9 J9 R28 R28
ATSD1_D<21>\I ATSD1_DQM<1>\I GPTOAP_SPARE<3>\I
C10 C10 F9 F9 NC J10 J10 M2 M2 PXL_CLK_OUT\I R29 R29
ATSD1_D<27>\I ATSD1_DQM<2>\I AP_CINE_VID<0>\I R207
C11 C11 F10 F10 J11 J11 M3 M3 R30 R30
ATSD1_D<31>\I ATSD1_DQM<3>\I R232 DGND AP_CINE_VID<1>\I 261 GPTOAP_SPARE<2>\I
C12 C12 F11 F11 NC J12 J12 M4 M4 DGND R31 R31
DGND 261 DGND GPTOAP_SPARE<1>\I
C13 C13 F12 F12 DGND J13 J13 M5 M5 V3.3 R32 R32
ATSD1_A<2>\I DGND GPTOAP_SPARE<0>\I
C14 C14 F13 F13 J14 J14 M6 M6
ATSD1_A<5>\I ATSD1_A<9>\I ATSD1_BA<1>\I AP_SYNC<1>\I R233
C15 C15 F14 F14 J15 J15 M7 M7 FPDP_CLK_BUF_OE\I T1 T1
DGND ATSD1_A<10>\I ATSD1_CS\I AP_SYNC<2>\I 261
C16 C16 F15 F15 J19 J19 M8 M8 T2 T2
ATSD1_A<7>\I ATSD1_A<11>\I ATSD2_BA<0>\I AP_VID<0>\I DGND
DGND C17 C17 F19 F19 J20 J20 M9 M9 T5 T5
ATSD2_A<7>\I R63 DGND AP_VID<1>\I DGND
C18 C18 F20 F20 J21 J21 M10 M10 NC T11 T11
DGND ATSD2_A<8>\I 261 DGND
C20 C20 F21 F21 V2.5 J22 J22 M11 M11 NC AP_LED<0>\I T28 T28
ATSD2_A<2>\I
C21 C21 F22 F22 J23 J23 M22 M22 NC T31 T31
ATSD2_A<5>\I DGND APTOGP_SPARE<3>\I
C22 C22 F23 F23 J24 J24 M23 M23 NC T32 T32
ATSD2_D<1>\I ATSD2_DQM<0>\I AP_LED<1>\I
C23 C23 F24 F24 J25 J25 M24 M24 APGP_CTL_MCNTL<0>\I
ATSD2_D<4>\I ATSD2_DQM<1>\I APGP_CTL_AD<16>\I
C24 C24 F25 F25 J26 J26 M25 M25 APGP_CTL_MCNTL<1>\I NC U3 U3
ATSD2_D<8>\I ATSD2_DQM<2>\I APGP_CTL_AD<17>\I
C25 C25 F26 F26 J27 J27 M26 M26 APGP_CTL_MCNTL<2>\I FPDP_DIR\I U5 U5
ATSD2_D<13>\I ATSD2_DQM<3>\I APGP_CTL_AD<18>\I R81
C26 C26 F28 F28 NC J28 J28 M27 M27 APGP_CTL_SCNTL<0>\I U6 U6
ATSD2_D<16>\I APGP_CTL_AD<19>\I 261 FPDP_D<24>\I
C27 C27 F29 F29 NC J29 J29 M28 M28 V3.3 NC U22 U22
ATSD2_D<20>\I APGP_CTL_AD<20>\I
C28 C28 F30 F30 NC J30 J30 M29 M29 DGND U27 U27
ATSD2_DQS<3>\I APGP_CTL_AD<21>\I LB_DP<1>\I
C29 C29 F31 F31 J31 J31 M30 M30 APGP_CTL_SCNTL<1>\I U28 U28
ATSD2_D<28>\I APGP_CTL_AD<1>\I APGP_CTL_AD<22>\I R269 LB_LBE<0>\I
C30 C30 F32 F32 J32 J32 M31 M31 GP_COMP_FAULT\I U30 U30
ATSD2_D<31>\I APGP_CTL_AD<0>\I APGP_CTL_AD<23>\I 261 AP_ERR_LED\I
A A
PACK_TYPE=FBGA
NOTE=EP1S60 PIN OUT WAS USED TO ALLOW FOR MIGRATION TO A LARGER PART.
AP (AQUISITION PROCESSOR)
FORMAT PER PR12001
LOWER LEVEL (1 OF 3)
DGND V2.5 V3.3
V2.5 V3.3 GE HEALTHCARE - SURGERY

D
SIZE DWG NO. REV
B 00-885794DDW 6
SCALE: N/A SHEET 13 OF 23
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
14
REV
6
1
U7
EP1S40_1020 EP1S40_1020 EP1S40_1020
SECTION 4 OF 9 AD1 AD1
VC_VID<0>\I
AD2 AD2
VC_VID<4>\I
AD3 AD3
VC_VID<8>\I
AD4 AD4
FPDP_D<19>\I
AD5 AD5
VC_SPARE<1>\I
AD6 AD6
FPDP_D<31>\I
AD7
D AA2 AA2
AP_TP<14>\I
AD8
AD7
AD8
D
FPDP_D<6>\I R15 AP_TP<15>\I
AA3 AA3 AD9 AD9
FPDP_D<12>\I 261 DGND
AA4 AA4 DGND NC AD10 AD10
AA5 AA5 V3.3 NC AD11 AD11
AA6 AA6 AD12 AD12 AK3 AK3
FPDP_D<28>\I R209 ABSD1_DQM<3>\I ABSD1_D<3>\I
FPDP_PIO<2>\I 261 DGND ABSD1_D<4>\I
AP_TP<9>\I DGND ABSD1_DQS<0>\I
AP_TP<10>\I ABSD1_A<4>\I ABSD1_D<12>\I
AA11 AA11 NC AD18 AD18 AG1 AG1 AK7 AK7
ABSD1_A<3>\I VC_VID<3>\I ABSD1_D<15>\I
V1 V1 AA12 AA12 AD19 AD19 AG2 AG2 AK8 AK8
FPDP_D<0>\I ABSD1_DQM<0>\I ABSD2_BA<1>\I VC_VID<7>\I ABSD1_DQS<2>\I
FPDP_TX_CLK\I V2 V2 AA13 AA13 NC AD20 AD20 AG3 AG3 AK9 AK9
ABSD2_BA<0>\I VC_VID<11>\I ABSD1_D<21>\I
V3 V3 AA14 AA14 AD21 AD21 AG4 AG4 VC_FIELD\I AK10 AK10
FPDP_D<9>\I ABSD1_A<11>\I DGND ABSD1_D<27>\I
V4 V4 AA15 AA15 AD22 AD22 AG5 AG5 NC AK11 AK11
FPDP_D<15>\I ABSD1_A<10>\I ABSD1_D<30>\I
FPDP_D<21>\I ABSD1_A<9>\I DGND
V6 V6 AA19 AA19 ABSD2_CAS\I AD24 AD24 AG8 AG8 NC ABSD1_WE\I AK13 AK13
FPDP_D<25>\I
FPDP_DVALID\I V7 V7 AA20 AA20 NS_TP<5>\I AD25 AD25 AG9 AG9 ABSD1_A<1>\I AK14 AK14
DGND DGND
FPDP_NRDY\I V8 V8 AA21 AA21 LB_BIGEND\I AD26 AD26 AG10 AG10 ABSD2_CLK*\I AK16 AK16
DGND DGND
V9 V9 AA22 AA22 NC AP_INTR\I AD27 AD27 AG11 AG11 ABSD1_CKE\I AK17 AK17
AP_TP<2>\I DGND
AP_TP<3>\I NS_TP<8>\I LB_DREQ<0>\I DGND ABSD2_A<6>\I
NC V22 V22 AA25 AA25 AD29 AD29 AG13 AG13 AK20 AK20
NS_TP<7>\I LB_LAD<27>\I ABSD2_A<2>\I
V23 V23 AA26 AA26 LB_CCS\I AD30 AD30 AG14 AG14 ABSD2_CS\I AK21 AK21
NS_TP<17>\I R80 LB_LAD<20>\I
V24 V24 AA27 AA27 LB_WAIT\I AD31 AD31 AG19 AG19 AK22 AK22
NS_TP<16>\I 261 LB_LAD<3>\I ABSD2_A<11>\I ABSD2_D<1>\I
V25 V25 AA28 AA28 V3.3 AD32 AD32 AG20 AG20 AK23 AK23
NS_TP<15>\I LB_READY\I ABSD2_A<9>\I ABSD2_D<4>\I
V26 V26 AA29 AA29 DGND AG21 AG21 AK24 AK24
LB_DP<0>\I ABSD2_A<10>\I ABSD2_D<8>\I
V27 V27 AA30 AA30 AE1 AE1 AG22 AG22 AK25 AK25
LB_DP<2>\I LB_LAD<17>\I R271 VC_VID<1>\I DGND ABSD2_D<13>\I
V28 AA31 AA31 AE2 AG23 AG23 AK26
C LB_LBE<1>\I
LB_LAD<31>\I
V29
V28
V29
LB_LAD<7>\I 261 VC_VID<5>\I
VC_VID<9>\I
AE3
AE2
AE3 AG24 AG24
DGND
ABSD2_DQM<0>\I
ABSD2_D<16>\I
ABSD2_D<20>\I
AK27
AK26
AK27
C
V30 V30 AB1 AB1 AE4 AE4 AG25 AG25 NC AK28 AK28
LB_LAD<14>\I FPDP_D<3>\I VC_VSYNC\I ABSD2_DQS<3>\I
LB_LAD<11>\I FPDP_D<7>\I VC_SPARE<2>\I ABSD2_D<27>\I
LB_LAD<10>\I FPDP_D<13>\I AP_HOLD\I ABSD2_D<31>\I
AB6 AB6 AE7 AE7 AG29 AG29
FPDP_D<29>\I AP_TP<16>\I LB_LAD<24>\I
W1 W1 AB7 AB7 AE8 AE8 AG30 AG30 AL3 AL3
FPDP_D<1>\I AP_TP<11>\I AP_TP<17>\I LB_LAD<23>\I ABSD1_D<1>\I
W2 W2 AB9 AB9 NC AE9 AE9 AG31 AG31 AL4 AL4
FPDP_D<4>\I DGND LB_LAD<0>\I ABSD1_D<2>\I
W3 W3 AB10 AB10 NC NC AE10 AE10 AG32 AG32 LB_ADS\I AL5 AL5
FPDP_D<10>\I ABSD1_D<8>\I
W4 W4 AB11 AB11 DGND AE11 AE11 AL6 AL6
FPDP_D<16>\I ABSD1_DQM<1>\I ABSD1_D<11>\I
W5 W5 AB12 AB12 NC AE12 AE12 AH1 AH1 NC AL7 AL7
FPDP_D<22>\I ABSD1_D<16>\I
W6 W6 AB13 AB13 AE13 AE13 AH2 AH2 NC AL8 AL8
FPDP_D<26>\I DGND R249 ABSD1_D<19>\I
FPDP_SYNC\I W7 W7 AB14 AB14 AE14 AE14 AH4 AH4 NC AL9 AL9
ABSD1_A<7>\I 10K ABSD1_A<2>\I ABSD1_D<24>\I
FPDP_SUSP\I W8 W8 AB15 AB15 V2.5 INIT_DONE\I AE15 AE15 AH5 AH5 AL10 AL10
ABSD1_A<8>\I ABSD1_D<6>\I ABSD1_D<28>\I
W9 W9 AB18 AB18 ABSD1_CS\I AE20 AE20 AH7 AH7 AL11 AL11
AP_TP<4>\I ABSD2_A<12>\I ABSD1_DQS<1>\I ABSD1_D<31>\I
W10 W10 AB19 AB19 ABSD2_RAS\I AE21 AE21 AH9 AH9 AL12 AL12
AP_TP<5>\I DGND ABSD1_D<23>\I DGND
NC W11 W11 AB20 AB20 NC AE22 AE22 AH11 AH11 AL13 AL13
DGND ABSD1_D<29>\I R235 ABSD1_BA<0>\I
NC W12 W12 AB21 AB21 AE23 AE23 AH13 AH13 ABSD1_CAS\I AL14 AL14
DGND 10K ABSD1_A<0>\I
NC W21 W21 AB22 AB22 AE24 AE24 AH14 AH14 DEV_CLR* V2.5 AL15 AL15
ABSD2_A<13>\I ABSD2_DQM<3>\I ABSD1_A<13>\I
NC W22 W22 AB23 AB23 NC AE25 AE25 AH18 AH18 ABSD1_CLK\I AL16 AL16
NS_TP<4>\I ABSD2_A<8>\I
W23 W23 AB24 AB24 AE26 AE26 AH19 AH19 V2.5 AL17 AL17
NS_TP<14>\I DGND LB_ALE\I DGND
W24 W24 AB26 AB26 AP_BREQO\I AE27 AE27 AH20 AH20 AL18 AL18
NS_TP<13>\I LB_LRESET\I ABSD2_A<3>\I R60
W25 W25 AB27 AB27 LB_LSERR\I AE28 AE28 AH22 AH22 AL19 AL19
NS_TP<12>\I LB_DREQ<1>\I ABSD2_D<2>\I 261
LB_DMPAF/EOT\I W26 W26 AB30 AB30 AE29 AE29 AH24 AH24 AL20 AL20
LB_LAD<18>\I LB_LAD<26>\I ABSD2_D<10>\I ABSD2_A<1>\I
W27 W27 AB31 AB31 AE30 AE30 AH26 AH26 AL21 AL21
LB_DP<3>\I LB_LAD<5>\I LB_LAD<21>\I ABSD2_D<18>\I ABSD2_A<4>\I
W28 W28 AB32 AB32 AE31 AE31 AH28 AH28 AL22 AL22
LB_LBE<2>\I LB_LAD<6>\I LB_LAD<2>\I ABSD2_D<25>\I ABSD2_D<0>\I
W29 AE32 AH29 AL23
B LB_LAD<30>\I
W30
W29
W30 AC2 AC2
LB_BTERM\I
AE32 AH29
AH31 AH31
NC
NC
ABSD2_D<3>\I
AL24
AL23
AL24 B
LB_LAD<15>\I FPDP_D<8>\I ABSD2_D<7>\I
W31 W31 AC3 AC3 AF1 AF1 AH32 AH32 NC AL25 AL25
LB_LAD<12>\I FPDP_D<14>\I VC_VID<2>\I ABSD2_D<12>\I
W32 W32 AC4 AC4 AF2 AF2 AL26 AL26
LB_LAD<9>\I FPDP_D<18>\I VC_VID<6>\I ABSD2_DQS<1>\I
AC5 AC5 AF3 AF3 AJ4 AJ4 AL27 AL27
FPDP_D<20>\I VC_VID<10>\I ABSD1_D<5>\I ABSD2_DQS<2>\I
Y1 Y1 AC6 AC6 AF4 AF4 AJ5 AJ5 AL28 AL28
FPDP_D<2>\I FPDP_D<30>\I VC_HSYNC\I ABSD1_D<7>\I ABSD2_D<23>\I
FPDP_D<5>\I AP_TP<12>\I VC_SPARE<3>\I ABSD1_D<13>\I ABSD2_D<28>\I
Y3 Y3 AC8 AC8 AP_HOLDA\I AF6 AF6 AJ7 AJ7 AL30 AL30
FPDP_D<11>\I AP_TP<13>\I ABSD1_D<14>\I ABSD2_D<30>\I
Y4 Y4 AC9 AC9 DGND AF7 AF7 AJ8 AJ8
FPDP_D<17>\I AP_TP<18>\I ABSD1_D<20>\I
Y5 Y5 AC10 AC10 NC AF8 AF8 AJ9 AJ9 AM4 AM4
FPDP_D<23>\I AP_TP<19>\I ABSD1_D<22>\I ABSD1_D<0>\I
FPDP_D<27>\I DGND ABSD1_D<26>\I ABSD1_D<9>\I
Y7 Y7 AC12 AC12 AF10 AF10 AJ11 AJ11 AM6 AM6
FPDP_PIO<1>\I ABSD1_DQM<2>\I R62 DGND ABSD1_DQS<3>\I ABSD1_D<10>\I
AP_TP<6>\I DGND 261 R38 ABSD1_A<12>\I ABSD1_D<17>\I
Y9 Y9 AC14 AC14 DGND AF12 AF12 AJ13 AJ13 ABSD1_RAS\I AM8 AM8
AP_TP<7>\I 261 DGND ABSD1_D<18>\I
Y10 Y10 AC15 AC15 V2.5 AF13 AF13 AJ15 AJ15 AM9 AM9
AP_TP<8>\I ABSD1_A<6>\I DGND ABSD1_D<25>\I
NC Y11 Y11 AC18 AC18 AF14 AF14 AJ16 AJ16 ABSD2_CLK\I AM11 AM11
ABSD1_A<5>\I R250 DGND DGND
NC Y12 Y12 AC19 AC19 ABSD2_WE\I AF20 AF20 AJ17 AJ17 ABREF_SD_CLK\I AM13 AM13
261 DGND ABSD1_BA<1>\I
NC Y21 Y21 AC20 AC20 DGND ABSD2_CKE\I AF21 AF21 AJ18 AJ18 AM14 AM14
ABSD2_A<7>\I DGND
NC Y22 Y22 AC21 AC21 AF22 AF22 AJ19 AJ19 ABSD1_CLK*\I AM16 AM16
DGND DGND DGND
NS_TP<11>\I ABSD2_DQM<2>\I ABSD2_A<5>\I DGND
NS_TP<10>\I ABSD2_DQM<1>\I DGND DGND
NS_TP<9>\I NS_TP<3>\I ABSD2_DQS<0>\I ABSD2_A<0>\I
LB_DEN\I Y26 Y26 AC25 AC25 AF26 AF26 AJ23 AJ23 AM22 AM22
NS_TP<6>\I NS_TP<2>\I ABSD2_D<5>\I DGND
LB_DTR\I Y27 Y27 AC26 AC26 AF27 AF27 AJ24 AJ24 AM24 AM24
AP_BREQI\I LB_DACK<1>\I ABSD2_D<9>\I ABSD2_D<6>\I
LB_LBE<3>\I LB_LINTO\I LB_DACK<0>\I ABSD2_D<14>\I ABSD2_D<11>\I
LB_LAD<29>\I LB_LWR\I LB_LAD<25>\I ABSD2_D<17>\I ABSD2_D<15>\I
A
Y30 AC29 AC29 AF30 AJ27 AJ27 AM27
LB_LAD<16>\I
Y31
Y30
Y31 AC30 AC30
LB_LAD<28>\I LB_LAD<22>\I
AF31
AF30
AF31 AJ28 AJ28
ABSD2_D<21>\I ABSD2_D<19>\I
AM28
AM27
AM28
A
LB_LAD<13>\I LB_LAD<19>\I LB_LAD<1>\I ABSD2_D<24>\I ABSD2_D<22>\I
Y32 Y32 AC31 AC31 LB_BLAST\I AF32 AF32 AJ29 AJ29 AM29 AM29
LB_LAD<8>\I LB_LAD<4>\I ABSD2_D<26>\I ABSD2_D<29>\I AP (AQUISITION PROCESSOR)
PACK_TYPE=FBGA
FORMAT PER PR12001
DGND V2.5 V3.3
V2.5 V3.3
D
SIZE DWG NO. REV
B 00-885794DDW 6
Tue Oct 21 08:39:06 2008 SCALE: N/A SHEET 14 0F 23
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
15
REV
6
1
V1.5
C L207 C410
1
1UH 2
1000P
C13 C96 C62

C411
2.2 2.2 2.2 D
0.01
L202 C286
1
1UH 2
0.01
D
C287
D 1000P
D
L205 C350
U7 1UH 0.01
1 2
EP1S40_1020 EP1S40_1020 EP1S40_1020
SPEED=7 SECTION 8 OF 9 C348 SECTION 9 OF 9
SECTION 7 OF 9 AJ14 VCCSEL 1000P NC L28 FPLL7CLKn
V1.5 NC L29 FPLL7CLKp
A2 GND GNDA_PLL1 T26 NC AB29 FPLL8CLKn
C D
A10 GND GNDG_PLL1 T22 NC AB28 FPLL8CLKp
A23 GND GNDA_PLL2 U26 M12 VCCINT NC AB4 FPLL9CLKn
A31 GND GNDG_PLL2 T24 M14 VCCINT NC AB5 FPLL9CLKp
+
B1 U7
C2 C341 C333 C353 C354 C342 C343 C338 C285 C289 M19 T25 L5
GND GNDA_PLL3 VCCINT VCCA_PLL1 NC FPLL10CLKn
B2 U11
68 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 M21 U25 L4
GND GNDG_PLL3 VCCINT VCCA_PLL2 NC FPLL10CLKp
B31 T7
6.3V N13 U8
GND GNDA_PLL4 VCCINT VCCA_PLL3
B32 GND GNDG_PLL4 U9 N15 VCCINT VCCA_PLL4 T8
H18 F17 N18 G17
V1.5
GND GNDA_PLL5 VCCINT VCCA_PLL5
H24 GND GNDG_PLL5 L16 N20 VCCINT VCCA_PLL6 AG17 C DGND T30 CLK0n
J17 GND GNDA_PLL6 AH17 C31 C296 C294 C295 C422 C94 C11 C226 C224 C12 P12 VCCINT VCCA_PLL7 D31 PXL_CLK\I T29 CLK0p
K1 GND GNDG_PLL6 AB16 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 P14 VCCINT VCCA_PLL8 AJ31 GPTOAP_CLK_SPARE\I T27 CLK1p
K32 GND GNDA_PLL7 D32 P16 VCCINT VCCA_PLL9 AJ2 DGND U32 CLK2n
M13 GND GNDG_PLL7 E30 P17 VCCINT VCCA_PLL10 D2 OSC_40M\I U31 CLK2p
M15 GND GNDA_PLL8 AJ32 P19 VCCINT VCCA_PLL11 E16 DGND U29 CLK3p
M16 GND GNDG_PLL8 AH30 P21 VCCINT VCCA_PLL12 AG16 OSC_66M_B\I AM19 CLK4p
M17 GND GNDA_PLL9 AJ1 R13 VCCINT DGND AK19 CLK5p
M18 AH3
C222 C14 C61 C93 C64 C16 C97 C400 C279 C280 R15
V1.5 DGND AK15
GND GNDG_PLL9 VCCINT CLK6p
0.01 0.01 2.2 2.2 2.2 0.01 0.01 0.01 0.01 0.01 C
C M20
N12
GND
GND
GNDA_PLL10
GNDG_PLL10
D1
E3
16V 16V 16V
R18
R20
VCCINT
VCCINT VCCG_PLL1 R22
ABSDX_REF_CLK\I
DGND
AM15
U4
CLK7p
CLK8p
C
N14 GND GNDA_PLL11 E17 T14 VCCINT VCCG_PLL2 U24 DGND U1 CLK9n
N16 H15 T16 V11
C420 C401 C219 C229 C407 C415 U2
GND GNDG_PLL11 VCCINT VCCG_PLL3 FPDP_RX_CLK\I CLK9p
N17 AH16 T17 T9
0.1 0.1 0.1 0.1 0.01 0.01 T6
GND GNDA_PLL12 VCCINT VCCG_PLL4 VC_PIXCLK\I CLK10p
N19 GND GNDG_PLL12 AE16 C118 C457 C334 C335 C121 C444 C409 C449 C414 C413 T19 VCCINT VCCG_PLL5 J16 DGND T3 CLK11n
N21 GND 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 U14 VCCINT VCCG_PLL6 AD16 OSC_66M_C\I T4 CLK11p
P13 GND U16 VCCINT VCCG_PLL7 D30 ATSDX_REF_CLK\I B15 CLK12p
P15 GND U17 VCCINT VCCG_PLL8 AJ30 D DGND D15 CLK13p
D
P18 GND U19 VCCINT VCCG_PLL9 AJ3 OSC_66M_A\I A19 CLK14p
P20 GND D V13 VCCINT VCCG_PLL10 D3 C19 CLK15p
DGND
R14 GND V3.3 V15 VCCINT VCCG_PLL11 H16
R16 GND V18 VCCINT VCCG_PLL12 AF16
R17 GND V20 VCCINT V2.5
R19 W14
V1.5 MSEL0 AG18
GND C228 C288 C344 C227 VCCINT MSEL0
T12 GND 2.2 0.01 0.01 0.01 W16 VCCINT C MSEL1 AE18 MSEL1
T13 GND 16V W17 VCCINT VCC_PLL5_OUTA H17 MSEL2 AE19 MSEL2
T15 GND W19 VCCINT VCC_PLL5_OUTB L17
T18 Y13 AE17
C345 C347 C339 C63
GND VCCINT VCC_PLL6_OUTA
T20 Y15 AB17
0.01 0.01 0.01 0.01 D
GND VCCINT VCC_PLL6_OUTB
T21
C405 C223 C221 C416 Y18 E14
GND VCCINT DATAO\I DATA0
U12
2.2 0.01 0.01 0.01 Y20 G18
GND VCCINT CONFIG_DONE\I CONF_DONE
U13
16V E19
GND DCLK\I DKLK
U15 GND VREF0B1 V21 D NCE\I AF18 nCE
V2.5
U18 GND V2.5 VREF0B2 F27 NCEO\I AH15 nCEO
U20 GND U23 VCCIO1 VREF0B3 E21 NCONFIG\I J18 nCONFIG
B U21
V14
GND
GND C293 C340 C346 C337
AA32
AK31
VCCIO1
VCCIO1
VREF0B4
VREF0B5
E6
R12
R24
1K
NSTATUS\I G16 nSTATUS
B
V16 GND 2.2 0.01 0.01 0.01 AK32 VCCIO1 VREF0B6 AG6
1 2
V17 GND 16V C31 VCCIO2 VREF0B7 AH12
V19 C32 AH27
L203 D16
GND VCCIO2 VREF0B8 TDI\I TDI
W13 M32 AA23
1UH R206 C17 F16
GND VCCIO2 VREF1B1 TDO\I TDO
W15 T23 L25
1K 0.01 E15
GND VCCIO2 VREF1B2 TMS\I TMS
W18
C402 C404 C284 C283 A21 E23 G14
GND VCCIO3 VREF1B3 TCK\I TCK
W20
2.2 0.01 0.01 0.01 A30 E8 G15
GND VCCIO3 VREF1B4 TRST\I TRST
Y14
16V K17 L8
GND VCCIO3 VREF1B5
Y16 GND A12 VCCIO4 VREF1B6 AB8 D
Y17 GND V3.3 A3 VCCIO4 VREF1B7 AH10
Y19 GND K16 VCCIO4 VREF1B8 AH25 AVREF2_1.25V\I F18 TEMPDIODEn
AA16 GND C1 VCCIO5 VREF2B1 AB25 E18 TEMPDIODEp
AA17 C2 R21
C33 C403 C336 C282
GND C417 C225 C412 C408 VCCIO5 VREF2B2
AC1 M1 E25
2.2 0.01 0.01 0.01
GND 2.2 0.01 0.01 0.01 VCCIO5 VREF2B3
AC32 GND 16V T10 VCCIO5 VREF2B4 E10 AVREF1_1.25V\I V2.5
AD17 GND U10 VCCIO6 VREF2B5 F6 AF15 nI/O_PULLUP
AF17 AA1 AA10
R61 AG15
GND VCCIO6 VREF2B6 PORSEL
AL1 AK1 AH8 V2.5 10K AF19
GND VCCIO6 VREF2B7 D PLL_ENA
AL2
C220 C406 C278 C32 AK2 AH23
GND VCCIO6 VREF2B8
AL31
2.2 0.01 0.01 0.01 AC16 AG27
GND VCCIO7 VREF3B1
AL32
16V AM12 E27 D
GND VCCIO7 VREF3B3 R97
AM10 GND AM3 VCCIO7 VREF3B4 E12 1K
AM2 GND AC17 VCCIO8 VREF3B6 V12
V2.5
AM23 GND AM21 VCCIO8 VREF3B7 AH6 1 2
A AM31 GND AM30 VCCIO8 VREF3B8 AH21 L209

A
1UH
C419 C290 C291 C349
PACK_TYPE=FBGA R95 C458
2.2 0.01 0.01 0.01
D 1K 0.01
D 16V
AP (AQUISITION PROCESSOR)
FORMAT PER PR12001
C116 C352 C351 C292

2.2 0.01 0.01 0.01 LOWER LEVEL (3 OF 3)
C281 C418 C421 C95

2.2 0.01 0.01 0.01 GE HEALTHCARE - SURGERY
SIZE DWG NO. REV
D
B 00-885794DDW 6
D
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
16
REV
6
1
U8
EP1S60_1020 EP1S60_1020 EP1S60_1020
SECTION 1 OF 9 CINE_VDRV\I G1 G1
CINE_D_OE\I G2 G2
CINE_TAG\I G3 G3 N1 N1
CINE_D<3>\I
G4 G4 N2 N2
DGND CINE_D<9>\I
G5 G5 N3 N3
AP_CINE_VID<8>\I
G6 G6 N4 N4
AP_CINE_VID<9>\I
NC G7 G7 N5 N5
AP_CINE_VID<10>\I
NC G8 G8 N6 N6
D GTSD1_D<0>\I
A4 A4 DGND
G9 G9
DGND
N7 N7 D
A5 A5 G10 G10 N8 N8
GTSD1_D<8>\I DGND
A6 A6 NC G11 G11 N9 N9
GTSD1_D<10>\I R220
A7 A7 G12 G12 K2 K2 N10 N10
GTSD1_DQS<2>\I 261 DGND CINE_D<6>\I APTOGP_SPARE<0>\I
A8 A8 V2.5 G13 G13 K3 K3 NC N11 N11
GTSD1_D<16>\I DGND
A9 A9 G19 G19 K4 K4 NC N22 N22
GTSD1_D<24>\I GTSD2_A<9>\I
A11 A11 G20 G20 K5 K5 N23 N23
GTSD1_A<13>\I GTSD2_A<10>\I DGND
A13 A13 G21 G21 K6 K6 N24 N24
GTSD1_A<0>\I DGND
A14 A14 D4 D4 G22 G22 K7 K7 N25 N25
DGND GTSD1_D<5>\I
A15 A15 D5 D5 GTSD2_A<13>\I G23 G23 K8 K8 N26 N26
DGND GTSD1_D<6>\I
GTSD1_CLK*\I A16 A16 D6 D6 G24 G24 K9 K9 N27 N27
GTSD1_D<13>\I DGND
GTSD2_CLK*\I A17 A17 D7 D7 NC G25 G25 K10 K10 NC N28 N28
GTSD1_D<14>\I
A18 A18 D8 D8 NC G26 G26 K11 K11 N29 N29
DGND GTSD1_D<20>\I DGND
A20 A20 D9 D9 G27 G27 K12 K12 N30 N30
GTSD2_A<0>\I GTSD1_D<22>\I GP_ERR_LED\I
A22 A22 D10 D10 G28 G28 K13 K13 N31 N31
DGND GTSD1_D<28>\I GP_TP<17>\I
A24 A24 D11 D11 G29 G29 K14 K14 GTSD1_RAS\I N32 N32
GTSD2_D<6>\I GTSD1_DQS<3>\I GP_TP<13>\I
A25 A25 D12 D12 G30 G30 K15 K15 GTSD1_CAS\I
GTSD2_D<11>\I GTSD1_A<6>\I GP_TP<10>\I
A26 A26 D13 D13 G31 G31 K18 K18 P1 P1
GTSD2_D<15>\I GTSD1_A<3>\I GP_TP<7>\I GTSD2_BA<1>\I AP_CINE_SYNC<0>\I
A27 A27 D14 D14 G32 G32 K19 K19 GTSD2_CAS\I P2 P2
GTSD2_D<19>\I DGND GP_TP<3>\I AP_CINE_SYNC<1>\I
A28 A28 D17 D17 K20 K20 GTSD2_RAS\I P3 P3
GTSD2_D<22>\I AP_CINE_SYNC<2>\I
A29 A29 D18 D18 H1 H1 K21 K21 GPTOAP_CINE_OE\I P4 P4
GTSD2_D<26>\I CINE_D<0>\I DGND
D19 D19 H2 H2 K22 K22 P5 P5
CINE_D<4>\I AP_CINE_VID<7>\I
B3 B3 D20 D20 GTSD2_A<6>\I H3 H3 K23 K23 P6 P6
B4 B4 D21 D21 GTSD2_CS\I H4 H4 K24 K24 AP_SW_RST\I P7 P7
GTSD1_D<2>\I DGND
B5 B5 D22 D22 H5 H5 K25 K25 APTOGP_SPARE<3>\I P8 P8
GTSD1_D<9>\I GTSD2_DQS<0>\I
B6 B6 D23 D23 H6 H6 K26 K26 P9 P9
C GTSD1_D<11>\I
GTSD1_D<18>\I
B7 B7 D24 D24
GTSD2_D<5>\I
GTSD2_D<9>\I
H7 H7 K27 K27 VTM_SCL\I
APTOGP_SPARE<2>\I
APTOGP_SPARE<1>\I
P10 P10 C
B8 B8 D25 D25 H8 H8 K28 K28 NC P11 P11
GTSD1_D<17>\I GTSD2_D<14>\I DGND
B9 B9 D26 D26 H9 H9 K29 K29 NC P22 P22
GTSD1_D<25>\I GTSD2_D<17>\I GP_TP<16>\I
B10 B10 D27 D27 NC H10 H10 K30 K30 P23 P23
GTSD1_D<26>\I GTSD2_D<21>\I GPTOAP_SPARE<3>\I DGND
B11 B11 D28 D28 H11 H11 K31 K31 P24 P24
GTSD1_D<30>\I GTSD2_D<24>\I DGND GPTOAP_SPARE<0>\I
B12 B12 D29 D29 H12 H12 P25 P25
DGND GTSD2_D<29>\I DGND
B13 B13 H13 H13 L1 L1 P26 P26
GTSD1_A<1>\I GTSD1_A<12>\I CINE_D<2>\I
B14 B14 E1 E1 NC H14 H14 L2 L2 P27 P27
GTSD1_A<4>\I GTSD1_BA<0>\I CINE_D<7>\I
GTSD1_CLK\I B16 B16 E2 E2 NC H19 H19 L3 L3 P28 P28
GTSD2_A<11>\I DGND
GTSD2_CLK\I B17 B17 E4 E4 NC H20 H20 L6 L6 P29 P29
GTSD2_A<12>\I
GTREF_SD_CLK\I B18 B18 E5 E5 H21 H21 L7 L7 P30 P30
GTSD1_D<7>\I DGND
B19 B19 E7 E7 H22 H22 L9 L9 APGP_CTL_SCNTL<1>\I P31 P31
DGND GTSD1_DQS<1>\I
B20 B20 E9 E9 H23 H23 L10 L10 NC APGP_CTL_SCNTL<0>\I P32 P32
GTSD2_A<1>\I GTSD1_D<23>\I
B21 B21 E11 E11 H25 H25 L11 L11
GTSD2_A<4>\I GTSD1_D<29>\I DGND R50
B22 B22 E13 E13 H26 H26 L12 L12 R1 R1
GTSD2_D<0>\I GTSD1_A<8>\I DGND 10K AP_CINE_VID<0>\I
B23 B23 E20 E20 H27 H27 L13 L13 V2.5 R2 R2
GTSD2_D<3>\I GTSD2_A<3>\I AP_CINE_VID<1>\I
B24 B24 E22 E22 H28 H28 L14 L14 GTSD1_CKE\I R3 R3
GTSD2_D<7>\I GTSD2_D<2>\I GP_TP<18>\I AP_CINE_VID<2>\I
B25 B25 E24 E24 H29 H29 L15 L15 GTSD1_WE\I R4 R4
GTSD2_D<12>\I GTSD2_D<10>\I GP_TP<14>\I R72 AP_CINE_VID<3>\I
B26 B26 E26 E26 H30 H30 L18 L18 GTSD2_WE\I R5 R5
GTSD2_DQS<1>\I GTSD2_D<18>\I GP_TP<11>\I 261 AP_CINE_VID<6>\I
B27 B27 E28 E28 H31 H31 L19 L19 DGND CINE_CLK_BUF_OE\I R6 R6
GTSD2_DQS<2>\I GTSD2_D<25>\I GP_TP<8>\I
B28 B28 E29 E29 NC H32 H32 L20 L20 RST_DISABLE R7 R7
GTSD2_D<23>\I GP_TP<4>\I DGND DGND
B29 B29 E31 E31 NC L21 L21 GP_INTR\I R8 R8
GTSD2_D<27>\I
B30 B30 E32 E32 NC J1 J1 L22 L22 R9 R9
J2 J2 L23 L23 R10 R10
CINE_D<5>\I DGND
C3 C3 F1 F1 CINE_PIXCLK\I J3 J3 L24 L24 GTSD2_CKE\I NC R11 R11
GTSD1_D<3>\I CINE_D<11>\I
C4 C4 F2 F2 CINE_HDRV\I J4 J4 L26 L26 R23 R23
B GTSD1_D<4>\I
GTSD1_DQS<0>\I
C5 C5 F3 F3 NC
DGND
J5 J5 L27 L27
DGND
VTM_SDA\I
DGND
R24 R24 B
C6 C6 F4 F4 NC J6 J6 L30 L30 R25 R25
GTSD1_D<12>\I GPTOAP_SPARE<2>\I
C7 C7 F5 F5 NC J7 J7 L31 L31 R26 R26
GTSD1_D<15>\I GPTOAP_SPARE<1>\I
C8 C8 F7 F7 J8 J8 L32 L32 R27 R27
GTSD1_D<19>\I GTSD1_DQM<0>\I GPTOAP_CLK_SPARE\I
C9 C9 F8 F8 J9 J9 R28 R28
GTSD1_D<21>\I GTSD1_DQM<1>\I
C10 C10 F9 F9 NC J10 J10 M2 M2 R29 R29
GTSD1_D<27>\I GTSD1_DQM<2>\I CINE_D<8>\I R49
C11 C11 F10 F10 J11 J11 M3 M3 R30 R30
GTSD1_D<31>\I GTSD1_DQM<3>\I R221 DGND AP_CINE_VID<11>\I 261 APGP_CTL_AD<30>\I
C12 C12 F11 F11 NC J12 J12 M4 M4 DGND R31 R31
DGND 261 DGND APGP_CTL_AD<29>\I
C13 C13 F12 F12 DGND J13 J13 M5 M5 V3.3 R32 R32
GTSD1_A<2>\I DGND APGP_CTL_AD<31>\I
C14 C14 F13 F13 J14 J14 M6 M6 R222
GTSD1_A<5>\I GTSD1_A<9>\I GTSD1_BA<1>\I DGND
C15 C15 F14 F14 GTSD1_CS\I J15 J15 M7 M7 261 T1 T1
DGND GTSD1_A<10>\I AP_CINE_VID<4>\I
C16 C16 F15 F15 J19 J19 M8 M8 T2 T2
GTSD1_A<7>\I GTSD1_A<11>\I GTSD2_BA<0>\I AP_CINE_VID<5>\I
C17 C17 F19 F19 J20 J20 M9 M9 T5 T5
DGND GTSD2_A<7>\I R240 DGND DGND
C18 C18 F20 F20 J21 J21 M10 M10 NC T11 T11
DGND GTSD2_A<8>\I 261
C20 C20 F21 F21 V2.5 J22 J22 M11 M11 NC T28 T28
GTSD2_A<2>\I DGND
C21 C21 F22 F22 J23 J23 M22 M22 NC T31 T31
GTSD2_A<5>\I DGND APGP_CTL_AD<28>\I
C22 C22 F23 F23 J24 J24 M23 M23 NC T32 T32
GTSD2_D<1>\I GTSD2_DQM<0>\I APGP_CTL_AD<27>\I
C23 C23 F24 F24 J25 J25 M24 M24
GTSD2_D<4>\I GTSD2_DQM<1>\I DGND
C24 C24 F25 F25 J26 J26 M25 M25 U3 U3
GTSD2_D<8>\I GTSD2_DQM<2>\I DGND
C25 C25 F26 F26 VTM_INT\I J27 J27 M26 M26 U5 U5
GTSD2_D<13>\I GTSD2_DQM<3>\I R109
C26 C26 F28 F28 NC J28 J28 M27 M27 U6 U6
GTSD2_D<16>\I GP_TP<19>\I 261
C27 C27 F29 F29 NC J29 J29 M28 M28 V3.3 NC U22 U22
GTSD2_D<20>\I GP_TP<15>\I
C28 C28 F30 F30 NC J30 J30 M29 M29 DGND U27 U27
GTSD2_DQS<3>\I GP_TP<12>\I APGP_CTL_AD<17>\I
C29 C29 F31 F31 J31 J31 M30 M30 R276 U28 U28
GTSD2_D<28>\I GP_TP<6>\I GP_TP<9>\I DGND APGP_CTL_AD<13>\I
C30 C30 F32 F32 J32 J32 M31 M31 261 U30 U30
GTSD2_D<31>\I GP_TP<2>\I GP_TP<5>\I GP_COMP_FAULT\I DGND
A PACK_TYPE=FBGA A
GP (GDRM PROCESSOR)
FORMAT PER PR12001
DGND V2.5 V3.3 LOWER LEVEL (1 OF 3)

D
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
17
REV
6
1
U8
EP1S60_1020 EP1S60_1020 EP1S60_1020
SECTION 4 OF 9 AD1 AD1
AP_VID<3>\I
AD2 AD2
AP_VID<7>\I
AD3 AD3
AP_VID<13>\I
AD4 AD4
DGND
AD5 AD5
AD6 AD6
AD7 AD7
D AA2
AA3
AA2
AA3
AP_SYNC<1>\I
AD8
AD9
AD8
AD9
D
DGND
AA4 AA4 NC AD10 AD10
AA5 AA5 NC AD11 AD11
GBSD1_DQM<3>\I GBSD1_D<3>\I
DGND GBSD1_D<4>\I
DGND GBSD1_DQS<0>\I
GBSD1_A<4>\I GBSD1_D<12>\I
AA11 AA11 NC AD18 AD18 AG1 AG1 AK7 AK7
GBSD1_A<3>\I AP_VID<0>\I GBSD1_D<15>\I
BRD_ID<0>\I GBSD1_DQM<0>\I GBSD2_BA<1>\I AP_VID<10>\I GBSD1_DQS<2>\I
V2 V2 AA13 AA13 NC AD20 AD20 AG3 AG3 AK9 AK9
BRD_ID<2>\I GBSD2_BA<0>\I DGND GBSD1_D<21>\I
DGND GBSD1_A<11>\I DGND DGND GBSD1_D<27>\I
GBSD1_A<10>\I GBSD1_D<30>\I
GBSD1_A<9>\I DGND
V6 V6 AA19 AA19 GBSD2_CAS\I AD24 AD24 AG8 AG8 NC GBSD1_WE\I AK13 AK13
DGND DGND GBSD1_A<1>\I
V8 V8 AA21 AA21 AD26 AD26 AG10 AG10 GBSD2_CLK*\I AK16 AK16
DGND DGND
V9 V9 AA22 AA22 NC AD27 AD27 AG11 AG11 GBSD1_CKE\I AK17 AK17
DGND
V10 V10 AA24 AA24 LB_LRESET\I AD28 AD28 AG12 AG12 AK18 AK18
DGND GBSD2_A<6>\I
NC V22 V22 AA25 AA25 AD29 AD29 AG13 AG13 AK20 AK20
APGP_CTL_BE<0>\I GP_VID<12>\I GBSD2_A<2>\I
V23 V23 AA26 AA26 R108 AD30 AD30 AG14 AG14 GBSD2_CS\I AK21 AK21
DGND APGP_CTL_BE<1>\I GP_VID<13>\I
V24 V24 AA27 AA27 261 AD31 AD31 AG19 AG19 AK22 AK22
DGND APGP_CTL_BE<2>\I GP_VID<14>\I GBSD2_A<11>\I GBSD2_D<1>\I
V25 V25 AA28 AA28 V3.3 AD32 AD32 AG20 AG20 AK23 AK23
APGP_CTL_AD<24>\I GP_VID<15>\I GBSD2_A<9>\I GBSD2_D<4>\I
V26 V26 AA29 AA29 DGND AG21 AG21 AK24 AK24
APGP_CTL_AD<21>\I GBSD2_A<10>\I GBSD2_D<8>\I
V27 V27 AA30 AA30 R107 AE1 AE1 AG22 AG22 AK25 AK25
APGP_CTL_AD<18>\I APGP_CTL_BE<3>\I AP_VID<2>\I DGND GBSD2_D<13>\I
V28 V28 AA31 AA31 261 AE2 AE2 AG23 AG23 AK26 AK26
APGP_CTL_AD<14>\I APGP_CTL_AD<6>\I AP_VID<8>\I DGND GBSD2_D<16>\I
C APGP_CTL_AD<10>\I
V29
V30
V29
V30 AB1 AB1
AP_VID<14>\I
AE3
AE4
AE3
AE4
AG24
AG25
AG24
AG25 NC
GBSD2_DQM<0>\I GBSD2_D<20>\I
AK27
AK28
AK27
AK28
C
APGP_CTL_AD<7>\I AP_VID<4>\I DGND GBSD2_DQS<3>\I
APGP_CTL_AD<3>\I AP_VID<5>\I GBSD2_D<27>\I
APGP_CTL_AD<0>\I AP_VID<11>\I GBSD2_D<31>\I
AB6 AB6 AE7 AE7 AG29 AG29
DGND GP_VID<0>\I
W1 W1 AB7 AB7 AE8 AE8 AG30 AG30 AL3 AL3
BRD_ID<1>\I DGND GP_VID<1>\I GBSD1_D<1>\I
W2 W2 AB9 AB9 NC AE9 AE9 AG31 AG31 AL4 AL4
BRD_ID<3>\I GP_VID<2>\I GBSD1_D<2>\I
W3 W3 AB10 AB10 NC NC AE10 AE10 AG32 AG32 AL5 AL5
DGND GP_VID<3>\I GBSD1_D<8>\I
W4 W4 AB11 AB11 AE11 AE11 AL6 AL6
GBSD1_DQM<1>\I DGND GBSD1_D<11>\I
W5 W5 AB12 AB12 NC AE12 AE12 AH1 AH1 NC AL7 AL7
GBSD1_D<16>\I
W6 W6 AB13 AB13 AE13 AE13 AH2 AH2 NC AL8 AL8
DGND R224 GBSD1_D<19>\I
W7 W7 AB14 AB14 GBSD1_A<2>\I AE14 AE14 AH4 AH4 NC AL9 AL9
GBSD1_A<7>\I 10K GBSD1_D<24>\I
W8 W8 AB15 AB15 V2.5 INIT_DONE\I AE15 AE15 AH5 AH5 AL10 AL10
GBSD1_A<8>\I GBSD1_D<6>\I GBSD1_D<28>\I
W9 W9 AB18 AB18 GBSD1_CS\I AE20 AE20 AH7 AH7 AL11 AL11
GBSD2_A<12>\I GBSD1_DQS<1>\I GBSD1_D<31>\I
W10 W10 AB19 AB19 GBSD2_RAS\I AE21 AE21 AH9 AH9 AL12 AL12
DGND GBSD1_D<23>\I DGND
NC W11 W11 AB20 AB20 NC AE22 AE22 AH11 AH11 AL13 AL13
DGND GBSD1_D<29>\I R223 GBSD1_BA<0>\I
NC W12 W12 AB21 AB21 AE23 AE23 AH13 AH13 GBSD1_CAS\I AL14 AL14
DGND 10K GBSD1_A<0>\I
NC W21 W21 AB22 AB22 AE24 AE24 AH14 AH14 DEV_CLR* V2.5 AL15 AL15
GBSD2_A<13>\I GBSD2_DQM<3>\I GBSD1_A<13>\I
NC W22 W22 AB23 AB23 NC AE25 AE25 AH18 AH18 GBSD1_CLK\I AL16 AL16
DGND GBSD2_A<8>\I
W23 W23 AB24 AB24 AE26 AE26 AH19 AH19 V2.5 AL17 AL17
DGND DGND DGND
W24 W24 AB26 AB26 AE27 AE27 AH20 AH20 R241 AL18 AL18
DGND GBSD2_A<3>\I
W25 W25 AB27 AB27 AE28 AE28 AH22 AH22 261 AL19 AL19
APGP_CTL_AD<25>\I GBSD2_D<2>\I
W26 W26 AB30 AB30 APGP_CTL_MCNTL<0>\I AE29 AE29 AH24 AH24 AL20 AL20
APGP_CTL_AD<22>\I GP_VID<8>\I GBSD2_D<10>\I GBSD2_A<1>\I
APGP_CTL_AD<19>\I GP_VID<9>\I GBSD2_D<18>\I GBSD2_A<4>\I
APGP_CTL_AD<15>\I GP_VID<10>\I GBSD2_D<25>\I GBSD2_D<0>\I
W29 W29 AE32 AE32 AH29 AH29 NC AL23 AL23
APGP_CTL_AD<11>\I GP_VID<11>\I GBSD2_D<3>\I
B APGP_CTL_AD<8>\I
W30
W31
W30
W31
AC2
AC3
AC2
AC3
AP_VID<6>\I
AF1 AF1
AH31
AH32
AH31
AH32
NC
NC
GBSD2_D<7>\I
AL24
AL25
AL24
AL25
B
APGP_CTL_AD<4>\I AP_VID<12>\I AP_VID<1>\I GBSD2_D<12>\I
W32 W32 AC4 AC4 AF2 AF2 AL26 AL26
APGP_CTL_AD<1>\I DGND AP_VID<9>\I GBSD2_DQS<1>\I
AC5 AC5 AF3 AF3 AJ4 AJ4 AL27 AL27
AP_VID<15>\I GBSD1_D<5>\I GBSD2_DQS<2>\I
AP_SYNC<2>\I DGND GBSD1_D<7>\I GBSD2_D<23>\I
AP_SYNC<0>\I GBSD1_D<13>\I GBSD2_D<28>\I
DGND GBSD1_D<14>\I GBSD2_D<30>\I
Y4 Y4 AC9 AC9 AF7 AF7 AJ8 AJ8
GBSD1_D<20>\I
GBSD1_D<22>\I GBSD1_D<0>\I
GBSD1_DQM<2>\I R47 GBSD1_DQS<3>\I GBSD1_D<10>\I
Y8 Y8 AC13 AC13 R48 NC AF11 AF11 AJ12 AJ12 AM7 AM7
DGND 261 GBSD1_A<12>\I GBSD1_D<17>\I
Y9 Y9 AC14 AC14 DGND 261 AF12 AF12 AJ13 AJ13 GBSD1_RAS\I AM8 AM8
DGND GBSD1_D<18>\I
Y10 Y10 AC15 AC15 V2.5 AF13 AF13 AJ15 AJ15 AM9 AM9
GBSD1_A<6>\I DGND GBSD1_D<25>\I
NC Y11 Y11 AC18 AC18 AF14 AF14 AJ16 AJ16 AM11 AM11
GBSD1_A<5>\I R70 DGND GBSD2_CLK\I DGND
NC Y12 Y12 AC19 AC19 GBSD2_WE\I AF20 AF20 AJ17 AJ17 AM13 AM13
261 DGND GBREF_SD_CLK\I GBSD1_BA<1>\I
NC Y21 Y21 AC20 AC20 DGND GBSD2_CKE\I AF21 AF21 AJ18 AJ18 AM14 AM14
GBSD2_A<7>\I DGND
NC Y22 Y22 AC21 AC21 AF22 AF22 AJ19 AJ19 GBSD1_CLK*\I AM16 AM16
DGND DGND DGND
DGND GBSD2_DQM<2>\I GBSD2_A<5>\I DGND
DGND GBSD2_DQM<1>\I DGND DGND
APGP_CTL_AD<26>\I DGND GBSD2_DQS<0>\I GBSD2_A<0>\I
APGP_CTL_AD<23>\I GBSD2_D<5>\I DGND
APGP_CTL_AD<20>\I GBSD2_D<9>\I GBSD2_D<6>\I
APGP_CTL_AD<16>\I GBSD2_D<14>\I GBSD2_D<11>\I
APGP_CTL_AD<12>\I GP_VID<4>\I GBSD2_D<17>\I GBSD2_D<15>\I
APGP_CTL_AD<9>\I GP_SYNC<0>\I GP_VID<5>\I GBSD2_D<21>\I GBSD2_D<19>\I
A APGP_CTL_AD<5>\I
Y31
Y32
Y31 AC30 AC30
AC31
GP_SYNC<1>\I GP_VID<6>\I
AF31
AF32
AF31 AJ28 AJ28
AJ29
AM28
AM29
AM28 A
APGP_CTL_AD<2>\I Y32 AC31 GP_SYNC<2>\I GP_VID<7>\I AF32 AJ29 GBSD2_D<26>\I GBSD2_D<29>\I AM29
PACK_TYPE=FBGA
GP (GDRM PROCESSOR)
FORMAT PER PR12001
DGND V2.5 V3.3

D
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
18
REV
6
1
V1.5
L206 C379
C 1UH 1000P
1 2
C137 C19 C76

C380
2.2 2.2 2.2 D
0.01
L201 C257
1
1UH 2
1000P
D
C256
0.01
D D
U8 L204 C317
1
1UH 2
1000P
EP1S60_1020 EP1S60_1020 EP1S60_1020
AJ14
C319 L28
SECTION 7 OF 9 VCCSEL NC FPLL7CLKn
0.01 L29
V1.5 NC FPLL7CLKp
A2 GND GNDA_PLL1 T26 NC AB29 FPLL8CLKn
C D
A10 GND GNDG_PLL1 T22 NC AB28 FPLL8CLKp
A23 GND GNDA_PLL2 U26 M12 VCCINT NC AB4 FPLL9CLKn
A31 GND GNDG_PLL2 T24 C384 C376 C254 C260 C249 C248 C304 C303 M14 VCCINT V1.5 NC AB5 FPLL9CLKp
B1 U7
C307 M19 T25 L5
GND GNDA_PLL3 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 VCCINT VCCA_PLL1 C NC FPLL10CLKn
B2 U11
0.01 M21 U25 L4
GND GNDG_PLL3 VCCINT VCCA_PLL2 NC FPLL10CLKp
B31 GND GNDA_PLL4 T7 N13 VCCINT VCCA_PLL3 U8
B32 GND GNDG_PLL4 U9 N15 VCCINT VCCA_PLL4 T8
H18 GND GNDA_PLL5 F17 N18 VCCINT VCCA_PLL5 G17
H24 GND GNDG_PLL5 L16 N20 VCCINT VCCA_PLL6 AG17 DGND T30 CLK0n
J17 GND GNDA_PLL6 AH17 C322 C265 C266 C382 C428 C138 C427 C208 P12 VCCINT VCCA_PLL7 D31 PXL_CLK\I T29 CLK0p
K1 AB16
C321 P14 AJ31 DGND T27
GND GNDG_PLL6 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 VCCINT VCCA_PLL8 CLK1p
K32 D32
0.01 P16 AJ2 DGND U32
GND GNDA_PLL7 VCCINT VCCA_PLL9 CLK2n
M13 GND GNDG_PLL7 E30 P17 VCCINT VCCA_PLL10 D2 OSC_40M\I U31 CLK2p
M15 GND GNDA_PLL8 AJ32 P19 VCCINT VCCA_PLL11 E16 DGND U29 CLK3p
M16 GND GNDG_PLL8 AH30 P21 VCCINT VCCA_PLL12 AG16 OSC_66M_B\I AM19 CLK4p
M17 GND GNDA_PLL9 AJ1 R13 VCCINT DGND AK19 CLK5p
M18 AH3 R15
V1.5 DGND AK15
GND GNDG_PLL9 C77 C74 C108 C210 C209 C109 C45 C18 VCCINT CLK6p
M20 D1
C207 R18 C AM15
GND GNDA_PLL10 2.2 2.2 2.2 0.01 0.01 0.01 0.01 0.01 VCCINT GBSDX_REF_CLK\I CLK7p
N12 E3
0.01 R20 R22 U4
C N14
GND
GND
GNDG_PLL10
GNDA_PLL11 E17 T14
VCCINT
VCCINT
VCCG_PLL1
VCCG_PLL2 U24 C213 C247 C370 C390
DGND
U1
CLK8p
CLK9n
C
N16 H15 T16 V11
C314 C316 C311 C312 C310 U2
GND GNDG_PLL11 VCCINT VCCG_PLL3 0.1 0.1 0.1 0.1 CLK9p
N17 AH16 T17 T9
0.01 0.01 0.01 0.01 0.01 T6
GND GNDA_PLL12 VCCINT VCCG_PLL4 CLK10p
N19 GND GNDG_PLL12 AE16 T19 VCCINT VCCG_PLL5 J16 T3 CLK11n
N21 GND C75 C323 C47 C245 C78 C302 C44 C268 C107 U14 VCCINT VCCG_PLL6 AD16 OSC_66M_C\I T4 CLK11p
P13 GND 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 U16 VCCINT VCCG_PLL7 D30 GTSDX_REF_CLK\I B15 CLK12p
P15 GND D U17 VCCINT VCCG_PLL8 AJ30 D D15 CLK13p
DGND
P18 GND U19 VCCINT VCCG_PLL9 AJ3 OSC_66M_A\I A19 CLK14p
P20 GND V13 VCCINT VCCG_PLL10 D3 C19 CLK15p
V3.3 DGND
R14 GND V15 VCCINT VCCG_PLL11 H16
D V2.5
R16 GND V18 VCCINT VCCG_PLL12 AF16
R17 GND C205 C258 C313 C255 V20 VCCINT
R19 GND 2.2 0.01 0.01 0.01 W14 VCCINT MSEL0 AG18 MSEL0
V2.5
T12 GND W16 VCCINT MSEL1 AE18 MSEL1
T13 GND W17 VCCINT VCC_PLL5_OUTA H17 MSEL2 AE19 MSEL2
T15 GND W19 VCCINT VCC_PLL5_OUTB L17
T18 Y13 AE17
C315 C309 C308 C252
GND VCCINT VCC_PLL6_OUTA
T20
C212 C206 C259 C211 Y15 AB17
0.01 0.01 0.01 0.01 D
GND VCCINT VCC_PLL6_OUTB
T21
2.2 0.01 0.01 0.01 Y18 E14
GND VCCINT DATAO\I DATA0
U12 GND Y20 VCCINT CONFIG_DONE\I G18 CONF_DONE
U13 GND DCLK\I E19 DKLK
D
U15 GND VREF0B1 V21 NCE\I AF18 nCE
V2.5
U18 GND VREF0B2 F27 V2.5 NCEO\I AH15 nCEO
U20 GND U23 VCCIO1 VREF0B3 E21 NCONFIG\I J18 nCONFIG
U21 GND C250 C306 C253 C262 AA32 VCCIO1 VREF0B4 E6 NSTATUS\I G16 nSTATUS
V14 AK31 R12
R31
B V16
GND
GND
2.2 0.01 0.01 0.01
AK32
VCCIO1
VCCIO1
VREF0B5
VREF0B6 AG6
1K B
V17 GND C31 VCCIO2 VREF0B7 AH12 1 2
V19 GND C32 VCCIO2 VREF0B8 AH27 L200 TDI\I D16 TDI
W13 M32 AA23
C204 R32 F16
GND VCCIO2 VREF1B1 1UH TDO\I TDO
W15
C264 C261 C387 C369 T23 L25
0.01 1K E15
GND VCCIO2 VREF1B2 TMS\I TMS
W18
2.2 0.01 0.01 0.01 A21 E23 G14
GND VCCIO3 VREF1B3 TCK\I TCK
W20 GND A30 VCCIO3 VREF1B4 E8 TRST\I G15 TRST
Y14 GND K17 VCCIO3 VREF1B5 L8
D
Y16 GND A12 VCCIO4 VREF1B6 AB8
Y17 GND V3.3 A3 VCCIO4 VREF1B7 AH10 GVREF2_1.25V\I
Y19 GND K16 VCCIO4 VREF1B8 AH25 VTM_TEMPGP_N\I F18 TEMPDIODEn
AA16 C1 AB25
C21 C372 C251 C305 E18
GND VCCIO5 VREF2B1 VTM_TEMPGP_P\I TEMPDIODEp
AA17
C374 C375 C378 C385 C2 R21
2.2 0.01 0.01 0.01 V2.5
GND VCCIO5 VREF2B2
AC1
2.2 0.01 0.01 0.01 M1 E25
GND VCCIO5 VREF2B3
AC32 GND T10 VCCIO5 VREF2B4 E10 R71
AD17 GND U10 VCCIO6 VREF2B5 F6 GVREF1_1.25V\I 10K AF15 nI/O_PULLUP
AF17 GND AA1 VCCIO6 VREF2B6 AA10 AG15 PORSEL
AL1 GND C386 C381 C246 C383 AK1 VCCIO6 VREF2B7 AH8 D AF19 PLL_ENA
AL2 GND 2.2 0.01 0.01 0.01 AK2 VCCIO6 VREF2B8 AH23 V2.5
AL31 GND AC16 VCCIO7 VREF3B1 AG27
AL32 GND AM12 VCCIO7 VREF3B3 E27 D
AM10 GND AM3 VCCIO7 VREF3B4 E12 R106
AM2 GND AC17 VCCIO8 VREF3B6 V12 1K
V2.5
AM23 GND AM21 VCCIO8 VREF3B7 AH6
AM31 GND AM30 VCCIO8 VREF3B8 AH21 1 2
A PACK_TYPE=FBGA
C389
2.2
C373
0.01
C318
0.01
C110
0.01
L208
1UH
A
D R105
C429
1K
D 0.01
GP (GDRM PROCESSOR)
FORMAT PER PR12001
C133 C388 C320 C263 LOWER LEVEL (3 OF 3)

C371 C267 C43 C46
2.2 0.01 0.01 0.01
2.2 0.01 0.01 0.01
SIZE DWG NO. REV
D
D B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
19
REV
6
1
*** Signal Cross-Reference *** ATSD2_CAS * 4C3 7D4 GP_INIT_DONE 5B6 3B7 12C5 PLX_DCLK 12C5
--- for the entire design -- ATSD2_CKE 4C3 7D4 GP_INTR 5C6 4B7 PLX_EED 2A1 3C7
ATSD2_CLK 4C3 7D4 GP_SYNC <2..0> 5B3 4B7 PLX_EESK 2A1 3C7
ABSD1_A <13..0> 4C3 8D8 ATSD2_CLK * 4C3 7D4 GP_TDO 5A6 3B7 4A8 PLX_LHOLD 2A4 3C7 12C5
ABSD1_BA <1..0> 4B3 8D8 ATSD2_CS * 4C3 7D4 GP_VID <15..0> 5B3 4B7 PLX_LHOLDA 3C7 2A4
ABSD1_CAS * 4C3 8D8 ATSD2_D <31..0> 4C3 7D4 GTSD1_A <13..0> 5D3 9D7 PLX_NCONFIG 2C2 3C7 12C5
D D
ABSD1_CKE 4C3 8D8 ATSD2_DQM <3..0> 4C3 7D4 GTSD1_BA <1..0> 5D3 9D7 PLX_TDO 2C5 4A8
ABSD1_CLK 4C3 8D8 ATSD2_DQS <3..0> 4C3 7D4 GTSD1_CAS * 5D3 9D7 PXL_CLK_OUT 4B7 5C6
ABSD1_CLK * 4C3 8D8 ATSD2_RAS * 4C3 7D4 GTSD1_CKE 5D3 9D7 TCK 4A8 2C5 3B7 5A6 12C4
ABSD1_CS * 4C3 8D8 ATSD2_WE * 4C3 7D4 GTSD1_CLK 5D3 9D7 TDI 12C7
ABSD1_D <31..0> 4B3 8D8 AVREF1_1.25V 4D3 8D1 GTSD1_CLK * 5D3 9D7 TDO 12B4
ABSD1_DQM <3..0> 4C3 8D8 AVREF2_1.25V 4D3 7D1 GTSD1_CS * 5D3 9D7 TMS 4A8 2C5 3B7 5A6 12C7
ABSD1_DQS <3..0> 4B3 8D8 CF_ADR <23..0> 12C8 GTSD1_D <31..0> 5D3 9D7 TRST * 4A8 2C5 5A6
ABSD1_RAS * 4C3 8D8 CF_CE 12C7 GTSD1_DQM <3..0> 5D3 9D7 VTM_INT 12C5
ABSD1_WE * 4C3 8D8 CF_OE 12C7 GTSD1_DQS <3..0> 5D3 9D7 VTM_INT * 5C6 3C7
ABSD2_A <13..0> 4B3 8D4 CF_READY 12C7 GTSD1_RAS * 5D3 9D7
ABSD2_BA <1..0> 4B3 8D4 CF_WE 12C7 GTSD1_WE * 5D3 9D7
ABSD2_CAS * 4B3 8D4 CINE_CLK_BUF_OE * 5C6 1D7 GTSD2_A <13..0> 5C3 9D4
ABSD2_CKE 4B3 8D4 CINE_PIXCLK_B 1C5 5A3 GTSD2_BA <1..0> 5C3 9D4
ABSD2_CLK 4B3 8D4 CLK_10HZ 4B7 3D7 12D7 GTSD2_CAS * 5D3 9D4
ABSD2_CLK * 4B3 8D4 CLK_CONF_66M 1B4 3D7 12C2 GTSD2_CKE 5D3 9D4
ABSD2_CS * 4B3 8D4 CONF_LED 12C4 GTSD2_CLK 5D3 9D4
ABSD2_D <31..0> 4B3 8D5 CONF_LED * 3B7 4A8 GTSD2_CLK * 5D3 9D4
ABSD2_DQM <3..0> 4B3 8D4 CONF_TDO 3B7 2C5 4A8 GTSD2_CS * 5D3 9D4
ABSD2_DQS <3..0> 4B3 8D4 CPLD_NSTATUS 3B7 12B2 2C2 GTSD2_D <31..0> 5C3 9D4
C ABSD2_RAS * 4B3 8D4 DEV_CLR 12C2 GTSD2_DQM <3..0> 5C3 9D4 C
ABSD2_WE * 4B3 8D4 DEV_OE 12C2 GTSD2_DQS <3..0> 5C3 9D4
APGP_CONF_DONE 4A7 5B6 3B7 12B2 FPDP_CLK_BUF_OE * 4A3 1D7 GTSD2_RAS * 5D3 9D4
APGP_CTL_AD <31..0> 4B7 5C6 FPDP_D <31..0> 4A3 6B6 GTSD2_WE * 5D3 9D4
APGP_CTL_BE <3..0> 4B7 5C6 FPDP_DIR * 4A3 6D7 GVREF1_1.25V 5D3 10D1
APGP_CTL_MCNTL <2..0> 4B7 5C6 FPDP_DVALID * 4A3 6D7 GVREF2_1.25V 5D3 9D1
APGP_CTL_SCNTL <1..0> 4B7 5C6 FPDP_NRDY * 4B3 6D7 LB_ACTIVE 12C2
APGP_DATAO 3B7 4A7 5B6 12B2 FPDP_PIO <2..1> 4A3 6D7 LB_ACTIVE * 3B7 4A8
APGP_DCLK 3B7 12B2 4A7 5B6 FPDP_SUSP * 4A3 6D7 LB_ADS 12B5
APGP_NCONFIG 3C7 12B2 4A7 5B6 FPDP_SYNC * 4A3 6D7 LB_ADS * 2A4 4D7 3C7
APGP_NSTATUS 4A7 5B6 3B7 12B2 FPSTROB 1D5 4A7 6D7 LB_ALE 2C4 4D7
APTOGP_SPARE <3..0> 4B7 5C6 GBSD1_A <13..0> 5C3 10D7 LB_BIGEND * 4D3 2A4
AP_BREQI 3C7 4D3 12C2 GBSD1_BA <1..0> 5C3 10D7 LB_BLAST 12C5
AP_BREQO 4D7 3C7 12C2 GBSD1_CAS * 5C3 10D7 LB_BLAST * 2A4 4D7 3C7
AP_CINE_SYNC <2..0> 4B3 5B6 GBSD1_CKE 5C3 10D7 LB_BTERM * 2A4 4D7
AP_CINE_VID <11..0> 4B3 5B6 GBSD1_CLK 5C3 10D7 LB_CCS * 4D3 2D2
AP_HOLD 4D7 3C7 12C2 GBSD1_CLK * 5C3 10D7 LB_DACK <1..0> * 2D2 4D7
AP_HOLDA 4D3 12C2 3C7 GBSD1_CS * 5C3 10D7 LB_DEN * 2C4 4D7
AP_INIT_DONE 4A7 3B7 12C2 GBSD1_D <31..0> 5C3 10D7 LB_DMPAF_EOT * 2D2 4D7
AP_INTR 12C2 GBSD1_DQM <3..0> 5C3 10D7 LB_DP <3..0> 2D2 4D7
B AP_INTR * 4D3 3C7 GBSD1_DQS <3..0> 5C3 10D7 LB_DREQ <1..0> * 4D3 2D2 B
AP_NCEO 4A7 5B6 GBSD1_RAS * 5C3 10D7 LB_DTR * 2C4 4D7
AP_SW_RST 4B7 5C6 GBSD1_WE * 5C3 10D7 LB_LAD <31..0> 2D4 3B4 3C7 4D7 12D5
AP_SYNC <2..0> 4B3 5B6 GBSD2_A <13..0> 5B3 10D4 LB_LBE <3..0> 12B4
AP_TDO 4A8 5A6 GBSD2_BA <1..0> 5B3 10D4 LB_LBE <3..0> * 2B4 4D7 3C7
AP_VID <15..0> 4B3 5B6 GBSD2_CAS * 5B3 10D4 LB_LINTI 12D7
ATSD1_A <13..0> 4D3 7D7 GBSD2_CKE 5C3 10D4 LB_LINTI * 3C7 2A4
ATSD1_BA <1..0> 4D3 7D7 GBSD2_CLK 5C3 10D4 LB_LINTO * 2A4 4D7
ATSD1_CAS * 4D3 7D7 GBSD2_CLK * 5C3 10D4 LB_LRESET * 4D7 3B7 3C4 5C6
ATSD1_CKE 4D3 7D7 GBSD2_CS * 5B3 10D4 LB_LSERR * 2A4 4D7
ATSD1_CLK 4D3 7D7 GBSD2_D <31..0> 5B3 10D4 LB_LWR 2A4 4D7 3C7 12B5
ATSD1_CLK * 4D3 7D7 GBSD2_DQM <3..0> 5B3 10D4 LB_READY * 2A4 3C7 4D7
ATSD1_CS * 4D3 7D7 GBSD2_DQS <3..0> 5B3 10D4 LB_WAIT * 2C2 4D7
ATSD1_D <31..0> 4D3 7D7 GBSD2_RAS * 5B3 10D4 OSC_40M 1D5 4D7 5D6
ATSD1_DQM <3..0> 4D3 7D7 GBSD2_WE * 5B3 10D4 OSC_66M_AP 1B4 4D7
ATSD1_DQS <3..0> 4D3 7D7 GPTOAP_CINE_OE 4B7 5C6 OSC_66M_GP 1B4 5D6
ATSD1_RAS * 4D3 7D7 GPTOAP_CLK_SPARE 4B6 5C6 OSC_66M_PLX 1B4 2D2
ATSD1_WE * 4D3 7D7 GPTOAP_SPARE <3..0> 5C6 4B7 PLX_BREQI 3C7 2A4
ATSD2_A <13..0> 4C3 7D4 GP_COMP_FAULT 5C6 4B7 PLX_BREQO 2A4 3C7 12C5
ATSD2_BA <1..0> 4C3 7D4 GP_ERR_LED * 5A6 4B8 PLX_DATAO 12C5
A A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
20
REV
6
1
*** Unit Cross-Reference *** C61 CERSMT_1206 15C6 C126 CERSMT_0603 7A8 C191 CERSMT8DIP4X 5B4
--- for the entire design -- C62 CERSMT_1206 15D4 C127 CERSMT_0603 7A7 C192 CERSMT8DIP4X 5B4
C63 CERSMT_0603 15B3 C128 CERSMT_0603 7A7 C200 CERSMT_0805 4C1
ASM_U14 ADDONS 1B2 C64 CERSMT_1206 15C6 C129 CERSMT_1206 10A8 C201 CERSMT_0603 9B7
ASM_U15 ADDONS 1B2 C65 CERSMT_0603 7B8 C130 CERSMT_0603 10B1 C202 CERSMT_0603 9B7
C1 CERSMT_0603 11B3 C66 CERSMT_0603 7B8 C131 CERSMT_0603 10A7 C203 CERSMT_0603 9C4
D C2 TASMT_7343 15D7 C67 CERSMT_0603 7B8 C132 CERSMT_0603 10A7 C204 CERSMT_0603 18B3
D
C4 CERSMT_0603 11B2 C69 CERSMT_0603 7B7 C134 CERSMT_0603 11B3 C206 CERSMT_0603 18B6
C5 CERSMT_0603 11B2 C70 CERSMT_1206 10B8 C135 CERSMT_0603 1C6 C207 CERSMT_0603 18C7
C6 TASMT_7343 10B8 C71 CERSMT_0603 10B4 C136 CERSMT_0603 11C4 C208 CERSMT_0603 18C6
C7 CERSMT_0603 8A7 C72 CERSMT_0603 10B8 C137 CERSMT_1206 18D5 C209 CERSMT_0603 18C6
C8 CERSMT_0603 8A7 C73 CERSMT_0603 10B8 C138 CERSMT_0603 18C6 C210 CERSMT_0603 18C6
C9 CERSMT_0603 8B4 C74 CERSMT_1206 18C7 C139 CERSMT_0603 11A4 C211 CERSMT_0603 18B6
C10 CERSMT_0603 11B2 C75 CERSMT_0603 18C7 C140 CERSMT_1206 11B5 C212 CERSMT_1206 18B6
C11 CERSMT_0603 15C6 C76 CERSMT_1206 18D4 C141 CERSMT_1206 2B4 C213 CERSMT_0805 18C4
C12 CERSMT_0603 15C5 C77 CERSMT_1206 18C7 C142 CERSMT_1206 2B1 C214 CERSMT_0603 1D7
C13 CERSMT_1206 15D4 C78 CERSMT_0603 18C6 C143 CERSMT_0603 2B8 C215 CERSMT_0805 1D7
C14 CERSMT_0603 15C6 C79 CERSMT_0603 9A7 C144 TASMT_7343 9B8 C216 CERSMT_1206 1D8
C15 CERSMT_0603 1A5 C80 CERSMT_0603 9B4 C145 CERSMT_0603 1B7 C217 CERSMT_0603 1D6
C16 CERSMT_0603 15C6 C81 CERSMT_0603 9A8 C146 CERSMT_1206 1B5 C218 CERSMT_0603 1D5
C17 CERSMT_0603 15B3 C82 CERSMT_0603 9A8 C147 CERSMT_1206 5D8 C219 CERSMT_0805 15C3
C18 CERSMT_0603 18C6 C83 CERSMT_0603 9A8 C148 CERSMT_1206 5D8 C220 CERSMT_1206 15A6
C19 CERSMT_1206 18D5 C84 CERSMT_0603 9A7 C149 CERSMT_0603 11C4 C221 CERSMT_0603 15B5
C20 CERSMT_0603 1A6 C85 CERSMT_0603 11B2 C150 TASMT_7343H 11C4 C222 CERSMT_0603 15C7
C C21 CERSMT_1206 18B3 C86 TASMT_7343H 11D6 C151 CERSMT_0805 11C5 C223 CERSMT_0603 15B6 C
C22 TASMT_7343 7B8 C87 TASMT_7343H 11D4 C152 CERSMT_1210 11C6 C224 CERSMT_0603 15C5
C23 CERSMT_0603 9B8 C88 CERSMT_0603 8A8 C153 CERSMT_1206 11C5 C225 CERSMT_0603 15A6
C24 CERSMT_0603 11B3 C89 CERSMT_0603 8A7 C154 CERSMT_0805 11C6 C226 CERSMT_0603 15C5
C25 CERSMT_0603 9B7 C90 CERSMT_0603 8A8 C155 CERSMT_0603 11A4 C227 CERSMT_0603 15B5
C26 CERSMT_0603 9B7 C91 CERSMT_0603 8A7 C156 TASMT_7343H 11A4 C228 CERSMT_1206 15B6
C27 CERSMT_0603 9B8 C92 CERSMT_0603 8A8 C157 CERSMT_0805 11A5 C229 CERSMT_0805 15C3
C28 CERSMT_0603 11B2 C93 CERSMT_1206 15C6 C158 CERSMT_1210 11B6 C230 CERSMT8DIP4X 4D8
C29 CERSMT_0603 8A7 C94 CERSMT_0603 15C6 C159 CERSMT_0805 11A6 C231 CERSMT8DIP4X 4D8
C30 CERSMT_1206 8A8 C95 CERSMT_0603 15A5 C160 CERSMT_0603 11B2 C232 CERSMT_0603 8B7
C31 CERSMT_0603 15C7 C96 CERSMT_1206 15D4 C161 CERSMT_0603 11C3 C233 CERSMT8DIP4X 4D8
C32 CERSMT_0603 15A5 C97 CERSMT_0603 15C6 C162 CERSMT_0603 2C8 C234 CERSMT8DIP4X 4D8
C33 CERSMT_1206 15A3 C98 CERSMT_0603 7A8 C163 CERSMT_0603 2C8 C235 CERSMT_0603 8B8
C35 CERSMT_0603 7B7 C100 CERSMT_0603 7B1 C165 CERSMT_0603 2A7 C237 CERSMT8DIP4X 4D8
C36 CERSMT_0603 7B4 C101 CERSMT_1206 10A8 C166 CERSMT_0603 2B8 C238 CERSMT_0603 8B8
C37 CERSMT_1206 10B8 C102 CERSMT_0603 10A8 C167 CERSMT_0603 2C8 C239 CERSMT_1206 9B8
B C41 CERSMT_0603 10B7 C106 CERSMT_0603 10A8 C171 CERSMT_0603 2C7 C243 CERSMT_0603 9B8 B
C42 CERSMT_0603 10B8 C107 CERSMT_0603 18C6 C172 CERSMT_0603 2B8 C244 CERSMT_0603 9B8
C43 CERSMT_0603 18A6 C108 CERSMT_1206 18C6 C173 CERSMT_0603 2B8 C245 CERSMT_0603 18C6
C44 CERSMT_0603 18C6 C109 CERSMT_0603 18C6 C174 CERSMT_0603 2B8 C246 CERSMT_0603 18A6
C45 CERSMT_0603 18C6 C110 CERSMT_0603 18A6 C175 CERSMT_0805 2A7 C247 CERSMT_0805 18C4
C46 CERSMT_0603 18A6 C111 CERSMT_0603 9B1 C176 CERSMT_0603 2A6 C248 CERSMT_0603 18D6
C47 CERSMT_0603 18C7 C112 CERSMT_0603 9A8 C177 CERSMT_1206 2A7 C249 CERSMT_0603 18D6
C49 CERSMT_0603 9B8 C114 CERSMT_1206 9A8 C179 TASMT_7343 2B3 C251 CERSMT_0603 18B3
C50 CERSMT_0603 9B8 C115 CERSMT_0603 1A5 C180 CERSMT_1206 5D7 C252 CERSMT_0603 18B4
C51 CERSMT_1206 9B8 C116 CERSMT_1206 15A4 C181 CERSMT_1206 5D7 C253 CERSMT_0603 18B6
C52 CERSMT_0603 11D5 C117 CERSMT_0603 11B2 C182 CERSMT_0603 11B3 C254 CERSMT_0603 18D6
C53 CERSMT_0603 8A8 C118 CERSMT_0603 15C7 C183 TASMT_7343H 11C6 C255 CERSMT_0603 18C6
C54 CERSMT_0603 8A8 C119 CERSMT_0603 1A5 C184 TASMT_7343H 11B6 C256 CERSMT_0603 18D4
C55 CERSMT_0603 8A8 C120 CERSMT_0603 4B7 C185 CERSMT_0603 11C3 C257 CERSMT_0603 18D4
C56 CERSMT_0603 8A8 C121 CERSMT_0603 15C6 C186 CERSMT_0603 11C3 C258 CERSMT_0603 18C6
C57 CERSMT_0603 8A8 C122 CERSMT_0603 2B2 C187 CERSMT_0603 11C2 C259 CERSMT_0603 18B6
C58 CERSMT_0603 8B1 C123 CERSMT_1206 2B2 C188 CERSMT_0603 11C3 C260 CERSMT_0603 18D6
C60 CERSMT_1206 8A8 C125 CERSMT_0603 7A8 C190 CERSMT8DIP4X 5B4 C262 CERSMT_0603 18B6
A A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
21
REV
6
1
C263 CERSMT_0603 18A4 C328 CERSMT_0603 10B8 C393 CERSMT_0603 10C1 C458 CERSMT_0603 15A3
C264 CERSMT_1206 18B6 C329 CERSMT_1206 7B8 C394 CERSMT_1206 7A8 C459 CERSMT_0603 12B2
C265 CERSMT_0603 18C7 C330 CERSMT_0603 7C4 C395 CERSMT_0603 7A7 C460 CERSMT_0805 12A2
C266 CERSMT_0603 18C6 C331 CERSMT_0603 7B8 C396 CERSMT_0603 7A8 C461 CERSMT_0805 12A1
D C267 CERSMT_0603 18A6 C332 CERSMT_0603 7B8 C397 CERSMT_0603 7A7 C462 CERSMT_0603 12B1 D
C268 CERSMT_0603 18C6 C333 CERSMT_0603 15D6 C398 CERSMT_0603 7A8 C463 CERSMT_1206 12A2
C270 CERSMT_0603 10B8 C335 CERSMT_0603 15C6 C400 CERSMT_0603 15C5 C465 CERSMT_0805 12A1
C271 CERSMT_0603 10C4 C336 CERSMT_0603 15A2 C401 CERSMT_0805 15C3 C466 CERSMT_0805 12A1
C272 CERSMT_1206 7B8 C337 CERSMT_0603 15B5 C402 CERSMT_1206 15B6 C467 CERSMT_0603 12B1
C273 CERSMT_0603 7B7 C338 CERSMT_0603 15D5 C403 CERSMT_0603 15A2 C468 CERSMT_0603 3C2
C274 CERSMT_0603 7B7 C339 CERSMT_0603 15B3 C404 CERSMT_0603 15B6 C469 CERSMT_0603 3C1
C275 CERSMT_0603 7B8 C340 CERSMT_0603 15B6 C405 CERSMT_1206 15B6 C470 CERSMT_0603 3C2
C276 CERSMT_0603 7B8 C341 CERSMT_0603 15D6 C406 CERSMT_0603 15A6 C471 CERSMT_0805 5D7
C277 CERSMT_0603 7B7 C342 CERSMT_0603 15D6 C407 CERSMT_0603 15C3 C472 CERSMT_0603 1B5
C278 CERSMT_0603 15A5 C343 CERSMT_0603 15D6 C408 CERSMT_0603 15A5 C473 CERSMT_0603 1B5
C279 CERSMT_0603 15C5 C344 CERSMT_0603 15B5 C409 CERSMT_0603 15C6 C474 CERSMT_1206 1B8
C280 CERSMT_0603 15C5 C345 CERSMT_0603 15B4 C410 CERSMT_0603 15D3 C475 CERSMT_0805 1B8
C281 CERSMT_1206 15A6 C346 CERSMT_0603 15B5 C411 CERSMT_0603 15D3 C476 CERSMT_0805 2B1
C282 CERSMT_0603 15A2 C347 CERSMT_0603 15B3 C412 CERSMT_0603 15A5 C477 CERSMT_0603 2B1
C283 CERSMT_0603 15B5 C348 CERSMT_0603 15D3 C413 CERSMT_0603 15C5 C478 CERSMT_0603 2B1
C285 CERSMT_0603 15D5 C350 CERSMT_0603 15D3 C415 CERSMT_0603 15C3 C480 CERSMT_1206 2B2
C286 CERSMT_0603 15D3 C351 CERSMT_0603 15A3 C416 CERSMT_0603 15B5 C481 CERSMT_0603 2B2
C C287 CERSMT_0603 15D3 C352 CERSMT_0603 15A3 C417 CERSMT_1206 15A6 C482 CERSMT_0603 2C1 C
C288 CERSMT_0603 15B6 C353 CERSMT_0603 15D6 C418 CERSMT_0603 15A6 C483 CERSMT_0603 2C2
C289 CERSMT_0603 15D5 C354 CERSMT_0603 15D6 C419 CERSMT_1206 15A6 C484 CERSMT_0603 2B2
C291 CERSMT_0603 15A5 C356 CERSMT_0603 8C4 C421 CERSMT_0603 15A5 C486 CERSMT_0603 2C2
C294 CERSMT_0603 15C6 C359 CERSMT_0603 8A8 C424 CERSMT_0603 8C1 C489 CERSMT_0603 2C8
C295 CERSMT_0603 15C6 C360 CERSMT_0603 8B7 C425 CERSMT_0603 8A8 C490 CERSMT_0805 2C1
C299 CERSMT_0603 9A8 C364 CERSMT_0603 9A7 C429 CERSMT_0603 18A3 C494 CERSMT_0603 2C2
C300 CERSMT_0603 9A8 C365 CERSMT_0603 9A7 C430 CERSMT_0603 10A7 C495 CERSMT_0603 2C2
C303 CERSMT_0603 18D6 C368 CERSMT_0603 9A8 C433 CERSMT_0603 10A8 C498 CERSMT_1206 2B2
C304 CERSMT_0603 18D6 C369 CERSMT_0603 18B6 C434 CERSMT_0603 10A8 C499 CERSMT_0603 2B8
B C307 CERSMT_0603 18D7 C372 CERSMT_0603 18B3 C437 CERSMT_0603 7A8 C502 CERSMT_0603 2A2 B
C308 CERSMT_0603 18B4 C373 CERSMT_0603 18A6 C438 CERSMT_0603 7A8 C503 CERSMT_0805 2A3
C309 CERSMT_0603 18B4 C374 CERSMT_1206 18A6 C439 CERSMT_1206 2B1 C504 CERSMT_0603 12B2
C310 CERSMT_0603 18C3 C375 CERSMT_0603 18A6 C440 CERSMT_0603 2B1 C505 CERSMT_0603 12B2
C311 CERSMT_0603 18C3 C376 CERSMT_0603 18D7 C441 CERSMT_1206 2C1 C506 CERSMT_0805 12A2
C312 CERSMT_0603 18C3 C377 CERSMT_0603 5C7 C442 CERSMT_0805 2C1 C507 CERSMT_0603 4D1
C314 CERSMT_0603 18C3 C379 CERSMT_0603 18D4 C444 CERSMT_0603 15C6 C509 CERSMT_0805 12A2
C315 CERSMT_0603 18B4 C380 CERSMT_0603 18D4 C445 CERSMT_0603 2B2 C510 CERSMT_1206 12A3
C317 CERSMT_0603 18D4 C382 CERSMT_0603 18C6 C447 CERSMT_0603 2C2 C512 CERSMT_0805 12A3
C318 CERSMT_0603 18A6 C383 CERSMT_0603 18A6 C448 CERSMT_0603 2B2 C513 CERSMT_1206 12A3
C319 CERSMT_0603 18D4 C384 CERSMT_0603 18D7 C449 CERSMT_0603 15C5 C514 CERSMT_0805 12A3
C320 CERSMT_0603 18A4 C385 CERSMT_0603 18A6 C450 CERSMT_0603 2B2 C515 CERSMT_0603 12B3
C321 CERSMT_0603 18C7 C386 CERSMT_1206 18A6 C451 CERSMT_0805 2B1 C516 CERSMT_1206 3C1
C322 CERSMT_0603 18C7 C387 CERSMT_0603 18B6 C452 CERSMT_0603 2B2 C517 CERSMT_0603 5D6
C323 CERSMT_0603 18C7 C388 CERSMT_0603 18A4 C453 CERSMT_0603 2B2 C518 CERSMT_1206 2C1
C324 CERSMT_0603 10B7 C389 CERSMT_1206 18A6 C454 CERSMT_0603 2B2 C519 CERSMT_0805 2C1
C325 CERSMT_0603 10B7 C390 CERSMT_0805 18C4 C455 CERSMT_0603 2C2 C520 CERSMT_0603 2C1
A C326 CERSMT_0603 10B8 C391 CERSMT_0603 10A7 C456 CERSMT_0805 2C1 C521 CERSMT_0603 2C2
A
C327 CERSMT_0603 10B8 C392 CERSMT_0603 10A8 C457 CERSMT_0603 15C6 C522 CERSMT_0603 2C2
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
22
REV
6
1
C523 CERSMT_0603 2C2 P8 HDST_SMT_2X10_51407703 4B2 4C2 R60 RESSMT_0603 14B4 R125 RESSMT_0805 2A8
C524 CERSMT_0603 2C8 P9 CONN_EDGE_PCI_188_UNIV 2A5 2A5 2A7 2A8 2B5 R61 RESSMT_0603 15A2 R126 RESSMT8DIP4X 5B3
C525 CERSMT_0805 2B1 2B5 2B7 2B7 2B7 2B7 2B7 2B8 2B8 2B8 R62 RESSMT_0603 14A7 R127 RESSMT8DIP4X 5B3
C526 CERSMT_0603 2B1 2B8 2C7 2C7 2C7 2C7 2C7 2C7 2C8 2C8 R63 RESSMT_0603 13A7 R128 RESSMT8DIP4X 5B3
C527 CERSMT_0603 2C2 2C8 2D7 2D8 R64 RESSMT8DIP4X 7A4 R129 RESSMT_0603 5A3
D C528 CERSMT_0603 2C1 Q1 TN2106 2B5 R65 RESSMT8DIP4X 7A4 R130 RESSMT_0603 11D4 D
C529 CERSMT_0603 2B3 R1 RESSMT8DIP4X 8B5 R66 RESSMT_0603 7B6 R131 RESSMT_0603 11C4
C530 CERSMT_0603 2C2 R2 RESSMT8DIP4X 8B5 R67 RESSMT_0603 10B6 R132 RESSMT_0603 11B4
C531 CERSMT_0603 2C3 R3 RESSMT8DIP4X 4D8 R68 RESSMT8DIP4X 10B4 R200 RESSMT8DIP4X 9C4
C532 CERSMT_0603 2C2 R4 RESSMT_0603 8B6 R69 RESSMT8DIP4X 10B4 R201 RESSMT8DIP4X 9C4
C533 CERSMT_0603 2B3 R5 RESSMT8DIP4X 4D8 R70 RESSMT_0603 17A6 R202 RESSMT_0603 9D6
C534 CERSMT_0805 2B1 R6 RESSMT_0603 8D6 R71 RESSMT_0603 18A2 R203 RESSMT_0603 9D6
C535 CERSMT_1206 2B2 R7 RESSMT8DIP4X 4D8 R72 RESSMT_0603 16B3 R204 RESSMT_0603 1B6
C536 CERSMT_0603 2D8 R8 RESSMT8DIP4X 4D8 R73 RESSMT_0603 9B3 R205 RESSMT_0603 1C7
C537 CERSMT_0603 2C8 R9 RESSMT8DIP4X 4D8 R74 RESSMT_0603 9B6 R206 RESSMT_0603 15B3
C538 CERSMT_0603 12B2 R10 RESSMT_0603 6D4 R75 RESSMT8DIP4X 9A1 R207 RESSMT_0603 13B4
C539 CERSMT_0805 12A2 R11 RESSMT_0603 6D4 R76 RESSMT8DIP4X 9A1 R208 RESSMT_0603 1B5
C540 CERSMT_0603 12B2 R12 RESSMT_0603 6D5 R77 RESSMT_0805 11D5 R209 RESSMT_0603 14D7
C541 CERSMT_0603 2D8 R13 RESSMT_0603 6D5 R78 RESSMT8DIP4X 8A1 R210 RESSMT_0603 6D5
C542 CERSMT_0603 12B3 R14 RESSMT8DIP4X 6D5 R79 RESSMT8DIP4X 8A1 R211 RESSMT_0603 6D5
C543 CERSMT_0805 12A1 R15 RESSMT_0603 14D7 R80 RESSMT_0603 14C7 R212 RESSMT_0603 6D4
C544 CERSMT_0603 12B1 R16 RESSMT8DIP4X 6D5 R81 RESSMT_0603 13A4 R213 RESSMT_0603 6D4
C545 CERSMT_0603 11C2 R17 RESSMT8DIP4X 6C5 R82 RESSMT8DIP4X 7B1 R214 RESSMT_0603 8D6
C546 CERSMT_0603 11C2 R18 RESSMT8DIP4X 6C5 R83 RESSMT8DIP4X 7A1 R215 RESSMT8DIP4X 8C5
C547 CERSMT_0603 11C2 R19 RESSMT8DIP4X 6C5 R84 RESSMT_0603 7B3 R216 RESSMT8DIP4X 8C5
C C548 CERSMT_0603 11C2 R20 RESSMT8DIP4X 6C5 R85 RESSMT_0603 10B3 R217 RESSMT_0603 4D2 C
C549 CERSMT_0603 11C2 R21 RESSMT8DIP4X 6B5 R86 RESSMT8DIP4X 10A1 R218 RESSMT8DIP4X 9C4
C550 CERSMT_0603 11C2 R22 RESSMT8DIP4X 6B5 R87 RESSMT8DIP4X 10A1 R219 RESSMT8DIP4X 9C4
C551 CERSMT_1206 2D8 R23 RESSMT8DIP4X 6B5 R88 RESSMT_0603 9D3 R220 RESSMT_0603 16D5
CB1 POLYSWITCH_3812 11D6 R24 RESSMT_0603 15B3 R89 RESSMT_0603 9B3 R221 RESSMT_0603 16B5
CB2 POLYSWITCH_3812 11D7 R25 RESSMT_0603 5A2 R90 RESSMT8DIP4X 9B1 R222 RESSMT_0603 16B3
CB3 POLYSWITCH_3812 11D7 R26 RESSMT_0603 5A4 R91 RESSMT8DIP4X 9B1 R223 RESSMT_0603 17B4
CB4 POLYSWITCH_3812 11B7 R27 RESSMT_0603 5A4 R92 RESSMT_0603 4C3 R224 RESSMT_0603 17C6
DS1 LED2_RED_67480213 4B7 R28 RESSMT_0603 5A3 R93 RESSMT_0603 8B3 R225 RESSMT8DIP4X 10C4
DS2 LED4_GRN_67480211 4B7 R29 RESSMT_0603 5A3 R94 RESSMT_0603 3B7 R226 RESSMT8DIP4X 10C4
E1 JMPST_1X2_90012601 2D8 R30 RESSMT_0603 5A3 R95 RESSMT_0603 15A3 R227 RESSMT_0603 10D6
L1 INDSMTMLD_1210 1D8 R31 RESSMT_0603 18B3 R96 RESSMT_0603 4A6 R228 RESSMT_0603 10D6
L2 INDSMT_43800020 11B4 R32 RESSMT_0603 18B3 R97 RESSMT_0603 15A3 R229 RESSMT_0603 7D6
L3 INDSMTMLD_1210 1B8 R33 RESSMT_0603 9B6 R98 RESSMT8DIP4X 7A1 R230 RESSMT8DIP4X 7C4
L4 INDSMT_43800020 11C4 R34 RESSMT8DIP4X 9A4 R99 RESSMT8DIP4X 7A1 R231 RESSMT8DIP4X 7C4
L200 INDSMTMLD_1210 18B4 R35 RESSMT8DIP4X 9A4 R100 RESSMT_0603 7B3 R232 RESSMT_0603 13B6
L201 INDSMTMLD_1210 18D4 R36 RESSMT_0603 4C2 R101 RESSMT_0603 10D3 R233 RESSMT_0603 13B4
L202 INDSMTMLD_1210 15D3 R37 RESSMT8DIP4X 4D2 R102 RESSMT_0603 10B3 R234 RESSMT_0603 13B4
L203 INDSMTMLD_1210 15B3 R38 RESSMT_0603 14A6 R103 RESSMT8DIP4X 10B1 R235 RESSMT_0603 14B4
L204 INDSMTMLD_1210 18D4 R39 RESSMT_0603 13D6 R104 RESSMT8DIP4X 10B1 R236 RESSMT8DIP4X 9C1
B B
L205 INDSMTMLD_1210 15D3 R40 RESSMT8DIP4X 7B4 R105 RESSMT_0603 18A3 R237 RESSMT8DIP4X 9C1
L206 INDSMTMLD_1210 18D4 R41 RESSMT8DIP4X 7A4 R106 RESSMT_0603 18A3 R238 RESSMT_0603 9D3
L207 INDSMTMLD_1210 15D3 R42 RESSMT_0603 7B6 R107 RESSMT_0603 17C6 R239 RESSMT_0603 9D6
L208 INDSMTMLD_1210 18A4 R43 RESSMT_0603 7D6 R108 RESSMT_0603 17C6 R240 RESSMT_0603 16A6
L209 INDSMTMLD_1210 15A3 R44 RESSMT_0603 10B6 R109 RESSMT_0603 16A3 R241 RESSMT_0603 17B4
L210 INDSMTMLD_1210 2C1 R45 RESSMT8DIP4X 10A4 R110 RESSMT_0603 5B1 R242 RESSMT8DIP4X 10C4
MISC3 ADDONS 1B2 R46 RESSMT8DIP4X 10A4 R111 RESSMT8DIP4X 2A2 R243 RESSMT8DIP4X 10C4
MISC4 ADDONS 1A2 R47 RESSMT_0603 17B6 R112 RESSMT_0603 2D2 R244 RESSMT_0603 10D6
MISC5 ADDONS 1A2 R48 RESSMT_0603 17B5 R113 RESSMT_0603 2D2 R245 RESSMT_0603 7D6
MISC8 ADDONS 1B2 R49 RESSMT_0603 16B3 R114 RESSMT_0603 2C5 R246 RESSMT8DIP4X 7C4
MISC9 ADDONS 1B2 R50 RESSMT_0603 16B3 R115 RESSMT_0603 1B7 R247 RESSMT8DIP4X 7C4
MISC??? ADDONS 1A2 R51 RESSMT8DIP4X 9B4 R116 RESSMT_0603 11A2 R248 RESSMT_0603 13B4
P1 D50RA_80P_51180030 6A4 6A4 6A4 6B4 6B4 6B4 R52 RESSMT8DIP4X 9B4 R117 RESSMT8DIP4X 11A3 R249 RESSMT_0603 14B6
6B4 6B4 6C4 6C4 6C4 6D4 6D4 6D4 R53 RESSMT_0603 11D6 R118 RESSMT_0805 11C5 R250 RESSMT_0603 14A7
P2 HDSHRST_2X5_51408753 4C3 4D3 4D3 R54 RESSMT8DIP4X 8B1 R119 RESSMT_0805 11C6 R251 RESSMT_0603 4A6
P3 HDST_SMT_2X10_51407703 4B1 4C1 R55 RESSMT8DIP4X 8A5 R120 RESSMT_0805 11B5 R252 RESSMT_0603 8D3
P4 D50RA_40P_51180031 4B8 4B8 4C8 4C8 R56 RESSMT8DIP4X 8B1 R121 RESSMT_0805 11A6 R253 RESSMT_0603 8D6
P5 D50RA_34P_51180039 4A2 4A2 4A3 4A3 R57 RESSMT8DIP4X 8A5 R122 RESSMT_0805 2A8 R254 RESSMT8DIP4X 8C5
P6 D50RA_40P_51180031 5A2 5B2 5B2 5C2 5C2 R58 RESSMT_0603 8B3 R123 RESSMT_0805 2A8 R255 RESSMT8DIP4X 8C1
A P7 HDST_SMT_2X10_51407703 5A1 5A1 5B1 5B1 R59 RESSMT_0603 8B6 R124 RESSMT_0805 2A8 R256 RESSMT8DIP4X 8C5 A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
00-885794DDW
SHT
23
REV
6
1
R257 RESSMT8DIP4X 8C1 U5 SDRAM_256MBIT_62610418 9C5

R258 RESSMT8DIP4X 9C1 U6 74LCX125 4C1 4D1
R259 RESSMT8DIP4X 9C1 U7 EP1S40_1020_VCC 13D8 14D8 15D8
R260 RESSMT_0603 9D3 U8 EP1S60_1020_VCC 16D7 17D8 18D8
D R261 RESSMT_0603 5C7 U9 SDRAM_256MBIT_62610418 8C2
D
R262 RESSMT_0603 1C6 U10 SDRAM_256MBIT_62610418 9C2
R265 RESSMT_0603 10D3 U13 29LV640_TSOP_VCC 3C3
R266 RESSMT_0603 7D3 U14 EPM3256ATC144_VCC 12D6
R267 RESSMT8DIP4X 7C1 U15 FM93CS56L 2B2
R268 RESSMT8DIP4X 7C1 U16 PCI9656_JMODE_272 2D6
R269 RESSMT_0603 13A4 U17 49FCT3805 1B6
R270 RESSMT_0603 4B7 U18 ADM1025 5D6
R271 RESSMT_0603 14C7 U19 TPS54613 11C5
R272 RESSMT8DIP4X 8C1 U20 TPS54615 11B5
R273 RESSMT8DIP4X 8C1 U200 SDRAM_256MBIT_62610418 9D5
R274 RESSMT_0603 11D5 U201 SDRAM_256MBIT_62610418 10D5
R276 RESSMT_0603 16A3 U203 SDRAM_256MBIT_62610418 8D6
C R280 RESSMT_0603 7D3 U207 SDRAM_256MBIT_62610418 7D2 C
R281 RESSMT_0603 7D3 VR1 MIC29152BU_62610423 11D6
R282 RESSMT8DIP4X 7C1 Y1 OSC_SMT_EN_V33_VCC 1C7
R283 RESSMT8DIP4X 7C1 Y2 OSC_SMT_EN_V33_VCC 1B7
R284 RESSMT_0603 1A5
R285 RESSMT_0603 2C5
R286 RESSMT_0603 3B6
R288 RESSMT_0603 8D3
R298 RESSMT8DIP4X 2C5
B R300 RESSMT8DIP4X 2D5 B
R308 RESSMT8DIP4X 3D4
TP1 TEST_POINT_COLOR 11D4
TP3 TEST_POINT_COLOR 11C4
TP5 TEST_POINT_COLOR 11B4
U1 49FCT3805 1D6
U2 SDRAM_256MBIT_62610418 8C6
A U3 SDRAM_256MBIT_62610418 7C5
A
U4 SDRAM_256MBIT_62610418 10C5
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885794DDW 6
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REVISION HISTORY
REV CHANGE NUMBER DESCRIPTION OF CHANGE ORIGINATOR OR AUTHOR
A ECO FK49 RELEASE TO MANUFACTURING PER ECO FK49 F. FARRINGTON

B ECO FP55 REVISED PER ECO FP55 R. VAN OS
6 ECO 2033800 REVISED PER ECO 2033800 J. BRUENING
7 DCN 2513 CHANGES TO MULTIPLE SHEETS SEE DCN K. KOONS
8 DCN 03735 CHANGES TO MULTIPLE SHEETS SEE DCN B. BAILEY
9 DCN 04054 CHANGES TO MULTIPLE SHEETS SEE DCN B. GUTHRIE
10 DCN 04050 CHANGES TO MULTIPLE SHEETS SEE DCN B. GUTHRIE
11 DCN 05811 SHT 3, CHANGE PART NO FROM 879004 TO 888920 N. NEWBOLD
D 12 DCN 06185 SHT 9 &10 CHNG PRT NO FROM 902748 TO 5309354 J. RUVALCABA
D
13 DCN 06350 CHANGE PART NO. FROM 00-887458 TO 5315470 M. UHREY
14 DCN 06667 PART NO. CHANGE FOR PS1, PS2 AND PS3 D. OAKESON
15 DCN 07584 CHANGE DVD PART NO. TO 5321841 J. RUVALCABA
16 DCN 07584 CHG. SHT. 12 TO ADD P/N 5331424 TO TABLE S. BROWN
17 DCN 09149 CHG. SHT. 12 TO ADD P/N 5337057 TO TABLE S. BROWN
18 DCN 07946 CHG. SHT. 1,3,8,10 - NEW GPOS,RTOS PN's J. CORNELLA
19 DCN 11396 CHG. SHT. 12 TO ADD P/N 5346331 S. BROWN
20 DCN 11782 CHG. SHT. 1,9,10 - MONITORS, SHT 12 - PRW CORD K. MOORE
21 DCN 12325 CHG. SHT. 2,3,4,12-SATA DRIVE, PWR CORD INFO J. RUVALCABA
22 ECN1128 CHG. SHT. 1,3,7,8 FOR CINE DRIVE T-CARD, DVD T. BROWN
23 ECN1199 CHG. SHT. 1,9,10 NAV SCREEN, SHT 11 CORD ASM K. MOORE
24 ECN1593 CHANGED PER ECN S. BROWN
25 ECN2019 CHANGED PER ECN J. RUVALCABA
26 ECN2216 CHANGED PER ECN A. QUILTER
C C
B B
NOTES:
LEGEND 1. FOR ADDITIONAL 9900 SYSTEM INFORMATION REFER TO
COMMUNICATIONS DRAWING NUMBER 00-878981 AND 00-884675.
DATA
A A
CONTROL
FORMAT PER PR12001
THIS DOCUMENT AND THE INFORMATION CONTAINED UNLESS OTHERWISE SPECIFIED ORIGINAL DRAWN BY: DATE:
VIDEO HEREIN IS CONFIDENTIAL AND PROPERTY OF OEC DIMENSIONS ARE IN INCHES. GE HEALTHCARE - SURGERY
MEDICAL SYSTEMS, INC., A UNIT OF GE HEALTHCARE
AND WHOLLY - OWNED SUBSIDIARY OF GENERAL
TOLERANCES ARE:
FRACTIONS: +/- N/A
K. KOONS 06/23/05 DWG TITLE
VAC POWER ELECTRIC. IT IS DISCLOSED TO YOU FOR THE SOLE
PURPOSE OF YOUR PERFORMANCE UNDER THE DECIMALS: X +/- N/A ORIGINAL RESPONSIBLE ENGINEER: DATE:
CONTRACT WITH OEC MEDICAL SYSTEMS. IT IS NOT
TO BE COPIED OR IN ANY WAY DISCLOSED TO THIRD
.X +/- N/A
S. BROWN 06/29/05 INTERCONNECT DIAGRAM, WKSTN, 9900
.XX +/- N/A
VDC POWER PARTIES. IT SHALL BE RETURNED TO OEC
00-885899-03 1 MEDICAL SYSTEMS UPON DEMAND. YOU HEREBY .XXX +/- N/A SIZE DWG NO. REV
AGREE TO THESE RESTRICTIONS AND IDEMNIFY
PART NUMBER(S) REV OEC MEDICAL SYSTEMS FOR ALL LOSS OR DAMAGE
ARISING FROM BREACH OF THIS OBLIGATION BY
ANGLES: +/- N/A
B 00-885899DDW 26
YOU OR ENTITIES OR AGENTS UNDER YOUR
RELATED PARTS CONTROL.
DO NOT SCALE DRAWING SCALE: NONE SHEET 1 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OPTION 2 (NAV) OPTION 1 (NON-NAV) I/R TX

00-901382
TOUCH SCREEN TOUCH SCREEN AMPL. SPEAKER
X-RAY ON I/R RX 75-149930-00
LEFT RIGHT LEFT RIGHT DVD KEYBOARD USB HUB
MONITOR MONITOR MONITOR MONITOR INDICATOR AMBIENT DRIVE W/TOUCHPAD 00-902698
B/W FP COLOR FP B/W FP B/W FP 5304305 LT SENSOR 5393289 00-886464 1 4
5364342 5364344 5364342 5364343 5340095 2 3
IN/OUT
D D
DVI (FEMALE) DVI (FEMALE) 25 SKT 25 SKT D-SUB 37 SKT D-SUB USB RCPT USB RCPT
D-SUB
EMI BOX
DUAL PASSIVE BACKPLANE
SECTION "A" SECTION "B"
DC PWR
5251751 OUT
LPT1 USB LINUX USB USB USB
RTOS
SINGLE BOARD
SINGLE BOARD USB ETH2
COMPUTER
COMPUTER
SATA CINE CINE 5266165 (NON-NAV) SATA
5263643 (NON-NAV)
DRIVE BRIDGE 00-886890 (NAV)
886688 (NAV)
5328097 5309876 COM2 COM USB
C VGA ETH ETH1 AUD VGA COM C

SER/USB
VIDEO IMAGE DISPLAY DVI SYSTEMS SERIAL ATA ISOLATED
VID/FRAMSYNC
CONTROLLER PROCESSOR ADAPTOR INTERFACE DC PWR DC PWR HARD INTERFACE
TWINAXIAL BNC 00-888920 00-879056
00-885796 5268480 OUT OUT DRIVE 00-887455
TO INTER
CABLE 5371629
DVI
DC PWR DC PWR
IN IN
15 SKT D-SUB
TO INTER
CABLE
LF VID
BNC
TO INTER 25 SKT D-SUB THRU-HOLE 15 SKT D-SUB USB RCPT BACK PANEL
CABLE
B DVI BNC BNC BNC S(Y/C) 15 DSUB 15 HDDSUB RJ45 B
RT RS170 LF RT ENDO- F.S. RM DICOM
OUT LF MON MON SCOPE CNTL 10/100
OUT INPUT
L1 PS3 FUSE
3200 VA CIRCUIT ISD POWER 1400 VA PS2 PS1 PS3 NAV NAV MONITOR
CONTROL UPS SURGE SUPPR 5404868 5404868 5321829 TRACKER TOOLS
ISOLATION BREAKERS 00-887088
5315470 5196397 CABLE, ASM BOX
XFMR
5224923 00-886659
5269989
NON-NAV ONLY
TO C-ARM
INTERCONNECT
CABLE
TO
TO COOLING
COOLING TB3 FANS
SURGE WKST SYS/UPS FAN B1 & B2
10/20A
CIRCUIT SUPPR ON/OFF OFF B3
A BREAKERS 5340092 SWITCH SWITCH A
00-879474 00-886504 TB2
FORMAT PER PR12001
ACCESSORY
POWER GE HEALTHCARE - SURGERY
SIZE DWG NO. REV
TB4 00-885899DDW
B 26
SCALE:
NONE SHEET
2 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FRNT, LOWER LFT

EMI BOX
ASM 879137
886995 CHASSIS GND
P1
25 SUB-D SURGE SEE SHT 13
Filtered 5600pF
Signal to Shell SUPPRESSOR 1. EMI CHASSIS TO LEFT DOOR (-01)
J8 P8 886367
D A38J3 P3 5340092 P2 2. EMI CHASSIS TO RIGHT DOOR (-01) D
AC_CUR_RTN BLK BLK AC CUR RTN SEE SHT 5,6,7, D5
AC_CUR_SEN WHT
1 1
WHT AC CUR SEN
8 A38 3. EMI CHASSIS TO REAR DOOR (-01)
14 14 3
AC_VOLT_RTN BRN BLK AC VOLT RTN 4. TOP PLATE TO LOWER MONITOR ARM (-03)
2 2 6
AC_VOLT_SEN WHT
15 15
RED AC VOLT SEN
1 P4 5. UPPER MONITOR ARM TO MONITOR PLATE (-02)
RED CORD_SEL_1 SEE SHT 13 6. MONITOR PLATE TO MONITOR RT (-02)
3 4
WHT CORD_SEL_2
4 5 7. MONITOR PLATE TO MONITOR LFT (-02)
ORN CORD_SEL_3
TO J7 5 9
SYSTEMS I/F WHT CORD_SEL_4 P5
6 10
(SHT 8, C6) SEE SHT 5,6,7, D5
886338
886367
P1 A39J6 P6 J1
+12V YEL BRN +12V P5 A39J5
1 8 8 2
TO 5420489, J1 2
GND BRN
7 7
BLK GND
4 1 115 VAC PH GRY
12
(SHT 4, A4)
3
GND BLK
20 20
BLU GND
5 4 115 VAC RTN GRY/WHT
6
4 +5V RED RED +5V BLK
19 19 1 9
GND
6 ISD PWR 3 CHASSIS E5
CNTRL GRN/YEL
C GND GRY WHT 5315470 3 C
23 23 A39J8 P8 E9
LCH_WDK ORN ORN LCH_WDK
C_ARM_OFF YEL
9 9
YEL C_ARM_OFF
4 A39
10 10 3 P2 A39J2
CMD_DATA GRN GRN CMD_DATA 1 LOOP 2 ORN
11 11 6 19
PD_INT BLU BRN PD_INT 2 KEY PWR BLK
12 12 1 14
CMD_CLK VIO VIO CMD_CLK 3 LOOP 1 GRN
13 13 5 24
UPS_ON WHT BLU UPS_ON 4 CNCT ON YEL
21 21 7 22
GND BRN BLK GND 5 INT GOOD LO
22 22 8
ISD_STATUS RED RED ISD_STATUS 6 INT GOOD HI
25 25 2
INTERCONNECT CABLE
5335509: 20FT
VIDEO HI GRN
J3 P3
VIDEO HI GRN 5335510: 30FT
TO A1A1J6 1
VIDEO CNTRL VIDEO LO NTRL VIDEO LO NTRL
2
(SHT 9, C7) VIDEO SHLD SHLD VIDEO SHLD SHLD
13
PILOT HI GRN J4 P4 PILOT HI GRN

4
879426 PILOT LO NTRL PILOT LO NTRL
B PILOT SHLD SHLD PILOT SHLD SHLD
5 B
16
DC COM BLK J6 P6 DC COM BRN

15
TO J3 ARCNET HI GRN 1 1 ARCNET HI GRN
7
SYSTEMS I/F ARCNET LO NTRL 2 2 ARCNET LO NTRL
8
(SHT 8, D6) ARCNET SHLD SHLD 9 9 ARCNET SHLD SHLD
17
FRAME SYNC HI GRN 4 4 FRAME SYNC HI GRN
10
FRAMESYNC LO NTRL 5 5 FRAMESYNC LO NTRL
11
FRAME SYNC SHLD SHLD FRAME SYNC SHLD SHLD
20
887000 INT GOOD HI WHT/ORN 7 7 INT GOOD HI WHT/ORN
INT GOOD LO WHT/RED 8 8 INT GOOD LO WHT/RED
CHASSIS GND (SPARE)RED
18
15 SUB-D SHLD
Filtered 50pF
Signal to Shell E4 E2
TO DISPLAY ADPTR J7 P7
(SHT 9, B2) HI-RES VID (LEFT) CNTR HI-RES VID (LEFT) CNTR
A HI-RES VID RTN (LEFT) SHLD HI-RES VID RTN (LEFT) SHLD
21 A
23
885999
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885899DDW 26
SCALE:
NONE SHEET
3 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3 A1J3
1 +3.3V ORN
VIDEO CONTROLLER
SYSTEMS INTERFACE
SINGLE BRD COMPTER
SPARE
IMAGE PROCESSOR
DISPLAY ADAPTER
CINE BRIDGE
SINGLE BRD COMPUTER
SPARE
SPARE
SPARE
SPARE
2 +3.3V ORN
COM BLK
3
+5V RED
4
COM BLK
5
SECTION 'B'
+5V RED
6
D 7
COM BLK D
PWR OK GRY
8
+5VSB VIO
9
+12V YEL
10
11 +3.3V ORN
-12V BLU
12
COM BLK
13
PS ON GRN
14
COM BLK
15
COM BLK
16
COM BLK
5268480
5309876
17
888920
879056
886888
885796
886890 (NAV), 5266165 (NON-NAV) A1B1 (SHT 10,11)

18 -5V WHT SECTION 'B'
+5V RED P1 J1
19
+5V RED 5404996
20 POWER
P3 J3
P4 A1J4 SUPPLY
A1B2
A1B3
A1B4
A1B5
5404998 PS1
A1A1 (SHT 9)
A1A2 (SHT 8)
A1A3 5263643
A1A5 (SHT 9)
A1A6 (SHT 9)
COM BLK
A1A7 (SHT 9)
A1A4
1
COM BLK 5404868
2
+12V YEL
3
+12V YEL SATA PS1P2 PS1J2
4
C DRIVE 1
+12V YEL 1
YEL C
P1 A1J1 COM BLK BLK
+3.3V ORN FORMATTED 2
+5V BLK
2
BLK
1 3 3
+3.3V ORN 5371629 COM RED RED
2 4 4
COM BLK
3 5 5372292
DUAL PASSIVE +5V RED
(SHT 10,11)
4
COM BLK
BACKPLANE 5
6
+5V RED
5251751 (NON-NAV) 887154-02 7
COM BLK
PWR OK GRY
A1 (NAV) 887413 8
9
+5VSB VIO
SECTION 'A'
10
+12V YEL
P1 J1
SECTION 'A'
+3.3V ORN
PWR OK WHT PWR OK WHT
11 5404996
1
COM BLK
1
COM BLK
12
-12V
COM
BLU
BLK
POWER
4 4 13 P3 J3
PS ON GRN
5404998
SUPPLY
COM BLK COM BLK
14
COM BLK 5404868 PS2
1 1 15
COM BLK COM BLK COM BLK
2 2 16
P7 A1A1J7 +12V YEL +12V YEL COM BLK
3 3 17
+5V +12V YEL +12V YEL -5V WHT
2 4 4 18
B 5
COM
19
+5V RED CINE HDD A43P2 A43J2 B
+5V RED P13-15 +12V YEL
20 CINE P10-12
1 1
COM BLK
DRIVE 2 2
887153 887152 887154-01 886479-02 P2 A1J2
P4-6
3 3
COM BLK
COM BLK 5328097 P7-9 +5V RED
1 4 4
PWR OK
PWR OK
COM BLK PART OF
2 EMI FERRITE
COM
COM
COM
COM
COM
COM
+12V YEL 5330346
12V
12V
12V
12V
SECTION 'B' 3
+12V YEL
P5 4
A1J10 A1J6 A1J8 A1J7 A1J9
1 2 1 2 3 4 1 2 8 16 6 14 15 7 13 12 11 10 9 5 4 3 2 1 1 2 3 4 1 2
A1J5
P10 P6 P8 P7 P9
+12V
+12V
+12V
+12V
COM
COM
COM
COM
COM
COM
COM
COM
J2
+5V
+5V
+5V
+5V
YEL +12V
1
RED +5V
2
YEL +12V
3
RED +5V
4
YEL +12V 5 TO 886655, P2
BLK COM 6 (SHT 8, B6)
BLK COM 7
BLK COM 8
BLK COM 9
A EMI BOX BLK COM 10
A
5420489 J1
FORMAT PER PR12001
YEL +12V
1
BLK COM TO 886338, P1
2
BLK COM (SHT 3, C7)
RED +5V
3 GE HEALTHCARE - SURGERY
4
SIZE DWG NO. REV
B 00-885899DDW 26
SCALE:
NONE SHEET
4 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5269989 CB4 LN 2
A38J1 P1 P2 A38J2 AC1 BRN 1 2 BRN
AC PHASE BRN 8.5A LN 1
1 SURGE 1 125 CT
PRIMARY 1
TO POWER CORD AC NEUTRAL WHT/BLU WHT/RED 3 4 WHT/RED
3 4 113 AC2
ASSEMBLIES POWER IND + SUPPRESSOR
4 3 101
SEE SHT 13 POWER IND RTN
6 5340092 6 6 BLU 55-700481 BLU
AC PHASE A38
D AC NEUTRAL
10 0
CB3
D
12
WHT/BRN 125
P3 P4 P5
PRIMARY 2
BLU 113 AC BRN 1 2 BRN
2 1 A38J5 10A
GRN/YEL 101
TO 886367, P8 SEE SHT 13 887449 5326013 6 RTN BLU 3 4 BLU
SHT 3, D6 0
SHLD 55-700452
881062
SYS/UPS OFF SW E19
(MTG) P1 A39J1
886504 RTN
A39J11 P11 3 AC
P15 J15
BLK UPS OFF LMP 1
NEUT FLOAT
8 6 2
RED +12V 4 ISD PWR CNTRL AC2
7 6
GRN UPS OFF SW AC1
3
WHT GND
5 5315470 4 GND BLK
4 10 A39 5
SHLD SHLD
2
E7
6 887763
1 P2 A39J2
5 115VAC
C FAN B3 TO 5335509 (20 FT) OR 5335510 (30 FT), J1 C
886668 SHT 3, C5
TB4 (SEE TABLE) P5 A39J5

886665 TB2
TB4 VOLTAGE TABLE (REFERENCE) 115VAC BLK TO 5335509 (20 FT) OR 5335510 (30FT), J1
AC1 A39J4 P4
AC1 SHT 3, C5
FROM TO VOLTAGE NEUTRAL BLU 1
CONNECT CONNECT (Vac) NEU NEU
ACCESSORY 2
TB4-AC1 115VAC BLK P3 A39J3 J1 P1 ON/OFF SW
TB4-NEU 115 PWR 4
AC2 AC2 12V KEY ORN
886666
4 3 2 1
TB4-AC2 TB4-NEU 115
GND 902763 A39J10 P10 KEY PWR IN RED SW1
TB4-AC1 TB4-AC2 230 887762
887020 3 12V KEY GRN
902763 1 PWR SW LMP* BLK
2
P12 P9 887452
2 3 4 A39J12 5 3 1 A39J9
887761 WHT UPS_OFF
YEL +VDC
886667
RED TRK
B 5224923 B
LN 1 BLK
LN 2 BLK
UPS IN
SFTY GND GRN/YEL TB3
LOB 5196397 E21 BLK
1 PS1
GND
5
A42 AC1 5404868 BACKPLANE & SBC-B SEE
ACF GRN/YEL (SHT 4, C1)
8 P1
LN 1 BLK AC1
YEL +VDC LN 2 BLK 2 BLK
9 OUT
WHT UPS OFF SFTY GND GRN/YEL 2 AC2 PS2
3 5404868 BACKPLANE & SBC-A SEE
P3 NAVJ3 J1
(SHT 4, B1)
TRACKER ORN AC2 887085
5
BLK
886659 4
GRN 902764
2 PS3 F1/F2 6.3AT
A44 5321829 MONITORS TO 5335442, P12
(SHT 10, D5)
RED
7 P/O 887088
886501
A FAN B1 & B2
230 VAC
A
20-839958-00
FORMAT PER PR12001
L1
5229852 887091 TO PS4
(SHT 12, D1)
NAV OPTION SIZE
B
SCALE:
DWG NO.
00-885899DDW
SHEET
REV
26
NONE 5 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5269989 CB4 LN 2
AC PHASE BRN 8.5A LN 1
1 SURGE 1 125 CT
PRIMARY 1
3 4 113 AC2
4 3 101
6 5340092 6 6 BLU 55-700481 BLU
AC PHASE A38
D AC NEUTRAL
10 0
CB3
D
12
WHT/BRN 125
P3 P4 P5
PRIMARY 2
2 1 A38J5 10A
GRN/YEL 101
SHT 3, D6 0
SHLD 55-700452
881062
SYS/UPS OFF SW E19
(MTG) P1 A39J1
886504 RTN
A39J11 P11 3 AC
P15 J15
BLK UPS OFF LMP 1
NEUT FLOAT
8 6 2
RED +12V 4 ISD PWR CNTRL AC2
7 6
GRN UPS OFF SW AC1
3
WHT GND
5 5315470 4 GND BLK
4 10 A39 5
SHLD SHLD
2
E7
6 887763
1 P2 A39J2
5 115VAC
C FAN B3 SEE SHT 3, C5 C
886668

886665 TB2
TB4 VOLTAGE TABLE (REFERENCE) 115VAC BLK
A39J4 P4 SEE SHT 3, C5
AC1 AC1
ACCESSORY 2
TB4-NEU 115 PWR 4
AC2 AC2 12V KEY ORN
886666
4 3 2 1
TB4-AC2 TB4-NEU 115
TB4-AC1 TB4-AC2 230 887762
887020 3 12V KEY GRN
2
P12 P9 887452
2 3 4 A39J12 5 3 1 A39J9
5191898 WHT UPS_OFF
YEL +VDC
886667
B 5224923 B
LN 1 BLK
LN 2 BLK
UPS IN
SFTY GND GRN/YEL TB3
5196397 E21 BLK
1 PS1
5
A42 AC1 5404868 BACKPLANE & SBC-B SEE
GRN/YEL (SHT 4, C1)
8 P1
LN 1 BLK AC1
YEL +VDC LN 2 BLK 2 BLK
9 OUT
WHT UPS OFF SFTY GND GRN/YEL 2 AC2 PS2
3 5404868 BACKPLANE & SBC-A SEE
J1 (SHT 4, B1)
AC2 887085
902764 PS3 F1/F2 6.3AT
5321829 MONITORS TO 5335442, P12
(SHT 10, D5)
P/O 887088
886501
A FAN B1 & B2
230 VAC
A
20-839958-00
FORMAT PER PR12001
L1
5229852
UPS OPTION SIZE
B
SCALE:
DWG NO.
00-885899DDW
SHEET
REV
26
NONE 6 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5269989 CB4
AC PHASE BRN 8.5A
1 SURGE 1 125 CT
PRIMARY 1
3 4 113 AC2
4 3 101
6 5340092 6 6 BLU 55-700481 BLU
AC PHASE A38
10 0
AC NEUTRAL CB3
D 12 D
WHT/BRN 125
P3 P4 P5
PRIMARY 2
2 1 A38J5 10A
GRN/YEL 101
SHT 3, D6 0
SHLD 55-700452
881062
E19
(MTG) P1 A39J1
RTN
A39J11 P11 3
AC
1
NEUT FLOAT
6 2
4 ISD PWR CNTRL AC2
UPS OFF SW 6
AC1
GND
5 5315470 4 GND BLK
10 A39 5
887763 E7
P2 A39J2
115VAC
FAN B3 SEE SHT 3, C5
C 886668 C
886665 TB2
TB4 VOLTAGE TABLE (REFERENCE) 115VAC BLK
A39J4 P4 SEE SHT 3, C5
AC1 AC1
ACCESSORY 2
TB4-NEU 115 PWR 4
AC2 AC2 12V KEY ORN
886666
4 3 2 1
TB4-AC2 TB4-NEU 115
TB4-AC1 TB4-AC2 230
887020 3 12V KEY GRN
2
P12 P9 887452
2 3 4 A39J12 5 3 1 A39J9
5224923
B B
TB3
BLK PS1
AC1 5404868 BACKPLANE & SBC-B SEE
GRN/YEL (SHT 4, C1)
P1 AC1
2 BLK
2 AC2 PS2
5404868 BACKPLANE & SBC-A SEE
J1 (SHT 4, B1)
AC2 887085
902764 PS3 F1/F2 6.3AT
5321829 MONITORS TO 5335442, P12
(SHT 10, D5)
P/O 887088
886501 FAN B1 & B2
230 VAC
A 20-839958-00 A
L1
5229852
FORMAT PER PR12001
NON-NAV / NON- UPS OPTION SIZE DWG NO.
00-885899DDW
REV
B 26
SCALE:
NONE SHEET 7 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REAR PANEL
886884 EMI BOX
P1 B4J1
BLU 2 2 COM 886136
FAN
RED 1 1 +12V A1A2J10 P10
TO A1A1J8 WHT VC SYNC 1 P4 A1A2J4 A3J2 P2 P4 A3J4
B4 VIDEO CNTRL BLK VC RTN 2 ARCNET HI 2 ARC NET HI 2
1 1 1 FS: REMOTE DIAG
EMI FERRITE (SHT 9, B8) BLK VC RTN 3 ARCNET LO 2 ARCNET LO 2
2 2 2
43-600004 WHT VC SYNC SLV 4 ARCNET SHLD 2
879463 3 3 3 901559
FRAME SYNC HI 2 FRAME SYNC HI 2
D A1A2J3 P3 SYSTEMS 4
FRAME SYNC LO 2
4 ISOLATED 4
FRAME SYNC LO 2 D
5 5 5
DVD 1
+12V GRN ARCNET HI 1 1 INTERFACE 6
FRAME SYNC SHLD 2
6 INTERFACE 6
DIAG TXD
5393289 COM NAT ARCNET LO 1 FRAME SYNC LO SLV DIAG RXD
2
COM BLK ARCNET SHLD
2 879056 7
FRAME SYNC HI SLV
7 5268480 7
GND
3 TO J6 6 8 8 8
4
+5V EMI BOX NAT FRAME SYNC LO 1 9 A1A2 9
FRAME SYNC SLV SHLD
9 A3 9
CONFIG 0
(SHT 3, B7) GRN FRAME SYNC HI 1 SPARE CONFIG 1
BLK FRAME SYNC SHLD
10 (ISA) 10
SPARE
10 10
CONFIG 2
5 11 EMI FERRITE 11 11
887000 WHT/ORN INT GOOD HI 3 12
SPARE
43-189990 12 12
CONFIG 3
P/O 5335442 WHT/RED INT GOOD LO 8 15 SUB-D 13
+5VDC
LFT SPKR RED Filtered 50pF FRAME SYNC LO SLV
COM BLK P11 A1A2J11
886137 Signal to Shell
14
FRAME SYNC HI SLV
A3J1 P1 15
RT SPKR WHT RELAY GND
1 1
RELAY +12V
SPEAKER 2
PWR INJCT
2
A1A2J7 P7 P3 A3J3
75-149930-00 WHT AC CUR SENS
3
SPARE 1
3
PWR INJCT 1
TO J8 8 4 4 1
+12V BLK AC CUR RTN SPARE 2 XRAY ON 1
1 EMI BOX 1 5 5 2
COM (SHT 3, D7) WHT AC VOLT SENS XRAY ON RM IN USE 1
2 9 6 6 3
BRN AC VOLT RTN RM IN USE DR INT SW REFERENCE
3 2 7 7 4
886338 GRY GND SPARE 3 DR INT SW RTN
4 3 8 8 5
BRN GND DR INT SW PWR INJCT 2
4 9 9 6
C BLK GND
5 10
DR INT SW RTN
10 7
XRAY ON 2 C
WHT UPS_ON CNTL 1 RM IN USE 2
6 11 11 8
RED ISD_STATUS CNTL 1 RTN CNTL 1
7 12 12 9
ORN LCH_WDK CNTL 2 CNTL 1 RTN
10 13 13 10
TOP YEL C_ARM_OFF
11 14
CNTL 2 RTN
14 11
+5V EMI BOX GRN CMD_DATA +5V
USB 4PRT 1 12 15 15 12
COM 37 SUB-D BLU PD_INT +5V
2 13 16 16 13
HUB 3 Filtered 5600pF VIO CMD_CLK
14 17
GND
17 14
CNTL 2
902698 Signal to Shell GND CNTL 2 RTN
4 18 18 15
DIAG TXD
19 19
P10 J10 DIAG RXD
20 20
DIAG RTN
P1 A46J1 21 21
LFT SPKR RED CONFIG 0
14 14 TO SBC-B AUD 22 22 P5
COM BLK CONFIG 1
1 33 33 23 23
XRAY LAMP RT SPKR WHT (SHT 10, SHT 11, B3) CONFIG 2
2 15 15 24 24
886863 3 25
CONFIG 3
25
A46 P2 ISOLAT RLY CNTL
4 26 26
GRN +12V YEL
4 4 1
WHT COM BLK TO 5420489, J2 EMI FERRITE
23 23 6
BLK COM BLK (SHT 4, A4) 43-189966
24 24 7
B P1 A45J1 RED
5 5
+5V RED
2
A3J6 P6 B
RED GRN +12V YEL TO SBC-B
A1A2J6 P6
XRAY LAMP 1 BLU WHT
6 6
COM BLK
3 ETHERNET
2 25 25 8 6 (SHT 10, B3) 887883
886863 3
RED RED
7 7
+5V RED
4
BLU BLK COM BLK 7
A45 4 26 26 9 22 EMI FERRITE
YEL 43-189990
5 9
BLK
10 10
887106 P2 J2
11
XRAY LMP GRY XRAY LMP GRY
1 31 31 18
XRAY LMP RTN WHT XRAY LMT RTN WHT
2 13 13 19
COM WHT/BLK COM BLK
3 32 32 8
P1 A31J1 4 12
5 13
4 886655 14
3
IR RCV 11
+12V YEL
8 8
+12V 15
COM BLK COM 16
5340095 12
IR CTS RED
27 27
IR CTS RED 17
8 9 9 1
A31 7
IR RXD GRN/WHT
28 28
IR RX ORN
2
IR RTS GRN/BRN IR RTS YEL
9 10 10 3
A 6
IR TXD GRN
29 29
IR TX GRN
4
A
IR RTN BRN IR RTN BRN
10 11 11 5
AMB LIGHT 1 BLU AMB LIGHT 1 BLU
1 30 30 20
FORMAT PER PR12001
AMB LIGHT 2 VIO AMB LIGHT 2 VIO

2 12 12 21
P/O 5335442 SIZE DWG NO. REV
B 00-885899DDW 26
SCALE:
NONE SHEET
8 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3 A1A1J3 A1A5J4 P4 P5 A1A5J5 A1A6J8 P8

GND (1,3,5,7,9, 11,12,14,15,17,19,21) GND (1,4,6,8,11,14,17,18,21,23,25,28,31,34)
J3 A1A6P3 VGA SBC B (GPOS)
GND (23,25,27,29,31,33,35,37,39) LCLKH
2 2 5266165 (W/O NAV)
VC SPARE (3) LCLKL
2 2 3 3 886690 (M10, NAV)
VIDEO VC SPARE (2) LS0 886687-01
4
VC SPARE (1)
4 IMAGE 5
LS1
5 DISPLAY YEL A1B1
CONTROLLER 6
VC HSYNC*
6
PROCESSOR 7
LD0
7
ADAPTER
8 8 9 9
D 888920 10
VC VSYNC*
10 885796 10
LD1
10 5268480 D
VC PIXCLK LD2 J2 A1A6P2 VGA
A1A1 13
VC D11
13
A1A5 12
LD3
12
A1A6 SBC A (RTOS)
886688 (NAV)
16 16 13 13
(ISA) 18
VC D10
18 (PCI) 15
LD4
15 (PCI) 886687-02
5263643 (NON-NAV)
VC D9 LD5 A1A3
20 20 16 16 BLK
VC D8 RCLKH
22 22 19 19
VC D7 RCLKL
24 24 20 20
VC D6 RS0 EMI BOX
26 26 22 22
VC D5 RS1 DVI-I CONNECTIONS REAR
28 28 24 24
VC D4 RD0 J5 A1A6P5 J21
30 30 26 26
VC D3 RD1 REFER TO DETAIL 'A' DVI - EXT RT MON
32 32 27 27 FOR PINOUT
VC D2 RD2
34 34 29 29
VC D1 RD3 886688-04
36 36 30 30 GRN EMI FERRITE
VC D0 RD4
38 38 32 32 43-189990
VC FIELD RD5 J4 A1A6P4
40 40 33 33
DVI - RT MON TO J14
886142 886143 (SHT 10, SHT 11, C6)
RED 886688-01
P6 A1A1J6
8 VIDEO HI GRN J7 A1A6P7
VIDEO LO NTRL DVI - LFT MON
C 4
VIDEO SHLD SHLD TO J3, J4 TO J13 C
3 EMI BOX (SHT 10, SHT 11, D6)
(SHT 3, B8) BLU 886688-03
1 PILOT HI GRN EMI FERRITE
5 PILOT LO NTRL J6 A1A6P6 43-600004 J17
PILOT SHLD SHLD LFT MON TV
6 2 REAR PANEL EMI
1 GND J11
879426 3
LFT MON TV
TOP EMI
8 GND J5
P5 A1A1J5 J12 LFT MON TV
TOP EMI 4 TOP FRONT EMI
886853 5 GND J19
RT MON HR EXT
VCR OUT 11 REAR PANEL EMI
P8 A1A1J8 6 GND
VC SYNC WHT 12
1
VC RTN BLK TO A1A2J10 P6 7 J18
2 LFT MON HR EXT
VC RTN BLK SYS I/F 14 REAR PANEL EMI
3 (SHT 8, D5)
VC SYNC SLV WHT GND
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
7
9
4
4 13 J7
A1A5J6 LFT MON HR EXT
879463 15
GND
FRONT LOWER LFT EMI
10
885999
B B
1 DATA 2-
2 DATA 2+
3 GND
4 NC
5 NC GND (8-40 EVEN)
6 DDC CLK
886144
GND (1,2,3,5,6)
7 DDC DATA
CINE PIXCLK
CINE HDRV*
CINE VDRV*
CINE D OE*
8 VSYNC
CINE TAG*
NO CONN
CINE D10
CINE D11
9 DATA 1-
CINE D2
CINE D3
CINE D4
CINE D5
CINE D6
CINE D7
CINE D8
CINE D9
CINE D0
CINE D1
10 DATA 1+
11 GND
12 NC
13 NC A1A7J6
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
7
9
4
14 5V
15 GND P6
16 HPI
17 DATA 0-
18 DATA 0+
19
CINE HDD
GND
20 NC CINE P4 A1A7J4
GND GND
1 S1
21
22 GND
NC
BRIDGE 2
TX+ RP+ S2
23 CLK+ 5309876 TX- RP- CINE
A 24 CLK-
3
GND GND
S3
DRIVE A
4 S4
C1
C2 GRN
RED A1A7 5
RX- TP- S5 5328097
RX+ TP+
(PCI)
FORMAT PER PR12001
C3 BLU 6 S6
C4 HSYNC 7
GND GND S7
C5 GND
PART OF GE HEALTHCARE - SURGERY
DETAIL 'A' 5330346 SIZE DWG NO. REV
B 00-885899DDW 26
DVI-I PINOUT SCALE:
NONE SHEET
9 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P/O 5335442
PS3COV J1 887088 YEL +12V YEL +12V

POWER PS3COV P1 J12 P12 1 1 TOUCH KEYBOARD
BLK BLK COM YEL +12V LEFT YEL +12V RIGHT
SUPPLY 1 1 1 1 1 1
BLK COM
2
BLK COM
2 SCREEN 902742
2 2 BLK 2 2 BLK 2 2 COM 3 MONITOR 3 MONITOR
5321829 YEL F1 6.3A YEL +12V BLK COM BLK COM A41 A40
3 3 3 3 3 3 4 5364342 (BW) 4 5364343 (BW)
PS3 YEL YEL +12V
4 4
BLK
4 4
BLK
4 4
COM
5364344 (COLOR)
D 5 5
BLK
5 5
BLK
5 5
COM RT MON USB D
6 6 6 6 6 6
YEL F2 6.3A YEL +12V
7 7 7 7 7 7
8 8 YEL 8 8 YEL 8 8 +12V
887172 TOP LFT MON RT MON P/O 5220784 886764

9 SUB-D EMI
Filtered 5600pF J13 P13
Signal to Shell 886688-03 BLU BLU
EMI
TO DA J14 P14 P/O 5335442 FERRITE
(SHT 9, C1) 886688-01 RED RED
OUT OUT OUT OUT
USB HUB
902698
IN
TOP
EMI BOX
SBC P43 P6 J6 J2 USB 1 J15 P15
SBC A (RTOS) SBC B (GPOS) +5V PR1 887539-01
C 1 1
USB2- PR2
1 1
USB 2 DVD C
886688 886890 3 3
5 5
USB2+ PR2
2
3
2
3
5393289
J8 USB 2 J16 P16
A1A3 (M10 NAV) USB 7 7
GND PR1
4 4 887539-02 886842 SATA-USB CNVRTR
HDR 10 10 +5V PR3 USB 3
A1B1 8 8
USB3- PR4
5
6
5
6
5419997
USB3+ PR4 EMI J22 P22

6 6
PR3
7 7 FERRITE 887351 UPS
4 4 GND 8 8 5196397 A42
887329
TOP SBC ETHER P1 P1 J1 J9 SBC-B
EMI 1 1 TX+ PR1 7 7
TX- PR1 TO EXT I/F, J6
J9 LPT1 2 2 8 8 (SHT 8, B3)
BLK STROBE RX+ PR2 887883
1 1 1 10/100 3 3 5 5
WHT AUTOFEED GND PR3
14 2 2 ETH 4 4 4 4
2
RED DATA 0
3 3 HDR 5 5
GND PR3
3 3 M-BRKT
GRN ERROR RX- PR2
15
ORN DATA 1
4 4 6 6
GND PR4
6 6 887163
3 5 5 7 7 1 1
BLU INIT GND PR4
16 6 6 8 8 2 2
WHT/BLK DATA 2 887327
4 7 7
RED/BLK SELECT
17 8 8
GRN/BLK DATA 3
B 5
ORN/BLK GND
9 9 B
18 10 10 SBC P45 P7 J7 J3 SBC-B AUD
BLU/BLK DATA 4
6 11 11 LFT SPKR WHT RED LFT SPKR
19
BLK/WHT GND
12 12 A1A3 ETH A1B1 ETH AUDIO 7 7 COM BLK
2 2
BLK COM TO J10
7
RED/WHT DATA 5
13 13 OUT 8 8 RT SPKR RED
4 4
WHT RT SPKR (SHT 8, B6)
GRN/WHT GND 1GB 1GB 9 9 5 5
20 14 14 ETHERNET ETHERNET 887330 P/O 886655
BLU/WHT DATA 6 CAT 6 CROSSOVER 886661
8 15 15
BLK/RED GND
21 16 16
WHT/RED DATA 7
9
ORN/RED GND
17 17 887539-03
22 18 18 USB
BLU/RED ACK
10 19 19
RED/GRN GND
23 20 20 SER-USB
ORN/GRN BUSY
11 21 21 USB
BLK/WHT/RED GND 1006190
24 22 22
WHT/BLK/RED PAPER END
12 23 23 FRNT
RED/BLK/WHT END EMI BOX
25 24 24
GRN/BLK/WHT SELECT HDD SATA
13 25 25 902756 SATA J1 P1
5215547 886781 (SATA) 2
RED RX
1 1
RX (NAV A4 TX) BLK
WHT TX TX (NAV A4 RX) WHT
3 2 2
BLK GND GND RED
5 3 3
A 2 RED RX
6 6
RX (NAV A1 TX) BRN A
COM1 5 BLK GND GND GRN TO
TO DA, J3 TO DA, J2 13 13
(SHT 9, D2)
VGA
(SHT 9, D2)
VGA 3 WHT TX
14 14
TX (NAV A1 RX) BLU (SHT 12, B8)
NAV
FORMAT PER PR12001
886687-02 886687-01 SBC COM

TO BLK +5Vdc 8 +5Vdc BLK
(PS1P1) WHT +5Vdc 11 +5Vdc WHT
886550 886532
SIZE DWG NO. REV
B 00-885899DDW 26
SCALE:
NONE SHEET
10 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P/O 5335442
PS3COV J1 887088 YEL +12V YEL +12V

PS3COV P1 J12 P12 1 LEFT 1 RIGHT TOUCH KEYBOARD
POWER BLK BLK COM YEL +12V YEL +12V
1 1 1 1 1 1 2 MONITOR 2 MONITOR SCREEN 902742
SUPPLY 2 2 BLK 2 2 BLK 2 2 COM BLK COM
3
BLK COM
3
5321829 3 3
YEL
3 3
F1 6.3A YEL
3 3
+12V BLK COM
4
5364342 (BW) BLK COM
4
5364343 (BW) A41 A40
PS3 4 4 YEL 4 4 YEL 4 4 +12V 5364344 (COLOR)
BLK BLK COM
D 5 5
BLK
5 5
BLK
5 5
COM RT MON USB J1 D
6 6 6 6 6 6
7 7 YEL 7 7 F2 6.3A YEL 7 7 +12V
8 8 YEL 8 8 YEL 8 8 +12V
887172 TOP LFT MON RT MON P/O 5220784 886764

9 SUB-D EMI
Filtered 5600pF J13 P13
Signal to Shell 886688-03 BLU BLU
EMI
TO DA J14 P14 P/O 5335442 FERRITE
(SHT 9, C1) 886688-01 RED RED
OUT OUT OUT OUT
USB HUB
902698
IN
TOP
EMI BOX
SBC CN2CN3 P4 J4 J2 USB 1 J15 P15
+5V PR1 887539-01
C 1 1
USB0- PR2
1 1
USB 0
DVD C
2 2 2 2 5393289
USB0+ PR2
3 3 3 3 J7 USB 2 J16 P16
GND PR1 887539-02 886842
4 4 4 4 SATA-USB CNVRTR
+5V PR3 USB 1 5419997
5 5 5 5
USB1- PR4
6 6 6 6 J3 USB 3 J22 P22
USB1+ PR4
7 7
PR3
7 7 887539-03 887351 UPS
8 8 GND 8 8 USB 2 5196397 A42
SBC A (RTOS) SBC B (GPOS) USB
P5 J5 J8 USB 4 EMI
TOP 5263643 5266165 HDR
GND PR1 FERRITE
EMI 9 9 1 1 USB 3
J9 LPT1 A1A3 (NON-NAV) 10 10
USB2+ PR2 2 2
BLK STROBE USB2- PR2
1
WHT AUTOFEED
1 1 A1B1 11 11
+5V PR1
3 3
14 2 2 12 12 4 4
2
RED DATA 0
3 3 13 13
GND PR3
5 5 M-BRKT
GRN ERROR USB3+ PR4
15
ORN DATA 1
4 4 14 14
USB3- PR4
6 6 5270559
3 5 5 15 15 7 7
BLU INIT +5V PR3
16 6 6 16 16 8 8
WHT/BLK DATA 2
4 7 7
RED/BLK SELECT 5265237
17 8 8
GRN/BLK DATA 3
B 5
ORN/BLK GND
9 9 B
18 10 10 SBC P11 P6 J6 J1 SBC-B AUD
BLU/BLK DATA 4
6 11 11 RT SPKR RED RED LFT SPKR
BLK/WHT GND AUDIO 1 1 5 5
19 12 12 A1A3 ETH A1B1 ETH LFT SPKR WHT BLK COM TO J10
7
RED/WHT DATA 5
13 13 OUT 2 2 COM BLK
2 2
WHT RT SPKR (SHT 8, B6)
GRN/WHT GND 1GB 1GB 3 3 4 4
20 14 14 ETHERNET ETHERNET 5269349 P/O 886655
BLU/WHT DATA 6 CAT 6 CROSSOVER 886661
8 15 15
BLK/RED GND
21 16 16
WHT/RED DATA 7
9 17 17
ORN/RED GND
22 18 18
BLU/RED ACK
10 19 19
RED/GRN GND
23 20 20
ORN/GRN BUSY
11 21 21
BLK/WHT/RED GND
24 22 22
WHT/BLK/RED PAPER END HDD SATA
12 23 23 SATA
RED/BLK/WHT END 902756
25 24 24 886781 (SATA)
GRN/BLK/WHT SELECT
13 25 25
5215547 VGA TO DA, A1A6J3
(SHT 9, D3)
886687-01
A A
TO DA, J2
(SHT 9, D3) VGA 10/100
ETH
TO EXT I/F, A3J6 NON-NAV
FORMAT PER PR12001
886687-02 887883 (SHT 8, B3)
SIZE DWG NO. REV
B 00-885899DDW 26
SCALE:
NONE SHEET
11 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AC1
POWER P/O 887091
SUPPLY AC AC2
TRACKER BOX CHASSIS (NAV) A44 INPUT GND (SHT 5, A2)
PS4
WHT
ORN
ORN
ORN
GRN
GRY
RED
RED
RED
RED
BLK
BLK
BLK
BLU
BLK
BLK
BLK
BLK
YEL
VIO
902852-01
PWR OK
+5VSB
PS ON
+3.3V
+3.3V
+3.3V
+12V
COM
COM
COM
COM
COM
COM
COM
-12V
+5V
+5V
+5V
+5V
D D
NAVJ2
-5V
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
FLASHDISK
SPEAKER J8
RIBBON 1003312
A7 J3 A7P3 (+5V, +12V, GND)
POWER PRI
IDE 1003297
(MOUNT W/ LABELS FACING INSIDE BOX.

886841 AIR FLOW BLOWS INWARD)
COM1 MOTHERBOARD 1003313
KEY BOARD A1 68 PIN TRACKER BUS RIBBON CABLE
MOUSE 1005560 1005696

(+12V)
VGA VIDEO
PCI SLOT PCI SLOT
C TRANSMITTER DRIVER C
A8 J6 J10 A2 J6 J10
1005696 J3
1005967 RECEIVER #2
1005967 RECEIVER #1 A3
J4
TOP POSITION BOTTOM POSITION 1005520
J5
DB15 DB15 DB15
J2
J13 J12 J15 J15 J12 J13 J1
A8P13 A8P12 A2P12 A2P13 A3P1
A3P2
COM2
1003872 1003872
888093 P1
J1
A50 J2 J1 +5Vdc, BLK

00-902955 +5Vdc, WHT
RS232 ISOLATOR PCB
B P1
A5 B
J1 1003330
RS-232, 15 SUB-D J3 A4P2 J2 UIFB
POWER PCB
Filtered 50pF J9 A4P9
NAVP1 J1 Signal to Shell A5P3 HD15
BRN RX WHT RX (A1 TX) 9 SUB-D
TO
(SHT 10, GRN GND
6
13
BLK GND A4 Filtered 5600pF
BLU TX RED TX (A1 RX) 1007168 Signal to Shell
B2) 14 J3
BLK RX WHT RX (A4 TX)
1 A4P7 J7 J3 A4P3 TO UPS
WHT TX RED TX (A4 RX)
RED GND
2
BLK GND HD15
886531 9 SUB-D
3 (F)
WHT +5Vdc 11 GRN +5Vdc SEE
BLK +5Vdc GRN +5Vdc A4P6 J6 (SHT 5, B7)
8 A51 888093
P1
J1
886532 886529 J12 888093

00-902955
J1
P1
E1
RS232 ISOLATOR PCB A4P1 J1
FT SW 886530 (+5V, +12V, GND)
MINI PHN J11 A4P11
JACK J2
886527-02 886527-01 886528
A (+5V, +12V, GND) A
RCVR 2 RCVR 1 TX
FORMAT PER PR12001
PORT 2 PORT 1
R F RECEIVER PACK 2 R F RECEIVER PACK 1 TRANSMITTER SOURCE GE HEALTHCARE - SURGERY

SIZE DWG NO. REV
B 00-885899DDW 26
SCALE:
NONE SHEET
12 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5197599 5197599
LINE FILTER LINE FILTER
43-399892 43-399892
LINE LOAD LINE LOAD
E1 E1
LF1 LF1
D D
BLU BLU
5196804 BRN
5196804 BRN
BLU BLU
BRN BRN
J52 J52
CB1 3 1 7 9 P52 CB2 CB1 3 1 7 9 P52 CB2

10A 55-700452 10A 55-700452
20A BRN 1 2 20A BRN 1 2
TB1 A38J1 A38J1
BRN 1 2 BRN BRN 1 2 BRN
3 4 1 3 4 1
BRN BRN BRN 10 TO SURGE SUPP BRN BRN 10 TO SURGE SUPP
1
BLU 3 4 BLU BLU (SHT 5, D6) 3 4 BLU BLU (SHT 5, D6)

3 3
BLU BLU BLU 12 BLU BLU BLU 12
55-700476 55-700476
WHT/BRN 6 WHT/BRN 6
2
20A WHT/BLU 4 15A WHT/BLU 4

GRN/YEL GRN/YEL GRN/YEL
CORD_SEL_1
3
E1 2 E1 CORD_SEL_2
C RF CHOKE GND
7
TO SURGE SUPP RF CHOKE
GND
3 C
(SHT 5, D6) 7
GREEN LAMP 11 GREEN LAMP 11
AC POWER 12 AC POWER 12
6
6
8
100-127VAC CORD ASM 100-127VAC CORD ASM 8
5342154 DOMESTIC 20 AMP LANYARD A38J4
5342150 DOMESTIC 15 AMP LANYARD A38J4
5197599
LINE FILTER
43-399892
LINE LOAD INTERNATIONAL CONFIG.
E1
LF1
PART NUMBER DESCRIPTION
BLU BLU
5304930 CABLE ASM, POWER CORD, 230V, 10A, 30ft 9900, TYPE UK2-15P
B BRN BRN
B
5304528 CABLE ASM, POWER CORD, 230V, 10A, 30ft 9900, TYPE UK1-13P
CABLE ASM, POWER CORD, 230V, 10A, 30ft, TYPE AU2-10P, 9900
5318497
J52
R2 R1
5304823 CABLE ASM, POWER CORD, 230V, 10A, 30ft 9900, TYPE SW1-10P
P52
3 7
0.2 OHM 0.2 OHM
5304428 CABLE ASM, POWER CORD, 230V, 10A, 20ft 9900, TYPE L620P
CB1
10A 5197603 CABLE ASM, POWER CORD, 230V 10A 20FT 9900 NOTE: TYPE EUI-16P
A38J1
BRN 1 2 BRN BRN
BRN
1
WHT/BRN 3
5197604 CABLE ASM, POWER CORD, 230V 10A 30FT 9900 NOTE: TYPE EUI-16P
TO SURGE SUPP
BLU 3 4 BLU (SHT 5, D6)
10 5197605 CABLE ASM, POWER CORD, 250V MAX, 10A, 20ft CHINA 9900
BLU BLU
5255428 12
WHT/BRN 6 5197606 CABLE ASM, POWER CORD, 250V MAX, 10A, 30ft CHINA 9900
20A WHT/BLU 4
GREEN LAMP
GRN/YEL GRN/YEL AC POWER 5331424 CABLE ASM, POWER CORD, 230V, 10A, 30ft SI-32, 9900
RF CHOKE E1
5337057 CABLE ASM, POWER CORD, 230V, 10A, 30ft NEMA 5-15, 9900
CORD_SEL_4
A GND
5
5346331 CABLE ASM, POWER CORD, 230V, 10A, 30ft AFSNIT 107-2-D1, 9900 A
200-250VAC CORD ASM 7
6 5404053 CABLE ASM, POWER CORD, 120V, 20A, 20ft NBR14136, 9900
CORD ASSEMBLIES/LINE FILTER
NOTE: SEE INTERNATIONAL
FORMAT PER PR12001
INTERNATIONAL 8
CONFIG. TABLE FOR SPECIFIC 5404055 CABLE ASM, POWER CORD, 230V, 10A, 30ft NBR14136, 9900
LANYARD A38J4
GE P/N'S
SIZE DWG NO. REV
B 00-885899DDW 26
SCALE: SHEET
NONE 13 OF 14
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EMI BOX - REAR PANEL EMI BOX - TOP NAV EMI - RT SIDE
J17 J18 J19 J20

D D
J10 J11 J15 J13 J1
TV LFT RT S-VID
37-D USB DVI 15-D
IR RECEIVER VCR HUB
J21 SPEAKER IN
LFT MON
J2
DVI
J9 J12 J16 J14
25-D USB DVI

RM CNTRL VCR DVD
FS DICOM LPT RTOS RT MON
OUT
J3
15-D RJ45 15-HDD
J22
9-D
USB
ISOLATED EXTERNAL INTERFACE UPS
C C
EMI BOX - FRONT, LOWER LEFT EMI BOX - TOP FRONT NAV EMI - LF SIDE
J8
25-D
ISD PWR CNTRL
J1 J5
B RX1 RX2 TX B
15-D
RS 232 TV
LFT MON
J7 FOR NAV
CAMERA J3
VIDEO
PILOT
TONE J4
J6
A ARCNET
A
15-D
FRAME SYNC
INT GOOD
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-885899DDW 26
SCALE:
NONE SHEET
14 OF 14
8 7 6 5 4 3 2 1
Document Information for: 00-887453DDW
Type Drawing Print

Name 00-887453DDW
Revision A1
State Release
Description SCH, PCB, ISOLATED INTERFACE

Originator Information not available
File List
00-887453DDW_rA1.pdf
This page is generated automatically by the GEMS ePDM System

Approved Document - 00-887453DDW_rA1.pdf Page 1 of 2

Approved Document - 00-887453DDW_rA1.pdf Page 2 of 2
Document Information for: 00-888918-01SCH
Type Drawing Print

Name 00-888918-01SCH
Revision 3
State Release
ECO 2104174
Description PCB, SCHEMATIC VIDEO CONTROL
Originator 212063211_kirk_l_baldwin
File List
1. 00-888918-01SCH_s1_r3.pdf
See the GEHC Myworkshop System to determine the status of this document.

212063211_kirk_l_baldwin Approved 06/30/2010 8:51:27 PM GMT
212063211_kirk_l_baldwin Approved 06/30/2010 8:52:01 PM GMT
This page is generated automatically by the GEHC MyWorkshop System.

Approved Document - 00-888918-01SCH_r3.pdf Page 1 of 16

DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 1 3 1
U15 TP2 REVISION HISTORY
VCC VCC
74F02 R14 C87 0.01 REV EFFECTIVE DATE CHANGE # DESCRIPTION OF CHANGE ORIGINATOR OR AUTHOR
BP_VSYNC* 8 1 2 C2
10 PILOT_TONE
SYNC GENERATOR 1 01-12-07 LEGACY K. JOHNSON
2
BP_EN* 9 R46 R71 R70 4.75 LEGACY
1
1
0.01 VCC VCC
374 374 374 CR4 D U22 1146P 2 06-27-08 DCN05411 RELEASE TO MANUFACTURING N. NEWBOLD
D
1501A TDI VCC
2
U15 R170 TP6 45 SYNCGEN1 3 NA ECN1435 CHANGED PER ECN D. SEGO
74F02
1 2 TDI
1 3
R17 TMS 43
2
1
1
11 R25 4.75 TMS
1
113 2 Q1 U3 1K U5 44
CR5 9 TCLK
1K R136
1K
12 MMBT3904 AD8561 -5V A & TCLK
2
909 1501A TRST* 52 27 TDO_0
PILOT_DET
2
10 5 TRST* TDO
1
2 7
B Q U5
R172
R137
4.75K
3 8 R167 75 2 1 R140 R225
1
1
D Q2 A & XE1 1 2 75 1K 1K SIGNAL TEST POINT
MMBT3904
11
R Q
12 2 13 N_SP
B Q BBVCC 53 COLORS ARE WHITE
MSEL1
1
VCC C85 33P 74LS123 D FROM XE2 74 32
1
STATUS*
2
PILOT_HI T1 R171 R165 6 1 2
MSEL0 STATUS*
4
6
5
P6 - 1
6 1 1 2 1 2
4.75K CX 3
R Q
4 BIT-BLASTER 10 11 TP4
D C84 DCLK CFD1 D
2
P S 1 2 7 VCC PORT R173 DCLK CONF_DONE
2
301 R11 RX/CX 0.1 74LS123 D 14 78 TP34
C89 1K DATA0A
R169
5 2 R2 100K 14 DATA0 SDOUT
FROM CCD CAMERA
301
22P R164 CX CONFIG* 33 TP44 TP91
301 CONFIG*
1
2
2
15
1
1 2
D D RX/CX ICM_RDY 4 49 IOCHRDY TP11
ICM_RDY IOCHRDY
1
PILOT_LO 4 3
R163
P6 - 5 100K 54
E1
SYNC_HIZ*
2
TP7
75
CHIP_HIZ*
1
REF1
1
+5V R177 D MRST* 31
R1 TP18 RST* TP8
4.75
1
P6 - 6
1 2 D D
1
1 2
100 R41 EPF8636ALC84-3
1
1 2
D
D R21 13 56
1
U21 1 2 HSYNC*
D 332 C110 COMP_SYNC HSYNC*
100 PILOT_STBL 3 25 VSYNC*
+5V D 0.01 GS4881 PILOT_STBL VSYNC*
R246 HSYNC
1 PILOT_DET 42 66 BP_CLAMP*
C20 TP19 TP27 PILOT_DET BP_CLAMP*
0.047 8
V+ ODD 7 PIXCLK2Q 82 35 PILOT_OK
0 C19 Y2 34.093MHZ PIXCLK2Q PILOT_OK
2
VIDEO EVEN PIXCLK 12 64 CLK_OUT
VCR VIDEO VCR_ODD_EVEN PIXCLK CLK_OUT
U7
6
RSET VSYNC
3 33EN 1 5 34MHZ 28 67 33EN
1
6
0.01 EN CLK 34MHZ 33EN

2
P5 4 V+ LT1395 R178
4
GND BP
5 39MHZ 24 55 39EN
39MHZ 39EN +5V
R19 - 1
681K 62 2
COMP_SYNC
1 2 3 + EN PILOT_TONE +5V
V- PILOT_TONE PILOT_EN C56
332 C111 TP16 VCO 36 65 VCO_EN*
5
VCO VCO_EN*
2
Y1 38.934MHZ
2
0.1 0.01 D
1
2
C6
3.32K
2
R20 40 81 R124
R42
39EN VCR_HSYNC
1 5 VCR_HSYNC U1 R161
1
1 2
75 U31 EN CLK 34 U1* R162
2.21K
2
0.01 U1* 4.75 2.21K
DG411 22 D1
1
D 16 D1 R123
R244
C18 8
1
ODD_EVEN 1K
ODD_EVEN
1
0
15 14 NRZ_ODD_EVEN 58 72 DS2
1
D +5V U73
U4VP R183 NRZ_ODD_EVEN LOCKOUT
2
13
0.1 V+ VCR_ODD_EVEN 30 18 AD8561
1
D R264 4.75 VCR_ODD_EVEN 50HZ_CNT200
R43 12
VL
1 2
15 TP23
2 7
75 150K VCR60_CNT162
U4VM 4 D +5V 3 8
V- PHASE_LOCK 29 51 REF
5 PHASE_LOCK VCR50_CNT162
-5V VCRVID GND 71
C C114 C
1
QUALSYNC
1
+5V
2
D 0.01 1
R38 50HZ_CNT98
R159
4
6
5
R180 21
332 D U19 CNTH_EQ0 DS1
2K
1 2
1 2 D 61 R122
4.75 GS4981 NTSC_HCNT 1K -5V D TP35
+5V 77 +5B
R247 0.047 1
COMPSYNC V+
8 U8 U8 LN_CNTEN
1
0 MUXVID 2 7 13 12 11 10 16 U74 U10
VIDEO HSYNC 60_EQ0
1
.714 MV C112 U20 69 TEST OUTPUTS AD8561 74F02 14
3 6 74HC14 74HC14
1
C16 D 0.01 C13 VSYNC RSET 50_EQ0 2 7 5
GS4881 4 5 41 V 4 PHASE_LOCK
NORM RES VIDEO HSYNC
1 GND BP VCR60_EQ0 3 8 6
C17 NRZ_ODD_EVEN 9 G
6
2
R16 U6 0.01 8 7 VCR50_EQ0
P9 4 V+ LT1395 V+ ODD 79 7
332 - 1 2 HS_60* R121
1 2 3 + EN 0.047 VIDEO EVEN 19 750
2
V- WAS U7 6 3 HS_50* TP10 +5V 2.0V NOM
2
RSET VSYNC
4
6
5
48
2
5
4 5 R182 C115 HS_VCR_60* REF D

2
R18 GND BP TP38
1
3.32K
681K 0.1 63
R39
R181
681K
75 HS_VCR_50*
1
VIDSEL1 37 84 REF D
C113
2
C5 VIDSEL1 LOCK_RST TP20 -5V
1
0.1
VIDSEL0 7 46 D
1
1
0.01 VIDSEL0 CNT_RST REF R126
1
83 10M
V_RST U75
R245
8
73 70
1
D CLKSEL2
0
D CLKSEL2 END_FRAME CR2 R65

D U1* 6 -
U31 23 20
1
1 2
CLKSEL1 V+ 7
CLKSEL1 START_VSYNC 5 V- TP33
D DG411 CLKSEL0 57 60 1501A 1K + LF412C
1 CLKSEL0 END_VSYNC FROM PHASE DETECTOR
C15
+5V CR3 R64
4
2 3
FIRST FPGA IN CONFIGURATION D1
1
1 2
-5V U4VP C177
2
13
0.1 R263 V+ SERIAL PATH 1501A 1K L4
R4 0 REF R40 150K 12
VL D
1 2 +5V
75 U4VM 4 R34 0.1 0.47UH +5B
1.25V V- 1 2 TP26
R26 5 D
TP1 GND +5V U46 +5B
332 R166 100K
1
NRVID
1 2 4.75 74F02 14 U46 U10

+5V CLKSEL2 11 74F02 14 U10 74F02
1
D R249 D MUXVID 1 2
V 14
B 13 5 R154 74F02 R157 B
1
14
6
R3 U1 C86 12 V 4 2
V VCO
4 V+ G 6 R22
2 1 8
V 1 2 1
VIDEO_LO 332 - 1 0 0.01 G VCO_EN* 0
10 3
G
2
+ EN LT1395 7 2 1 9 0
2
1 2 3
U9 7 G
V- C123 0.01 VCC VCC 7
- 4 TP31 0
R69
7
5
75
+5V
511
R5
+5V CY7B991
2
P6 D
1
C11 10P U4 D TP90 D

2
2
D R250 C120 AD8561 E2 VCCQ
R32
1
D 1 2 CS_TEST 8
21
2
R28 VCCQ
1
1 2 2 7 2
R158 D
2
1 2
0 NC 3 9 TP12 C7
0.1 0 COMP_SYNC 1K FS VCCN R191 C38
1
3 8
332
R6
R7 332 U17 R175 C8

U16 17 16 2K 1 2 1000P
5
75 D FB VCCN TP87 Q3 43P 220P

AD8055 LT1204
1
4 - 31
TEST VCCN 18
REF MMBT3906 500V 100K
V+ 1 C109
1
1
1 16
IN0 VP C118
2 1
CLK_OUT
2
3 V- 1 25 TP25
2
+ NRVID REF VCCN R44

4
6
5
3 IN1 OUT 15 D
2
REF 1 2
0.01
2
R47 R155 R57
2
5 IN2 FB 13 1 2 0.01 C108

2
10K
2
75 100 7 10 TP55 2K
511
R13 0 REF 4F1 4Q1 R192 1000P

R12
1 2
2
IN3 SD* R31 C1
1
7 12
3
R15 D CR6
3
TP15
1 2
R29 332 R27 1K
6
4F0 4Q0
11 4.75K CR1 CR7 6.5P TO 25P
GND2 ENABLE 100 R184 R79 R176
1
2 11 1211
1
1
R8 5 14 PIX_DIV4 1211 1211
4.75 3F1 3Q1 4.75K 100K
21
75 GND4 A1 VIDSEL1 D
1
1 2 4 10 SEE TABLE A SEE TABLE A SEE TABLE A
1
1 2
4 15
1
VIDSEL0 D D 3F0 3Q0

1
1
332 C12 GND6 A0
1
6 9
1
1
332
30 19 VC_PIXCLK Q4
1
10P 2F1 2Q1
R10
8 14
-5V
6
U2 REF VN -5V PIXCLK MMBT3904

2
LT1395
29
2F0 2Q0
20 LOOP FILTER
4 V+
P6 R9 - D R168 VCC 27 23 D
1
1
R248 1F1 1Q1 D D D
1
- 8
1 2 3 + EN D 2K PIXCLK2Q
C121
V- 0 26
1F0 1Q0
24
VIDEO_HI
0.1
-5V
5
332
2
2
HI RES VIDEO
1
REF
R251
1K REF
1K REF
1K REF
1K REF
2
2
0
C88 R128 R139 R135

P6 - 3 -5V R147
R145
75 75 75
R153
R151
R149
R143
D 0.01
0
DRAWING NO. TO PART NO. CORRELATION MATRIX
1K
1
D
1
1
D
D -5V C273 C101 C68 DRAWING NO. PART NO. PART REV.
1K REF
1K REF
1K REF
REF
R30 1000P 1000P 1000P
REF
2
2
A
1 2 NOTES:
00-888918-01SCH 00-888918-01 5 A
R142
750 1. UNLESS OTHERWISE SPECIFIED:
R152
R150
R148
R146
R144
0
1K
RESISTORS ARE IN OHMS.
0
U18 VCRVID D D D
8
HRAMP R33 CAPACITORS ARE IN MICROFARADS.

1
1
1 2 2 - INDUCTORS ARE IN MICROHENRIES.
V+ 1
1K 3 V- 2. UNINSTALLED COMPONENTS ARE INDICATED BY THE REF(=NO_STUFF) PROPERTY.
+ LF412C
D THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS ORIGINAL DRAWN BY DATE
FORMAT PER PR12001
3. THE PCB ASSEMBLY PART NUMBERS FOR THIS SCHEMATIC ARE 00-888920-01 UNLESS OTHERWISE SPECIFIED
4
AND 5260471. CONFIDENTIAL AND PROPERTY OF OEC MEDICAL SYSTEMS, INC., DIMENSIONS ARE IN INCHES F. FARRINGTON 09-19-07
A UNIT OF GE HEALTHCARE AND WHOLLY-OWNED SUBSIDIARY OF
TOLERANCES ARE: DRAWING TITLE
GENERAL ELECTRIC. IT IS DISCLOSED TO YOU FOR THE SOLE ORIGINAL RESPONSIBLE ENGINEER DATE
TABLE A PURPOSE OF YOUR PERFORMANCE UNDER THE CONTRACT WITH FRACTIONS: +/- N/A
N. NEWBOLD 09-19-07 PCB SCHEMATIC, VIDEO CONTROL
D ASSEMBLY NUMBER OEC MEDICAL SYSTEMS. IT IS NOT TO BE COPIED OR IN ANY WAY
DECIMALS: X +/- N/A
DISCLOSED TO THIRD PARTIES. IT SHALL BE RETURNED TO .X +/- N/A SIZE DWG NO. REV
REF DES 00-888920-01 5260471 OEC MEDICAL SYSTEMS UPON DEMAND. YOU HEREBY AGREE TO
CR1,CR6,CR7 NOT STUFFED STUFFED THESE RESTRICTIONS AND INDEMNIFY OEC MEDICAL SYSTEMS
.XX
.XXX
+/-
+/-
N/A
N/A B 00-888918-01SCH 3
DO NOT SCALE DRAWING
FOR ALL LOSS OR DAMAGE ARISING FROM BREACH OF THIS ANGLES: +/- N/A SHEET
Wed Jun 23 08:41:36 2010 OBLIGATION BY YOU OR ENTITIES OR AGENTS UNDER YOUR CONTROL. SCALE: N/A. 1 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 2 3 1
P12 - 1
AD_IN<0>
P12 - 2
TEST PORT FOR P12 - 3
DIGITIZED DATA AD_IN<1>
P12 - 4
VC_VSYNC*
P12 - 5 P8 - 1
AD_IN<2> TO SYSTEMS
P12 - 6 P8 - 2
P12 - 7 P8 - 3 INTERFACE PCB
AD_IN<3>
P12 - 8 P8 - 4
R36
+5V C142 750 P12 - 9 SLAV_SYNC*
1 2 AD_IN<4> D
0.01 U31 P12 - 10
R66 U31 TP32
R67 DG411 +5V P12 - 11
100 DG411 VSYNC* 1 2
8 +5V AD_IN<5> VC_FIELD
HSYNC* 1 2 9 P12 - 12 P3 - 1
U4VP VC_D<0>
100 7 6 0
2
P12 - 13 P3 - 2
1
10 11 HRAMP R190
D U4VP 13
2 1 13
V+ R185 AD_IN<6>
P12 - 14 1 VC_D<1>
P3 - 3 D
V+ 4.75 4.75 VC_D<2>
+
12
VL C28 P12 - 15 2
P3 - 4
12
VL R179 4.7
2 1 U4VM 4 R55 AD_IN<7> 3 VC_D<3>
U4VM 4 V- 1 2 P12 - 16 P3 - 5
V- +5V TP47
1
4.75 5 4 VC_D<4>
5 GND 6.81K C116 P12 - 17 P3 - 6
GND WHT AD_IN<8> 5 VC_D<5>
C143 U18 P12 - 18 P3 - 7
0.01 D D 6 VC_D<6>
8
P12 - 19 P3 - 8
1
D R56 0.1
6
C35 U30 6 - AD_IN<9> 7 VC_D<7>
AVIG
+
C45 18.2K V+ 7 P12 - 20 P3 - 9
1 2 5 V- 8 VC_D<8>
4.7 -5V D 8 X1 VP + LF412C P12 - 21 P3 - 10
0.01 +5V AD_IN<10> VC_D<9>
C30 X2 + AD835 P12 - 22 9
P3 - 11
R63
4
7
PU1000 10 VC_D<10>
1 2 W D
2
+1 5 P12 - 23 P3 - 12
4.75 0.1 1 Y1 R37 AD_IN<11> 11 VC_D<11>
D + R186 P12 - 24 P3 - 13
C33 2 Y2 2.87K C117 VC_D<11..0>
4.75
6
U48 TP3 PU1000 P12 - 25 P3 - 14
VN Z 0.1 VC_HSYNC*
TP61 P12 - 26 P3 - 15
X1 VP R35 +5V
1
0.1 8 U32 VC_VSYNC*
D + AD835 2.87K P12 - 27 P3 - 16 TO IMAGE PROCESSOR
4
U32 X2 R58 VC_VSYNC* VC_HSYNC*
1
7
8
R62 W 1 2 2 - D -5V P12 - 28 P3 - 17

1
2
5
1 2 6 - +1 V+ 1 CS_TEST
V+ 7 1 Y1 274K 3 V- C14 P12 - 29 P3 - 18
2.21K 5 V- + + LF412C -5V R203 VC_FIELD
+ LF412C 2 Y2 4.7 D C178 P12 - 30 P3 - 19
4.75
+
C31 VN Z 0.01 P12 - 31 P3 - 20
4
PU1000G TP48
4
PIXCLK
TP49 P12 - 32 P3 - 21
1
2
PU1000G 7 R81
3
4
WHT R60 0.1 D D 3 1 2 P12 - 33 P3 - 22
+ HSYNC*
2
8 V+ P12 - 34 P3 - 23
1
4.75
U47 332
1
D -5V C42 TRIM
16.2K
P12 - 35 P3 - 24
R80
6
4.7 U29 +2.5V REFERENCE OP177 VSYNC*
1
TRIM P12 - 36 P3 - 25
D AD680 VCC
-5V +5V 1 V- 2 P12 - 37 P3 - 26
VERTICAL ANTI-VIGNETTING
1
+2.500V - ODD_EVEN
D 6 4 P12 - 38 P3 - 27
OUT D
3 R202 C41 P12 - 39 P3 - 28
C U67
+5V 2
TEMP 2 1
P12 - 40 P3 - 29 C
DAC_MAX505 IN 4.75 0.01
R127 GND D JUMPER P12-39 TO P12-40 P3 - 30
22 2 1 -5V D REF TO DISABLE A/D LATCHES

RD VDD +5 HORIZONTAL ANTI-VIGNETTING 4 R105 P3 - 31
DAC_WR* 17 3 4.75 R104 (U44 & U45) FOR TESTING.
WR VSS -5 1 2 1 2 P3 - 32
C58 332 332 P3 - 33
DAC_LCH* VC_PIXCLK
8
LDAC 0.1 D C236 D P3 - 34
ISA_A<1> +5V
1 18
A1 R230 0.01 P3 - 35
0 ISA_A<0> 19 2 1
A0 P3 - 36
4.75 P3 - 37
D 7 R101
2
7 ISA_D<7> 9 3 1 2
D7 R118 + P3 - 38
2
U61 8 V+
ISA_D<6>
REF
10 23 332
R88
R86
6 1 2
576
332
ISA_A<19..0> D6 VOUTD P3 - 39
REF
TRIM
R102
6
332
5 ISA_D<5> 11 1K C44 C175
D5 R117 OP177 REF P3 - 40
ISA_D<4> +5V 0.1 0.1
4 12
D4 VOUTC
24 1 2
TP50 TRIM R109
1
2
ISA_D<3> 13 4.75 1 V- 2
1
3 1 2
+5V
REF
D3 R115 C29 D - +5V
C48
56P
2 ISA_D<2> 14 1 1 2 C27 R59 D 4 332
D2 VOUTB 0.01 1K R89 D
ISA_D<1> 15 1K 0.01 332 R229 C235
1
1 D
C240
D1
R256
0.01
2 1
2
1 2 D
1
ISA_D<0>
0
16 2
1
0 1 2
D0 VOUTA 4.75 D
+5V R61 0.01
R261
R114 C32 D U59 R110 R228 U50
ISA_D<15..0> 1K D
-5V 4.75
0
4.75 0.01
220P
20
C43
LT1395 1 2
VREFD D D L8 L9 5MHZ LP 4 V+ 74F574
21 R72 L10 R90 - 1 332 1.25V AD_LCHEN* 1
VREFC
1
2
2 1 1 2 1 2 1 2 1 2 3 + EN TP60 PIXCLK
4 V- 11
0.1
VREFB U64
2
0.01
0.01
75 0.47UH 5.6UH 332

0.1
2
5
5 1.8UH 2 VDD WHT TO CRCT PLD
2
2
VREFA C34 TP43 C234
R119
R82
INPT
100
0.01 C46 1 4 17 AD_IN<0>
75
0
C39 D7 Q7
1
R92
C233
C228
75
AD_IN<1>
C232
C230
C239
0.01
6
AGND 180P 470P 4 S1 0.01 7
D6 Q6
14 1
C52 D 5 3.25V D
7 +5V 6 S2 8 13 AD_IN<2>
1
2
DGND TP51 U49 D5 Q5

1
1
0.01 GND 3
1
ADG819 AD_IN<3>
R257
D 5 16 3
D U46 WHT ADS800 D4 Q4
B
0
74F02 14 2
U63
16 23
D 6
D3 Q3
15 AD_IN<4> 4 B
VIDSEL0 D VDD CLK REFT
1
2 9 12 AD_IN<5> 5
D D V 1 D BP_CLAMP* 1 INPT 18 22 D2 Q2
3 OE CM ODD_EVEN 3 18 VC_FIELD
G 4 S1 19 21 D1 Q1
-5V MSBI REFB TO I.P.
2
D 5 1 2 2 19
REF 7 R99 6 S2 D0 Q0
R94 1 2 GND 3 R201
R116
R84
ADG819
1K
1K
1 2 +5V 24 13
R91 301 +VSA B12 1K
0 332 20
+VSA B11 12
0.082UH 1 2 R259 VCC D
17 11
1
L11 20% 25MHZ LP L13 D +VS B10
R78 L12
2 1 1 2 1 2 1 2
D 0 15
+VS B9
10
+5V D DIGITIZED DATA
6
+5V 75 0.39UH 1UH 10% U60 C50 0.01 9

+5V 4 V+ B8
R93 - 1 R100 2VPP MAX 26 8 TO CRCT PLD
R254 R255 C238 C237 1 2 + EN C51 IN B7
2
6
LT1395 10 U62 2VPP MAX
2
47P V- D 0.1 27 7
2
R187 82P 332 1 2 4 V+ LT1395 R97 IN B6

5
R188 0 0 - 1 1 2 6
+5V
2
4.75 C179 + EN B5
R95
3
4.75 C119
75
2
C145 -5V V- 10 1 5
2
C180 0.01 C49 0.01 GND B4
2
0.1 R252
5
U66
2
MUXVID 0.01 50V R106 14 4

1
2
R103 GND B3
1
68.1
50V R262
1
0 D D R96 150 150K 25 3 74F574

REF
AGND B2
R85
332
REF
U27 0.01 1
R87
332
28 2
C122 D D 0 AGND B1 PIXCLK 11
1
LT1204
1
0.1
1
D C26 47P D D
D TO CRCT PLD
1
1 16
IN0 VP
1
-5V
REF
IN1 OUT D 4 17 AD_IN<6>

C47
56P
3 15 6
D D D D D7 Q7
1
R52 D
14
5 IN2 FB 13 1 2 1 2 R53 3 18 AD_IN<7> 7

13
1 2
R108 D6 Q6
12
6
- V+ V+ 7 IN3 SD* 12 R49 1K 221
1 2
U43 REF R107 NOTE: B1 IS MSB, B12 IS LSB 5 16 AD_IN<8> 8
1K 1 2 1 2
ON OUTPUT OF ADS800. D5 Q5
4 +RG NC R50 2 GND2 ENABLE 11 332 R74 R77 +5V 6 15 AD_IN<9> 9
+5V
2
R48 I 1 2 DELAY 1 2 49.9 332 D4 Q4

LMH6502 10
AD_IN<10>
R111
6
909 VG 4 GND4 A1 10
332 REF 10T20NS R258 2
D3 Q3
19 10
R54
174
68.1
2 15 VREF 4 V+ R205 332 D

AD_IN<11>
2
-RG GND U28
6 GND6 A0 9
- 1 1 12 IN U45 C176 7
D2 Q2
14 11
6
3 V- V- 3 + EN R204 0 0 C54 VC_HSYNC*

HSYNC*
2
+ 8
REF VN
14
V- 75 14 1 2 4 V+ LT1395 R83 0.01 8
D1 Q1 13
9
- 1 150K TO I.P.
1
LT1395 R206 REF 0 VSYNC* VC_VSYNC*

2
10% 9 12
5
D
11
AVIG 13 1 2 3 + EN 0.01 D0 Q0
A
8
U44
2
A R207 REF 0 V- U65 R112 C55

6
7
D 20% 3 1 2 D D AD_IN<11..0>
R253
10 0.1
1
5
LT1395
C146
0.01
R208 REF 4 V+
2
0
30%
2
1.8UH
0 2
2
12 1 - 1 1 2 D
L1
40% R209 REF 0

D
1 2 3 + EN
REF
4 1 2 V-
R51
332
2
R98 475
R73
332
R210 REF 0
5
COM
50%
2
C144 11 1 2 R260
REF
0.1 +5V R113

R75
R193 R211 REF 0

332
C147 D 60% 5 1 2
150
1
R76
D
1
R194
750
0.1 4.75 0
1
70% R212 REF 0

4.75 U46 -5V 10 1 2
REF
C25
56P
FORMAT PER PR12001
74F02 80% R213 REF 0 C53 -5V
1
D
1
14 6 1 2
D
1
MAGSEL0
1
8
1
R214 REF
REF
V 10 90% 9 1 0 2 0.01 D
C40
56P
MAGSEL1 9 D
D G 100%
-5V -5V D
7 D
8 71 2
REF R215 D
0 SIZE DWG NO. REV
R216
D
1 2 REF
D B 00-888918-01SCH 3
75
N/A SHEET
Wed Jun 23 07:25:09 2010 SCALE: 2 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 3 3 1
TP64
RED
PIXEL INTERPOLATOR 857P
+5V U68
1
FL2 U76 CRCT
EMI FL INTERP_DIS 122
7805 INTERP_DIS
ISA_+12V R120 7A 50V GAIN_BYPASS 154
1 2 1 3 1 IN OUT 3 GAIN_BYPASS VCC
ANALOG +5V GAM_BYPASS 49
6.2 GND GAM_BYPASS
ISA_GAIN* 85
2.25W ISA_GAIN*
TP69 ISA_GAM* 62
+
TP14 TP9 C61 C57 ISA_GAM*
1
FL1 4.7 0.1 BLK VCC ISA_GAMP* 136
VCC RED RED ISA_GAMP*
EMI FL R200 R226
1
7A 50V XE5 120 1K 1K
1
1 2
1 3 N_SP
D DIGITAL +5V 84 D
2
MSEL1
TP21 TP37 TP5 TP13 XE6 1 2 117
+
C10 C37 D MSEL0
BLK BLK BLK BLK D DCLKA 1 4 CFD2 TO DECODER PLD
68 68 DCLK CONF_DONE
1
DATA0A 12 37 STAT_CRCT*
TP71 DATA0 STATUS*
1
+5V_SEN FL3 R227 CFD1 40 128
P7 1 - U77 YEL CONFIG* SDOUT
+5VDC 1K FROM SYNCGEN
P7 2 - D EMI FL
7905 116
1
R125 7A 50V MRST*
2
P7 3 - RST*
+3.3V_SEN TP30 TP86 ISA_-12V 1 12 3 2 IN OUT 3 ANALOG -5V D CRCT_HIZ* 36
P7 4 - V3.3 REF GND CHIP_HIZ*
U26 YEL YEL 6.2
P7 5 - LT1117 2.25W 1 EPF8452AQC160-3
P7 6 - 3.3V C59
1
TP17
2
3 VIN VOUT 2 C62 0.1 PIXCLK 5 27 PIXDAT<11> 11
P7 7 - DIGITAL +3.3V -5V PIXCLK PIXDATA11
GND TP24 TP84 4.7 BLK 123 PIXDAT<10>
+
10
P7 8 - PIXDATA10
+
+
1 C23 C90 C60 BLK BLK 109 PIXDAT<9>
1
9
POWER
+
C24 PIXDATA9
68 0.1 68 11 PIXDAT<8> 8
68 PIXDATA8
1
129 PIXDAT<7> 7
TP88 PIXDATA7
D D 6 ICM<6> 56 58 PIXDAT<6> 6
ICM6 PIXDATA6
U33 YEL 5 ICM<5> 153 15 PIXDAT<5> 5
ICM5 PIXDATA5
D R68 78L05 ICM<4> 51 159 PIXDAT<4>
1
4 4
D 1 2 8 IN OUT 1 ICM4 PIXDATA4 CORRECTED VIDEO DATA
ISA_+12V +5B ICM<3> 57 114 PIXDAT<3>
GND VCO +5V 3
ICM3 PIXDATA3 3
TO GAMMA AND GAMMA' LUT'S
100 144 18
2 ICM<2> PIXDAT<2> 2
C36 2 3 6 7 C21 ICM2 PIXDATA2
+
C141 C78 C22 FROM IMAGE ICM<1> 55 113 PIXDAT<1>
+
1 1
4.7 0.01 0.1 0.01 CORRECTION MAP (ICM) ICM1 PIXDATA1
4.7 0 ICM<0> 143 106 PIXDAT<0> 0
VCC ICM<6..0> ICM0 PIXDATA0 PIXDAT<11..0>
11 OFFSET<11> 87 152 OFFSUB<11> 11

OFFSET11 OFFSUB11
D 10 OFFSET<10> 150 112 OFFSUB<10> 10
OFFSET10 OFFSUB10
1
9 OFFSET<9> 89 97 OFFSUB<9> 9
OFFSET9 OFFSUB9
C R141 R174 D 8 OFFSET<8> 68
OFFSET8 OFFSUB8
54 OFFSUB<8> 8 C
2
1K 1K 131 151
7 OFFSET<7> OFFSUB<7> 7
R23 OFFSET7 OFFSUB7
6 OFFSET<6> 65 30 OFFSUB<6> 6
2
10K VCC OFFSET6 OFFSUB6

R134 5 OFFSET<5> 88 25 OFFSUB<5> 5
2 1 OFFSET5 OFFSUB5
OFFSET<4> 146 50 OFFSUB<4>
1
4 4
1K U12 OFFSET4 OFFSUB4
VCC 3 OFFSET<3> 23 22 OFFSUB<3> 3
74HCT244 OFFSET3 OFFSUB3 OFFSET SUBTRACTOR
27
28
29
30
32
31
1
FROM LAST FPGA D 1 E3 2 OFFSET<2> 63 26 OFFSUB<2> 2 TO GAIN LUT
EN 2 CONFIG DS3 FROM OFFSET LUT OFFSET2 OFFSUB2
CONF_DONE CFG_DONE* 19 DONE OFFSET<1> 115 8 OFFSUB<1>
27
28
29
30
32
1 1
31
EN 1 10 20 OFFSET1 OFFSUB1
ISA_OFS* 10 20 0 OFFSET<0> 35 145 OFFSUB<0> 0
OFFSET<11..0> OFFSET0 OFFSUB0 OFFSUB<11..0>
2
9 19
DCLK 8 12 DCLKA 9 19
1 - P10 A3 2 Y3 8 EMI_ENCLOS 18
GND 6 14 DCLKB 8 90116701 18 11 GAIN<11> 77 99
2 - P10 A2 Y2 7 17 GAIN11 PMX0
CONF_DONE 4 16 DATA0A 7 17 10 GAIN<10> 138
3 - P10 A1 Y1 6 16 GAIN10
VCC 2 18 DS3_DRV* 6 16 9 GAIN<9> 139
4 - P10 A0 Y0 5 15 GAIN9
CONFIG* TO FIRST FPGA BANK_SEL<2> 11 9 ICM<15> 5 15 8 GAIN<8> 6
5 - P10 A3 1 Y3 4 14 GAIN8
BBVCC TO FIRST FPGA R132
2 1K 1 13 7 4 14 7 GAIN<7> 149
6 - P10 A2 Y2 3 13 GAIN7
STATUS* TO FIRST FPGA R131
2 1K 1 15 5 3 13 6 GAIN<6> 61
7 - P10 A1 Y1 2 12 GAIN6
BBGND R133
2 1K 1 17 3 2 12 5 GAIN<5> 59
8 - P10 A0 Y0 1 11 GAIN5
DATA0 1 11 4 GAIN<4> 141
9 - P10 GAIN4
22
23
24
25
26
21
GND D 3 GAIN<3> 79
10 - P10 U11 XU11 GAIN3
R189 2 GAIN<2> 134
EPC1 GAIN2
22
23
24
25
26
21
2
BIT-BLASTER PORT 0 FROM GAIN LUT 7

2 DCLK DATA 1 1 2 1 GAIN<1>
R45 GAIN1
3 OE 0 GAIN<0> 44
4.75K GAIN<11..0> GAIN0
4 CS CASC 6
D 9 104
GAMMA<11> VC_D<11>
1
11 11
GAMMA11 IP_VID11
EPLD CONFIGURATION EPROM 10 GAMMA<10> 135 43 VC_D<10> 10
+5VMB
D D GAMMA10 IP_VID10
9 GAMMA<9> 45 157 VC_D<9> 9
GAMMA9 IP_VID9
B 8 GAMMA<8> 66
GAMMA8 IP_VID8
19 VC_D<8> 8 B
7 GAMMA<7> 78 96 VC_D<7> 7
GAMMA7 IP_VID7
C190
C241
C194
C249
C181
C189
C183
C185
C251
C242
C252
C245
C256
C187
C247
C186
C191
C192
C248
C188
C182
C243
C184
C246
C244
C193
C254
C250
C253
C255
6 GAMMA<6> 29 24 VC_D<6> 6
GAMMA6 IP_VID6
5 GAMMA<5> 64 17 VC_D<5> 5
GAMMA5 IP_VID5
4 GAMMA<4> 42 105 VC_D<4> 4
GAMMA4 IP_VID4 TO IMAGE PROCESSOR
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
VCC 3 GAMMA<3> 32 95 VC_D<3> 3

GAMMA3 IP_VID3
2 GAMMA<2> 31 125 VC_D<2> 2
FROM GAMMA LUT GAMMA2 IP_VID2
1 GAMMA<1> 10 110 VC_D<1> 1
GAMMA1 IP_VID1
0 GAMMA<0> 142 20 VC_D<0> 0
GAMMA<11..0> VC_D<11..0>
C170
C203
C264
C100
C231
C129
C262
C211
C296
C271
C164
C134
C198
C257
C278
C322
C268
C311
C169
C217
C205
C216
C166
C158
GAMMA0 IP_VID0
C76
C72
C66
C73
C4
11 AD_IN<11> 90 102 ICMDLY3<6> 6

D A/DIN11 ICMDLY3_6
10 AD_IN<10> 137 101 ICMDLY3<5> 5
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
A/DIN10 ICMDLY3_5
9 AD_IN<9> 158 132 ICMDLY3<4> 4
A/DIN9 ICMDLY3_4
8 AD_IN<8> 33 156 ICMDLY3<3> 3
A/DIN8 ICMDLY3_3
7 AD_IN<7> 111 16 ICMDLY3<2> 2
TP39 A/DIN7 ICMDLY3_2
AD_IN<6> 48 103 ICMDLY3<1>
C214
C159
C153
C131
C321
C210
C269
C212
C157
C201
C137
C261
C135
C208
C140
C219
C204
C149
C294
C151
C263
C215
C133
C199
C138
C260
C167
C196
C104
C213
6 1
A/DIN6 ICMDLY3_1
C67
C65
C94
C83
C79
C69
C95
C96
C93
C71
BLK 86 73 TO GAIN LUT

5 AD_IN<5> A/DIN5 ICMDLY3_0 ICMDLY3<0> 0
127 ICMDLY3<6..0>
1
4 AD_IN<4>
A/DIN4
AD_IN<3> 47
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
3
A/DIN3
2 AD_IN<2> 76
A/DIN2
1 AD_IN<1> 34
A/DIN1
AD_IN<11..0> 0 AD_IN<0> 52
A/DIN0
DIGITIZED VIDEO DATA
C207
C266
C223
C195
C220
C258
C221
C267
C172
C162
C128
C197
C105
C103
C136
C225
C174
C202
C295
C160
C227
C209
C152
C139
C107
C124
C98
C97
C82
C74
C70
C81
V3.3 A
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
A
C259
C171
C303
C155
C168
C125
C150
C163
C148
C229
C173
C130
C280
C161
C127
C272
C102
C132
C226
C270
C222
C154
C265
C293
C156
C206
C165
C200
C106
C224
C218
C312
C314
C320
C276
C292
C318
C316
C301
C288
C284
C286
C302
C291
C300
C274
C283
C298
C289
C299
C313
C277
C281
C275
C315
C287
C282
C317
C290
C285
C297
C319
C75
C99
C77
C92
C80
C91
C3
FORMAT PER PR12001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
SIZE DWG NO. REV
D D
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:25:27 2010 SCALE: 3 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 4 3 1
JTAG TEST PORT ISA ADDRESS DECODER
1 - P11 U72 381P
+5VMB VCC
ISA ADDRESS BUFFERS TDI TDO_0 72
2 - P11 TDI DECODER
TMS 76
3 - P11 TMS +POWER
TMS TCLK 74
2
4 - P11 TCLK +IO_POWER
U82 TRST* 54 120 TDO1
5 - P11 VCC TRST* TDO R217 R195
74HCT244 TCLK TO ICM PLD
R239 +5VMB 6 - P11 XE101 207 1K
1 2 1 2
N_SP 1K
EN 2 C310 7 - P11 49
1K 19 20 TP74 REF MSEL1
1
EN 1 VCC TRST*
D
TP73 8 - P11 XE9 1 2 4 TO ICM PLD
0.01 +5VMB MSEL0 153 CFD3
R238 REF 9 - P11 158 CONF_DONE
DCLKB
2
2 1 8 12 BP_VSYNC* TP82 DCLK 108
A3 2 Y3 TDO DEC_STAT*
2
1K AEN 6 14 ISA_AEN REF 10 - P11 R220 DATA0A 147
DATA0
STATUS*
198
A2 Y2
1
R218 D 103 SDOUT TP58
ISARESET4 ISA_RESET 1K CFD2
A1 Y1
16
10K CONFIG*
1
D REF
BALE 2 18 ISA_BALE D 9
D A0 Y0 ISA_RESET D
1
E4 ISA_RESET
LA<23> 11 9 ISA_LA<23> 1 2 161 197
1
SLAV_SYNC* A3 1 Y3 2 RST* MRST*
ISA BUS INTERFACE EDGE CONNECTOR LA<22> 13
A2 Y2
7 ISA_LA<22> DEC_HIZ* 150
RST* MRST*
1
CHIP_HIZ*
LA<21> 15 5 ISA_LA<21>
IOCHK* A1 Y1
P1 - A1 SBHE* LA<20> 17 3 ISA_LA<20> C126 EPF8636AQC208-4
SD<7> P2 - C1 A0 Y0 7 143
P1 - A2 LA<23> 0.01 PIXCLK GAM_SEL<0>
P2 - C2 CLK R6_0 TP42
SD<6> 136 GAM_SEL<1>
P1 - A3 LA<22> R6_1
SD<5> P2 - C3 41
P1 - A4 LA<21> U85 TP76 GAM_SEL<2>
P2 - C4 R6_2
SD<4> D 144 SPARE2
P1 - A5 74HCT244
1
LA<20> R234 +5VMB REF TP77 R6_3
SD<3> P2 - C5 1 2 1 148
P1 - A6 EN 2 C307 GAMP_SEL<0>
P2 - C6 LA19 REF TP45 R6_4 TP29
1
SD<2> 1K 19 20 160 GAMP_SEL<1>
P1 - A7 EN 1 VCC
D
P2 - C7 LA18 D REF TP46 R6_5
SD<1> 0.01 40
1
P1 - A8 GAMP_SEL<2>
P2 - C8 LA17 REF R6_6
SD<0> IOR* 8 12 ISA_IORD* 146
1
P1 - A9 A3 2 Y3 SPARE3
1
P2 - C9 MEMR* ISA_BALE 162 R6_7
IOCHRDY IOW* 6 14 ISA_IOWR* BALE 180 MEMCS16*
P1 - A10 A2 Y2
1
P2 - C10 MEMW* ISA_AEN 65 MEMCS16*
AEN SMEMR* 4 16 ISA_SMEMR* AEN* 205 SRDY
P1 - A11 SD<8> A1 Y1
SA<19> P2 - C11 SMEMW* 2 ISA_SMEMW* ISA_SMEMW* 81 MEM_ACS
P1 - A12 A0 Y0
18 SMEMWR* 163 ISA_VIDCTRL*
SD<9> ISA_SMEMR* 77 ISA_VIDCTRL*
SA<18> P2 - C12 19 SA<19> 11 9 ISA_A<19> 19 SMEMRD* 58
P1 - A13 SD<10> A3 1 Y3 VC_IO_DEC
P2 - C13 ISA_IOWR* 145 VC_IO_DEC (NO CONNECT)
SA<17> 18 SA<18> 13 7 ISA_A<18> 18
VCC IO_WR* 172 VC_RD*
P1 - A14 SD<11> A2 Y2 112 VC_RD*
SA<16> P2 - C14 SA<17> 15 ISA_A<17> ISA_IORD*
P1 - A15 17
A1 Y1
5 17 IO_RD* 176 VC_IO_RD
SD<12> VC_IO_RD
SA<15> P2 - C15 16 SA<16> 17 3 ISA_A<16> 16
P1 - A16 SD<13> A0 Y0 29
SA<14> P2 - C16 ISA_ICM*
10K2
10K2
10K2
10K2
P1 - A17 ISA_ICM*
SD<14> 178 ICM_CE*
SA<13> P2 - C17 U84 10K RESISTORS ICM_CE*
P1 - A18 SD<15> INSTALLED
SA<12> P2 - C18 R236 74HCT244 10
P1 - A19 +5VMB ISA_GAM*
R233
R222
R198
R196
1 2 1
EN 2 C308 ISA_GAM*
SA<11> 31 GAM_CE*
P1 - A20 MEMCS16* 1K 19 20 R197 752 129 GAM_CE*
1
P2 - D1 EN 1 VCC 1 REV<3>
D
SA<10> R7_3 181 GAM_WR*
P1 - A21 IOCH16* D 0.01 R219 752 166 GAM_WR*
SA<9> P2 - D2 1 REV<2> R7_2 8
P1 - A22 SA<15> ISA_A<15> GAM_OE*
P2 - D3 IRQ10 15 8
A3 2 Y3
12 15 R221
1 752 REV<1> 168 GAM_OE*
SA<8> R7_1
P1 - A23 IRQ11 14 SA<14> 6 14 ISA_A<14> 14 REF R232 752 22 179 ISA_GAMP*
C SA<7> P2 - D4 A2 Y2 1 REV<0> C
P1 - A24 R7_0 ISA_GAMP*
IRQ12 13 SA<13> 4 16 ISA_A<13> 13 184 GAMP_CE*
SA<6> P2 - D5 A1 Y1 GAMP_CE*
P1 - A25 IRQ15 12 SA<12> 2 18 ISA_A<12> 12 93 GAMP_WR*
SA<5> P2 - D6 A0 Y0 GAMP_WR*
P1 - A26 IRQ14 11 SA<11> 11 9 ISA_A<11> 11 152 GAMP_OE*
SA<4> P2 - D7 A3 1 Y3 GAMP_OE*
P1 - A27 DACK0* 10 SA<10> 13 7 ISA_A<10> 10 D
SA<3> P2 - D8 A2 Y2 80 ISA_VMSK*
P1 - A28 DRQ0 9 SA<9> 15 5 ISA_A<9> 9 ISA_VMSK*
SA<2> P2 - D9 A1 Y1 75 VMSK_CE*
P1 - A29 DACK5* 8 SA<8> 17 3 ISA_A<8> 8 VMSK_CE*
SA<1> P2 - D10 A0 Y0 99 86 VMSK_WR*
P1 - A30 VMSK_WREN
P2 - D11 DRQ5 VMSK_WREN VMSK_WR*
SA<0> 169 VMSK_OE*
P1 - A31 DACK6* U83 VMSK_OE*
P2 - D12
ISA_GND DRQ6 R237 74HCT244 +5VMB 195 ISA_GAIN*
P1 - B1 P2 - D13 1 2 1 TP79 88 ISA_GAIN*
ISARESET EN 2 C309 PILOT_OK GAIN_CE*
P1 - B2 P2 - D14 DACK7* R7_7 39
1K 19
EN 1 VCC
20 CFG_DONE* 201 GAIN_CE*
D
DRQ7 R7_6 56 GAIN_WR*
P1 - B3 P2 - D15 D 0.01 59 GAIN_WR*
PHASE_LOCK
1
IRQ9 R7_5 199 GAIN_OE*
P1 - B4 P2 - D16 7 SA<7> 8 12 ISA_A<7> 7 84 GAIN_OE*
A3 2 Y3 VSYNC*
P1 - B5 ISA_-5V P2 - D17 MASTER* R7_4
SA<6> ISA_A<6> ISA_OFS*
2
C63 6 6
A2 Y2
14 6 64
P1 B6 DRQ2 P2 D18 ISA_GND ISA_OFS*
- - SA<5> ISA_A<5> OFS_CE*
R231
100P 5 4
A1 Y1
16 5 28
10K
ISA_-12V OFS_CE*
P1 - B7 4 SA<4> 2 18 ISA_A<4> 4 79 OFS_WR*
SRDY* A0 Y0 OFS_WR*
P1 - B8 3 SA<3> 11 9 ISA_A<3> 3 183 OFS_OE*
ISA_+12V A3 1 Y3 OFS_OE*
1
P1 - B9 2 SA<2> 13 7 ISA_A<2> 2 48
ISA_GND A2 Y2 ISA_LA<23>
P1 - B10 LA23 94 BANK_SEL<0>
1 SA<1> 15 5 ISA_A<1> 1
ISA_LA<22> 203 R0_0
SMEMW* A1 Y1 D LA22 30
P1 - B11 SA<0> ISA_A<0> BANK_SEL<1>
0 17
A0 Y0
3 0
ISA_LA<21> 57 R0_1
SMEMR* LA21 38 BANK_SEL<2>
P1 - B12 202 R0_2
IOW* ISA_A<19..0> ISA_LA<20>
P1 - B13 LA20 90 BANK_SEL<3>
+5VMB 19 ISA_A<19> 97 R0_3
IOR* ISA_A19 42 BANK_SEL<4>
P1 - B14 95 R0_4
SA<19..0> 18 ISA_A<18>
P1 - B15 DACK3* ISA_A18 43 BANK_SEL<5>
ISA DATA BUFFERS 17 ISA_A<17> 100 R0_5
DRQ3 ISA_A17 170 BANK_SEL<6>
2
P1 - B16 62 R0_6 (NO CONNECT)

ISA_A<16>
DACK1* TP72 TP89 16

ISA_A16 24 BANK_SEL<7>
P1 - B17 R130 U80 167 R0_7 (NO CONNECT)
+5VMB 15 ISA_A<15>
DRQ1 REF REF ISA_A15
B P1 - B18
REFRESH*
1K 74HCT245 C279 14 ISA_A<14> 98
ISA_A14 R1_0
149 RST_ACC B
P1 - B19 ISA_VIDCTRL*
1
19 G3 VCC
20 ISA_A<13> 192 87 RST_PEAK
1
13
P1 - B20 SYSCLK ISA_A13 R1_1
3 EN1 [BA] 0.01 12 ISA_A<12> 83 70 RST_FLTR
P1 - B21 IRQ7 VC_RD* ISA_A12 R1_2
1 3 EN2 [AB] 11 ISA_A<11> 13 189 AUTO_RST_EN
P1 - B22 IRQ6 ISA_A11 R1_3
10 ISA_A<10> 15 175 INTERP_DIS
P1 - B23 IRQ5 ISA_A10 R1_4
1 B 9 ISA_A<9> 11 177 RECURSEL
P1 - B24 IRQ4 ISA_A9 R1_5
15 SD<15> 9 2 11 ISA_D<15> 15
ISA_A<8> 196 191 RECURS_BYPASS
IRQ3 A 8
ISA_A8 R1_6
P1 - B25 14 SD<14> 8 12 ISA_D<14> 14 14 188
A B 7 ISA_A<7> VLI_EN_ALL
P1 - B26 DACK2* TP85 ISA_A7 R1_7
13 SD<13> 7 13 ISA_D<13> 13
ISA_A<6> 142
TC A B 6
ISA_A6 66
P1 - B27 RED SD<12> ISA_D<12> DAC_WR*
12 6
A B
14 12
5 ISA_A<5> 101 DAC_WR*
BALE ISA_A5 68 DAC_LCH*
P1 - B28 SD<11> 5 15 ISA_D<11> 194 DAC_LCH*
1
11 11
+5VMB A B 4 ISA_A<4>
P1 - B29 ISA_A4
10 SD<10> 4 16 ISA_D<10> 10
ISA_A<3> 12 23 VMSK_BANK0
OSC A B 3
ISA_A3 R2_0
P1 - B30 TP66 9 SD<9> 3 17 ISA_D<9> 9 61 173
ISA_A<2> VMSK_BANK1
+
ISA_GND A B 2
ISA_A2 R2_1
P1 - B31 C64 BLK 8 SD<8> 2 18 ISA_D<8> 8 204 190 TP41
A B 1 ISA_A<1> VMSK_BANK2
68 ISA_A1 R2_2
ISA_A<0> 45 71 VMSK_BANK3
1
0
U86 ISA_A0 R2_3
116 SPARE1
1
+5VMB R2_4
74HCT245 C306 185 GAIN_BYPASS
R2_5
ISA_VIDCTRL* 19 G3 20 ISA_A<19..0> 44 GAM_BYPASS
VCC
D
R2_6 TP40
3 EN1 [BA] 0.01 135 AVG_BYPASS
D R2_7
D VC_RD* 1 3 EN2 [AB]
REF
186 TP59
CAM_GAIN<0>
R3_0
1
73 CAM_GAIN<1> TP78
REF
50 mil trace required on pcb to 1 B R3_1
115 CAM_GAIN<2> TP80
REF 1
7 SD<7> 9 2 11 ISA_D<7> 7 R3_2
connect gnd's together. A 187
SD<6> ISA_D<6> CAM_GAIN<3> TP83
8 12 R3_3
REF1
6 6
A B 114 TP28
SD<5> 7 13 ISA_D<5> R3_4 CAM_GAIN<4>
REF 1
5 5
A B 128
SD<4> ISA_D<4> CAM_GAIN<5> TP36
REF
4 6
A B
14 4 R3_5
1
A SD<3> 5 15 ISA_D<3> R3_6
37 CAM_GAIN<6> TP22 A
REF 1
3 3
A B 21
SD<2> ISA_D<2> CAM_GAIN<7>
2 4
A B
16 2 R3_7
REF1
1 SD<1> 3 17 ISA_D<1> 1
ISA_D<7> 63 134 BP_EN*
A B
1
7
ISA_D7 R4_0
0 SD<0> 2 A B 18 ISA_D<0> 0
6 ISA_D<6> 119 165 VIDSEL0
ISA_D6 R4_1
ISA_D<15..0> 5 ISA_D<5> 118 69 VIDSEL1
SD<15..0> ISA_D5 R4_2
4 ISA_D<4> 117 127 MAGSEL0
ISA_D4 R4_3
FORMAT PER PR12001
3 ISA_D<3> 92 85 MAGSEL1
ISA_D3 R4_4
2 ISA_D<2> 113 82 CLKSEL0
ISA_D2 R4_5
174 89
1
0
ISA_D<1>
ISA_D<0> 133
ISA_D1 R4_6
126
CLKSEL1
CLKSEL2
ISA_D0 R4_7 SIZE DWG NO. REV
ISA_D<15..0>
CLKSEL2=0 SELECTS 25FPS
REGISTERS AT I/O ADDRESSES
CLKSEL2=1 SELECTS 30FPS B 00-888918-01SCH 3
220H TO 237H
N/A SHEET
Wed Jun 23 07:25:58 2010 SCALE: 4 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 5 3 1
IMAGE CORRECTION MAP

CONTROLLER PLD
U79 388P
ICM_CE* 68 ICM
ICM_CE*
V3.3 ISA_BALE 69
ISA_BALE
ISA_SMEMR* 6 OFFSET-CORRECTED
ISA_RD* VIDEO DATA
ISA_SMEMW* 73 147 ICM_RDY
2
ISA_WR* ICM_IOCHRDY FROM CRCT PLD ISA INTERFACE
R129 ISA_ICM* 72 TO SYNCGEN PLD
ISA_ICM* OFFSUB<11..3> U38
1K ISA_OFS* 129
D VLI_IOCHRQ* 62
ISA_OFS* 74HCT245 D
VLI_IOCHRQ* 19 ISA_GAIN*
1
TDO1 55 95 TDO2 G3
TDI (I/O = 3.3V) TDO ISA INTERFACE GAIN LOOK-UP TABLE (LUT) 3 EN1 [BA]
TMS 59 TO VLI PLD
TMS VCC U35 (ILLUMINATED CORRECTION) 1 ISA_SMEMR*
TCLK 57 3 EN2 [AB]
TCLK 74HCT244 U36
TRST* 40 ISA_GAIN* 1
VCC TRST* EN 2 TC551664
B 1
19 SPEED=15_NS
2
EN 1 XE3 1 2 40 15 GAIN<15> 11 9 ISA_D<15> 15
XE8 1 2 1 UB 2 A
N_SP R223 R240 XE4 1 2 39 14 GAIN<14> 12 8 ISA_D<14> 14
38 1K BANK_SEL<1> 8 12 OFFSUB<11> 11 LB B A
MSEL1 1K A3 2 Y3 GAIN_CE* 6 13 GAIN<13> 13 7 ISA_D<13> 13
XE7 1 2 3 BANK_SEL<0> 6 14 OFFSUB<10> 10 CS B A
MSEL0 A2 Y2 GAIN_WR* 17 12 GAIN<12> 14 6 ISA_D<12> 12
2
120 118 WR B A
1
DCLKA CFD4 14 ISA_A<14> 4 16 OFFSUB<9> 9
DCLK CONF_DONE A1 Y1 GAIN_OE* 41 11 GAIN<11> 15 5 ISA_D<11> 11
R243 DATA0A 113 83 STAT_ICM* 13 ISA_A<13> 2 18 OFFSUB<8> 8 RD B A
DATA0 STATUS* A0 Y0 10 GAIN<10> 16 4 ISA_D<10> 10
1K D CFD3 81 152 TO VLI PLD 12 ISA_A<12> 11 9 OFFSUB<7> 7 B A
CONFIG* SDOUT TP65 A3 1 Y3 D 9 GAIN<9> 17 3 ISA_D<9> 9
TP53 11 ISA_A<11> 13 7 OFFSUB<6> 6 64K X16 B A
TP67 A2 Y2
1
GAIN<8> ISA_D<8>
1 REF
SRAM 8 18 B A 2 8
MRST* 87 10 ISA_A<10> 15 5 OFFSUB<5> 5
REF
RST* A1 Y1 OFFSUB<11> GAIN<15>
1 REF
ISA INTERFACE 35 TP81 11 18
A15 D15
38 15
ICM_HIZ* 9 ISA_A<9> 17 3 OFFSUB<4> 4
(VCC = 3.3V) CHIP_HIZ* TP54 A0 Y0 10 OFFSUB<10> 19 37 GAIN<14>
1
14
A14 D14 U34
REF
U81 EPF8636AQC160-3 OFFSUB<9> GAIN<13>
REF
9 20 36 13
A13 D13 74HCT245
1
74LCX16245 8 OFFSUB<8> 21 35 GAIN<12> 12
25 PIXCLK 116 76 ICM_CAS* A12 D12 19 ISA_GAIN*
1
OE2 PIXCLK RAM_CAS* U37 7 OFFSUB<7> 24 32 GAIN<11> 11
G3
143 ICM_RAS* A11 D11
DIR2 [BA] RAM_RAS* 74HCT244 6 OFFSUB<6> 25 31 GAIN<10> 10
3 EN1 [BA]
ISA_SMEMR* 24 HSYNC* 7 56 ICM_WR* IMAGE CORRECTION MAP (ICM) ISA_GAIN* 1 A10 D10 1 ISA_SMEMR*
DIR2 [AB] HSYNC* RAM_WE* EN 2 5 OFFSUB<5> 26 30 GAIN<9> 9
3 EN2 [AB]
ICM_CE* 48 58 ICM_CS* 19 A9 D9
OE1 RAM_CS* EN 1 4 OFFSUB<4> 27 29 GAIN<8> 8
1 VSYNC* 115 130 ICM_CKE A8 D8
DIR1 [AB] VSYNC* RAM_CKE 3 OFFSUB<3> 42 16 GAIN<7> 7 B 1
RAM_DQ<15..0> 8 ISA_A<8> 8 12 OFFSUB<3> 3 A7 D7 7 GAIN<7> 11 9 ISA_D<7> 7
DIR1 [BA] A3 2 Y3 6 ICMDLY3<6> 43 15 GAIN<6> 6
2 A
CLKSEL2 142 14 ICM_UDQM 7 ISA_A<7> 6 14 ICMDLY3<6> 6 A6 D6 6 GAIN<6> 12 8 ISA_D<6> 6
CLKSEL2 RAM_DQMH U78 A2 Y2 5 ICMDLY3<5> 44 14 GAIN<5> 5 B A
13 ICM_LDQM 6 ISA_A<6> 4 16 ICMDLY3<5> 5 A5 D5 5 GAIN<5> 13 7 ISA_D<5> 5
B7 RAM_DQML SDRAM_256MBIT V3.3 A1 Y1 4 ICMDLY3<4> 1 13 GAIN<4> 4 B A
15 ISA_D<15> 26 23 ICM_D<15> 5 ISA_A<5> 2 18 ICMDLY3<4> 4 A4 D4 4 GAIN<4> 14 6 ISA_D<4> 4
C 14 ISA_D<14> 27
A7
22 ICM_D<14> 18 79 15 PIXCLK 38
SPEED=7E
1 4 ISA_A<4> 11
A0 Y0
9 ICMDLY3<3> 3
3 ICMDLY3<3> 2
A3 D3
10 GAIN<3> 3
3 GAIN<3> 15
B A
5 ISA_D<3> 3
C
A6 B6 ISA_DB15 RAM_DQ15 CLK VDD A3 1 Y3 2 ICMDLY3<2> 3 9 GAIN<2> 2 B A
13 ISA_D<13> 29 20 ICM_D<13> 156 28 14 37 14 3 ISA_A<3> 13 7 ICMDLY3<2> 2 A2 D2 2 GAIN<2> 16 4 ISA_D<2> 2
A5 B5 ISA_DB14 RAM_DQ14 CKE VDD A2 Y2 1 ICMDLY3<1> 4 8 GAIN<1> 1 B A

A4 2 B4 ISA_DB13 RAM_DQ13 CAS VDD A1 Y1 0 ICMDLY3<0> 5 7 GAIN<0> 0 B A
A3 B3 ISA_DB12 RAM_DQ12 RAS VDDQ A0 Y0 B A
10 ISA_D<10> 33 16 ICM_D<10> 24 22 11 16 9
A2 B2 ISA_DB11 RAM_DQ11 WE VDDQ
9 ISA_D<9> 35 14 ICM_D<9> 19 99 10 19 43
A1 B1 ISA_DB10 RAM_DQ10 CS VDDQ ICMDLY3<6..0> GAIN<15..0>
8 ISA_D<8> 36 13 ICM_D<8> 155 101 9 15 49 OFFSET LOOK-UP TABLE (LUT)
A0 B0 ISA_DB9 RAM_DQ9 DQML VDDQ VCC (NON-ILLUMINATED CORRECTION) ONLY 12 LSB'S USED
159 105 8 39 U70
B7 ISA_DB8 RAM_DQ8 DQMH U52
7 ISA_D<7> 37 12 ICM_D<7> 153 77 7 28 74HCT245
A7 ISA_DB7 RAM_DQ7 VSS
2
42 125 PD431000
6 ISA_D<6> 38 11 ICM_D<6> 6 41
G3 19 ISA_OFS*
A6 B6 ISA_DB6 RAM_DQ6 VSS R199 OFS_WR* 29
5 ISA_D<5> 40 9 ICM_D<5> 158 122 5 54 ISA INTERFACE 1K WE
A5 B5 ISA_DB5 RAM_DQ5 VSS OFS_CE* 22 & 3 EN1 [BA]
4 ISA_D<4> 41 8 ICM_D<4> 102 74 4 6 D CS1 1 ISA_SMEMR*
A4 1 B4 ISA_DB4 RAM_DQ4 VSSQ 30 & 3 EN2 [AB]
ISA_D<3> 43 6 ICM_D<3> 151 23 CS2
1
3 3 12
A3 B3 ISA_DB3 RAM_DQ3 VSSQ OFS_OE* 24 &
2 ISA_D<2> 44 5 ICM_D<2> 47 98 2 46 OE 1
A2 B2 ISA_DB2 RAM_DQ2 VSSQ ICM<15> B
1 ISA_D<1> 46 3 ICM_D<1> 21 104 1 52 15
15 OFFSET<15> 11 9 ISA_D<15> 15
A1 B1 ISA_DB1 RAM_DQ1 VSSQ FROM U4 15
ICM<15> 2 21 OFFSET<15> 15
2 A
0 ISA_D<0> 47 2 ICM_D<0> 90 91 0 A16 I/O 7 14 OFFSET<14> 12 8 ISA_D<14> 14
ISA_D<15..0> A0 BUFFER B0 ISA_DB0 RAM_DQ0 SHEET 3 14
ICM<14> 31 20 OFFSET<14> 14 B A
137 ICM_ADRS<12> 36 53RAM_DQ<15> 15 A15 I/O 6 13 OFFSET<13> 13 7 ISA_D<13> 13
RAM_ADR12 A12 DQ15 13
ICM<13> 3 19 OFFSET<13> 13 B A
139 64 ICM_ADRS<11> 35 51RAM_DQ<14> 14 A14 I/O 5 12 OFFSET<12> 14 6 ISA_D<12> 12
BA1 RAM_ADR11 A11 DQ14 12
ICM<12> 28 18 OFFSET<12> 12 B A
138 12 ICM_ADRS<10> 22 50RAM_DQ<13> 13 A13 I/O 4 11 OFFSET<11> 15 5 ISA_D<11> 11
BA0 RAM_ADR10 A10 DQ13 11
ICM<11> 4 17 OFFSET<11> 11 B A
RAM_ADR9 A9 DQ12 10
ICM<10> 25 15 OFFSET<10> 10 B A
RAM_ADR8 A8 DQ11 U53 9
ICM<9> 23 14 OFFSET<9> 9 B A
RAM_ADR7 A7 DQ10 74HCT244 8
ICM<8> 26 13 OFFSET<8> 8
B A
127 ICM_ADRS<6> 31 44RAM_DQ<9> 9
ISA_OFS* 1 A9 I/O 0
RAM_ADR6 A6 DQ9 EN 2 7
ICM<7> 27
34 ICM_ADRS<5> 30 42RAM_DQ<8> 8 19 A8
RAM_ADR5 A5 DQ8 EN 1 7 CAM_GAIN<7> 5
17 ICM_ADRS<4> 29 13RAM_DQ<7> 7 A7
RAM_ADR4 A4 DQ7 6 CAM_GAIN<6> 6
61 ICM_ADRS<3> 26 11RAM_DQ<6> 6 BANK_SEL<1> 8 12 ICM<14> 14 A6
B BANK_SEL<5> 66
RAM_ADR3
52 ICM_ADRS<2> 25
A3 DQ6
10RAM_DQ<5> 5 BANK_SEL<0> 6
A3 2 Y3
14 ICM<13> 13
5 CAM_GAIN<5> 7
A5 B
ADD19 RAM_ADR2 A2 DQ5 A2 Y2 4 CAM_GAIN<4> 8 ISA INTERFACE
BANK_SEL<4> 128 148 ICM_ADRS<1> 24 8 RAM_DQ<4> 4 14 ISA_A<14> 4 16 ICM<12> 12 A4
ADD18 RAM_ADR1 A1 DQ4 A1 Y1 3 CAM_GAIN<3> 9
BANK_SEL<3> 134 50 ICM_ADRS<0> 23 7 RAM_DQ<3> 3 13 ISA_A<13> 2 18 ICM<11> 11 A3 128K x8
ADD17 RAM_ADR0 A0 DQ3 A0 Y0 2 CAM_GAIN<2> 10
BANK_SEL<2> 11 5 RAM_DQ<2> 2 12 ISA_A<12> 11 9 ICM<10> 10 A2 SRAM
ADD16 DQ2 A3 1 Y3 1 CAM_GAIN<1> 11
BANK_SEL<1> 71 103 ICM<15> 15 21 4 RAM_DQ<1> 1 11 ISA_A<11> 13 7 ICM<9> 9 A1
ADD15 LUT_ADD15 BA1 DQ1 A2 Y2 0 CAM_GAIN<0> 12
BANK_SEL<0> 31 43 ICM<14> 14 20 2 RAM_DQ<0> 0 10 ISA_A<10> 15 5 ICM<8> 8 A0
ADD14 LUT_ADD14 BA0 DQ0 A1 Y1
14 ISA_A<14> 123 44 ICM<13> 13 PACK_TYPE=TSOPII 9 ISA_A<9> 17 3 ICM<7> 7
ADD13 LUT_ADD13 A0 Y0
13 ISA_A<13> 124 112 ICM<12> 12 U69
ADD12 LUT_ADD12 U51
12 ISA_A<12> 135 46 ICM<11> 11 74HCT245
ADD11 LUT_ADD11 U54 PD431000
11 ISA_A<11> 94 10 ICM<10> 10 19 ISA_OFS*
ADD10 LUT_ADD10 ISA_OFS* 74HCT244 OFS_WR* 29 G3
10 ISA_A<10> 8 110 ICM<9> 9 1 WE
ADD9 LUT_ADD9 EN 2 OFS_CE* 22 & 3 EN1 [BA]
9 ISA_A<9> 9 92 ICM<8> 8 19 CS1 1 ISA_SMEMR*
ADD8 LUT_ADD8 EN 1 30 & 3 EN2 [AB]
8 ISA_A<8> 78 111 ICM<7> 7 CS2
ADD7 LUT_ADD7 OFS_OE*24 &
7 ISA_A<7> 132 108 ICM<6> 6 8 ISA_A<8> 8 12 CAM_GAIN<7> OE 1
ADD6 LUT_ADD6 A3 2 Y3 B
6 ISA_A<6> 29 89 ICM<5> 5 7 ISA_A<7> 6 14 CAM_GAIN<6> 7 OFFSET<7> 11 9 ISA_D<7> 7
ADD5 LUT_ADD5 A2 Y2 15
ICM<15> 2 21 OFFSET<7> 7
2 A
5 ISA_A<5> 133 114 ICM<4> 4 6 ISA_A<6> 4 16 CAM_GAIN<5> A16 I/O 7 6 OFFSET<6> 12 8 ISA_D<6> 6
ICM<14> 31 20 OFFSET<6> 6 B A
ICM<13> 3 19 OFFSET<5> 5 B A
ADD2 LUT_ADD2 A3 1 Y3 12
ICM<12> 28 18 OFFSET<4> 4 B A
ICM<11> 4 17 OFFSET<3> 3 B A
ICM<10> 25 15 OFFSET<2> 2 B A
1 ISA_A<1> 17 3 CAM_GAIN<0> A11 I/O 2 1 OFFSET<1> 17 3 ISA_D<1> 1
A0 Y0 9
ICM<9> 23 14 OFFSET<1> 1 B A
TO LUT ADDRESS LINES A10 I/O 1 0 OFFSET<0> 18 2 ISA_D<0> 0
ISA_A<19..0> 8
ICM<8> 26 13 OFFSET<0> 0
B A
ISA_A<19..0> A9 I/O 0
ICM<15..0> 7
ICM<7> 27
A8
7 CAM_GAIN<7> 5
A7
6 CAM_GAIN<6> 6 ISA_D<15..0>
A6
A 5 CAM_GAIN<5> 7
A5
A
4 CAM_GAIN<4> 8 ONLY 12 LSB'S USED
A4
3 CAM_GAIN<3> 9 OFFSET<15..0>
A3 128K x8
2 CAM_GAIN<2> 10
A2 TO CRCT FPLD
SRAM
1 CAM_GAIN<1> 11
A1
0 CAM_GAIN<0> 12
FROM DECODER PLD A0
FORMAT PER PR12001
CAM_GAIN<7..0>
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:26:14 2010 SCALE: 5 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 6 3 1
GAMMA PRIME (GAMP) LUT

ISA INTERFACE
U14
ISA_A<19..0> U25
SRAM_32KX8
74HCT245
SPEED=15_NS
G3 19 ISA_GAMP*
GAMP_WR* 27
9 8 CFG_DONE* WE &
VLI FUNCTIONS U8 74HC14
GAMP_CE* 20
CE
3 EN1
3 EN2
[BA]
[AB] 1 ISA_SMEMR*
U71 354P GAMP_OE* 22 &
OE
ISA_VMSK* 28 VLI
D VC_IO_RD 31
ISA_VMSK*
123 SRDY* ISA INTERFACE GAMP_SEL<2> 1 19 GAMP_D<7>
7 B 1 D
VC_IO_RD SRDY* A14 I/O 7 7
GAMP_D<7> 11 9 ISA_D<7> 7
GAMMA LOOK-UP TABLE (LUT) SRDY 18 142 VLI_IOCHRQ* U24 GAMP_SEL<1> 26 18 GAMP_D<6>
6
2 A
ISA INTERFACE SRDY_IN VLI_IOCHRQ* A13 I/O 6 6
GAMP_D<6> 12 8 ISA_D<6> 6
U41 TDO2 17 102 TDO 74HCT244 GAMP_SEL<0> 2 17 GAMP_D<5>
5 B A
U39 TDI TDO ISA_GAMP* 19 A12 I/O 5 5
GAMP_D<5> 13 7 ISA_D<5> 5
SRAM_32KX8 TMS 29 TO JTAG PORT VCC EN 11 PIXDAT<11> 23 16 GAMP_D<4>
4 B A
74HCT245 TMS A11 I/O 4 4
GAMP_D<4> 14 6 ISA_D<4> 4
SPEED=15_NS TCLK 27 10 PIXDAT<10> 21 15 GAMP_D<3>
3 B A
19 ISA_GAM* TCLK 11 ISA_A<11> 11 9 PIXDAT<11> 11 A10 I/O 3 3
GAMP_D<3> 15 5 ISA_D<3> 3
GAM_WR* G3 VCC TRST* 45 A3 Y3 PIXDAT<9> 13 GAMP_D<2> B A
2
27 9 24 2
2
WE & TRST* 10 ISA_A<10> 13 7 PIXDAT<10> 10 A9 I/O 2 2
GAMP_D<2> 16 4 ISA_D<2> 2
GAM_CE* 20 3 EN1 [BA] A2 Y2 8 PIXDAT<8> 25 12 GAMP_D<1>
1 B A
CE 1 ISA_SMEMR* R138 R224 9 ISA_A<9> 15 5 PIXDAT<9> 9 A8 I/O 1 1
GAMP_D<1> 17 3 ISA_D<1> 1
GAM_OE* 3 EN2 [AB] XE121 1 A1 Y1 PIXDAT<7> 11 GAMP_D<0> B A
22
OE & 2
N_SP 1K 1K 7 3
A7 I/O 0 0
0
U24 44 8 ISA_A<8> 17
A0 Y0 3 PIXDAT<8> 8 GAMP_D<0> 18 B A 2 ISA_D<0> 0
6 PIXDAT<6> 4
MSEL1 TO BIT A6
1
B 1 XE111 2
1
74HCT244 GAM_SEL<2> 1 19 GAMMA<15> 15 2 BLASTER PORT 5 PIXDAT<5> 5
ISA_GAM* 1 A14 I/O 7 15 GAMMA<15> 11 9 ISA_D<15> 15 MSEL0 A5
EN GAM_SEL<1> 26 18 GAMMA<14> 14
2 A DCLKB 125 124 CONF_DONE 4 PIXDAT<4> 6
A13 I/O 6 14 GAMMA<14> 12 8 ISA_D<14> 14 DCLK CONF_DONE U13 A4
GAM_SEL<0> 2 17 GAMMA<13> 13 B A DATA0A 129 82 STAT_VLI* 3 PIXDAT<3> 7
2
12 ISA_A<12> 8 12 PIXDAT<11> 11 A12 I/O 5 13 GAMMA<13> 13 7 ISA_D<13> 13 D DATA0 STATUS* 74HCT244 A3
A3 Y3 11 PIXDAT<11> 23 16 GAMMA<12> 12 B A CFD4 81 97 ISA_GAMP* 1 2 PIXDAT<2> 8 ISA_D<15..0>
R235
ISA_A<11> 6 14 PIXDAT<10> A11 I/O 4 GAMMA<12> 14 6 ISA_D<12> CONFIG* SDOUT EN 2 A2
10K
11 10 12 12
A2 Y2 10 PIXDAT<10> 21 15 GAMMA<11> 11 B A 19 1 PIXDAT<1> 9
10 ISA_A<10> 4 16 PIXDAT<9> 9 A10 I/O 3 11 GAMMA<11> 15 5 ISA_D<11> 11 EN 1 A1
A1 Y1 9 PIXDAT<9> 24 13 GAMMA<10> 10 B A MRST* 94 RST* 0 PIXDAT<0> 10
9 ISA_A<9> 2 18 PIXDAT<8> 8 A9 I/O 2 10 GAMMA<10> 16 4 ISA_D<10> 10 A0
A0 Y0 B A 14
1
8 PIXDAT<8> 25 12 GAMMA<9> 9 VLI_HIZ* 7 ISA_A<7> 8 12 PIXDAT<7> 7
A8 I/O 1 9 GAMMA<9> 17 3 ISA_D<9> 9 CHIP_HIZ* A3 2 Y3
7 PIXDAT<7> 3 11 GAMMA<8> 8 B A 6 ISA_A<6> 6 14 PIXDAT<6> 6
A7 I/O 0 8 GAMMA<8> 18 2 ISA_D<8> 8 EPF8820AQC160-4 A2 Y2
U23 6 PIXDAT<6> 4 B A 5 ISA_A<5> 4 16 PIXDAT<5> 5
A6 A1 Y1 NOTE: ONLY 10 MSB'S OF PIXEL DATA
74HCT244 5 PIXDAT<5> 5 PIXCLK 33 4 ISA_A<4> 2 18 PIXDAT<4> 4 ARE REQUIRED FOR GAMMA'. THE 2
ISA_GAM* 1 A5 PIXCLK A0 Y0
EN 2 4 PIXDAT<4> 6 PIX_DIV4 113 3 ISA_A<3> 11 9 PIXDAT<3> 3 LSB'S HAVE BEEN INCLUDED TO
19 A4 PIXCLK_4 A3 1 Y3 FACILITATE HOOKUP.
EN 1 3 PIXDAT<3> 7 2 ISA_A<2> 13 7 PIXDAT<2> 2
A3 TP68 A2 Y2
2 PIXDAT<2> 8 VSYNC* 70 1 ISA_A<1> 15 5 PIXDAT<1> 1
8 ISA_A<8> 8 12 PIXDAT<7> 7 A2 V_SYNC* A1 Y1
A3 2 Y3 1 PIXDAT<1> 9 HSYNC* 65 TP75 0 ISA_A<0> 17 3 PIXDAT<0> 0
7 ISA_A<7> 6 14 PIXDAT<6> 6 A1 H_SYNC* A0 Y0
A2 Y2
1
0 PIXDAT<0> 10
6 ISA_A<6> 4 16 PIXDAT<5> 5 A0
A1 Y1 U40 98 ACTIVE
U42 25FPS ACTIVE PIXDAT<11..0>
1
5 ISA_A<5> 2 18 PIXDAT<4> 4 100 GAMP_D<7..0>
A0 Y0 74HCT245 CLKSEL2 5 VLI_EN
C 4 ISA_A<4> 11
A3 1 Y3
9 PIXDAT<3> 3 SRAM_32KX8
19 ISA_GAM* RST_PEAK 89
30FPS VLI_EN
73 VMSK_WREN C
ISA_A<3> PIXDAT<2> G3 RST_PEAK VMSK_WREN
3 13
A2 Y2
7 2 SPEED=15_NS 72 50 TP56
RST_ACC
2 ISA_A<2> 15 5 PIXDAT<1> 1 GAM_WR* 27 3 EN1 [BA] RST_ACC VMSK_RD

A1 Y1 WE & 1 ISA_SMEMR* RST_FLTR 78 106 VMSK_ISA_EN* TP57
1 ISA_A<1> 17 3 PIXDAT<0> 0 GAM_CE* 20 3 EN2 [AB] RST_FLTR VMSK_ISA_EN* REF
A0 Y0 CE AUTO_RST_EN 88 49 VMSK_ADRS_EN
AUTO_RST_EN VMSK_ADRS_EN
1
GAM_OE* 22 &
OE VLI_EN_ALL 7 42 AUTO_RST
B 1 VLI_EN_ALL AUTO_RST
1
ISA_A<19..0> GAMMA<7> ISA_D<7> RECURS_BYPASS 134
NOTE: A0 IS NOT USED BECAUSE OF 1 19 7 11 2 A 9 7
RECURS_BYPASS
GAM_SEL<2> GAMMA<7> 7
16-BIT ADDRESSING ON SOME RAMS. A14 I/O 7 6 GAMMA<6> 12 8 ISA_D<6> 6 RECURSEL 132 141
GAM_SEL<1> 26 18 GAMMA<6> 6 B A RECURSEL ST_LCH_EN
A13 I/O 6 5 GAMMA<5> 13 7 ISA_D<5> 5 AVG_BYPASS 90 96
GAM_SEL<0> 2 17 GAMMA<5> 5 B A AVG_BYPASS SP_LCH_EN
IN VIDEO MODE, PIXDAT<11..0> IS A12 I/O 5 4 GAMMA<4> 14 6 ISA_D<4> 4 20
11 PIXDAT<11> 23 16 GAMMA<4> 4 B A VMSK_BANK3 84 HLD_CNT_EN
DRIVEN BY THE CRCT FPGA AND IS A11 I/O 4 3 GAMMA<3> 15 5 ISA_D<3> 3 VMSK_ADRS_HI3
10 PIXDAT<10> 21 15 GAMMA<3> 3 B A VMSK_BANK2 130 TEST
A TRI-STATE 12-BIT BUS. A10 I/O 3 2 GAMMA<2> 16 4 ISA_D<2> 2 VMSK_ADRS_HI2 68 OUTPUTS
9 PIXDAT<9> 24 13 GAMMA<2> 2 B A VMSK_BANK1 74 ISA_TST ISA INTERFACE
A9 I/O 2 1 GAMMA<1> 17 3 ISA_D<1> 1 VMSK_ADRS_HI1 150
8 PIXDAT<8> 25 12 GAMMA<1> 1 B A VMSK_BANK0 71 HS_TST U57
A8 I/O 1 0 GAMMA<0> 18 2 ISA_D<0> 0 VMSK_ADRS_HI0 156
7 PIXDAT<7> 3 11 GAMMA<0> 0
B A WD_TST 74HCT244
A7 I/O 0 7 GAMP_D<7> 61 8 1
6 PIXDAT<6> 4 GAMP_D7 ENABLE_RCURS EN 2
A6 6 GAMP_D<6> 140 55 19
5 PIXDAT<5> 5 GAMP_D6 HS_LONG EN 1
A5 ISA_D<15..0> 5 GAMP_D<5> 77 ISA INTERFACE
4 PIXDAT<4> 6 GAMP_D5
A4 4 GAMP_D<4> 154 15 ISA_A<15> 8 12 VMSK_A<15> 15 VLI MASK (VMSK) LUT
3 PIXDAT<3> 7 GAMP_D4 A3 2 Y3 U58
A3 NOTE: PIXDATA USABLE BITS ARE 11-0. 3 GAMP_D<3> 153 14 ISA_A<14> 6 14 VMSK_A<14> 14 U55
2 PIXDAT<2> 8 GAMP_D3 A2 Y2 74HCT245
A2 ACTUAL DATA PATH WIDTH IS 12 BITS. 2 GAMP_D<2> 76 13 ISA_A<13> 4 16 VMSK_A<13> 13
SRAM_32KX8
1 PIXDAT<1> 9 GAMP_D2 A1 Y1 19
FROM CRCT PLD A1 GAMP_D<1> 128 ISA_A<12> VMSK_A<12> 12 G3
10 1
GAMP_D1 12 2
A0 Y0
18 SPEED=15_NS
PIXDAT<11..0> 0 PIXDAT<0> 3 EN1 [BA]
A0 0 GAMP_D<0> 139 11 ISA_A<11> 11 9 VMSK_A<11> 11
VMSK_WR* 27
FROM GAMMA` LUT GAMP_D0 A3 1 Y3 WE & 1 ISA_SMEMR*
10 ISA_A<10> 13 7 VMSK_A<10> 10
VMSK_CE* 20 3 EN2 [AB]
GAMP_D<7..0> A2 Y2 CE
7 VMSK_D<7> 91 9 ISA_A<9> 15 5 VMSK_A<9> 9
VMSK_OE* 22 &
VMSK_D7 A1 Y1 OE VMSK_D<6>
6 VMSK_D<6> 36 8 ISA_A<8> 17 3 VMSK_A<8> 8 B 1
TO CRCT PLD VMSK_D6 A0 Y0 7 VMSK_D<7> 11 9 ISA_D<7> 7
2
5 VMSK_D<5> 37 14
VMSK_A<14> 1 19 VMSK_D<7> 7 A
GAMMA<15..0> VMSK_D5 A14 I/O 7 6 12 8 ISA_D<6> 6
4 VMSK_D<4> 40 13
VMSK_A<13> 26 18 VMSK_D<6> 6 B A
B 3 VMSK_D<3> 43
VMSK_D4
U56 12
VMSK_A<12> 2
A13 I/O 6
17 VMSK_D<5> 5
5 VMSK_D<5> 13
B A
7 ISA_D<5> 5
B
VMSK_D3 A12 I/O 5 4 VMSK_D<4> 14 6 ISA_D<4> 4
2 VMSK_D<2> 38 74HCT244 11
VMSK_A<11> 23 16 VMSK_D<4> 4 B A
VMSK_D2 1 A11 I/O 4 3 VMSK_D<3> 15 5 ISA_D<3> 3
1 VMSK_D<1> 41 EN 2 10
VMSK_A<10> 21 15 VMSK_D<3> 3 B A
FROM VMSK LUT VMSK_D1 19 A10 I/O 3 2 VMSK_D<2> 16 4 ISA_D<2> 2
0 VMSK_D<0> 85 66 VMSK_A<14> 14 EN 1 9
VMSK_A<9> 24 13 VMSK_D<2> 2 B A
VMSK_D<7..0> VMSK_D0 VMSK_A14 A9 I/O 2 1 VMSK_D<1> 17 3 ISA_D<1> 1
116 VMSK_A<13> 13 8
VMSK_A<8> 25 12 VMSK_D<1> 1 B A
VMSK_A13 7 ISA_A<7> 8 12 VMSK_A<7> 7 A8 I/O 1 0 VMSK_D<0> 18 2 ISA_D<0> 0
3 ISA_A<3> 95 86 VMSK_A<12> 12 A3 2 Y3 7
VMSK_A<7> 3 11 VMSK_D<0> 0 B A
ISA_A3 VMSK_A12 6 ISA_A<6> 6 14 VMSK_A<6> 6 A7 I/O 0
2 ISA_A<2> 15 87 VMSK_A<11> 11 A2 Y2 6
VMSK_A<6> 4
ISA_A2 VMSK_A11 5 ISA_A<5> 4 16 VMSK_A<5> 5 A6
1 ISA_A<1> 32 108 VMSK_A<10> 10 A1 Y1 5
VMSK_A<5> 5
ISA BUS ISA_A1 VMSK_A10 4 ISA_A<4> 2 18 VMSK_A<4> 4 A5 VMSK_D<7..0>
0 ISA_A<0> 30 112 VMSK_A<9> 9 A0 Y0 4
VMSK_A<4> 6
ISA_A<19..0> ISA_A0 VMSK_A9 3 ISA_A<3> 11 9 VMSK_A<3> 3 A4
110 VMSK_A<8> 8 A3 1 Y3 3
VMSK_A<3> 7
VMSK_A8 2 ISA_A<2> 13 7 VMSK_A<2> 2 A3
7 ISA_D<7> 16 109 VMSK_A<7> 7 A2 Y2 2
VMSK_A<2> 8
ISA_D7 VMSK_A7 1 ISA_A<1> 15 5 VMSK_A<1> 1 A2
6 ISA_D<6> 22 111 VMSK_A<6> 6 A1 Y1 1
VMSK_A<1> 9 ISA_D<15..0>
ISA_D6 VMSK_A6 0 ISA_A<0> 17 3 VMSK_A<0> 0 A1
5 ISA_D<5> 107 101 VMSK_A<5> 5 A0 Y0 0
VMSK_A<0> 10
ISA_D5 VMSK_A5 A0
4 ISA_D<4> 118 25 VMSK_A<4> 4
ISA_D4 VMSK_A4
3 ISA_D<3> 21 26 VMSK_A<3> 3
ISA_D3 VMSK_A3
2 ISA_D<2> 119 99 VMSK_A<2> 2
ISA_D2 VMSK_A2
1 ISA_D<1> 105 135 VMSK_A<1> 1
ISA_D1 VMSK_A1
ISA BUS 0 ISA_D<0> 117 9 VMSK_A<0> 0
ISA_D0 VMSK_A0 VMSK_A<15..0>
ISA_D<15..0>
LAST FPGA IN CONFIGURATION
SERIAL PATH
ISA_A<19..0>
A A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:26:47 2010 SCALE: 6 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 7 3 1
D D
C C
B UNUSED DEVICES B
VCC VCC VCC +5V

2
R24 R156
2
1K 1K
2
R160
+5B
1K R241
1
4.75
U10
1
74F02 14
1
11
V 13
C9
12
0.1
G
7
U75
8
C304
2 -
D D V+ 1
0.01
3 V-
U8 + LF412C
U15 5 6
4
74F02
5 74HC14 D
2
4
6 U8
C305
3 4 R242
A U15 74HC14 4.75
0.01 A
74F02
1
2
1
3
-5V D
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:26:49 2010 SCALE: 7 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 8 3 1
D D
50HZ_CNT98\I
CONF_DONE\I
PILOT_STBL\I
VCR50_EQ0\I
ODD_EVEN\I
LN_CNTEN\I
LOCK_RST\I
PILOT_EN\I
PIXCLK2Q\I
ICM_RDY\I
VIDSEL0\I
HS_60*\I
SDOUT\I
V_RST\I
DCLK\I
N_SP\I
U1\I
84
83
82
79
78
77
76
75
10
11
81
9
8
7
6
4
3
2
1
VCC 80
U22
GND 5
CONF_DONE
DCLK
N_SP
I/O6
I/O1
I/O64
I/O63
I/O62
I/O60
I/O61
I/O45/SDOUT
C C
I/O19/ADD0
I/O38/RDY_N_BUSY
I/O11/DATA2
I/O12/DATA3
I/O13/DATA4
I/O14/DATA5
I/O15/DATA6
I/O16/DATA7
12 74
PIXCLK\I I1 MSEL0 MSEL0\I
13 73
COMP_SYNC\I I/O10/DATA1 I4 CLKSEL2\I
14 72 LOCKOUT\I
DATA0\I I/O9/DATA0 I/O20/ADD1
15 71
VCR60_CNT162\I I/O7 I/O21/ADD2 QUALSYNC\I
16 70
60_EQ0\I
17
I/O8 EPF8636ALC84 I/O22/ADD3
69
END_FRAME\I
50_EQ0\I
VCC I/O23/ADD4
50HZ_CNT200\I 18
I/O17 SPEED=A_3 GND 68
19 67
HS_50*\I
20
I/O37 NOTE: I/O24/ADD5
66
33EN\I
START_VSYNC\I I/O43 I/O25/ADD6 BP_CLAMP*\I
21 65
CNTH_EQ0\I
22
I/O46 THIS COMPONENT I/O26/ADD7
64
VCO_EN*\I
D1\I I/O47 I/O27/ADD8 CLK_OUT\I
CLKSEL1\I
23
I/O48 BODY DRAWING I/O28/ADD9
63 HS_VCR_50*\I
24 62
39MHZ\I
25
I/O49 IS NOT INTENDED I/O29/ADD10
61
PILOT_TONE\I
NTSC_HCNT\I
VSYNC*\I I/O50 I/O30/ADD11
26 GND FOR PRODUCTION I/O31/ADD12
60
END_VSYNC\I
27
TDO\I
28
I/O3/TDO SCHEMATIC USE. VCC 59
58 NRZ_ODD_EVEN\I
34MHZ\I I/O42/CS I/O32/ADD13
PHASE_LOCK\I
29
I/O41/N_CS I/O33/ADD14
57 CLKSEL0\I
30 56
VCR_ODD_EVEN\I I/O39/N_WS I/O34/ADD15 HSYNC*\I
RST*\I
31
I2
SYNCGEN1 I/O35/ADD16
55
39EN\I
32 54
STATUS*\I N_STATUS I3 CHIP_HIZ*\I
I/O44/CLKUSR
I/O18/RDCLK
I/O36/ADD17
I/O40/N_RS
N_CONFIG
I/O4/TCLK
I/O5/TMS
N_TRST
I/O2/TDI
B B
MSEL1
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O51
47 GND
38 VCC
PACK_TYPE=PLCC
33
34
35
36
37
39
40
42
43
44
45
46
48
49
50
52
53
41
51
TMS\I
VCO\I
CNT_RST\I
VCR_HSYNC\I
IOCHRDY\I
TCLK\I
MSEL1\I
TRST*\I
TDI\I
U1*\I
VCR50_CNT162\I
HS_VCR_60*\I
VCR60_EQ0\I
CONFIG*\I
VIDSEL1\I
PILOT_DET\I
PILOT_OK\I
A A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:28:52 2010 SCALE: 8 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 9 3 1
D D
GAIN_BYPASS\I
INTERP_DIS\I
ISA_GAMP*\I
ICMDLY3_3\I
ICMDLY3_4\I
PIXDATA10\I
OFFSUB11\I
PIXDATA4\I
OFFSET10\I
GAMMA10\I
PIXDATA7\I
OFFSUB7\I
OFFSUB0\I
OFFSET4\I
OFFSET7\I
GAMMA0\I
A/DIN10\I
IP_VID2\I
GAIN10\I
IP_VID9\I
SDOUT\I
A/DIN9\I
A/DIN4\I
GAIN2\I
GAIN9\I
GAIN7\I
GAIN4\I
ICM2\I
ICM0\I
ICM5\I
159
158
157
156
154
153
152
150
149
146
145
144
143
142
139
138
137
136
135
134
132
130
129
128
127
125
124
123
122
151
141
131
160
155
148
147
140
133
126
121
U68
GND
GND
GND
NO_CONNECT
VCC
VCC
VCC
VCC
I/O99
I/O98
I/O97
I/O96
I/O95
I/O94
I/O116
I/O115
I/O114
I/O113
I/O112
I/O110
I/O109
I/O108
I/O107
I/O106
I/O105
I/O104
I/O103
I/O102
I/O100
I/O111
I/O101
I/O45/SDOUT
I/O19/ADD0
I/O38/RDY_N_BUSY
I/O11/DATA2
I/O12/DATA3
I/O13/DATA4
I/O14/DATA5
I/O15/DATA6
I/O16/DATA7
1 120 N_SP\I
DCLK\I DCLK N_SP
2 NO_CONNECT NO_CONNECT 119
4 117
CONF_DONE\I CONF_DONE MSEL0 MSEL0\I
5 116
PIXCLK\I I1 I4 RST*\I
C GAIN8\I
6
I/O1 I/O93
115
OFFSET1\I C
7 114 PIXDATA3\I
GAIN1\I I/O2 I/O92
8 113 PIXDATA1\I
OFFSUB1\I I/O3 I/O91
9 112
GAMMA11\I I/O4 I/O90 OFFSUB10\I
10 111
GAMMA1\I I/O5 I/O89 A/DIN7\I
11 110 IP_VID1\I
PIXDATA8\I I/O10/DATA1 I/O20/ADD1
DATA0\I 12 109
I/O9/DATA0 I/O21/ADD2 PIXDATA9\I
13 GND GND 108
14 GND EPF8452AQC160 GND 107
15 106
PIXDATA5\I I/O6 SPEED=A_3 I/O22/ADD3 PIXDATA0\I
16 105
ICMDLY3_2\I I/O7 I/O23/ADD4 IP_VID4\I
17 104
IP_VID5\I I/O8 I/O24/ADD5 IP_VID11\I
PIXDATA2\I 18
I/O17 NOTE: I/O25/ADD6
103
ICMDLY3_1\I
19 102
IP_VID8\I I/O37 I/O26/ADD7 ICMDLY3_6\I
IP_VID0\I
20
I/O43 THIS COMPONENT I/O27/ADD8
101
ICMDLY3_5\I
22
21 VCC
BODY DRAWING VCC 100
99 PMX0\I
OFFSUB3\I I/O46 I/O28/ADD9
OFFSET3\I
23
I/O47 IS NOT INTENDED I/O29/ADD10
98
24 97
IP_VID6\I
25
I/O48 FOR PRODUCTION I/O30/ADD11
96
OFFSUB9\I
OFFSUB5\I I/O49 I/O31/ADD12 IP_VID7\I
OFFSUB2\I 26
I/O50 SCHEMATIC USE. I/O32/ADD13
95
IP_VID3\I
27 94
PIXDATA11\I I/O42/CS I/O33/ADD14
28 GND GND 93
29 92
GAMMA6\I I/O41/N_CS I/O34/ADD15
30 91
CRCT
OFFSUB6\I
I/O39/N_WS I/O35/ADD16
31 90
GAMMA2\I I/O51 I/O88 A/DIN11\I
B GAMMA3\I 32
I/O52 I/O87
89 OFFSET9\I B
33 88
A/DIN8\I I/O53 I/O86 OFFSET5\I
34 87
A/DIN1\I I/O54 I/O85 OFFSET11\I
35 86
OFFSET0\I I/O55 I/O84 A/DIN5\I
36 85
CHIP_HIZ*\I I2 I3 ISA_GAIN*\I
37 84
STATUS*\I N_STATUS MSEL1 MSEL1\I
40 81
CONFIG*\I N_CONFIG VCC
NO_CONNECT
I/O44/CLKUSR
I/O18/RDCLK
I/O36/ADD17
I/O40/N_RS
I/O56
I/O57
I/O58
I/O59
I/O60
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O72
I/O73
I/O74
I/O75
I/O76
I/O77
I/O78
I/O79
I/O80
I/O82
I/O83
I/O61
I/O71
I/O81
GND
GND
GND
VCC
VCC
VCC
VCC
46
53
60
67
70
75
80
41
42
43
44
45
47
48
49
50
52
54
55
56
57
58
59
62
63
64
65
66
68
69
72
73
74
76
77
78
79
51
61
71
PACK_TYPE=SQFP
GAMMA7\I
GAMMA4\I
GAMMA9\I
GAMMA5\I
GAMMA8\I
GAM_BYPASS\I
OFFSUB4\I
OFFSUB8\I
OFFSET8\I
OFFSET2\I
OFFSET6\I
ICM4\I
ICM1\I
ICM6\I
GAIN0\I
GAIN5\I
GAIN6\I
GAIN3\I
ICM3\I
GAIN11\I
PIXDATA6\I
ICMDLY3_0\I
ISA_GAM*\I
A/DIN3\I
A/DIN6\I
A/DIN0\I
A/DIN2\I
IP_VID10\I
A A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:27:21 2010 SCALE: 9 OF 15
8 7 6 5 4 3 2 1
A
C
D
B
FORMAT PER PR12001
Wed Jun
23
07:27:40
8
8
2010
7
7
ISA_ICM*\I
ISA_A10\I
ISA_A11\I
ISA_GAM*\I
GAIN_CE*\I
ISA_A0\I
ISA_A7\I
ISA_A3\I
ISA_A9\I
ISA_RESET\I
LA23\I
R2_6\I
R0_5\I
R0_4\I
R6_2\I
R6_6\I
R0_2\I
R3_6\I
R0_1\I
R0_7\I
R2_0\I
R7_0\I
R3_7\I
OFS_CE*\I
MSEL1\I
MSEL0\I
GAM_OE*\I
+IO_POWER\I
CLK\I
GAM_CE*\I
+POWER\I
+POWER\I
+POWER\I

41
31
21
11
49
48
45
44
43
42
40
39
38
37
33
32
30
29
28
24
23
22
15
14
13
12
10
9
8
7
6
5
4
1
2
P9
P7
U72
P11
P48
P45
P44
P42
P40
P38
P15
P13
VCC
VCC
VCC
47 GND
46 GND
20 GND
19 GND
VCCIO
MSEL1
MSEL0
P8/ADD1
P28/ADD9
P24/ADD8
P23/ADD7
P22/ADD6
P21/ADD5
P14/ADD4
P12/ADD3
P10/ADD2
P30/ADD11
P43/ADD16
P41/ADD15
P39/ADD14
P37/ADD13
P31/ADD12
P29/ADD10
PACK_TYPE=SQFP
52 NO_CONNECT
51 NO_CONNECT
50 NO_CONNECT
36 NO_CONNECT
35 NO_CONNECT
34 NO_CONNECT
27 NO_CONNECT
26 NO_CONNECT
25 NO_CONNECT
18 NO_CONNECT
17 NO_CONNECT
16 NO_CONNECT
3 NO_CONNECT
NO_CONNECT
NO_CONNECT
53
NO_CONNECT NO_CONNECT 208
54 207
TRST*\I N_TRST N_SP N_SP\I
55 206
+IO_POWER\I VCCIO VCCIO +IO_POWER\I
6
6
56 205
GAIN_WR*\I P56 P205 MEM_ACS\I
57 204
LA21\I P57/ADD17 P204 ISA_A1\I
58 203
VC_IO_DEC\I P58 P203/ADD0 LA22\I
59 202
R7_5\I P59/CLKUSR P202 LA20\I
201
60 GND P201/RDY_N_BUSY R7_6\I
61 200
ISA_A2\I P61 GND
62 199
ISA_A16\I P62 P199 GAIN_OE*\I
63 198
ISA_D7\I P63 P198/SDOUT SDOUT\I
64 197
ISA_OFS*\I P64/RDCLK P197 MRST*\I
65 196
AEN*\I P65 P196 ISA_A8\I
66 195
DAC_WR*\I P66/N_RS P195 ISA_GAIN*\I
194
67 GND P194 ISA_A4\I
68 193
DAC_LCH*\I P68 VCCIO +IO_POWER\I
69 192
R4_2\I P69 P192 ISA_A13\I
70 191
R1_2\I P70 P191 R1_6\I
71 190
R2_3\I P71 P190 R2_2\I
72 189
TDI\I P72/TDI P189 R1_3\I
73 188
R3_1\I P73 P188 R1_7\I
74 187
TCLK\I P74/TCLK P187 R3_3\I
75 186
VMSK_CE*\I P75 P186 R3_0\I
76 185
TMS\I P76/TMS P185 R2_5\I
5
5
77 184
SMEMRD*\I P77 P184 GAMP_CE*\I
78 183
+IO_POWER\I VCCIO P183 OFS_OE*\I
79 182
OFS_WR*\I P79 VCCIO +IO_POWER\I
80 181
SPEED=A_4
ISA_VMSK*\I P80 P181 GAM_WR*\I

81 180
SMEMWR*\I P81 P180 MEMCS16*\I
82 179
R4_5\I P82 P179 ISA_GAMP*\I
83 178
ISA_A12\I P83 P178/DATA7 ICM_CE*\I
84 177
R7_4\I P84 P177 R1_5\I
85 176
R4_4\I P85 P176 VC_IO_RD\I
EPF8636AQC208_VCC
86 175
VMSK_WR*\I P86 P175 R1_4\I
87 174
R1_1\I P87 P174 ISA_D1\I
DECODER
88 173
R7_7\I P88 P173 R2_1\I
89 172
R4_6\I P89 P172/DATA6 VC_RD*\I
90 171
R0_3\I P90 GND
91 170
+IO_POWER\I VCCIO P170 R0_6\I
92 169
ISA_D3\I P92 P169/DATA5 VMSK_OE*\I
93 168
GAMP_WR*\I P93 P168 R7_1\I
94 167
R0_0\I P94 P167 ISA_A15\I
95 166
ISA_A18\I P95 P166 R7_2\I
165
96 GND P165/DATA4 R4_1\I
97 164
ISA_A19\I P97 GND
4
4
98 163
ISA_A14\I P98 P163 ISA_VIDCTRL*\I
99 162
VMSK_WREN\I P99 P162/DATA3 BALE\I
100 161
ISA_A17\I P100 P161 RST*\I
101 160
ISA_A5\I P101 P160/DATA2 R6_5\I
102 159
+IO_POWER\I VCCIO VCCIO +IO_POWER\I
103 158
CONFIG*\I N_CONFIG DCLK DCLK\I
P149/DATA1
P147/DATA0
P116/N_CS
P120/TDO
P118/CS
P114/N_WS
P112
P113
P115
P117
P119
P126
P127
P128
P129
P133
P134
P135
P136
P142
P143
P144
P145
P146
P148
P150
P152
N_STATUS
VCCIO
VCC
VCC
CONF_DONE
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
GND
GND
GND
GND
GND
111
121
131
141
151
105
106
107
109
122
123
124
125
130
132
139
140
154
155
156
108
110
112
113
114
115
116
117
118
119
120
126
127
128
129
133
134
135
136
137
138
142
143
144
145
146
147
148
149
150
152
153
TDO\I
R3_4\I
R3_2\I
R2_4\I
R4_7\I
R4_3\I
R3_5\I
R7_3\I
R4_0\I
R2_7\I
R6_1\I
R6_0\I
R6_3\I
R6_7\I
R6_4\I
R1_0\I
DATA0\I
ISA_A6\I
IO_RD*\I
ISA_D2\I
ISA_D4\I
ISA_D5\I
ISA_D6\I
ISA_D0\I
IO_WR*\I
+POWER\I
3
3
STATUS*\I
+POWER\I
CHIP_HIZ*\I
GAMP_OE*\I
+IO_POWER\I
CONF_DONE\I
DWG NO.
2
00-888918-01SCH
SIZE
B
SCALE: N/A
DWG NO.
10
SHT
3
REV
1
1
GE HEALTHCARE -
00-888918-01SCH
SHEET
10
3
SURGERY
REV
OF 15
A
C
D
B
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 11 3 1
D D
ICM_IOCHRDY\I
RAM_ADR12\I
RAM_ADR1\I
RAM_ADR6\I
RAM_RAS*\I
LUT_ADD0\I
RAM_DQ6\I
RAM_DQ5\I
RAM_CKE\I
ISA_DB14\I
ISA_OFS*\I
CLKSEL2\I
ISA_DB8\I
ISA_DB5\I
ISA_DB9\I
ISA_DB7\I
ISA_DB3\I
SDOUT\I
ADD11\I
ADD17\I
ADD18\I
ADD12\I
ADD13\I
ADD4\I
ADD6\I
BA1\I
BA0\I
159
158
157
156
155
153
152
150
148
147
146
145
144
143
142
139
138
137
136
135
134
133
132
130
129
128
127
125
124
123
122
151
141
160
154
149
140
126
131
121
U79
GND
GND
GND
VCCIO
VCCIO
VCCIO
VCCIO
P159
P158
P156
P153
P150
P148
P147
P146
P145
P144
P143
P142
P139
P138
P136
P135
P134
P133
P130
P128
P125
P123
P151
P141
P152/SDOUT
P157/ADD0
P137/DATA7
P132/DATA6
P129/DATA5
P127/DATA4
P124/DATA3
P122/DATA2
P155/RDY_N_BUSY
N_SP\I 1
N_SP DCLK
120
DCLK\I
MSEL0\I 3
MSEL0 CONF_DONE 118
CONF_DONE\I
4 VCC GND 117
5 VCC 116
P116 PIXCLK\I
ISA_RD*\I 6
P6 P115/DATA1
115
VSYNC*\I
HSYNC*\I 7 114
P7/ADD1 P114 LUT_ADD4\I
ADD9\I 8
P8 P113/DATA0
113
DATA0\I
ADD8\I 9
P9/ADD2 P112
112
LUT_ADD12\I
LUT_ADD10\I 10 111
C ADD16\I 11
P10 P111
110
LUT_ADD7\I C
RAM_ADR10\I 12 109
P12 P109 LUT_ADD2\I

RAM_DQML\I 13
P13/ADD4 P108
108
LUT_ADD6\I
RAM_DQMH\I 14
P14 EPF8636AQC160 VCCIO 107
15 GND VCC 106
SPEED=A_3
16 GND 105
P105 RAM_DQ8\I
RAM_ADR4\I 17
P17/ADD5 P104
104
RAM_DQ1\I
ISA_DB15\I 18
P18/ADD6 NOTE: P103
103
LUT_ADD15\I
ISA_DB10\I 19
P19/ADD7 P102
102
ISA_DB4\I
RAM_DQ12\I 20
P20/ADD8 THIS COMPONENT P101
101
RAM_DQ9\I
ISA_DB1\I 21 100
RAM_DQ11\I 22
P21/ADD9 BODY DRAWING P100
99
ISA_DB12\I
P22/ADD10 P99 RAM_DQ10\I
RAM_DQ3\I 23
P23/ADD11 IS NOT INTENDED P98
98
RAM_DQ2\I
24
ISA_DB11\I P24/ADD12
25 VCCIO
FOR PRODUCTION GND 97
96
GND
26 VCC SCHEMATIC USE. P95/TDO
95 TDO\I
ADD0\I 27
P27/ADD13 P94
94
ADD10\I
RAM_DQ14\I 28
P28 P93/CS
93
ISA_DB13\I
ICM
ADD5\I 29 92
RAM_DQ13\I 30
P30 P91/N_CS
91
RAM_DQ0\I
ADD14\I 31
P31/ADD15 P90
90
ISA_DB0\I
LUT_ADD3\I 32
P32 P89/N_WS
89
LUT_ADD5\I
ADD1\I 33
P33/ADD16 P88
88
LUT_ADD1\I
RAM_ADR5\I 34
P34 P87
87
RST*\I
CHIP_HIZ*\I 35
P35 GND 86
36 GND 85
B 37 GND
VCC
84
B
GND
MSEL1\I 38
MSEL1 N_STATUS
83
STATUS*\I
TRST*\I 40
N_TRST N_CONFIG
81
CONFIG*\I
P44/CLKUSR
P48/RDCLK
P43/ADD17
P50/N_RS
P57/TCLK
P59/TMS
P55/TDI
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
P42
P46
P47
P49
P52
P53
P54
P56
P58
P62
P63
P64
P65
P66
P67
P68
P69
P72
P73
P74
P76
P77
P78
P79
P61
P71
45
60
70
75
80
41
51
42
43
44
46
47
48
49
50
52
53
54
55
56
57
58
59
62
63
64
65
66
67
68
69
72
73
74
76
77
78
79
61
71
PACK_TYPE=SQFPV33
TMS\I
RAM_DQ4\I
RAM_DQ7\I
RAM_WE*\I
ADD2\I
ADD3\I
ADD7\I
RAM_ADR8\I
RAM_ADR0\I
RAM_ADR2\I
RAM_ADR3\I
RAM_ADR7\I
RAM_DQ15\I
TCLK\I
RAM_ADR9\I
RAM_CS*\I
RAM_ADR11\I
ADD19\I
ADD15\I
RAM_CAS*\I
TDI\I
LUT_ADD14\I
LUT_ADD13\I
LUT_ADD11\I
ISA_WR*\I
ICM_CE*\I
ISA_DB2\I
ISA_DB6\I
ISA_BALE\I
VLI_IOCHRQ*\I
ISA_ICM*\I
A A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:28:37 2010 SCALE: 11 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 12 3 1
RECURS_BYPASS\I
VMSK_ADRS_HI2\I
VLI_IOCHRQ*\I
CONF_DONE\I
ST_LCH_EN\I
RECURSEL\I
GAMP_D4\I
GAMP_D3\I
GAMP_D6\I
GAMP_D0\I
GAMP_D1\I
VMSK_A1\I
WD_TST\I
HS_TST\I
DATA0\I
SRDY*\I
DCLK\I
D D
158
157
156
154
153
152
150
148
147
146
145
144
142
140
139
138
136
135
134
133
132
130
129
128
125
124
123
122
151
141
121
160
159
155
149
143
137
127
126
131
U71
GND
GND
GND
GND
CONF_DONE
VCC
DCLK
VCCIO
VCCIO
VCCIO
VCCIO
P158
P157
P156
P154
P153
P152
P151
P150
P148
P147
P146
P145
P144
P142
P141
P140
P139
P138
P136
P135
P134
P133
P132
P130
P129
P128
P123
P122
P121
N_SP\I 1
N_SP P120
120
2 119
MSEL0\I MSEL0 P119 ISA_D2\I
3 VCC 118
P118 ISA_D4\I
4 117
P4 P117 ISA_D0\I
5 116
VLI_EN\I P5 P116 VMSK_A13\I
6 115
P6 GND
7 114
VLI_EN_ALL\I P7 VCC
8 113
ENABLE_RCURS\I P8 P113 PIXCLK_4\I
9 112
VMSK_A0\I P9 P112 VMSK_A9\I
10 111
P10 P111 VMSK_A6\I
11 110
P11 P110 VMSK_A8\I
12 GND 109
P109 VMSK_A7\I
13 GND 108
P108 VMSK_A10\I
CHIP_HIZ*\I
14
P14 EPF8820AQC160 P107
107
ISA_D5\I
15 106
C ISA_A2\I
16
P15 SPEED=A_4 P106
105
VMSK_ISA_EN*\I C
ISA_D7\I P16 P105 ISA_D1\I
17
TDI\I P17 VCCIO 104
SRDY_IN\I
18
P18 NOTE: GND 103
19 102
P19 P102 TDO\I
HLD_CNT_EN\I 20
P20 THIS COMPONENT P101
101
VMSK_A5\I
21 100
ISA_D3\I
22
P21 BODY DRAWING P100
99
25_30FPS\I
ISA_D6\I P22 P99 VMSK_A2\I
23 VCCIO IS NOT INTENDED P98
98
ACTIVE\I
97
25
24 VCC
FOR PRODUCTION P97
96
SDOUT\I
SP_LCH_EN\I
VMSK_A4\I P25 P96
VMSK_A3\I
26
P26 SCHEMATIC USE. P95
95
ISA_A3\I
27 94
TCLK\I P27 P94 RST*\I
28 93
ISA_VMSK*\I P28 GND
29 92
TMS\I P29 VCC
30 91
ISA_A0\I
VC_IO_RD\I
ISA_A1\I
31
32
P30
P31
P32
VLI P91
P90
P89
90
89
VMSK_D7\I
AVG_BYPASS\I
RST_PEAK\I
33 88
PIXCLK\I P33 P88 AUTO_RST_EN\I
34 GND 87
P87 VMSK_A11\I
35 GND 86
P86 VMSK_A12\I
36 85
VMSK_D6\I P36 P85 VMSK_D0\I
37 84
VMSK_D5\I P37 P84 VMSK_ADRS_HI3\I
38 83
VMSK_D2\I P38 GND
39 82
P39 N_STATUS STATUS*\I
40 81
VMSK_D4\I P40 N_CONFIG CONFIG*\I
B B
MSEL1
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
VCC
P42
P43
P45
P48
P49
P50
P52
P53
P54
P55
P56
P58
P59
P60
P62
P64
P65
P66
P67
P68
P70
P72
P73
P74
P76
P77
P78
P41
P61
P71
46
47
57
63
69
75
79
80
51
42
43
44
45
48
49
50
52
53
54
55
56
58
59
60
62
64
65
66
67
68
70
72
73
74
76
77
78
41
61
71
PACK_TYPE=SQFP
VMSK_WREN\I
VMSK_RD\I
HS_LONG\I
GAMP_D7\I
GAMP_D2\I
GAMP_D5\I
VMSK_ADRS_EN\I
RST_ACC\I
VMSK_D1\I
VMSK_D3\I
AUTO_RST\I
MSEL1\I
H_SYNC*\I
VMSK_A14\I
V_SYNC*\I
RST_FLTR\I
TRST*\I
VMSK_ADRS_HI0\I
VMSK_ADRS_HI1\I
ISA_TST\I
A A
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:29:09 2010 SCALE: 12 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 13 3 1
Title: Cref Part Report C74 CERSMT_1206 888918[3A7] C152 CERSMT_1206 888918[3A6] C230 CERSMT_1206 888918[2B8]
Design: 888918 C75 CERSMT_1206 888918[3A8] C153 CERSMT_1206 888918[3A8] C231 CERSMT_1206 888918[3B8]
Date: Oct 3 13:16:51 2007 C76 CERSMT_1206 888918[3B8] C154 CERSMT_1206 888918[3A6] C232 CERSMT_1206 888918[2B8]
C77 CERSMT_1206 888918[3A6] C155 CERSMT_1206 888918[3A8] C233 CERSMT_1206 888918[2B8]
C78 CERSMT_1206 888918[3C5] C156 CERSMT_1206 888918[3A6] C234 CERSMT_1206 888918[2B3]
C1 CERSMTTRIM_2320 888918[1B1] C79 CERSMT_1206 888918[3A7] C157 CERSMT_1206 888918[3A7] C235 CERSMT_1206 888918[2B4]
C2 CERSMT_1206 888918[1D7] C80 CERSMT_1206 888918[3A5] C158 CERSMT_1206 888918[3B6] C236 CERSMT_1206 888918[2C4]
C3 CERSMT_1206 888918[3A8] C81 CERSMT_1206 888918[3A7] C159 CERSMT_1206 888918[3A8] C237 CERSMT_1206 888918[2B6]
C4 CERSMT_1206 888918[3B8] C82 CERSMT_1206 888918[3A7] C160 CERSMT_1206 888918[3A6] C238 CERSMT_1206 888918[2B6]
C5 CERSMT_1206 888918[1C8] C83 CERSMT_1206 888918[3A7] C161 CERSMT_1206 888918[3A7] C239 CERSMT_1206 888918[2B5]
D C6 CERSMT_1206 888918[1C8] C84 CERSMT_1206 888918[1D6] C162 CERSMT_1206 888918[3A7] C240 CERSMT_1206 888918[2B5] D
C7 MICAR 888918[1B2] C85 CERSMT_1206 888918[1D6] C163 CERSMT_1206 888918[3A8] C241 CERSMT_1206 888918[3B8]
C8 CERSMT_1206 888918[1B1] C86 CERSMT_1206 888918[1B6] C164 CERSMT_1206 888918[3B7] C242 CERSMT_1206 888918[3B7]
C9 CERSMT_1206 888918[7A7] C87 CERSMT_1206 888918[1D7] C165 CERSMT_1206 888918[3A6] C243 CERSMT_1206 888918[3B7]
C10 TASMT_7343 888918[3D7] C88 CERSMT_1206 888918[1A7] C166 CERSMT_1206 888918[3B6] C244 CERSMT_1206 888918[3B6]
C11 CERSMT_0805 888918[1B7] C89 CERSMT_1206 888918[1D8] C167 CERSMT_1206 888918[3A6] C245 CERSMT_1206 888918[3B7]
C12 CERSMT_0805 888918[1A7] C90 CERSMT_1206 888918[3C7] C168 CERSMT_1206 888918[3A8] C246 CERSMT_1206 888918[3B6]
C13 CERSMT_1206 888918[1C6] C91 CERSMT_1206 888918[3A7] C169 CERSMT_1206 888918[3B6] C247 CERSMT_1206 888918[3B7]
C14 TASMT_6032 888918[2C5] C92 CERSMT_1206 888918[3A6] C170 CERSMT_1206 888918[3B8] C248 CERSMT_1206 888918[3B7]
C15 CERSMT_1206 888918[1B7] C93 CERSMT_1206 888918[3A6] C171 CERSMT_1206 888918[3A8] C249 CERSMT_1206 888918[3B8]
C19 CERSMT_1206 888918[1D8] C97 CERSMT_1206 888918[3A8] C175 CERSMT_1206 888918[2C2] C253 CERSMT_1206 888918[3B6]
C20 CERSMT_1206 888918[1D7] C98 CERSMT_1206 888918[3A8] C176 CERSMT_1206 888918[2A2] C254 CERSMT_1206 888918[3B6]
C21 CERSMT_1206 888918[3C5] C99 CERSMT_1206 888918[3A6] C177 CERSMT_1206 888918[1B3] C255 CERSMT_1206 888918[3B6]
C22 TASMT_6032 888918[3C5] C100 CERSMT_1206 888918[3B8] C178 CERSMT_1206 888918[2C4] C256 CERSMT_1206 888918[3B7]
C23 TASMT_7343 888918[3C7] C101 CERSMT_1206 888918[1A3] C179 CERSMT_1206 888918[2B6] C257 CERSMT_1206 888918[3B7]
C24 TASMT_7343 888918[3C7] C102 CERSMT_1206 888918[3A7] C180 CERSMT_1206 888918[2B6] C258 CERSMT_1206 888918[3A8]
C25 CERSMT_0805 888918[2A6] C103 CERSMT_1206 888918[3A7] C181 CERSMT_1206 888918[3B8] C259 CERSMT_1206 888918[3A8]
C C27 CERSMT_1206 888918[2B7] C105 CERSMT_1206 888918[3A7] C183 CERSMT_1206 888918[3B8] C261 CERSMT_1206 888918[3A7] C
C28 TASMT_6032 888918[2D5] C106 CERSMT_1206 888918[3A6] C184 CERSMT_1206 888918[3B6] C262 CERSMT_1206 888918[3B8]
C29 CERSMT_1206 888918[2B6] C107 CERSMT_1206 888918[3A6] C185 CERSMT_1206 888918[3B8] C263 CERSMT_1206 888918[3A6]
C30 POLYPR_0X1U_41507724 888918[2D6] C108 CERSMT_1206 888918[1B1] C186 CERSMT_1206 888918[3B7] C264 CERSMT_1206 888918[3B8]
C31 CERSMT_1206 888918[2C8] C109 CERSMT_1206 888918[1B2] C187 CERSMT_1206 888918[3B7] C265 CERSMT_1206 888918[3A6]
C32 CERSMT_1206 888918[2B7] C110 CERSMT_1206 888918[1D7] C188 CERSMT_1206 888918[3B7] C266 CERSMT_1206 888918[3A8]
C33 CERSMT_1206 888918[2D8] C111 CERSMT_1206 888918[1C7] C189 CERSMT_1206 888918[3B8] C267 CERSMT_1206 888918[3A7]
C34 CERSMT_1206 888918[2B7] C112 CERSMT_1206 888918[1C7] C190 CERSMT_1206 888918[3B8] C268 CERSMT_1206 888918[3B7]
C35 POLYPR_0X01U_41507725 888918[2D8] C113 CERSMT_1206 888918[1B7] C191 CERSMT_1206 888918[3B7] C269 CERSMT_1206 888918[3A7]
C36 TASMT_6032 888918[3C6] C114 CERSMT_1206 888918[1C6] C192 CERSMT_1206 888918[3B7] C270 CERSMT_1206 888918[3A7]
C37 TASMT_7343 888918[3D7] C115 CERSMT_1206 888918[1C5] C193 CERSMT_1206 888918[3B6] C271 CERSMT_1206 888918[3B7]
C38 CERSMT_1206 888918[1B1] C116 CERSMT_1206 888918[2D4] C194 CERSMT_1206 888918[3B8] C272 CERSMT_1206 888918[3A7]
C39 CERSMT_1206 888918[2B6] C117 CERSMT_1206 888918[2D4] C195 CERSMT_1206 888918[3A8] C273 CERSMT_1206 888918[1A3]
C40 CERSMT_0805 888918[2A5] C118 CERSMT_1206 888918[1B6] C196 CERSMT_1206 888918[3A5] C274 CERSMT_1206 888918[3A4]
C41 CERSMT_1206 888918[2C4] C119 CERSMT_1206 888918[2A8] C197 CERSMT_1206 888918[3A7] C275 CERSMT_1206 888918[3A3]
C42 TASMT_6032 888918[2C7] C120 CERSMT_1206 888918[1B7] C198 CERSMT_1206 888918[3B7] C276 CERSMT_1206 888918[3A5]
C43 CERSMT_0603 888918[2B3] C121 CERSMT_1206 888918[1A6] C199 CERSMT_1206 888918[3A6] C277 CERSMT_1206 888918[3A4]
C45 TASMT_6032 888918[2D7] C123 CERSMT_1206 888918[1B7] C201 CERSMT_1206 888918[3A7] C279 CERSMT_1206 888918[4B6]
C48 CERSMT_0805 888918[2B5] C126 CERSMT_1206 888918[4D4] C204 CERSMT_1206 888918[3A6] C282 CERSMT_1206 888918[3A3]
B B
C51 POLYPR_0X1U_41507724 888918[2B3] C129 CERSMT_1206 888918[3B8] C207 CERSMT_1206 888918[3A8] C285 CERSMT_1206 888918[3A3]
C53 CERSMT_1206 888918[2A4] C131 CERSMT_1206 888918[3A8] C209 CERSMT_1206 888918[3A6] C287 CERSMT_1206 888918[3A3]
C55 POLYPR_0X1U_41507724 888918[2A4] C133 CERSMT_1206 888918[3A6] C211 CERSMT_1206 888918[3B7] C289 CERSMT_1206 888918[3A4]
C56 CERSMT_1206 888918[1C2] C134 CERSMT_1206 888918[3B7] C212 CERSMT_1206 888918[3A7] C290 CERSMT_1206 888918[3A3]
C57 CERSMT_1206 888918[3D5] C135 CERSMT_1206 888918[3A7] C213 CERSMT_1206 888918[3A5] C291 CERSMT_1206 888918[3A4]
C58 CERSMT_1206 888918[2C7] C136 CERSMT_1206 888918[3A7] C214 CERSMT_1206 888918[3A8] C292 CERSMT_1206 888918[3A5]
C59 CERSMT_1206 888918[3D4] C137 CERSMT_1206 888918[3A7] C215 CERSMT_1206 888918[3A6] C293 CERSMT_1206 888918[3A6]
C60 TASMT_7343 888918[3C6] C138 CERSMT_1206 888918[3A6] C216 CERSMT_1206 888918[3B6] C294 CERSMT_1206 888918[3A6]
C61 TASMT_6032 888918[3D6] C139 CERSMT_1206 888918[3A6] C217 CERSMT_1206 888918[3B6] C295 CERSMT_1206 888918[3A6]
C62 TASMT_6032 888918[3D5] C140 CERSMT_1206 888918[3A7] C218 CERSMT_1206 888918[3A6] C296 CERSMT_1206 888918[3B7]
C63 CERSMT_1206 888918[4B8] C141 CERSMT_1206 888918[3C5] C219 CERSMT_1206 888918[3A6] C297 CERSMT_1206 888918[3A3]
C64 TASMT_7343 888918[4A7] C142 CERSMT_1206 888918[2D6] C220 CERSMT_1206 888918[3A8] C298 CERSMT_1206 888918[3A4]
C65 CERSMT_1206 888918[3A8] C143 CERSMT_1206 888918[2D6] C221 CERSMT_1206 888918[3A8] C299 CERSMT_1206 888918[3A4]
A A
C72 CERSMT_1206 888918[3B7] C150 CERSMT_1206 888918[3A8] C228 CERSMT_1206 888918[2B8] C306 CERSMT_1206 888918[4A6]
C73 CERSMT_1206 888918[3B6] C151 CERSMT_1206 888918[3A6] C229 CERSMT_1206 888918[3A7] C307 CERSMT_1206 888918[4D6]
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:29:48 2010 SCALE: 13 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 14 3 1
C308 CERSMT_1206 888918[4C6] P5 CONN_SMBHS_58019880 888918[1C8] R46 RESSMT_1206 888918[1D8] R124 RESSMT_1206 888918[1C2]
C309 CERSMT_1206 888918[4C6] P6 HDMLXMFLKRA_2X4_51411327 888918[1A8 1D8 R47 RESSMT_1206 888918[1B6] R125 RESWW_2_25W 888918[3D5]
C310 CERSMT_1206 888918[4D6] 1D8 1D8 1B8 R48 RESSMT_1206 888918[2A8] R126 RESSMT_1206 888918[1B2]
C311 CERSMT_1206 888918[3B7] 1A8] R49 RESSMT_0603 888918[2A7] R127 RESSMT_1206 888918[2C7]
C312 CERSMT_1206 888918[3A5] P7 MINJRRA_2X4_51411109 888918[3D8 3D8 R50 RESSMT_1206 888918[2A8] R128 RESSMT_1206 888918[1A3]
C313 CERSMT_1206 888918[3A4] 3D8 3D8 3D8 3D8 R51 RESSMT_0603 888918[2A6] R129 RESSMT_1206 888918[5D7]
C314 CERSMT_1206 888918[3A5] 3D8 3D8] R52 RESSMT_0603 888918[2A7] R130 RESSMT_1206 888918[4B6]
C315 CERSMT_1206 888918[3A3] P8 HDMLXMFLKRA_2X2_51411325 888918[2D1 2D1 R53 RESSMT_0603 888918[2A6] R131 RESSMT_1206 888918[3B6]
C316 CERSMT_1206 888918[3A5] 2D1 2D1] R54 RESSMT_0603 888918[2A6] R132 RESSMT_1206 888918[3B6]
C317 CERSMT_1206 888918[3A3] P9 CONN_SMBHS_58019880 888918[1C8] R55 RESSMT_1206 888918[2D4] R133 RESSMT_1206 888918[3B6]
D C318 CERSMT_1206 888918[3A5] P10 HDBKRA_2X5_90012604 888918[3B8 3B8 R56 RESSMT_1206 888918[2D4] R134 RESSMT_1206 888918[3C6] D
C319 CERSMT_1206 888918[3A3] 3C8 3C8 3C8 3C8 R57 RESSMT_1206 888918[1B2] R135 RESSMT_1206 888918[1A3]
C320 CERSMT_1206 888918[3A5] 3B8 3B8 3B8 R58 RESSMT_1206 888918[2C6] R136 RESSMT_1206 888918[1D5]
C321 CERSMT_1206 888918[3A8] 3B8] R59 RESSMT_1206 888918[2B6] R137 RESSMT_1206 888918[1D5]
C322 CERSMT_1206 888918[3B7] P11 HDBKRA_2X5_90012604 888918[4D5 4D5 R60 RESSMT_1206 888918[2C8] R138 RESSMT_1206 888918[6D4]
CR1 DIO_SMT_VAR 888918[1A2] 4D5 4D5 4D5 4D5 R61 RESSMT_1206 888918[2B7] R139 RESSMT_1206 888918[1A3]
CR2 DIO_SMT_1501A 888918[1B2] 4D5 4D5 4D5 R62 RESSMT_1206 888918[2C8] R140 RESSMT_1206 888918[1D3]
CR3 DIO_SMT_1501A 888918[1B2] 4D5] R63 RESSMT_1206 888918[2D8] R141 RESSMT_1206 888918[3C7]
CR4 DIO_SMT_1501A 888918[1D7] P12 HDBKST_2X20_90012602 888918[2D2 2D2 R64 RESSMT_1206 888918[1B2] R142 RESSMT_1206 888918[1A4]
CR5 DIO_SMT_1501A 888918[1D7] 2D2 2D2 2D2 2D2 R65 RESSMT_1206 888918[1B2] R143 RESSMT_1206 888918[1A4]
CR6 DIO_SMT_VAR 888918[1A1] 2D2 2D2 2D2 2D2 R66 RESSMT_1206 888918[2D8] R144 RESSMT_1206 888918[1A4]
CR7 DIO_SMT_VAR 888918[1A1] 2D2 2D2 2D2 2D2 R67 RESSMT_1206 888918[2D7] R145 RESSMT_1206 888918[1A4]
DS1 LED_RA_67599204 888918[1C1] 2C2 2D2 2C2 2C2 R68 RESSMT_1206 888918[3C6] R146 RESSMT_1206 888918[1A4]
DS2 LED_RA_67599204 888918[1C1] 2C2 2C2 2C2 2C2 R69 RESSMT_1206 888918[1B1] R147 RESSMT_1206 888918[1A4]
DS3 LED_RA_67599204 888918[3C5] 2C2 2D2 2D2 2C2 R70 RESSMT_1206 888918[1D8] R148 RESSMT_1206 888918[1A4]
E1 JMPST_1X2_90012601 888918[1D7] 2C2 2D2 2C2 2C2 R71 RESSMT_1206 888918[1D8] R149 RESSMT_1206 888918[1A4]
E2 JMPST_1X2_90012601 888918[1B5] 2C2 2C2 2D2 2D2 R72 RESSMT_1206 888918[2B7] R150 RESSMT_1206 888918[1A5]
E3 EMI_ENCLOS_90116701 888918[3B5] 2D2 2D2 2D2 2D2 R73 RESSMT_0603 888918[2A6] R151 RESSMT_1206 888918[1A5]
E4 JMPST_1X2_90012601 888918[4D5] 2D2 2D2] R74 RESSMT_0603 888918[2A6] R152 RESSMT_1206 888918[1A5]
FL1 EMI_FLTR_43600000 888918[3D7] Q1 MMBT3904 888918[1D8] R75 RESSMT_0603 888918[2A5] R153 RESSMT_1206 888918[1A5]
FL2 EMI_FLTR_43600000 888918[3D6] Q2 MMBT3904 888918[1D8] R76 RESSMT_0603 888918[2A5] R154 RESSMT_1206 888918[1B2]
C FL3 EMI_FLTR_43600000 888918[3D5] Q3 MMBT3906 888918[1B2] R77 RESSMT_0603 888918[2A5] R155 RESSMT_1206 888918[1B5] C
L1 INDSMTMLD_1210 888918[2A6] Q4 MMBT3904 888918[1A2] R78 RESSMT_1206 888918[2B6] R156 RESSMT_1206 888918[7B7]
L4 INDSMTMLD_1210 888918[1B2] R1 RESSMT_1206 888918[1D8] R79 RESSMT_1206 888918[1A2] R157 RESSMT_1206 888918[1B1]
L8 INDSMTMLD_1210 888918[2B6] R2 RESSMT_1206 888918[1D7] R80 RESSMT_0603 888918[2C3] R158 RESSMT_1206 888918[1B4]
L9 INDSMTMLD_1210 888918[2B6] R3 RESSMT_0603 888918[1B8] R81 RESSMT_0603 888918[2C3] R159 RESSMT_1206 888918[1C5]
L10 INDSMTMLD_1210 888918[2B6] R4 RESSMT_0603 888918[1B8] R82 RESSMT_0603 888918[2B3] R160 RESSMT_1206 888918[7A7]
L11 INDSMTMLD_1210 888918[2B6] R5 RESSMT_0603 888918[1B8] R83 RESSMT_0805 888918[2A3] R161 RESSMT_1206 888918[1C1]
L12 INDSMTMLD_1210 888918[2B6] R6 RESSMT_0603 888918[1B8] R84 RESSMT_1206 888918[2B3] R162 RESSMT_1206 888918[1C1]
L13 INDSMTMLD_1210 888918[2B6] R7 RESSMT_1206 888918[1B8] R85 RESSMT_0603 888918[2A5] R163 RESSMT_1206 888918[1D6]
P1 CONN_EDG_AB31 888918[4C8 4D8 R8 RESSMT_0603 888918[1A8] R86 RESSMT_0603 888918[2C5] R164 RESSMT_1206 888918[1D6]
4C8 4C8 4B8 4D8 R9 RESSMT_0603 888918[1A8] R87 RESSMT_0603 888918[2A5] R165 RESSMT_1206 888918[1D7]
4C8 4C8 4C8 4D8 R10 RESSMT_0603 888918[1A8] R88 RESSMT_0603 888918[2C6] R166 RESSMT_1206 888918[1B6]
4C8 4C8 4C8 4C8 R11 RESSMT_1206 888918[1D7] R89 RESSMT_0603 888918[2B5] R167 RESSMT_1206 888918[1D6]
4B8 4B8 4C8 4B8 R12 RESSMT_0603 888918[1B8] R90 RESSMT_0603 888918[2B5] R168 RESSMT_1206 888918[1A6]
4C8 4C8 4B8 4B8 R13 RESSMT_0603 888918[1B8] R91 RESSMT_0603 888918[2B5] R169 RESSMT_1206 888918[1D7]
4B8 4B8 4B8 4C8 R14 RESSMT_1206 888918[1D7] R92 RESSMT_1206 888918[2B5] R170 RESSMT_1206 888918[1D7]
4B8 4C8 4B8 4B8 R15 RESSMT_1206 888918[1A6] R93 RESSMT_0603 888918[2B5] R171 RESSMT_1206 888918[1D7]
4C8 4B8 4B8 4B8 R16 RESSMT_0603 888918[1C8] R94 RESSMT_0603 888918[2B6] R172 RESSMT_1206 888918[1D5]
4B8 4B8 4C8 4B8 R17 RESSMT_1206 888918[1D6] R95 RESSMT_1206 888918[2A5] R173 RESSMT_1206 888918[1D5]
4C8 4B8 4B8 4B8 R18 RESSMT_1206 888918[1C8] R96 RESSMT_0805 888918[2A5] R174 RESSMT_1206 888918[3C7]
4C8 4B8 4B8 4B8 R19 RESSMT_0603 888918[1C8] R97 RESSMT_0805 888918[2B4] R175 RESSMT_1206 888918[1B1]
4C8 4B8 4C8 4C8 R20 RESSMT_1206 888918[1C8] R98 RESSMT_1206 888918[2A5] R176 RESSMT_1206 888918[1A2]
B B
4C8 4D8 4D8 4C8 R21 RESSMT_1206 888918[1D5] R99 RESSMT_0603 888918[2B4] R177 RESSMT_1206 888918[1D7]
4D8 4C8 4C8 4D8 R22 RESSMT_1206 888918[1B2] R100 RESSMT_0805 888918[2B5] R178 RESSMT_1206 888918[1C7]
4D8 4D8 4B8 R23 RESSMT_1206 888918[3C7] R101 RESSMT_0603 888918[2C3] R179 RESSMT_1206 888918[2D6]
4D8] R24 RESSMT_1206 888918[7B8] R102 RESSMT_0603 888918[2C3] R180 RESSMT_1206 888918[1C7]
P2 CONN_EDG_CD18 888918[4D7 4D7 R25 RESSMT_1206 888918[1D8] R103 RESSMT_1206 888918[2A4] R181 RESSMT_1206 888918[1B7]
4D7 4C7 4C7 4C7 R26 RESSMT_0603 888918[1B8] R104 RESSMT_0603 888918[2C3] R182 RESSMT_1206 888918[1C6]
4D7 4D7 4D7 4C7 R27 RESSMT_1206 888918[1A7] R105 RESSMT_0603 888918[2C4] R183 RESSMT_1206 888918[1C6]
4C7 4C7 4C7 4C7 R28 RESSMT_0603 888918[1B7] R106 RESSMT_0805 888918[2A3] R184 RESSMT_1206 888918[1A6]
4C7 4C7 4C7 4C7 R29 RESSMT_0603 888918[1B7] R107 RESSMT_0805 888918[2A5] R185 RESSMT_1206 888918[2D4]
4C7 4C7 4C7 4C7 R30 RESSMT_1206 888918[1A8] R108 RESSMT_0603 888918[2A4] R186 RESSMT_1206 888918[2D4]
4B7 4C7 4D7 4C7 R31 RESSMT_0603 888918[1B7] R109 RESSMT_0603 888918[2B3] R187 RESSMT_1206 888918[2B8]
4C7 4C7 4D7 4D7 R32 RESSMT_1206 888918[1B6] R110 RESSMT_0603 888918[2B4] R188 RESSMT_1206 888918[2A8]
4D7 4C7 4C7 4C7 R33 RESSMT_1206 888918[1A8] R111 RESSMT_0805 888918[2A5] R189 RESSMT_1206 888918[3B4]
4C7 4C7] R34 RESSMT_1206 888918[1B5] R112 RESSMT_0805 888918[2A4] R190 RESSMT_1206 888918[2D6]
P3 D50RA_40P_51180007 888918[2C1 2D1 R35 RESSMT_1206 888918[2D4] R113 RESSMT_1206 888918[2A4] R191 RESSMT_1206 888918[1B2]
2D1 2D1 2C1 2C1 R36 RESSMT_1206 888918[2D4] R114 RESSMT_1206 888918[2B7] R192 RESSMT_1206 888918[1A2]
2D1 2C1 2C1 2D1 R37 RESSMT_1206 888918[2D4] R115 RESSMT_1206 888918[2B7] R193 RESSMT_1206 888918[2A8]
2C1 2C1 2D1 2D1 R38 RESSMT_0603 888918[1C8] R116 RESSMT_1206 888918[2B3] R194 RESSMT_1206 888918[2A8]
2C1 2C1 2D1 2C1 R39 RESSMT_0603 888918[1C8] R117 RESSMT_1206 888918[2C7] R195 RESSMT_1206 888918[4D2]
2C1 2C1 2C1 2C1 R40 RESSMT_1206 888918[1B7] R118 RESSMT_1206 888918[2C7] R196 RESSMT_1206 888918[4C4]
2C1 2C1 2C1 2C1 R41 RESSMT_0603 888918[1D8] R119 RESSMT_1206 888918[2B2] R197 RESSMT_1206 888918[4C4]
A A
2D1 2D1 2D1 2C1 R42 RESSMT_0603 888918[1C8] R120 RESWW_2_25W 888918[3D6] R198 RESSMT_1206 888918[4C4]
2C1 2C1 2C1 2C1 R43 RESSMT_1206 888918[1C7] R121 RESSMT_1206 888918[1C2] R199 RESSMT_1206 888918[5C3]
2C1 2D1 2D1 2D1 R44 RESSMT_1206 888918[1B2] R122 RESSMT_1206 888918[1C2] R200 RESSMT_1206 888918[3D2]
2C1 2D1] R45 RESSMT_1206 888918[3B7] R123 RESSMT_1206 888918[1C2] R201 RESSMT_1206 888918[2B2]
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:30:01 2010 SCALE: 14 OF 15
8 7 6 5 4 3 2 1
DWG NO. SHT REV
8 7 6 5 4 3 00-888918-01SCH 15 3 1
R202 RESSMT_1206 888918[2C4] TP15 TEST_POINT_COLOR 888918[1A8] U6 LT1395LOC_SOT23 888918[1C8] 8918[4A4]

R203 RESSMT_1206 888918[2C4] TP16 TEST_POINT_COLOR 888918[1C5] U7 LT1395LOC_SOT23 888918[1C8] U73 AD8561LOC_SOIC 888918[1C2]
R204 RESSMT_0603 888918[2A5] TP17 TEST_POINT_COLOR 888918[3D5] U8 74HC14_SOIC 888918[1C5 1C5] U74 AD8561LOC_SOIC 888918[1C2]
R205 RESSMT_0603 888918[2A6] TP18 TEST_POINT_COLOR 888918[1D5] U8 74HC14_SOIC 888918[6D3] U75 LF412C_SOIC 888918[1B2]
R206 RESSMT_0603 888918[2A5] TP19 TEST_POINT_COLOR 888918[1D5] U8 74HC14_SOIC 888918[7A7 7A7] U75 LF412C_SOIC 888918[7A6]
R207 RESSMT_0603 888918[2A5] TP20 TEST_POINT_COLOR 888918[1B3] U9 CY7B991_PLCCR 888918[1A4] U76 7805_TO220HU 888918[3D6]
R208 RESSMT_0603 888918[2A5] TP21 TEST_POINT_COLOR 888918[3D7] U10 74F02_SCD_VCC_SOIC 888918[1C1 1B1 U77 7905_TO220HU 888918[3D5]
R209 RESSMT_0603 888918[2A5] TP22 TEST_POINT_COLOR 888918[4A2] 1B1] U78 SDRAM_256MBIT_62610394_TSOPII 888918[5B5]
R210 RESSMT_0603 888918[2A5] TP23 TEST_POINT_COLOR 888918[1C3] U10 74F02_SCD_VCC_SOIC 888918[7A7] U79 EPF8636AQC160_SQFPV33 icm[9B6]888918[
R211 RESSMT_0603 888918[2A5] TP24 TEST_POINT_COLOR 888918[3D6] U11 EPC1_SDIP 888918[3B7] 5A7]
D R212 RESSMT_0603 888918[2A5] TP25 TEST_POINT_COLOR 888918[1B3] U12 74HCT244_SOIC 888918[3B6] U80 74HCT245_VCC_SOIC 888918[4A6] D
R213 RESSMT_0603 888918[2A5] TP26 TEST_POINT_COLOR 888918[1B1] U13 74HCT244_SOIC 888918[6C3] U81 74LCX16245_TSSOP 888918[5B8]
R214 RESSMT_0603 888918[2A5] TP27 TEST_POINT_COLOR 888918[1D5] U14 SRAM_32KX8_SOJ 888918[6C2] U82 74HCT244_VCC_SOIC 888918[4D6]
R215 RESSMT_0603 888918[2A5] TP28 TEST_POINT_COLOR 888918[4A2] U15 74F02_SOIC 888918[1D8 1D8] U83 74HCT244_VCC_SOIC 888918[4B6]
R216 RESSMT_0603 888918[2A6] TP29 TEST_POINT_COLOR 888918[4D2] U15 74F02_SOIC 888918[7A7 7A7] U84 74HCT244_VCC_SOIC 888918[4C6]
R217 RESSMT_1206 888918[4D2] TP30 TEST_POINT_COLOR 888918[3D6] U16 AD8055_SOT23 888918[1B8] U85 74HCT244_VCC_SOIC 888918[4C6]
R218 RESSMT_1206 888918[4D4] TP31 TEST_POINT_COLOR 888918[1B6] U17 LT1204_SOIC 888918[1A7] U86 74HCT245_VCC_SOIC 888918[4A6]
R219 RESSMT_1206 888918[4C4] TP32 TEST_POINT_COLOR 888918[2D7] U18 LF412C_SOIC 888918[1A8] XE1 SHORT_PC_X1 888918[1D4]
R220 RESSMT_1206 888918[4D4] TP33 TEST_POINT_COLOR 888918[1B2] U18 LF412C_SOIC 888918[2D4] XE2 SHORT_PC_X1 888918[1D4]
R221 RESSMT_1206 888918[4C4] TP34 TEST_POINT_COLOR 888918[1D3] U19 GS4981_SOIC 888918[1C6] XE3 SHORT_PC_X1 888918[5D3]
R222 RESSMT_1206 888918[4C4] TP35 TEST_POINT_COLOR 888918[1C1] U20 GS4881_SOIC 888918[1C7] XE4 SHORT_PC_X1 888918[5D3]
R223 RESSMT_1206 888918[5D6] TP36 TEST_POINT_COLOR 888918[4A2] U21 GS4881_SOIC 888918[1C7] XE5 SHORT_PC_X1 888918[3D3]
R224 RESSMT_1206 888918[6D3] TP37 TEST_POINT_COLOR 888918[3D6] U22 EPF8636ALC84_PLCC syncgen1[8B6]88 XE6 SHORT_PC_X1 888918[3D3]
R225 RESSMT_1206 888918[1D3] TP38 TEST_POINT_COLOR 888918[1B3] 8918[1B4] XE7 SHORT_PC_X1 888918[5D7]
R226 RESSMT_1206 888918[3D2] TP39 TEST_POINT_COLOR 888918[3A8] U23 74HCT244_SOIC 888918[6C8] XE8 SHORT_PC_X1 888918[5D7]
R227 RESSMT_1206 888918[3D4] TP40 TEST_POINT_COLOR 888918[4A2] U24 74HCT244_SOIC 888918[6D3 6C8] XE9 SHORT_PC_X1 888918[4D4]
R228 RESSMT_1206 888918[2B3] TP41 TEST_POINT_COLOR 888918[4A2] U25 74HCT245_SOIC 888918[6D1] XE10 SHORT_PC_X1 888918[4D4]
R229 RESSMT_1206 888918[2B4] TP42 TEST_POINT_COLOR 888918[4D2] U26 LT1117_SOT 888918[3D7] XE11 SHORT_PC_X1 888918[6D5]
R230 RESSMT_1206 888918[2C4] TP43 TEST_POINT_COLOR 888918[2B7] U27 LT1204_SOIC 888918[2A7] XE12 SHORT_PC_X1 888918[6D5]
R231 RESSMT_1206 888918[4B4] TP44 TEST_POINT_COLOR 888918[1D3] U28 LMH6502_SOIC 888918[2A8] Y1 OSC_8P_EN_10TTL 888918[1C6]
R232 RESSMT_1206 888918[4C4] TP45 TEST_POINT_COLOR 888918[4D5] U29 AD680_SOIC 888918[2C5] Y2 OSC_8P_EN_10TTL 888918[1C6]
C R233 RESSMT_1206 888918[4C4] TP46 TEST_POINT_COLOR 888918[4D5] U30 AD835_SOIC 888918[2D5] C
R234 RESSMT_1206 888918[4D6] TP47 TEST_POINT_COLOR 888918[2D3] U31 DG411_SOIC 888918[1B7 1C7]
R235 RESSMT_1206 888918[6C5] TP48 TEST_POINT_COLOR 888918[2C6] U31 DG411_SOIC 888918[2D8 2D6]
R236 RESSMT_1206 888918[4C6] TP49 TEST_POINT_COLOR 888918[2C8] U32 LF412C_SOIC 888918[2C6 2C8]
R237 RESSMT_1206 888918[4C6] TP50 TEST_POINT_COLOR 888918[2B5] U33 78L05_SOIC 888918[3C6]
R238 RESSMT_1206 888918[4D7] TP51 TEST_POINT_COLOR 888918[2B3] U34 74HCT245_SOIC 888918[5C1]
R239 RESSMT_1206 888918[4D7] TP53 TEST_POINT_COLOR 888918[5C5] U35 74HCT244_SOIC 888918[5C4]
R240 RESSMT_1206 888918[5D5] TP54 TEST_POINT_COLOR 888918[5C5] U36 TC551664_SOJ 888918[5C3]
R241 RESSMT_1206 888918[7A6] TP55 TEST_POINT_COLOR 888918[1A3] U37 74HCT244_SOIC 888918[5C4]
R242 RESSMT_1206 888918[7A6] TP56 TEST_POINT_COLOR 888918[6C3] U38 74HCT245_SOIC 888918[5C1]
R243 RESSMT_1206 888918[5D7] TP57 TEST_POINT_COLOR 888918[6C3] U39 74HCT245_SOIC 888918[6C5]
R244 RESSMT_1206 888918[1C8] TP58 TEST_POINT_COLOR 888918[4D3] U40 74HCT245_SOIC 888918[6C5]
R245 RESSMT_1206 888918[1B8] TP59 TEST_POINT_COLOR 888918[4A2] U41 SRAM_32KX8_SOJ 888918[6C7]
R246 RESSMT_1206 888918[1D8] TP60 TEST_POINT_COLOR 888918[2B3] U42 SRAM_32KX8_SOJ 888918[6B7]
R247 RESSMT_1206 888918[1C8] TP61 TEST_POINT_COLOR 888918[2C8] U43 DELAYSMT_10T20NS_RISMD 888918[2A6]
R248 RESSMT_1206 888918[1A7] TP64 TEST_POINT_COLOR 888918[3D5] U44 LT1395LOC_SOT23 888918[2A6]
R249 RESSMT_1206 888918[1B7] TP65 TEST_POINT_COLOR 888918[5C5] U45 LT1395LOC_SOT23 888918[2A5]
R250 RESSMT_1206 888918[1B7] TP66 TEST_POINT_COLOR 888918[4A7] U46 74F02_VCC_SOIC 888918[1B3 1B3]
R251 RESSMT_1206 888918[1A7] TP67 TEST_POINT_COLOR 888918[5C6] U46 74F02_VCC_SOIC 888918[2A7 2B5]
R252 RESSMT_1206 888918[2A7] TP68 TEST_POINT_COLOR 888918[6C4] U47 OP177_SOIC 888918[2C4]
R253 RESSMT_1206 888918[2A7] TP69 TEST_POINT_COLOR 888918[3D5] U48 AD835_SOIC 888918[2C7]

R254 RESSMT_1206 888918[2B7] TP71 TEST_POINT_COLOR 888918[3D4] U49 ADS800_SOIC 888918[2A3]
B B
R255 RESSMT_1206 888918[2B6] TP72 TEST_POINT_COLOR 888918[4B6] U50 74F574_SOIC 888918[2B2]
R256 RESSMT_1206 888918[2B5] TP73 TEST_POINT_COLOR 888918[4D5] U51 SRAM_128KX8_SOJ 888918[5A3]
R257 RESSMT_1206 888918[2B5] TP74 TEST_POINT_COLOR 888918[4D5] U52 SRAM_128KX8_SOJ 888918[5B3]
R258 RESSMT_1206 888918[2A4] TP75 TEST_POINT_COLOR 888918[6C3] U53 74HCT244_SOIC 888918[5B4]
R259 RESSMT_1206 888918[2B4] TP76 TEST_POINT_COLOR 888918[4D5] U54 74HCT244_SOIC 888918[5A4]
R260 RESSMT_1206 888918[2A4] TP77 TEST_POINT_COLOR 888918[4D5] U55 SRAM_32KX8_SOJ 888918[6B2]
R261 RESSMT_1206 888918[2B4] TP78 TEST_POINT_COLOR 888918[4A2] U56 74HCT244_SOIC 888918[6B3]
R262 RESSMT_1206 888918[2A4] TP79 TEST_POINT_COLOR 888918[4C4] U57 74HCT244_SOIC 888918[6B3]
R263 RESSMT_0805 888918[1B7] TP80 TEST_POINT_COLOR 888918[4A2] U58 74HCT245_SOIC 888918[6B1]
R264 RESSMT_0805 888918[1C7] TP81 TEST_POINT_COLOR 888918[5C5] U59 LT1395LOC_SOT23 888918[2B5]
T1 XFMR_SMT_44800000 888918[1D8] TP82 TEST_POINT_COLOR 888918[4D5] U60 LT1395LOC_SOT23 888918[2B5]
TP1 TEST_POINT_COLOR 888918[1B8] TP83 TEST_POINT_COLOR 888918[4A2] U61 OP177_SOIC 888918[2B3]
TP2 TEST_POINT_COLOR 888918[1D6] TP84 TEST_POINT_COLOR 888918[3D6] U62 LT1395LOC_SOT23 888918[2B4]
TP3 TEST_POINT_COLOR 888918[2C6] TP85 TEST_POINT_COLOR 888918[4B7] U63 ADG819LOC_SOT23 888918[2B4]
TP4 TEST_POINT_COLOR 888918[1D3] TP86 TEST_POINT_COLOR 888918[3D6] U64 ADG819LOC_SOT23 888918[2B4]
TP5 TEST_POINT_COLOR 888918[3D6] TP87 TEST_POINT_COLOR 888918[1B3] U65 LT1395LOC_SOT23 888918[2A4]
TP6 TEST_POINT_COLOR 888918[1D6] TP88 TEST_POINT_COLOR 888918[3C5] U66 74F574_SOIC 888918[2A2]
TP7 TEST_POINT_COLOR 888918[1D3] TP89 TEST_POINT_COLOR 888918[4B6] U67 DAC_MAX505_SOIC 888918[2B8]
TP8 TEST_POINT_COLOR 888918[1D3] TP90 TEST_POINT_COLOR 888918[1B4] U68 EPF8452AQC160_SQFP crct[10A7]88891
TP9 TEST_POINT_COLOR 888918[3D7] TP91 TEST_POINT_COLOR 888918[1D3] 8[3A3]
TP10 TEST_POINT_COLOR 888918[1C3] U1 LT1395LOC_SOT23 888918[1B8] U69 74HCT245_SOIC 888918[5A1]
A A
TP11 TEST_POINT_COLOR 888918[1D3] U2 LT1395LOC_SOT23 888918[1A8] U70 74HCT245_SOIC 888918[5B1]
TP12 TEST_POINT_COLOR 888918[1B3] U3 AD8561LOC_SOIC 888918[1D7] U71 EPF8820AQC160_SQFP vli[12B6]888918
TP13 TEST_POINT_COLOR 888918[3D6] U4 AD8561LOC_SOIC 888918[1B6] [6A5]
TP14 TEST_POINT_COLOR 888918[3D7] U5 74LS123_SCD_SOIC 888918[1D6 1D6] U72 EPF8636AQC208_VCC_SQFP decoder[11A6]88
FORMAT PER PR12001
SIZE DWG NO. REV
B 00-888918-01SCH 3
N/A SHEET
Wed Jun 23 07:30:11 2010 SCALE: 15 OF 15
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5262582SCH
SHT
1
REV
1 1
REVISION HISTORY
1 CHANGED PER DCN R. WILLIAMS

08-13-09 DCN07948
Master in Document Control
D D
SOCKET
RIGHT_ANGLE
USB_TYPEA
J4
1 1 G1 G1
G1 G1 1 1 1 6 2 2 G2 G2
G2 G2 2 2 2 7 3 3 G3 G3
G3 G3 3 3 3 8 4 4 G4 G4
G4 G4 4 4 4 9
5 10
SOCKET J7
J2 RIGHT_ANGLE
USB_TYPEA PIN
A
RIGHT_ANGLE
WIRE_TO_BOARD
SOCKET
RIGHT_ANGLE C
C USB_TYPEA
J5
1 1 G1 G1
G1 G1 1 1 1 1 6 6 2 2 G2 G2
G2 G2 2 2 2 2 7 7 3 3 G3 G3
G3 G3 3 3 3 3 8 8 4 4 G4 G4
G4 G4 4 4 4 4 9 9
5 5 10 10
SOCKET J8
J3 RIGHT_ANGLE
USB_TYPEA PIN
A
RIGHT_ANGLE
WIRE_TO_BOARD
J6
J1
1 1 4 4 1 1
2 2 5 5 2 2
3 3 6 6 3 3
4 4 A
B 5 5 B
SOCKET
PIN
RIGHT_ANGLE
RIGHT_ANGLE
STEREO_AUDIO_JACK
WIRE_TO_BOARD
DRAWING NO. TO PART NO. CORRELATION MATRIX

DRAWING NO. PART NO. PART REV.
5262582SCH 5262582 1
A A
FORMAT PER PR12001
THIS DOCUMENT AND THE INFORMATION UNLESS OTHERWISE SPECIFIED ORIGINAL DRAWN BY: DATE:
CONTAINED HEREIN IS CONFIDENTIAL AND
PROPERTY OF OEC MEDICAL SYSTEMS, INC.,
DIMENSIONS ARE IN INCHES
TOLERANCES ARE: M. RICHINS 11-27-07
A UNIT OF GE HEALTHCARE AND WHOLLY-
OWNED SUBSIDIARY OF GENERAL ELECTRIC. FRACTIONS: +/- DWG TITLE
IT IS DISCLOSED TO YOU FOR THE N/A
SOLE PURPOSE OF YOUR PERFORMANCE
DECIMALS: X +/- N/A
N/A
ORIGINAL RESPONSIBLE ENGINEER: DATE:
PCB BOARD SCH, GPOS
SYSTEMS. IT IS NOT TO BE COPIED OR .X +/- B. SPRATT 11-16-07
IN ANY WAY DISCLOSED TO THIRD PARTIES.
IT SHALL BE RETURNED TO OEC MEDICAL .XX +/- N/A MULTI BRACKET, ROHS
SYSTEMS UPON DEMAND. YOU HEREBY
AGREE TO THESE RESTRICTIONS AND .XXX +/- N/A SIZE DWG NO. REV
Wed Aug 12 11:01:10 2009

ALL LOSS OR DAMAGE ARISING FROM
BREACH OF THIS OBLIGATION BY YOU
ANGLES: +/- N/A
B 5262582SCH 1
OR ENTITIES OR AGENTS UNDER YOUR DO NOT SCALE DRAWING SCALE:
CONTROL. NONE SHEET 1 OF 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
1
REV
1 1
REVISION HISTORY
1 12-18-09 DCN12033 CHANGE PER DCN G. POPE
D D
V3.3
8
7
6
5
R249
10K
U50 185P
4A4 CLK_CONF_66M CLK_CONF_66M
2
3
4
1
IN
3B6 CLK_10HZ CLK_10HZ CF_READY CF_READY
IN
4D5 VTM_INT* VTM_INT
IN
CF_BYTE*
CF_WP*
2A4 15C5 OUT
PLX_LHOLDA PLX_LHOLDA V3.3
PLX_LHOLD
U49
2A4 IN PLX_LHOLD
15D5 15D2 15C2 15B5 3D7 2D4 1A3 LB_LAD<31..0> LB_LAD<31..0> CF_CE CF_CE* 29LV640
BI
2A4 15C5 PLX_BREQI PLX_BREQI CF_OE CF_OE* SPEED=120_NS
OUT
2A4 PLX_BREQO PLX_BREQO CF_WE CF_WE* VCC 43
IN
2A4 15D7 PLX_INTI* PLX_INTI 32 CE
OUT
2C2 15B2 CPLD_NSTATUS CPLD_NSTATUS 3D7 2D2 LB_LRESET* 34 OE
OUT IN
3D7 2B4 LB_LBE<1..0>* LB_LBE<1..0> 13 WE NC/VIO 29
IN
3D7 2A4 LB_ADS* LB_ADS CF_ADR<23..0> CF_ADR<23..0> 16 WP
IN
3D7 2A4 LB_BLAST* LB_BLAST ACC
IN
3D7 2A4 LB_WR LB_LWR 14 RESET RY 17 CF_READY
BI
15B5 3D7 2A4 LB_READY* LB_READY 53 BYTE BY
OUT
C 2C2 PLX_NCONFIG PLX_NCONFIG

C
IN V3.3
2A1 PLX_EESK PLX_DCLK
IN
2A1 PLX_EED PLX_DATAO
IN
23 1 NC/A23
DA_PCI_IRQ
C544 C499 C542 C502 C18
3D4 IN DA_PCI_IRQ 22 2 NC/A22
DA_HOLD
0.1 0.1 2.2
3D7 IN DA_HOLD 21 15 A21 0.01 0.01
3D4 15C2 OUT
DA_HOLDA DA_HOLDA CONFIG_CPLD 20 12 A20
V3.3 15C2 3D4 IN
DA_BREQI DA_BREQI 19 11 A19
3D7 DA_BREQO DA_BREQO 18 18 A18
IN
17 19 A17 D
3B6 15B2 DA_NCONFIG DA_NCONFIG 16 54 A16
OUT
DA_DCLK R175 20
3B6 15B2 OUT DA_DCLK 15 3 A15 DQ15/A-1 51 15
R173 R176 R174 DA_DATAO
15B2 3B6 OUT DA_DATAO 14 4 A14 DQ14 49 14
10K 10K 10K VP_NSTATUS
3B6 IN VP_NSTATUS 13 5 A13 DQ13 47 13
3B6 DA_CONF_DONE DA_CONF_DONE 12 6 A12 DQ12 45 12

IN
11 7 A11 DQ11 42 11
DA_INIT_DONE 10 8 A10 DQ10 40 10
3B6 DA_INIT_DONE 9 9 A9 DQ9 38 9

IN
8 10 A8 DQ8 36 8
3A2 15C4 CONF_LED* CONF_LED 7 20 A7 DQ7 50 7

OUT
3A2 15C2 LB_ACTIVE* LB_ACTIVE 6 21 A6 DQ6 48 6
OUT
V3.3
5 22 A5 DQ5 46 5
4 23 A4 DQ4 44 4
3 24 A3 DQ3 41 3
2 25 A2 DQ2 39 2
R172 R171
B 10K 10K
1
0
26
31
A1
A0
DQ1
DQ0
37
35
1
0
B
CONF_DEV_OE DEV_OE
3D7 2D2 LB_LRESET* DEV_CLR PACK_TYPE=TSOP
IN
4D1 3A7 TMS TMS

IN
4D1 3A7 TCK TCK
IN
3A7 VP_TDO TDI
IN
CONF_TDO R254 20
4C2 2C5 OUT TDO
SEE SHEET 15
15D5 15D2 15C2 3D7 2D4 1C6 LB_LAD<15..0>

BI
NOTES:
1. THE PCB ASSEMBLY PART NUMBER IS 5268480. DRAWING NO. TO PART NO. CORRELATION MATRIX
CONFIGURATION DRAWING NO. PART NO. PART REV.

2. UNLESS OTHERWISE SPECIFIED:
CAPACITORS ARE IN MICROFARADS. 5265289SCH 5265289 1
A RESISTORS ARE IN OHMS. A
INDUCTORS ARE IN MICROHENRIES.
3. UNINSTALLED COMPONENTS ARE INDICATED BY

THE "NO_STUFF=REF" PROPERTY.
FORMAT PER PR12001
UNLESS OTHERWISE SPECIFIED DATE:

THIS DOCUMENT AND THE INFORMATION ORIGINAL DRAWN BY:
CONTAINED HEREIN IS CONFIDENTIAL AND DIMENSIONS ARE IN INCHES
PROPERTY OF OEC MEDICAL SYSTEMS, INC., TOLERANCES ARE: 12/01/09
A UNIT OF GE HEALTHCARE AND WHOLLY- F. FARRINGTON
OWNED SUBSIDIARY OF GENERAL ELECTRIC. FRACTIONS: +/- N/A DWG TITLE
IT IS DISCLOSED TO YOU FOR THE
SOLE PURPOSE OF YOUR PERFORMANCE DECIMALS: X +/- N/A ORIGINAL RESPONSIBLE ENGINEER: DATE: PC BOARD SCH
SYSTEMS. IT IS NOT TO BE COPIED OR
IN ANY WAY DISCLOSED TO THIRD PARTIES.
.X +/- N/A G. POPE 12/01/09 VORTEX DISPLAY ADAPTER ROHS
IT SHALL BE RETURNED TO OEC MEDICAL .XX +/- N/A
SYSTEMS UPON DEMAND. YOU HEREBY .XXX +/- N/A
AGREE TO THESE RESTRICTIONS AND SIZE DWG NO. REV
Tue Dec 01 13:18:33 2009

ALL LOSS OR DAMAGE ARISING
BREACH OF THIS OBLIGATION
FROM
BY YOU
ANGLES: +/- N/A
B 5265289SCH 1
OR ENTITIES OR AGENTS UNDER YOUR DO NOT SCALE DRAWING SCALE: SHEET
Master in Document Control CONTROL. NONE 1 OF 22
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
2
REV
1
1
U58
PCI9656_JMODE PCI9656_JMODE
AD<63..0> SPEED=66_MHZ 15D5 15D2 15C2 15B5 3D7 1C6 1A3 LB_LAD<31..0>
BI
P1 - A1 TRST* P1 - B68 63 63 T4 AD63 GNT1 N3 NC 31 N18 LAD31 LB_DACK<1..0>*
OUT 3D7
P1 - B2 TCK P1 - A68 62 62 U3 AD62 GNT2 R1 NC 30 N19 LAD30 DACK0 A13 0
P1 - A3 TMS P1 - B69 61 61 W1 AD61 GNT3 R2 NC 29 N20 LAD29 DACK1 C13 1 LB_DREQ<1..0>*

IN 3D4
P1 - A4 TDI P1 - A70 60 60 V3 AD60 GNT4 P4 NC 28 M17 LAD28 DREQ0 B13 0
Y2 U11 M18 A14

D P1 - B4 TDO P1
P1
-
-
B71
A71
59
58
59
58 W4
AD59
AD58
GNT5
GNT6 W12
NC
NC V3.3
27
26 M19
LAD27
LAD26
DREQ1
DMPAF/EOT D14
1
LB_DMPAF_EOT* 3D7
D
BI
P1 - A40 SDONE P1 - B72 57 57 V4 AD57 25 M20 LAD25 LB_DP<3..0>
BI 3D7
P1 - A41 SBO* P1 - A73 56 56 U5 AD56 24 L19 LAD24 DP3 D18 3 V3.3
P1 - B49 M66EN* P1 - B74 Y3 AD55 REQ1 P1 L18 LAD23 DP2 B20
V3.3
55 55 23 2
8
7
6
5
P1 - A74 54 54 Y4 AD54 REQ2 P2 D 22 L20 LAD22 DP1 C18 1
V5 T1 R167 K20 B19 R247

C591 P1 - B75 53 53 AD53 REQ3 21 LAD21 DP0 0
W5 R3 10K K19 10K

P1 - B9 PRSNT1* 0.01 P1 - A76 52 52 AD52 REQ4 20 LAD20 R168
P1 - B11 PRSNT2* P1 - B77 51 51 Y5 AD51 REQ5 Y12 19 K18 LAD19 CCS D12 LB_CCS*
IN 3D4 10K
- V6 AD50 REQ6 V12 PLX_REQ K17 LAD18
2
3
4
1
P1 A77 50 50 18
+12V
D P1 - B78 49 49 U7 AD49 17 J20 LAD17 LCLK D20 CLK_66M_PLX
IN 4A4
P1 - B1 P1 - A79 48 48 W6 AD48 16 J19 LAD16
P1 - A2 P1 - B80 47 47 Y6 AD47 MODE1 A19 PCI_MODE1 15 J18 LAD15 PMEREQ B10
P1 - A80 46 46 V7 AD46 MODE0 A20 PCI_MODE0 14 J17 LAD14 LRESET A16 LB_LRESET*
OUT 3D7 1B6 1C4
5V_PCI
VCC P1 - B81 45 45 W7 AD45 HOSTEN C15 LB_HOSTEN* 13 H20 LAD13 USERI_LLOCKI B14 CPLD_NSTATUS 1C6 15B2
-12V IN
P1 - A82 44 44 Y7 AD44 V3.3 12 H19 LAD12 USERO_LLOCKO C14 PLX_NCONFIG
OUT 1C6 15C5
P1 - A5 P1 - B83 43 43 V8 AD43 R170 11 H18 LAD11 WAIT B16 LB_WAIT*
BI 3D7
P1 - B5 CB6 P1 - A83 42 42 W8 AD42 CPCISW Y14 CPCISW 8 1 10 G20 LAD10
Y8 U12 CPCI64EN* 7 2 G19 A11
+
P1 - B6 3.0A C115 C116 P1 - B84 41 41 AD41 CPCI64EN 9 LAD9 PRESENT_DET V2.5

P1 - A8
100 100
P1 - A85 40 40 V9 AD40 BD_SEL C9 BD_SEL* 6 3 8 F20 LAD8 D
16V 16V
P1 - A61 P1 - B86 39 39 W9 AD39 ENUM Y13 5 4 7 G18 LAD7 VAUX_2V5 D10
P1 - A62 P1 - A86 38 38 Y9 AD38 LED_ON V13 6 F19 LAD6
37 W10
10K D E20 C11 C582 C595 C583 C597 C589 C563 C552 C598 C603
P1 - B61 P1 - B87 37 AD37 5 LAD5 VCORE
36 V10 G17 C19 0.01 0.01 0.01 0.01 0.1 0.1 0.1 0.1 2.2
P1 - B62 P1 - A88 36 AD36 4 LAD4 VCORE
CB5 D P1 - B89 35 35 Y10 AD35 EESK A12 PLX_EESK 2A1 3 F18 LAD3 VCORE E2
V3.3_PCI IN
3.0A P1 - A89 34 34 Y11 AD34 EECS B12 PLX_EECS 2A1 2 E19 LAD2 VCORE P3
D IN
33 W11 B11 E18 U9
C P1
P1
-
-
A21
B25
P1
P1
-
-
B90
A91
33
32 V11
AD33
AD32
EEDI/EEDO PLX_EED
IN 2A1 1
D19
LAD1
LAD0
VCORE
VCORE U19
D C
V3.3
32 0
A5
C134
C132
C133
C131
P1 - A27 P1 - B20 31 31 AD31

P1 - B31 P1 - A20 30 30 D7 AD30 TRST D9 TRST*
IN 3A7 4D1 3D7 OUT
LB_DTR* W14 DIR VAUX_CARD C10
P1 - A33 P1 - B21 29 29 C6 AD29 TCK A8 TCK
IN 3A7 4D1 3D7 OUT
LB_DEN* Y15 DEN
B5 A7 CONF_TDO LB_ALE V14 W2
0.1
0.1
0.1
0.1
P1 - B36 P1 - A22 28 28 AD28 TDI IN 1B6 3D7 BI ALE VDDA

A4 C8 R169 20 PLX_TDO W15
P1 - A39 P1 - B23 27 27 AD27 TDO OUT 4C2 NC LA28
P1 - B41 P1 - A23 26 26 C5 AD26 TMS B8 TMS
IN 3A7 4D1 NC Y16 LA27 VRING A1
P1 - B43
D P1 - B24 25 25 B4 AD25 NC U14 LA26 VRING D4
P1 - A45 P1 - A25 24 24 A3 AD24 NC V15 LA25 VRING D6
P1 - A53 P1 - B27 23 23 B3 AD23 NC W16 LA24 VRING D8
P1 - B54 P1 - A28 22 22 B2 AD22 NC Y17 LA23 VRING D11
P1 - A14 NC P1 - B29 21 21 A2 AD21 NC V16 LA22 VRING D13 C562 C588 C590 C553 C606 C561 C596 C557 C586 C564 C555
P1 - A29 20 20 C3 AD20 NC W17 LA21 VRING D15 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.1 0.1 0.1
P1 - B30 19 19 B1 AD19 NC Y18 LA20 VRING D17
P1 - A10 P1 - A31 18 18 C2 AD18 NC U16 LA19 VRING F4
P1 - A16 200 R166 P1 - B32 17 17 D2 AD17 NC V17 LA18 VRING F17
P1 - B19 P1 - A32 16 16 D3 AD16 PME B9 NC W18 LA17 VRING H4 D
P1 - A59 200 R165 P1 - A44 15 15 H3 AD15 NC Y19 LA16 VRING H17
P1 - B59 P1 - B45 14 14 H2 AD14 NC V18 LA15 VRING K4 C587 C580 C585 C558 C578 C556 C592 C584 C594 C559
P1 - A66 200 R187 P1 - A46 13 13 H1 AD13 IDSEL C4 PCI_IDSEL P1 - A26 V2.5 NC W19 LA14 VRING L17 0.01 0.01 0.01 0.01 0.1 0.1 0.1 0.1 0.1 0.1
P1 - B70 P1 - B47 12 12 J4 AD12 FRAME C1 PCI_FRAME* P1 - A34 NC Y20 LA13 VRING N4
P1 - A75 200 R186 P1 - A47 11 11 J3 AD11 DEVSEL E1 PCI_DEVSEL* P1 - B37 NC W20 LA12 VRING N17
P1 - B79 P1 - B48 10 10 J2 AD10 LOCK G4 PCI_LOCK* P1 - B39 NC V19 LA11 VRING R4
P1 - A84 P1 - A49 9 9 J1 AD9 IRDY D1 PCI_IRDY* P1 - B35 NC U18 LA10 VRING R17 D
P1 - B88 P1 - B52 8 8 K2 AD8 IDQEN A10 NC T17 LA9 VRING U4
K1 V20 U6
B P1 - B3
P1
P1
-
-
B53
A54
7
6
7
6 L2
AD7
AD6
IDQEN* NC
NC U20
LA8
LA7
VRING
VRING U8
C593
0.1
C605
0.1
C554
0.1
B
P1 - B15 P1 - B55 5 5 L3 AD5 PCLK L1 PCI_CLK P1 - B16 NC T18 LA6 VRING U10
P1 - B17 P1 - A55 4 4 L4 AD4 NC T19 LA5 VRING U13
P1 - B22 P1 - B56 3 3 M1 AD3 NC T20 LA4 VRING U15
P1 - B28 P1 - A57 2 2 M2 AD2 INTA B7 PCI_INTA* P1 - A6 1C6 3D7 LB_LBE<3..0>* NC R18 LA3 VRING U17 D
BI
P1 - B34 P1 - B58 1 1 M3 AD1 RST A6 PCI_RST* P1 - A15 15B4 NC P17 LA2
M4 G3 PCI_SERR* J9 C604 C565 C551 C602
P1 - B38 P1 - A58 0 0 AD0 SERR P1 - B42 VSS
V3.3 R20 J10 2.2 2.2 2.2 2.2
P1 - B46 3 LBE3 VSS
CBEN<7..0>
R248 P18 J11
P1 - B57 2 LBE2 VSS
E3 PCI_TRDY*
10K P19 J12
P1 - B64 TRDY P1 - A36 1 LBE1 VSS
P1 - B67 P1 - A64 7 7 T2 CBE7 STOP F3 PCI_STOP* P1 - A38 0 P20 LBE0 VSS K9
U1 LB_BIGEND* C12 K10 V3.3 U48 D
P1 - B73 P1 - B65 6 6 CBE6 3D4 IN BIGEND VSS
P1 - B76 P1 - A65 5 5 T3 CBE5 3D7 OUT
LB_LSERR* D16 LSERR VSS K11 FM93CS56L
P1 - B82 P1 - B66 4 4 U2 CBE4 PERR F2 PCI_PERR* P1 - B40 15D7 1C6 IN
PLX_INTI* B15 LINTI VSS K12 8 VCC SK 2 PLX_EESK
OUT 1C6 2C5
P1 - B85 P1 - B26 3 3 D5 CBE3 PAR64 V1 PCI_PAR64* P1 - A67 3D7 OUT
LB_LINTO* A15 LINTO VSS L9 6 PE CS 1 PLX_EECS
OUT 2C5
P1 - B91 P1 - B33 2 2 E4 CBE2 PAR G2 PCI_PAR P1 - A43 15C5 1C6 OUT
PLX_LHOLD B18 LHOLD VSS L10 7 PRE DI 3 PLX_EED
OUT 1C6 2C5
C512
P1 - B94 P1 - B44 1 1 G1 CBE1 15C5 1C6 IN
PLX_LHOLDA B17 LHOLDA VSS L11 C511 DO 4
P1 - A18 P1 - A52 0 0 K3 CBE0 15C5 1C6 3D7 BI

LB_BLAST* A18 BLAST VSS L12 0.1
0.01
P1 - A24 ACK64 N1 PCI_ACK64* P1 - B60 3D7 BI
LB_BTERM* C20 BTERM VSS M9
P1 - A30 REQ64 N2 PCI_REQ64* P1 - A60 15C5 1C6 IN
PLX_BREQI C16 BREQI VSS M10
P1 - A35 A9 VIO 15C5 1C6 OUT
PLX_BREQO A17 BREQO VSS M11 PRE
P1 - A37 F1 VIO 15B5 1C6 3D7 BI

LB_ADS* C17 ADS VSS M12 D PE
P1 - A42 C579 C600 C599 C581 V2 VIO GNT0/REQ C7 PCI_REQ* P1 - B18 15B5 3D7 1C6 LB_READY* E17 READY VSSA Y1 REF
8
7
6
5
BI
P1 - A48 0.1 0.1 0.01 0.01 W13 VIO REQ0/GNT B6 PCI_GNT* P1 - A17 3D7 1C6 BI
LB_WR R19 LWR VBB W3
V3.3 R154 R153
P1 - A56
PACK_TYPE=PBGA 1K 1K
A P1 - A63
D A
P1 - A69
-
2
3
4
1
P1 A72
P1 - A78 D PCI
FORMAT PER PR12001
P1 - A81 D
P1 - A87
P1 - A90
P1 - A93
D SIZE DWG NO. REV
B 5265289SCH 1
Tue Dec 01 13:17:30 2009 SCALE: N/A SHEET 2 OF 22
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
3
REV
1
1
LB_ADS*
U45 LB_CCS*
15B5 1C6 2A4 BI LB_ADS SECTION 1 OF VP LB_CCS OUT 2D2
2C4 LB_ALE LB_ALE LB_BIGEND LB_BIGEND* 2A4
BI OUT
PLX PCI9656
2C4 LB_DEN* LB_DEN LB_BREQI DA_BREQI 15C2 1C6
IN OUT
15C5 1C6 2A4 LB_BLAST* LB_BLAST
BI SECTION 2 OF VP
15C2 1C6 DA_BREQO LB_BREQO LB_DREQ<1..0> LB_DREQ<1..0>* 2D2
OUT OUT
2A4 LB_BTERM* LB_BTERM RESET_DISABLE LFT_WS_VP_DDC_CLK LFT_WS_VP_DDC_CLK 11A2
BI OUT
2C4 LB_DTR* LB_DTR LB_HOLDA DA_HOLDA 1C6 15C2 LFT_WS_VP_DDC_DATA LFT_WS_VP_DDC_DATA 11A2
IN IN BI
2D2 LB_DMPAF_EOT* LB_DMPAF/EOT DA_PCI_IRQ DA_PCI_IRQ 1C6 15C2 RT_WS_VP_DDC_CLK RT_WS_VP_DDC_CLK 11A2
BI OUT OUT
2D2 LB_DP<3..0> LB_DP<3..0> RT_WS_VP_DDC_DATA RT_WS_VP_DDC_DATA 11A2
BI D BI
2D2 LB_DACK<1..0>* LB_DACK<1..0> LVBUF_CLK LVBUF_CLK 5C7 RT_X_VP_DDC_CLK RT_X_VP_DDC_CLK 11A2
IN OUT OUT
D LVBUF_CKE LVBUF_CKE
OUT 5C7 RT_X_VP_DDC_DATA RT_X_VP_DDC_DATA
BI 11A2 D
15D5 15D2 15C2 15B5 2D4 1C61A3 LB_LAD<31..0> LB_LAD<31..0> LVBUF_CAS LVBUF_CAS* 5C7
BI OUT
15B4 1C62B4 LB_LBE<3..0>* LB_LBEN<3..0> LVBUF_RAS LVBUF_RAS* 5C7 LFT_WS_CVID_EN LFT_WS_CVE 14C2
BI OUT OUT
1C6
15C2 DA_HOLD LB_HOLD LVBUF_WE LVBUF_WE* 5C7 LFT_WS_OE LFT_WS_OE* 11B7
OUT OUT OUT
2A4 LB_LINTO* LB_LINTO LVBUF_CS LVBUF_CS* 5C7 LFT_WS_SEL LFT_WS_SEL 11B7
IN OUT OUT
1C4 1B6 2D2 LB_LRESET* LB_LRESET LVBUF_DQM<3..0> LVBUF_DQM<3..0> 5C7 LFT_WS_HSYNC LFT_WS_HSYNC 11C7
BI OUT OUT
2A4 LB_LSERR* LB_LSERR LVBUF_ADR<12..0> LVBUF_ADR<12..0> 5C7 LFT_WS_VSYNC LFT_WS_VSYNC 11B7
IN OUT OUT
2A4 1C6 LB_WR LB_WR LVBUF_BA<1..0> LVBUF_BA<1..0> 5C7 LFT_WS_C3 LFT_WS_C3 11C5
BI OUT OUT
15B5 2A4 1C6 LB_READY* LB_READY LVBUF_DQ<31..0> LVBUF_DQ<31..0> 5C7 LFT_WS_DVI_CLK LFT_WS_DVI_CLK 11C6
BI BI OUT
2C2 LB_WAIT* LB_WAIT LFT_WS_DVI_SCL LFT_WS_DVI_SCL 11C5
BI OUT
LOBUF_CLK LOBUF_CLK 5D7 LFT_WS_DVI_SDA LFT_WS_DVI_SDA 11C5
OUT BI
P8 - 2 LCLKH IP_LCLKH LOBUF_CKE LOBUF_CKE 5D7 LFT_WS_DVI_DE LFT_WS_DVI_DE 11C5
OUT OUT
P8 - 3 LCLKL IP_LCLKL VP LOBUF_CAS LOBUF_CAS*
OUT 5D7 LFT_WS_DVI_HSYNC LFT_WS_DVI_HSYNC
OUT 11C5
P8 - 7 LS1 IP_LS1 VIDEO LOBUF_RAS LOBUF_RAS* 5D7 LFT_WS_DVI_VSYNC LFT_WS_DVI_VSYNC 11C5
OUT OUT
P8 - 5 LS0 IP_LS0 PROCESSOR LOBUF_WE LOBUF_WE* 5D7 LFT_WS_DVI_ISEL LFT_WS_DVI_ISEL 11C5
OUT OUT
P8 - 15 LD4 IP_LD4 LOBUF_CS LOBUF_CS* 5D7 LFT_WS_DV<11..0> LFT_WS_DV<11..0> 8B8 11B5
OUT OUT
P8 - 13 LD3 IP_LD3 LOBUF_DQM<3..0> LOBUF_DQM<3..0> 5D7
OUT
P8 - 12 LD2 IP_LD2 LOBUF_ADR<12..0> LOBUF_ADR<12..0> 5D7 LFT_X_CS LFT_X_CS 14C7
OUT OUT
P8 - 10 LD1 IP_LD1 LOBUF_BA<1..0> LOBUF_BA<1..0> 5D7 LFT_X_OE LFT_X_OE* 14D7
OUT OUT
P8 - 9 LD0 IP_LD0 LOBUF_DQ<31..0> LOBUF_DQ<31..0> 5D7 LFT_X_BLK LFT_X_BLK 14D7
BI OUT
P8 - 16 LD5 IP_LD5 LFT_X_SEL LFT_X_SEL 14D7
OUT
RVBUF_CLK RVBUF_CLK 6C7
OUT
P8 - 19 RCLKH IP_RCLKH RVBUF_CKE RVBUF_CKE 6C7 RT_WS_CVID_EN RT_WS_CVE 14D2
OUT OUT
P8 - 20 RCLKL IP_RCLKL RVBUF_CAS RVBUF_CAS* 6C7 RT_WS_OE RT_WS_OE* 12B7
OUT OUT
P8 - 24 RS1 IP_RS1 RVBUF_RAS RVBUF_RAS* 6C7 RT_WS_SEL RT_WS_SEL 12B7
OUT OUT
P8 - 22 RS0 IP_RS0 RVBUF_WE RVBUF_WE* 6C7 RT_WS_HSYNC RT_WS_HSYNC 12C7
OUT OUT
C P8 - 32 RD4 IP_RD4 RVBUF_CS RVBUF_CS*
OUT 6C7 RT_WS_VSYNC RT_WS_VSYNC
OUT 12B7 C
P8 - 30 RD3 IP_RD3 RVBUF_DQM<3..0> RVBUF_DQM<3..0> 6C7 RT_WS_C3 RT_WS_C3 12C5
OUT OUT
P8 - 29 RD2 IP_RD2 RVBUF_ADR<12..0> RVBUF_ADR<12..0> 6C7 RT_WS_DVI_CLK RT_WS_DVI_CLK 12C6
OUT OUT
P8 - 27 RD1 IP_RD1 RVBUF_BA<1..0> RVBUF_BA<1..0> 6C7 RT_WS_DVI_SCL RT_WS_DVI_SCL 12C5
OUT OUT
P8 - 26 RD0 IP_RD0 RVBUF_DQ<31..0> RVBUF_DQ<31..0> 6C7 RT_WS_DVI_SDA RT_WS_DVI_SDA 12C5
BI BI
P8 - 33 RD5 IP_RD5 RT_WS_DVI_DE RT_WS_DVI_DE 12C5
OUT
ROBUF_CLK ROBUF_CLK 6D7 RT_WS_DVI_HSYNC RT_WS_DVI_HSYNC 12C5
OUT OUT
4C8 OSC_EN_109M OSC_EN_109M ROBUF_CKE ROBUF_CKE 6D7 SEL_WS_CLK RT_WS_DVI_VSYNC RT_WS_DVI_VSYNC 12C5
6
OUT OUT OUT

4B8 OSC_EN_102M OSC_EN_102M ROBUF_CAS ROBUF_CAS* 6D7 WS_CLK RT_WS_DVI_ISEL RT_WS_DVI_ISEL 12C5
OUT OUT OUT
OSC_EN_138M ROBUF_RAS* RT_WS_DV<11..0>
R118
R127
R128
R126
4B8 OUT OSC_EN_138M ROBUF_RAS OUT 6D7 SEL_EXT_CLK RT_WS_DV<11..0> OUT 9B7 12B5
ROBUF_WE*
75
75
75
75
ROBUF_WE OUT 6D7 EXT_CLK

XOSC_109M ROBUF_CS* RT_X_BNC_SEL
3
4C5 XOSC_109M ROBUF_CS 6D7 RT_X_BNC_SEL 14D7

1
IN OUT OUT
4C5 XOSC_102M XOSC_102M ROBUF_DQM<3..0> ROBUF_DQM<3..0> 6D7 11D5 SB2_HSYNCO SB2_HSYNC RT_X_BNC_OE RT_X_BNC_OE* 14D7
IN OUT IN OUT
6
4A4 CLK_66M_A CLK_66M_A ROBUF_ADR<12..0> ROBUF_ADR<12..0> 6D7 11D5 SB2_VSYNCO SB2_VSYNC RT_X_CS RT_X_CS 14C7
IN OUT IN OUT
C333
C407
C405
C408
330P
330P
330P
330P
4A4 CLK_66M_B CLK_66M_B ROBUF_BA<1..0> ROBUF_BA<1..0> 6D7 11A2 SB2_VP_DDC_CLK SB2_VP_DDC_CLK RT_X_OE RT_X_OE* 13B8
IN OUT IN OUT
4B5 XOSC_138M XOSC_138M ROBUF_DQ<31..0> ROBUF_DQ<31..0> 6D7 11A2 SB2_VP_DDC_DATA SB2_VP_DDC_DATA RT_X_BLK RT_X_BLK 14D7
IN BI BI OUT
11D5 SB2_MSEN_VP SB2_MSEN_VP RT_X_SEL RT_X_SEL 13A8
BI OUT
3
2
1
FPGA_TST1<17..0> FPGA_TST1<17..0> 4A3 RT_X_HSYNC RT_X_HSYNC 13B8

OUT OUT
15D7 1D6 CLK_10HZ CLK_10HZ FPGA_TST2<17..0> FPGA_TST2<17..0> 4A3 11D5 SB1_HSYNCO SB1_HSYNC RT_X_VSYNC RT_X_VSYNC 13B8
OUT OUT IN OUT
11D5 SB1_VSYNCO SB1_VSYNC RT_X_C3 RT_X_C3 13C5
V3.3 R229 10K IN OUT
DEV_OE LFT_WSDAC_CLK LFT_WSDAC_CLK 8D8 11A2 SB1_VP_DDC_CLK SB1_VP_DDC_CLK RT_X_DVI_CLK RT_X_DVI_CLK 13C7
OUT IN OUT
DEV_CLR_N LFT_WSDAC_BLANK LFT_WSDAC_BLANK* 8D8 11A2 SB1_VP_DDC_DATA SB1_VP_DDC_DATA RT_X_DVI_SCL RT_X_DVI_SCL 13C6
OUT BI OUT
R158 10K BOOT_DISPLAY LFT_WSDAC_SYNC LFT_WSDAC_SYNC* 8C8 11D5 SB1_MSEN_VP SB1_MSEN_VP RT_X_DVI_SDA RT_X_DVI_SDA 13C6
OUT BI BI
D LFT_WSDAC_SYNCT LFT_WSDAC_SYNCT 8C8 RT_X_DVI_DE RT_X_DVI_DE 13C5
OUT OUT
15C2 1B8 DA_INIT_DONE INIT_DONE LFT_WSDAC_M2 LFT_WSDAC_M2 8C8 11D5 LFT_WS_HPO LFT_WS_HPO RT_X_DVI_HSYNC RT_X_DVI_HSYNC 13C5
OUT OUT IN OUT
15B2 1C6 DA_NCONFIG NCONFIG LFT_WSDAC_M1 LFT_WSDAC_M1 8C8 RT_X_DVI_VSYNC RT_X_DVI_VSYNC 13C5
V3.3 IN OUT OUT
B 15B2 1B6 OUT
VP_NSTATUS NSTATUS 11D5 IN
RT_WS_HPO RT_WS_HPO RT_X_DVI_ISEL RT_X_DVI_ISEL
OUT 13C5 B
15B2 1B6 DA_DCLK DCLK RT_X_DV<11..0> RT_X_DV<11..0> 13B6
IN OUT
S1 DA_DATAO LFT_XDAC_CLK
R55 15B2 1B6 BI DATAO LFT_XDAC_CLK OUT 8D5
P1 1 1K 15B2 1B6 DA_CONF_DONE CONFIG_DONE LFT_XDAC_BLANK LFT_XDAC_BLANK* 8D5 11D5 RT_X_HPO RT_X_HPO TV_CS TV_CS 14C7
R54 OUT OUT IN OUT
2 100 NCE NCE LFT_XDAC_SYNC LFT_XDAC_SYNC* 8D5 TV_BLK TV_BLK 14D7
OUT OUT
P2 3 R159 10K LFT_XDAC_SYNCT LFT_XDAC_SYNCT 8C5
OUT
P3 4D5 VTM_TEMP_N VTM_TEMP_N LFT_XDAC_M2 LFT_XDAC_M2 8C5
OUT OUT
4D5 VTM_TEMP_P VTM_TEMP_P LFT_XDAC_M1 LFT_XDAC_M1 8C5
OUT OUT
VTM_SDA LFT_XDAC_VID<9..0> LFT_XDAC_VID<9..0> 8B5
D OUT
4D5 VTM_SCL VTM_SCL
OUT
4D5 IN
VTM_INT* VTM_INT RT_WSDAC_CLK RT_WSDAC_CLK
OUT 9C7 V3.3
VCCSEL RT_WSDAC_BLANK RT_WSDAC_BLANK* 9C7
OUT
RT_WSDAC_SYNC RT_WSDAC_SYNC* 9C7
OUT
RT_WSDAC_SYNCT RT_WSDAC_SYNCT 9C7
D OUT
RT_WSDAC_M2 RT_WSDAC_M2 9C7
1
OUT
P8 - 1
RT_WSDAC_M1
RT_WSDAC_M1 OUT 9C7
P8 - 4
RED
RED
TOP
BOT
GRN
RED
DS1
-
DS2
P8 6
P8 - 8
RT_XDAC_CLK
RT_XDAC_CLK OUT 9C4
P8 - 11
RT_XDAC_BLANK* 9C4
2
RT_XDAC_BLANK
1
OUT
P8 - 14
RT_XDAC_SYNC* LB_ACTIVE*
RT_XDAC_SYNC OUT 9C4 15C2 1B6 IN
P8 - 17
BRD_ID<3..0> RT_XDAC_SYNCT CONF_LED*
BRD_ID<3..0> RT_XDAC_SYNCT OUT 9C4 15C4 1B6 IN
P8 - 18
RT_XDAC_M2
RT_XDAC_M2 9C4
3
0
1
OUT
P8 - 21
RT_XDAC_M1
RT_XDAC_M1 OUT 9C4
P8 - 23
RT_XDAC_VID<9..0>
R157 R156 R250 R155 RT_XDAC_VID<9..0> 9B4
3
1
OUT
P8 - 25
1K 1K 1K 1K
A P8
P8
-
-
28
31
REF REF REF REF
TV_DAC_CLK TV_DAC_CLK
OUT 7D6 A
TV_DAC_BLANK TV_DAC_BLANK* 7D6
OUT
P8 - 34
TV_DAC_SYNC*
TV_DAC_SYNC OUT 7C6
TV_DAC_SYNCT TV_DAC_SYNCT 7C6
D
OUT
VP (VIDEO PROCESSOR)
FORMAT PER PR12001
TV_DAC_M2 TV_DAC_M2 7C6

D OUT
2C5 4D1 TRST* TRST TV_DAC_M1 TV_DAC_M1 7C6
OUT OUT
15C7 2C5 1B6 4D1 TMS TMS TV_DAC_VID<9..0> TV_DAC_VID<9..0> 7B6
OUT OUT
15C4 2C5 1B6 4D1 TCK TCK
4D1
OUT
TDI TDI LED_IND<3..0> LED_IND<3..0>* GE HEALTHCARE - SURGERY
IN
4C2 1B6 VP_TDO TDO
OUT
SEE SHEETS 16 & 17 SIZE DWG NO. REV
R228
20 B 5265289SCH 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
4
REV
1
1
V3.3
V3.3 V3.3
C334 REF JTAG HEADER P9 - 6 TRST*
OUT 3A7 2C5
0.1 R91 R117
U32 REF V3.3
10
10K 1K
ADM1025 U20
4 VCC SDA 1 P9 - 4 P9 - 5 9 8 TMS 3A7 1B6
ANA_V33A OUT
P9 2 2C5 15C7
D SCL - 74LCX125
D
2
A
V1.5 V1.8 V2.5 D GND P9 -
R94
3
D 10
C VID3
13
8
511 VTM_SCL
12 5VIN VID2 7
IN 3B7 U20
R93 D TCK
13 3.3VIN VID1 6 C332 P9 - 1 12 11
OUT 3A7 1B6
R92 511 2C5 15C4
14 2.5VIN VID0 5 1000P P9 - 7 NC 74LCX125
R90 511 8
15 VCCIN P9 - NC
VTM_TEMP_N
R261
511 D-/NTI 9 3B7
4
IN 75
16 ADD/NTO U20
C270 C269 C268 C267 RST/INT D+ 10 VTM_TEMP_P 3B7 5 6 TDI 3A7 15C7
IN OUT
P9 - 9
2.2 2.2 2.2 2.2 12VIN/VID4 11 74LCX125
V3.3 C601
PACK_TYPE=QSOP
220P
2
VOLTAGE AND TEMP MONITOR VTM_INT*
OUT 1D6 3B7 15C5 R50
7 2 R53
TS_BUF_JTAG
8 1 10K
D
D
1
5 4
6 3
1K D
1
R51
20
P9 - 3 3 2
74LCX125
REF V3.3 V3.3 U20
V3.3 L26
1UH REF REF
C16
R179 R182 0.1
C REF
C576 REF
C120
REF
C119 10K 10K C
2.2 1000P
0.01
D
1
REF
Y2 102MHZ R48
D R178
PLX_TDO
0
4
V3.3 2C5 IN
20
3C6 OSC_EN_109M 1
EN CLK 3 XOSC_109M 3C6 R49
IN OUT
VP_TDO
0
REF 3A7 IN
V3.3 L28 OSCSMT5X7
REF
R52 REF
CONF_TDO
0
1UH REF Y4 102MHZ 1B6 IN
R181 REF
4
V3.3 20
REF REF
1 3 XOSC_102M 3C6
REF EN CLK OUT
C574
C124 C123
2.2 REF
0.01 1000P OSCSMT5X7
D
V3.3 5V_PCI
3C6 OSC_EN_102M
IN VCC
REF REF
V3.3 L27 REF R259 REF
1UH Y3 102MHZ 10K R119
4
R180 0
V3.3 20
REF
REF REF 1
EN CLK 3 XOSC_138M
OUT 3B6 FPGA TEST HEADER 1 FPGA TEST HEADER 2
C575
C122 C121
2.2 REF
B 0.01 1000P OSCSMT5X7
REF REF B
P10 - 1 P11 - 1
V3.3
17 P10 - 19 17 P11 - 19
D P10 - 18 P11 - 18
V3.3
16 16
3C6 OSC_EN_138M 15 P10 - 17 15 P11 - 17

IN
14 P10 - 16 14 P11 - 16
R251 U55
V3.3 L25 13 P10 - 15 13 P11 - 15
10K C541 C540 C539
1UH 49FCT3805 12 P10 - 14 12 P11 - 14
R252 2.2 0.01 0.01
12 OEB 11 P10 - 13 11 P11 - 13
10K 9 OEA 10 P10 - 12 10 P11 - 12
C577 C118 C117 9 P10 - 11 9 P11 - 11
2.2 0.1 0.01
MON
13
D 8 P10 - 10 8 P11 - 10
D 11 INB OB4 14 7 P10 - 9 7 P11 - 9
OB3 15 6 P10 - 8 6 P11 - 8
OB2 17 5 P10 - 7 5 P11 - 7
V3.3 D Y1 66MHZ OB1 18 4 P10 - 6 4 P11 - 6
4
V3.3 OB0 19 3 P10 - 5 3 P11 - 5
1 3 10 INA OA4 7 CLK_CONF_66M 1D6 15C2 - -
EN CLK OUT
2 P10 4 2 P11 4
R260 R177 OA3 6 CLK_66M_A 3B6 1 P10 - 3 1 P11 - 3
OUT
20 CLK_66M_B
10K OA2 4
OUT 3B6 0 P10 - 2 0 P11 - 2
OA1 3 P10 - 20
OA0 2 CLK_66M_PLX 2D2 P11 - 20
OUT
3B4 FPGA_TST1<17..0>
PACK_TYPE=QSOP IN
D
3B4 FPGA_TST2<17..0> D
IN
R255 R237 R227 R253
A 75 75 75 75 A
CLOCKS, HEADERS AND
C560 C449 C394 C546
FORMAT PER PR12001
220P 220P 220P 220P VOLTAGE & TEMPERATURE MONITORS
D
SIZE DWG NO. REV
B 5265289SCH 1

8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
5
REV
1
1
LOBUF
U25
SDRAM_256MBIT V3.3
SPEED=7E
3D4 LOBUF_CLK 38 CLK VDD 1
IN
3D4 LOBUF_CKE 37 CKE VDD 14
IN
3D4 LOBUF_CAS* 17 CAS VDD 27
IN
3D4 LOBUF_RAS* 18 RAS VDDQ 3
IN
3C4 LOBUF_WE* 16 WE VDDQ 9
IN
3C4 LOBUF_CS* 19 CS VDDQ 43
IN
D 3 15 DQML VDDQ 49
D
2 39 DQMH
VSS 28
3C4 LOBUF_DQM<3..0> VSS 41

IN
VSS 54
3C4 LOBUF_ADR<12..0> VSSQ 6 D

IN
VSSQ 12
3C4 LOBUF_BA<1..0> VSSQ 46

IN
VSSQ 52
3C4 LOBUF_DQ<31..0>
BI
12 36 A12 DQ15 53 31
11 35 A11 DQ14 51 30
LVBUF U33
10 22 A10 DQ13 50 29
SDRAM_256MBIT V3.3 9 34 A9 DQ12 48 28
SPEED=7E 8 33 A8 DQ11 47 27
3D4 LVBUF_CLK 38 CLK VDD 1 7 32 A7 DQ10 45 26

IN
3D4 LVBUF_CKE 37 CKE VDD 14 6 31 A6 DQ9 44 25
IN
3D4 LVBUF_CAS* 17 CAS VDD 27 5 30 A5 DQ8 42 24
IN
3D4 LVBUF_RAS* 18 RAS VDDQ 3 4 29 A4 DQ7 13 23
IN
3D4 LVBUF_WE* 16 WE VDDQ 9 3 26 A3 DQ6 11 22
IN
3D4 LVBUF_CS* 19 CS VDDQ 43 2 25 A2 DQ5 10 21
IN
3 15 DQML VDDQ 49 1 24 A1 DQ4 8 20
2 39 DQMH 0 23 A0 DQ3 7 19
VSS 28 DQ2 5 18
3D4 LVBUF_DQM<3..0> VSS 41 1 21 BA1 DQ1 4 17

IN
C LVBUF_ADR<12..0>
VSS 54
D
0 20 BA0 DQ0 2 16
C
3D4 IN VSSQ 6
VSSQ 12 PACK_TYPE=TSOPII
3D4 LVBUF_BA<1..0> VSSQ 46
IN U26
VSSQ 52
3D4 BI
LVBUF_DQ<31..0> SDRAM_256MBIT V3.3
SPEED=7E
12 36 A12 DQ15 53 31 38 CLK VDD 1
11 35 A11 DQ14 51 30 37 CKE VDD 14
10 22 A10 DQ13 50 29 17 CAS VDD 27
9 34 A9 DQ12 48 28 18 RAS VDDQ 3
8 33 A8 DQ11 47 27 16 WE VDDQ 9
7 32 A7 DQ10 45 26 19 CS VDDQ 43
R204
75
6 31 A6 DQ9 44 25 1 15 DQML VDDQ 49
5 30 A5 DQ8 42 24 0 39 DQMH
4 29 A4 DQ7 13 23 VSS 28
3 26 A3 DQ6 11 22 C258 VSS 41
2 25 A2 DQ5 10 21 220P VSS 54
1 24 A1 DQ4 8 20 VSSQ 6 D
V3.3 0 23 A0 DQ3 7 19 VSSQ 12
DQ2 5 18 VSSQ 46
1 21 BA1 DQ1 4 17 D VSSQ 52
0 20 BA0 DQ0 2 16
C260
C205 C326 C321 C323 C384 C387 C320
2.2 PACK_TYPE=TSOPII 12 36 A12 DQ15 53 15
0.01 0.01 0.01 0.01 0.01 0.01 0.01 11 35 A11 DQ14 51 14
U34
B V3.3
10 22 A10 DQ13 50 13
B
SDRAM_256MBIT 9 34 A9 DQ12 48 12
SPEED=7E 8 33 A8 DQ11 47 11
D 38 CLK VDD 1 7 32 A7 DQ10 45 10
V3.3 37 CKE VDD 14 6 31 A6 DQ9 44 9
17 CAS VDD 27 5 30 A5 DQ8 42 8
18 RAS VDDQ 3 4 29 A4 DQ7 13 7
16 WE VDDQ 9 3 26 A3 DQ6 11 6
C319 19 CS VDDQ 43 2 25 A2 DQ5 10 5

R226
C324 C328 C386 C322 C318 C266 C317

75
2.2 1 15 DQML VDDQ 49 1 24 A1 DQ4 8 4

0.01 0.01 0.01 0.01 0.01 0.01 0.01
0 39 DQMH 0 23 A0 DQ3 7 3
VSS 28 DQ2 5 2
C383 VSS 41 1 21 BA1 DQ1 4 1
220P VSS 54 0 20 BA0 DQ0 2 0
D VSSQ 6 D
V3.3 VSSQ 12 PACK_TYPE=TSOPII
VSSQ 46
D VSSQ 52
C325
C331 C385 C204 C263 C203 C262 C202
2.2 12 36 A12 DQ15 53 15
0.01 0.01 0.01 0.01 0.01 0.01 0.01 11 35 A11 DQ14 51 14
10 22 A10 DQ13 50 13
9 34 A9 DQ12 48 12
8 33 A8 DQ11 47 11
V3.3 D 7 32 A7 DQ10 45 10
A 6 31 A6 DQ9 44 9
A
5 30 A5 DQ8 42 8
4 29 A4 DQ7 13 7
C264 3 26 A3 DQ6 11 6
LOBUF AND LVBUF MEMORY FOR VP_FPGA
C265 C327 C261 C201 C200 C329 C259
FORMAT PER PR12001
2.2 2 25 A2 DQ5 10 5
0.01 0.01 0.01 0.01 0.01 0.01 0.01
1 24 A1 DQ4 8 4
0 23 A0 DQ3 7 3
DQ2 5 2
1 21 BA1 DQ1 4 1 GE HEALTHCARE - SURGERY

D 0 20 BA0 DQ0 2 0
SIZE DWG NO. REV

PACK_TYPE=TSOPII B 5265289SCH 1

8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
6
REV
1
1
ROBUF
U57
SDRAM_256MBIT V3.3
SPEED=7E
3C4 ROBUF_CLK 38 CLK VDD 1
IN
3C4 ROBUF_CKE 37 CKE VDD 14
IN
3C4 ROBUF_CAS* 17 CAS VDD 27
IN
3C4 ROBUF_RAS* 18 RAS VDDQ 3
IN
3C4 ROBUF_WE* 16 WE VDDQ 9
IN
3C4 ROBUF_CS* 19 CS VDDQ 43
IN
D 3 15 DQML VDDQ 49 D
2 39 DQMH
VSS 28
3C4 ROBUF_DQM<3..0> VSS 41

IN
VSS 54
3B4 ROBUF_ADR<12..0> VSSQ 6 D

IN
VSSQ 12
3B4 ROBUF_BA<1..0> VSSQ 46

IN
VSSQ 52
3B4 ROBUF_DQ<31..0>
BI
12 36 A12 DQ15 53 31
11 35 A11 DQ14 51 30
RVBUF U47 10 22 A10 DQ13 50 29
SDRAM_256MBIT V3.3 9 34 A9 DQ12 48 28
SPEED=7E 8 33 A8 DQ11 47 27
3C4 RVBUF_CLK 38 CLK VDD 1 7 32 A7 DQ10 45 26

IN
3C4 RVBUF_CKE 37 CKE VDD 14 6 31 A6 DQ9 44 25
IN
3C4 RVBUF_CAS* 17 CAS VDD 27 5 30 A5 DQ8 42 24
IN
3C4 RVBUF_RAS* 18 RAS VDDQ 3 4 29 A4 DQ7 13 23
IN
3C4 RVBUF_WE* 16 WE VDDQ 9 3 26 A3 DQ6 11 22
IN
3C4 RVBUF_CS* 19 CS VDDQ 43 2 25 A2 DQ5 10 21
IN
3 15 DQML VDDQ 49 1 24 A1 DQ4 8 20
2 39 DQMH 0 23 A0 DQ3 7 19
VSS 28 DQ2 5 18
3C4 RVBUF_DQM<3..0> VSS 41 1 21 BA1 DQ1 4 17

IN
C VSS 54 0 20 BA0 DQ0 2 16 C
3C4 RVBUF_ADR<12..0> VSSQ 6 D
IN
VSSQ 12 PACK_TYPE=TSOPII
3C4 RVBUF_BA<1..0> VSSQ 46
IN U56
VSSQ 52
3C4 BI
RVBUF_DQ<31..0> SDRAM_256MBIT V3.3
SPEED=7E
12 36 A12 DQ15 53 31 38 CLK VDD 1
11 35 A11 DQ14 51 30 37 CKE VDD 14
10 22 A10 DQ13 50 29 17 CAS VDD 27
9 34 A9 DQ12 48 28 18 RAS VDDQ 3
8 33 A8 DQ11 47 27 16 WE VDDQ 9
7 32 A7 DQ10 45 26 19 CS VDDQ 43
R258
75
6 31 A6 DQ9 44 25 1 15 DQML VDDQ 49
5 30 A5 DQ8 42 24 0 39 DQMH
4 29 A4 DQ7 13 23 VSS 28
3 26 A3 DQ6 11 22 C569 VSS 41
2 25 A2 DQ5 10 21 220P VSS 54
1 24 A1 DQ4 8 20 VSSQ 6 D
V3.3 0 23 A0 DQ3 7 19 VSSQ 12
DQ2 5 18 VSSQ 46
1 21 BA1 DQ1 4 17 D VSSQ 52
0 20 BA0 DQ0 2 16
C522 C518 C520 C524 C440 C573 C441

2.2 0.01 0.01 0.01 0.01 0.01 0.01 PACK_TYPE=TSOPII 12 36 A12 DQ15 53 15
11 35 A11 DQ14 51 14
B U46 10 22 A10 DQ13 50 13

B
SDRAM_256MBIT V3.3 9 34 A9 DQ12 48 12
SPEED=7E 8 33 A8 DQ11 47 11
D 38 CLK VDD 1 7 32 A7 DQ10 45 10
V3.3 37 CKE VDD 14 6 31 A6 DQ9 44 9
17 CAS VDD 27 5 30 A5 DQ8 42 8
18 RAS VDDQ 3 4 29 A4 DQ7 13 7
16 WE VDDQ 9 3 26 A3 DQ6 11 6
C516 C525 C442 C572 C521 C523 C519 C517 C571 19 CS VDDQ 43 2 25 A2 DQ5 10 5
R246
2.2 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 15 DQML VDDQ 49 24 A1 DQ4 8
75
1 1 4
0 39 DQMH 0 23 A0 DQ3 7 3
VSS 28 DQ2 5 2
C477 VSS 41 1 21 BA1 DQ1 4 1
220P VSS 54 0 20 BA0 DQ0 2 0
VSSQ D
D 6
V3.3 VSSQ 12 PACK_TYPE=TSOPII

VSSQ 46
D VSSQ 52
C443 C439 C435 C438 C445 C444 C446 C480

2.2 0.01 0.01 0.01 0.01 0.01 0.01 0.01 12 36 A12 DQ15 53 15
11 35 A11 DQ14 51 14
10 22 A10 DQ13 50 13
9 34 A9 DQ12 48 12
8 33 A8 DQ11 47 11
V3.3 D 7 32 A7 DQ10 45 10
A 6 31 A6 DQ9 44 9 A
5 30 A5 DQ8 42 8
4 29 A4 DQ7 13 7
C437 C515 C514 C436 C570 C481 C479 C478 3 26 A3 DQ6 11 6

ROBUF AND RVBUF MEMORY FOR VP_FPGA
FORMAT PER PR12001
2.2 0.01 0.01 0.01 0.01 0.01 0.01 0.01 2 25 A2 DQ5 10 5
1 24 A1 DQ4 8 4
0 23 A0 DQ3 7 3
DQ2 5 2
1 21 BA1 DQ1 4 1
D 0 20 BA0 DQ0 2 0
SIZE DWG NO. REV
B 5265289SCH 1
PACK_TYPE=TSOPII
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
7
REV
1
1
TV VIDEO DAC
D D
ANA_V33B
E
C73 C428 C431 C429 C347

0.01 0.1 0.01 0.1 2.2
U40
THS-8135_DAC
3A4 TV_DAC_CLK 26 40
IN CLK 3.3V
3A4 TV_DAC_BLANK* 23 44 A
IN BLANK 3.3V
3A4 TV_DAC_SYNC* 24
IN SYNC
TV_DAC_SYNCT DAC_18 10B7
3A4 IN
25
SYNC_T 1.8V
12
IN
TV_DAC_M2
C354 C353 C352
3A4 IN
48
M2
TV_DAC_M1
0.01 0.1 2.2
3A4 IN
47
M1
1
BPb9
2
BPb8 A
R217
3
BPb7
4.75K
4
BPb6
5
BPb5
C 6
BPb4 ABPb
45 C
A 7
BPb3
8
BPb2
9
BPb1
10
BPb0
22
RPr9
21
RPr8
R236
20
RPr7
4.75K
19
RPr6
18
RPr5
17 43
RPr4 ARPr
A 16
RPr3
15
RPr2
14
RPr1
13
RPr0
C427
0.1 9 27
GY9
8 28
GY8 C350 REF
7 29
GY7 220P
6 30
GY6
5 31
GY5 L8
4 32 41 TV_X_VID 14A5
GY4 AGY OUT
3 33 3.3UH
GY3
2 34
GY2 R216 C57 R104
C349
1 35
GY1 DGND
11 75 75
B 3A4 IN
TV_DAC_VID<9..0> 0 36
GY0
180P 1500P
B
49
PWR_PAD
A A
39
COMP A A
38 42
FSADJ AGND
37 46
VREF AGND
R123 SQFP
1.87K
C430 A
0.1
A
A
A
5 4 5 4
R243 6 3 6 3 C82
75 9 7 2 7 2 330P
8 8 1 8 1
7 5 4 5 4
R242 6 6 3 6 3 C83
75 5 7 2 7 2 330P
4 8 1 8 1
3 5 4 5 4
R241 2 6 3 6 3 C84
A 75 1
0
7
8
2
1
7
8
2
1
330P
A
FORMAT PER PR12001
SIZE DWG NO. REV
B 5265289SCH 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
8
REV
1
1
LEFT WORKSTATION VDAC

ANA_V33B
E
LEFT EXTERNAL VDAC
ANA_V33B
D E D
C281 C339 C282 C341 C283

2.2 0.01 0.1 0.01 0.1 C75
C424 C425 C423 C422 2.2
0.01 0.1 0.01 0.1
U41
A U31
THS-8135_DAC
THS-8135_DAC 3B4 LFT_XDAC_CLK
IN
26
CLK 3.3V
40
A
3B4 LFT_WSDAC_CLK 26 40 3B4 LFT_XDAC_BLANK* 23 44
IN CLK 3.3V IN BLANK 3.3V
3B4 LFT_WSDAC_BLANK* 23 44 3B4 LFT_XDAC_SYNC* 24
IN BLANK 3.3V IN SYNC
3B4 LFT_WSDAC_SYNC* 24 3B4 LFT_XDAC_SYNCT 25 12 DAC_18 10B7
IN SYNC IN SYNC_T 1.8V IN
3B4 LFT_WSDAC_SYNCT 25 12 DAC_18 10B7
IN SYNC_T 1.8V IN
3B4 LFT_XDAC_M2 48
IN M2 C344
3B4 LFT_WSDAC_M2 48 3B4 LFT_XDAC_M1 47 C346
IN M2 IN M1 C345
LFT_WSDAC_M1
2.2
3B4 IN
47
M1 C286 C285 C284 0.01 0.1
0.01 0.1 2.2
R206
1
4.75K
BPb9
R215 1
BPb9
2
BPb8
A
4.75K
75 2
BPb8
3
BPb7
3 A 4
BPb7 BPb6
4 5
BPb6 BPb5
R234
330P
C61
C C
5 6 45
BPb5 BPb4 ABPb
6
BPb4 ABPb
45
A 7
BPb3
A 7
BPb3
8
BPb2
8 9
BPb2 BPb1
A 9 10
BPb1 BPb0
10
R213
BPb0
22
4.75K
RPr9
22 21
4.75K
RPr9 RPr8
21 20
RPr8 RPr7
20 19
RPr7 RPr6
R235
19 18
RPr6 RPr5
18 17 43
RPr5 RPr4 ARPr
17 43 A 16
RPr4 ARPr RPr3
16 15
RPr3 RPr2
A 15 14
RPr2 RPr1
14 13
RPr1 RPr0
13 C426
RPr0
0.1 9 27
GY9
9 27 8 28
GY9 GY8
8 28
GY8
7 29
GY7 R194
0
7 29
GY7 R193 6 30
GY6
30
0 31
6 5
GY6 GY5 REF L9
5 31 4 32 41 LFT_X_VID 14D7
GY5 REF L6
GY4 AGY OUT
4 32 41 LFT_WS_VID 11B7 3 33 4.7UH
C340
GY4 AGY OUT GY3 R109 R108
3 33 4.7UH 2 34 REF REF
0.1
GY3 R87 R86 GY2 75 75
2 34
GY2 REF REF 75 1 35
GY1 DGND
11 C60 C58
75
B 3C1 LFT_WS_DV<11..0>
1
0
35
36
GY1 DGND
11 C39
220P
C37
220P
3B4 IN
LFT_XDAC_VID<9..0> 0 36
GY0
49
220P 220P
B
IN GY0 PWR_PAD
49 39 A A A A
PWR_PAD COMP
39 A A A A 38 42
COMP FSADJ AGND
38 42 37 46
FSADJ AGND VREF AGND
37 46
R110
VREF AGND
R124 SQFP
3.74K C74
C65 SQFP 3.74K
0.1
0.1 A
A
A A
A
A A A
6 3 6 3
R240 5 4 5 4
C85
75 7 2 7 2
330P
9
8 8 1 8 1
7 5 4 5 4
R239 6 6 3 6 3
C86
75 7 2 7 2
330P
5
4 8 1 8 1
3 5 4 5 4
R238 2 6 3 6 3
C87
75 7 2 7 2
330P
1
0 8 1 8 1
A A
A
FORMAT PER PR12001
SIZE DWG NO. REV
B 5265289SCH 1

8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
9
REV
1
1
D D
RIGHT WORKSTATION VDAC RIGHT EXTERNAL VDAC
ANA_V33A
A ANA_V33A
A
C312 C304
C380 C379 C382 C381 C363 C364 C362 C361
2.2 2.2
0.01 0.1 0.01 0.1 0.01 0.1 0.01 0.1
C366
0.1
U29
A U27
A
THS-8135_DAC
THS-8135_DAC 3A4 RT_XDAC_CLK 26 40
IN CLK 3.3V
3B4 RT_WSDAC_CLK 26 40 3A4 RT_XDAC_BLANK* 23 44
IN CLK 3.3V IN BLANK 3.3V
3B4 RT_WSDAC_BLANK* 23 44 3A4 RT_XDAC_SYNC* 24
IN BLANK 3.3V IN SYNC
3A4 RT_WSDAC_SYNC* 24 3A4 RT_XDAC_SYNCT 25 12 DAC_18 10B7
IN SYNC IN SYNC_T 1.8V IN
3A4 RT_WSDAC_SYNCT 25 12 DAC_18 10B7
IN SYNC_T 1.8V IN
3A4 RT_XDAC_M2 48 C307 C306 C305
IN M2
3A4 RT_WSDAC_M2 48 3A4 RT_XDAC_M1 47 0.01 2.2
IN M2 IN M1 0.1
3A4 RT_WSDAC_M1 47 C314 C316
IN M1 C315
R208
R210 0.01 0.1 2.2
C R95
4.75K
4.75K
1
BPb9 C
75
1
BPb9
2
BPb8 A
2 3
BPb8 BPb7
3 A 4
BPb7 BPb6
4 5
BPb6 BPb5
330P
A
C67
5 6 45
BPb5 BPb4 ABPb
A 6
BPb4 ABPb
45 7
BPb3
7 8
BPb3 BPb2
8 9
BPb2 BPb1
A 9 10
BPb1 BPb0
10
R225
BPb0 R221
22
4.75K 4.75K
RPr9
22 21
RPr9 RPr8
21 20
RPr8 RPr7
20 19
RPr7 RPr6
19 18
RPr6 RPr5
18
RPr5 A 17
RPr4 ARPr
43
A 17
RPr4 ARPr
43 16
RPr3
16 15
RPr3 RPr2
15 14
RPr2 RPr1
14 13
RPr1 RPr0
13
RPr0
C27 9 27
GY9
0.1 9 27 8 28
GY9 GY8
8 28
GY8
7 29
GY7 R139
0
7 29
GY7 R137 6 30
GY6
B 6 30
GY6
0 5 31
GY5 REF L4
B
5 31 4 32 41 RT_X_VID 13A8 14D7
GY5 REF L2
GY4 AGY OUT
4 32 41 RT_WS_VID 12B7 3 33 4.7UH
GY4 AGY OUT GY3 R62
3 33
GY3 4.7UH 2 34
GY2 REF REF R61
R57 R56 75
2 34
GY2 75 REF REF 1 35
GY1 DGND
11 C32 C30 75
75 RT_XDAC_VID<9..0>
1 35
GY1 DGND
11 C26 C23 3A4 IN
0 36
GY0 220P 220P
3C1 RT_WS_DV<11..0> 0 36 220P 220P 49
IN GY0 PWR_PAD
49 39 A A A A
PWR_PAD COMP
39 A A A A 38 42
COMP FSADJ AGND
38 42 37 46
FSADJ AGND VREF AGND
37 46
2
VREF AGND
2
R96 R103 SQFP
C52
3.74K C49 SQFP 3.74K
0.1 A
0.1 A
A
1
A A
A
A A
R100 8 1 8 1
75 7 2 7 2 C368
9 6 3 6 3 330P
8 5 4 5 4
R101 7 8 1 8 1
75 6 7 2 7 2 C367
5 6 3 6 3 330P
4 5 4 5 4
A R102 3 8 1 8 1
C365
A
75 2 7 2 7 2
6 3 6 3
330P
1
0 5 4 5 4
FORMAT PER PR12001
A GE HEALTHCARE - SURGERY
SIZE DWG NO. REV
B 5265289SCH 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
10
REV
1
1
TP3 5V_PCI
VCC TP2
V3.3_PCI REF
D
RED
RED 2.5V SUPPLY 1.5V SUPPLY
3.3V ANALOG SUPPLY R144 R188
D 1K 1K U52
V1.5 D
V2.5 VR3 C
U37 REF
LT1117
ANA_V33A VOUT 4 MIC29152BU
LT1117 A CB4 2.5V
2
IN OUT
4
VOUT 4 L22
1 5
3.3V C112
4.7UH 3 VIN VOUT 2 EN ADJ
C130
2.2A GND GND
3 VIN VOUT 2 0.1 0.1 3.0A R130
GND C95 C76
+
REF R184 0 SOT 3 6 100 C66 C335 C337 C472 C336
2.2 100
+
C113 C129 C114 0.01 0.01 0.01 0.01
1
C102 0.1
+
C111 C97 C98 16V
1000P 2.2 1000P 33
1
C68 33 0.1 R129
33 25V
REF
R183 0 25V
0.1 475
D D
A D D
D D
TP6 VR1
C101
MIC29152BU
A RED
33
2 4
IN OUT
+12V SUPPLY 1
EN ADJ
5
+
L21 R164 GND R162
C108 4.7UH C128 1K +12V 100
3.3V ANALOG SUPPLY 0.1 2.2A 0.1 3 6
C96
0.1
U38 C107 C109 C127 C110 D R161

ANA_V33B 2.2 1000P 2.2 1000P D 100
LT1117 E
VOUT 4
3.3V C470 C413

REF R163
C 3 VIN VOUT 2
0.01 0.01
10K C
GND A U42 D D
LM2940 C89 +5V
0.1
5V
1
1 3 0.1
C412 IN OUT
GND TAB
0.01
3.3V SUPPLY V3.3
+
2 4
C69
C80 C20
33 33 VR2
A MIC29152BU
C338 C8 2
IN OUT
4
0.01 33
A 1
EN ADJ
5
C88
+
GND R190 C77 C78 C410 C469 C411 C409
TP7 C79 100
100 1000P 0.01 0.01 0.01 0.01 0.01
100 16V
3 6
A DAC_18 7C4 8C2 8C5 9C2 9C5

RED 16V
OUT
-12V SUPPLY R185 R189
1.8V SUPPLY C103
L20
4.7UH
C126 1K D D 121
R191
121
D
V1.8 0.1 2.2A 0.1
U44
L17
LT1086 1 2
OUT2
4 C106 C104 C125 C105 -12V
3
IN OUT1 2 2.2 1000P 2.2 1000P D
GND C94 C92
R140 REF DESIGNATIONS DEVICE GND 1.5V 1.8V 2.5V 3.3V 5.0V UNUSED
113
2.2 0.1
C93 U50 EPM3256 SHOWN SHOWN
TO263HTSK C91
1000P
1
U49 29LV640 33,52 SHOWN

0.1 A D
U58 PCI9656 SHOWN SHOWN SHOWN
R141 U43
B 49.9 U48 FM93CS56 5 SHOWN B
LM2990 U45 EP1S40 SHOWN SHOWN SHOWN SHOWN
4 GND GND GND
C19
TAB 5V TP1 TP4 TP5
U32 ADM1025 SHOWN SHOWN
2 3 33
IN OUT Y1,2,3,4 OSC 2 SHOWN
D GND
A BLK BLK BLK
U55 49FCT3805 5,8,16 1,20
TO263HTSK 1
C90 C7 -5V U20 74LCX125 7 14
33 33
U25.26,33,34,46,47
+
+
SDRAM_256 SHOWN SHOWN SHOWN
3.3V DVI SUPPLY A
C513
U56,57
U27,29,31,40,41 THS_8135 SHOWN SHOWN SHOWN

0.1
U39 U24,28,30 SII_1162 SHOWN SHOWN
A U53,54 GTL2010 SHOWN SHOWN SHOWN
LT1117 D
VOUT 4 DVI_V33A U37,38,39,52 LT1117 SHOWN SHOWN SHOWN
3.3V C273 C471 B
U44 LT1086 SHOWN SHOWN
0.01 0.01
3 VIN VOUT 2
GND
SHOWN
+
C81 U6 74ACT04 SHOWN SHOWN

C70 C275
1
33
0.1 0.01
C280 REF DESIGNATIONS DEVICE GND -5.0V +5.0V -12V +12V UNUSED
0.01 U2,7,18,21 AD8185 SHOWN SHOWN SHOWN

A R114 0 U23
U1,3,4,5,8,9,10 LT1395 SHOWN SHOWN SHOWN

R112 0 U11,12,13,14
R125 0 U15,16,17
U22 ISL43141 SHOWN SHOWN
R132 0
U42 LM2940 SHOWN SHOWN
R133 0
A REF
R111 0 U43 LM2990 SHOWN SHOWN A
L18
REF R115 0
R113 0
L16
REF R131 0
FORMAT PER PR12001
REGULATION
L19
REF
L24 L29 REF A D

REF
L23 L216 L1
SIZE DWG NO. REV
A D D D B 5265289SCH 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
11
REV
1
1
5V_PCI
VCC VCC
VCC
V3.3
R147 R146
0.1 4.7K 68K
C99
D
R134 +5V +5V +5V +5V +5V +5V +5V
5
U53 -5V -5V -5V -5V -5V
100K L7 CB3
C40 C41
GTL2010 0.75A
2.2 0.1
D 24
GREF GND
1
C209 C208 C216 C212 C211
C220
C213
C215
C214
C217
C221
23 2
DREF SREF
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01 0.01 0.01 0.01 0.01
C9
SB1_VSYNC SB1_VSYNCO
4
12A7
4
3B3
1
1
13 12
IN D10 S10 OUT
D 12A7 IN
SB1_HSYNC 14
D9 S9
11 SB1_HSYNCO
SB2_HSYNCO
OUT 3B3 A D
SBC1_MSEN
15
D8 S8
10
OUT 3C3
12C7 BI SB2_VSYNCO
16
D7 S7
9
OUT 3B3
RT_WS_HPO 3B3 -
-
17
D6 S6
8
OUT A A A A J7 1
1 J2 A
10K
10K
10K
10K
18 7 RT_X_HPO 3B3
D5 S5 OUT
19 6 LFT_WS_HPO 3B3 J7 - 2
2 - J2
D4 S4 OUT
SB2_MSEN_VP DVI_V33A
R145
R257
R256
R148
20
D3 S3
5
BI 3B3
21 4 SB1_MSEN_VP 3B3 LEFT WORKSTAION DVI B J7 - 3
3 - J2
D2 S2 BI
22 3
D1 S1
R88 DVI_V33A J7 - 4
4 - J2 C43 L203
A 0.1 10K B
1000P
1000P
8
5
J7 - 5
0.1
0.1
2.2
5 - J2
L201
4.7K V3.3 R205
3.32K J7 - 6
-
L202
6 J2 R135
C42
VCC
C279
C10
C44
C210
U24 J7 - 7
4
-
1
7 J2
L200
A SII_1162
SBC2_VSYNC RT_X_HPI LFT_WS_DVI_CLK
J7 - 8
8 - J2 IN D 3D1 IN
12
IDCK+ VCC
22
A
RT_WS_HPI
13C2 11 3
IN V3.3 IDCK- VCC
12C2 R89 -
1000P
J7 9
- 3D1 LFT_WS_DVI_DE 19 40
9 J2 DE AVCC
VCC
0.1
IN
2.2
75
0.1
3D1 LFT_WS_DVI_HSYNC 20 34 C274
R136 HSYNC VCC
AVCC
8
5
IN
-
1000P
J7 10
0.1
- 3D1 LFT_WS_DVI_VSYNC 21 46 1000P
10 J2 4.7K VSYNC PVCC2
7
+5V IN
2.2
R38 R36 LFT_WS_DVI_ISEL
C277
R116 3C1 25
ISEL PVCC1
28
C276
249 IN
C278
249
C207
J7 - 11
11 - J2 C45 4.7K RST
6
A 330P
C271
44
EG/HPLG
C206
C272
V+ U16 J7 - 12
301
3D1 LFT_WS_C3
2
- R32
1
12 J2 4 24
C - IN C3/A2
A A C
2
1
1 47
LT1395 PD
A J7 - 13
R200
13 - J2 A 3D1 LFT_WS_HSYNC 3 EN 75 2
VREF
IN +
V- A
LFT_WS_DVI_SCL
J7 - 14
3D1
5
14 - J2 IN
27
SCL/D1 ESWI
30
LFT_WS_DVI_SDA
2
3D1 BI
26
SDA/D0
J7 - 15
15 - J2
-5V A 11 5
D11 MSEN
48
R47 301 C14 0.1
10 6 33
R201 R43 C62 D10 TXC+ J7 - 16
16 - J2 SBC2_MSENS 249 249 330P 7 32
1 2 1 2
9
D9 TXC-
R214 11 1 8 1 8 8 8 42 LFT_WS_DVI_DATA2P
+5V D8 TX2+ J7 - 17
17 - J2 75 10 2 7 2 7 7 9
D7 TX2-
41 R44 301 C11 0.1
9 3 6 3 6 6 10 39
D6 TX1+
6
LFT_WS_DVI_DATA2N J7 - 18
18 - J2 A U19
8 4 5 4 5 5 13
D5 TX1-
38
LFT_WS_DVI_DATAP
4 V+ R40 C63 4 14 36
- R212 7 1 8 1 8 D4 TX0+ R45 301 C12 0.1 J7 - 19
19 - J2 LT1395
1 3 15
D3 TX0-
35
75 6 2 7 2 7
3D1 LFT_WS_VSYNC 3 EN 75 2 16
D2
LFT_WS_DVI_DATA1N
IN + 5 3 6 3 6 J7 - 20
20 - J2
V- 1 17 45 LFT_WS_DVI_DATA0P
4 4 5 4 5 D1 PGND
5
330P 0 18
D0 PGND
29 R46 301 C13 0.1
J7 - 21
2
21 - J2 R211 3 1 8 1 8
AGND
43
LFT_WS_DVI_DATA0N
-5V A 75 2 2 7 2 7 1
GND AGND
37
J7 - 22
22 - J2 1 3 6 3 6 4
GND AGND
31
U18
+5V +5V 3C1 LFT_WS_DV<11..0> 0 4 5 4 5 23 49
IN GND MTGP LFT_WS_DVI_CLKP J7 - 23
23 - J2 AD8185
LFT_WS_OE* V+
6 C64
3D1 IN A A LFT_WS_DVI_CLKN
LFT_WS_SEL
14
VCC V+
13 330P A J7 - 24
24 - J2 3D1 IN 17
V+
23 21 LFT_WS_RED J7 - C1
C1 - J2
OE V+
B SEL_B
V+
24
LFT_WS_GREEN
B
22 R37 J7 - C2
C2 - J2
8 B2 16
75
5 A2 R35 LFT_WS_BLUE J7 - C3
C3 - J2
10 B1 18
75
3 A1 LFT_WS_HSYNCO J7 - C4
C4 - J2
12 B0 20
R34
LFT_WS_VSYNCO
1 A0 75 VCC J7 - C5A
C5A - J2
LFT_WS_VID
8B5 IN
0.1
2
DGND J7 - C5B
C5B - J2 IN C100
4
AGND V-
7
D
9
AGND V-
15
VCC U54 J7 - M1
M1 - J2
11 19
R149
V3.3 LFT_WS_DDC_DATA
AGND V- 100K GTL2010
LFT_WS_DDC_CLK
J7 - M2
M2 - J2 D 24
GREF GND
1
A -5V 23 2
DREF SREF
SB2_DDC_CLK SB2_VP_DDC_CLK 3B3
A 13
D10 S10
12
OUT
SB2_DDC_DATA 14 11 SB2_VP_DDC_DATA 3B3
D9 S9 OUT
SB1_DDC_CLK 15 10 SB1_VP_DDC_CLK 3B3
12A7 BI D8 S8 OUT
SB1_DDC_DATA 16 9 SB1_VP_DDC_DATA 3B3
12A7 BI D7 S7 OUT
1 8 17 8 LFT_WS_VP_DDC_DATA 3D1 A
SB2_RED D6 S6 IN
OUT 14D7 2 7 18 7 LFT_WS_VP_DDC_CLK 3D1
SB2_GREEN D5 S5 IN
OUT 14D7 3 6 19 6 RT_WS_VP_DDC_DATA 3D1
SB2_BLUE D4 S4 IN
OUT 14D7 4 5 20 5 RT_WS_VP_DDC_CLK 3D1
D3 S3 IN
REF 21 4 RT_X_VP_DDC_DATA 3D1
R138
D2 S2 IN
22 3 RT_X_VP_DDC_CLK 3D1
0
D1 S1 IN
A A
8
R39 R42 R41
4
1
1
8
5
75 75 75
R152 R151
VCC R150 V3.3
4.7K 4.7K
FORMAT PER PR12001
4.7K
2
4
1
5
2
4
1
R268 R267 RT_X_DDC_CLK
OUT 13A2 GE HEALTHCARE - SURGERY
4.7K 4.7K RT_X_DDC_DATA 13A2
OUT
RT_WS_DDC_CLK SIZE DWG NO. REV
RT_WS_DDC_DATA
OUT
OUT
12A2
12A2 B 5265289SCH 1

8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
12
REV
1
1
5V_PCI
VCC
C22
0.1
1 2
L3 CB1
C24
0.75A
2.2
D D
A
J4 - 1
1 - J3
DVI_V33A J4 - 2
2 - J3
RIGHT WORK STATION DVI B
J4 - 3
3 - J3
C374 R97 DVI_V33A J4 - 4

4 - J3 L210
10K
1000P
1000P
0.1
B
0.1
J4 - 5
2.2
0.1
-
L208
5 J3
R98
3.32K J4 - 6
-
L209
6 J3
C309
C369
C378
C310
C51
V3.3 U28 J4 - 7
7 - J3
L207
A SII_1162
RT_WS_DVI_CLK J4 - 8
8 - J3 3C1 IN
12
IDCK+ VCC
22
A
11 3
IDCK- VCC -
1000P
J4 9
- R99 3C1 RT_WS_DVI_DE 19 40
9 J3 DE AVCC
VCC
0.1
IN
0.1
2.2
8
5
75 3C1 RT_WS_DVI_HSYNC 20 34 C308
IN HSYNC VCC
AVCC -
1000P
J4 10
- 3C1 RT_WS_DVI_VSYNC 21 46 1000P
10 J3 IN VSYNC PVCC2
0.1
2.2
RT_WS_DVI_ISEL
C376
R142 3C1 IN
25
ISEL PVCC1
28
C377
C375
C373
R6 R5 J4 - 11
11 - J3 4.7K RST
249 249 C50
C370
C371
44
EG/HPLG
C C
C372
2
4
-
1
+5V 330P J4 12
301
12 - J3 3C1 RT_WS_C3 24
IN C3/A2
A
47
PD A J4 - 13
R209
13 - J3 A 2
VREF
A U1 A
4 V+ J4 - 14
14 - J3 - R1 3C1 RT_WS_DVI_SCL 27
SCL/D1 30
1 IN ESWI
LT1395 3C1 RT_WS_DVI_SDA 26
RT_WS_HSYNC EN BI SDA/D0
3C1 IN
3
+ 75 J4 - 15
15 - J3 V-
11 5
D11 MSEN
48
R60 301 C29 0.1
10 6 33
5
C46 D10 TXC+ 11C6 RT_WS_HPI J4 - 16
SBC1_MSEN OUT
16 - J3 BI 11D8 9 7
D9 TXC-
32
2
330P RT_WS_DVI_DATA2P
R224 11 1 8 1 8 8 8
D8 TX2+
42
17 - J3 -5V A 75 10 2 7 2 7 7 9 41 R59 301 C28 0.1

J4 - 17
D7 TX2-
9 3 6 3 6 6 10 39
R9 R8 D6 TX1+ RT_WS_DVI_DATA2N J4 - 18
18 - J3 249 249 8 4 5 4 5 5 13
D5 TX1-
38
RT_WS_DVI_DATA1P
+5V C47 4 14
D4 TX0+
36
R223 7 1 8 1 8 R10 301 C1 0.1 J4 - 19
19 - J3 3 15
D3 TX0-
35
75 6 2 7 2 7
16 RT_WS_DVI_DATA1N
2
D2
6
5 3 6 3 6
RT_WS_DVI_DATA0P
J4 - 20
20 - J3 A U3 4 4 5 4 5
1 17
D1 PGND
45
4 V+ 330P 0 18 29 R11 301 C2 0.1

- R7 D0 PGND J4 - 21
21 - J3 LT1395
1 R222 3 1 8 1 8
AGND
43
RT_WS_DVI_DATA0N
3C1 RT_WS_VSYNC 3 EN 75 75 2 2 7 2 7 1
GND AGND
37
IN + J4 - 22
22 - J3
V- 1 3 6 3 6 4 31
GND AGND
RT_WS_DV<11..0>
5
3C1 IN
0 4 5 4 5 23
GND MTGP
49
RT_WS_DVI_CLKP J4 - 23
2
23 - J3
+5V C48
3C1 RT_WS_OE* -5V A 330P A RT_WS_DVI_CLKN -
- IN +5V A J4 24
24 J3
3C1 RT_WS_SEL U2 A
IN
B C1 - J3 AD8185
6
RT_WS_RED J4 - C1
B
V+
14 13 RT_WS_GREEN J4 - C2
C2 - J3
VCC V+
17
V+
23 21 RT_WS_BLUE J4 - C3
C3 - J3
OE V+
24
V+ R4
SEL_B RT_WS_HSYNCO
22 J4 - C4
C4 - J3
8 B2 16
75
RT_WS_VSYNCO
5 A2 J4 - C5A
C5A - J3
10 B1 18
R3 75
3 A1 J4 - C5B
C5B - J3
RT_WS_VID B0 R2
9B4 IN
12 20
1 A0 75 J4 - M1
M1 - J3
RT_WS_DDC_DATA
11A3 BI
2 11A3 RT_WS_DDC_CLK J4 - M2
M2 - J3
DGND OUT
4 7
AGND V-
9 15
AGND V-
11 19
AGND V-
IN
A
-5V A
A
SB1_RED 13A8 14D7
OUT
SB1_GREEN 13A8 14D7
OUT
SB1_BLUE 13A8 14D7
OUT
SB1_HSYNC 11D8 +5V +5V +5V +5V +5V +5V +5V
OUT
SB1_VSYNC 11D8 -5V -5V -5V -5V -5V
A SB1_DDC_CLK
OUT
IN 11A7 A
SB1_DDC_DATA 11A7
BI
C257
C256
C248
C247
C253
C252
C255
C254
C250
C249
C251
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
C21
FORMAT PER PR12001
A A A A A GE HEALTHCARE - SURGERY
SIZE DWG NO. REV
B 5265289SCH 1

8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
13
REV
1
1
5V_PCI
VCC
+5V +5V +5V +5V +5V +5V +5V
PGB0010603
-5V -5V -5V -5V -5V L5 CB2
C34
C33 0.75A
2.2
D212
0.1
C246
C245
C237
C236
C240
C242
C244
C243
C239
C238
C241
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
D D
C4
A
A
RT_X_DVI_DATA2N J5 - 1
A A A A A RIGHT EXTERNAL DVI

RT_X_DVI_DATA2P J5 - 2
R120 DVI_V33A
B J5 - 3
10K
C72
DVI_V33A J5 - 4
R122 0.1 L212
1000P
3.32K
B
0.1
J5 - 5
2.2
L205
0.1
C433
1000P J5 - 6
L206
C302
A
C434
C432
C303
J5 - 7
U30
L204
SII_1162 J5 - 8
3B1 RT_X_DVI_CLK 12 22 A
IN IDCK+ VCC
RT_X_DVI_DATA1N
11 3
-
1000P
IDCK- VCC J5 9
V3.3
0.1
3B1 RT_X_DVI_DE
0.1
19 40
IN DE AVCC
VCC
2.2
RT_X_DVI_HSYNC
C301 RT_X_DVI_DATA1P
3B1 20 34 -
1000P
IN HSYNC VCC
AVCC J5 10
R121 1000P
0.1
3B1 RT_X_DVI_VSYNC 21 46
IN VSYNC PVCC2
2.2
C359
75
C358
C360
3B1 RT_X_DVI_ISEL
C357
IN
25
ISEL PVCC1
28 J5 - 11
RST
C355
C356
301
C -
C
44
EG/HPLG J5 12
C56
R143 RT_X_C3
C71 3B1 IN
24
C3/A2 A
330P
4.7K
47
PD
A J5 - 13
R207
2
VREF A
4
-
1
J5 14
A 3B1 RT_X_DVI_SCL 27
SCL/D1 30
IN ESWI
3B1 RT_X_DVI_SDA 26
-
BI SDA/D0 D11 D9
J5 15
11 5 48
D11 MSEN R64 301 C36 0.1 PGB0010603 PGB0010603
+5V R15 C53 10 6 33 11C6 RT_X_HPI J5 - 16
R17 D10 TXC+ OUT
249 249
330P 9 7
D9 TXC-
32
6
11 1 8 1 8 8 8 42 RT_X_DVI_DATA0N J5 - 17
D8 TX2+
A U5
R220
10 2 7 2 7 7 9 41 R63 301 C35 0.1
D10 PGB0010603
4 V+ R12 75 D7 TX2- PGB0010603 D4
- 9 3 6 3 6 6 10 39 RT_X_DVI_DATA0P J5 - 18
1 D6 TX1+
LT1395 8 4 5 4 5 5 13 38
3B1 RT_X_HSYNC 3 EN 75 D5 TX1-
IN + C54 4 14 36 J5 - 19
V- D4 TX0+
PGB0010603
7 1 8 1 8
R219 3 15 35 D5 PGB0010603
D3 TX0- PGB0010603
5
6 2 7 2 7 R21 301 C5 0.1 D6

75 2 16
D2 J5 - 20
2
5 3 6 3 6
1 17 45
D1 PGND
A
D2
4 4 5 4 5
-5V
0 18
D0 PGND
29 J5 - 21
330P D7 PGB0010603
R218 3 1 8 1 8
AGND
43 R22 301 C6 0.1
PGB0010603 D8
+5V 75 2 2 7 2 7 1
GND AGND
37
A J5 - 22
R20 R19
1 3 6 3 6 4 31
249 249 GND AGND
3B1 RT_X_DV<11..0> 0 4 5 4 5 23 49 RT_X_DVI_CLKP J5 - 23
GND MTGP
6
IN
A U8 C55
V+ R18 RX_X_DVI_CLKN -
4
- 330P A A J5 24
1 A
LT1395
EN
B 3B1 RT_X_VSYNC 75 RT_X_RED -
B
3 J5 C1
IN +
V-
A
PGB0010603
PGB0010603
A RT_X_GREEN
5
J5 - C2
2
RT_X_BLUE
D207
D211
-5V A J5 - C3
U7 RT_X_HSYNCO
+5V +5V J5 - C4
AD8185
6 RT_X_VSYNCO
V+ J5 - C5A
14 13
VCC V+
17
V+ J5 - C5B
3B1 RT_X_OE* 23 21
IN OE V+
24
V+ -
RT_X_SEL SEL_B J5 M1
3B1 IN
22 R16 RT_X_DDC_DATA
8 B2 16
75 11A3 BI
11A3 RT_X_DDC_CLK J5 - M2
12A7 SB1_RED 5 A2 OUT
IN
10 B1 18
R14 75
PGB0010603
PGB0010603
12A7 SB1_GREEN 3 A1
IN R13 75
9B1 RT_X_VID 12 B0 20
IN
12A7 SB1_BLUE 1 A0
IN
D3
D1
PGB0010603
PGB0010603
PGB0010603
2 A
DGND
4 7
AGND V-
9
AGND V-
15
A
D210
D209
D208
11 19
AGND V-
A
A -5V
A
A
FORMAT PER PR12001
SIZE DWG NO. REV
B 5265289SCH 1

8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
14
REV
1
1
+5V R58
249
6
+5V
+5V U21 U4
R107 R106 R105 V+ R203
A 4
-
75 75 75 AD8185 R69 1 RT_WS_GREEN
6 249
LT1395 IN
V+ 3 EN
14 13 +
VCC V+ +5V R25
V- 75
3C1 RT_X_BNC_OE* 17
IN V+
5
249
3C1 RT_X_BNC_SEL 23 21
OE V+
6
IN
2
R70
12A7 SB1_RED 24
IN V+ U10
SEL_B 681
D 12A7 IN
SB1_GREEN
SB1_BLUE
22
B2
4
-
V+ -5V
D
12A7 IN
8 16
LT1395
1
A2 R24
9B1 RT_X_VID 5 3.32K R71 3 EN RT_X_BNC_1
IN + J6 - 11
10 B1 18 1.69K R68 V-
A1 9.09K R67
75
5
3 J6 - 6
B0
PGB0010603
12 20
2
3C1 LFT_X_OE*
IN A0
1
-5V A
D205
3C1 LFT_X_SEL PACK_TYPE=SOIC
IN A
8B1 LFT_X_VID
IN 2 +5V
11A6 SB2_RED DGND U6
IN
1
4 7
11A6 SB2_GREEN AGND V- +5V R65
IN 9 15 74ACT04
11A6 SB2_BLUE AGND V- 249 14 7
IN VCC GND
11
AGND V-
19
A
6
3B1 RT_X_BLK 3C1 RT_WS_CVE 13 12
A Y
249
IN IN
R66
3C1 LFT_X_BLK U9 11 10
IN 4 V+ R23 A Y
3B1 TV_BLK -5V -
IN A 1 RT_X_BNC_2
J6 - 12
9
A Y
8
U22 +5V LT1395 5 6

3 EN 75 A Y
R263 + J6 - 7 3 4
ANA_33B ADG712 V- A Y
3D1 LFT_WS_CVE
PGB0010603
13 1 2
E V+ A Y
2
REF IN
5
R262 REF
IN4
0 C417 220P 0 1
D206
2
REF D4 S4
0 R231
2 3
A
3B1 RT_X_CS 1
REF L12 L10
16 IN3 -5V A
IN
D3 S3
1
4.7UH 4.7UH 15 14
9 IN2 A
REF REF +5V
REF REF R84
C415 C418 C420 R232 10 D2 S2 11
A
249
220P 220P 220P 511 8 IN1
6
7 D1 S1 6
A A A A 5 4 4 V+ U15
C ANA_V33A
GND NC -
LT1395
1
R30 LFT_X_BNC_1 J6 - 14 C
PACK_TYPE=TSSOP 3 EN 75
R192 REF
R264 -5V + J6 -
A A V- 13
PGB0010603
0 REF C416 220P
REF 0
5
+5V
D200
0 R230 REF L13 L11 R33
249
R81
3C1 LFT_X_CS
A
2
IN U23 249
6
+5V +5V
4.7UH 4.7UH -5V A
REF REF REF AD8185 U17
REF C421 6 4 V+ R202
C414 C419 R233 V+ -
220P 220P
220P
511
14
VCC V+
13
+5V R80
A LT1395
1 LFT_WS_GREEN
IN
V+
17 3 EN
249 + 75
V-
A A A A 23
OE V+
21 R31
6
R85
5
24 249
V+ U14
SEL_B 681
V+
2
22 4
ANA_33B R265 - R29 LFT_X_BNC_2
8 B2 16 1 J6 - 15
E R266 LT1395 -5V
REF A2
0 C474 220P 0 5 3.32K R83 3 EN 75
+ J6 - 10
REF B1 1.69K R82 V-
PGB0010603
10 18
REF L15 L14
3B1 TV_CS A1 9.09K R79
5
3
IN
D201
B0
2
REF R244 4.7UH 4.7UH 12 20
A
511 REF REF REF
1 A0 A
REF -5V
C473 C475 C476 R245
220P 220P 220P 511 2
DGND +5V
4 7 R72 A
AGND V- 249
A A A A 9 15
AGND V-
6
11 19
AGND V- U11
4 V+ R26
- TV_X_BNC_1
R73 J6 -
A -5V 249
LT1395
1 2
B 3
+
V-
EN
75 B
PGB0010603
J6 - 9 J6 - 1
5
+5V +5V +5V +5V +5V +5V +5V +5V +5V +5V J6 - 16
D204
2
-5V -5V -5V -5V -5V -5V J6 - 17
-5V A A
A
C287
C289
C288
C292
C290
C342
C343
C295
C297
C296
C299
C300
C298
C348
C291
C351
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
REF
A
R75 +5V R74
249
249
A R27
6
TV_X_BNC_2 J6 - 3
R76
V+ U12
4
- 75
A A A A A A J6 - 8
PGB0010603
1.37K 1
LT1395
7B3 TV_X_VID 3 EN
+
D203
IN
V-
A
5
A
2
-5V A
+5V +5V +5V +5V +5V +5V +5V +5V +5V +5V +5V
-5V -5V -5V -5V -5V -5V -5V -5V -5V
-5V
+5V
R77
C234
C235
C232
C233
C230
C228
C229
C227
C226
C224
C225
C222
C223
C294
C293
C219
C218
C313
249
C231
C311
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
6
C3
V+ U13
4
- R28
A R78
249
LT1395
1 TV_X_BNC_3
J6 - 4 A
3 EN 75
+ J6 - 5
V-
PGB0010603
A A A A A A A A A 5
A A
D202
FORMAT PER PR12001
A
-5V A
A
SIZE DWG NO. REV
B 5265289SCH 1

8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
15
REV
1
1
D V3.3 D
V3.3
LB_LAD<31..0>\I
15D2 15C2 15B5 3D7 2D4 1C6 1A3 BI
U50
EPM3256ATC144 EPM3256ATC144
SPEED=7.5_NS
3B6 CLK_10HZ\I 1 P1 P37 37 CF_ADR<11>\I 15C8 V3.3 73 VCCIO P109 109 LB_LAD<8>\I 1A3 1C6 2D4 3D7 15D5
IN OUT BI
2A4 1C6 PLX_INTI*\I 2 P2 P38 38 CF_ADR<12>\I 15C8 31 LB_LAD<31>\I 74 P74 P110 110 LB_LAD<7>\I 1A3 1C6 2D4 3D7 15D5
OUT OUT BI
3 GNDIO P39 39 CF_ADR<13>\I 15C8 75 P75 P111 111 LB_LAD<6>\I 1A3 1C6 2D4 3D7 15D5
OUT BI
4D1 TDI\I 4 IO-TDI P40 40 CF_ADR<14>\I 15C8 V3.3 76 VCCIO P112 112 LB_LAD<5>\I 1A3 1C6 2D4 3D7 15D5
15D5 IN OUT BI
15C8 CF_ADR<16>\I 5 P5 P41 41 CF_ADR<15>\I 15C8 77 GNDIO P113 113 LB_LAD<4>\I 1A3 1C6 2D4 3D7 15D5
15C5 CF_ADR<23..0>\I
OUT OUT BI
15B2 CF_OE*\I 6 P6 P42 42 30 LB_LAD<30>\I 78 P78 GNDIO 114
OUT OUT
15B7 CF_CE*\I 7 P7 P43 43 29 LB_LAD<29>\I 79 P79 VCCIO 115 V3.3
OUT
15C7 CF_ADR<0>\I VTM_INT*\I LB_LAD<28>\I LB_LAD<3>\I
0 8 P8 P44 44
IN 4D5 28 80 P80 P116 116
BI 1A3 1C6 2D4 3D7 15D5
1 CF_ADR<1>\I 9 P9 P45 45 27 LB_LAD<27>\I 81 P81 P117 117 LB_LAD<2>\I 1A3 1C6 2D4 3D7 15D5
BI
BI
BI
12 P12 P48 48 24 LB_LAD<24>\I 84 P84 P120 120 DA_PCI_IRQ\I 3D4
IN
13 GNDIO P49 49 85 GNDIO P121 121 LB_ACTIVE*\I 1B6 3A2
OUT
4 CF_ADR<4>\I 14 P14 VCCIO 50 V3.3 23 LB_LAD<23>\I 86 P86 P122 122
C 5 CF_ADR<5>\I 15 P15 VCC 51 V3.3 22 LB_LAD<22>\I 87 P87 VCC 123 V3.3 C

6 CF_ADR<6>\I 16 P16 GND 52 21 LB_LAD<21>\I 88 P88 GND 124
PLX_NCONFIG\I TCK\I CLK_CONF_66M\I
17 GNDIO P53 53
IN 2C2 4D1 3A7 IN
89 IO-TCK IN/GCLK1 125
IN 4A4
7 CF_ADR<7>\I 18 P18 P54 54 PLX_DCLK\I 20 LB_LAD<20>\I 90 P90 IN/OE1 126 DEV_OE\I
IN IN
PLX_DATAO\I CONF_LED*\I DEV_CLR\I
19 P19 P55 55
IN 3A2 1B6 OUT
91 P91 IN/GLCRn 127
IN
4D1 3A7 TMS\I 20 IO-TMS P56 56 PLX_BREQO\I 2A4 19 LB_LAD<19>\I 92 P92 IN/OE2/GCLK2 128 DA_HOLD\I 3D7
IN IN IN
15C8 CF_ADR<17>\I 21 P21 GND 57 18 LB_LAD<18>\I 93 P93 GND 129
OUT
15C8 CF_ADR<18>\I 22 P22 VCC 58 V3.3 94 GNDIO VCC 130 V3.3
OUT
CF_READY\I 23 P23 GNDIO 59 V3.3 95 VCCIO P131 131 DA_BREQI\I 3D4 1C6
IN OUT
V3.3 24 VCCIO P60 60 PLX_BREQI\I 1C6 2A4 17 LB_LAD<17>\I 96 P96 P132 132 DA_BREQO\I 3D7
OUT IN
15C8 CF_ADR<21>\I 25 P25 P61 61 PLX_LHOLDA\I 1C6 2A4 16 LB_LAD<16>\I 97 P97 P133 133 DA_HOLDA\I 1C6 3D4
OUT OUT OUT
26 GNDIO P62 62 PLX_LHOLD\I 2A4 15 LB_LAD<15>\I 98 P98 P134 134 DA_INIT_DONE\I 3B6
IN IN
CF_WE*\I 27 P27 P63 63 LB_BLAST*\I 2A4 3D7 14 LB_LAD<14>\I 99 P99 GNDIO 135
OUT IN
15C8 CF_ADR<20>\I 28 P28 GNDIO 64 13 LB_LAD<13>\I 100 P100 P136 136 DA_CONF_DONE\I 3B6
OUT IN
15C8 CF_ADR<19>\I 29 P29 P65 65 LB_ADS*\I 2A4 3D7 12 LB_LAD<12>\I 101 P101 P137 137 DA_DATAO\I 1B6 3B6
OUT IN OUT
LB_LBE<1..0>*\I
8 CF_ADR<8>\I 30 P30 P66 66 2B4 11 LB_LAD<11>\I 102 P102 P138 138 DA_DCLK\I 1B6 3B6
IN OUT
9 CF_ADR<9>\I 31 P31 P67 67 LB_LWR\I 3D7 103 P103 P139 139 DA_NCONFIG\I 1C6 3B6
IN 3D7 OUT
10 CF_ADR<10>\I 32 P32 P68 68 LB_READY*\I 1C6 TDO\I 104 IO-TDO P140 140 VP_NSTATUS\I 3B6
OUT OUT IN
11 CF_ADR<11>\I 33 GNDIO P69 69 LB_LBE<1>*\I 2A4 1 105 GNDIO P141 141 CPLD_NSTATUS\I 1C6 2C2
OUT
12 CF_ADR<12>\I 34 P34 P70 70 LB_LBE<0>*\I 0 10 LB_LAD<10>\I 106 P106 P142 142 CF_ADR<23>\I 15C8
OUT
13 CF_ADR<13>\I 35 P35 P71 71 9 LB_LAD<9>\I 107 P107 P143 143 CF_ADR<22>\I 15C8
OUT
14 CF_ADR<14>\I 36 P36 P72 72 LB_LAD<20>\I 1C6 2D4 3D7 15D5 8 LB_LAD<8>\I 108 P108 VCCIO 144 V3.3
BI
16 CF_ADR<16>\I
PACK_TYPE=TQFP 6 LB_LAD<6>\I
B 19 CF_ADR<19>\I 3 LB_LAD<3>\I B
23 CF_ADR<23>\I
V3.3
C501 C508 C567 C549 C545 C547 C497 C503

0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01
144 109 V3.3 D

NOTE-1: 1 108 NOTE-2:
USE THIS BODY THIS FIGURE
REPRESENTATION REPRESENTS C504 C498 C509 C496 C543 C550 C505 C548
ONLY AT THE LOGIC COMPONENT 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
SUB-LEVEL OF A 73 PINOUT
36
HIERARCHICAL ( TOP VIEW )
37 72
DRAWING. ( REF-ONLY ).
V3.3 D
NOTE-3: VCC PINS ARE 3.3V
NOTE-4: VCCIO PINS ARE 2.5V OR 3.3V
C510 C500
A 2.2 2.2 A
D
FORMAT PER PR12001
CONFIG CPLD
LOWER LEVEL
SIZE DWG NO. REV
B 5265289SCH 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 DWG NO.
5265289SCH
SHT
16
REV
1
1
U45
EP1S40_780
SPEED=8 EP1S40_780 EP1S40_780 EP1S40_780
SECTION 1 OF 7 SECTION 2 OF 7 SECTION 3 OF 7 SECTION 4 OF 7
IP_LS0\I A3 A3 D21 D21 LOBUF_ADR<0>\I LOBUF_DQ<9>\I H21 H21 M5 M5 RT_WS_DV<9>\I RT_X_DV<11>\I V7 V7 AA25 AA25 DGND RVBUF_DQ<26>\I AE23 AE23
IP_LD0\I A4 A4 D22 D22 LOBUF_CS*\I LOBUF_ADR<4>\I H22 H22 M6 M6 RT_WS_DV<10>\I RT_X_HSYNC\I V8 V8 AA26 AA26 DGND RVBUF_DQ<5>\I AE24 AE24
IP_LD2\I A5 A5 D23 D23 LOBUF_ADR<8>\I LVBUF_DQ<2>\I H23 H23 M7 M7 RT_WS_DV<11>\I RT_X_VSYNC\I V9 V9 AA27 AA27 RVBUF_RAS*\I RVBUF_DQ<10>\I AE25 AE25
IP_LD4\I A6 A6 D24 D24 LVBUF_DQ<20>\I LVBUF_DQ<4>\I H24 H24 M8 M8 RT_WS_HSYNC\I TV_X_CS\I V10 V10 AA28 AA28 RVBUF_ADR<8>\I RVBUF_ADR<10>\I AE27 AE27
IP_RS0\I A7 A7 D27 D27 LVBUF_CS*\I CLK_10HZ\I H25 H25 M9 M9 DGND RT_X_C3\I V11 V11 RVBUF_ADR<4>\I AE28 AE28
IP_RD0\I A8 A8 D28 D28 LVBUF_ADR<11>\I DGND H26 H26 M10 M10 RT_WSDAC_M2\I ROBUF_DQ<0>\I V18 V18 AB1 AB1 TV_DAC_CLK\I
IP_RD2\I A9 A9 LVBUF_ADR<0>\I H27 H27 M11 M11 RT_WS_C3\I LB_DP<3>\I V19 V19 AB2 AB2 TV_DAC_VID<1>\I TV_DAC_VID<8>\I AF1 AF1
D
IP_RD4\I
FPGA_TST1<0>\I
A10
A11
A10
A11
E1
E2
E1
E2
LFT_WS_DV<4>\I
LFT_WS_DV<5>\I
LVBUF_ADR<6>\I H28 H28 M12
M18
M12
M18
BOOT_DISPLAY*\I
SB2_MSEN_VP\I
LB_DP<2>\I
LB_DMPAF/EOT*\I
V20
V21
V20
V21
AB3
AB4
AB3
AB4
TV_DAC_VID<0>\I
TV_DAC_M1\I
TV_DAC_VID<9>\I
LB_LBEN<0>*\I
AF2
AF4
AF2
AF4
D
FPGA_TST1<1>\I A13 A13 E6 E6 LED_IND<3>*\I LFT_WSDAC_CLK\I J1 J1 M19 M19 SB1_VP_DDC_DATA\I LB_DREQ<1>*\I V22 V22 AB5 AB5 TV_DAC_M2\I LB_LBEN<1>*\I AF5 AF5
LOBUF_DQ<24>\I FPGA_TST1<17>\I LFT_XDAC_SYNC*\I SB1_VSYNC\I LB_HOLD\I TV_DAC_SYNCT\I LB_LAD<16>\I
A16 A16 E8 E8 J2 J2 M20 M20 V23 V23 AB6 AB6 AF6 AF6
LOBUF_DQ<0>\I FPGA_TST2<0>\I LFT_XDAC_BLANK*\I M21 SB2_VP_DDC_DATA\I LB_HOLDA\I RT_X_HPO\I LB_LAD<18>\I
A18 A18 E10 E10 J3 J3 M21 V24 V24 AB7 AB7 AF7 AF7
LOBUF_DQ<23>\I FPGA_TST2<1>\I LFT_XDAC_VID<0>\I M22 SB2_VSYNC\I RVBUF_DQ<22>\I VTM_INT*\I LB_LAD<20>\I
A19 A19 E12 E12 J4 J4 M22 V25 V25 AB8 AB8 AF8 AF8
LOBUF_DQ<15>\I A20 A20 E13 E13 FPGA_TST2<2>\I LFT_XDAC_VID<1>\I J5 J5 M23 M23 LVBUF_DQ<27>\I RVBUF_DQ<14>\I V26 V26 AB9 AB9 RT_X_SEL\I LB_LAD<22>\I AF9 AF9
LOBUF_BA<0>\I A21 A21 E15 E15 LVBUF_CLK\I LFT_XDAC_VID<2>\I J6 J6 M24 M24 LVBUF_DQ<29>\I RVBUF_DQ<15>\I V27 V27 AB10 AB10 RT_X_OE*\I LB_LAD<24>\I AF10 AF10
LOBUF_WE*\I A22 A22 E16 E16 LOBUF_DQ<30>\I LFT_XDAC_VID<3>\I J7 J7 M25 M25 RVBUF_ADR<12>\I V28 V28 AB11 AB11 RT_X_BNC_OE*\I LB_LAD<26>\I AF11 AF11
LOBUF_ADR<12>\I A23 A23 E17 E17 LOBUF_DQ<29>\I LFT_XDAC_VID<4>\I J8 J8 M26 M26 AB12 AB12 LB_DACK<0>*\I LB_LAD<28>\I AF12 AF12
LVBUF_DQ<23>\I A24 A24 E19 E19 LOBUF_DQ<19>\I RT_WS_VP_DDC_DATA\I J9 J9 M27 M27 RT_XDAC_BLANK*\I W1 W1 AB17 AB17 LB_WAIT*\I LB_LAD<15>\I AF13 AF13
LVBUF_DQ<15>\I A25 A25 E21 E21 LOBUF_ADR<1>\I RT_WS_VP_DDC_CLK\I J10 J10 RT_XDAC_SYNC*\I W2 W2 AB18 AB18 ROBUF_DQ<4>\I OSC_EN_138M\I AF15 AF15
LVBUF_WE*\I A26 A26 E23 E23 LOBUF_ADR<7>\I DEV_OE\I J11 J11 N1 N1 RT_WS_DVI_CLK\I RT_XDAC_VID<1>\I W3 W3 AB19 AB19 ROBUF_DQ<17>\I ROBUF_DQ<27>\I AF16 AF16
E27 E27 LVBUF_BA<0>\I FPGA_TST2<11>\I J12 J12 N3 N3 RT_WS_DVI_DE\I RT_XDAC_VID<3>\I W4 W4 AB20 AB20 ROBUF_DQ<12>\I ROBUF_DQ<26>\I AF17 AF17
IP_LS1\I B3 B3 E28 E28 LVBUF_ADR<9>\I FPGA_TST2<17>\I J13 J13 N4 N4 RT_WS_DVI_HSYNC\I RT_XDAC_VID<5>\I W5 W5 AB21 AB21 ROBUF_BA<1>\I ROBUF_DQ<7>\I AF18 AF18
IP_LD1\I B4 B4 DGND J16 J16 N5 N5 RT_WS_DVI_VSYNC\I RT_XDAC_VID<7>\I W6 W6 AB22 AB22 ROBUF_ADR<9>\I ROBUF_DQ<22>\I AF19 AF19
IP_LD3\I B5 B5 F1 F1 LFT_WS_DV<6>\I DGND J17 J17 N6 N6 RT_WSDAC_BLANK*\I RT_XDAC_VID<9>\I W7 W7 AB23 AB23 RVBUF_DQ<29>\I ROBUF_DQ<9>\I AF20 AF20
IP_LD5\I B6 B6 F2 F2 LFT_WS_DV<7>\I FPGA_TST2<13>\I J18 J18 N7 N7 RT_WSDAC_SYNC*\I RT_XDAC_M2\I W8 W8 AB24 AB24 RVBUF_DQ<2>\I ROBUF_ADR<1>\I AF21 AF21
IP_RS1\I B7 B7 F3 F3 LFT_WS_DV<8>\I LOBUF_DQ<16>\I J19 J19 N8 N8 RT_WS_VSYNC\I RT_X_DVI_ISEL\I W10 W10 AB25 AB25 RVBUF_DQM<2>\I ROBUF_ADR<6>\I AF22 AF22
IP_RD1\I B8 B8 F4 F4 LFT_WS_DV<9>\I LOBUF_DQM<2>\I J20 J20 N9 N9 RT_WSDAC_M1\I INIT_DONE\I W11 W11 AB26 AB26 RVBUF_DQ<11>\I RVBUF_DQ<25>\I AF23 AF23
IP_RD3\I B9 B9 F5 F5 LFT_WS_DV<10>\I LOBUF_DQM<1>\I J21 J21 N10 N10 RT_WSDAC_SYNCT\I RT_WS_OE*\I W12 W12 AB27 AB27 RVBUF_CS*\I RVBUF_DQ<6>\I AF24 AF24
IP_RD5\I B10 B10 F6 F6 LFT_WS_DV<11>\I LOBUF_DQ<8>\I J22 J22 N19 N19 DGND W14 W14 AB28 AB28 RVBUF_ADR<7>\I RVBUF_DQ<9>\I AF25 AF25
FPGA_TST1<2>\I B11 B11 F7 F7 LFT_WS_OE*\I LVBUF_DQ<24>\I J23 J23 N20 N20 LED_IND<1>*\I W15 W15 RVBUF_ADR<0>\I AF27 AF27
FPGA_TST1<3>\I B12 B12 F8 F8 LFT_X_BLK\I LVBUF_DQ<5>\I J24 J24 N21 N21 VTM_SCL\I OSC_EN_109M\I W16 W16 AC1 AC1 TV_DAC_VID<2>\I RVBUF_ADR<1>\I AF28 AF28
FPGA_TST1<4>\I B13 B13 F9 F9 FPGA_TST2<3>\I LVBUF_DQ<16>\I J25 J25 N22 N22 VTM_SDA\I ROBUF_DQ<1>\I W18 W18 AC2 AC2 TV_DAC_VID<3>\I
DGND B15 B15 F10 F10 FPGA_TST2<4>\I LVBUF_DQ<10>\I J26 J26 N23 N23 LVBUF_DQ<28>\I DGND W19 W19 AC5 AC5 TV_X_BLK\I LB_READY*\I AG3 AG3
C
LOBUF_DQ<25>\I
LOBUF_DQ<6>\I
B16
B17
B16
B17
F11
F12
F11
F12
FPGA_TST2<5>\I
FPGA_TST2<6>\I
LVBUF_ADR<1>\I
LVBUF_ADR<5>\I
J27
J28
J27
J28
N24
N25
N24
N25
LVBUF_DQ<30>\I
LVBUF_DQ<31>\I
ROBUF_DQ<15>\I
LB_DACK<1>*\I
W21
W22
W21
W22
AC6
AC7
AC6
AC7
LB_ALE\I
LB_BIGEND*\I
LB_BTERM*\I
LB_LBEN<2>*\I
AG4
AG5
AG4
AG5
C
LOBUF_DQ<1>\I B18 B18 F17 F17 LOBUF_DQ<31>\I N26 N26 LVBUF_DQM<3>\I ROBUF_RAS*\I W23 W23 AC8 AC8 LB_CCS*\I LB_LAD<1>\I AG6 AG6
LOBUF_DQ<22>\I B19 B19 F18 F18 LOBUF_DQ<4>\I LFT_XDAC_VID<5>\I K1 K1 N28 N28 ROBUF_CAS*\I W24 W24 AC9 AC9 DEV_CLR_N*\I LB_LAD<3>\I AG7 AG7
LOBUF_DQ<14>\I B20 B20 F19 F19 LOBUF_DQ<18>\I LFT_XDAC_VID<6>\I K2 K2 RVBUF_DQ<23>\I W25 W25 AC10 AC10 RT_X_BNC_SEL\I LB_LAD<5>\I AG8 AG8
LOBUF_BA<1>\I B21 B21 F20 F20 LOBUF_DQ<11>\I LFT_XDAC_VID<7>\I K3 K3 P3 P3 DGND RVBUF_DQ<13>\I W26 W26 AC11 AC11 LB_DREQ<0>*\I LB_LAD<7>\I AG9 AG9
LOBUF_CAS*\I B22 B22 F21 F21 LOBUF_ADR<2>\I LFT_XDAC_VID<8>\I K4 K4 P26 P26 IP_RCLKL\I RVBUF_WE*\I W27 W27 AC19 AC19 ROBUF_DQ<19>\I LB_LAD<9>\I AG10 AG10
LOBUF_ADR<11>\I B23 B23 F22 F22 LOBUF_ADR<6>\I LFT_XDAC_VID<9>\I K5 K5 RVBUF_ADR<11>\I W28 W28 AC20 AC20 ROBUF_DQ<18>\I LB_LAD<11>\I AG11 AG11
LVBUF_DQ<22>\I B24 B24 F23 F23 LVBUF_DQ<0>\I LFT_XDAC_M1\I K6 K6 R3 R3 DGND AC21 AC21 ROBUF_DQ<11>\I LB_LAD<13>\I AG12 AG12
LVBUF_DQ<14>\I B25 B25 F24 F24 LVBUF_DQ<19>\I LFT_XDAC_M2\I K7 K7 R26 R26 IP_LCLKL\I RT_XDAC_CLK\I Y1 Y1 AC22 AC22 ROBUF_ADR<8>\I LB_LAD<14>\I AG13 AG13
LVBUF_CAS*\I B26 B26 F25 F25 LVBUF_DQ<18>\I LFT_XDAC_SYNCT\I K8 K8 RT_XDAC_VID<0>\I Y2 Y2 AC23 AC23 RVBUF_DQ<28>\I DGND AG15 AG15
F26 F26 LVBUF_DQ<12>\I RT_WS_DVI_SCL\I K10 K10 T1 T1 RT_WSDAC_CLK\I RT_XDAC_VID<2>\I Y3 Y3 AC24 AC24 RVBUF_DQ<3>\I ROBUF_DQ<25>\I AG16 AG16
LFT_WS_DV<0>\I C1 C1 F27 F27 LVBUF_BA<1>\I RT_WS_DVI_SDA\I K11 K11 T3 T3 RT_X_DV<2>\I RT_XDAC_VID<4>\I Y4 Y4 AC27 AC27 RVBUF_BA<0>\I ROBUF_DQ<24>\I AG17 AG17
LFT_WS_DV<1>\I C2 C2 F28 F28 LVBUF_ADR<8>\I ROBUF_CLK\I K14 K14 T4 T4 RT_X_DV<3>\I RT_XDAC_VID<6>\I Y5 Y5 AC28 AC28 RVBUF_ADR<6>\I ROBUF_DQM<0>\I AG18 AG18
LFT_WS_C3\I C4 C4 DGND K15 K15 T5 T5 RT_X_DV<5>\I RT_XDAC_VID<8>\I Y6 Y6 ROBUF_DQ<23>\I AG19 AG19
LFT_WS_DVI_ISEL\I LFT_WS_DVI_CLK\I RVBUF_CLK\I
T6 RT_X_DV<7>\I RT_XDAC_M1\I TV_DAC_VID<4>\I ROBUF_DQ<8>\I
C5 C5 G1 G1 K16 K16 T6 Y7 Y7 AD1 AD1 AG20 AG20
LFT_WS_DVI_SDA\I C6 C6 G2 G2 LFT_WS_DVI_DE\I FPGA_TST2<15>\I K18 K18 T7 T7 DGND RT_XDAC_SYNCT\I Y8 Y8 AD2 AD2 TV_DAC_VID<5>\I ROBUF_ADR<2>\I AG21 AG21
LFT_WS_VP_DDC_CLK\I C7 C7 G3 G3 LFT_WS_DVI_HSYNC\I FPGA_TST2<12>\I K19 K19 T8 T8 DGND RT_X_DVI_SCL\I Y9 Y9 AD5 AD5 LB_WR\I ROBUF_ADR<5>\I AG22 AG22
FPGA_TST1<5>\I C8 C8 G4 G4 LFT_WS_DVI_VSYNC\I LVBUF_CKE\I K21 K21 T9 T9 DGND RT_X_DVI_SDA\I Y10 Y10 AD6 AD6 LB_BREQI\I RVBUF_DQ<24>\I AG23 AG23
FPGA_TST1<6>\I C9 C9 G5 G5 LFT_WS_HSYNC\I LOBUF_CKE\I K22 K22 T10 T10 RESET_DISABLE\I RT_WS_SEL\I Y11 Y11 AD8 AD8 LB_LAD<30>\I RVBUF_DQ<7>\I AG24 AG24
FPGA_TST1<7>\I C10 C10 G6 G6 DGND LVBUF_DQ<25>\I K23 K23 T19 T19 RVBUF_CKE\I LB_LSERR*\I Y13 Y13 AD10 AD10 LB_LAD<31>\I RVBUF_DQ<8>\I AG25 AG25
FPGA_TST1<8>\I C11 C11 G7 G7 LFT_WS_SEL\I LVBUF_DQ<6>\I K24 K24 T20 T20 ROBUF_CKE\I DGND Y16 Y16 AD12 AD12 XOSC_109M\I RVBUF_ADR<2>\I AG26 AG26
FPGA_TST1<9>\I C12 C12 G8 G8 LFT_X_OE*\I LVBUF_DQM<2>\I K25 K25 T21 T21 SEL_EXT_CLK\I Y17 Y17 AD13 AD13 X0SC_138M\I
FPGA_TST1<10>\I C13 C13 G9 G9 LFT_X_SEL\I LVBUF_DQ<9>\I K26 K26 T22 T22 ROBUF_DQ<2>\I Y18 Y18 AD15 AD15 LFT_WS_CVID_EN\I LB_ADS*\I AH3 AH3
LOBUF_CLK\I FPGA_TST2<7>\I LVBUF_ADR<2>\I RVBUF_DQ<19>\I LB_DTR*\I ROBUF_DQ<31>\I LB_BLAST*\I
C15 C15 G10 G10 K27 K27 T23 T23 Y19 Y19 AD16 AD16 AH4 AH4
LOBUF_DQ<26>\I C16 C16 G11 G11 FPGA_TST2<8>\I LVBUF_ADR<4>\I K28 K28 T24 T24 RVBUF_DQ<18>\I ROBUF_DQ<14>\I Y20 Y20 AD17 AD17 ROBUF_DQ<30>\I LB_LBEN<3>*\I AH5 AH5
B LOBUF_DQ<7>\I
LOBUF_DQ<2>\I
C17
C18
C17
C18
G12
G18
G12
G18
FPGA_TST2<9>\I
LOBUF_DQ<5>\I LFT_XDAC_CLK\I L1 L1
T25
T26
T25
T26
RVBUF_DQ<16>\I
RVBUF_DQ<17>\I
ROBUF_CS*\I
ROBUF_ADR<12>\I
Y21
Y22
Y21
Y22
AD18
AD19
AD18
AD19
ROBUF_DQ<5>\I
ROBUF_DQ<20>\I
LB_LAD<0>\I
LB_LAD<2>\I
AH6
AH7
AH6
AH7
B
LOBUF_DQ<21>\I C19 C19 G19 G19 DGND RT_WS_DV<0>\I L2 L2 T28 T28 RVBUF_DQ<31>\I Y23 Y23 AD21 AD21 ROBUF_ADR<10>\I LB_LAD<4>\I AH8 AH8
LOBUF_DQ<13>\I C20 C20 G21 G21 LOBUF_ADR<3>\I RT_WS_DV<1>\I L3 L3 RVBUF_DQ<0>\I Y24 Y24 AD23 AD23 RVBUF_DQ<27>\I LB_LAD<6>\I AH9 AH9
LOBUF_ADR<10>\I LOBUF_ADR<5>\I RT_WS_DV<2>\I RT_X_DV<0>\I ROBUF_WE*\I RVBUF_DQ<4>\I LB_LAD<8>\I
C21 C21 G22 G22 L4 L4 U2 U2 Y25 Y25 AD24 AD24 AH10 AH10
LOBUF_RAS*\I C22 C22 G23 G23 LVBUF_DQ<1>\I RT_WS_DV<3>\I L5 L5 U3 U3 RT_X_DV<1>\I RVBUF_DQ<12>\I Y26 Y26 AD27 AD27 RVBUF_BA<1>\I LB_LAD<10>\I AH11 AH11
LOBUF_ADR<9>\I C23 C23 G24 G24 LVBUF_DQ<3>\I RT_WS_DV<4>\I L6 L6 U4 U4 RT_X_DV<4>\I RVBUF_CAS*\I Y27 Y27 AD28 AD28 RVBUF_ADR<5>\I LB_LAD<12>\I AH13 AH13
LVBUF_DQ<21>\I LVBUF_DQ<17>\I RT_WS_DV<5>\I RT_X_DV<6>\I RVBUF_ADR<9>\I ROBUF_DQM<3>\I
C24 C24 G25 G25 L7 L7 U5 U5 Y28 Y28 AH16 AH16
LVBUF_DQ<13>\I C25 C25 G26 G26 LVBUF_DQ<11>\I LFT_X_CS\I L8 L8 U6 U6 RT_X_DV<8>\I AE1 AE1 TV_DAC_VID<6>\I ROBUF_DQM<2>\I AH19 AH19
LVBUF_RAS*\I C27 C27 G27 G27 LVBUF_ADR<10>\I DGND L9 L9 U7 U7 RT_X_CS\I TV_DAC_SYNC*\I AA1 AA1 AE2 AE2 TV_DAC_VID<7>\I ROBUF_DQM<1>\I AH20 AH20
LVBUF_ADR<12>\I C28 C28 G28 G28 LVBUF_ADR<7>\I DGND L10 L10 U8 U8 DGND TV_DAC_BLANK*\I AA2 AA2 AE4 AE4 LB_LINTO*\I ROBUF_ADR<3>\I AH21 AH21
RT_WS_DVI_ISEL\I L11 L11 U9 U9 DGND DGND AA3 AA3 AE5 AE5 DA_PCI_IRQ\I ROBUF_ADR<4>\I AH22 AH22
LFT_WS_DV<2>\I LFT_WSDAC_SYNC*\I FPGA_TST2<16>\I DGND DGND LB_LAD<17>\I RVBUF_DQM<3>\I
D1 D1 H1 H1 L13 L13 U10 U10 AA4 AA4 AE6 AE6 AH23 AH23
LFT_WS_DV<3>\I D2 D2 H2 H2 LFT_WSDAC_BLANK*\I FPGA_TST2<14>\I L17 L17 U19 U19 LB_DP<0>\I BRD_ID<0>*\I AA5 AA5 AE7 AE7 LB_LAD<19>\I RVBUF_DQM<0>\I AH24 AH24
LFT_WS_DVI_SCL\I D5 D5 H3 H3 DGND SB1_MSEN_VP\I L18 L18 U20 U20 LB_DP<1>\I BRD_ID<1>*\I AA6 AA6 AE8 AE8 LB_LAD<21>\I RVBUF_DQM<1>\I AH25 AH25
LFT_WS_HPO\I D6 D6 H4 H4 DGND SB1_VP_DDC_CLK\I L19 L19 U21 U21 LB_DEN*\I BRD_ID<2>*\I AA7 AA7 AE9 AE9 LB_LAD<23>\I RVBUF_ADR<3>\I AH26 AH26
LFT_WS_VP_DDC_DATA\I LFT_WS_VSYNC\I SB1_HSYNC\I DGND BRD_ID<3>*\I LB_LAD<25>\I
D7 D7 H5 H5 L20 L20 U22 U22 AA8 AA8 AE10 AE10
FPGA_TST1<11>\I LFT_WSDAC_M1\I SB2_VP_DDC_CLK\I U23 LED_IND<2>*\I RT_X_VP_DDC_CLK\I LB_LAD<27>\I

D8 D8 H6 H6 L21 L21 U23 AA9 AA9 AE11 AE11
FPGA_TST1<12>\I LFT_WSDAC_M2\I SB2_HSYNC\I U24 OSC_EN_102M\I RT_X_VP_DDC_DATA\I LB_LAD<29>\I

D9 D9 H7 H7 L22 L22 U24 AA10 AA10 AE12 AE12
FPGA_TST1<13>\I D10 D10 H8 H8 LFT_WSDAC_SYNCT\I LVBUF_DQ<26>\I L23 L23 U25 U25 RVBUF_DQ<21>\I RT_X_BLK\I AA11 AA11 AE13 AE13 XOSC_102M\I
FPGA_TST1<14>\I D11 D11 H9 H9 LED_IND<0>*\I LVBUF_DQ<7>\I L24 L24 U26 U26 RVBUF_DQ<20>\I DGND AA14 AA14 AE14 AE14 SEL_WS_CLK\I
FPGA_TST1<15>\I D12 D12 H10 H10 RT_WS_HPO\I LVBUF_DQM<0>\I L25 L25 U27 U27 DGND AA15 AA15 AE15 AE15 RT_WS_CVID_EN\I
FPGA_TST1<16>\I D13 D13 H11 H11 FPGA_TST2<10>\I LVBUF_DQ<8>\I L26 L26 ROBUF_DQ<3>\I AA18 AA18 AE16 AE16 ROBUF_DQ<29>\I
DGND D15 D15 H14 H14 DGND LVBUF_DQM<1>\I L27 L27 V1 V1 RT_X_DVI_CLK\I ROBUF_DQ<16>\I AA19 AA19 AE17 AE17 ROBUF_DQ<28>\I
LOBUF_DQ<28>\I D16 D16 H15 H15 DGND LVBUF_ADR<3>\I L28 L28 V2 V2 RT_X_DVI_DE\I ROBUF_DQ<13>\I AA20 AA20 AE18 AE18 ROBUF_DQ<6>\I
LOBUF_DQ<27>\I D17 D17 H17 H17 LOBUF_DQM<3>\I V3 V3 RT_X_DVI_HSYNC\I ROBUF_BA<0>\I AA21 AA21 AE19 AE19 ROBUF_DQ<21>\I
A LOBUF_DQ<3>\I
LOBUF_DQ<20>\I
D18
D19
D18
D19
H18
H19
H18
H19
LOBUF_DQM<0>\I
LOBUF_DQ<17>\I
RT_WS_DV<6>\I
RT_WS_DV<7>\I
M2
M3
M2
M3

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Document Information for 00-887907-03 Rev 1

Part Number 00-887907-03

Type Drawing Print

Description SCH, PCB, SYSTEM INTERFACE

Information not available Approved Information not available

This page is generated automatically by the GEMS ePDM System

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A 12-16-04 FC16 CHANGED PER ECO FC16 S. BROWN

6 10-22-08 DCN07164 CHANGED PER DCN G. POPE

C216 C214 C215

C474 C475 C145

00-885796-60 SPEC, PERF, VORTEX IMAGE PROCESSOR

C20 C15 C119 C115

12-225104-05 SCR,SEMS SPR,PAN,TRX,4-40,5/16,SZC

THIS DOCUMENT AND THE INFORMATION

P9 B9 PRSNT1* P9 B71 59 59 Y2 AD59 GNT5 U11 NC 27 M18 LAD27 DREQ1 A14 1

P9 A62 P9 A86 38 38 Y9 AD38 LED_ON V13 6 F19 LAD6

P9 A45 0.01 0.01 0.01 P9 A25 24 24 A3 AD24 NC V15 LA25 VRING D6

P9 A53 P9 B27 23 23 B3 AD23 NC W16 LA24 VRING D8 D

P9 A10 P9 A31 18 18 C2 AD18 REF 2.2 NC U16 LA19 VRING F4

P9 B22 P9 B56 3 3 M1 AD3 NC T20 LA4 VRING U15

P9 B28 P9 A57 2 2 M2 AD2 INTA B7 PCI_INTA* P9 A6 NC R18 LA3 VRING U17 D

P9 B67 P9 A64 T2 CBE7 STOP F3 PCI_STOP* P9 A38 P20 LBE0 VSS K9

APGP_CONF_DONE APGP_CONF_DONE 12 6 A12 DQ12 45 12

AP_INIT_DONE 10 8 A10 DQ10 40 10

AP_INIT_DONE GP_INIT_DONE 9 9 A9 DQ9 38 9

P4 24 VC_D<7> 7 AP ABSD1_CLK ABSD1_CLK

P4 13 VC_PIXCLK ABSD1_RAS ABSD1_RAS*

REF R307 DA_RS<1..0> RS<1..0> P5 34

REF REF REF REF

R210 R211 R212 R213

R13 R12 R11 R10

P1 65 (FRONT PANEL DATA PORT)

R43 100 SDRAM_256MBIT V2.5 R280 100 SDRAM_256MBIT V2.5

ATSD1_DQM<3..0> VSS 66 ATSD2_DQM<3..0> VSS 66

10 28 A10 DQ12 60 4 5 28 10 28 A10 DQ12 60 4 5 28

0 26 BA0 DQ0 2 4 5 16 0 26 BA0 DQ0 2 4 5 16

SDRAM_256MBIT V2.5 SDRAM_256MBIT V2.5

C22 C272 C331 C332 C275 C276 C273 C277 C274 20 34 20 34

10 28 A10 DQ12 60 4 5 12 10 28 A10 DQ12 60 4 5 12

0 26 BA0 DQ0 2 4 5 0 0 26 BA0 DQ0 2 4 5 0

C435 C98 C99 C126 C125 C127 C128 C124

2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01

R6 100 SDRAM_256MBIT V2.5 R288 100 SDRAM_256MBIT V2.5

10 28 A10 DQ12 60 4 5 28 10 28 A10 DQ12 60 4 5 28

0 26 BA0 DQ0 2 4 5 16 0 26 BA0 DQ0 2 4 5 16

SDRAM_256MBIT V2.5 SDRAM_256MBIT V2.5

VSSQ 64 R58 VSSQ 64

VSSQ 12 D R93 VSSQ 12 D

13 17 NC/A13 DQ15 65 1 8 15 C9 13 17 NC/A13 DQ15 65 1 8 15 C58

2.2 0.01 0.01 1000P 0.01 0.01 0.01 0.01

2.2 0.01 0.01 0.01 0.01 1000P 0.01 0.01