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ECE 410: VLSI Design Course Lecture Notes: (Uyemura Textbook)
ECE 410: VLSI Design Course Lecture Notes: (Uyemura Textbook)
• pMOS
+ pMOS
– switching behavior source
Vsg
• on = closed, when Vin < VDD - |Vtp| pMOS
-
– |Vtp| = pMOS “threshold voltage” magnitude Vin Vsg > |Vtp| = on
gate Vsg = VDD - Vin
– Vin is referenced to ground, Vin = VDD-Vsg
• off = open, when Vin > VDD - |Vtp| drain
VDD VDD +
nMOS Vgs=Vtn Passes a good low
ON when gate 0V ? VDD ?- Max high is VDD-Vtn
is ‘high’
Vy = 0 V Vy =
VDD-Vtn
0V 0V -
pMOS Vsg=|Vtp| Passes a good high
ON when gate VDD ? 0V ?+ Min low is |Vtp|
is ‘low’ Vy = VDD Vy = |Vtp|
Rule to Remember
‘source’ is at lowest potential for nMOS and at highest potential for pMOS
– pMOS
• case 1) if Vg < Vi - |Vtp|, then Vo = Vi (Vi-Vg > |Vtp|)
Vi
– here Vi is the “source” so the pMOS will pass Vi to Vo
Vg • case 2) if Vg > Vi - |Vtp|, then Vo = Vg+|Vtp| (Vi-Vg < |Vtp|)
Vo – here Vo is the “source” so the pMOS output is limited
For pMOS, min(Vo) = Vg+|Vtp|
IMPORTANT:
Rules only apply if the devices is ON (e.g., Vg > Vtn for nMOS)
ECE 410, Prof. A. Mason Lecture Notes Page 2.6
MOSFET Terminal Voltages: Examples
– nMOS rules max(Vo) = Vg-Vtn
• case 1) if Vg > Vi + Vtn, then Vo = Vi (Vg-Vi > Vtn)
• case 2) if Vg < Vi + Vtn, then Vo = Vg-Vtn (Vg-Vi < Vtn)
• nMOS examples (Vtn=0.5V) 1.5 Vo
Vo 2
– 1: Vg=5V, Vi=2V acts as
• Vg=5 > Vi +Vtn = 2.5 ⇒ Vo = 2V 5
Vg 2
Vg the source
– 2: Vg=2V, Vi=2V
• Vg=2 < Vi+Vtn = 2.5 ⇒ Vo = 1.5V 2Vi source 2Vi
– y = x • A, i.e. y = x if A = 1
AND, or multiply function
a AND b
a OR b
NOR
Remember This??
a=1 ⇒ SW1 closed, SW2 open ⇒ y=0 = a
a • b = a + b, a+b=a•b
DeMorgan relations a=0 ⇒ SW1 open, SW2 closed ⇒ y=1 = a
– y = x • A, i.e. y = x if A = 1
– parallel = OR
a OR b
• assert-low switch
– y = x • A, i.e. y = x if A = 0 =x
– series = NOR a b
0 1
=VDD Vin=VDD
1 0
c = ab
c = a+b
x
x+y 0 0 1
y 0 1 0
1 0 0
• Karnaugh map 1 1 0
x y
x y z
g(x,y) = x y z
z
• note shared gate inputs
y • is input order important?
x xyz • in series, parallel, both?
x y
z
• this schematic resembles how the
circuit will look in physical layout
a•b=a+b a+b=a•b
• assert-low OR
• bubbles = inversions
• creates NAND function
– Series-connected pMOS
– NOR-AND rule a+b=a•b
x x x y
x x
equivalent y
to y
y y x y
x+y
g(x,y) = x y = x + y
to implement pMOS this way, must push all bubbles • assert-low AND
to the inputs and remove all NAND/NOR output bubbles
• creates NOR function
ECE 410, Prof. A. Mason Lecture Notes Page 2.21
Review: CMOS NAND/NOR Gates
• NOR Schematic • NAND Schematic
x x
y
g(x,y) = x + y g(x,y) = x y
y
x x
EXAMPLE: g(x,y) = x y
F = ab ⇒ y
x
Fp = a b = a+b; OR/parallel
Fn = ab = ab; AND/series
ECE 410, Prof. A. Mason Lecture Notes Page 2.23
CMOS Combinational Logic Example
• Construct a CMOS logic gate to implement the function:
F = a • (b + c) a 14 transistors (cascaded gates)
F
b
c
• pMOS • nMOS
– Apply DeMorgan expansions – Invert output for nMOS
F = a + (b + c) Fn = a • (b + c)
6 transistors
F=a+(b•c) (CMOS) – Apply DeMorgan
– Invert inputs for pMOS none needed
Fp = a + (b • c) a b
– Resulting Schematic
– Resulting Schematic c
F=a(b+c)
F=a(b+c) a
a b
a
b c b c
c
F=a(b+c)
eX
b X
Complete CMOS
AOI/OAI circuits
• nMOS
– Group 1: c & d in parallel
– Group 2: b in series with G1
– Group 3: a parallel to G2
follow same order in pMOS
don’t compliment inputs
• pMOS
– Group 1: c & d in series
– Group 2: b parallel to G1
– Group 3: a in series with G2
• pMOS • nMOS
– Apply DeMorgan expansions – Invert output for nMOS
none needed Fn = a • (b + c)
– Invert inputs for pMOS – Apply DeMorgan
Fp = a • (b + c) Fn = a + (b+c )
– Resulting Schematic ? Fn = a + (b • c)
– Resulting Schematic ?
• nMOS a b
– Invert Output
c
• Fn = a • b • (a + c) = a • b + (a + c)
– Eliminate NANDs and NORs
F=a b (a+c)
a
• Fn = a • b + ( a • c)
– Reduce Function
• Fn = a • (b + c) b c
– Resulting Schematic ?
– Complement operations for pMOS
• Fp = a + (b • c)
• Exclusive-NOR
– a⊕b=a•b+a•b
– inverse of XOR
a
b b
a a
schematic symbol
= a b, b = 1 = a b, b = 1
a⊕b=a•b+a•b
= a, a = 1