Switch-Mode Power Converter Compensation Made Easy: Robert Sheehan

Switch-mode power
converter compensation
made easy
Robert Sheehan
Systems Manager,
Power Design Services
Member Group Technical Staff
Louis Diana
Field Application,
America Sales and Marketing
Senior Member Technical Staff
Texas Instruments
Using this paper as a quick look-up reference can help
designers compensate the most popular switch-mode
power converter topologies.
Engineers have been designing switch-mode power converters for some time now.
If you’re new to the design field or you don’t compensate converters all the time,
compensation requires some research to do correctly. This paper will break the procedure
down into a step-by-step process that you can follow to compensate a power converter.
We will explain the theory of compensation and why it is necessary, examine various power
stages, and show how to determine where to place the poles and zeros of the compensation
network to compensate a power converter. We will examine typical error amplifiers as well
as transconductance amplifiers to see how each affects the control loop and work through a
number of topologies/examples so that power engineers have a quick reference when they
need to compensate a power converter.
Introduction Many SMPS designers would appreciate a how-

A switch-mode power supply (SMPS) regulates to reference paper that they can use to look up
the output voltage against any changes in compensation solutions to various topologies with
output loading or input line voltage. An SMPS various feedback modes. We are striving to provide
accomplishes this regulation with a feedback loop, this in a single paper.
which requires compensation if it has an error
Control-loop and compensation
amplifier with linear feedback. This paper covers
definitions
the necessary definitions and theory required to
As stated previously, a SMPS’s primary function
understand how a linear feedback loop works.
is to regulate its output against input/output
We will define poles and zeros and power-stage
variations and transients, which requires a feedback
characteristics, along with various error amplifiers; Figure 1
loop. Figure 1 shows a typical SMPS with a
discuss isolated feedback and optocouplers; and
feedback loop.
give examples of how to compensate various buck,
boost and buck-boost topologies. We will cover
voltage-mode control and current-mode control
methods. Unless otherwise noted, equations
and graphs depict fixed-frequency, continuous-
conduction-mode (CCM) operation. We will define
discontinuous-conduction-mode (DCM) versus
CCM, and how each affects the feedback loop. This
paper also includes a section on the practical limits
of devices used in SMPSs.
Figure 1. A test signal injected into the feedback of the control loop
measures the frequency response.
Texas Instruments 2 September 2016

Figure 1 contains a power stage and an error
amplifier. The power stage contains all of the
magnetics and power switches, as well as a IOUT
pulse-width modulated (PWM) controller. The error
amplifier provides the feedback mechanism and
VOUT
Figure 3
compensation. A voltage divider connected to the
output provides a sample of the output voltage,
which is compared to a reference voltage by the
error amplifier. The error voltage coming out of the
error amplifier drives the PWM duty cycle higher if
Figure 2:.Poor transient response characterized by underdamped
the output voltage is low, or drives the PWM duty ringing of the output voltage when stepping the load current.
cycle lower if the output voltage is high. Thus, the
feedback scheme used here is negative feedback.
Loop gain is the gain around the feedback loop,
comprising the product of error-amplifier gain, IOUT
modulator gain and power-stage gain. The feedback
loop’s gain and phase response versus frequency
will determine how well the SMPS will function. VOUT
The bandwidth of the control loop determines
its speed in responding to a transient condition.
Compensation adjusts the loop bandwidth and
tailors the frequency response. Increasing the loop Figure 3. Good transient response exhibits no ringing with a critically
damped characteristic.
bandwidth increases the speed at which the SMPS
reacts to a transient. Therefore, maximizing the
crossover frequency will produce a quicker transient Phase and gain-margin definitions
response. Phase and gain margin are parameters used to
Phase margin, which we discuss in the next section, identify the health of a feedback loop. A control loop
also plays an important role in compensation. is unstable if the loop has unity gain when the phase
Figure 2 shows the results of low phase margin. In passes through zero. Gain margin is the gain value
this case there is ringing after the load transient and when the phase passes through 0 degrees. This
is measured in decibels and should be a negative
the loop is underdamped. This is not a desirable
number. Phase margin is the value of the phase
response.
measured in degrees when the gain passes through
In Figure 3, the phase margin has increased;
zero. This is measured in degrees and should be a
therefore, the waveform does not show any ringing
positive number (Figure 4).
after the load transient. This response is well
damped.

Control Loop – Frequency Response
20 45
60 135
0 0
Magnitude (dB)
40 90
Magnitude (dB)
Phase (°)
Phase (°)
20 Phase 45 -20 -45
margin
0 0
Gain margin -40 -90
-20 -45
-40 -90 -60 -135

0.1 1 10 100 1000 0.01 0.1 1 10 100 1000
Frequency (kHz) Frequency (kHz)
Figure 4. Phase margin is the difference in degrees when the gain Figure 5. The Bode plot of a pole shows the gain decreasing by –20
crosses zero. Gain margin is the difference in decibels when the phase dB/decade, with a phase shift at higher frequencies of –90 degrees.
crosses zero. Equation 2 defines a zero where s is in the
numerator. At the frequency of the zero the gain is
Sufficient phase margin is required to prevent
3 dB up and increasing at a +20 dB/decade slope.
oscillations. A phase margin of 45 degrees or
The phase starts to increase one decade before
greater is the design goal. A gain margin of –6 dB is
the zero frequency, is 45 degrees up at the zero
the minimum, while –10 dB is considered good.
frequency, and continues to increase another 45
Although higher crossovers are generally preferable, Figure 6 degrees for one more decade. The total change is
there are practical limitations. The rule of thumb 90 degrees over two decades (Figure 6).
is one-fifth to one-tenth the switching frequency.
s
Attenuation at the switching frequency is also 1+
ωZ (2)
important for noise immunity to minimize jitter. The H ( s) =
1
gain should ideally pass through zero with a slope
of –20 dB/decade. This will maximize gain margin
and will also negate the chance of the gain turning 60 135
positive at a higher frequency where the phase may
40 90
Magnitude (dB)
be going through zero. If that happens, you could

Phase (°)
have an unstable control loop.
20 45
Poles and zeros definitions 0 0

Equation 1 defines a pole where s is in the
-20 -45
denominator. At the frequency of the pole the gain 0.01 0.1 1 10 100 1000
is –3 dB down and rolling off at a –20 dB/decade Frequency (kHz)
slope. The phase starts to decrease one decade
Figure 6. The Bode plot of a zero shows the gain increasing by +20
before the pole frequency, is 45 degrees down at the dB/decade, with a phase shift at higher frequencies of +90 degrees.
pole frequency, and continues to decrease another
45 degrees for one more decade. The total change Figure 7 shows an inverted zero often used with a
is –90 degrees over two decades (Figure 5). low-frequency pole when using the mid-band gain
1 as the reference gain, defined by Equation 3. The
H
( s) = (1) inverted zero still has s in the numerator, but s and
s
1+
ωP ω are swapped.

re 7
ωZ As mentioned in the introduction, we will discuss

1+
H ( s) = s (3) two types of loop control methods: voltage-mode
1 control and current-mode control. The control
method determines the characteristics of the of the
60 45 power stage. For example, in a voltage-mode buck
converter the inductor-capacitor (LC) filter exhibits
40 0
Magnitude (dB)
a complex conjugate pole at the LC resonant
Phase (°)
20 -45 frequency. This means that there are two poles at
the same frequency, and the gain changes –40 dB/
0 -90 decade with an associated phase change of –180
degrees. A current-mode buck converter does not
-20 -135
0.01 0.1 1 10 100 1000 have a complex pole at the LC resonant frequency.
Frequency (kHz) Equation 5 shows the transfer function of a complex
conjugate pole with a quality factor, Q, associated
Figure 7. The Bode plot of an inverted zero shows the gain going up
and to the left of the reference gain, shown here as 0 dB. This cancels with the LC filter. Q is a measure of the sensitivity
a pole at some lower frequency so that the phase changes from –90 or quality of the tuned circuit. A higher Q value
degrees to 0 degrees.
corresponds to a narrower bandwidth of the tuned
circuit. A high Q value is not so good for a power-
A right-half-plane zero is characteristic of boost and
supply output filter, however, because as Q increases
buck-boost power stages. The magnitude increases
the phase slope increases. This means that the
at 20 dB/decade with an associated phase lag
phase changes much more quickly over a small band
of –90 degrees. As you can see in Equation 4, s
of frequencies, whereas two regular poles would
re 8 is in the numerator, but it is negative. This makes
change with a more gradual slope over two decades.
compensating the converter more difficult (Figure 8).
1
s H ( s) =
1− s s2 (5)
ωZ 1+ + 2
( s) =
H (4) QO ⋅ ωO ωO
1
Figure 9 Figure 9 illustrates how phase slope increases as
Q increases. Since a high Q LC filter can cause a
60 45
–180 degree phase shift in the loop Bode plot, it
40 0 is important to understand the Q of the LC filter in
Magnitude (dB)
order to compensate for this phase change.

Phase (°)
20 -45
20 45
0 -90
Gain
0 0
Magnitude (dB)
-20 -135 Q=2

Phase (°)
0.01 0.1 1 10 100 1000 -20 Q=1 -45

Frequency (kHz) Q = 0.5
-40 Q = 0.25 -90
Figure 8. The Bode plot of a right-half-plane zero shows the gain -60 -135
increasing by +20 dB/decade, with a phase shift at higher frequencies Phase
of –90 degrees. -80 -180
0.01 0.1 1 10 100 1000
Frequency (kHz)
Figure 9. The Bode plot of a complex conjugate pole shows the

gain decreasing by –40 dB/decade, with a phase shift at higher
frequencies of –180 degrees.

Equivalent series resistance zero converter with its associated input/output voltage
The equivalent series resistance (ESR) zero is transfer function. As you can see in Equation 7,
associated with output capacitance. Although all the output voltage is related to the input voltage
Figure 11 multiplied by the on-time duty cycle, D.
capacitors exhibit ESR, ceramic capacitors have
very low ESR – in the order of 3-5 mΩ. Electrolytic-
type capacitors have higher ESR – in the order V
OUT = VIN ⋅ D
(7)
of 10-20 mΩ for an aluminum polymer and up to
hundreds of mΩ for regular electrolytic capacitors.
The ESR in an output capacitor determines the
frequency at which the ESR zero occurs; see the
numerator in Equation 6. Figure 10 shows the
frequency response of an LC filter with an ESR
zero, which comes in at about 10 kHz. The gain
transitions from a slope of –40 dB to a slope of –20 Figure 11. A buck converter steps down the input to produce a lower
dB, and the phase turns positive for 90 degrees output voltage.
re 10 over two decades. Forward, two-switch forward, active-clamp forward

s and half-bridge converters are also buck-derived
1+
( s) = ωZ (6) topologies, but their input/output voltage transfer
H
s s2 functions are multiplied by the transformer turns
1+ + 2
QO ⋅ ωO ωO
ratio. See Equation 8. Push-pull, full bridge and
phase-shifted full bridge also have the same input/
20 45 output voltage transfer function, but with a factor
0 0 of 2 multiplier as well as the transformer turns ratio.
Magnitude (dB)
See Equation 9.
Phase (°)
-20 -45
-40 -90 N
V OUT = VIN ⋅ D ⋅ S (8)
-60 -135 NP
-80 -180
NS (9)
0.01 0.1 1 10 100 1000 VOUT = VIN ⋅ 2 ⋅ D ⋅
NP
Frequency (kHz)
Figure 10. An ESR zero after the complex conjugate pole causes the
Boost topologies
slope of the gain to reduce to –20 dB/decade, while the phase shift Boost topologies deliver energy to the output 180
moves toward –90 degrees.
degrees out of phase with the energy delivered to
Buck-derived topologies the input. This causes a right-half-plane zero to
appear in the transfer function. Figure 12 shows a
Buck-derived topologies deliver power to the output
boost power stage, along with its associated input/
after reception at the input. Buck-derived topologies
output voltage transfer function. In Equation 10, Dˊ
running in CCM with voltage-mode feedback have
is the off-time duty cycle given by Dˊ = 1 – D.
an LC filter response with one complex conjugate
pole and one ESR zero. Figure 11 shows a buck

Figure 13
gure 12
1
V OUT = VIN ⋅ (10)
D′
IN OUT
Figure 13. A single switch buck-boost converter inverts the polarity of

the input voltage. The magnitude of the output voltage can be lower or
higher than the input.
Figure 12. A boost converter steps up the input to produce a higher

output voltage. Voltage-mode buck
Operation of a voltage-mode buck modulator is
Buck-boost-derived topologies very straightforward. Along with the schematic for a
Figure 14
Inverting buck-boost, flyback, single-ended primary voltage-mode buck power stage, Figure 14 shows
inductor converter (SEPIC), Zeta and Cuk converters how comparing the feedback error voltage, VC, with a
are examples of buck-boost-derived topologies. linear ramp, VRAMP, accomplishes PWM.
These topologies have the potential to buck down
the input voltage or boost up the input voltage, much
like the more advanced buck-derived topologies
that use a transformer. The exception is the inverting
buck-boost, which inverts the polarity of the voltage
at the output. Buck-boost topologies store energy
in the inductor on the first part of the switching
period, delivering that energy to the output during
the second part of the switching period. Much like a
boost converter, this creates a right-half-plane zero,
which as we mentioned before can complicate the
compensation of the feedback loop.
Figure 14. This voltage-mode-controlled buck converter detail shows
Figure 13 shows a schematic of an inverting the control voltage intersecting the ramp modulating the PWM duty
buck-boost, while Equation 11 shows the input- cycle.
to-output voltage relationship. Equation 11 holds

true for inverting buck-boost, Zeta, Cuk and SEPIC Equations 13 and 14 calculate the duty cycle
relationship for a buck converter in CCM:
topologies. The flyback equation, Equation 12, has

the multiplier of the coupled inductor (transformer) VOUT
D = (13)
turns ratio. VIN

D VIN − VOUT
V OUT = VIN ⋅ (11) ′=
D (14)
D′ VIN
D NS
V OUT = VIN ⋅ ⋅ (12)
D′ N P

Equation 15 shows the transfer function for a more gradual slope over two decades. A high-Q
voltage-mode
buck converter: LC filter can cause a –180 degree phase shift in
s the loop Bode plot. You may be able to minimize
1+
vÔUT ωZ this phase shift by moving the error-amplifier zeros
= AVC ⋅
vˆC s s2 (15)
1+ + 2 to coincide with the LC resonant frequency. (We
QO ⋅ ωO ωO
will use this method in the voltage-mode buck
The transfer function comprises several parts. The example.) Equation 19 for Q ignores the output
first part is the PWM modulator gain. The PWM capacitor’s ESR and the inductor’s DC resistance.
output is a pulse waveform averaged by the output Both of these effects will slightly lower the Q.
filter and applied to the load as a direct current ROUT
QO =
(DC) voltage. The modulator gain is the average of L (19)
C OUT
this pulse train divided by the control voltage. The
Figure 15
control voltage is bounded by the ramp, while the We typically see voltage mode used only for buck-
output is bounded by zero and the input voltage. derived topologies, because these topologies don’t
Equation 16 defines the modulator gain for a CCM exhibit a right-half-plane zero in the power-stage
voltage-mode buck, where the input voltage is transfer function. Figure 15 shows the associated
divided by the peak-to-peak ramp voltage, VRAMP. Bode response.
The second part is a complex conjugate pole
characteristic of the LC output filter. It rolls off at 40 45
O
AVC
–40 dB/decade, with a phase change of –180 20 2  0
Magnitude (dB)
degrees. See Equation 17. This pole is followed by Z
Phase (°)
0 -45
the ESR zero of the output capacitor in Equation 18, 2 
-20 -90
reducing the slope to –20 dB/decade.
-40 -135
dv d ⎛ v ⎞ V -60 -180
A VC = OUT = ⋅ ⎜⎜ v IN ⋅ C ⎟⎟ = IN EQua16 (16)
dvC dvC ⎝ v RAMP ⎠ VRAMP 0.01 0.1 1 10 100 1000
Frequency (kHz)
1
ω O = (17) Figure 15. The voltage-mode buck frequency response has the
L ⋅ COUT characteristic complex conjugate pole with ESR zero.
1
ω Z = (18) Current-mode buck
RESR ⋅ COUT
The difference between voltage- and current-mode
The Q associated with the complex conjugate control is that for current-mode control, the PWM
pole determines the slope of the phase. See modulator uses the inductor ripple current as the
Equation 19. As we discussed in the section on ramp. Voltage-mode control uses a fixed ramp,
complex conjugate poles, Q complicates converter which contains no information about the inductor
compensation because as Q increases, the phase current. Current-mode control exhibits some
slope increases. This means that the phase changes desirable attributes because it samples the inductor
much quicker over a small band of frequencies, current. The inner current loop splits the complex
whereas two regular poles would change with a conjugate pole of the filter into two real poles, turning

the modulator into a voltage-controlled current
VOUT
source. Current-mode control also provides a cycle- D= (20)
VIN
by-cycle current limit, which is advantageous for
protecting the power stage. VIN − VOUT
′=
D (21)
VIN
Along with these advantages comes a not-so-
advantageous attribute: subharmonic oscillation. Equation 22 shows the transfer function for the
Subharmonic oscillation occurs when the inductor current-mode buck power stage:
ripple current does not return to its initial value by the
s
start of next switching cycle. For peak current-mode 1+
vÔUT ωZ
control, this occurs at a duty cycle greater than 50 vˆC ≈ AVC ⋅ ⎛ s ⎞ ⎛ s ⎞ (22)
⎜⎜1 + ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟
percent. With larger inductances, as the slope of ⎝ ωP ⎠ ⎝ ωL ⎠
the inductor current decreases and tends toward

As you can see, in Equation 22 the transfer function
becoming flat, the PWM modulator can trigger on
is made up of gain, AVC, calculated by Equation 23:
noise, making the problem worse. Subharmonic
oscillation is normally characterized by alternating ROUT
AVC ≈
wide and narrow pulses at the switch node. An Ri (23)
external ramp added to the inductor current ramp where Ri = A ⋅ RS .
cancels the subharmonic oscillation and is known as
Equations 24 and 25 express two separate poles.
slope compensation. This external ramp stabilizes
The first pole (Equation 24) is related to the output
the modulator gain.
capacitor and the output load:

Figure 16 shows the schematic of the current-mode
1
buck power stage. ω P ≈ (24)
COUT ⋅ ROUT
Figure 16
Equations 20 and 21 give the duty-cycle relationship
The second pole (Equation 25) is related to the
for the current-mode buck in CCM, which is the
inductance and VSLOPE. The modulator voltage
same as voltage mode:
gain, Km, is equal to VIN/VSLOPE at D = 0.5 and will
have little variation with operating conditions when
properly scaling VSLOPE.
K m ⋅R i
ωL =
L (25)
 VIN
where K m ≈ at D = 0.5.
VSLOPE
Figure 16. The current-mode buck power stage incorporates the The transfer function also contains an ESR zero
inductor current sense as an inner control loop. The current loop
acts as a lossless damping resistor, splitting the complex conjugate associated with the output capacitor, expressed as
pole of the output filter into two real poles. It turns the modulator into Equation
26:
a voltage-controlled current source, where the inductor current is
proportional to the control voltage at VC. 1
ω
Z = R ⋅C (26)
ESR OUT

For the peak current-mode buck, Equation 27 Current-mode boost
calculates the optimal value of slope compensation: The current-mode boost is similar to the current-
mode buck, but the current-mode boost exhibits
VOUT ⋅R i ⋅T
V SLOPE = (27) a right-half-plane zero in the transfer function. This
L
is because energy is stored in the inductor during
where R is the current-sense gain times the
i the switch on-time and delivered to the output
sense resistor, and T is equal to the switching during the off-time. This energy storage and delivery
period, 1/fSW.
Figure 18 tends to limit the overall loop bandwidth due to the
Dozens of papers tackle the subject of modeling associated phase lag of the right-half-plane zero.
current-mode control. Simple average modeling is Figure 18 shows the schematic of the current-
usually good enough for most applications. More mode boost power stage.
accurate models that look at the control behavior
up to and beyond half the switching frequency are
becoming more common. While these are simplified,
Equation 22 and the Bode plot in Figure 17 are
common for the current-mode buck power stage.

Not all data sheets have enough information to
accurately calculate the control-to-output gain.
Both the equivalent current-sense gain, Ri, and
Figure 18. In this example of a current-mode boost power stage,
slope compensation, VSLOPE, are required, but for the inductor current is sampled in the metal-oxide semiconductor
re 17 internally compensated regulators, data sheets may

not include the value of Ri, or may not list the value
field-effect transistor (MOSFET) source resistor.

of VSLOPE for switching regulators with internal power
for the current-mode boost in CCM:
switches. Only the power stage L and COUT are
available to adjust the response. V − VIN

D = OUT (28)
VOUT
40 45
P VIN
AVC D ′ = (29)
20 2  0 VOUT
Magnitude (dB)
Phase (°)
0 -45 Equation 30 shows the transfer function for the

-20 -90 current-mode boost power stage. As you can see,
Z L
-40 -135 it contains two poles, one zero, one right-half-plane
2  2 
zero and an associated gain.
-60 -180
0.01 0.1 1 10 100 1000
⎛ s ⎞ ⎛ s ⎞
Frequency (kHz)
⎜⎜1 − ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟ (30)
ˆvOUT ⎝ ω R ⎠ ⎝ ω Z ⎠
≈ AVC ⋅
Figure 17. The current-mode buck power stage exhibits a single pole vˆC ⎛ s ⎞ ⎛ s ⎞
⎜⎜1 + ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟
at ωP as the dominant characteristic ω ω
⎝ P ⎠ ⎝ L ⎠

Figure 19
Equation 31 expresses the gain as: Figure 19 shows the Bode plot of the current-mode
boost power stage.
ROUT ⋅ D′
A VC ≈ (31)
2 ⋅ Ri
40 45
P
AVC L
where Ri = A ⋅ RS and D′ = 1 − D. 20 2  0
Magnitude (dB)
2 
Phase (°)
Equation 32 calculates the first pole, which is related 0 -45
to the output capacitance and the load resistance. -20 R Z -90

The effect of boosting moves the pole out by a 2  2 
-40 -135
factor of two [9].
-60 -180
0.01 0.1 1 10 100 1000
2
ω P ≈ (32) Frequency (kHz)
COUT ⋅ ROUT
Figure 19. The current-mode boost power stage has a right-half-
Equation 33 calculates the second pole, which is plane zero at ωR in the transfer function.
related to the inductance. The modulator voltage
gain, Km, is equal to VOUT/VSLOPE at D = 0.5 and will Current-mode buck-boost
have little variation with operating conditions when Like the current-mode boost, the current-mode
properly scaling VSLOPE. buck-boost also exhibits a right-half-plane zero
in the transfer function. It has the same energy
K m ⋅R i
ωL = storage characteristic during the switch on-time,
L
with energy delivered to the output during the
(33)
V off-time. Again, this tends to limit the overall loop
where K m ≈ OUT at D = 0.5.
VSLOPE
bandwidth due to the associated phase lag of the
right-half-plane zero.
Equation 34 gives the right-half-plane zero,
which is related to the inductance and output Figure 20 shows the schematic of the current-
resistance, while Equation 35 is related to the output mode buck-boost power stage. For the buck-boost,
the convention used here is to define either VIN or
capacitance ESR: Figure 20
VOUT with its sign on the schematic. This is shown in
R ⋅ D′2
ω R = OUT (34) Figure 20 as –VOUT. All equations use the absolute

L
value of VIN and VOUT, regardless of sign.
1
ω Z = (35)
RESR ⋅ COUT
For the peak current-mode boost, Equation 36

calculates the optimal value of slope compensation:

(V − VIN )⋅Ri ⋅T
V SLOPE = OUT (36)
L 
where Ri is the current-sense gain times the sense

resistor, and T is equal to the switching period, Figure 20. This positive-to-negative current-mode buck-boost power
stage is a level-shifted version of the standard buck converter.
1/fSW.


ROUT ⋅ D′2
ω R = (43)
for the current-mode buck-boost in CCM: L⋅D

VOUT
D
= (37) 1
VIN + VOUT ω Z = (44)
RESR ⋅ COUT
VIN
′=
D (38) For the peak current-mode buck-boost,
VIN + VOUT
Equation 45 calculates the optimal value of slope
Equation 39 shows the transfer function for the compensation:

current-mode buck-boost power stage. As you can
VOUT ⋅R i ⋅T
see, it contains two poles, one zero, one right-half- V SLOPE = (45)
L
plane zero and an associated gain.
⎛
Figure 21 where Ri is the current-sense gain times the sense
s ⎞ ⎛ s ⎞
⎜⎜1 − ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟ resistor, and T is equal to the switching period,
vÔUT ω ω
≈ AVC ⋅ ⎝ R ⎠ ⎝ Z ⎠
(39) 1/fSW.
vˆC ⎛ s ⎞ ⎛ s ⎞
⎜⎜1 + ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟
⎝ ωP ⎠ ⎝ ωL ⎠ Figure 21 shows the Bode plot of the current-mode
buck-boost power stage.
Equation 40 expresses the gain as:
ROUT ⋅ D′ 40 45
AVC ≈ P
(1 + D )⋅ Ri (40) AVC L
20 2  0
Magnitude (dB)
where Ri = A ⋅ RS and D′ = 1 − D . 2 
Phase (°)
0 -45
Equation 41 calculates the first pole, which is related -20 R Z -90

to the output capacitance and the load resistance:
2  2 
-40 -135
1+ D
ω P ≈ (41) -60 -180
COUT ⋅ ROUT 0.01 0.1 1 10 100 1000
Frequency (kHz)
Equation 42 calculates the second pole, which is
related to the inductance. The modulator voltage Figure 21. Like the current-mode boost, the current-mode buck-boost
power stage also has a right-half-plane zero at ωR in the transfer
gain, Km, is equal to (VIN+VOUT)/VSLOPE at D = 0.5 and
function.
will have little variation with operating conditions
when properly scaling VSLOPE. Current-mode forward and other
K m ⋅R i
buck-derived topologies
ωL =
L The current-mode forward is similar to the current-
(42) mode buck, since energy transfers to the output
VIN + VOUT
where K m ≈ at D = 0.5. during the primary switch on-time. Adjusting the
VSLOPE
transformer turns ratio provides the nominal output
Equation 43 gives the right-half-plane zero, voltage within a practical duty-cycle range.
which is related to the inductance and output
Figure 22 shows the schematic of the current-
resistance, while Equation 44 is related to the output
mode forward power stage.
capacitance ESR:

ure 22
T1 Equation 51 calculates the second pole, which is

NP : NS D1 L
VIN VOUT related to the inductance. The modulator voltage
CIN COUT
D2 ROUT gain, Km, is equal to VIN/VSLOPE at D = 0.5 and will
RESR
PWM have little variation with operating conditions when
Logic Q1
properly scaling VSLOPE.
VSLOPE
A
+ 2
- 
RS K m ⋅R i ⎛N ⎞
+ VC ωL = ⋅ ⎜⎜ S ⎟⎟
L ⎝ NP ⎠ (51)
Figure 22. A single-switch current-mode forward power stage has a
buck-type output at the secondary. The inductor current is reflected VIN
into the primary and sampled in series with the switch. VSLOPE
Equation 52 gives the zero, which is related to the

output capacitance ESR:
for the current-mode forward in CCM:
1
VOUT N P ω Z = (52)
D = ⋅ (46) RESR ⋅ COUT
VIN N S
NP For the peak current-mode forward, Equation 53

VIN − VOUT ⋅
′= NS (47) calculates
the optimal value of slope compensation:
D
VIN
VOUT ⋅R i ⋅T N S
V SLOPE = ⋅ (53)
Equation 48 shows the transfer function for the L NP
current-mode forward power stage. As you can
where Ri is the current-sense gain times the
see, it contains two poles, one zero and an

Figure 23 sense resistor, and T is equal to the switching
associated gain.
period, 1/fSW.
s
1+
vÔUT ωZ Figure 23 shows the Bode plot of the current-mode
≈ AVC ⋅
ˆ
vC ⎛ s ⎞ ⎛ s ⎞ (48) forward power stage.
⎜⎜1 + ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟
⎝ ω P ⎠ ⎝ ω L ⎠
Equation 49 expresses the gain as: 40 45

P
AVC
R N 20 2  0
Magnitude (dB)
AVC ≈ OUT ⋅ P
Ri N S (49)
Phase (°)
0 -45

where Ri = A ⋅ RS . -20 -90

Z L
-40 -135
2  2 
Equation 50 calculates the first pole, which is related
-60 -180
to the output capacitance and the load resistance: 0.01 0.1 1 10 100 1000
Frequency (kHz)
1
ω P ≈ (50)
COUT ⋅ ROUT Figure 23. The current-mode forward power-stage frequency
response is similar to that of the buck.

Current-mode flyback Equation 57 expresses the gain as:
The current-mode flyback has a right-half-plane zero R ⋅ D′ N P
AVC ≈ OUT ⋅
in the transfer function. The magnetizing inductance
(1 + D )⋅ Ri N S (57)
stores energy during the switch on-time, with
energy delivered to the output during the off-time. where Ri = A ⋅ RS and D′ = 1 − D .
This tends to limit the overall loop bandwidth due Equation 58 calculates the first pole, which is related
ure 24 to the associated phase lag of the right-half-plane
to the output capacitance and the load resistance:
zero.
Figure 24 shows the schematic of the current- 1+ D
(58)
ωP ≈
COUT ⋅ ROUT
mode flyback power stage.

T1 Equation 59 calculates the second pole, which is
NP : NS D1
VIN VOUT related to the inductance. The modulator voltage
CIN LP COUT
ROUT gain, Km, is equal to (VIN+VOUT·NP/NS)/VSLOPE at D
RESR
PWM = 0.5 and will have little variation with operating
Logic Q1
VSLOPE conditions when properly scaling VSLOPE.
A
+
RS
-  K m ⋅R i
+ VC ωL =
LP
(59)
Figure 24. For the current-mode flyback power stage, the isolation
transformer also serves as the energy-storage inductor. NP
VIN + VOUT ⋅
NS
VSLOPE
for the current-mode flyback in CCM: Equation 60 gives the right-half-plane zero,
which is related to the inductance and output
VOUT
D= resistance, while Equation 61 is related to the output
N
V ⋅ S +V (54)
IN OUT
NP capacitance ESR:

2
VIN R ⋅ D′2 ⎛ N P ⎞
′=
D (55) ω R = OUT ⋅⎜ ⎟ (60)
NP LP ⋅ D ⎜⎝ N S ⎟⎠
VIN + VOUT ⋅
NS
1
Equation 56 shows the transfer function for the ω Z = (61)
RESR ⋅ COUT
current-mode flyback power stage. As you can see,
it contains two poles, one zero, one right-half-plane
For the peak current-mode flyback, Equation 62
zero and an associated gain. calculates the optimal value of slope compensation:
⎛ s ⎞ ⎛ s ⎞
⎜⎜1 − ⎟⎟ ⋅ ⎜⎜1 + ⎟ VOUT ⋅R i ⋅T N P
vˆ ω R ⎠ ⎝ ω Z ⎟⎠ V
SLOPE = ⋅ (62)
OUT ≈ AVC ⋅ ⎝ (56) LP NS
vˆC ⎛ s ⎞ ⎛ s ⎞
⎜⎜1 + ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟
⎝ ωP ⎠ ⎝ ωL ⎠

where Ri is the current-sense gain times the Equation 63 is written by summing the currents at
re 25 sense resistor, and T is equal to the switching the error-amplifier inputs:
period, 1/fSW.
′
v ÔUT vˆ ⎛ 1 1 ⎞
+ C = vˆFB ⋅ ⎜⎜ + ⎟⎟ (63)
Figure 25 shows the Bode plot of the current-mode RFBT Z COMP ⎝ RFBT Z COMP ⎠
flyback power stage.
Equation 64 relates the feedback voltage to the
control voltage by the open loop gain of the

40 45
P amplifier:
AVC L
20 2  0
Magnitude (dB)
2  − vˆC
Phase (°)
0 -45 v ˆFB = (64)
AOL
-20 R Z -90
2  2 
-40 -135 Equation 65 combines Equations 63 and 64:
-60 -180 ⎛ ⎞
0.01 0.1 1 10 100 1000 ⎜ ⎟
Frequency (kHz) vˆC Z COMP ⎜ 1 ⎟
vˆ′ = − R ⋅⎜
⎛ ⎞⎟
(65)
OUT FBT ⎜ 1 + 1 ⋅ ⎜1 + Z COMP ⎟ ⎟
Figure 25. The current-mode flyback power-stage frequency ⎜
⎝ AOL ⎜⎝ RFBT ⎟⎠ ⎟⎠
response is similar to that of the buck-boost.
Equation 66 shows that if the gain of the error
Type I error amplifier
amplifier is large enough
Figure 26 shows a Type I error amplifier
configuration, which is the simplest form of ⎛ RFBT ⎞
A OL ⋅ ⎜⎜ ⎟⎟ >> 1 (66)
R
⎝ FBT + Z COMP ⎠
compensation; it is characterized by a single pole.
You can analyze this circuit by recognizing that the
Then the closed-loop gain can be expressed by
error amplifier is inverting and has a virtual short
Equation 67 as:
between VFB and VREF. The feedback impedance
gure 26 divided by the input impedance gives you the small vˆ Z
C ≈ − COMP = −
1 ω
= − EA (67)
signal gain. Since VREF can be viewed as an AC ′
vÔUT RFBT s ⋅ CCOMP ⋅ RFBT s
ground, you can ignore the value of RFBB, as it does

not affect the AC transfer function. Equation 68 defines the error amplifier pole
frequency:
1
ω
EA = (68)
RFBT ⋅ CCOMP

Examining the result reveals a single pole at the
origin. In practice, this is limited at DC by the
open-loop gain of the amplifier and is called
Figure 26. Type I error amplifier compensation has a single capacitor dominant-pole compensation.
in the feedback. Figure 27 shows the straight-line approximation of

the frequency response for an error amplifier with
Type I compensation. Type I compensation is often

Power Supply Design Seminar 2016/17
used for a constant-current type of current-mode where AVM is defined as the mid-band voltage gain.
buck, driving a light-emitting diode (LED) load with Examining the result reveals that in Equation 70 the
re 27 no output capacitor. While you can use this type of

dominant-pole compensation for any power
mid-band voltage gain is:
RCOMP
supply, for many systems this type of A
VM ≈ (70)
RFBT
compensation does not offer the flexibility
necessary to achieve optimal performance. Equation 71 reveals a zero at:
1
60 135 ω ZEA = (71)
RCOMP ⋅ CCOMP
40 90
Magnitude (dB)
While Equation 72 reveals a high-frequency pole at:

Phase (°)
20 45
0 0
1
 EA ω HF ≈
-20 -45 RCOMP ⋅ C HF
2  (72)
-40 -90
0.01 0.1 1 10 100 1000
assuming CCOMP >> CHF .
Frequency (kHz)
In practice, the open-loop gain of the amplifier
Figure 27. A Type I error-amplifier frequency response is will limit the error-amplifier gain at DC. Type II
characterized by a single pole.
gure 28 compensation is generally well suited for use with
Type II error amplifier current-mode control. In selective cases, you can
Figure 28 shows the schematic of a Type II error use it for voltage-mode control with a high value of
amplifier.
Figure 29 ESR in the output capacitor.
Figure 29 shows the straight-line approximation of

the frequency response for an error amplifier with
Type II compensation.
80 180
60 135
Magnitude (dB)
Phase (°)
40 90
Figure 28. Type II error-amplifier compensation adds a resistor and
high-frequency capacitor to the feedback. 20 AVM 45
 ZEA  HF
0 2  2  0
Using the same derivation process as for Type I -20 -45

compensation, Equation 69 expresses the 0.01 0.1 1 10 100 1000
Frequency (kHz)
voltage-gain transfer function as:
s Figure 29. A Type II compensator frequency response has a mid-band
ωZEA 1+
1+ gain between the zero and pole.
vˆC s AVM ⋅ ωZEA ωZEA
≈ − AVM ⋅ ≈− ⋅
v ÔUT
′
1+
s s 1+
s (69)
ωHF ωHF

Type II transconductance amplifier The difference is in the mid-band voltage gain, given
by Equation 74:
The difference between a conventional error
AVM = K FB ⋅ g m ⋅ RCOMP
amplifier and a transconductance amplifier is
(74)
that with a transconductance amplifier, the input RFBB
where K FB = .
resistor divider network and the transconductance RFBB + RFBT
(gm) parameter are now a part of the gain transfer
function. Recalling the section on Type I error As you can see from Equation 73, a Type II error
amplifiers, the bottom resistor of the input divider amplifier has a pole at the origin, a zero and a
dropped out of the transfer function due to the second high-frequency pole. Equations 75 and 76
virtual ground effect. Both pins were at the same are identical to Equations 71 and 72:
potential and the AC contribution of the lower 1

ω ZEA = (75)
resistor was nonexistent. In a transconductance RCOMP ⋅ CCOMP
amplifier, there is no local feedback; therefore there
is no virtual ground. You can no longer ignore the 1
ω HF ≈
bottom resistor of the input divider, and gm can RCOMP ⋅ C HF
vary depending on the integrated circuit design. A (76)
assuming CCOMP >> C HF and REA >> RCOMP .
transconductance amplifier is also well suited for
Figure 30 Type II compensation.
The transconductance and output resistance of the
Figure 30 shows the schematic of a Type II amplifier set the open-loop gain, which will limit the
transconductance error amplifier. error-amplifier gain at DC. Equation 77 expresses
the open-loop gain as:
A OL = g m ⋅ REA (77)
You can use the transconductance amplifier for

current-mode control. We do not recommend its
use for Type III operation with voltage-mode control
Figure 30. Type II transconductance amplifier compensation because of the feedback divider limitation on phase
components are referenced to ground at the output. boost for low-voltage outputs.
Figure 31 shows the straight-line approximation
The voltage-gain transfer function for a Type II
of the frequency response for a transconductance
transconductance amplifier is the same as for
error amplifier with Type II compensation.
a regular error amplifier, as you would expect.
Equation 73 is identical to Equation 69:
ω s
1 + ZEA 1+
vˆC A ⋅ ω
s ≈ − VM ZEA ⋅ ω
≈ − AVM ⋅ ZEA (73)
′
vÔUT s s s
1+ 1+
ωHF ωHF

The mid-band gain is the same as it is for a Type II
80 180
error amplifier. Equation 79 is identical to Equation 70:
60 135
Magnitude (dB)
RCOMP
A
VM ≈ (79)
Phase (°)
40 90 RFBT
20 AVM 45
 ZEA  HF Examining the Type III transfer function reveals
0 2  2  0
two zeros: one zero set by RCOMP and CCOMP (Equation
-20 -45
0.01 0.1 1 10 100 1000
80) and another zero set by RFBT and CFF (see
Frequency (kHz) Equation 81) to help offset the complex conjugate
poles:
Figure 31. A transconductance error amplifier with Type II
compensation has a frequency response equivalent to a standard 1
operational amplifier. ω ZEA = (80)
RCOMP ⋅ CCOMP
Type III error amplifier

1
ω
FZ ≈ (81)
Type III compensation is generally the most useful RFBT ⋅ C FF
Figure 32 technique for compensating voltage-mode-control
converters, but it requires two additional components RFF and CFF along with RCOMP and CHF determine the
not present in Type II compensation, shown in poles in the system, usually occurring after the output
Figure 32. filter’s complex conjugate pole. The examples will
reveal more on the exact placement of these poles
and zeros. See Equations 82 and 83:
1
ω FP = (82)
RFF ⋅ C FF
1
ω
HF ≈ (83)
Figure 32. Type III error-amplifier compensation adds a lead network RCOMP ⋅ C HF
across the top divider resistor.
This compensation network provides a pole at assuming CCOMP >> C HF and RFBT >> RFF .
the origin, two zeros and two higher-frequency Type III compensation is useful in power supplies
poles in the feedback path. The two zeros offset where the output capacitor ESR is very low, such as
the complex conjugate pole of the voltage-mode in converters with ceramic output capacitors.
buck. Type III compensation can increase both
The reason for this is that low-ESR capacitors push
the bandwidth and phase margin of a closed-loop
the ESR zero higher in frequency than high-ESR
system.
capacitors. Thus, your converter will not benefit
Equation 78 expresses the voltage-gain transfer from the phase boost at lower frequencies, but Type
function for Type III compensation as: III compensation can make up for that.
⎛ ωZEA ⎞ ⎛ s ⎞ ⎛ s ⎞ ⎛ s ⎞
⎜1 + ⎟ ⋅ ⎜1 + ⎟ ⎜⎜1 + ⎟ ⋅ ⎜1 + ⎟
vˆC ⎝ s ⎠ ⎜⎝ ω FZ ⎟⎠ A ⋅ω ⎝ ωZEA ⎟⎠ ⎜⎝ ω FZ ⎟⎠
= − AVM ⋅ = − VM ZEA ⋅
′
vÔUT ⎛ s ⎞ ⎛ s ⎞ s ⎛ s ⎞ ⎛ s ⎞
⎜⎜1 + ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟ ⎜⎜1 + ⎟⎟ ⋅ ⎜⎜1 + ⎟⎟
⎝ ω FP ⎠ ⎝ ω HF ⎠ ⎝ ω FP ⎠ ⎝ ω HF ⎠
(78)

re 33
Figure 33 shows the straight-line approximation of Adding RBIAS maintains a minimum current through
the frequency response for an error amplifier with the TL431 for regulation. It is not part of the
Type III compensation. frequency compensation network. Equation 84
expresses the voltage-gain transfer function as:
80 270 ωZEA s
1+ 1+
60 225 vˆC s AVM ⋅ ωZEA ωZEA
≈ − AVM ⋅ ≈− ⋅
vˆ OUT
′ s s s (84)
Magnitude (dB)
40 180 1+ 1+
ωHF ωHF
Phase (°)
20 135
AVM  FP  HF
0 90 In Equation 85 the mid-band voltage gain is:

 ZEA  FZ 2  2 
-20 45
2  2  RP
-40 0 VM = CTR ⋅
A (85)
0.01 0.1 1 10 100 1000 RD
Frequency (kHz)
Equation
86 defines the current transfer ratio:
Figure 33. A Type III compensator frequency response boosts the gain
and phase in the mid band. IC
CTR = (86)
IF
Isolated feedback with optocoupler
Figure 34 shows Type II compensation using an As you can see from Equation 84, this isolated
optocoupler and the TL431 shunt regulator. The feedback with an optocoupler is configured as a
current-transfer ratio and resistors set the mid-band Type II error amplifier, which has a pole at the origin,
gain through the optocoupler. Bias currents and the a zero and a second high-frequency pole. See
diode forward voltage can limit the dynamic range. Equations
87 and 88:
The reference voltage for a standard TL431 is 2.5
1
V, which can work for 5-V outputs and higher. For ω ZEA = (87)
RFBT ⋅ CCOMP
lower output voltages, the TLV431 has a 1.24-V
Figure 35

reference. 1
ω
HF = (88)
In Figure 34, CP includes the parasitic capacitance RP ⋅ C P
of the optocoupler’s output transistor. Parasitic
capacitance is often the limiting factor of the Figure 35 shows the frequency-response plot.
Figure 34 bandwidth in this configuration. The associated
phase shift can go to –180 degrees, making 80 180
compensation at higher frequencies challenging.
60 135
Magnitude (dB)
Phase (°)
40 90
20 AVM 45
 ZEA  HF
0 0
2  2 
-20 -45
0.01 0.1 1 10 100 1000
Frequency (kHz)
Figure 35. The frequency response of this optocoupler feedback has

Figure 34. This isolated feedback with an optocoupler uses a shunt a Type II characteristic.
regulator for secondary-side voltage control.

Voltage-mode buck example Once you have selected AVM and calculated
Figure 36 is the complete voltage-mode buck the pole/zero location, you can solve for the
Figure 36
regulator model, showing the modulator, output filter compensation component values using the
and error amplifier. For Type III compensation, use a equations below. We recommend that you verify the
standard voltage-type operational amplifier. system crossover frequency and phase margin on
the bench to confirm your desired performance.
Use the following simplified design method for the

voltage-mode buck:
• Choose a value for RFBT based on the bias current and
power dissipation.
• Pick a target bandwidth; typically, fSW/10: ωC = 2∙π∙fC.
• Find AVM to achieve the target bandwidth.
• Set ωZEA and ωFZ equal to the output-filter complex
conjugate pole ωO: ωZEA = ωFZ = ωO.
Figure 36. The complete voltage-mode buck converter with power
stage and error amplifier. The fixed ramp shown could be proportional, • Set ωFP equal to the output-filter zero, ωZ: ωFP = ωZ.
depending upon the controller. • Set ωHF equal to half the switching frequency: ωHF =
2∙π∙fSW/2.
Voltage-mode buck compensation
strategy Solve Equations 89 through 93 to find the
We will now outline the compensation guidelines for

component values:
a voltage-mode buck with Type III compensation.

ωC
This is an approximate method. Choose a large A VM = (89)
AVC ⋅ ωO
value for RFBT; typical values for RFBT are between
2 kΩ and 200 kΩ. AVM, the mid-band voltage gain, R COMP = AVM ⋅ RFBT (90)
is one of the design parameters; by changing this
parameter, you can change the performance of the 1

C
FF = (91)
system. The value of AVM that gives you the desired ω FZ ⋅ RFBT

performance will vary with modulator gain.
1
For voltage-mode control, set the system bandwidth C COMP = (92)
ωZEA ⋅ RCOMP
typically at 10 percent of the switching frequency.
The two zeros, ωZEA and ωFZ, should cancel the 1

C HF = (93)
output filter’s complex conjugate pole. Set the ωHF ⋅ RCOMP
pole frequency, ωFP, to cancel the output-filter zero
caused by the output capacitor ESR. Set the high-
frequency pole, ωHF, equal to half the switching
frequency. For higher bandwidth, set ωHF equal to
the switching frequency.

s
1 Voltage-mode buck compensation
vÔUT Z
 AVC  results
vˆC s s2
1  2
QO  O O Figure 37 shows the voltage-mode buck idealized
straight-line plots of the power stage, error amplifier
40 45
AVC O and control loop. The overall control loop is the
Magnitude (dB)
20 2  0
product of the power-stage and error-amplifier
Phase (°)
0 -45
Z transfer functions. On the Bode plots, the overall
-20 -90
2  loop gain is the sum in decibels of the power-stage
-40 -135
gain and error-amplifier gain. Adjust the mid-band
-60 -180
0.01 0.1 1 10 100 1000 gain of the error amplifier to meet the target
Frequency (kHz) loop bandwidth.
Power stage (a)
Current-mode buck example
  ZEA   s  Figure 38 is the complete current-mode buck
1    1   Figure 38
vˆC  s    FZ  regulator model, showing the modulator, output filter
  AVM 

ˆvOUT  s   s  and error amplifier. For Type II compensation, this
1    1  
  FP    HF  example uses a transconductance amplifier.
60 270
40  HF 225
Magnitude (dB)
2 
Phase (°)
20 180
 FP
0 135
2 
AVM
-20  ZEA  FZ 90 
&
2  2 
-40 45
0.01 0.1 1 10 100 1000
Frequency (kHz)
Error amplifier (b)

Figure 38. This current-mode buck shows idealized current sensing in
series with the inductor.
vÔUT vÔUT vˆC
 

vÔUT 
vˆC vÔUT Current-mode buck compensation
60 135 strategy
40 90 We will now outline the compensation guidelines for
Magnitude (dB)
a current-mode buck with Type II compensation.

Phase (°)
20 45
0 0 At frequencies after the output-filter pole, the

C
-20 2  -45 modulator transconductance and output-filter
-40 -90
capacitor set the power-stage gain.
0.01 0.1 1 10 100 1000
Frequency (kHz) You can adjust the mid-band voltage gain, AVM,
to achieve the target loop bandwidth, typically
Control loop (c)
one-tenth the switching frequency.
Figure 37. The power-stage (a) and error-amplifier (b) plots sum to
produce the control-loop plot (c) for the voltage-mode buck frequency To give the maximum amount of phase boost, place
response. the error-amplifier zero, ωZEA, a decade below the
target crossover frequency. An alternate strategy

is to place the error-amplifier zero at the load pole Current-mode buck compensation
of ωO, which will give you an equivalent result. The results
high-frequency pole, ωHF, should cancel the ESR Figure 39 shows the current-mode buck idealized
zero of the output capacitor. For capacitors with straight-line plots of the power stage, error amplifier
very low ESR, set the pole to 10 times the crossover and control loop.
frequency. If the error amplifier has a relatively low s
1
unity-gain bandwidth, CHF may not be required. vÔUT
 AVC 
Z
vˆC  s   s 
1    1  
For an ideal current-mode buck, the upper limit for  P   L 
the loop bandwidth is fSW/5. For nonideal parameters
40 90
P
– such as a relatively high amount of slope AVC
20
2  45
Magnitude (dB)
compensation – you may need to lower the loop
Phase (°)
Z
bandwidth to less than fSW/20. A Type III feedback 0
2 
0
network could compensate for this, but is not -20

L
-45
effective with a transconductance amplifier. -40 -90

2 
0.01 0.1 1 10 100 1000
Use the following simplified design method for the Frequency (kHz)
Figure 39 (b)
current-mode buck: Power stage (a)
• Choose a value for RFBT based on the bias current and 
1  ZEA
power dissipation. vˆC s
  AVM 

vÔUT s
1
• Find the modulator transconductance in A/V.  HF
• Pick a target bandwidth; typically, fSW/10: ωC = 2∙π∙fC. 40 225
• Find AVM to achieve the target bandwidth. 20 180

Magnitude (dB)
Phase (°)
• Set ωZEA equal to one-tenth the target crossover frequency: 0 AVM 135
 ZEA  HF
ωZEA = ωC/10. 2  2 
-20 90
• Set ωHF equal to the ESR zero frequency: ωHF = ωZ.
-40 45
0.01 0.1 1 10 100 1000
Solve Equations 94 through 99 to find the
component values: Figure 39 (c) Frequency (kHz)
Error amplifier (b)

1
Gm (mod) = (94)
Ri vÔUT vÔUT vˆC
 

vÔUT 
vˆC vÔUT
ωC ⋅ COUT
AVM = (95)

Gm (mod) 60 135
40 90
Magnitude (dB)
RCOMP = AVM ⋅ RFBT (op amp) (96)

Phase (°)
20 45
0 0
AVM C
RCOMP = (gm amp) (97) -20 2  -45
g m ⋅ K FB
-40 -90
0.01 0.1 1 10 100 1000
1
CCOMP = (98) Frequency (kHz)
ωZEA ⋅ RCOMP
Control loop (c)
1
C
HF = (99) Figure 39. The power-stage (a) and error-amplifier (b) plots sum to
ωHF ⋅ RCOMP produce the control-loop plot (c) for the current-mode buck frequency
response.

Current-mode boost example Use the following simplified design method for the
Figure 40 is the complete current-mode boost current-mode boost:
Figure 40
regulator model, showing the modulator, output filter • Choose a value for RFBT based on the bias current and
and error amplifier. For Type II compensation, this power dissipation.
example uses a transconductance amplifier. • Find the modulator transconductance in A/V.
• Find the right-half-plane zero frequency at the minimum
input voltage and maximum load current.
• Set the target bandwidth to one-fourth the right-half-plane
zero frequency: ωC = 2∙π∙fC = ωR/4.

• Find AVM to achieve the target bandwidth.
• Set ωZEA equal to one-tenth the target crossover
frequency: ωZEA = ωC/10.
• Set ωHF equal to the lower of the right-half-plane or ESR
Figure 40. This current-mode boost senses the current in series with
the switch. zero frequency: ωHF = ωR or ωZ.

Current-mode boost compensation

component values:
strategy
D′
We will now outline the compensation guidelines for G
m (mod) = (100)
Ri
a current-mode boost with Type II compensation.
At frequencies after the output-filter pole, the ROUT ⋅ D′2
ω R = (101)
modulator transconductance and output-filter L
capacitor set the power-stage gain. The overall ω ⋅C

A VM = C OUT (102)
loop bandwidth is typically limited to one-fourth Gm (mod)
the right-half-plane zero frequency. You can adjust
R COMP = AVM ⋅ RFBT (op amp) (103)
AVM to achieve the target loop bandwidth. To give

the maximum amount of phase boost, place the AVM
R
COMP = (gm amp) (104)
error-amplifier zero, ωZEA, a decade below the target g m ⋅ K FB
crossover frequency. The high-frequency pole, ωHF,
1 (105)
should cancel the lower of the right-half-plane or CCOMP =
ωZEA ⋅ RCOMP
ESR zero frequency.
1
Some sets of operating conditions and parameter C HF = (106)
ωHF ⋅ RCOMP
values may require additional phase margin. In such
cases, the crossover frequency may be limited Current-mode boost compensation
to one-fifth or one-sixth the right-half-plane zero results
frequency. Figure 41 shows the current-mode boost idealized
straight-line plots of the power stage, error amplifier
and control loop.

 s   s  Current-mode buck-boost example
1    1  
vÔUT     Z 
 AVC   R
Figure 42 is the complete current-mode
vˆC  s   s 
1    1   buck-boost regulator model, showing the
  P    L 
Figure 42 modulator, output filter and error amplifier. For

40 45 Type II compensation, this example uses a
P
AVC L
20 2  0 transconductance amplifier.
Magnitude (dB)
2 
Phase (°)
0 -45
-20 R Z -90
2  2 
-40 -135
-60 -180
0.01 0.1 1 10 100 1000
Frequency (kHz)

Power stage (a)

1  ZEA
vˆC s
  AVM 

vÔUT s
1
 HF Figure 42. The error amplifier is referenced to -VOUT for this
current-mode buck-boost.
40 270
20  HF 225 Current-mode buck-boost

AVM
Magnitude (dB)
0
2  180 compensation strategy
Phase (°)
 ZEA
-20 2  135 We will now outline the compensation guidelines
-40 90 for the current-mode buck-boost with Type II
-60 45 compensation. At frequencies after the output-filter
0.01 0.1 1 10 100 1000
pole, the modulator transconductance and output-
Frequency (kHz)
filter capacitor set the power-stage gain.
Error amplifier (b)
The overall loop bandwidth is typically limited to
one-fourth the right-half-plane zero frequency.
vÔUT vÔUT vˆC Adjust AVM to achieve the target loop bandwidth.
 

vÔUT 
vˆC vÔUT To give the maximum amount of phase boost, place
the error-amplifier zero, ωZEA, a decade below the
60 135
target crossover frequency. The high-frequency
40 90
pole, ωHF, should cancel the lower of the right-half-
Magnitude (dB)
Phase (°)
20 45
plane or ESR zero frequency.
0 0
C Some sets of operating conditions and parameter
-20 2  -45
values may require additional phase margin.
-40 -90
0.01 0.1 1 10 100 1000 In such cases, the crossover frequency may be
Frequency (kHz)
limited to one-fifth or one-sixth the right-half-plane
Control loop (c) zero frequency.
produce the control-loop plot (c) for the current-mode boost frequency
response.

Figure 43 (a)
Use the following simplified design method for the  s   s 
1    1  
current-mode buck-boost: vÔUT   R    Z 
 AVC 
vˆC  s   s 
• Choose a value for RFBT based on the bias current and 1    1  
  P    L 
power dissipation.
40 45
• Find the modulator transconductance in A/V. P
AVC L
20 2  0
Magnitude (dB)
• Find the right-half-plane zero frequency at the minimum 2 
Phase (°)
0 -45
-20 R Z -90
• Set the target bandwidth to one-fourth the right-half-plane 2  2 
-40 -135
zero frequency: ωC = 2∙π∙fC = ωR/4.
-60 -180
• Find AVM to achieve the target bandwidth. 0.01 0.1 1 10 100 1000
Frequency (kHz)
Figure 43 (b)
Power stage (a)

• Set ωHF equal to the lower of the right-half-plane or ESR 1  ZEA
vˆC s
  AVM 
zero frequency: ωHF = ωR or ωZ. 
vÔUT 1
s
 HF
40 270
component values:
20  HF 225
D′ (107) AVM
Magnitude (dB)
Gm (mod) = 0
2  180
Ri
Phase (°)
 ZEA
-20 2  135
R ⋅ Dʹ′2
ω R = OUT (108) -40 90
L⋅D
-60 45
0.01 0.1 1 10 100 1000
ω ⋅C
Figure 43 (c)
AVM = C OUT
Gm (mod)
(109) Frequency (kHz)
Error amplifier (b)

R COMP = AVM ⋅ RFBT (op amp) (110)
vÔUT vÔUT vˆC
 

vÔUT 
vˆC vÔUT
(111) AVM
RCOMP = (gm amp)
g m ⋅ K FB 60 135
40 90
1
C COMP = (112)
Magnitude (dB)
Phase (°)
ωZEA ⋅ RCOMP 20 45
0 0
C
1 (113)
CHF = -20 2  -45
ωHF ⋅ RCOMP
-40 -90
0.01 0.1 1 10 100 1000
Current-mode buck-boost Frequency (kHz)
compensation results Control loop (c)

Figure 43 shows the current-mode buck-boost
idealized straight-line plots of the power stage, error
produce the control-loop plot (c) for the current-mode buck-boost
amplifier and control loop. frequency response.

Isolated current-mode forward the optocoupler feedback, which incorporates the
example primary-side amplifier. In this configuration, the
optocoupler emitter is at a virtual ground of VREF.
Figure 44 is the complete isolated current-mode
This minimizes the pole due to the optocoupler’s
Figure 44 forward converter model, showing the modulator,
parasitic capacitance, since the collector-to-emitter
output filter and error amplifier. For Type II
voltage does not change.
compensation, this example uses a TL431 shunt
regulator and optocoupler. For an ideal current-mode forward, the upper
T1
NP : NS D1 L limit for the loop bandwidth is fSW/5. For nonideal
VIN VOUT
CIN D2
COUT
ROUT parameters such as a relatively high amount of
RESR
PWM
Logic slope compensation, you may need to lower the
Q1
VSLOPE loop bandwidth to less than fSW/20.
+ VCC RS
- RD CS
+
 Ri
RFBT
+
RP Use the following simplified design method for the
VC CCOMP
- current-mode forward:
+ RE
Peak current-mode forward VREF
TL431 RFBB
• Choose a value for RFBT based on the bias current and
Optimal VSLOPE = VOUT·Ri·T/L·NS/NP
power dissipation.
Figure 44. This isolated current-mode forward converter uses the • Find the modulator transconductance in A/V.
primary-side error amplifier as part of the feedback.
• Pick the target bandwidth; typically, fSW/10: ωC = 2∙π∙fC.
Current-mode forward compensation • Find AVM to achieve the target bandwidth.
strategy • Adjust RD, RP and COUT as required.
We will now outline the compensation guidelines for • Set ωZEA equal to one-tenth the target crossover
a current-mode forward with Type II compensation. frequency: ωZEA =ωC/10.
At frequencies after the output-filter pole, the • Set ωHF equal to the ESR zero frequency: ωHF = ωZ.
modulator transconductance and output-filter
capacitor set the power-stage gain. Adjust AVM to
component values:
achieve the target loop bandwidth, typically one-
tenth the switching frequency. The selection of RD 1 NP
G
m (mod) = ⋅ (114)
Ri N S
and RP for DC bias considerations may limit AVM.
In such cases, you may need to increase COUT
ωC ⋅ COUT
A
VM = (115)
to meet the desired crossover frequency. To give Gm (mod)
the maximum amount of phase boost, place the
error-amplifier zero, ωZEA, a decade below the target R
RD = CTR ⋅ P
(116)
crossover frequency. The high-frequency pole,ωHF, A VM
should cancel the ESR zero of the output capacitor.

1
C COMP = (117)
For capacitors with very low ESR, you can set the RFBT ⋅ ωZEA
pole to 10 times the crossover frequency. This
1
example uses a high-bandwidth configuration for C S = (118)
RS ⋅ ω HF

s Current-mode forward compensation
1
vÔUT Z results
 AVC 
vˆC  s   s 
1    1   Figure 45 shows the current-mode forward
  P    L 
idealized straight-line plots of the power stage, error

40 90 amplifier and control loop.
P
AVC 2 
20 45
Magnitude (dB)
Isolated current-mode flyback
Phase (°)
Z
0
2 
0
example
-20
L
-45 Figure 46 Figure 46 is the complete current-mode flyback
2  regulator model showing the modulator, output
-40 -90
0.01 0.1 1 10 100 1000 filter and error amplifier. For Type II compensation,
Frequency (kHz)
this example uses a TL431 shunt regulator and
Power stage (a) optocoupler.
T1
 ZEA VIN
NP : NS D1
VOUT
1
vˆC s CIN LP COUT
  AVM  ROUT

vÔUT s RESR
1 PWM
 HF Logic Q1
VSLOPE
A VCC
40 225 +
- Ri = A·RS RS
+

+ RP RD
20 180 VC
Magnitude (dB)
Phase (°)
CP RBIAS
0 AVM 135
 ZEA  HF RFBT
CCOMP
-20
2  2  90 Peak current-mode flyback TL431
Optimal VSLOPE = VOUT·Ri·T/LP·NP/NS RFBB
-40 45
0.01 0.1 1 10 100 1000 Figure 46. The optocoupler feedback for this isolated current-mode
Frequency (kHz) flyback is implemented with a minimum of components.
Error amplifier (b)

Current-mode flyback compensation
vÔUT vÔUT vˆC strategy
 

vÔUT 
vˆC vÔUT We will now outline the compensation guidelines for
the current-mode flyback with Type II compensation.
60 135
At frequencies after the output-filter pole, the
40 90
modulator transconductance and output-filter
Magnitude (dB)
Phase (°)
20 45
capacitor set the power-stage gain. The overall loop
0 0 bandwidth is typically limited to one-fourth the right-
C
-20 2  -45 half-plane zero frequency. Adjust AVM to achieve the
-40 -90 target loop bandwidth. The selection of RD and RP
0.01 0.1 1 10 100 1000
Frequency (kHz)
for DC bias considerations may limit AVM. In such
cases, you may need to increase COUT to meet the
Control loop (c) desired crossover frequency. To give the maximum
amount of phase boost, place the error-amplifier
Figure 45. The power-stage (a) and error-amplifier (b) plots sum zero, ωZEA, a decade below the target crossover
to produce the control-loop plot (c) for the current-mode forward
frequency response. frequency. The high-frequency pole, ωHF, should
cancel the lower of the right-half-plane or ESR
zero frequency.

Figure 47 (a)
Some sets of operating conditions and parameter  s   s 
1    1  
values may require additional phase margin. vÔUT   R    Z 
 AVC 
In such cases, the crossover frequency may be vˆC  s   s 
1    1  
  P    L 
limited to one-fifth or one-sixth the right-half-plane
zero frequency. 40 45
P
AVC L
Use the following simplified design method for the 20 2  0
Magnitude (dB)
2 
current-mode flyback:
Phase (°)
0 -45
• Choose a value for RFBT based on the bias current and -20 R Z -90
power dissipation. 2  2 
-40 -135
• Find the modulator transconductance in A/V.
-60 -180
0.01 0.1 1 10 100 1000
• Find the right-half-plane zero frequency at the minimum
Frequency (kHz)
Figure 47 (b)
• Set the target bandwidth to one-fourth the right-half-plane Power stage (a)
zero frequency: ωC = 2∙π∙fC = ωR/4. 
1  ZEA
• Find AVM to achieve the target bandwidth. vˆC s
  AVM 

vÔUT s
• Adjust RD, RP and COUT as required. 1
 HF
40 270
20  HF 225
• Set ωHF equal to the lower of the right-half-plane or ESR
Magnitude (dB)
AVM 2 
0 180
zero frequency: ωHF = ωR or ωZ.
Phase (°)
 ZEA
-20 2  135
-40 90
component values:
-60 45
(mod) = D′ ⋅ N P
G (119) 0.01 0.1 1 10 100 1000
m
Ri N S Figure 47 (c) Frequency (kHz)
2 Error amplifier (b)

R ⋅ D′2 ⎛ N P ⎞
ω R = OUT ⋅⎜ ⎟ (120)
LP ⋅ D ⎜⎝ N S ⎟⎠
vÔUT vÔUT vˆC
 
ω ⋅C 
vÔUT 
vˆC vÔUT
A VM = C OUT (121)
Gm (mod)
60 135
R
R D = CTR ⋅ P (122) 40 90
Magnitude (dB)
A VM
Phase (°)
20 45
1 0 0
C COMP = (123)
RFBT ⋅ ωZEA -20
C
-45
2 
1 -40 -90
C P = (124) 0.01 0.1 1 10 100 1000
RP ⋅ ω HF
Frequency (kHz)
Current-mode flyback compensation Control loop (c)

results
Figure 47 shows the current-mode flyback Figure 47. The power-stage (a) and error-amplifier (b) plots sum
to produce the control-loop plot (c) for the current-mode flyback
idealized straight-line plots of the power stage, error frequency response.
amplifier and control loop.

Bandwidth versus transient response With no ESR, slew rate or duty-cycle limiting, Equation
Transient response is directly related to the 125 calculates tP as:
bandwidth of the control loop. With no ESR, slew 1

tP =
4 ⋅ fC
rate or duty-cycle limiting, the initial response time is
one-fourth the effective control-loop period. This is (125)
1
tP = = 25µs
the equivalent first quarter of a sinusoidal response 4 ⋅10kHz
at the unity-gain frequency. The peak voltage will vary Current-mode single-pole approximation with Equation
based on the topology and damping, but is easily 126 calculates VP as:
predictable with a surprising degree of accuracy.
ΔI
VP =
It is important to verify the performance over all 2 ⋅ π ⋅ f C ⋅C OUT
operating conditions. Duty-cycle limiting can cause (126)
5A
a significant droop when operating the control loop VP = = 180mV
2 ⋅ π ⋅10kHz ⋅ 440µF
outside its linear range. Reference [11] is an Applied
Current-mode critically damped (as shown in
Power Electronics Conference and Exhibition (APEC)
ure 48 paper on the topic, which includes design methods
Figure 49) with Equation 127 calculates VP as:
ΔI
to meet transient response. Figure 48 shows a VP =
e ⋅ π ⋅ f C ⋅C OUT
typical frequency-response plot, while Figure 49
(127)
shows the transient response. 5A
VP = = 130mV
e ⋅ π ⋅10kHz ⋅ 440µF
60 135 Voltage-mode control with Equation 128 calculates VP

40 90 as:
Magnitude (dB)
ΔI
Phase (°)
20 45 VP =
8 ⋅ f C ⋅C OUT
49 0
-20 fC
0
-45

VP =
5A
= 140mV
(128)
8 ⋅10kHz ⋅ 440µF
-40 -90
0.01 0.1 1 10 100 1000
Frequency (kHz)
Practical limitations of error
Figure 48. The current-mode bandwidth is set at 10 kHz for this amplifiers
example.
The error-amplifier bandwidth can limit the maximum
loop-crossover frequency. As you can see from
Figure 50, where the closed-loop gain intersects the
∆I open-loop gain plot, the phase drops quickly. You will
need a wider-bandwidth op amp for voltage mode
due to Type III compensation.
vP
tP
Figure 49.The corresponding current-mode transient response shows

tP = 25 μs and VP = 130 mV for a load step of ∆I = 5 A.

ure 50
bandwidth, a voltage-mode converter can approach

Error amplifier BW limit
80 270 one-third the switching frequency and have adequate
60 225 phase and gain margin. An ideal current-mode buck can
Magnitude (dB)
achieve one-fifth the switching frequency with critical
Phase (°)
40 180
damping. Higher crossover frequency results in higher
20
0 90
Figure 52
135
noise sensitivity and possible switching jitter. A general
rule of thumb is one-fifth to one-tenth the switching
-20 45
0.01 0.1 1 10 100 1000 frequency. The right-half-plane zero usually limits boost
Frequency (kHz)
and buck-boost converters operating in CCM.
Figure 50: The error amplifier’s open-loop gain and bandwidth set a
hard limit for the closed-loop response.
Voltage-mode control loop
80 180
Practical limitations of optocouplers 60 135
Magnitude (dB)
Phase Margin (°)

Resistance in series with the output transistor forms a 40 90
pole in the kilohertz range. The pole is dependent on
20 45
bias current and output resistance. As you can see in
0 0
Figure 51, higher output resistance causes the pole fSW = 200 kHz
-20 -45
to occur at a lower frequency. In a simplified analysis, 0.01 0.1 1 10 100 1000
Frequency (kHz)
we used a single pole with an external capacitor. With
ure 51 no external capacitor the roll-off approaches –40 dB/ Figure 52. The voltage-mode control loop shows the phase going
to zero near the switching frequency. The available gain and phase
decade, with phase shift at higher frequencies of margin set an upper limit on the control-loop bandwidth.
–180 degrees. This is more of an issue for forward- or
other buck-derived topologies with higher crossover Discontinuous versus continuous
frequencies. conduction-mode
DCM occurs when the inductor current dwells at zero
Opto frequency response
20 45 before the end of the switching cycle. DCM is a normal
Gain condition for diode-rectified circuits when the load drops
0
Figure 53
0
Magnitude (dB)
to a light level. DCM causes a reduction in bandwidth,

Phase (°)
-20 -45
which you can clearly see in Figure 53 for the current-
-40 RP = 1 kΩ -90
RP = 5 kΩ mode response. In general, if the control loop is stable in
-60 RP = 20 kΩ -135
Phase CCM, it will also be stable in DCM.
-80 -180
1 10 100 1000
Frequency (kHz) Current-mode buck power stage
40 90
Figure 51. The optocoupler pole moves toward lower frequencies at 20 45
Magnitude (dB)
lower bias currents using higher resistor values. Gain

0 0
Phase (°)
-20 -45
Practical limitations due to the
-40 -90
switching frequency CCM Phase
-60 -135
DCM
The maximum crossover frequency is some fraction -80 -180
of the switching frequency. Figure 52 shows the 0.01 0.1 1 10 100 1000
Frequency (kHz)
control-loop phase margin going quickly negative at
the switching frequency. With a sufficient error-amplifier Figure 53. The current-mode power-stage bandwidth is reduced in
DCM.

Figure 55
re 54
For the voltage-mode response shown in Figure
54, the order of the filter is reduced in DCM, since
the inductor now acts as a current source.
Voltage-mode buck power stage

40 90
20 45
Magnitude (dB)
Gain
0 0
Phase (°)
-20 -45
Figure 55. The converter acts as a load on the input filter. For stability,
filter ZOUT << converter ZIN.
-40 -90
-60 CCM Phase -135
DCM Equations 132 and 133 calculate the characteristic
-80 -180
0.01 0.1 1 10 100 1000 source impedance and resonant frequency,
Frequency (kHz) respectively:
LIN
Figure 54. The voltage-mode power-stage bandwidth is also reduced Z S = (132)
in DCM. CIN
1
DCM duty cycle f S = (133)
2 ⋅ π ⋅ LIN ⋅ CIN
Equations 129 through 131 show the duty-cycle
equations for DCM. To determine the mode The converter exhibits a negative input impedance,
boundary, you can set the CCM and DCM duty- which is lowest at the minimum input voltage
cycle equations equal to each other. (Equation 134):
2
2 ⋅ L ⋅ f SW ⋅ I OUT ⋅VOUT VIN V

Buck: D= (129) Z IN = − = − IN (134)
VIN ⋅ (VIN − VOUT ) I IN POUT
Equation 135 gives the damping factor for the input

2 ⋅ L ⋅ f SW ⋅ I OUT ⋅ (VOUT − VIN )

Boost: D= (130) filter as:
VIN
1 ⎛ RL + RC Z S ⎞
ζ = ⋅ ⎜⎜ + ⎟ (135)
2 ⋅ L ⋅ f SW ⋅ I OUT ⋅VOUT (131) 2 ⎝ ZS Z IN ⎟⎠
Buck-boost: D=
VIN
where RL is the input wiring resistance and RC is the
Input-filter stability and second- series resistance of the input capacitors. The term
stage filters ZS/ZIN will always be negative due to ZIN.
Input-filter stability When ζ = 1, the input filter is critically damped, but

this value may be difficult to achieve with practical
The line impedance and input capacitors form a
component values. When ζ < 0.2, the input filter
resonant circuit when connecting the converter
to a remote input power source through a wiring will exhibit significant ringing. If ζ is zero or negative,
harness, as shown in Figure 55. Typical wiring there is not enough resistance in the circuit and the
inductance is on the order of 0.5 μH/m. An input input filter will sustain an oscillation.
inductor reduces reflected ripple current back

to the source. In order to minimize overshoot,
make CIN > 10·LIN.

The general guidelines are:
• Converter input impedance – switching regulators exhibit

a negative input impedance, which is lowest at the
minimum input voltage.
• Filter output impedance – an underdamped LC filter
Figure 56. A buck regulator with second-stage filter.
exhibits a high output impedance at resonance.
The general guidelines are:
• Relative impedance – for stability, the filter’s output
• Filter capacitors – make COUT1 smaller than COUT2. COUT1 is
impedance must be much less than the converter’s input
typically ceramic.
impedance.
• Filter inductors – make L2 smaller than L1. Make sure that
ISAT is greater than IOUT max.
When operating near the minimum input voltage,
you may need an aluminum electrolytic capacitor • Filter resonance – make the second-stage filter resonance
across CIN to damp the input. You should evaluate three times larger than the crossover frequency.
any parallel capacitor for its root-mean-square • Damping – damp the second-stage filter to a Q of 1.
(RMS) current rating. The current will split between
the ceramic and aluminum capacitors based on the Primary-side compensation
relative impedance at the switching frequency. considerations
Primary-side compensation
Second-stage filter
Figure 57 illustrates a method that uses the
Figure 56 shows the power stage of a buck
Figure 57
regulator followed by a second-stage filter. The first-
primary-side inverting amplifier to implement
frequency compensation. Though not often
stage capacitor is sized to handle the output RMS
used alone, it can complement secondary-side
current, while the second-stage capacitor reduces
compensation. If the output-voltage accuracy is not
the ripple voltage and provides energy storage
critical, a series Zener and resistor can directly drive
for the load transient. This method is particularly
the optocoupler from the output voltage.
useful for boost- or buck-boost-type outputs, which
have high ripple voltage due to the pulsing rectifier
VC VCC
current.
You must include the effect of the second-stage
RF
filter in the control-loop analysis. Account for the RI
total output capacitance and use the capacitance -
to determine the loop bandwidth. A second-stage
+ VREF RE
resonance at too low a frequency can cause the
Figure 57. Primary-side compensation can provide additional control
control loop to go unstable, even when taking
of the frequency response.
feedback at the first-stage output.

High-bandwidth configuration
Figure 60 Phase boost
Figure 58 shows a configuration where the Figure 60 shows how a feed-forward network
optocoupler emitter is at a virtual ground of VREF. across RD adds phase boost for increased
58 This configuration minimizes the pole due to the bandwidth. This method cancels the inherent pole
optocoupler’s parasitic capacitance, since the of the optocoupler.
collector-to-emitter voltage does not change. This
V′OUT
configuration is also particularly useful in forward RD CFF
converters to achieve high bandwidth; we used it
RFF
in the section covering the isolated current-mode
forward example.
CCOMP RFBT
VCC
VC TL431 RFBB
RP
Figure 60. Placing a lead network across the optocoupler’s
- gain-setting resistor adds phase boost.
+ VREF RE
Zener bias
Figure 58. The optocoupler emitter is biased at VREF of the primary- Figure 61 shows how Zener bias for RD eliminates
Figure 61
side amplifier in the high-bandwidth configuration.
the high-frequency feedback path for secondary-
side compensation. This method is common for
Secondary-side compensation higher output voltages to prevent exceeding the
considerations TL431’s voltage rating. RS and ZS can also bias the
ESR zero compensation optocoupler from the rectified secondary voltage.
Figure 59 shows how a resistor-capacitor (RC)

V′OUT
pole to the optocoupler can cancel the ESR zero RS
59 of the output capacitor, which is helpful when
RD ZS
RFBT
using aluminum electrolytic output capacitors CHF
with high ESR. We used this configuration in the
section covering the isolated current-mode forward CCOMP RCOMP
example. TL431 RFBB
V′OUT
CS RS
RD Figure 61. A Zener biases the optocoupler with a fixed voltage.
Real-world compensation example

Switching regulator with poor compensation
CCOMP RFBT
Figure 62 shows a basic current-mode buck
TL431 RFBB regulator, which uses a transconductance amplifier.
After building the circuit, it showed a fairly high
Figure 59. A simple RC to the optocoupler allows for ESR zero crossover frequency with low phase margin.
compensation.

DC bias of the output ceramic capacitors reduced
Power stage
the effective capacitance substantially. A switched 40 45
resistive load exercised the loop at its maximum
20 0
Magnitude (dB)
igure 62 bandwidth. Bench measurements of the control
Phase (°)
loop agreed with the transient response shown 0 -45
in Figure 63, where low phase margin results in -20 -90

output-voltage ringing.
0.1 μF
Figure 64 (b) -40 -135
-60 -180
3.3 μH
0.1 1 10 100 1000
VIN BOOT VOUT
VIN PH Frequency (kHz)
15 μF
31.6 kΩ
GND U1 47 μF (a)
VSENSE
EN
e 63
COMP 10 kΩ
SS/TR 5 kΩ Error amplifier
RT/CLK
22 μF 60 270
10 nF 100 kΩ 1 nF effective
capacitance 40 225
Magnitude (dB)
Phase (°)
Figure 62. A synchronous buck regulator exhibits poor transient 20 180
performance. 0 135
Figure 64 (c) -20
-40
90
45
0.1 1 10 100 1000
IOUT Frequency (kHz)
(b)
VOUT
Control loop
60 135
40 90
Magnitude (dB)
Phase (°)
Figure 63. An underdamped transient response indicates low phase 20 45

margin.
0 0
By observing the frequency response in Figure -20 -45

64, you can analyze the performance. In -40 -90
Figure 64a, the phase is headed toward –180 0.1 1 10 100 1000
Frequency (kHz)
degrees, indicating relatively high internal slope
compensation. In Figure 64b, the error-amplifier (c)
zero appears to be a bit high and the mid-band
gain is around 3 dB. In Figure 64c, the crossover Figure 64. The power-stage (a) and error-amplifier (b) plots sum to
produce the control-loop plot (c), showing high bandwidth and low
frequency is 95 kHz, with only 20 degrees of phase margin.
phase margin.

Switching regulator with revised compensation
Power stage
igure 65 Adjusting the compensation network of the error 40 45
amplifier achieves well-damped performance.
20 0
Magnitude (dB)
Figure 65 shows the revised circuit, while
Phase (°)
0 -45
Figure 66 shows the improved transient response.
-20 -90
0.1 μF
-40 -135
3.3 μH
Figure 67 (b)
VIN BOOT VOUT
VIN PH -60 -180
15 μF
31.6 kΩ 0.1 1 10 100 1000
GND U1 47 μF
VSENSE Frequency (kHz)
66 EN
SS/TR
COMP
RT/CLK
10 kΩ
1 kΩ (a)
22 μF
10 nF 100 kΩ 10 nF effective
capacitance
Error amplifier
Figure 65. Adjusting only two compensation components improved 60 270
the performance.
Magnitude (dB) 40 225
Phase (°)
20 180
0 135
IOUT -20 90
Figure 67 (c) -40 45
0.1 1 10 100 1000
VOUT Frequency (kHz)
(b)
Figure 66. A critically damped transient response indicates good Control loop
phase margin. 60 135
40 90
Magnitude (dB)
By observing the frequency response in

Phase (°)
20 45
Figure 67, you can analyze the performance.
0 0
In Figure 67a, there is no external adjustment for
-20 -45
slope compensation. All power-stage components
-40 -90
are the same. In Figure 67b, decreasing RCOMP
0.1 1 10 100 1000
lowers the mid-band gain, which will lower the Frequency (kHz)
crossover frequency. Increasing CCOMP to move the
error-amplifier zero to a lower frequency increases (c)
the phase margin at crossover. In Figure 67c, the

Figure 67. By leaving the power stage (a) as is and adjusting the
crossover frequency is now 30 kHz, with 67 degrees error-amplifier (b) response, the control loop (c) exhibits acceptable
of phase margin. gain and phase margin.

Summary 5. Dixon, L.H. “Control Loop Design.” Texas Instruments
This paper covered CCM operation of voltage- and Power Supply Design Seminar SEM800, 1991.
current-mode converters. Standard linear feedback 6. Dixon, L.H. “Control Loop Cookbook.” Texas Instruments
amplifiers for nonisolated and isolated converters Power Supply Design Seminar SEM1100, 1996.
enable a wide range of compensation techniques.
7. Ridley, R. “A More Accurate Current-Mode Control
We hope that you can use the design examples of
Model.” Texas Instruments Power Supply Design
popular topologies we have given here.
Seminar SEM1300, 1999.
To summarize the compensation design method
8. Mitchell, D., and Mammano, B. “Designing Stable
simply:
Control Loops.” Texas Instruments Power Supply Design
• Identify the poles and zeros of the power stage.
Seminar SEM1400, 2001.
• Cancel the power stage poles and zeros with zeros and
9. Sheehan, R. “Current Mode Modeling – Reference
poles in the error amplifier.
Guide.” (SNVA542), Texas Instruments, 2007.
• Adjust the gain for best performance.
10. Sheehan, R. “Understanding and Applying Current-Mode
Control Theory.” (SNVA555). Texas Instruments, 2007.
Additional information 11. Bag, S., Mukhopadhyay, S., Samanta, S., Sheehan,
1. Dixon, L.H. “Closing the Feedback Loop.” Texas R., and Roy, T. “Frequency Compensation and Power
Instruments Power Supply Design Seminar SEM300, Stage Design for Buck Converters to Meet Load
1984. Transient Specifications.” 2014 IEEE Applied Power
2. Dixon, L.H. “Current-Mode Control of Switching Power Electronics Conference and Exhibition – APEC 2014,
Supplies.” Texas Instruments Power Supply Design 1024-1031.
Seminar SEM400, 1985. 12. Meeks, D. “Loop Stability Analysis of Voltage Mode
3. Dixon, L.H. “The Right-Half-Plane Zero – A Simplified Buck Regulator with Different Output Capacitor Types
Explanation.” Texas Instruments Power Supply Design – Continuous and Discontinuous Modes.” Texas
Seminar SEM500, 1986. Instruments Application Report (SLVA301), April 2008.
4. Mammano, R. “Isolating the Control Loop.” Texas

Instruments Power Supply Design Seminar SEM700,
1990.

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Switch-Mode Power Converter Compensation Made Easy: Robert Sheehan

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Switch-mode power

Introduction Many SMPS designers would appreciate a how-

Texas Instruments 2 September 2016

Texas Instruments 3 September 2016

-40 -90 -60 -135

be going through zero. If that happens, you could

Poles and zeros definitions 0 0

Texas Instruments 4 September 2016

ωZ As mentioned in the introduction, we will discuss

a complex conjugate pole at the LC resonant

order to compensate for this phase change.

-20 -135 Q=2

0.01 0.1 1 10 100 1000 -20 Q=1 -45

Figure 9. The Bode plot of a complex conjugate pole shows the

Texas Instruments 5 September 2016

re 10 over two decades. Forward, two-switch forward, active-clamp forward

Texas Instruments 6 September 2016

Figure 13. A single switch buck-boost converter inverts the polarity of

Figure 12. A boost converter steps up the input to produce a higher

to-output voltage relationship. Equation 11 holds

Texas Instruments 7 September 2016

degrees. See Equation 17. This pole is followed by Z

Texas Instruments 8 September 2016

the inductor current decreases and tends toward

Texas Instruments 9 September 2016

re 17 internally compensated regulators, data sheets may

Equations 28 and 29 give the duty-cycle relationship

available to adjust the response. V − VIN

0 -45 Equation 30 shows the transfer function for the

Texas Instruments 10 September 2016

to the output capacitance and the load resistance. -20 R Z -90

For the peak current-mode boost, Equation 36

where Ri is the current-sense gain times the sense

Texas Instruments 11 September 2016

Equation 41 calculates the first pole, which is related -20 R Z -90

Texas Instruments 12 September 2016

T1 Equation 51 calculates the second pole, which is

Equation 52 gives the zero, which is related to the

NP For the peak current-mode forward, Equation 53

Equation 49 expresses the gain as: 40 45

where Ri = A ⋅ RS . -20 -90

Texas Instruments 13 September 2016

Texas Instruments 14 September 2016

control voltage by the open loop gain of the

in the feedback. Figure 27 shows the straight-line approximation of

Texas Instruments 15 September 2016

re 27 no output capacitor. While you can use this type of

While Equation 72 reveals a high-frequency pole at:

Figure 29 shows the straight-line approximation of

Using the same derivation process as for Type I -20 -45

Texas Instruments 16 September 2016

potential and the AC contribution of the lower 1

You can use the transconductance amplifier for

Texas Instruments 17 September 2016

Type III error amplifier

Texas Instruments 18 September 2016

Figure 35. The frequency response of this optocoupler feedback has

Texas Instruments 19 September 2016

Use the following simplified design method for the

We will now outline the compensation guidelines for

a voltage-mode buck with Type III compensation.

parameter, you can change the performance of the 1

The two zeros, ωZEA and ωFZ, should cancel the 1