Is Now Part of

‫ا‬ /‫م‬
‫ﺣﻣ‬
‫دﯾ‬
‫وﺳ‬
‫ف‬
‫اﻟﻣ‬

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com
‫ﺻ‬

‫ﺗﺻﻣﯾم ﻛوﻧﻔرﺗر ﻓﻼﯾﺑﺎك‬

‫رى‬

FPS ‫ﺑﺎﺳﺗﺧدام ﺳﻠﺳﻠﺔ اﯾﺳﯾﮭﺎت ﺷرﻛﺔ ﻓﯾرﺷﯾﻠد‬

Fairchild Power Switch (FPS)

 www.fairchildsemi.com

Application Note AN4137

Design Guidelines for Off-line Flyback Converters
Using Fairchild Power Switch (FPS)

Abstract

‫ﺧطوة ﺑﺧطوة ﺗﺻﻣﯾم ﺑﺎور ﺳﺑﻼى ﺑﺎﯾﺳﯾﮭﺎت ﺷرﻛﺔ ﻓﯾرﺷﯾﻠد ذات اﻟﻣوﺳﻔت اﻟداﺧﻠﻰ‬

/ ‫م‬
‫اﺣ‬
D R(n) L P(n)
Bridge
rectifier -
diode V DC R sn C sn Vsn
+ Np N S(n)
+

‫ﻣد‬
CO(n) CP(n) VO(n)
CDC -
Dsn
FPS D R1 L P1
‫ﯾ‬ Drain 1
‫وﺳ‬
N S1
CO1 CP1 V O1
AC line GND 2

FB Vcc
‫ف‬

4 3 Da
Ra
Rd Rbias
H11A817A
CB H11A817A
Ca Na R1
‫اﻟﻣ‬

RF CF
KA431
‫ﺻ‬

R2
‫رى‬

Figure 1. Basic Off-line Flyback Converter Using FPS

1. Introduction
Figure 1 shows the schematic of the basic off-line flyback
converter using FPS, which also serves as the reference
circuit for the design process described in this paper.
Because the MOSFET and PWM controller together with
various additional circuits are integrated into a single
package, the design of SMPS is much easier than the discrete
MOSFET and PWM controller solution. This paper provides
a step-by-step design procedure for a FPS based off-line
flyback converter, which includes designing the transformer
©2003 Fairchild Semiconductor Corporation
and output filter, selecting the components and closing the
feedback loop. The design procedure described herein is
general enough to be applied to various applications. The
design procedure presented in this paper is also imple-
mented in a software design tool (FPS design assistant) to
enable the engineer finish their SMPS design in a short time.
In the appendix, a step-by-step design example using the
software tool is provided. An experimental flyback converter
from the design example has been built and tested to show
the validity of the design procedure.
Rev. 1.3.0
 ‫‪AN4137‬‬ ‫ﻣراﺣل اﻟﺗﺻﻣﯾم‬ ‫‪APPLICATION NOTE‬‬

‫‪-1‬ﻋﯾن ﻣواﺻﻔﺎت اﻟﺑﺎور اﻻﺳﺎﺳﯾﺔ ‪ :‬اﻗل واﻗﺻﻰ ﺟﮭد‬

‫دﺧل ﻣﺗردد وﺗردد اﻟﺧط وﻗدرة اﻟﺧرج وﻛﻔﺎﺋﺔ اﻟﺑﺎور‬

‫‪ - 2‬ﺗﻌﯾﯾن ﺳﻌﺔ وﺟﮭد ﻣﻛﺛف اﻟدﺧل ﻟﻠﺧط‬

‫‪ - 3‬ﺗﻌﯾﯾن اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬

‫م‬
‫‪ - 4‬ﺗﻌﯾﯾن ﻣﺣﺎﺛﺔ ﻣﻠف اﻻﺑﺗداﺋﻰ ﻟﻠﻣﺣول‬ ‫ﻣﺣﺎﺛﺔ اﻟﻘﻠب ھﻰ ﻣن ﺗﺣدد ﻋدد‬
‫ﻟﻔﺎت اﻻﺑﺗداﺋﻰ‬

‫‪/‬‬
‫‪ -5‬اﺧﺗﺎر اﻻﯾﺳﻰ اﻟﻣﻧﺎﺳﺑﺔ ﻋﻠﻰ اﺳﺎس‬
‫ﻗدرة اﻟدﺧل واﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت‬

‫اﺣ‬
‫‪ - 6‬اﺧﺗﺎر اﻟﻘﻠب اﻟﻣﻧﺎﺳب ﺣﺳب ﻗدرة اﻟﺑﺎور‬
‫واﻗل ﻋدد ﻟﻔﺎت ﻟﻼﺑﺗداﺋﻰ‬

‫ﯾ‬ ‫ﻣد‬
‫‪ - 7‬اﺧﺗﺎر ﻋدد اﻟﻠﻔﺎت اﻟﺛﺎﻧوى ﻟﻛل ﺧرج‬

‫‪ - 8‬اﺣﺳب ﻗطر اﻟﺳﻠك ﻟﻛل ﺧرج‬

‫وﺳ‬
‫اذ ﻟم ﺗﻛن ﻣﺳﺎﺣﺔ ﺷﺑﺎك اﻟﻘﻠب ﻛﺎﻓﯾﺔ ﻟﻠﻣﻠﻔﺎت‬ ‫ﻧﻌم‬
‫ﻓﺎذھب اﻟﻰ اﻟﺧطوة ‪ 6‬ﻻﺧﺗﯾﺎر ﻗﻠب اﺧر اذا‬ ‫ھل ﻣﺳﺎﺣﺔ ﺷﺑﺎك اﻟﺑﻛرة ﻛﺎﻓﻰ ﻟﻠﻣﻠﻔﺎت ؟‬
‫ف‬

‫ﻛﺎن ﺑﺎﻻﻣﻛﺎن ﺗﻐﯾﯾر اﻟﻘﻠب‬

‫ﻻ‬

‫ﻧﻌم‬
‫ھل ﯾﻣﻛن ﺗﻐﯾﯾر اﻟﻘﻠب ؟‬
‫اﻣﺎ اذا ﻟم ﯾﻛن ھﻧﺎك اﻣﻛﺎﻧﯾﺔ ﻟﺗﻐﯾﯾر اﻟﻘﻠب ﻓﺎﻋد‬
‫اﻟﻣ‬

‫ﺗﺣدﯾد اﻟﻣﺣﺎﺛﺔ ﺣﺗﻰ ﺗﺣﺻل ﻋﻠﻰ ﻋدد ﻟﻔﺎت اﻗل‬ ‫ﻻﯾﻣﻛن ﺗﻐﯾﯾر اﻟﻘﻠب‬
‫ﺻ‬

‫‪ - 9‬اﺧﺗﺎر داﯾود اﻟﺧرج اﻟﻣﻧﺎﺳب ﻟﻛل ﺧرج ﺛﺎﻧوى‬

‫رى‬

‫‪ -10‬اﺣﺳب ﻣﻛﺛﻔﺎت اﻟﺧرج ﻟﻠﺛﺎﻧوى‬

‫‪ - 11‬ﺻﻣم داﺋرة اﻻﺧﻣﺎد ‪RCD‬‬

‫) ﺷﻛل ‪( 2‬‬ ‫‪ - 12‬ﺻﻣم داﺋرة اﻟﻔﯾدﺑﺎك‬

‫اﻧﺗﮭﻰ اﻟﺗﺻﻣﯾم‬

‫)‪(4‬‬ ‫اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﯾﻘﻊ ﻋﻠﻰ ﻣﻛﺛف اﻟدﺧل = اﻗﺻﻰ ﺟﮭد دﺧل ﻣﺗردد ‪ x‬ﺟذر ‪2‬‬
 ‫ﻓﻰ ھذا اﻟﺟزء ﺳﻧﻘوم ﺑﺗﺻﻣﯾم ﺑﺎور ﻣن ﻧوع ﻓﻼﯾﺑﺎك ﺑﺎﯾﺳﻰ ﻣن ﻓﯾرﺷﯾﻠد وﺑﺎﻻﺳﺗﻌﺎﻧﺔ ﺑﺎﻟرﺳم ‪ 1‬وﻓﻰ‬
‫اﻟﻌﻣوم ﻣﻌظم ﺗﻠك اﻻﯾﺳﯾﮭﺎت ﯾﺣﺗوى ﻋﻠﻰ ﻧﻔس اﻻطراف ﻣن ‪ 1‬اﻟﻰ ‪ 4‬اﻟﻣوﺟودة ﻓﻰ ﺷﻛل ‪..... 1‬‬
‫ﺷﻛل ‪ 2‬ﯾﺑﯾن ﻣراﺣل اﻟﺗﺻﻣﯾم وﺗﻔﺎﺻﯾل اﻟﺗﺻﻣﯾم ﻛﺎﻟﺗﺎﻟﻰ ‪:‬‬

‫‪ - 1‬ﺧطوة اوﻟﻰ ‪ :‬ﻣواﺻﻔﺎت اﻟﺑﺎور‬

‫)‪.(Vlinemin and Vlinemax‬‬ ‫‪ -‬اﻗﺻﻰ ﺟﮭد دﺧل واﻗل ﺟﮭد دﺧل ﻣﺗردد‬

‫‪. (Line frequency (fL -‬‬ ‫‪ -‬ﺗردد ﺧط اﻟدﺧل‬

‫‪.(Maximum output power (Po -‬‬ ‫‪ -‬اﻗﺻﻰ ﻗدرة ﺧرج‬

‫م‬
‫‪: (Eff) -‬‬ ‫‪ -‬ﻛﻔﺎﺋﺔ اﻟﺑﺎور‬

‫‪/‬‬
‫‪ -‬اذا ﻟم ﯾﻛن ھﻧﺎك ﺑﯾﺎﻧﺎت ﻣﻠزﻣﺔ ﻧﺿﻊ ﻗﯾﻣﺔ ﻛﻔﺎﺋﺔ اﻟﺑﺎور ﻣن ‪ 0.75 : 0.7‬ﻟﻠﺑﺎور اﻟﻣﻧﺧﻔض اﻟﻘدرة‬

‫اﺣ‬
‫‪ 0.85 : 0.8 -‬ﻟﻠﺑﺎور اﻟﻌﺎﻟﻰ اﻟﻘدرة‬
‫ﯾ‬ ‫ﻣد‬
‫ﺑﻣﻌرﻓﺔ اﻟﻛﻔﺎﺋﺔ ﯾﺗم ﺗﺣدﯾد اﻗﺻﻰ ﻗدرة دﺧل ﻣن ﺧﻼل اﻟﻌﻼﻗﺔ ‪:‬‬
‫وﺳ‬
‫اﻟﻛﻔﺎﺋﺔ = ﻗدرة اﻟﺧرج ‪ /‬ﻗدرة اﻟدﺧل‬

‫ﻗدرة اﻟدﺧل‬ ‫ﻗدرة اﻟﺧرج‬

‫ف‬

‫ﻛﻔﺎﺋﺔ اﻟﺑﺎور‬
‫اﻟﻣ‬

‫ھﻧﺎك ﻣﻌﺎﻣل ﺣﯾز اﻟﺣﻣل ﻟﻠﺧرج اﻟﻣﺗﻌدد اى ﻧﺻﯾب اﻟﻔرع ﻣن اﻟﻘدرة اﻟﻛﻠﯾﺔ ﻟﻠﺧرج ‪:‬‬
‫ﺻ‬

‫= اﻟﻘدرة اﻟﻛﻠﯾﺔ ﻟﻠﺧرج ‪ /‬ﻗدرة اﻟﻔرع‬

‫رى‬

‫وھذا اﻟﻣﻌﺎﻣل = ‪ 1‬ﺑﺎﻟﻧﺳﺑﺔ ﻟﻠﺧرج اﻟﻣﻔرد‬

‫‪ - 2‬ﺗﻌﯾﯾن ﻗﯾﻣﺔ ﻣﻛﺛف اﻟدﺧل ‪:‬‬

‫‪ -‬ﯾﺗم ﺗﻌﯾﯾن ﺳﻌﺔ ﻣﻛﺛف اﻟدﺧل اﻟرﺋﯾﺳﻰ ﺑﺣﺳﺎب ﻣن ‪ 3: 2‬ﻣﯾﻛرو ﻓﺎراد ﻟﻛل واﺣد وات ﻣن ﻗدرة اﻟدﺧل‬
‫اذا ﻛﺎن ﺟﮭد اﻟدﺧل ﯾوﻧﯾﻔرﺳﺎل ‪ 265-85‬ﻓوﻟت‬

‫)‪ 230‬ﻓوﻟت (‬ ‫‪ -‬ﺑﯾﻧﻣﺎ ﯾﺗم ﺣﺳﺎب واﺣد ﻣﯾﻛرو ﻓﻘط ﻟﻛل واﺣد وات اذا ﻛﺎن ﺟﮭد اﻟدﺧل اورﺑﻰ ‪265-195‬‬
 ‫ھﻧﺎك ﻋﻼﻗﺔ ﺗرﺑط ﻗﯾﻣﺔ اﻗل ﺟﮭد ﻣﺳﺗﻣر ﻋﻠﻰ اﻟﻣﻛﺛف ﻣﻊ ﺟﮭد اﻟﺧط اﻟﻣﺗردد ﻣﻊ ﻗدرة اﻟدﺧل ﻣﻊ‬
‫ﺗردد ﺧط اﻟدﺧل ‪ ) :‬ﻻداﻋﻰ ﻟﺣﻔظﮭﺎ ﻻن اﻟﺑرﻧﺎﻣﺞ ﯾﻌطﯾﮭﺎ ﻟك (‬

‫ﻗدرة اﻟدﺧل‬
‫ﻣﻌﺎﻣل اﻟﻣﻛﺛف‬

‫اﻗل ﺟﮭد ﻣﺳﺗﻣر ﻟﻠﻣﻛﺛف‬

‫ﺗردد اﻟﺧط‬
‫اﻗل ﺟﮭد ﺧط ﻣﺗردد‬ ‫ﻣﻛﺛف اﻟﺗﻧﻌﯾم‬

‫اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻟﻠﯾوﻧﯾﻔرﺳﺎل )‪ 370=1.4 x 265 = (265-85‬ﻓوﻟت‬

‫‪/‬‬ ‫م‬
‫اﺣ‬
‫ﯾ‬ ‫ﻣد‬ ‫اﻋﻠﻰ ﻧﻘطﺔ ﻟﺟﮭد اﻟﺧط‬
‫وﺳ‬
‫اﻗل ﻗﯾﻣﺔ ﻟﺟﮭد اﻟﺧط اﻟﻣﺳﺗﻣر‬
‫ف‬

‫زﻣن ﺷﺣن اﻟﻣﻛﺛف‬

‫اﻟﻣ‬

‫زﻣن ﻧﺻف ﻣوﺟﺔ ﺟﮭد اﻟﺧط‬

‫ﻣﻌﺎﻣل اﻟﻣﻛﺛف = زﻣن ﺷﺣن‬

‫ﺻ‬

‫اﻟﻣﻛﺛف ‪ /‬زﻣن اﻟﻧﺻف ﻣوﺟﺔ‬

‫اﻟﺟﮭد اﻟﻣﺳﺗﻣر ﻋﻠﻰ اﻟﻣﻛﺛف ﻣن اﻟﻘﺎﻧون اﻟﻣﻌروف = ﺟﮭد اﻟﺧط اﻟﻣﺗردد ‪( 1.14) .‬‬
‫رى‬

‫‪ - 3‬ﺗﻌﯾﯾن اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل ‪Dmax‬‬

‫‪ -‬اﻟﻔﻼﯾﺑﺎك ﻛوﻧﻔرﺗر ﻟﮫ ﻧظﺎﻣﯾن ﺗﺷﻐﯾل ﻣﻌروﻓﯾن ھﻣﺎ اﻟﻧظﺎم اﻟﻣﺗﺻل ‪ CCM‬واﻟﻧظﺎم‬

‫اﻟﻣﻧﻔﺻل ‪ DCM‬وھو ﺧﺎص ﺑﺻﻔﺎت ﺗﯾﺎر اﻟﻛوﻧﻔرﺗر ﻟﺣظﺔ ﺗوﻗف وﺗﺷﻐﯾل اﻟﻣوﺳﻔت‬
‫اﻣﺎ ان ﯾﻛون ﻣﺗﺻل او ﻣﻧﻔﺻل ﻛﻣﺎ ﻓﻰ اﻟﺷﻛل‬
‫‪ -‬ﺳﻧﺟد اﻧﮫ ﻓﻰ اﻟﻧظﺎم اﻟﻣﻧﻔﺻل ‪ DCM‬ﺗﯾﺎر اﻟداﯾود ﯾﺻل ﻟﻠﺻﻔر ﻗﺑل ﺑدء ﺗﺷﻐﯾل اﻟﻣوﺳﻔت‬
‫ﻟدورة ﺟدﯾدة وھذا اﻟﻧظﺎم ﺟﯾد ﺑﺎﻟﻧﺳﺑﺔ ﻟﻠﺑﺎور اﻟذى ﯾﺣﺗﺎج ﻣﺣول ﺻﻐﯾر اﻟﺣﺟم ﺣﯾث ﻻﯾﺣﺗﺎج‬
‫ﻧظﺎم اﻟﺗﺷﻐﯾل اﻟﻣﻧﻔﺻل اﻟﻰ ﻣﺣول ﻛﺑﯾر ﻟﺗﺧزﯾن اﻟطﺎﻗﺔ ﻛﻣﺎ ﻓﻰ ﺣﺎﻟﺔ اﻟﻧظﺎم اﻟﻣﺗﺻل‬

‫‪ -‬ﻋﺎﻣﺔ ﻧظﺎم ‪ DCM‬ﺗﯾﺎر اﻟﻣوﺳﻔت ﻓﯾﮫ ﯾﻛون ﻋﺎﻟﻰ ﺑﺎﻟﻣﻘﺎرﻧﺔ ﻣﻊ ﻧظﺎم ‪ CCM‬وﻣن ھﻧﺎ‬
‫ﻓﺎﻟﻣﻔﺎﻗﯾد ﻓﻰ اﻟﻘدرة ﻋﺎﻟﯾﺔ ﻓﻰ ﻧظﺎم اﻟﺗﺷﻐﯾل اﻟﻣﻧﻔﺻل ‪DCM‬‬

‫‪ -‬وﻻن اﻟﻔﻘد ﻓﻰ اﻟﻘدرة ﺳﯾﻛون ﻋﺎﻟﻰ ﻟو ﺗم اﺳﺗﺧدام ﻧظﺎم اﻟﺗﺷﻐﯾل اﻟﻣﻧﻔﺻل ﻟذﻟك ﯾوﺻﻰ‬
‫ﺑﺎﺳﺗﺧداﻣﮫ ﻓﻘط ﻓﻰ ﺣﺎﻟﺔ اﻟﺑﺎور ذو اﻟﺗﯾﺎر اﻟﻣﻧﺧﻔض واﻟﺧرج اﻟﻌﺎﻟﻰ اﻣﺎ ﻓﻰ اﻟﺑﺎور اﻟذى‬
‫ﺗﯾﺎره ﻋﺎﻟﻰ وﺧرﺟﮫ ﻣﻧﺧﻔض ﻓﯾﺗم اﺳﺗﺧدام اﻟﻧظﺎم اﻟﻣﺗﺻل ‪CCM‬‬

‫م‬
‫ﻻﺣظ ھﻧﺎ ان اﻟﻛوﻧﻔرﺗر ﯾﻌﻣل ﻋﻠﻰ ﺣدود اﻟوﺿﻊ ﺑﯾن اﻻﺗﺻﺎل واﻻﻧﻔﺻﺎل ﺑﻣﻌﻧﻰ ان ﻣوﺟﺔ ﺗﯾﺎر اﻟداﯾود او اﻟﻣوﺳﻔت ﻓﻰ ﺣﺎﻟﺔ‬
‫‪ CCM‬اﻟﻌﺎدﯾﺔ ﻻﺗﺻل اﻟﻰ اﻟﺻﻔر وﻟﻛﻧﮫ ھﻧﺎ اوﺻﻠﮭﺎ اﻟﻣﺻﻣم اﻟﻰ اﻟﺻﻔر ﺑﻌد ﺑدء اﻟﻣوﺟﺔ اﻟﺟدﯾدة ﻟﻠﻣوﺳﻔت وھﻰ ﺗﺳﻣﻰ‬

‫‪/‬‬
‫ﺣﺎﻟﺔ اﻟﺣدود ﺑﯾن اﻟﻧظﺎﻣﯾن اﻟﻣﺗﺻل واﻟﻣﻧﻔﺻل ﺣﯾث ﯾﺳﺗطﯾﻊ اﻟﻛوﻧﻔرﺗر اﻟﻌﻣل ﺗﺣت اﻗل ﺟﮭد ﻟﻠدﺧل وﯾﻌطﻰ اﻋﻠﻰ ﺗﯾﺎر وﺑذﻟك‬
‫ﯾﻘﻠل اﻟﻔﻘد ﻓﻰ اﻟﻘدرة ﻋﻠﻰ اﻟﻣوﺳﻔت‬

‫اﺣ‬
‫ﺣﺎﻟﺔ اﻟﺗﺷﻐﯾل اﻟﺣرﺟﺔ‬
‫اﻟﻣﺻﻣم ﺳﻣﺎه ﻧظﺎم‬
‫ﻣﺗﺻل ‪ CCM‬وﻟﻛن‬
‫ﯾ‬ ‫ﻣد‬ ‫ﻓﻰ اﻟواﻗﻊ ھو ﯾﺳﻣﻰ‬
‫اﻟﻧظﺎم اﻟﺣرج‬
‫وﺳ‬
‫زﻣن اﻟﺗﺷﻐﯾل اﻟﻣوﺳﻔت‬

‫زﻣن اﻟﺗوﻗف ﻟﻠﻣوﺳﻔت = زﻣن ﺗﺷﻐﯾل‬

‫اﻟداﯾود‬
‫ف‬

‫ﻣوﺟﺔ ﺗﯾﺎر اﻻﺑﺗداﺋﻰ واﻟﺛﺎﻧوى ﻟﻠﻧظﺎم اﻟﺣرج‬

‫اﻟﻣ‬

‫ﺗﯾﺎر اﻟﻣوﺳﻔت او اﻻﺑﺗداﺋﻰ‬ ‫ﺗﯾﺎر داﯾود اﻟﺧرج او اﻟﺛﺎﻧوى‬

‫ﺻ‬
‫رى‬

‫زﻣن ﺗﺷﻐﯾل اﻟداﯾود‬ ‫اﻟزﻣن اﻟﻣﯾت‬

‫اﻟزﻣن اﻟﻛﻠﻰ‬
‫ﻣوﺟﺔ ﺗﯾﺎر اﻻﺑﺗداﺋﻰ واﻟﺛﺎﻧوى ﻟﻠﻧظﺎم اﻟﻣﻧﻔﺻل ‪DCM‬‬

‫ﻓﻰ ھذا اﻟﺗﺻﻣﯾم ﻟم ﯾﻘم اﻟﻣﺻﻣم ﺑﺎﺳﺗﺧدام ﻧظﺎم ‪ CCM‬ﻛﺎﻣل وﻟﻛﻧﮫ ﺗﺣﺎﯾل وﺟﻌل ﻧظﺎم ‪ CCM‬ﻗرﯾب اﻟﺷﺑﮫ اﻟﻰ اﻟﻧظﺎم‬
‫اﻟﻣﻧﻔﺻل ‪ DCM‬ﺣﯾث ﻣن اﻟﻣﻔروض اﻻ ﯾﻧزل ﺗﯾﺎر اﻟﻣوﺳﻔت او ﺗﯾﺎر اﻟداﯾود اﻟﻰ اﻟﺻﻔر ﻛﻣﺎ ھو اﻟﺣﺎل ﻓﻰ ﺣﺎﻟﺔ ‪DCM‬‬
‫وﻟﻛﻧﮫ ﻗﺎم ﺑذﻟك ﺣﺗﻰ ﯾﺧﻔض اﻟﻣﻔﺎﻗﯾد ﻋﻠﻰ اﻟﻣوﺳﻔت وﻟﯾﺟﻌل اﻟﻌﻼﻗﺔ ﺑﯾن ﺟﮭد اﻟﺧرج وﺟﮭد اﻟدﺧل ﺗﻌﺗﻣد ﻓﻘط ﻋﻠﻰ‬
‫اﻟدﯾوﺗﻰ ﺳﯾﻛل ﻛﻣﺎ ھو اﻟﺣﺎل ﻓﻰ ‪ CCM‬ﻻن ﺗﻠك اﻟﻌﻼﻗﺔ ﻓﻰ ‪ DCM‬ﺗﻌﺗﻣد اﯾﺿﺎ ﻣﻊ اﻟدﯾوﺗﻰ ﺳﯾﻛل ﻋﻠﻰ اﻟﺣﻣل ﻣﻣﺎ‬
‫ﯾﺟﻌل ﻋﻣﻠﯾﺔ اﻟﺗﺻﻣﯾم ﻣﻌﻘدة ﻓﺎراد ان ﯾﺑﺳطﮭﺎ ﺑﺣﯾث ﯾﻌﺗﻣد ﻓﻘط ﻋﻠﻰ اﻟدﯾوﺗﻰ ﺳﯾﻛل وﻓﻰ ﻧﻔس اﻟوﻗت ﯾﺣﺻل ﻋﻠﻰ ﺗﯾﺎر‬
‫ﺧرج ﻋﺎﻟﻰ وھذا ﻣﺎﺟﻌﻠﮫ ﯾﻌﻣل ﻋﻠﻰ ﻧظﺎم ‪ CCM‬وﻟﻛن ﺑﺎﻟﻘرب ﻣن ﺣدود ‪DCM‬‬
 ‫ﻣﺣول اﻟﺑﺎور‬

‫ﺟﮭد اﻟﺧرج اﻟﻣﻧﻌﻛس‬

‫ﻣﻛﺛف اﻟﺗﻧﻌﯾم اﻟرﺋﯾﺳﻰ‬

‫اﻟدرﯾن‬
‫اﻟﺟﮭد ﻋﻠﻰ اﻟﻣوﺳﻔت‬
‫اﻟﻣوﺳﻔت‬

‫اﻟﺳورس‬

‫م‬
‫اﯾﺳﻰ اﻟﺑﺎور‬
‫ﺟﮭد اﻟﺷﺎرز‬

‫‪/‬‬
‫اﺣ‬
‫ﺟﮭد اﻟﺛﺎﻧوى اﻟﻣرﺗد اﺛﻧﺎء‬
‫اﺷﺗﻐﺎل اﻟداﯾود‬

‫اﻟﺟﮭد ﻋﻠﻰ ﻣﻛﺛف اﻟﻣدﺧل‬

‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫اﻟﻣوﺟﺔ اﻟﻣرﺑﻌﺔ ﻟﻠﺟﮭد ﻋﻠﻰ اﻟﻣوﺳﻔت‬
‫ف‬

‫ﻛﻣﺎ ﻧﻼﺣظ ﻓﻰ اﻟرﺳم اﺛﻧﺎء ﺗوﻗف اﻟﻣوﺳﻔت ﯾﺻﺑﺢ ھﻧﺎك ﺟﮭد ﻋﻛﺳﻰ ﻋﻠﻰ اﻟﺛﺎﻧوى ﯾوﻟد ﺗﯾﺎر ﻋﻠﻰ‬
‫داﯾود اﻟﺧرج ﯾرﺗد ﻋﻠﻰ اﻻﺑﺗداﺋﻰ ﺣﺳب ﻗﺎﻧون اﻟﺟﮭد ﻟﻠﻣﺣوﻻت اﻟذى ﯾرﺗﺑط ﺑﻧﺳﺑﺔ ﻋدد اﻟﻠﻔﺎت‬
‫اﻟﻣ‬

‫ﯾﺳﻣﻰ ھذا اﻟﺟﮭد اﻟﻣرﺗد ﻛﻣﺎ ﻓﻰ اﻟرﺳم ‪VRO‬‬

‫ﺻ‬

‫اﻟﺟﮭد اﻟواﻗﻊ ﻋﻠﻰ درﯾن اﻟﻣوﺳﻔت ﻟﺣظﺔ اﻟﺗوﻗف = ﺟﮭد اﻟﻣﻛﺛف ‪ +‬اﻟﺟﮭد اﻟﻣرﺗد ‪ +‬ﺟﮭد اﻟﺷﺎرز )ﻣن اﻟﻣﺣﺎﺛﺔ اﻟﺷﺎردة (‬
‫رى‬

‫ﻟو اردﻧﺎ ﺣﺳﺎب اﻟﺟﮭد اﻟذى ﯾﺿﻐط ﻋﻠﻰ اﻟﻣوﺳﻔت ﻟﺣظﺔ ﺗﺷﻐﯾﻠﮫ ﻟﻛﻰ ﻧﺧﺗﺎر ﻧوع اﻟﻣوﺳﻔت ﺣﺳب اﻟﺟﮭد‬
‫ﺳﯾﻛون ﻣﺟﻣوع اﻟﺛﻼث ﺟﮭود‬
‫ﻣن اﻟﻣﻌﺎدﻟﺔ ‪ 5‬ﺳﻧرى ان ﺟﮭد اﻟﺧرج اﻟﻣرﺗد ﯾﻌﺗﻣد ﻋﻠﻰ اﻟدﯾوﺗﻰ ﺳﯾﻛل واﻟﺟﮭد ﻋﻠﻰ اﻟﻣﻛﺛف وﺑﻌد‬
‫ﺣﺳﺎﺑﮫ ﯾﻣﻛﻧﻧﺎ اﻟوﺻول ﻟﻠﺟﮭد اﻟواﻗﻊ ﻋﻠﻰ درﯾن اﻟﻣوﺳﻔت ﻓﻰ اﻟﻣﻌﺎدﻟﺔ ‪ 6‬ﻛﻣﺎ ذﻛرﻧﺎ‬

‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬

‫اﻗل ﺟﮭد ﻟﻠﻣﻛﺛف‬

‫ﺟﮭد اﻟﺧرج اﻟﻣﻧﻌﻛس‬ ‫ﻣﺳﺗﻧﺗﺞ ﻣن اﻟﻘﺎﻧون اﻟﻌﺎدى‬

‫ﻟﻠﻔﻼﯾﺑﺎك اﻟذى ﯾرﺑط ﻋﻼﻗﺔ ﺟﮭد‬
‫اﻟﺧرج ﺑﺟﮭد اﻟدﺧل‬
‫‪D‬‬
‫اﻟﺟﮭد ﻋﻠﻰ اﻟﻣوﺳﻔت‬ ‫‪Vo = Vin x N‬‬
‫‪1 -D‬‬
‫‪Vo‬‬ ‫ﺣﯾث ‪:‬‬
‫اﻟﺟﮭد ﻋﻠﻰ اﻟﻣوﺳﻔت اﺛﻧﺎء اﻟﺗوﻗف ﺑدون ﺣﺳﺎب ﺟﮭد اﻟﺷﺎرز وﻟذﻟك ﺳﻣﺎه ‪ nom‬اى‬ ‫= ‪VRO‬‬
‫اﻟﻌﺎدى وﺑﺎﺿﺎﻓﺔ ﺟﮭد اﻟﺷﺎرز ﯾﺻﺑﺢ اﻗﺻﻰ ﺟﮭد ‪Vmax‬‬ ‫‪N‬‬
 ‫‪ -‬ﻣن اﻟﻣﻌﺎدﻟﺔ ‪ 5‬ﻻﺣظ ان اﻟﺟﮭد اﻟﻣرﺗد ﻣرﺗﺑط ﺑﺎﻟدﯾوﺗﻰ ﺳﯾﻛل وﻛﻠﻣﺎ ﻗﻠت اﻟدﯾوﺗﻰ ﺳﯾﻛل ﻗل اﻟﺟﮭد اﻟﻣرﺗد ﻻﻧﮫ طﺑﯾﻌﻰ‬
‫ان ﺟﮭد اﻟﺧرج ﯾﻘل ﻣﻊ ﺗﺷﻐﯾل اﻟﻣوﺳﻔت ﻓﺗرات ﻗﻠﯾﻠﺔ ‪ -‬ﻟذﻟك ﻣن ﺧﻼل اﻟﻣﻌﺎدﻟﺔ ‪ 6‬اذا اردﻧﺎ ان ﻧﺧﻔض اﻟﺟﮭد اﻟﺿﺎﻏط‬
‫ﻋﻠﻰ درﯾن اﻟﻣوﺳﻔت ﻧﻘوم ﺑﺧﻔض اﻟﺟﮭد اﻟﻣرﺗد اى ﺧﻔض اﻟدﯾوﺗﻰ ﺳﯾﻛل)راﺟﻊ ﺟدول ﺗﺣدﯾد اﻟﺟﮭد اﻟﻣرﺗد ﺣﺳب ﺟﮭد اﻟدﺧل(‬

‫‪ -‬ﻓﻰ اﻟﻌﺎدة ﯾوﺻﻰ اﻟﻣﺻﻣم ﺑﺎن ﻧﺟﻌل اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل ﻟﻣوﺳﻔت ‪ 650‬ﻓوﻟت ﺗﻛون ﺑﯾن ‪0.45‬‬
‫و ‪ 0.50‬ﻋﻧدﻣﺎ ﯾﻛون ﺟﮭد اﻟدﺧل ﯾوﻧﯾﻔرﺳﺎل‬
‫وذﻟك ﻻن اﻟﻛوﻧﻔرﺗر ﻋﻧدﻣﺎ ﯾﻌﻣل ﺑﻧظﺎم ‪ CCM‬وﻣﻊ دﯾوﺗﻰ ﺳﯾﻛل اﻛﺛر ﻣن ‪ 0.5‬ﻓﺎﻧﮫ ﺗﻧﺗﺞ ﺗرددات‬
‫ﻣﺻﺎﺣﺑﺔ ﻟﺗرددات اﻟﻣذﺑذب ﺗﺳﺑب اﺿطراب ﻓﻰ ﻋﻣل داﺋرة اﻟﻛﻧﺗرول ﻟذﻟك ﯾﺗم اﻟﺗوﺻﯾﺔ ﺑﺗﺷﻐﯾل‬
‫اﻟﻛوﻧﻔرﺗر ﺑدﯾوﺗﻰ ﺳﯾﻛل اﻗل ﻣن ‪0.5‬‬

‫م‬
‫‪ - 4‬ﺗﻌﯾﯾن ﻣﺣﺎﺛﺔ اﻟﻣﻠف اﻻﺑﺗداﺋﻰ ﻟﻠﻣﺣول‬

‫‪/‬‬
‫ﺗدﺧل اﻟﻣﺣﺎﺛﺔ ﻓﻰ ﺗﻌﯾﯾن اﻗﺻﻰ ﻛﺛﺎﻓﺔ ﻓﯾض ﻟﻠﻘﻠب وﻓﻰ ﺗﺣدﯾد ﻋدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ‬

‫اﺣ‬
‫ﻛﻣﺎ راﯾﻧﺎ ھﻧﺎك اﺧﺗﻼف ﻓﻰ ظروف اﻟﺗﺷﻐﯾل ﺑﯾن اﻟﻧظﺎﻣﯾن ‪ CCM , DCM‬ﻣن ﺣﯾث ﺟﮭود اﻟﺗﺷﻐﯾل واﻟﺣﻣل‬
‫وﻟﻛﻰ ﻧﻘوم ﺑﺣﺳﺎب ﻗﯾﻣﺔ ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ اﻟﺗﻰ ﺗﻼﺋم ﻛل ﻣن اﻟﻧظﺎﻣﯾن ﺳﻧﻔﺗرض ان اﻟﺑﺎور ﯾﻌﻣل ﻋﻧد اﻗﺻﻰ ﺣﻣل‬

‫ﻣد‬
‫وﻋﻧد اﻗل ﺟﮭد دﺧل وﻧرﯾد ان ﻧﻌﯾن ﻗﯾﻣﺔ اﻟﻣﺣﺎﺛﺔ اﻟﺗﻰ ﺗﺟﻌﻠﮫ ﯾﻌﻣل ﻋﻧد ﺗﻠك اﻟظروف اﻟﺳﯾﺋﺔ‬

‫ﯾﺗم ﺗﻌﯾﯾن اﻟﻣﺣﺎﺛﺔ ﻟﻠﻣﻠف اﻻﺑﺗداﺋﻰ ﺑﺗطﺑﯾق ﻗﺎﻧون ﻓﺎرادى ﻟﻠﺟﮭد اﻟﻣﺗوﻟد ﻋﻠﻰ اﻟﻣﻠف اﻻﺑﺗداﺋﻰ واﻟﻣﻌروف‬
‫ﯾ‬
‫وﺳ‬
‫ﺳﻧﺟد ان اﻟﻣﺣﺎﺛﺔ ‪= L‬‬ ‫واﻟزﻣن ھو زﻣن اﻟﺗﺷﻐﯾل ‪ton = T*D‬‬ ‫وﺑﺎﻟﺗﻌوﯾض ﻋن اﻟﺗﯾﺎر ‪I‬‬
‫ﺣﯾث ‪ T =1/F‬واﯾﺿﺎ ﺗﯾﺎر اﻟرﯾﺑل = ﻣﻌﺎﻣل اﻟرﯾﺑل ‪ 2 /‬اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﺗﯾﺎر اﻻﺑﺗداﺋﻰ‬
‫ف‬

‫اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﺗﯾﺎر اﻻﺑﺗداﺋﻰ = ﻗدرة اﻟدﺧل ‪ /‬اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﻠﺟﮭد اﻟﻣﺳﻠط ﻋﻠﻰ اﻻﺑﺗداﺋﻰ‬

‫اﻗل ﺟﮭد ﻣﺳﺗﻣر‬ ‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬ ‫= ‪Vmin * Dmax / Pin‬‬

‫ﻣﻌروف ان اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﻠﻣوﺟﺔ اﻟﻣرﺑﻌﺔ = ﻗﯾﻣﺔ اﻟﺟﮭد * اﻟدﯾوﺗﻰ ﺳﯾﻛل‬

‫اﻟﻣ‬

‫ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ‬ ‫ﺑﺎﻟﺗﻌوﯾض ﺳﻧﺻل اﻟﻰ اﻟﻘﺎﻧون اﻟﻌﺎم ﻟﻠﻣﺣﺎﺛﺔ اﻟذى ﯾرﺑطﮭﺎ ﺑﺎﻗل ﺟﮭد‬
‫ﻣﻌﺎﻣل اﻟرﯾﺑل‬
‫دﺧل واﻟدﯾوﺗﻰ ﺳﯾﻛل وﻗدرة اﻟدﺧل وﺗردد اﻟﺗﻘطﯾﻊ وﻣﻌﺎﻣل اﻟرﯾﺑل‬
‫ﺻ‬

‫ﻗدرة اﻟدﺧل‬ ‫ﺗردد اﻟﺗﻘطﯾﻊ‬

‫اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﺗﯾﺎر اﻟﻣوﺳﻔت‬

‫رى‬

‫اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﺗﯾﺎر اﻟﻣوﺳﻔت‬

‫ﻋﻧد اﺳﺗﺧدام ﻧظﺎم ‪CCM‬‬

‫ﺗﯾﺎر اﻟرﯾﺑل‬
‫ﯾﺗم اﻟﺗوﺻﯾﺔ ﺑﺟﻌل ﻣﻌﺎل اﻟرﯾﺑل ﻟﻠﺗﯾﺎر ‪= KRF‬‬
‫ﻣن ‪ 0.25‬اﻟﻰ ‪ 0.5‬ﻟﻠﻧظﺎم اﻟﯾوﻧﯾﻔرﺳﺎل وﻣن‬
‫‪ 0.8: 0.4‬ﻟﻠﻧظﺎم اﻻورﺑﻰ‬ ‫ﻻﺣظ ان اﻟﻣوﺳﻔت ﯾﺑدا اﻟﺗﺷﻐﯾل وھﻧﺎك‬ ‫ﺗﺷﻐﯾل‬ ‫ﺗﺷﻐﯾل‬
‫ﻗﯾﻣﺔ ﻟﻠﺗﯾﺎر اى ﻻﯾﺑدأ ﻣن اﻟﺻﻔر وذﻟك‬
‫ﻟوﺟود ﺑﻘﺎﯾﺎ طﺎﻗﺔ ﻣﻐﻧﺎطﯾﺳﯾﺔ ﻓﻰ اﻟﻘﻠب‬ ‫‪0‬‬
‫ﻣﻌﺎﻣل اﻟرﯾﺑل اﻗل ﻣن ‪1‬‬

‫ﻣﻌﺎﻣل اﻟرﯾﺑل = ﺗﯾﺎر اﻟرﯾﺑل ‪ 2 /‬ﻓﻰ اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﺗﯾﺎر اﻻﺑﺗداﺋﻰ‬

‫ﻓﻰ اﻟﻧظﺎم اﻟﻣﻧﻔﺻل ﺗﻼﺣظ ان ﺗﯾﺎر‬

‫اﻟﻣوﺳﻔت ﻛﺑﯾر ﻋن اﻟﻧظﺎم اﻟﻣﺗﺻل‬

‫ﻋﻧد ﺗﺷﻐﯾل اﻟﻣوﺳﻔت ﺗﯾﺎره ﯾﺑدا ﻣن اﻟﻘﯾﻣﺔ‬ ‫ﺗﺷﻐﯾل‬

‫ﺗﺷﻐﯾل‬
‫‪ 0‬وذﻟك ﻟﻌدم وﺟود اى طﺎﻗﺔ ﻣﺧزﻧﺔ ﻓﻰ‬
‫اﻟﻘﻠب ﻟﺣظﺔ اﻟﺗﺷﻐﯾل‬
‫‪0‬‬
‫ﻧظﺎم اﻟﺗﺷﻐﯾل اﻟﻣﻧﻔﺻل‬ ‫ﻣﻌﺎﻣل اﻟرﯾﺑل = ‪1‬‬
 ‫ﺑﻌد ﺗﺣدﯾد اﻟﻣﺣﺎﺛﺔ ﯾﺗم ﺗﻌﯾﯾن ﻗﯾﻣﺔ اﻗﺻﻰ ﺗﯾﺎر ﻟﻼﺑﺗداﺋﻰ واﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻣن ﺧﻼل اﻟﻌﻼﻗﺎت‬
‫اﻟﺗﺎﻟﯾﺔ ‪:‬‬

‫ﺷﺎھد اﻟرﺳم ﻓﻰ اﻟﺻﻔﺣﺔ اﻟﺳﺎﺑﻘﺔ‬

‫اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت ) اﻗﺻﻰ ﺗﯾﺎر اﺑﺗداﺋﻰ (‬

‫ﺗﯾﺎر ‪ RMS‬ﻟﻠﻣوﺳﻔت‬

‫اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﺗﯾﺎر اﻟﻣوﺳﻔت‬ ‫ﻗدرة اﻟدﺧل‬ ‫ﻗدرة اﻟدﺧل‬

‫=‬

‫م‬
‫اﻟﻘﯾﻣﺔ اﻟﻣﺗوﺳطﺔ ﻟﻠﻣوﺟﺔ اﻟﻣرﺑﻌﺔ ﻟﻠدﺧل‬
‫اﻟدﯾوﺗﻰ ﺳﯾﻛل‬
‫اﻗل ﺟﮭد دﺧل ﻣﺳﺗﻣر‬
‫ﻣن ﻗﺎﻧون ﻓﺎراداى‬

‫‪/‬‬
‫ﺗﯾﺎر اﻟرﯾﺑل‬

‫اﺣ‬
‫اﻟﻣﺣﺎﺛﺔ‬ ‫اﻟﺗردد‬

‫ﯾ‬ ‫ﻣد‬
‫ﻣﻠﺣوظﺔ ‪ :‬ﯾﻌﻣل اﻟﻛوﻧﻔرﺗر ﺑﻧظﺎم ‪ CCM‬ﻋﻧد اﻗل ﺟﮭد دﺧل واﻋﻠﻰ ﺣﻣل وﻟﻛن ﻟو زاد ﺟﮭد اﻟدﺧل رﺑﻣﺎ ﯾدﺧل‬
‫اﻟﻛوﻧﻔرﺗر ﻓﻰ ﺣﺎﻟﺔ ‪DCM‬‬
‫وﺳ‬
‫‪ -‬اﻗﺻﻰ ﺟﮭد دﺧل ﯾظل اﻟﻛوﻧﻔرﺗر ﯾﻌﻣل ﺧﻼﻟﮫ ﺑﻧظﺎم ‪ CCM‬ﯾﺣﺳب ﻣن اﻟﻌﻼﻗﺔ اﻟﺗﺎﻟﯾﺔ‬
‫ف‬

‫اﻗﺻﻰ ﺟﮭد دﺧل‬

‫اﻟﻣ‬

‫ﺟﮭد اﻟﺧرج اﻟﻣﻧﻌﻛس‬

‫ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ‬ ‫ﻗدرة اﻟدﺧل‬

‫ﺗردد اﻟﺗﻘطﯾﻊ‬
‫ﺻ‬

‫ﻣن اﻟﻌﻼﻗﺔ اﻟﺳﺎﺑﻘﺔ ﻧﻼﺣظ ﺗدﺧل اﻟﺗردد واﻟﻣﺣﺎﺛﺔ واﻟﺟﮭد اﻟﻣرﺗد ﻓﻰ ﺗﺣدﯾد ﻧوﻋﯾﺔ ﻧظﺎم اﻟﺗﺷﻐﯾل‬
‫رى‬

‫‪ -5‬اﺧﺗﯾﺎر اﻟﻣوﺳﻔت ‪:‬‬

‫ﻣن اﻟﻣﻌﺎدﻟﺔ ‪ 8‬ﺗم ﺗﻌﯾﯾن اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﺗﯾﺎر اﻟﻣوﺳﻔت وﺑﺎﺿﺎﻓﺔ ﻋﺎﻣل اﻣﺎن ﯾﺗم زﯾﺎدة اﻟﻘﯾﻣﺔ‬
‫ﺑﺣواﻟﻰ ‪ 12‬ﻓﻰ اﻟﻣﯾﺔ وﻓﻰ اﻟﻌﻣوم ﻣﻌظم اﻟﻣﺻﻣﻣﯾن ﯾﺟﻌﻠوھﺎ ‪ 50‬ﻓﻰ اﻟﻣﯾﺔ اﻣﺎن اى ﺳﯾﺧﺗﺎر‬
‫ﻣوﺳﻔت ﺗﯾﺎره ﺿﻌف ﺗﯾﺎر اﻟﻘﯾﻣﺔ اﻟﺧﺎرﺟﺔ ﻣن اﻟﻣﻌﺎدﻟﺔ ‪8‬‬
 ‫‪ - 6‬اﺧﺗﯾﺎر ﻗﻠب اﻟﻣﺣول اﻟﻔرارﯾت اﻟﻣﻧﺎﺳب واﻗل ﻋدد ﻟﻔﺎت ﻟﻼﺑﺗداﺋﻰ ‪:‬‬

‫ﻓﻰ اﻟﺟدول ‪ 1‬ﯾﺑدا اﺧﺗﯾﺎر ﺣﺟم اﻟﻘﻠب ﻋن ﺗﺻﻣﯾم ﺑﺎور ﯾوﻧﯾﻔرﺳﺎل ﻋﻧد ﺗردد ‪ 67‬ﻛﯾﻠو وﺧرج‬
‫واﺣد وﻋﻧدﻣﺎ ﯾﻛون ﺟﮭد اﻟدﺧل اورﺑﻰ ‪ 265: 195‬ﻓﺎن ﺗردد اﻟﺗﻘطﯾﻊ ﯾزﯾد ﻋن ‪ 67‬ﻛﯾﻠو وﯾﻘل‬
‫ﺣﺟم اﻟﻘﻠب ﻗﻠﯾﻼ اﻣﺎ ﺑﺎﻟﻧﺳﺑﺔ ﻟﻠﺗطﺑﯾﻘﺎت اﻟﺗﻰ ﻟﮭﺎ اﻛﺛر ﻣن ﺧرج ﻓﯾﺻﺑﺢ ﺣﺟم اﻟﻘﻠب اﻛﺑر ﻣن اﻟﺗﻰ‬
‫ﻓﻰ اﻟﺟدول‬
‫ﺑﻌد اﺧﺗﯾﺎر اﻟﻘﻠب ﻣن اﻟﺟدول ﺣﺳب اﻟﻘدرة وﻣن اﻟداﺗﺎﺷﯾت ﻟﻠﻘﻠب‬
‫ﺳﯾﺗم ﺣﺳﺎب اﻗل ﻋدد ﻣن اﻟﻠﻔﺎت ﯾﺣدث ﻋﻧدھﺎ اﻟﺗﺷﺑﻊ ﻣن ﺧﻼل‬
‫اﻟﻌﻼﻗﺔ اﻟﻘدﯾﻣﺔ ﻟﻘﺎﻧون ﻓﺎراداى‪:‬‬

‫ﺳﺗﺟد ﻓﻰ اﻟﻧﮭﺎﯾﺔ ‪ :‬اﻟﻣﺣﺎﺛﺔ ‪ x‬اﻟﺗﯾﺎر = ﻋدد اﻟﻠﻔﺎت ‪x‬اﻟﻔﯾض‬

‫م‬
‫اﻟﺗﯾﺎر ھو اﻋﻠﻰ ﻗﯾﻣﺔ ﻟﺗﯾﺎر اﻟﻣوﺳﻔت ‪ .....‬واﻟﻔﯾض = ﻛﺛﺎﻓﺔ اﻟﻔﯾض ‪ x‬ﻣﺳﺎﺣﺔ ﻣﻘطﻊ اﻟﻘﻠب‬

‫وﻋﻠﯾﮫ ﺳﯾﻛون ﻗﺎﻧون ﺣﺳﺎب اﻗل ﻋدد ﻟﻔﺎت ﻟﻼﺑﺗداﺋﻰ ﻻﺗﺳﺑب ﺗﺷﺑﻊ اﻟﻘﻠب ھو ‪:‬‬

‫‪/‬‬
‫ﻋدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ‬

‫اﺣ‬
‫اﻟﻣﺣﺎﺛﺔ ﻟﻼﺑﺗداﺋﻰ‬
‫اﻋﻠﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻘت‬
‫ﻻﺣظ ارﺗﺑﺎط ﻋدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ ﺑﺎﻟﻣﺣﺎﺛﺔ وﺗﯾﺎر اﻟﻣوﺳﻔت‬
‫وﻛﺛﺎﻓﺔ اﻟﻔﯾض وﻣﺳﺎﺣﺔ اﻟﻣﻘطﻊ وﻻﺣظ ﻛﻠﻣﺎ زادت ﻋدد‬

‫ﻛﺛﺎﻓﺔ اﻟﺗﺷﺑﻊ ﻟﻠﻔﯾض‬

‫ﻣﺳﺎﺣﺔ ﻣﻘطﻊ اﻟﻘﻠب‬
‫ﯾ‬ ‫ﻣد‬ ‫اﻟﻠﻔﺎت ﻗﻠت ﻛﺛﺎﻓﺔ اﻟﻔﯾض‬

‫ﻟﺗﺧﻔﯾض ﻋدد اﻟﻠﻔﺎت ﻟﺻﻐر ﺣﺟم اﻟﻘﻠب ﻗم ﺑﺗﺻﻐﯾر ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ‬

‫وﺳ‬
‫ﻓﻰ ﺣﺎﻟﺔ اﺳﺗﺧدام ﺟﮭد اﻟدﺧل اﻟﯾوﻧﯾﻔرﺳﺎل ﯾﺗم اﻋﺗﺑﺎر ﻛﺛﺎﻓﺔ اﻟﻔﯾض ﻟﻠﺗﺷﺑﻊ ﺑﯾن ‪ 0.35 : 0.3‬ﺗﺳﻼ‬
‫ف‬

‫ﻣﺳﺎﺣﺔ ﺷﺑﺎك اﻟﻣﻠﻔﺎت‬

‫اﻟﻣ‬
‫ﺻ‬
‫رى‬

‫ﻣﺳﺎﺣﺔ ﻣﻘطﻊ اﻟﻘﻠب‬

‫ﺟدول ﺳرﯾﻊ ﻻﺧﺗﯾﺎر ﻧوع اﻟﻘﻠب ﺣﺳب اﻟﻘدرة ﻓﻰ ﺣﺎﻟﺔ‬

‫اﻟﺟﮭد اﻟﯾوﻧﯾﻔرﺳﺎل وﺗردد‪ 67‬ﻛﯾﻠو وﺧرج واﺣد‬

‫ﻣﻠﺣوظﺔ ‪ :‬ھﻧﺎك ﺟدول اﺧر ﻛﺑﯾر ﻟﺗﺣدﯾد اﻟﻘﻠب ﺣﺳب اﻟﻘدرة ﻋﻧد ﺗرددات ﻣﺧﺗﻠﻔﺔ ﺗﺟده ﻓﻰ‬
‫ﻣﻠﻔﺎت ﺳﺎﺑﻘﺔ‬
 ‫‪APPLICATION NOTE‬‬ ‫‪AN4137‬‬

‫‪ - 7‬ﺗﻌﯾﯾن ﻋدد اﻟﻠﻔﺎت ﻟﻛل ﻣﻠف ﻣن ﻣﻠﻔﺎت اﻟﺧرج ‪:‬‬

‫ﻣﻠف اﻻﺑﺗداﺋﻰ‬
‫ﻣن اﻟﺷﻛل اﻟﻣﻠف اﻟﺛﺎﻧوى اﻟﺳﻔﻠﻰ ھو اﻟذى ﺳﯾﺎﺧذ ﻣﻧﮫ ﺧط اﻟﻔﯾدﺑﺎك‬
‫ﻟﺗﺣﺳس ﺟﮭد اﻟﺧرج وﻋﻼﻗﺔ اى ﻣﻠف ﺛﺎﻧوى ﻣﻊ اﻟﻣﻠف اﻻﺑﺗداﺋﻰ ﺗﻛون‬
‫ﻣن ﺧﻼل اﻟﻘﺎﻧون اﻟﻣﻌروف ﻻى ﻣﺣول ھﻰ ﻋﻼﻗﺔ ﻧﺳﺑﺔ اﻟﻠﻔﺎت اﻟﻰ‬
‫ﺟﮭد اﻟﺧرج ‪n‬‬
‫ﻧﺳﺑﺔ اﻟﺟﮭود ‪:‬‬
‫ﻣﻠف اﻟﺛﺎﻧوى‪n‬‬
‫اﻟﺟﮭد اﻟﻣﻧﻌﻛس ﻋﻠﻰ اﻻﺑﺗداﺋﻰ‬

‫م‬
‫ﻟﺣظﺔ ﺗوﻗف اﻟﻣوﺳﻔت‬

‫‪/‬‬
‫ﺟﮭد اﻟﺧرج ‪1‬‬ ‫‪14‬‬

‫اﺣ‬
‫ﺟﮭد اﻟداﯾود‬
‫ﺟﮭد اﻟﺛﺎﻧوى‬
‫ﻣﻠف اﻟﺗﺷﻐﯾل‬ ‫ﻣﻠف اﻟﺛﺎﻧوى ‪1‬‬

‫ﻣد‬
‫ﯾﺟب ان ﺗﻼﺣظ اﻧﮫ ﯾﺣﺳب ﻧﺳﺑﺔ ﻋدد اﻟﻠﻔﺎت ﻛﻌﻼﻗﺔ ﺑﯾن ﺟﮭدى اﻟﺛﺎﻧوى واﻻﺑﺗداﺋﻰ وان ﺟﮭد اﻻﺑﺗداﺋﻰ ھو اﻟﺟﮭد‬
‫اﻟواﻗﻊ ﻋﻠﻰ ﻣﻠﻔﺎت اﻻﺑﺗداﺋﻰ ﻟﺣظﺔ ﻣرور اﻟﺗﯾﺎر ﻓﻰ اﻟﺛﺎﻧوى وﻟﯾس ﺟﮭد اﻟدﺧل ﻟﻠﺧط ﻻن ﺟﮭد اﻟدﺧل ﻻﺗﺎﺛﯾر ﻟﮫ ﻓﻰ ھذه‬
‫ﯾ‬
‫اﻟﺣﺎﻟﺔ ﻧظرا ﻟﺗوﻗف ﺗﯾﺎر اﻻﺑﺗداﺋﻰ اﻟﻘﺎدم ﻣن اﻟﻣدﺧل‬
‫وﺳ‬
‫ﻋﻧد اﺧﺗﯾﺎر ﻗﯾﻣﺔ ﻟﻌدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ ﻓﻰ اﻟﻌﻼﻗﺔ ‪ 14‬ﯾﺟب ان ﺗﻛون اﻛﺑر ﻣن اﻟﻘﯾﻣﺔ اﻟﺗﻰ اﺳﺗﻧﺗﺟﻧﺎھﺎ ﻓﻰ اﻟﻣﻌﺎدﻟﺔ‬
‫‪ 13‬ﻧظرا ﻻﻧﻧﺎ ﻛﻧﺎ ﻧﺣﺳب اﻗل ﻗﯾﻣﺔ ﻟﻣﻠﻔﺎت اﻻﺑﺗداﺋﻰ‬
‫ف‬

‫ﻟﺣﺳﺎب ﻋدد ﻟﻔﺎت اى ﺧرج رﻗﻣﮫ ‪ 2‬او ‪ 3‬او ‪ n‬ﯾﺗم ﺣﺳﺎﺑﮫ ﻣن ﺧﻼل اﻟﻌﻼﻗﺔ ﺑﯾن اﻟﺟﮭد وﻋدد اﻟﻠﻔﺎت وھﻰ‬
‫ﻋﻼﻗﺔ ﺻﺣﯾﺣﺔ ﺳواء ﺑﯾن ﻋدد ﻟﻔﺎت اﻟﺛﺎﻧوى ﻣﻊ ﺑﻌﺿﮭﺎ اﻟﺑﻌض او ﻋدد ﻟﻔﺎت اﻟﺛﺎﻧوى ﻣﻊ اﻻﺑﺗداﺋﻰ‬
‫اﻟﺟﮭد اﻻﻣﺎﻣﻰ ﻟداﯾود رﻗم ‪n‬‬
‫اﻟﻣ‬

‫ﻋدد ﻟﻔﺎت اى ﻣﻠف رﻗﻣﮫ ‪n‬‬

‫ﺻ‬

‫ﺟﮭد اﻻﻣﺎﻣﻰ ﻟداﯾود اﻟﺧرج‪1‬‬

‫ﻗﺎﻋدة ﻋﺎﻣﺔ ‪:‬‬

‫رى‬

‫ﻋدد اﻟﻠﻔﺎت ‪/ 1‬ﻋدد اﻟﻠﻔﺎت ‪ = 2‬ﺟﮭد اﻟﺧرج ‪+ 1‬ﺟﮭد داﯾود‪ / 1‬ﺟﮭد اﻟﺧرج ‪ + 2‬ﺟﮭد داﯾود ‪2‬‬

‫ﻟﺣﺳﺎب ﻋدد ﻟﻔﺎت ﻣﻠف اﻟﺗﺷﻐﯾل ‪:‬‬

‫ﯾﻌﺗﺑر ﻣﻠف اﻟﺗﺷﻐﯾل ﻣﻠف ﺛﺎﻧﻰ اﯾﺿﺎ وﯾﺗم ﺗطﺑﯾق ﻧﻔس ﻗﺎﻋدة اﻟﻌﻼﻗﺔ ﺑﯾن اﻟﺟﮭد واﻟﻠﻔﺎت ﻣﻊ ﻣﻼﺣظﺔ اﻧﮫ ﯾﺗم اﺧﺗﯾﺎر‬
‫ﺟﮭد اﻟﺗﺷﻐﯾل ‪ Vcc‬ﻣن اﻟداﺗﺎﺷﯾت ﻟﻼﯾﺳﻰ‬

‫ﻋدد ﻟﻔﺎت اﻟﺗﺷﻐﯾل‬

 ‫ﺣﺳﺎب طول اﻟﺛﻐرة اﻟﮭواﺋﯾﺔ ‪:‬‬
‫ﻻﺣظ ﺗﺎﺛﯾر ﻋدد اﻟﻠﻔﺎت وﻣﺣﺎﺛﺔ اﻟﻘﻠب وﻣﺣﺎﺛﺔ اﻟﻣﻠف اﻻﺑﺗداﺋﻰ وﻣﺳﺎﺣﺔ اﻟﻘﻠب ﻋﻠﻰ طول اﻟﺛﻐرة‬

‫‪3.14‬‬

‫ﺑﺎﻟﻣﯾﻠﻠﻰ‬

‫ﻣﺳﺎﺣﺔ ﻣﻘطﻊ اﻟﻘﻠب ﺑﺎﻟﺳم ﻣرﺑﻊ‬ ‫ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ‬

‫ﻣﺣﺎﺛﺔ اﻟﻘﻠب ﻣوﺟودة ﻓﻰ اﻟداﺗﺎﺷﯾت ﻟﻠﻘﻠب‬

‫‪ - 8‬ﺣﺳﺎب ﻗطر ﺳﻠك اﻟﻣﻠﻔﺎت ﺑﻧﺎء ﻋﻠﻰ ﻗﯾﻣﺔ ﺗﯾﺎر ‪ RMS‬اﻟﻣﺎر ﻓﻰ ﻛل ﻣﻠف ‪:‬‬
‫ﯾﺗم ﺗﻌﯾﯾن ﻗطر اﻟﺳﻠك ﻣن ﺧﻼل ﺗﻌﯾﯾن اوﻻ اﻟﺗﯾﺎر اﻟذى ﺳﯾﻣر ﻓﯾﮫ اﻟﺳﻠك ﺛم اﺳﺗﺧدام ﻗﺎﻋدة ﻋﺎﻣﺔ ﻟﻠﻌﻼﻗﺔ ﺑﯾن طول اﻟﺳﻠك وﻗطر‬
‫اﻟﺳﻠك واﻟﺗﯾﺎر اﻟﻣﺎر ﻓﻰ اﻟﺳﻠك‬

‫م‬
‫ﻗﯾﻣﺔ ﺗﯾﺎر اى ﻣﻠف ﺛﺎﻧوى ﻣن اﻟﻌﻼﻗﺔ اﻟﺗﺎﻟﯾﺔ‬

‫‪/‬‬
‫اﻟﺟﮭد اﻟﻣﻧﻌﻛس ﻣن اﻟﺛﺎﻧوى‬
‫ﻣﻌﺎﻣل اﻟﺣﻣل ﻟﻠﻣﻠف ‪ n‬ﻣﻌﺎدﻟﺔ ‪2‬‬

‫اﺣ‬
‫ﺗﯾﺎر اﻟﺧرج رﻗم ‪n‬‬
‫ﺟﮭد اﻟداﯾود‬

‫ﻣد‬
‫ﺗﯾﺎر ‪ rms‬ﻟﻠﻣوﺳﻔت‬ ‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬
‫ﺟﮭد ﺧرج اﻟﻣﻠف ‪n‬‬

‫ﻻﺧﺗﯾﺎر ﻗطر اﻟﺳﻠك ﺣﺳب اﻻﻣﺑﯾر ‪:‬‬

‫ﯾ‬
‫ﻣﻠﺣوظﺔ ‪ :‬ﻛﺛﺎﻓﺔ اﻟﺗﯾﺎر ھﻰ ‪ 5‬اﻣﺑﯾر ‪ /‬ﻣﻠﻠﻰ ﻣرﺑﻊ ﻋﻧدﻣﺎ ﯾﻛون طول اﻟﺳﻠك اﻛﺑر ﻣن ‪ 1‬ﻣﺗر‬
‫وﺳ‬
‫ﻋﻧدﻣﺎ ﯾﻛون طول اﻟﺳﻠك ﻗﺻﯾر ﻧظرا ﻟﻘﻠﺔ ﻋدد اﻟﻠﻔﺎت ﯾﺗم اﻋﺗﯾﺎر ﻛﺛﺎﻓﺔ اﻟﺗﯾﺎر ﻣن ‪ 10: 6‬اﻣﺑﯾر ‪ /‬ﻣﻠﻠﻰ ﻣرﺑﻊ‬
‫ف‬

‫ﯾﺟب ﺗﺟﻧب اﺳﺗﺧدام ﺳﻠك اﻛﺑر ﻣن ‪ 1‬ﻣﻠﻠﻰ ﺣﺗﻰ ﺗﺗﺟﻧب اﻟﺗﺎﺛﯾر اﻟﺳطﺣﻰ ﻟﻠﺗﯾﺎر ﻋﻧد اﻟﺗرددات اﻟﻌﺎﻟﯾﺔ‬
‫واﯾﺿﺎ ﺣﺗﻰ ﯾﺳﮭل ﻟف اﻟﻣﻠﻔﺎت‬
‫اﻟﻣ‬

‫اﯾﺿﺎ ﻗم ﺑﺎﺧﺗﺑﺎر ﻟﻣﺳﺎﺣﺔ ﺷﺑﺎك اﻟﻣﻠﻔﺎت ﻟﺗرى ھل ھﻰ ﻣﻧﺎﺳﺑﺔ ام ﻻ ﻟﺣﺟم اﻟﻣﻠﻔﺎت‬

‫ﺻ‬

‫ﯾﺗم ﺣﺳﺎب ﻣﺳﺎﺣﺔ اﻟﺷﺑﺎك ﻣن ﺧﻼل اﻟﻌﻼﻗﺔ اﻟﺗﺎﻟﯾﺔ ‪:‬‬

‫رى‬

‫ﻋﻧد ﻟف اﻻﺳﻼك ﻓﺎﻧﮭﺎ ﻻﺗﻣﻼ اﻟﻣﺳﺎﺣﺔ‬

‫ﻣﺳﺎﺣﺔ اﻟﺷﺑﺎك‬ ‫اﻟﻛﻠﯾﺔ ﻟﻠﺷﺑﺎك وﻟﻛن ﯾوﺟد ﻓراغ ﻧﺗﯾﺟﺔ‬
‫ﻣﻌﺎﻣل اﻟﻣﻠﺊ‬ ‫ان اﻟﺳﻠك داﺋرة ﻟذﻟك ﯾﺗم اﺳﺗﻘطﺎع ﻧﺳﺑﺔ‬
‫ﻟﻠﻔراغ ﻋﻧد ﺣﺳﺎب ﻣﺳﺎﺣﺔ اﻟﺳﻠك اﻟذى‬
‫ﻣﺳﺎﺣﺔ ﻣﻘطﻊ اﻟﺳﻠك‬
‫ﺳﯾﻣﻸ ﻣﺳﺎﺣﺔ اﻟﺷﺑﺎك‬

‫ﯾﺗم اﺧﺗﯾﺎر ﻣﻌﺎﻣل اﻟﻣﻠﺊ ﺑﺎﻟﻧﺳﺑﺔ ﻟﻠﺑﺎور ذو ﺧرج واﺣد ﺑﯾن ‪0.25~0.2‬‬

‫اﻣﺎ ﻟﻠﺑﺎور ذو اﻟﺧرج اﻟﻣﺗﻌدد ﻓﯾﺗم اﻋﺗﺑﺎره ﺑﯾن ‪0.2~0.15‬‬

‫اذا وﺟدت ان ﻣﺳﺎﺣﺔ اﻟﺷﺑﺎك اﻟﻣوﺟودة ﻋﻧدك اﻗل ﻣن ﻣﺳﺎﺣﺔ اﻟﺷﺑﺎك اﻟﻣطﻠوﺑﺔ ﻗم ﺑﺎﻟرﺟوع ﻟﻠﺧطوة ‪ 6‬وﻗم ﺑﺎﺧﺗﯾﺎر‬
‫ﺣﺟم ﻗﻠب اﻛﺑر‬
 ‫اﯾﺿﺎ اذا ﻗﻣت ﺑﺎﻟﺗﺻﻣﯾم ووﺟدت ان اﻟﻣﻠﻔﺎت ﺣﺟﻣﮭﺎ ﻛﺑﯾر ﺑﻧﺳﺑﺔ ﺑﺳﯾطﺔ ارﺟﻊ ﻟﻠﺧطوة ‪ 4‬وﻗم‬
‫ﺑﺗﺻﻐﯾر ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ وذﻟك ﺑﺗﻛﺑﯾر ﻣﻌﺎﻣل اﻟرﯾﺑل ‪K RF‬‬
‫وﻋﻧد ﺗﺧﻔﯾض اﻟﻣﺣﺎﺛﺔ ﺳﯾﺗم ﺗﺧﻔﯾض ﻋدد اﻟﻠﻔﺎت ﻓﻰ اﻟﻣﻌﺎدﻟﺔ ‪ 13‬ﻣﻣﺎ ﯾﺟﻌل اﻟﻣﻠﻔﺎت ﻣﻼﺋﻣﺔ ﻟﻠﺷﺑﺎك‬

‫‪ - 9‬اﻟﺧطوة اﻟﺗﺎﺳﻌﺔ ‪ :‬ﺗﻌﯾﯾن ﺟﮭد وﺗﯾﺎر داﯾود اﻟﺧرج ‪:‬‬

‫ﯾﺗم ﺣﺳﺎب اﻟﺟﮭد اﻟﻌﻛﺳﻰ ﻟداﯾود اﻟﺧرج ﻣن ﺧﻼل اﻟﺟﮭد اﻟواﻗﻊ ﻋﻠﯾﮫ اﺛﻧﺎء ﺗوﻗﻔﮫ وھﻰ ﻓﺗرة ﺗﺷﻐﯾل‬

‫م‬
‫اﻟﻣوﺳﻔت ﺣﯾث ﯾﻛون واﻗﻊ ﻋﻠﯾﮫ اﻟﺟﮭد اﻟﻌﻛﺳﻰ اﻟﻘﺎدم ﻣن ﻣﻠف اﻻﺑﺗداﺋﻰ ‪ +‬ﺟﮭد اﻟﺧرج‬

‫‪/‬‬
‫اﻗﺻﻰ ﺟﮭد ﻋﻠﻰ ﻣﻛﺛف اﻟدﺧل‬ ‫اﻟﺟﮭد اﻟﻌﻛﺳﻰ ﻣن اﻻﺑﺗداﺋﻰ‬

‫اﺣ‬
‫ﺟﮭد داﯾود اﻟﺧرج اﻻﻣﺎﻣﻰ‬

‫اﻟﺟﮭد اﻟﻌﻛﺳﻰ ﻋﻠﻰ اﻟداﯾود‬

‫ﺟﮭد اﻟﺧرج‬
‫ﯾ‬ ‫ﻣد‬ ‫اﻟﺟﮭد اﻟﻌﻛﺳﻰ ﻟﻠﺧرج‬
‫اﻟﺟﮭد اﻟﻌﻛﺳﻰ ﻋﻠﻰ اﻟداﯾود ) ﺟﮭد اﻟﺛﺎﻧوى ( = ﺟﮭد اﻟﺧرج ‪ +‬ﺟﮭد اﻻﺑﺗداﺋﻰ ‪ x‬ﻧﺳﺑﺔ اﻟﻠﻔﺎت‬
‫وﺳ‬
‫ﺗﯾﺎر داﯾود اﻟﺧرج ‪:‬‬
‫ف‬
‫اﻟﻣ‬

‫ﻟﻼﻣﺎن ﻧﻘوم ﺑﺗﺣدﯾد اﻟﺟﮭد وﺗﯾﺎر اﻟداﯾود ﺑزﯾﺎدة اﻟﻘﯾﺔ ﺑﻧﺳﺑﺔ اﻣﺎن وھﻰ ‪ :‬ﻧﺿرب اﻟﺟﮭد‬
‫ﺻ‬

‫اﻟﻌﻛﺳﻰ اﻟﻧﺎﺗﺞ ﻓﻰ ‪ 1.3‬واﻟﺗﯾﺎر ﻓﻰ ‪1.5‬‬

‫رى‬

‫ﻣﻠﺣوظﺔ ‪ :‬ﻛل ﺗﻠك اﻟﻣﻌﺎدﻻت ﺗﺟدھﺎ ﻓﻰ اﻟﺑرﻧﺎﻣﺞ ﯾﺧرج ﻟك اﻟﻘﯾم ﺑدون ﺗﻌب‬
 ‫اﻧواع داﯾودات ﺷوﺗﻛﻰ وﻓﺎﺋث اﻟﺳرﻋﺔ ﻣﻊ ﺑﯾﺎن اﻟﺟﮭد اﻟﻌﻛﺳﻰ واﻟﺗﯾﺎر‬ ‫ﻣن ﺧﻼل ھذا اﻟﺟدول ﻟداﯾودات ﺷرﻛﺔ ﻓﯾرﺷﯾﻠد ﯾﻣﻛﻧك اﺧﺗﯾﺎر‬
‫داﯾود ﻧوع اﻟﺷوﺗﻛﻰ‬ ‫اﻟداﯾود ﺣﯾث ﺗﻼﺣظ ان داﯾودات اﻟﺷوﺗﻛﻰ اﻟﺟﮭد اﻟﻌﻛﺳﻰ ﻟﮭﺎ‬
‫رﻗم اﻟداﯾود‬ ‫اﻟﺟﮭد‬ ‫اﻟﺗﯾﺎر‬ ‫اﻗل ﻣن اﻟداﯾودات ﻓﺎﺋﻘﺔ اﻟﺳرﻋﺔ‬
Products VRRM IF trr Package
SB330 30 V 3A - TO-210AD
SB530 30 V 5A - TO-210AD
MBR1035 35 V 10 A - TO-220AC ‫ﻻﺣظ ان ﻣﯾزة داﯾودات ﺷوﺗﻛﻰ ان اﻟﺟﮭد اﻟﻣﺳﺗﮭﻠك ﺣواﻟﻰ‬
MBR1635 35 V 16 A - TO-220AC ‫ ﻓوﻟت ﺑﯾﻧﻣﺎ ﺗﺗﻣﯾز‬0.8 ‫ ﻓوﻟت ﺑﯾﻧﻣﺎ اﻟﻔﺎﺋق اﻟﺳرﻋﺔ ﺣواﻟﻰ‬0.5
SB340 40 V 3A - TO-210AD
‫اﻟداﯾودات ﻓﺎﺋﻘﺔ اﻟﺳرﻋﺔ ﺑﺎن اﻟﺟﮭد اﻟﻌﻛس ﻟﮭﺎ اﻋﻠﻰ‬
SB540 40 V 5A - TO-210AD
SB350 50 V 3A - TO-210AD
SB550 50 V 5A - TO-210AD

‫م‬
SB360 60 V 3A - TO-210AD
SB560 60 V 5A - TO-210AD

/
MBR1060 60 V 10 A - TO-220AC
MBR1660 60 V 16 A - TO-220AC

‫اﺣ‬
‫اﻟداﯾود ﻓﺎﺋق اﻟﺳرﻋﺔ‬
Products VRRM IF trr Package
EGP10B 100 V 1A 50 ns DO-41
UF4002
EGP20B
EGP30B
FES16BT
100 V
100 V
100 V
100 V
1A
2A
3A
16 A
50 ns
50 ns
50 ns
35 ns
DO-41
DO-15
DO-210AD
‫ﯾ‬
TO-220AC
‫ﻣد‬
‫وﺳ‬
EGP10C 150 V 1A 50 ns DO-41
EGP20C 150 V 2A 50 ns DO-15
EGP30C 150 V 3A 50 ns DO-210AD
‫ف‬

FES16CT 150 V 16 A 35 ns TO-220AC

EGP10D 200 V 1A 50 ns DO-41
UF4003 200 V 1A 50 ns DO-41
EGP20D 200 V 2A 50 ns DO-15
‫اﻟﻣ‬

EGP30D 200 V 3A 50 ns DO-210AD

FES16DT 200 V 16 A 35 ns TO-220AC
EGP10F 300 V 1A 50 ns DO-41
‫ﺻ‬

EGP20F 300 V 2A 50 ns DO-15

EGP30F 300 V 3A 50 ns DO-210AD
‫رى‬

EGP10G 400 V 1A 50 ns DO-41

UF4004 400 V 1A 50 ns DO-41
EGP20G 400 V 2A 50 ns DO-15
EGP30G 400 V 3A 50 ns DO-210AD
UF4005 600 V 1A 75 ns DO-41
EGP10J 600 V 1A 50 ns DO-41
EGP20J 600 V 2A 50 ns DO-15
EGP30J 600 V 3A 50 ns DO-210AD
UF4006 800 V 1A 75 ns TO-41
UF4007 1000 V 1A 75 ns TO-41

Table 2. Fairchild Diode quick selection table

©2002 Fairchild Semiconductor Corporation

7
 ‫‪ - 10‬ﺧطوة ‪ 10‬ﺗﻌﯾﯾن ﻣﻛﺛف اﻟﺧرج ‪:‬‬
‫ﯾﺗم ﺗﻌﯾﯾن ﺳﻌﺔ اى ﻣﻛﺛف ﻣن ﺧﻼل ﺗﻌﯾﯾن ﺗﯾﺎر اﻟرﯾﺑل وﺟﮭد اﻟرﯾﺑل ﻟﻠﻣﻛﺛف‬

‫ﺗﯾﺎر اﻟرﯾﺑل ﻟﻠﻣﻛﺛف‪:‬‬

‫ﺗﯾﺎر اﻟرﯾﺑل ﻟﻠﻣﻛﺛف‬

‫ﺗﯾﺎر ﺣﻣل اﻟﺧرج‬
‫ﻣن ﻣﻌﺎدﻟﺔ ‪21‬‬

‫ﯾﺟب اﺧﺗﯾﺎر ﺗﯾﺎر رﯾﺑل اﻗل ﻣن اﻟﻘﯾﻣﺔ اﻟﻧﺎﺗﺟﺔ ﻣن اﻟﻣﻌﺎدﻟﺔ ‪24‬‬

‫م‬
‫اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت‬
‫ﺟﮭد اﻟرﯾﺑل ﻟﻠﻣﻛﺛف‪:‬‬
‫اﻟﻣﻘﺎوﻣﺔ اﻟداﺧﻠﯾﺔ ﻟﻠﻣﻛﺛف ‪ESR‬‬
‫ﺗﯾﺎر اﻟﺣﻣل‬

‫‪/‬‬
‫دﯾوﺗﻰ‬

‫اﺣ‬
‫ﺳﻌﺔ اﻟﻣﻛﺛف‬ ‫ﺟﮭد اﻟداﯾود اﻻﻣﺎﻣﻰ‬
‫ﺟﮭد اﻟﺧرج‬

‫ﻋﻧدﻣﺎ ﺗﺟد ان اﻟرﯾﺑل ﻋﺎﻟﯾﺔ ﯾﻣﻛن وﺿﻊ ﻓﻠﺗر ﻧوع ‪ LC‬ﻋﻠﻰ اﻟﺧرج‬

‫‪ - 11‬ﺗﻌﯾﯾن ﻗﯾم داﺋرة اﻻﺧﻣﺎد او اﻟﺳﻧوﺑر‬

‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫ﻋﻧد ﺗوﻗف اﻟﻣوﺳﻔت ﯾظﮭر ﺟﮭد ﻋﺎﻟﻰ )ﺷﺎرز ( ﻋﻠﻰ ﻣدﺧل‬
‫اﻟدرﯾن ﯾﺿﺎف اﻟﯾﮫ ﺟﮭد ﻋﻛﺳﻰ ﻗﺎدم ﻣن ﻣﻠﻔﺎت اﻟﺛﺎﻧوى ‪+‬‬
‫ف‬

‫اﻟﻣﻠف اﻻﺑﺗداﺋﻰ ﻣﻊ ﻣﻠف اﻟﻣﺣﺎﺛﺔ اﻟﺷﺎردة ﻣﻊ‬ ‫ﺟﮭد اﻟدﺧل‬

‫داﺋرة اﻻﺧﻣﺎد ﯾﻛوﻧون داﺋرة ﻣﻐﻠﻘﺔ‬
‫ھذا اﻟﺟﮭد اﻟﻌﺎﻟﻰ ﻋﻠﻰ اﻟﻣوﺳﻔت ﯾﺻﺑﺢ ﺧطرا ﻋﻠﻰ اﻟﻣوﺳﻔت ﻻن‬
‫ھﻧﺎك ﻣﻛﺛف طﻔﯾﻠﻰ ﺑﯾن اﻟدرﯾن واﻟﺳورس ﯾﺳﻣﺢ ﺑﻣرور ﺗﯾﺎر ﻋﻠﻰ‬
‫اﻟﻣ‬

‫اﻟﻣوﺳﻔت اﺛﻧﺎء ﺗوﻗﻔﮫ وﻣﻊ ھذا اﻟﺟﮭد اﻟﻌﺎﻟﻰ ﯾﻣر ﺗﯾﺎر ﻋﺎﻟﻰ‬
‫وﯾﺳﺑب اﺣﺗراق اﻟﻣوﺳﻔت ﻟذﻟك ﯾﺗم ﻏﻠق اﻟﻣﻠف اﻻﺑﺗداﺋﻰ ﻋﻠﻰ‬
‫اﻟﻣﻛﺛ ف‬
‫ﺻ‬

‫اﻟرﺋﯾﺳﻰ‬ ‫ﻧﻔﺳﮫ ﻟﻠﺗﺧﻠص ﻣن اﻟﺟﮭد اﻟﻣرﺗد ‪ +‬ﺟﮭد اﻟﺷﺎرز‬

‫ﺟﮭد اﻟﺷﺎرز ﻛﻣﺎ ﻧﻌﻠم ﻧﺎﺗﺞ ﻣن ﻣﻠف اﻟﻣﺣﺎﺛﺔ اﻟﺷﺎردة ‪Llk‬‬

‫رى‬

‫ﻻﺣظ ان اﻟﻣﻠف ﯾﺳﻠك ﺳﻠوك ﺑطﺎرﯾﺔ ﻋﻧدﻣﺎ ﺗﻐﻠﻘﮫ ﺑواﺳطﺔ‬

‫اﻟﻣﺣﺎﺛﺔ اﻟﺷﺎردة‬
‫داﺋرة اﻻﺧﻣﺎد ﺣﯾث ﯾﻣر ﺗﯾﺎر ﻣن اﻧود اﻟداﯾود اﻟﻰ اﻟﻣﻛﺛف‬
‫واﻟﻣﻘﺎوﻣﺔ ﺛم ﯾﻌود ﻟﻠطرف اﻟﻌﻠوى ﻟﻠﻣﻠف ﻓﻰ داﺋرة ﻣﻐﻠﻘﺔ‬
‫ﺣﯾث ﯾﺗم ﺷﺣن اﻟﻣﻛﺛف ﺑﮭذا اﻟﺟﮭد اﻟزاﺋد وﺗﻘوم اﻟﻣﻘﺎوﻣﺔ‬
‫اﻟﺟﮭد ﻋﻠﻰ اﻟﻣوﺳﻔت‬
‫ﺑﺗﺧﻔﯾف اﻟﺗردد ﻟﺟﮭد اﻟﺷﺎرز واﯾﺿﺎ ﺗﻌﻣل ﻋﻠﻰ ﺗﻔرﯾﻎ‬
‫اﯾﺳﻰ اﻟﺑﺎور‬ ‫اﻟﻣﻛﺛف اﺛﻧﺎء ﺗﺷﻐﯾل اﻟﻣوﺳﻔت ﺣﺗﻰ ﯾﺷﺣن ﻣن ﺟدﯾد‬

‫ﯾﺗم ﻏﻠق داﺋرة اﻟﻣﻠﻔﯾن ﺑواﺳطﺔ داﯾود وﻣﻛﺛف وﻣﻘﺎوﻣﺔ‬

‫ﻓﺎﺋدة اﻟداﯾود ھو ﻣﻧﻊ ﻣرور ﺗﯾﺎر ﻓﻰ اﻟﻣﻛﺛف واﻟﻣﻘﺎوﻣﺔ اﺛﻧﺎء ﺗﺷﻐﯾل اﻟﻣوﺳﻔت ﻻن ﻟو ﻟم ﯾﻛن ھﻧﺎك داﯾود وﺳﯾﺻﺑﺢ‬
‫اﻟﻣﻛﺛف واﻟﻣﻘﺎوﻣﺔ ﻋﻠﻰ اﻟﺗوازى ﻣﻊ اﻟﻣﻠف اﻻﺑﺗداﺋﻰ وﺳﯾﻣر ﺗﯾﺎر ﻓﯾﮭﻣﺎ اﺛﻧﺎء ﺗﺷﻐﯾل اﻟﻣوﺳﻔت ﻣﻣﺎ ﯾﺳﺑب ﺧﻠل ﻓﻰ ﻋﻣل‬
‫اﻟﻣﺣول اى ﻟن ﯾﻌﻣل اﻟﻣﺣول ﺑﺻورة ﺻﺣﯾﺣﺔ‬
 ‫ﻧﺣن ﻧﻘوم ﺑﻐﻠق داﺋرة اﻟﻣﻠﻔﯾن ﻛﻣﺎ ﻗﻠﻧﺎ ﺑﻣﻛﺛف وﻟم ﻧﺳﺗﺧدم ﻣﻘﺎوﻣﺔ ﻓﻘط ﺣﺗﻰ ﻻﯾﺗم ﻓﻘد ﻓﻰ اﻟﻘدرة ﻋﻠﻰ‬
‫اﻟﻣﻘﺎوﻣﺔ واﯾﺿﺎ ﻻن اﻟﻣﻛﺛف اﺳرع ﻓﻰ ﺗﻣرﯾر اﻟﺗﯾﺎر ﻋﻠﯾﮫ ﺣﯾث ﻻﯾﻌﺗﺑر اﻟﻣﻛﺛف ﺣﻣل ذو ﻣﻘﺎوﻣﺔ وﻋﻠﯾﮫ‬
‫اﻟﮭدف ﻓﻘط ھو اﻟﺗﺧﻠص ﻣن ﺟﮭد اﻟﺷﺎرز وﺟزء ﻣن اﻟﺟﮭد اﻟﻣﻧﻌﻛس ﻣن اﻟﺛﺎﻧوى وﺗﺧزﯾﻧﮭم ﻋﻠﻰ اﻟﻣﻛﺛف‬
‫وﻓﺎﺋدة اﻟﻣﻘﺎوﻣﺔ اﻟﻣرﺑوطﺔ ﻣﻌﮫ ﻋﻠﻰ اﻟﺗوازى ھﻰ ﺗﻔرﯾﻎ اﻟﻣﻛﺛف ﻟﯾﻛون ﺟﺎھز ﻻﺳﺗﻘﺑﺎل ﺷﺣﻧﺔ ﺷﺎرز‬
‫ﺟدﯾدة وﺑﺗﻠك اﻟطرﯾﻘﺔ ﻧﻛون ﻗد ﺗﺧﻠﺻﻧﺎ ﻣن اﻟﺟﮭد اﻟﻣﻔﺎﺟﺊ ﺑﺗﺧزﯾﻧﮫ ﻋﻠﻰ اﻟﻣﻛﺛف واﯾﺿﺎ ﻗد ﺗﺧﻠﺻﻧﺎ ﻣن‬
‫اﻟﺗﯾﺎر اﻟﻠﺣظﻰ اﻟﻛﺑﯾر ﻧﺗﯾﺟﺔ ﻟﮭذا اﻟﺟﮭد اﻟﻌﺎﻟﻰ‬

‫ﻟﻛﻰ ﻧﺣدد ﻗﯾﻣﺔ اﻟﻣﻛﺛف اﻟذى ﺳﻧﺿﻌﮫ ﻓﻰ داﺋرة اﻻﺧﻣﺎد او اﻟﺳﻧوﺑر ﯾﺟب ان ﺗﻛون ﺳﻌﺗﮫ ﺗﺳﺗوﻋب‬
‫اﻟﺗﯾﺎر اﻟﻣﺎر واﯾﺿﺎ ﯾﺟب ان ﯾﻛون ﺟﮭده ﻋﺎﻟﻰ ﻟﯾﻼﺋم اﻟﺟﮭد اﻟﻌﺎﻟﻰ اﻟﻣرﺗد‬

‫ﺗﺣدﯾد اﻟﻘدرة اﻟﻣﺳﺗﮭﻠﻛﺔ ﻋﻠﻰ ﻣﻛﺛف اﻻﺧﻣﺎد ‪:‬‬

‫م‬
‫اﻟﻘدرة اﻟﻣﺳﺗﮭﻠﻛﺔ ﻋﻠﻰ اﻟﻣﻛﺛف ھﻰ ﻧﻔﺳﮭﺎ اﻟﻘدرة اﻟﻣﺳﺗﮭﻠﻛﺔ ﻋﻠﻰ اﻟﻣﻘﺎوﻣﺔ ﻻن اﻟﻣﻛﺛف ﺳوف ﯾﻔرغ اﻟﺟﮭد‬

‫‪/‬‬
‫اﻟﻣﺧزن ﻓﻰ اﻟﻣﻘﺎوﻣﺔ اﻟﻣوﺻﻠﺔ ﻣﻌﮫ ﻋﻠﻰ اﻟﺗوازى‬

‫اﺣ‬
‫اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﺗﯾﺎر اﻟﻣوﺳﻔت‬
‫ﺟﮭد ﻣﻛﺛف اﻻﺧﻣﺎد‬ ‫ﺗردد اﻟﺗﻘطﯾﻊ‬

‫ﻗدرة اﻻﺧﻣﺎد اﻟﻣﺳﺗﻧﻔذة‬

‫ﻣﻘﺎوﻣﺔ اﻻﺧﻣﺎد‬
‫ﯾ‬ ‫اﻟﻣﺣﺎﺛﺔ اﻟﺷﺎردة‬
‫ﻣد‬ ‫اﻟﺟﮭد اﻟﻣرﺗد ﻣن اﻟﺧرج‬
‫وﺳ‬
‫ﺟﮭد داﺋرة اﻻﺧﻣﺎد ‪ Vsn‬ﯾﺗم اﺧﺗﯾﺎره ﺑﺣﯾث ﯾﻛون اﻛﺑر ﻣن اﻟﺟﮭد اﻟﻣﻧﻌﻛس ﻣن اﻟﺧرج ﺑﻘﯾﻣﺔ ﺗﻘﻊ ﺑﯾن ‪ 2‬اﻟﻰ ‪2.5‬‬
‫ف‬

‫ﻣرة ﻣن ﻗﯾﻣﺔ ﺟﮭد اﻟﺧرج اﻟﻣﻧﻌﻛس ﻋﻠﻰ اﻻﺑﺗداﺋﻰ ‪VRO‬‬

‫ﯾﺗم اﺧﺗﯾﺎر ﻗدرة اﻟﻣﻘﺎوﻣﺔ ﻣن اﻟﻣﻌﺎدﻟﺔ ‪ 26‬ﺑﺣﯾث ﺗﺗﺣﻣل اﻗﺻﻰ ﻗدرة ﻋﻠﻰ داﺋرة اﻻﺧﻣﺎد‬
‫اﻟﻣ‬

‫ﯾﺗم ﺣﺳﺎب ﺟﮭد اﻟرﯾﺑل ﻋﻠﻰ ﻣﻛﺛف اﻻﺧﻣﺎد ﻣن ﺧﻼل اﻟﻌﻼﻗﺔ اﻟﺗﺎﻟﯾﺔ ‪:‬‬
‫ﺻ‬

‫ﺟﮭد اﻻﺧﻣﺎد‬
‫ﺟﮭد اﻟرﯾﺑل‬
‫رى‬

‫ﺗردد اﻟﺗﻘطﯾﻊ‬
‫ﺳﻌﺔ ﻣﻛﺛف اﻻﺧﻣﺎد‬
‫ﻣﻘﺎوﻣﺔ اﻻﺧﻣﺎد‬

‫ﺗذﻛر ان اﻟﻣﻌﺎدﻟﺔ ‪ 26‬ﺗم ﺣﺳﺎﺑﮭﺎ ﻋﻧد اﻟﻌﻣل ﺑﻧظﺎم ‪ CCM‬ﻣﻊ وﺟود اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﻠﺣﻣل ﻣﻊ اﻗل ﺟﮭد‬
‫دﺧل ﻣﺗردد ﻟﻠﻣﺻدر‬

‫ﻛﻠﻣﺎ زاد ﺟﮭد اﻟدﺧل ﻗل ﺗﯾﺎر اﻟﻣوﺳﻔت وﻗل ﺟﮭد داﺋرة اﻻﺧﻣﺎد ‪Vsn‬‬
 ‫وﻟﺣﺳﺎب ﺟﮭد اﻻﺧﻣﺎد ﻋﻧد اﻗﺻﻰ ﺣﻣل واﻗﺻﻰ ﺟﮭد دﺧل ﺳﯾﻛون ھﻧﺎك ﻣﺳﻣﻰ ﺛﺎﻧﻰ ھو ‪Vsn2‬‬

‫ﺟﮭد داﺋرة اﻟﺳﻧوﺑر ﻋﻧد اﻗﺻﻰ‬ ‫‪28‬‬

‫ﺟﮭد دﺧل واﻗﺻﻰ ﺣﻣل‬
‫ﺗﯾﺎر اﻟﻣوﺳﻔت ﻋﻧد اﻗﺻﻰ ﺗﯾﺎر ﺣﻣل‬

‫ﺗﯾﺎر اﻟﻣوﺳﻔت ﻋﻧد اﻗﺻﻰ ﺟﮭد دﺧل واﻗﺻﻰ ﺗﯾﺎر ﺣﻣل ﻋﻧد اﻟﻌﻣل ﺑﻧظﺎم ‪ DCM‬وﻣن اﻟﻣﻌﺎدﻟﺔ ‪12‬‬

‫‪/‬‬ ‫م‬
‫‪30‬‬

‫اﺣ‬
‫ﻣد‬
‫وﻣن اﻟﻣﻌﺎدﻟﺔ ‪ 28‬ﻓﺎن اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﻠﺟﮭد اﻟواﻗﻊ ﻋﻠﻰ اﻟﻣوﺳﻔت ﻋﻧد اﻗﺻﻰ ﺣﻣل واﻗﺻﻰ ﺟﮭد دﺧل ‪:‬‬
‫ﯾ‬
‫وﺳ‬
‫ﺟﮭد اﺧﻣﺎد ‪2‬‬
‫اﻗﺻﻰ ﺟﮭد ﻣرﺗد ﻋﻠﻰ اﻟﻣوﺳﻔت‬
‫ف‬

‫اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻋﻠﻰ ﻣﻛﺛف اﻟدﺧل‬

‫ﻋﻧد اﺧﺗﯾﺎر اﻟﻣوﺳﻔت ﯾﺟب ان ﯾﻛون ﺟﮭد اﻻﻧﮭﯾﺎر ﻟﮫ اﻋﻠﻰ ﻣن اﻟﻘﯾﻣﺔ اﻟﻣﺳﺗﺧرﺟﺔ ﻣن ‪ 31‬ﺑﺣﯾث ﺗﻣﺛل اﻟﻘﯾﻣﺔ اﻟﻣﺳﺗﺧرﺟﺔ‬
‫اﻟﻣ‬

‫ﻣن ‪ 31‬ﻧﺳﺑﺔ ‪ 90‬ﻓﻰ اﻟﻣﯾﺔ ﻣن ﺟﮭد اﻟﻣوﺳﻔت اﻟذى ﺳﯾﺗم اﺧﺗﯾﺎره‬

‫ﺻ‬

‫وﻛذﻟك اﻟداﯾود اﻟﻣﺧﺗﺎر ﯾﺟب ان ﯾﻛون ﺟﮭده اﻟﻌﻛﺳﻰ اﻋﻠﻰ ﻣن ﺟﮭد اﻧﮭﯾﺎر اﻟﻣوﺳﻔت وﻋﺎﻣﺔ ﯾﺗم اﺳﺗﺧدام داﯾود ﻓﺎﺋق‬
‫اﻟﺳرﻋﺔ ﯾﺗﺣﻣل ‪ 1‬اﻣﺑﯾر‬
‫رى‬

‫زﯾﺎدة ﻟﻼﻣﺎن‬

‫اﻟﺟﮭد اﻟﺿﺎﻏط ﻋﻠﻰ‬ ‫ﺟﮭد اﻟﺷﺎرز ﻟﻠﻣﺣﺎﺛﺔ اﻟﺷﺎردة‬ ‫ﯾﺗم اﻋﺗﺑﺎره ﻣن‬
‫اﻟﻣوﺳﻔت‬ ‫‪ 5‬اﻟﻰ ‪ 10‬ﻓوﻟت‬

‫ﺟﮭد اﻻﺧﻣﺎد‬ ‫ﺟﮭد اﻟﺧرج اﻟﻣﻧﻌﻛس‬

‫اﻗﺻﻰ ﺟﮭد ﻋﻠﻰ ﻣﻛﺛف اﻟدﺧل‬

 ‫‪ - 12‬ﺗﺻﻣﯾم داﺋرة اﻟﻔﯾدﺑﺎك‬

‫ﻟﻠﻔوﺗوﻛﺎﺑﻠر ﻣﻌﺎﻣل ﯾﺳﻣﻰ ‪ CTR‬وھو ﻣﻌﺎﻣل اﻧﺗﻘﺎل‬

‫اﻟﺗﯾﺎر او اﻟﻧﺳﺑﺔ ﺑﯾن ﺗﯾﺎر اﻟﺗراﻧزﺳﺗور وﺗﯾﺎر اﻟﻠﯾد‬
‫ﻓﻰ اﻟﻣﯾﺔ وھﻰ ﻧﺳﺑﺔ ﺗﺧﺗﻠف ﻣن ﻓوﺗوﻛﺎﺑﻠر اﻟﻰ اﺧر‬
‫ﺣﺳب ﻧوﻋﮫ‬

‫ﻓﻰ دواﺋر اﻟﺗﺻﻣﯾم اﻟﺗﺎﺑﻌﺔ ﻟﮭذه اﻟﺷرﻛﺔ ﺑﯾﻌﺗﺑر ان‬

‫‪ CTR = 100%‬اى ﺗﯾﺎر اﻟﻠﯾد = ﺗﯾﺎر اﻟﺗراﻧزﺳﺗور‬

‫اﻟﺟﮭد ﻋﻠﻰ اﻟﻣﻛﺛف ‪ CB‬ھو ﺟﮭد ﻣدﺧل اﻟﻔﯾدﺑﺎك‬

‫وھو ﯾﺳﺎوى اﻟﺟﮭد ﺑﯾن ﻣﺟﻣﻊ وﻣﺷﻊ ﺗراﻧزﺳﺗور‬
‫اﻟﻔوﺗوﻛﺎﺑﻠر اﻟذى ﺗﺗﻐﯾر ﻗﯾﻣﺗﮫ ﺗﺑﻌﺎ ﻟﻘﯾﻣﺔ ﺗﯾﺎر ﻟﯾد‬

‫م‬
‫اﻟﻔوﺗوﻛﺎﺑﻠر ﺣﯾث ﻛﻠﻣﺎ زاد ﺗﯾﺎر اﻟﻠﯾد اﻧﺧﻔض اﻟﺟﮭد‬
‫ﺑﯾن اﻟﻣﺟﻣﻊ واﻟﺷﻣﻊ وﺑﺎﻟﺗﺎﻟﻰ ﯾﻧﺧﻔض ﻋﻠﻰ ﻣدﺧل‬

‫‪/‬‬
‫اﻟﻔﯾدﺑﺎك‬

‫اﺣ‬
‫ھﻧﺎك ﻋﻼﻗﺔ ﺑﯾن ﺟﮭد ﻣدﺧل اﻟﻔﯾدﺑﺎك واﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت وھﻰ‬
‫ﺗﻌرف ﺑﻣﻌﺎﻟم اﻟﺗﺣﻛم ﻓﻰ ﺗﯾﺎر اﻟﻣوﺳﻔت ‪: K‬‬
‫ﯾ‬ ‫ﻣد‬ ‫اﻗﺻﻰ ﺗﯾﺎر ﻟﻠدرﯾن‬
‫وﺳ‬
‫ﺟﮭد ﻣدﺧل اﻟﻔﯾدﺑﺎك‬
‫‪ 2.5‬ﻓوﻟت‬
‫ف‬

‫‪ Iover‬ھو اﻗﺻﻰ ﺗﯾﺎر ﯾﻣر ﻓﻰ اﻟﻣوﺳﻔت وﯾﺳﺑب ﺗﺷﺑﻊ اﻟﻘﻠب‬

‫ھو اﻗﺻﻰ ﺟﮭد ﯾﺻل اﻟﯾﮫ ﻣدﺧل اﻟﻔﯾدﺑﺎك وﯾﺣدث ﻋﻧده ﺗﺷﺑﻊ اﻟﻘﻠب وھو‬
‫اﻟﻣ‬

‫ﻻﯾﺳﯾﮭﺎت ‪2.5V = FPS‬‬

‫ﺻ‬
‫رى‬
 ‫ ﺗرﻛﺗﮫ ﺑدون ﺗرﺟﻣﺔ‬- ‫ﻣوﺿوع ﻣﻛﻠﻛﻊ‬
APPLICATION NOTE AN4137

‫ﺗﺻﻣﯾم ﺧط اﻟﻔﯾدﺑﺎك‬

FPS vo1' vo1

vFB RD
ibias

iD Rbias
RB CB
1:1

‫م‬
CF RF R1
KA431

/
R2

‫اﺣ‬
Ipk

‫ﻓﻰ ﻧظﺎم اﻟﺗﺷﻐﯾل اﻟﻣﺗﺻل اﻟﻌﻼﻗﺔ ﺑﯾن اﺷﺎرة ﺟﮭد‬

‫ﻣد‬
MOSFET
current
: ‫اﻟﺧرج وﺟﮭد ﻣدﺧل اﻟﻔﯾدﺑﺎك ﻛﺎﻟﺗﺎﻟﻰ‬
Figure 12. Control Block Diagram
‫ﯾ‬
‫وﺳ‬
‫ف‬

where VDC is the DC input voltage, RL is the effective total

load resistance of the controlled output, defined as Vo12/Po,
Np and Ns1 are specified in step-7, VRO is specified in equa-
tion (5), Vo1 is the reference output voltage, Po is specified in
step-1 and K is specified in equation (32). The pole and zeros
‫اﻟﻣ‬

of equation (33) are defined as

‫ﺻ‬
‫رى‬

2
1 R (1 – D) (1 + D)
w z = -------------------- , w rz = ------------L----------------------------- and w p = ------------------
R c1 C o1 DL m ( N s1 ⁄ N p )
2 R L C o1

where Lm is specified in equation (7), D is the duty cycle of

the FPS, Co1 is the reference output capacitor and RC1 is the
ESR of Co1.

©2003 Fairchild Semiconductor Corporation

9
When the converter has more than one output, the low fre-
quency control-to-output transfer function is proportional to
the parallel combination of all load resistance, adjusted by
the square of the turns ratio. Therefore, the effective load
resistance is used in equation (33) instead of the actual load
resistance of Vo1.
Notice that there is a right half plane (RHP) zero (wrz) in the
control-to-output transfer function of equation (33). Because
the RHP zero reduces the phase by 90 degrees, the crossover
frequency should be placed below the RHP zero.
Figure 13 shows the variation of a CCM flyback converter

‫م‬
control-to-output transfer function for different input volt-
ages. This figure shows the system poles and zeros together
with the DC gain change for different input voltages. The

/
gain is highest at the high input voltage condition and the
RHP zero is lowest at the low input voltage condition.

‫اﺣ‬
Figure 14 shows the variation of a CCM flyback converter
control-to-output transfer function for different loads. This
figure shows that the low frequency gain does not change for
different loads and the RHP zero is lowest at the full load
condition.
For DCM operation, the control-to-output transfer function
of the flyback converter using current mode control is given
by
‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
v̂ o1 Vo1 ( 1 + s ⁄ w z )
G vc = --------- = --------- ⋅ ---------------------------- (34)
ˆv V FB ( 1 + s ⁄ w p )
FB
1
‫ف‬

where wz = -------------------- , w p = 2 ⁄ R L C o1
R c1 C o1

Vo1 is the reference output voltage, VFB is the feedback volt-

age for a given condition, RL is the effective total resistance
‫اﻟﻣ‬

of the controlled output, Co1 is the controlled output capaci-

tance and Rc1 is the ESR of Co1.
Figure 15 shows the variation of the control-to-output trans-
‫ﺻ‬

fer function of a flyback converter in DCM for different

loads. Contrary to the flyback converter in CCM, there is no
RHP zero and the DC gain does not change as the input volt-
age varies. As can be seen, the overall gain except for the DC
‫رى‬

gain is highest at the full load condition.

The feedback compensation network transfer function of fig-
ure 12 is obtained as
AN4137 APPLICATION NOTE

When the input voltage and the load current vary over a wide
range, it is not easy to determine the worst case for the feed-
ˆ w i 1 + s ⁄ w zc
v FB back loop design. The gain together with zeros and poles
- = - ----- ⋅ ---------------------------
-------- (35)
v o1ˆ s 1 + 1 ⁄ w pc vary according to the operating condition. Moreover, even
though the converter is designed to operate in CCM or at the
RB 1 1
where w i = ----------------------
- , w zc = --------------------------------- , w pc = --------------- boundary of DCM and CCM in the minimum input voltage
R1 RD CF ( R F + R 1 )C F RB CB
and full load condition, the converter enters into DCM
changing the system transfer functions as the load current
and RB is the internal feedback bias resistor of FPS, which is decreases and/or input voltage increases.
typically 2.8kΩ and R1, RD, RF, CF and CB are shown in fig- One simple and practical way to this problem is designing
ure 12. the feedback loop for low input voltage and full load condi-
tion with enough phase and gain margin. When the converter
operates in CCM, the RHP zero is lowest in low input volt-
40 dB age and full load condition. The gain increases only about

‫م‬
fp 6dB as the operating condition is changed from the lowest
20 dB
input voltage to the highest input voltage condition under
universal input condition. When the operating mode changes

/
fp
High input voltage from CCM to DCM, the RHP zero disappears making the
0 dB
system stable. Therefore, by designing the feedback loop

‫اﺣ‬
Low input voltage
fz
with more than 45 degrees phase margin in low input voltage
-20 dB
frz
and full load condition, the stability over all the operating
frz ranges can be guaranteed.

‫ﻣد‬
fz
-40 dB
The procedure to design the feedback loop is as follows
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz

Figure 13. CCM flyback converter control-to output trans- (a) Determine the crossover frequency (fc). For CCM mode
flyback, set fc below 1/3 of right half plane (RHP) zero to
fer function variation for different input voltages
‫ﯾ‬
minimize the effect of the RHP zero. For DCM mode fc can
‫وﺳ‬
be placed at a higher frequency, since there is no RHP zero.
40 dB
fp Light load (b) When an additional LC filter is employed, the crossover
frequency should be placed below 1/3 of the corner fre-
quency of the LC filter, since it introduces a -180 degrees
‫ف‬

20 dB

fp phase drop. Never place the crossover frequency beyond the

0 dB corner frequency of the LC filter. If the crossover frequency
Heavy load is too close to the corner frequency, the controller should be
designed to have a phase margin greater than 90 degrees
‫اﻟﻣ‬

-20 dB
when ignoring the effect of the post filter.
fz frz f rz
-40 dB (c) Determine the DC gain of the compensator (wi/wzc) to
cancel the control-to-output gain at fc.
‫ﺻ‬

1Hz 10Hz 100Hz 1kHz 10kHz 100kHz

Figure 14. CCM flyback converter control-to output trans- (d) Place a compensator zero (fzc) around fc/3.
fer function variation for different loads (e) Place a compensator pole (fpc) above 3fc.
‫رى‬

40 dB
Loop gain T
40 dB
fp
20 dB fp
20 dB fzc
Heavy load
Compensator
0 dB fp fpc
0 dB
fc
-20 dB fz Control to output
Light load
frz
-20 dB
fz
-40 dB
fz
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz -40 dB

Figure 15. DCM flyback converter control-to output trans- 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
fer function variation for different loads
Figure 16. Compensator design

©2003 Fairchild Semiconductor Corporation

10
 APPLICATION NOTE AN4137

ing the startup. While, too large a capacitor may increase the
When determining the feedback circuit component, there are startup time.
some restrictions as follows. (b) Vcc resistor (Ra) : The typical value for Ra is 5-20Ω. In
the case of multiple outputs flyback converter, the voltage of
(a) The voltage divider network of R1 and R2 should be
the lightly loaded output such as Vcc varies as the load cur-
designed to provide 2.5V to the reference pin of the KA431.
rents of other outputs change due to the imperfect coupling
The relationship between R1 and R2 is given as
of the transformer. Ra reduces the sensitivity of Vcc to other
outputs and improves the regulations of Vcc.
‫ﻗﺎﻧون ﺣﺳﺎب ﻣﻘﺎوﻣﺔ‬ 2.5 ⋅ R 1
‫ﻣﺟزئ اﻟﺟﮭد ﻟﻠﻔﯾدﺑﺎك‬ R 2 = -----------------------
- (36)
Vo1 – 2.5

where Vo1 is the reference output voltage.

(b) The capacitor connected to feedback pin (CB) is related to

‫م‬
the shutdown delay time in an overload condition by

/
‫اﺣ‬
T delay = ( V SD – 2.5 ) ⋅ C B ⁄ I delay (37

where VSD is the shutdown feedback voltage and Idelay is the

shutdown delay current. These values are given in the data
‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
sheet. In general, a 10 ~ 50 ms delay time is typical for most
applications. Because CB also determines the high frequency
pole (wpc) of the compensator transfer function as shown in
equation (36), too large a CB can limit the control bandwidth
‫ف‬

by placing wpc at too low a frequency. Typical value for CB is

10-50nF.
(c) The resistors Rbias and RD used together with the opto-
coupler H11A817A and the shunt regulator KA431 should
‫اﻟﻣ‬

be designed to provide proper operating current for the

KA431 and to guarantee the full swing of the feedback volt-
age for the FPS device chosen. In general, the minimum
‫ﺻ‬

cathode voltage and current for the KA431 are 2.5V and
1mA, respectively. Therefore, Rbias and RD should be
designed to satisfy the following conditions.
‫رى‬

V o1 – V OP – 2.5
----------------------------------------- > I FB (38)
RD
V OP
-------------
- > 1mA (39)
R bias
where Vo1 is the reference output voltage, VOP is opto-diode
forward voltage drop, which is typically 1V and IFB is the
feedback current of FPS, which is typically 1mA. For exam-
ple, Rbias< 1kΩ and RD < 1.5kΩ for Vo1=5V.

Miscellaneous
(a) Vcc capacitor (Ca) : The typical value for Ca is 10-50uF,
which is enough for most application. A smaller capacitor
than this may result in an under voltage lockout of FPS dur-

©2003 Fairchild Semiconductor Corporation

11
AN4137 APPLICATION NOTE

- Summary of symbols - ‫ﻣﻠﺧص اﻟرﻣوز اﻟﺗﻰ ﺟﺎءت ﻓﻰ اﻟﻣوﺿوع‬

Aw : Winding window area of the core in mm2

Ae : Cross sectional area of the core in mm2
Bsat : Saturation flux density in tesla.
Co(n) : Output capacitor of the n-th output
Dmax : Maximum duty cycle ratio
Eff : Estimated efficiency
fL : Line frequency
fs : Switching frequency of FPS
Idspeak : Maximum peak current of MOSFET
Idsrms : RMS current of MOSFET

‫م‬
Ids2 : Maximum peak drain current at the maximum input voltage condition.
Iover : FPS current limit level.

/
Isec(n)rms : RMS current of the secondary winding for the n-th output
ID(n)rms : Maximum rms current of the rectifier diode for the n-th output

‫اﺣ‬
Icap(n)rms : RMS Ripple current of the output capacitor for the n-th output
Io(n) : Output load current for the n-th output
: Load occupying factor for the n-th output

‫ﻣد‬
KL(n)
KRF : Current ripple factor
Lm : Transformer primary side inductance
Llk : Transformer primary side leakage inductance
‫ﯾ‬
Losssn : Maximum power loss of the snubber network in normal operation
‫وﺳ‬
Npmin : The minimum number of turns for the transformer primary side to avoid saturation
Np : Number of turns for primary side
Ns1 : Number of turns for the reference output
: Number of turns for the n-th output
‫ف‬

Ns(n)
Po : Maximum output power
Pin : Maximum input power
Rc(n) : Effective series resistance (ESR) of the n-th output capacitor.
: Snubber resistor
‫اﻟﻣ‬

Rsn
RL : Effective total output load resistor of the controlled output
Vlinemin : Minimum line voltage
‫ﺻ‬

Vlinemax : Maximum line voltage

VDCmin : Minimum DC link voltage
VDCmax : Maximum DC line voltage
Vdsnom : Maximum nominal MOSFET voltage
‫رى‬

Vo1 : Output voltage of the reference output.

VF1 : Diode forward voltage drop of the reference output.
Vcc* : Nominal voltage for Vcc
VFa : Diode forward voltage drop of Vcc winding
VD(n) : Maximum voltage of the rectifier diode for n-th output
∆Vo(n) : Output voltage ripple for the n-th output
VRO : Output voltage reflected to the primary
Vsn : Snubber capacitor voltage under minimum input voltage and full load condition
Vsn2 : Snubber capacitor voltage under maximum input voltage and full load condition
∆Vsn : Maximum Snubber capacitor voltage ripple
Vdsmax : Maximum voltage stress of the MOSFET

©2003 Fairchild Semiconductor Corporation

12
‫‪APPLICATION NOTE‬‬ ‫‪AN4137‬‬

‫ﻣﺛﺎل ﻋﻠﻰ ﺗﺻﻣﯾم ﺑﺎور ﻣن اﻟﺷرﻛﺔ ﺑﺎﺳﺗﺧدام اﻻﯾﺳﻰ ‪FSDM07652R‬‬

‫ﺧرج ﻣﺗﻌدد‬
‫اﻟﺟﮭﺎز‬ ‫رﻗم اﻻﯾﺳﻰ‬ ‫ﻗدرة اﻟﺧرج‬ ‫ﺟﮭد اﻟدﺧل‬ ‫اﻗﺻﻰ ﺟﮭد وﺗﯾﺎر ﻟﻠﺧرج‬ ‫اﻟرﯾﺑل‬

‫)‪3.3V (2A‬‬ ‫‪± 5%‬‬

‫رﺳﯾﻔر‬ ‫)‪5V (2A‬‬ ‫‪± 5%‬‬
‫‪Set-top Box‬‬ ‫‪FSDM07652R‬‬ ‫‪47W‬‬ ‫‪85V-265VAC‬‬ ‫)‪12V (1.5A‬‬ ‫‪± 5%‬‬
‫)‪18V (0.5A‬‬ ‫‪±5%‬‬
‫)‪33V (0.1A‬‬ ‫‪±5%‬‬

‫م‬
‫اﻗل ﺟﮭد دﺧل ﻣﺗردد‬ ‫‪85 V.rms‬‬
‫اﻗﺻﻰ ﺟﮭد دﺧل ﻣﺗردد‬

‫‪/‬‬
‫‪265 V.rms‬‬
‫ﺗردد ﺟﮭد اﻟدﺧل‬ ‫‪60 Hz‬‬
‫ﺟﮭد اﻟﺧرج‬ ‫ﻗدرة اﻟﺧرج‬ ‫ﻣﻌﺎﻣل اﻟﺗﯾﺎر‬

‫اﺣ‬
‫ﺗﯾﺎر اﻟﺧرج‬
‫)‪Vo(n‬‬ ‫)‪Io(n‬‬ ‫)‪Po(n‬‬ ‫)‪KL(n‬‬
‫ﺧرج ‪ 1‬ﺳﯾﺎﺧذ ﻣﻧﮫ اﻟﻔﯾدﺑﺎك ‪1st output for feedback‬‬ ‫‪3.3‬‬ ‫‪V‬‬ ‫‪2.00‬‬ ‫‪A‬‬ ‫‪7‬‬ ‫‪W‬‬ ‫‪14‬‬ ‫‪%‬‬
‫ﺧرج ‪2‬‬

‫ﻣد‬
‫‪2nd output‬‬ ‫‪5‬‬ ‫‪V‬‬ ‫‪2.00‬‬ ‫‪A‬‬ ‫‪10‬‬ ‫‪W‬‬ ‫‪21‬‬ ‫‪%‬‬
‫‪3rd output‬‬ ‫ﺧرج ‪3‬‬ ‫‪12‬‬ ‫‪V‬‬ ‫‪1.50‬‬ ‫‪A‬‬ ‫‪18‬‬ ‫‪W‬‬ ‫‪38‬‬ ‫‪%‬‬
‫ﺧرج ‪4‬‬
‫‪4th output‬‬ ‫‪18‬‬ ‫‪V‬‬ ‫‪0.50‬‬ ‫‪A‬‬ ‫‪9‬‬ ‫‪W‬‬ ‫‪19‬‬ ‫‪%‬‬
‫ﺧرج ‪5‬‬
‫‪5th output‬‬ ‫‪33‬‬ ‫‪V‬‬ ‫‪0.10‬‬ ‫‪A‬‬ ‫‪3‬‬ ‫‪W‬‬ ‫‪7‬‬ ‫‪%‬‬
‫ﺧرج ‪6‬‬
‫‪6th output‬‬ ‫‪V‬‬ ‫‪A‬‬ ‫‪0‬‬ ‫‪W‬‬ ‫‪0‬‬ ‫‪%‬‬
‫ﯾ‬
‫اﻗﺻﻰ ﻗدرة ﺧرج = )‪Maximum output power (Po‬‬ ‫‪46.9 W‬‬
‫وﺳ‬
‫)‪Estimated efficiency (Eff‬‬ ‫اﻟﻛﻔﺎﺋﺔ‬ ‫‪70 %‬‬
‫= )‪Maximum input power (Pin‬‬ ‫اﻗﺻﻰ ﻗدرة ﻟﻠدﺧل‬ ‫‪67.0 W‬‬
‫ﺗم ﺣﺳﺎب ‪ 2‬ﻣﯾﻛرو ﻟﻛل واﺣد وات ﺗﺻﺑﺢ ﺳﻌﺔ‬
‫ف‬

‫اﻟﻣﻛﺛف = ‪ 150 ......134=2*67‬ﻣﯾﻛرو‬

‫ﺗﻌﯾﯾن ﺳﻌﺔ وﺟﮭد ﻣﻛﺛف اﻟﺗﻧﻌﯾم اﻟرﺋﯾﺳﻰ‬

‫)‪DC link capacitor (CDC‬‬ ‫‪150 uF‬‬ ‫ﺳﻌﺔ ﻣﻛﺛف اﻟﺧط‬
‫اﻟﻣ‬

‫‪min‬‬
‫= ) ‪Minimum DC link voltage (VDC‬‬ ‫‪92 V‬‬ ‫اﻗل ﺟﮭد ﻣﺳﺗﻣر ﻋﻠﻰ ﻣﻛﺛف اﻟﺗﻧﻌﯾم اﻟرﺋﯾﺳﻰ‬
‫‪max‬‬
‫=) ‪Maximum DC link voltage (VDC‬‬ ‫‪375 V‬‬ ‫اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻋﻠﻰ اﻟﻣﻛﺛف اﻟرﺋﯾﺳﻰ‬
‫ﺻ‬

‫ﺗﻌﯾﯾن اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬

‫)‪Maximum duty ratio (Dmax‬‬ ‫‪0.48‬‬ ‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬
‫رى‬

‫‪nom‬‬
‫‪Max nominal MOSFET voltage‬‬ ‫=‬ ‫) ‪(Vds‬‬ ‫‪460 V‬‬ ‫اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻋﻠﻰ اﻟﻣوﺳﻔت‬
‫=)‪Output voltage reflected to primary (VRO‬‬ ‫‪85 V‬‬ ‫ﺟﮭد اﻟﺧرج اﻟﻣرﺗد ﻋﻠﻰ اﻟﻣوﺳﻔت‬

‫×‪☞ Dmax is set to be 0.48 so that Vdsnom would be about 70% of BVdss (650V‬‬ ‫)‪×0.7=455V‬‬
‫ﺗم اﺧﺗﯾﺎر اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل = ‪ 0.48‬ﺣﺗﻰ ﯾﺻﺑﺢ اﻟﺟﮭد اﻟواﻗﻊ ﻋﻠﻰ اﻟﻣوﺳﻔت ‪ 70‬ﻓﻰ اﻟﻣﯾﺔ ﻣن ﺟﮭد اﻧﮭﯾﺎر اﻟﻣوﺳﻔت )‪ 650‬ﻓوﻟت(‬
‫ﺗﻌﯾﯾن ﻣﺣﺎﺛﺔ ﻣﻠﻔﺎت اﻻﺑﺗداﺋﻰ‬
‫)‪Switching frequency of FPS (fs‬‬ ‫ﺗردد اﻟﺗﻘطﯾﻊ ‪66 kHz‬‬ ‫) ‪K RF = 1 ( DCM‬‬
‫) ‪K RF < 1 (CCM‬‬
‫)‪Ripple factor (KRF‬‬ ‫ﻣﻌﺎﻣل اﻟرﯾﺑل ‪0.33‬‬
‫= )‪Primary side inductance (Lm‬‬ ‫ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ ‪671 uH‬‬ ‫‪∆I‬‬ ‫‪I EDC‬‬
‫= )‪Maximum peak drain current (Idspeak‬‬ ‫‪2.01 A‬‬ ‫اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت‬
‫‪rms‬‬
‫= )‪RMS drain current (Idsrms‬‬ ‫‪1.07 A‬‬ ‫ﺗﯾﺎر ‪ RMS‬ﻟﻠﻣوﺳﻔت‬ ‫= ‪K RF‬‬
‫‪∆I‬‬
‫‪##‬‬ ‫‪2I EDC‬‬
‫‪Maximum DC link voltage in CCM‬‬ ‫)‪(VDCCCM‬‬ ‫‪375 V‬‬ ‫اﻗﺻﻰ ﺟﮭد دﺧل ﻣﺳﺗﻣر‬

‫‪©2002 Fairchild Semiconductor Corporation‬‬

‫‪13‬‬
AN4137 APPLICATION NOTE

‫ﺗﻌﯾﯾن رﻗم اﻻﯾﺳﻰ اﻟﻣﻧﺎﺳﺑﺔ ﺑﺎﻋﺗﺑﺎر ﺗﯾﺎر اﻟدرﯾن‬

Typical current limit of FPS (Iover) 2.50 A ‫اﻗﺻﻰ ﺗﯾﺎر ﻟﻼﯾﺳﻰ ﻣن اﻟداﺗﺎﺷﯾت‬
Minimum Iover considering tolerance of 12% 2.20 A > 2.01 A ‫ ﻓﻰ اﻟﻣﯾﺔ‬12 ‫ﺑﺗﺧﻔﯾض‬
->O.K.
☞ Since the maximum peak drain current (Idspeak) is 2.0A, FSDM07652R is chosen, whose current limit
level (Iover) is 2.5A. The current limit tolerance (12%) is considered.
‫ اﻣﺑﯾر وھﻰ ﻣﻧﺎﺳﺑﺔ‬2.5 ‫ ﻻن اﻗﺻﻰ ﺗﯾﺎر ﻟﮭﺎ‬FSDM07652 ‫ﺗم اﺧﺗﯾﺎر اﻻﯾﺳﻰ‬

‫ﺗﻌﯾﯾن اﻟﻘﻠب اﻟﻣﻧﺎﺳب ﻟﻠﻣﺣول واﻗل ﻋدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ‬

Saturation flux density (Bsat) 0.35 T ‫ﻛﺛﺎﻓﺔ اﻟﻔﯾض ﻟﻠﺗﺷﺑﻊ‬
Cross sectional area of core (Ae) 109.4 mm
2
‫ﻣﺳﺎﺣﺔ ﻣﻘطﻊ اﻟﻘﻠب‬
Minimum primary turns (Npmin)= 43.8 T ‫اﻗل ﻋدد ﻟﻔﺎت اﺑﺗداﺋﻰ‬

‫م‬
‫ﺗم اﺧﺗﯾﺎر اﻟﻘﻠب ﺣﺳب ﻗدرة اﻟﺑﺎور اوﻻ ﺛم ﯾﺗم اﺳﺗﺧراج اﻟﺑﯾﺎﻧﺎت اﻟﻣوﺟودة ﻣن اﻟداﺗﺎﺷﯾت‬

/
‫ ﺣﺗﻰ ﺗﻛون ﻣﺳﺎﺣﺔ اﻟﺷﺑﺎك ﻣﻧﺎﺳﺑﺔ ﻟﻠﻣﻠﻔﺎت‬1 ‫ وھو اﻛﺑر ﻗﻠﯾﻼ ﻣن اﻟﻘﻠب اﻟﻣوﺟود ﻓﻰ ﺟدول‬EER3530 ‫ﺗم اﺧﺗﯾﺎر اﻟﻘﻠب‬

‫اﺣ‬
‫ﺗﻌﯾﯾن ﻋدد اﻟﻠﻔﺎت ﻟﻛل ﻣﻠف ﺧرج‬
‫ﺟﮭد اﻟﺧرج‬ ‫ﺟﮭد اﻟداﯾود‬ ‫ﻋدد اﻟﻠﻔﺎت‬

‫ﻣد‬
Vo(n) VF(n) # of turns
Vcc (Use Vcc start voltage) ‫ﻣﻠﻔﺎت اﻟﺗﺷﻐﯾل‬ 12 V 1.2 V 6.9 => 7 T
1st output for feedback ‫ﻣﻠﻔﺎت ﺧط اﻟﻔﯾدﺑﺎك‬ 3.3 V 0.5 V 2 => 2 T
2nd output 2 ‫ﻣﻠﻔﺎت اﻟﺧط‬ 5 V 0.5 V 2.9 => 3 T
3 ‫ﺧرج‬
‫ﯾ‬
3rd output 12 V 1.2 V 6.9 => 7 T
4 ‫ﺧرج‬
‫وﺳ‬
4th output 18 V 1.2 V 10.1 => 10 T
5th output 5 ‫ﺧرج‬ 33 V 1.2 V 18.0 => 18 T
6 ‫ﺧرج‬
6th output 0 V 0V 0.0 => 0 T
VF : Forward voltage drop of rectifier diode Primary turns (Np)= 45 T ‫ﻋدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ‬
‫ف‬

--->enough turns
Ungapped AL value (AL) ‫ﺑﺎﻟﻘﻠب‬ ‫ﺧﺎص‬
‫ﺑﺎﻟﺛﻐرة‬ ‫ﻣﻌﺎﻣلﺧﺎص‬
‫ﻣﻌﺎﻣل‬ 2130 nH/T2
Gap length (G) ; center pole gap = 0.34631 mm ‫طول اﻟﺛﻐرة اﻟﮭواﺋﯾﺔ‬

☞ In general, the optimum turn ratio between 5V and 3.3V is 3/2, considering the diode forward voltage
‫اﻟﻣ‬

drop.
‫ﺻ‬

‫ﺗﻌﯾﯾن ﺣﺟم اﻟﺳﻠك ﻟﻛل ﻣﻠف ﻟﻠﻣﺣول‬

rms 2
Diameter Parallel ID(n)rms (A/mm2)
‫رى‬

Primary winding ‫ﻣﻠف اﻻﺑﺗداﺋﻰ‬ 0.5 mm 1T 1.1 A 5.44

Vcc winding ‫ﻣﻠف اﻟﺗﺷﻐﯾل‬ 0.3 mm 2T 0.1 A 0.71
1st output winding 1 ‫ﺧرج‬ 0.4 mm 4T 3.5 A 6.97
2nd output winding 0.4 mm 4T 3.7 A 7.30
3rd output winding 0.4 mm 3T 2.8 A 7.30
4th output winding 0.4 mm 2T 0.9 A 3.76
5th output winding 0.4 mm 1T 0.2 A 1.55
6th output winding 6 ‫ﺧرج‬ mm T ##### A #####
Copper area (Ac) = ‫ﻣﺳﺎﺣﺔ اﻟﻧﺣﺎس‬ 19.70 mm2
Fill factor (KF) ‫ﻣﻌﺎﻣل اﻟﻣﻠﺊ ﻟﻠﻣﻠﻔﺎت‬ 0.15
2
Required window area (Awr) ‫ﻣﺳﺎﺣﺔ اﻟﺷﺑﺎك‬ 131.33 mm

‫ اﻣﺑﯾر ﻟك ﻣﯾﻠﻠﻰ ﻋﻧد اﺧﺗﯾﺎر ﻗطر اﻟﺳﻠك‬5 ‫ ﻓوﻟت ﻗﻠﯾﻠﺔ ﻓﯾﻣﻛن اﺳﺗﺧدام ﻛﺛﺎﻓﺔ ﺗﯾﺎر اﻛﺑر ﻣن‬3.3 ‫ و‬5 ‫ﻧظرا ﻻن ﻋدد ﻟﻔﺎت اﻟﺧرج‬
‫ ﻧظرا ﻻن اﻟﺧرج ﻣﺗﻌدد‬0.15 ‫ﺗم اﺧﺗﯾﺎر ﻣﻌﺎﻣل ﻣﻠﺊ‬
©2002 Fairchild Semiconductor Corporation
14
APPLICATION NOTE AN4137

‫ﺗﻌﯾﯾن داﯾودات ﺧطوط اﻟﺧرج‬

VD(n) ‫اﻟﺟﮭد اﻟﻌﻛﺳﻰ‬ ID(n)rms ‫ﺗﯾﺎر اﻟداﯾود‬

Vcc diode ‫داﯾود اﻟﺗﺷﻐﯾل‬ 70 V 0.10 A
1st output diode 1 ‫داﯾود اﻟﺧرج‬ 20 V 3.50 A
2nd output diode 29 V 3.67 A
3rd output diode 70 V 2.75 A
4th output diode 103 V 0.95 A
5th output diode 184 V 0.19 A
6th output diode 6 ‫داﯾود اﻟﺧرج‬ 0 V ##### A
‫ﻣواﺻﻔﺎت ورﻗم اﻟداﯾود‬
Vcc winding ‫اﻟﺗﺷﻐﯾل‬ UF4003 (200V /1A, VF=1V) Ultra Fast Recovery Diode ‫ﻓﺎﺋق اﻟﺳرﻋﺔ‬

‫م‬
1st output (3.3V)
1 ‫ﺧرج‬
SB540 (40V/5A, VF=0.55V) × 2 Schottky Barrier Diode ‫ﺷوﺗﻛﻰ‬
2nd output (5V) SB560 (60V/5A, VF=0.67V) × 2 Schottky Barrier Diode ‫ﺷوﺗﻛﻰ‬

/
3rd output (12V) EGP30D (200V/3A, VF=0.95V) Ultra Fast Recovery Diode ‫ﻓﺎﺋق‬
4st output (18V) EGP20D (200V/2A, VF=0.95V) Ultra Fast Recovery Diode ‫ﻓﺎﺋق‬

‫اﺣ‬
5st output (30V) 5 ‫ﺧرج‬ UF4004 (400V /1A, VF=1V) Ultra Fast Recovery Diode ‫ﻓﺎﺋق‬
‫رﻗم اﻟداﯾود وﺟﮭده اﻟﻌﻛﺳﯩﻰ وﺗﯾﺎره واﻟﺟﮭد اﻟﻣﺎﻣﻰ‬

1st output capacitor

‫ﯾ‬
1 ‫ﻣﻛﺛف اﻟﺧرج‬
‫ﻣد‬
‫ﺗﻌﯾﯾن ﻣﻛﺛﻔﺎت اﻟﺧرج‬
‫ﺳﻌﺔ اﻟﻣﻛﺛف‬
Co(n)
2000 uF
ESR ‫اﻟﻣﻘﺎوﻣﺔ‬
RC(n)
100 mΩ 2.9
‫رﯾﺑل اﻟﺗﯾﺎر‬
Icap(n)
A
‫رﯾﺑل اﻟﺟﮭد‬
ΔVo(n)
0.64 V
‫وﺳ‬
2nd output capacitor 2000 uF 100 mΩ 3.1 A 0.67 V
3rd output capacitor 330 uF 300 mΩ 2.3 A 1.53 V
4th output capacitor 470 uF 300 mΩ 0.8 A 0.52 V
5th output capacitor 47 uF 480 mΩ 0.2 A 0.18 V
‫ف‬

6th output capacitor 6 ‫ﻣﻛﺛف اﻟﺧرج‬ uF mΩ ##### A ##### V

Since the voltage ripples for 3.3V, 5V and 12V exceed the ripple spec of ± 5%, additional LC filter stage
should be used for these three outputs. 220uF capacitor together with 2.2uH inductor are used for the post
filter. To attenuate the voltage ripple caused by switching, the corner frequency of the post filter (fo) is set
‫اﻟﻣ‬

at about one decade below the switching frequency.

1 10 6
fo = = = 7.2kHz
2π L p1C p1 2π 2.2 × 220
‫ﺻ‬

11. Design RCD snubber ‫ﺗﻌﯾﯾن داﺋرة اﻟﺳﻧوﺑر‬

Primary side leakage inductance (Llk) 4.5 uH
‫رى‬

Maximum Voltage of snubber capacitor (Vsn) 190 V

Maximum snubber capacitor voltage ripple 5 %
Snubber resistor (Rsn)= ‫ﻣﻘﺎوﻣﺔ اﻟﺳﻧوﺑر‬ 33.1 ㏀
Snubber capacitor (Csn)= ‫ﻣﻛﺛف اﻟﺳﻧوﺑر‬ 9.2 nF 0.185
Power loss in snubber resistor (Psn)= 1.1 W (In Normal Operation) ‫اﻟﻘدرة اﻟﻣﻔﻘودة ﻋﻠﻰ اﻟﺳﻧوﺑر‬

Peak drain current at VDCmax (Ids2) = 1.75 A ‫اﻗﺻﻰ ﺗﯾﺎر ﻟﻠدرﯾن ﻋﻧد اﻗﺻﻰ ﺟﮭد دﺧل ﻣﺳﺗﻣر‬

Max Voltage of Csn at VDCmax (Vsn2)= 172 V ‫اﻗﺻﻰ ﺟﮭد ﯾﻘﻊ ﻋﻠﻰ ﻣﻛﺛف اﻟﺳﻧوﺑر ﻋﻧد اﻗﺻﻰ ﺟﮭد دﺧل‬
max
Max Voltage stress of MOSFET (Vds )= 547 V ‫اﻗﺻﻰ ﺟﮭد ﺿﺎﻏط ﻋﻠﻰ درﯾن اﻟﻣوﺳﻔت اﺛﻧﺎء ﺗوﻗﻔﮫ‬

☞ The snubber capacitor and snubber resistor are chosen as 10nF and 33kΩ
Ω, respectively. The maximum
voltage stress on the MOSFET is designed to be 84% of 650V BVdss voltage of the FSDM07652R. The
actual Vdsmax would be lower than this.

©2002 Fairchild Semiconductor Corporation

15
AN4137 APPLICATION NOTE

12. Design Feedback control loop ‫ﺗﻌﯾﯾن ﺧط اﻟﻔﯾدﺑﺎك‬

Control-to-output DC gain = 2
Control-to-output zero (wz) = 5000 rad/s => fz= 796 Hz
Control-to-output RHP zero (wrz)= 694765 rad/s => frz= 110,631 Hz
Control-to-output pole (wp)= 2153 rad/s => fp= 343 Hz
FPS vo1' vo1
Voltage divider resistor (R1) 1 ‫ﻣﻘﺎوﻣﺔ ﻣﺟزئ اﻟﺟﮭد‬ 5.6 ㏀ vFB RD
2 ‫ﻣﻘﺎوﻣﺔ اﻟﻣﺟزئ‬ ibias
Voltage divider resistor (R2)= 18 ㏀
iD Rbias
Opto coupler diode resistor (RD) ‫ﻣﻘﺎوﻣﺔ ﺣﻣﺎﯾﺔ اﻟﻠﯾد‬ 1 ㏀ CB
1:1
B R1
KA431 Bias resistor (Rbias) 431 ‫ﻣﻘﺎوﻣﺔ ﺣﻣﺎﯾﺔ اﻟﻣﻧظم‬ 1.2 ㏀ CF RF

‫م‬
KA431
Feeback pin capacitor (CB) = ‫ﻣﻛﺛف ﻣدﺧل اﻟﻔﯾدﺑﺎك‬ 33 nF
Feedback Capacitor (CF) = 431 ‫ﻣﻛﺛف ﺧط اﻟﻣﻧظم‬ 47 nF R2

Feedback resistor (RF) = 431 ‫ﻣﻘﺎوﻣﺔ ﻣﻊ اﻟﻣﻧظم‬ 1.2 ㏀

/
Feedback integrator gain (wi) = 11398 rad/s => fi= 1,815 Hz

‫اﺣ‬
Compensator zero (wzc)= 3129 rad/s => fzc= 498 Hz
Compensator pole (wpc)= 10101 rad/s => fpc= 1,608 Hz

60

40
‫ﯾ‬ 16 3.64105
25 3.63
40 3.60099
‫ﻣد‬ 41
37
33
44.7
40.9
16 -2 -88.7
Control-to-output
25 -2
36.8 Compensator
40 -4 -86.8
-88
#
#
#
‫وﺳ‬
63 3.53167 29 32.8 T (Closed 63loop
-6 gain)-85 #
Gain (dB)

20
100 3.36222 25 28.7 100 -9 -82.2 #
160 2.96516 21 24.4 160 ## -77.9 #
0 250 2.20575 18 20.3 250 ## -72.2 #
‫ف‬

10 100 400 1000

0.89557 15 15.9
10000 400 ## 100000
-65.2 #
630 -0.6501 13 12.1 630 ## -59.7 #
-20
1000 -2.0185 11 8.75 1000 ## -58.3 #
1600 -2.9016 9 5.74 1600 ## -62.1 #
-40 2500 -3.3275 6 2.74 2500 ## -68.5 #
‫اﻟﻣ‬

4000 -3.5257
frequency (Hz) 3 -0.8 4000 -8 -75.2 #
6300 -3.5983 -1 -4.5 6300 -7 -80.2 #
10000 -3.6107 -5 -8.4 10000 -8 -83.7 #
0
‫ﺻ‬

16000 -3.5697 -9 -12 16000 ## -86 #

10 100 1000 10000 100000
25000 -3.4485 # -16 25000 ## -87.5 #
-30
40000 -3.1334 # -20 40000 ## -88.4 #
63000 -2.448 # -23 63000 ## -89 #
‫رى‬ Phase (degree)

-60
100000 -1.0745 # -26 1E+05 ## -89.4 #
-90

-120

-150

-180
frequency (Hz)

☞ The control bandwidth is 4kHz. Since the crossover frequency is too close to the corner frequency of the
post filter (fo=7.2 kHz), the controller is designed to have enough phase margin when ignoring the effect of
the post filter.

©2002 Fairchild Semiconductor Corporation

16
 ‫ﻣﺧطط اﻟﺗﺻﻣﯾم‬
APPLICATION NOTE AN4137

Design Summary
• For the FPS, FSDM07652R is chosen. This device has a fixed switching frequency of 66kHz. Startup and soft-start circuits
are implemented inside the device.
• To limit the current, 10 ohms resistors (Ra and Rdamp) are used in series with Da and DR5. These damping resistors improve
the regulations of the very lightly loaded outputs.

Figure 17 shows the final schematic of the flyback converter designed by FPS Design Assistant.

‫ﻣﻘﺎوﻣﺔ ﺗﺣﺟﯾم اﻟﺗﯾﺎر ﺣﯾث ﺗﻘوم ﺑﺗﺣﺳﯾن ﺗﻧظﯾم اﻟﺟﮭد ﻟﻼﺣﻣﺎل اﻟﺧﻔﯾﻔﺔ‬
VO5 33V
Rdamp 10
NS5 DR5
Co5 5 ‫ﺧرج‬
UF4004
47uF/ 50V

‫م‬
VO4 18V

/
EGP20D
DR4 Co4
NS4
470uF/25V 4 ‫ﺧرج‬

‫اﺣ‬
VO3 12V
Lp3 2.2 uH
DR3
3 ‫ﺧرج‬

‫ﻣد‬
EGP30D Cp3
Co3
NS3 220uF/ 25V
‫داﺋرة اﻟﺳﻧوﺑر‬ 330uF/25V

‫ﻗﻧطرة اﻟﺗوﺣﯾد‬
Rsn
10nF
GBLA06
‫ﻣﻛﺛف رﺋﯾﺳﻰ‬ Csn VO2 5V
‫ﯾ‬ 33k 1kV Np Lp2 2.2 uH
CDC 2W
DR2 2 ‫ﺧرج‬
‫وﺳ‬
SB560

NS2 Cp2
150uF/400V Co2
Dsn UF4007 1000uF× 2 /10V
220uF/ 10V

‫اﯾﺳﻰ اﻟﺑﺎور‬ 6 ‫درﯾن‬ VO1 3.3V

‫ف‬

Vstr Lp1 2.2 uH

1
1.5nF/275Vac Drain UF4003 DR1 SB540 1 ‫ﺧرج‬
Cp1
FPS R a 10 Da
CL2 CL2 NS1 Co1 220uF/ 10V
(DM07652R) Vcc 3
1000uF× 2 /10V

FB GND ‫ﻣﻠف اﻟﺗﺷﻐﯾل‬

Line Filter
Ca
‫اﻟﻣ‬

Na
(33mH) 4 2 ‫ﻣﻘﺎوﻣﺔ اﻟﻠﯾد‬ 431 ‫ﻣﻘﺎوﻣﺔ ﺗﺣدﯾد ﺗﯾﺎر‬
‫ﻓﯾدﺑﺎك‬ 33uF/35V 1k Rd
Rbias
CL1 0.47uF/275Vac
1k 5.6k
H11A817A
‫ﻟﯾد اﻟﻔﺗوﻛﺎﺑﻠر‬
‫ﺻ‬

R1

RL1 CB H11A817A
1.5M
1.2k 47nF ‫ﻣﺟزئ ﺟﮭد اﻟﻔﯾدﺑﺎك‬
33nF
NTC Fuse RF
5D-13 CF
‫رى‬

KA431
‫ﻓوﺗوﻛﺎﺑﻠر‬
431 ‫ﻣﻧظم اﻟﺟﮭد‬ 18k
AC line
R2

Figure 17. The final schematic of the flyback converter

©2003 Fairchild Semiconductor Corporation

17
AN4137 APPLICATION NOTE

Experimental Verification
In order to show the validity of the design procedure pre-
sented in this paper, the converter of the design example has
been built and tested. All the circuit components are used as
designed in the design example and the measured trans-
former characteristics are shown in table 3.
Figure 18 shows the FPS drain current and DC link voltage
waveforms at the minimum input voltage and full load con-
dition. As can be seen, the maximum peak drain current
(Idspeak) is 2A and the minimum DC link voltage (VDCmin) is
about 90V. The designed values are 2.01A and 92V, respec-
tively.

‫م‬
Figure 19 shows the FPS drain current and voltage wave-
forms at the minimum input voltage and full load condition.

/
As designed, the maximum duty ratio (Dmax) is about 0.5
and the maximum peak drain current (Idspeak) is 2A.

‫اﺣ‬
Figure 20 shows the FPS drain current and voltage wave- Figure 18. Waveforms of drain current and DC link
voltage at 85Vac and full load condition (time:2ms/div)
forms at the maximum input voltage and full load condition.
The maximum voltage stress on the MOSFET is about 520V,

‫ﻣد‬
which is lower than the designed value (547V). This is
because of the lossy discharge of the inductor or the stray
capacitance. Another reason is that the power conversion
efficiency at the maximum input voltage is higher than the
estimated efficiency used in step-1.
‫ﯾ‬
‫وﺳ‬
As calculated in design step-4, the converter operates at the
boundary between CCM and DCM under the maximum
input voltage and full load condition (The maximum DC link
voltage guaranteeing CCM at full load was obtained as 375V
‫ف‬

in design step-4).
Figure 21 shows the current and voltage waveforms of the
first output (3.3V) rectifier diode. The maximum reverse
voltage of this diode was calculated as 20V in step-9 and the
‫اﻟﻣ‬

measured value is 23V.

Table 4 shows the line regulation of each output. 3.3V and Figure 19. Waveforms of drain current and voltage
5V output shows ±3% and ±4% regulations, respectively. at 85Vac and full load condition (time : 5us/div)
‫ﺻ‬

Figure 22 shows the measured efficiency at the full load con-

dition for different input voltages. The minimum efficiency
is about 73% at the minimum input voltage condition better
than the 70% target efficiency specified in step-1.
‫رى‬

Core EER3530 (ISU ceramics)

Primary side 682 uH @ 70kHz
inductance
Leakage 4.5 uH @70kHz with all other
inductance windings shorted.
Resistance 0.76 Ω

Table 3. The measured transformer characteristics

Figure 20. Waveforms of drain current and voltage

at 265Vac and full load condition (time : 5us/div)

©2002 Fairchild Semiconductor Corporation

18
APPLICATION NOTE AN4137

Efficiency
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72

‫م‬
85 115 145 175 205 235 265
Input voltage (Vac)

/
Figure 22. Measured efficiency

‫اﺣ‬
Figure 21. Current and voltage waveforms of the first
output (3.3V) rectifier diode at 265Vac and full load
condition (time : 5us/div)

‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
Input Vo1 Vo2 Vo3 Vo4 Vo5
voltage (3.3V) (5V) (12V) (18V) (33V)
85Vac 3.21 V 5.18 V 12.88 V 19.7 V 35.7 V
-2.7 % 3.6 % 7.3 % 9.4 % 8.2 %
‫ف‬

115Vac 3.21 V 5.14 V 12.77 V 19.4 V 34.6 V

-2.7 % 2.8 % 6.4 % 7.8 % 4.8 %
145Vac 3.21 V 5.11 V 12.67 V 19.2 V 34.1 V
‫اﻟﻣ‬

-2.7 % 2.2 % 5.6 % 6.7 % 3.2 %

175Vac 3.21 V 5.09 V 12.57 V 19.1 V 33.8 V
-2.7 % 1.8 % 4.8 % 5.9 % 2.4 %
‫ﺻ‬

205Vac 3.21 V 5.08 V 12.52 V 19.0 V 33.6 V

-2.7 % 1.6 % 4.3 % 5.4 % 1.9 %
235Vac 3.21 V 5.07 V 12.48 V 18.9 V 33.5 V
‫رى‬

-2.7 % 1.4 % 4.0 % 5.1 % 1.6 %

265Vac 3.21 V 5.06 V 12.47 V 18.9 V 33.5 V
-2.7 % 1.2 % 3.9 % 5.1 % 1.4 %

Table 4. Line regulation of each output at full load

condition

©2002 Fairchild Semiconductor Corporation

19
AN4137 APPLICATION NOTE

by Hang-Seok Choi / Ph. D

FPS Application Group / Fairchild Semiconductor

Phone : +82-32-680-1383 Facsimile : +82-32-680-1317
E-mail : hschoi@fairchildsemi.co.kr

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‫ف‬
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‫رى‬

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www.fairchildsemi.com

1/13/04 0.0m 002

Stock#ANxxxxxxxxx
 2003 Fairchild Semiconductor Corporation
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‫رى‬

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