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Compal confidential
Schematics Document
2 2

Mobile Penryn uFCPGA with Intel

Cantiga_GM+ICH9-M core logic
2009-07-15
Blade 1.4 MV
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
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Compal confidential Montevina Consumer 14" UMA
CK505 72QFN
Clock Generator
Thermal Sensor Mobile Penryn
1 SLG8SP553V 1

EMC1402 uFCPGA-478 CPU P17

P06

P6, 7, 8

Fan conn P06 H_A#(3..35)

FSB
H_D#(0..63) 667/800/1066 MHz 1.05V
DDR3 800/1066MHz
LVDS Panel 1.5V DDR3 SO-DIMM X2
BANK 0, 1, 2, 3 P15, 16
Interface P19
Intel Cantiga MCH
Dual Channel
CRT FCBGA 1329
P18

Support V1.3 USB conn x1

P9,10, 11, 12, 13, 14 P30

2
HDMI P35 2

USB2.0 X12
DMI X4 C-Link BT Conn
P30

USB Camera
P19
PCI-E BUS*5 Azalia

Intel ICH9-M SATA Master-1

Finger print P30
SATA Slave
PCIE RTL8103EL Mini-Card Mini-Card mBGA-676
SATA Slave
CardReader (10/100M) TV-tuner or New Card P20,21,22,23
WLAN
JMB385 P27
Robson Audio CKT AMP & Audio Jack
P25 P26 P26 P26
Codec_IDT9271B7 TPA6017A2
P28 P29

5 in1 Slot RJ45/11 CONN LPC BUS MDC

P33 P25 P29
3 3

SATA HDD Connector

P24
ENE
KB926 SATA ODD ConnectorP24
SPI
RTC CKT. LED P32
P21 P33

Int.KBD e-SATA Connector P30

ACCELEROMETER-1 Touch Pad CONN. USB Board Conn
Dock P33 P32 USB conn x2 P30
ST P24
USB2.0*1

ACCELEROMETER-2 RGB SPI ROM Audio board

BOSCH P24
RJ45 SST25VF080P31 、CIR Conn P29

4
SPDIF 4

MIC*1
K/B backlight Conn LINE-OUT*1 Capsense switch Conn
P33
P33

Security Classification Compal Secret Data Compal Electronics, Inc.

2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P36 P34 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
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Sheet 2 of 45
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Voltage Rails O MEANS ON X MEANS OFF USB assignment:
: means Digital Ground USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
: means Analog Ground USB-3 Dock
power USB-4 Camera
plane USB-5 WLAN
+B +5VALW +1.8V +5VS @ : means just reserve , no build USB-6 Bluetooth
+3VS USB-7 Finger Printer
+3VALW +1.5VS
45@ : means need be mounted when 45 level assy or rework stage. USB-8 MiniCard(WWAN/TV)
+0.9V DEBUG@ : means just reserve for debug. USB-9 Express card
State +VCCP USB-10 X
+CPU_CORE
BATT @ : means need be mounted when 45 level assy or rework stage. USB-11 X
+2.5VS CONN@ : means ME part
+1.8VS
ESATA @ : means just reserve for ESATA PCIe assignment:
GS @ : means just reserve for G sensor PCIe-1 TV /WWAN/Robeson
S0 O O O O PCIe-2 X
FP @ : means just reserve for Finger Print PCIe-3 WLAN
S1 O O O O Multi @ : means just reserve for Multi Bay PCIe-4 GLAN (Realtek)
PCIe-5 Card reader
S3
NewC@ : means just reserve for New card PCIe-6 New Card
O O O X
DOCK@ : means just reserve for Docking
S5 S4/AC O O X X Main@ : means just reserve for Main stream
I2C / SMBUS ADDRESSING
S5 S4/ Battery only O X X X OPP@ : means just reserve for OPP
S5 S4/AC & Battery 2MiniC@ : means just reserve for 2nd Mini card slot DEVICE HEX ADDRESS
don't exist X X X X
1

PA @ : means just reserve for PA DDR SO-DIMM 0 A0 10100000 1

DDR SO-DIMM 1 A4 10100100

PR @ : means just reserve for PR CLOCK GENERATOR (EXT.) D2 11010010

SMBUS Control Table

SERIAL Thermal Cap sensor ： UMA GM PA FF (V)
43154432L01：
SOURCE INVERTER BATT EEPROM Sensor SODIMM CLK CHIP MINI CARD LCD board NEW CARD G sensor ： UMA GM PR FF (V)
43154432L02：
SMB_EC_CK1 ： UMA GL PR FF-
43154432L03：
SMB_EC_DA1
KB926 X V V X X X X X V X X ： UMA GM OPP
43154432L04： (V)
SMB_EC_CK2 ： UMA GL OPP
43154432L05：
KB926 X X X V X X X X X X X
SMB_EC_DA2 ：SA00001P930 (SI-1、
Cantiga GM45 B0(QR32)： 、SI-2)
SMB_CK_CLK1
ICH9 X X X X V V V X X V V ：
ICH9M A2 ES2 Base： 、SI-2)
SA00002AN10 (SI-1、
SMB_CK_DAT1 ：SA00002JT10 (PV-1)
Cantiga GM45 B-2 QS QT62：
LCD_CLK
Cantiga X X X X X X X V X X X ：SA00002JT50 (PV-2)
Cantiga GM45 B-3 QS QU36：
LCD_DAT ：SA00002JH00 (PV-1、
ICH9M A-3 QS - BASE QT09： 、PV-2)
：SA00002JJE0 (MV-1、
Cantiga GM45 B-3 QS SLB97： 、MV-2)
：SA00002JHB0 (MV-1、
ICH9M A-3 QS -BASE SLB8Q： 、MV-2)
：Main@/DEBUG@/DOCK@/NewC@/FP@/ESATA@/GS@/Multi@/2MiniC@/PA@
43154432L01：
：Main@/DEBUG@/DOCK@/NewC@/FP@/ESATA@/GS@/PR@
43154432L02： ：DA600007110 --->M/B
PCB：
：Main@/DEBUG@/DOCK@/NewC@/FP@/PR@
43154432L03： DAZ03V00200 --->Main
：OPP@/DEBUG@/PR@
43154432L04： DAZ03V00101 --->OPP
：OPP@/DEBUG@/PR@
43154432L05：

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom Montevina Blade UMA LA4105P 1.0

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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Date: Saturday, July 18, 2009 Sheet 3 of 45
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WWW.AliSaler.Com 60mA
+3VAUX_BT

50mA
Finger printer

25mA +3VS_DVDD
1A ALC268
D
+V_BATTERY Dock con D

20mA
+3VALW_EC
35mA
MDC 1.5 10mA
SPI ROM
177mA
0.3A ICH9 1A
INVPWR_B+ LVDS CON New card
300mA
LAN 278mA
AC VIN ICH9
1.7A 5.89A 3.39A
+3VALW +3VS 1.5A
2A 550mA +LCDVDD LVDS CON
B++ JMB385
250mA
+3VS_CK505
657mA ICH_VCC1_5
C
1A C

0.3A 2.2A ICH9 Mini card (WLAN)

+1.5VS 1.56A
ICH9 1A
Mini card (TV tu/WWAN/Robeson)

0.58A 1.3A 35mA +VDDA

+5VALW +5VS IDT 9271B7
B+
7A 10mA
+5VAMP

1.8A
ODD

700mA
B
SATA B
3.7A
3.7 X 3=11.1V MCH
1.8A
DC BATT Muti Bay
8 A
1.9A 12.11A DDR2 800Mhz 4G x2
B+++ +1.8V 50mA
PC Camera(4.75V)
50mA
+0.9V
1.17A
ICH9

4.7A 1.26A
1.05V_B+ +VCCP MCH

2.3A
CPU

2A 10mA 34A/1.025V
CPU_B+ +VCC_CORE CPU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power delevry
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0

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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, July 18, 2009 Sheet 4 of 45
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Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom Montevina Blade UMA LA4105P 1.0

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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Date: Saturday, July 18, 2009 Sheet 5 of 45
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WWW.AliSaler.Com +3VS

ITP-XDP Connector XDP_DBRESET# 1

@R1
@ R1
2 1K_0402_5%

Change value in 5/02 +VCCP

： follow check list ver:1.5 change to 51 ohm
PV：
04/29 MV1 R2~R8 change to 54.9 Ohm,
XDP_TDI R2 1 2 54.9_0402_1%
follow checklist 2.0
XDP_TMS R3 1 2 54.9_0402_1%
D D
XDP_TDO R4 1 2 54.9_0402_1%

XDP_TRST# R7 1 2 54.9_0402_1%
<9> H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS# XDP_TCK R8 1 2 54.9_0402_1%
A[3]# ADS# H_ADS# <9>

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
H_A#5 A[4]# BNR# H_BPRI# H_BNR# <9>
L4 A[5]# BPRI# G5 H_BPRI# <9>
H_A#6 K5 This shall place near CPU
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# <9>
H_A#8 N2 F21 H_DRDY#
H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# <9>
J1 A[9]# DBSY# E1 H_DBSY# <9>
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <9>
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# T1
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <21>
H_A#15 P1 Place TP with a
H_A#16 A[15]# H_LOCK#
R1 H4
H_ADSTB#0 M1
A[16]# LOCK# H_LOCK# <9> GND 0.1" away
<9> H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
H_REQ#0 RESET# H_RS#0 H_RESET# <9>
<9> H_REQ#0 K3 REQ[0]# RS[0]# F3 H_RS#0 <9>
H_REQ#1 H2 F4 H_RS#1
<9> H_REQ#1 H_REQ#2 REQ[1]# RS[1]# H_RS#2 H_RS#1 <9>
<9> H_REQ#2 K2 REQ[2]# RS[2]# G3 H_RS#2 <9>
H_REQ#3 J3 G2 H_TRDY#
<9> H_REQ#3 H_REQ#4 REQ[3]# TRDY# H_TRDY# <9>
<9> H_REQ#4 L1 REQ[4]#
G6 H_HIT#
<9> H_A#[17..35] H_A#17 HIT# H_HITM# H_HIT# <9>
C H_A#18
Y2 A[17]# HITM# E4 H_HITM# <9> ： Delete XDP connector
03/18 PV： C
U5 A[18]#
H_A#19 R3 AD4
A[19]# BPM[0]#
ADDR GROUP_1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS

H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK +3VS
H_A#26 A[25]# TCK XDP_TDI
H_A#27
T3
A[26]# TDI
AA6
XDP_TDO
： Checklist Ver 1.5 change to 56 ohm
PV：
W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 AB5
A[28]# TMS

0.1U_0402_16V4Z
H_A#29 Y4 AB6 XDP_TRST# 1
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 C20 XDP_DBRESET# <22>
H_A#31 A[30]# DBR# C2
V4 A[31]#
H_A#32 W3 U1
H_A#33 A[32]# 2
AA4
A[33]# THERMAL
H_A#34 AB2 H_PROCHOT# R13 1 2 56_0402_1%
H_A#35 A[34]# +VCCP SMB_EC_CK2
AA3 D21 1 8 SMB_EC_CK2 <32>
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA_R R14 H_THERMDA VDD SMCLK
<9> H_ADSTB#1 V1
ADSTB[1]# THERMDA
A24 1 2 0_0402_5%
B25 H_THERMDC_R R15 1 2 0_0402_5% H_THERMDC H_THERMDA 2 7 SMB_EC_DA2
H_A20M# THERMDC DP SMDATA SMB_EC_DA2 <32>
A6 C3
<21> H_A20M# A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# 1 2 H_THERMDC 3 6 R6 1 2 10K_0402_5%

<21> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <9,21> DN ALERT# +3VS
H_IGNNE# C4 2200P_0402_50V7K
<21> H_IGNNE# IGNNE# THERM# 4 5
H_STPCLK# THERM# GND
<21> H_STPCLK# D5
H_INTR STPCLK#
<21> H_INTR C6
LINT0 H CLK R16 04/29 MV1 reserve
H_NMI B4 A22 CLK_CPU_BCLK 1 2
<21> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <17> +3VS 10K for 2nd source
H_SMI# A3 A21 CLK_CPU_BCLK# 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
<21> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <17>
M4
RSVD[01] Address:100_1100
N5
RSVD[02] H_THERMDA, H_THERMDC routing together,
T2
B
V3
RSVD[03] Trace width / Spacing = 10 / 10 mil B
RSVD[04]
B2
RESERVED

RSVD[05]
D2
RSVD[06]
D22
RSVD[07]
D3
RSVD[08] For Merom, R14 and R15 are 0ohm
F6
RSVD[09] For Penryn, R14 and R15 are 100ohm.
、 R15 to 0 ohm
04/29 MV1 change R14、 PWM Fan Control circuit
+5VS
11/01 update
Penryn
JP2
1
1
2
2

1
+VCCP
1 1
D1 C4 C5 3
4.7U_0805_10V4Z 0.1U_0402_16V4Z GND
4 GND
RB751V_SOD323
1

@ 2 2 ACES_88231-02001

2
R17 CONN@
56_0402_5%
+FAN
2 2

Change PCB Footprint from

1
2
5
6

1
B

D Q2 @ D2 ACES_85204-02001_2P to
E

H_PROCHOT# OCP# G
3 1 OCP# <22> ACES_88231-02001_2P
C

@ Q1 3 RLZ5.1B_LL34
<32> FAN_PWM S
MMBT3904_NL_SOT23-3 SI3456BDV-T1-E3_TSOP6

2
4
+VCCP
A A
2

R18
56_0402_5%
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

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WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
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+VCC_CORE +VCC_CORE
<9> H_D#[0..15] H_D#[32..47] <9>
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 AB24 A9 AB7
H_D#2 D[1]# D[33]# H_D#34 VCC[002] VCC[069]
E26 V24 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9

DATA GRP 2
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 V23 A13 AC12
H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
G25 T22 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 U25 A17 AC15
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E23 U23 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 W22 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 Y23 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 W24 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 AA24 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
H_DSTBN#0 J26 Y26 H_DSTBN#2 B18 AD18
<9> H_DSTBN#0 H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 H_DSTBN#2 <9> VCC[017] VCC[084]
<9> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <9> B20 VCC[018] VCC[085] AE9
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
<9> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <9> VCC[019] VCC[086]
<9> H_D#[16..31] H_D#[48..63] <9> C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 D[26]# D[58]# AE21 D18 VCC[032] VCC[099] AF18
H_D#27 T24 AD21 H_D#59 E7 AF20 +VCCP
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100] R19
R24 D[28]# D[60]# AC22 E9 VCC[034]
H_D#29 L25 AD23 H_D#61 E10 G21 +VCCPA 1 2 0_0402_5%
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01] +VCCPB 0_0402_5%
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6 1 2
C H_D#31 H_D#63 R20 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
<9> H_DSTBN#1 H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 H_DSTBN#3 <9> VCC[038] VCCP[04]
<9> H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 <9> E17 VCC[039] VCCP[05] M6
H_DINV#1 N24 AC20 H_DINV#3 E18 J21 + C6
<9> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <9> VCC[040] VCCP[06]
E20 K21 330U_D2E_2.5VM_R7
+V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
@ R21 2 1K_0402_5% TEST1 COMP1 2
1 C23 TEST1 MISC COMP[1] U26 F9 VCC[043] VCCP[09] N21
@ R22 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 Y1 F12 R21
TEST4 TEST3 COMP[3] VCC[045] VCCP[11]
T3 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# R23 R24 R25 R26 VCC[046] VCCP[12]
T4 AF1 E5 H_DPRSTP# <9,21,43> F15 T21
TEST5 DPRSTP# VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# <21> VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 TEST7 DPWR# H_DPWR# <9> VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
<17> CPU_BSEL0 CPU_BSEL1 BSEL[0] PWRGOOD H_CPUSLP# H_PWRGOOD <21> VCC[050] VCCP[16]
<17> CPU_BSEL1 B23 D7 H_CPUSLP# <9> AA7
CPU_BSEL2 BSEL[1] SLP# H_PSI# VCC[051]
<17> CPU_BSEL2 C21 AE6 H_PSI# <43> AA9 B26
BSEL[2] PSI# VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M

0.01U_0402_16V7K
Penryn AA12
VCC[054]
AA13 AD6 CPU_VID0 <43>
VCC[055] VID[0]
* Route the TEST3 and TEST5 signals through AA15
VCC[056] VID[1]
AF5 CPU_VID1 <43> 1 1
AA17 AE5 CPU_VID2 <43>
a ground referenced Zo = 55-ohm trace that VCC[057] VID[2] C7 C8
AA18 AF4 CPU_VID3 <43>
VCC[058] VID[3]
ends in a via that is near a GND via and is AA20 VCC[059] VID[4] AE3 CPU_VID4 <43> 2 2
accessible through an oscilloscope Resistor placed within 0.5" AB9
VCC[060] VID[5]
AF3 CPU_VID5 <43>
AC10 AE2 CPU_VID6 <43>
of CPU pin.Trace should be VCC[061] VID[6]
connection. AB10
VCC[062]
at least 25 mils away from AB12
VCC[063] VCCSENSE
AB14 VCC[064] VCCSENSE AF7 VCCSENSE <43>
any other toggling signal. AB15
VCC[065] Near pin B26
COMP[0,2] trace width is 18 AB17
VCC[066] VSSSENSE
AB18 AE7 VSSSENSE <43>
mils. COMP[1,3] trace width VCC[067] VSSSENSE
B Penryn B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 is 4 mils. .

166 0 1 1

Length match within 25 mils.

200 0 1 0
The trace width/space/other is 20/7/25.
+VCCP
266 0 0 0
1

R27
1K_0402_1%
+VCC_CORE
2

+V_CPU_GTLREF

R28 1 2 100_0402_1% VCCSENSE

1

R29
2K_0402_1% R30 1 2 100_0402_1% VSSSENSE
2

Close to CPU pin within

Close to CPU pin AD26 500mils.
A A
within 500mils.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 7 of 45
 5 4 3 2 1

WWW.AliSaler.Com
+VCC_CORE

1 1 1 1 1 1 1 1
Place these capacitors on C9 C10 C11 C12 C13 C14 C15 C16
L8 (North side,Secondary
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
Layer) 2 2 2 2 2 2 2 2

D D
+VCC_CORE
JCPU1D
A4 P6
VSS[001] VSS[082]
A8
VSS[002] VSS[083]
P21 Place these capacitors on 1 1 1 1 1 1 1 1
A11 P24 L8 (North side,Secondary C17 C18 C19 C20 C21 C22 C23 C24
VSS[003] VSS[084]
A14 R2
VSS[004] VSS[085] Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A16 R5
VSS[005] VSS[086] 2 2 2 2 2 2 2 2
A19 VSS[006] VSS[087] R22
A23 R25
VSS[007] VSS[088]
AF2 T1
VSS[008] VSS[089]
B6 VSS[009] VSS[090] T4
B8 T23 +VCC_CORE
VSS[010] VSS[091]
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6 Place these capacitors on 1 1 1 1 1 1 1 1
B19 U21 L8 (North side,Secondary C25 C26 C27 C28 C29 C30 C31 C32
VSS[014] VSS[095]
B21 VSS[015] VSS[096] U24
B24 V2 Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[016] VSS[097] 2 2 2 2 2 2 2 2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 W4 +VCC_CORE
VSS[021] VSS[102]
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3 Place these capacitors on 1 1 1 1 1 1 1 1
C25 Y6 C33 C34 C35 C36 C37 C38 C39 C40
VSS[025] VSS[106] L8 (North side,Secondary
D1 VSS[026] VSS[107] Y21
D4 Y24 Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[027] VSS[108] 2 2 2 2 2 2 2 2
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 AA14
D23
VSS[032] VSS[113]
AA16
Mid Frequence Decoupling
VSS[033] VSS[114]
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 AB1
VSS[037] VSS[118]
E11 AB4
VSS[038] VSS[119]
E14 AB8
VSS[039] VSS[120]
E16 AB11
VSS[040] VSS[121]
E19 AB13
E21
E24
VSS[041]
VSS[042]
VSS[122]
VSS[123]
AB16
AB19
ESR <= 1.5m ohm
VSS[043] VSS[124] Near CPU CORE regulator
F5
F8
VSS[044]
VSS[045]
VSS[125]
VSS[126]
AB23
AB26
Capacitor > 1980uF
F11 AC3
VSS[046] VSS[127]
F13 AC6
VSS[047] VSS[128] +VCC_CORE
F16 AC8
VSS[048] VSS[129]
F19 AC11
VSS[049] VSS[130]
F2 AC14
VSS[050] VSS[131]
F22 AC16
VSS[051] VSS[132]
330U_D2_2VY_R7M

330U_D2_2VY_R7M

330U_D2_2VY_R7M

330U_D2_2VY_R7M
F25 VSS[052] VSS[133] AC19
G4 AC21
VSS[053] VSS[134]
G1 AC24 1 1 1 1
VSS[054] VSS[135] @
G23 AD2
VSS[055] VSS[136] C41 + C42 + C43 + C44 +
G26 AD5
VSS[056] VSS[137]
H3 VSS[057] VSS[138] AD8
H6 AD11
VSS[058] VSS[139] 2 2 2 2
H21 AD13
VSS[059] VSS[140]
H24 AD16
VSS[060] VSS[141]
J2 AD19
B VSS[061] VSS[142] B
J5 VSS[062] VSS[143] AD22
J22 AD25
VSS[063] VSS[144]
J25 AE1
VSS[064] VSS[145]
K1 AE4
VSS[065] VSS[146]
K4
VSS[066] VSS[147]
AE8 11/21 Change ESR=7m ohm
K23 AE11
VSS[067] VSS[148]
K26 AE14
VSS[068] VSS[149]
L3 AE16
VSS[069] VSS[150]
L6 AE19
VSS[070] VSS[151]
L21 AE23
VSS[071] VSS[152]
L24 AE26
VSS[072] VSS[153]
M2 VSS[073] VSS[154] A2
M5 AF6
M22
VSS[074] VSS[155]
AF8 +VCCP Inside CPU center cavity in 2 rows
VSS[075] VSS[156]
M25 AF11
VSS[076] VSS[157]
N1 AF13
VSS[077] VSS[158]
N4 VSS[078] VSS[159] AF16 1 1 1 1 1 1
N23 AF19 C45 C46 C47 C48 C49 C50
VSS[079] VSS[160]
N26 AF21
VSS[080] VSS[161] 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
P3 A25
VSS[081] VSS[162] 2 2 2 2 2 2
AF25
VSS[163]
Penryn
.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 8 of 45
 5 4 3 2 1

WWW.AliSaler.Com H_A#[3..35] <6> U2B

<7> H_D#[0..63] U2A

DDR CLK/ CONTROL/COMPENSATION

A14 H_A#3 M36
H_A#_3 T7 RESERVED

0.01U_0402_25V7K
H_D#0 H_A#4 M_CLK_DDR0

2.2U_0603_6.3V4Z
F2 H_D#_0 H_A#_4 C15 T8 N36 RESERVED SA_CK_0 AP24 M_CLK_DDR0 <15>
H_D#1 G8 F16 H_A#5 R33 AT21 M_CLK_DDR1 M_CLK_DDR1 <15>
H_D#2 H_D#_1 H_A#_5 H_A#6 +1.5V T9 RESERVED SA_CK_1 M_CLK_DDR2
F8 H_D#_2 H_A#_6 H13 T10 T33 RESERVED SB_CK_0 AV24 M_CLK_DDR2 <16>
H_D#3 E6 C18 H_A#7 AH9 AU20 M_CLK_DDR3 M_CLK_DDR3 <16>
H_D#4 H_D#_3 H_A#_7 H_A#8 T11 RESERVED SB_CK_1
G2 H_D#_4 H_A#_8 M16 1 1 T12 AH10 RESERVED

1
C51

C52
H_D#5 H6 J13 H_A#9 AH12 AR24 M_CLK_DDR#0
H_D#6 H_D#_5 H_A#_9 H_A#10 T13 RESERVED SA_CK#_0 M_CLK_DDR#1 M_CLK_DDR#0 <15>
H2 P16 R31 AH13 AR21
H_D#7 H_D#_6 H_A#_10 H_A#11 T14 RESERVED SA_CK#_1 M_CLK_DDR#2 M_CLK_DDR#1 <15>
F6 R16 1K_0402_1% K12 AU24
H_D#8 H_D#_7 H_A#_11 H_A#12 2 2 T15 RESERVED SB_CK#_0 M_CLK_DDR#3 M_CLK_DDR#2 <16>
D4 N17 T16 AL34 AV20 M_CLK_DDR#3 <16>
H_D#9 H_D#_8 H_A#_12 H_A#13 RESERVED SB_CK#_1
H3 M13 AK34

2
H_D#10 H_D#_9 H_A#_13 H_A#14 SMRCOMP_VOH T17 RESERVED DDR_CKE0_DIMMA
M9 E17 T18 AN35 BC28 DDR_CKE0_DIMMA <15>
H_D#11 H_D#_10 H_A#_14 H_A#15 RESERVED SA_CKE_0 DDR_CKE1_DIMMA
M11
H_D#_11 H_A#_15
P17 80% of 1.5V VCC_SM T19 AM35
RESERVED SA_CKE_1
AY28 DDR_CKE1_DIMMA <15>

1
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
J1 F17 T20 T24 AY36 DDR_CKE2_DIMMB <16>
H_D#13 H_D#_12 H_A#_16 H_A#17 R32 RESERVED SB_CKE_0 DDR_CKE3_DIMMB
J2 G20 BB36 DDR_CKE3_DIMMB <16>
H_D#_13 H_A#_17 SB_CKE_1

RSVD
H_D#14 N12 B19 H_A#18 3.01K_0402_1% B31
H_D#_14 H_A#_18 T21 RESERVED
H_D#15 J6 J16 H_A#19 20% of 1.5V VCC_SM B2 BA17 DDR_CS0_DIMMA#
H_D#16 H_D#_15 H_A#_19 H_A#20 T22 RESERVED SA_CS#_0 DDR_CS1_DIMMA# DDR_CS0_DIMMA# <15>
P2 E20 M1 AY16

2
H_D#_16 H_A#_20 T23 RESERVED SA_CS#_1 DDR_CS1_DIMMA# <15>
H_D#17 L2 H16 H_A#21 SMRCOMP_VOL AV16 DDR_CS2_DIMMB#
H_D#18 H_D#_17 H_A#_21 H_A#22 SB_CS#_0 DDR_CS3_DIMMB# DDR_CS2_DIMMB# <16>
R2 J20 AR13 DDR_CS3_DIMMB# <16>
H_D#_18 H_A#_22 SB_CS#_1

1
0.01U_0402_25V7K
H_D#19 H_A#23

2.2U_0603_6.3V4Z
N9 L17 T24 AY21
H_D#20 H_D#_19 H_A#_23 H_A#24 R33 RESERVED M_ODT0
L6 H_D#_20 H_A#_24 A17 1 1 SA_ODT_0 BD17 M_ODT0 <15>

C53

C54
H_D#21 M5 B17 H_A#25 1K_0402_1% AY17 M_ODT1
H_D#_21 H_A#_25 SA_ODT_1 M_ODT1 <15> +1.5V
H_D#22 J3 L16 H_A#26 BF15 M_ODT2 M_ODT2 <16>
H_D#23 H_D#_22 H_A#_26 H_A#27 SB_ODT_0 M_ODT3
N2 C21 BG23 AY13 M_ODT3 <16>

2
H_D#24 H_D#_23 H_A#_27 H_A#28 2 2 T25 RESERVED SB_ODT_1
R1 H_D#_24 H_A#_28 J17 T26 BF23 RESERVED
H_D#25 N5 H20 H_A#29 BH18 BG22 SMRCOMP R34 1 2 80.6_0402_1%
H_D#26 H_D#_25 H_A#_29 H_A#30 T27 RESERVED SM_RCOMP SMRCOMP#
N6 B18 BF18 BH21 R35 1 2 80.6_0402_1%
H_D#27 H_D#_26 H_A#_30 H_A#31 T28 RESERVED SM_RCOMP#
H_D#28
P13 H_D#_27 H_A#_31 K17
H_A#32 SMRCOMP_VOH
Follow Design Guide
N8 H_D#_28 H_A#_32 B20 SM_RCOMP_VOH BF28
H_D#29 L7 F21 H_A#33 BH28 SMRCOMP_VOL For Cantiga: 80.6ohm
H_D#30 H_D#_29 H_A#_33 H_A#34 +3VS SM_RCOMP_VOL
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35 AV42 V_DDR_MCH_REF
H_D#32 H_D#_31 H_A#_35 PM_EXTTS#0 R38 SM_VREF SM_PWROK
Y3 H_D#_32 1 2 10K_0402_5% SM_PWROK AR36 @ R36 1 2 0_0402_5%
H_D#33 AD14 H12 H_ADS# BF17 SM_REXT R37 1 2 499_0402_1%
H_D#34 H_D#_33 H_ADS# H_ADSTB#0 H_ADS# <6> SM_REXT TP_SM_DRAMRST#
Y6 H_D#_34 H_ADSTB#_0 B16 H_ADSTB#0 <6> SM_DRAMRST# BC36 SM_DRAMRST# <15,16>
H_D#35 Y10 G17 H_ADSTB#1 PM_EXTTS#1 R39 1 2 10K_0402_5%
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <6>
H_D#36 Y12 A9 H_BNR# B38 CLK_MCH_DREFCLK
H_D#37 H_D#_36 H_BNR# H_BPRI# H_BNR# <6> DPLL_REF_CLK CLK_MCH_DREFCLK# CLK_MCH_DREFCLK <17>
Y14 H_D#_37 H_BPRI# F11 H_BPRI# <6> DPLL_REF_CLK# A38 CLK_MCH_DREFCLK# <17>
H_D#38 Y7 G12 H_BR0# CLKREQ#_7 R40 1 2 10K_0402_5% E41 MCH_SSCDREFCLK
H_D#39 H_D#_38 H_BREQ# H_DEFER# H_BR0# <6> DPLL_REF_SSCLK MCH_SSCDREFCLK# MCH_SSCDREFCLK <17>
HOST

W2 H_D#_39 H_DEFER# E9 H_DEFER# <6> DPLL_REF_SSCLK# F41 MCH_SSCDREFCLK# <17>

H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# <6>

CLK
H_D#41 Y9 AH7 CLK_MCH_BCLK F43 CLK_MCH_3GPLL
H_D#42 H_D#_41 HPLL_CLK CLK_MCH_BCLK# CLK_MCH_BCLK <17> PEG_CLK CLK_MCH_3GPLL# CLK_MCH_3GPLL <17>
AA13 H_D#_42 HPLL_CLK# AH6 CLK_MCH_BCLK# <17> PEG_CLK# E43 CLK_MCH_3GPLL# <17>
H_D#43 AA9 J11 H_DPWR#
C H_D#44 H_D#_43 H_DPWR# H_DRDY# H_DPWR# <7> C
AA11 H_D#_44 H_DRDY# F9 H_DRDY# <6>
H_D#45 AD11 H9 H_HIT#
H_D#46 H_D#_45 H_HIT# H_HITM# H_HIT# <6> DMI_TXN0
AD10 H_D#_46 H_HITM# E12 H_HITM# <6> DMI_RXN_0 AE41 DMI_TXN0 <22>
H_D#47 AD13 H11 H_LOCK# AE37 DMI_TXN1
H_D#48 H_D#_47 H_LOCK# H_TRDY# H_LOCK# <6> DMI_RXN_1 DMI_TXN2 DMI_TXN1 <22>
AE12 H_D#_48 H_TRDY# C9 H_TRDY# <6> DMI_RXN_2 AE47 DMI_TXN2 <22>
H_D#49 AE9 AH39 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 <22>
H_D#50 AA2
H_D#51 H_D#_50 DMI_TXP0
AD8 AE40 DMI_TXP0 <22>
H_D#52 H_D#_51 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1
AA3 <17> MCH_CLKSEL0 T25 AE38 DMI_TXP1 <22>
H_D#53 H_D#_52 H_DINV#0 MCH_CLKSEL1 CFG_0 DMI_RXP_1 DMI_TXP2
AD3 J8 H_DINV#0 <7> <17> MCH_CLKSEL1 R25 AE48 DMI_TXP2 <22>
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3
AD7 L3 H_DINV#1 <7> <17> MCH_CLKSEL2 P25 AH40 DMI_TXP3 <22>
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2 CFG_2 DMI_RXP_3
AE14 Y13 H_DINV#2 <7> P20
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 CFG_3 DMI_RXN0
AF3 Y1 H_DINV#3 <7> P24 AE35 DMI_RXN0 <22>
H_D#57 H_D#_56 H_DINV#_3 CFG5 CFG_4 DMI_TXN_0 DMI_RXN1
AC1 H_D#_57 <11> CFG5 C25 CFG_5 DMI_TXN_1 AE43 DMI_RXN1 <22>
H_D#58 AE3 L10 H_DSTBN#0 CFG6 N24 AE46 DMI_RXN2
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 H_DSTBN#0 <7> <11> CFG6 CFG7 CFG_6 DMI_TXN_2 DMI_RXN3 DMI_RXN2 <22>
AC3 M7 H_DSTBN#1 <7> <11> CFG7 M24 AH42 DMI_RXN3 <22>
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 CFG8 CFG_7 DMI_TXN_3
AE11 AA5 H_DSTBN#2 <7> <11> CFG8 E21
H_D#_60 H_DSTBN#_2 CFG_8

CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_RXP0
H_DSTBN#3 <7> <11> CFG9 DMI_RXP0 <22>

DMI
H_D#62 H_D#_61 H_DSTBN#_3 CFG10 CFG_9 DMI_TXP_0 DMI_RXP1
AG2 <11> CFG10 C24 AE44 DMI_RXP1 <22>
H_D#63 H_D#_62 H_DSTBP#0 CFG11 CFG_10 DMI_TXP_1 DMI_RXP2
AD6 L9 H_DSTBP#0 <7> <11> CFG11 N21 AF46 DMI_RXP2 <22>
H_D#_63 H_DSTBP#_0 H_DSTBP#1 CFG12 CFG_11 DMI_TXP_2 DMI_RXP3
M8 H_DSTBP#1 <7> <11> CFG12 P21 AH43 DMI_RXP3 <22>
H_DSTBP#_1 H_DSTBP#2 CFG13 CFG_12 DMI_TXP_3
AA6 H_DSTBP#2 <7> <11> CFG13 T21
+H_SWNG H_DSTBP#_2 H_DSTBP#3 CFG14 CFG_13
C5 H_SWING H_DSTBP#_3 AE5 H_DSTBP#3 <7> <11> CFG14 R20 CFG_14
H_RCOMP E3 CFG15 M20
H_RCOMP H_REQ#0 <11> CFG15 CFG16 CFG_15
B15 H_REQ#0 <6> <11> CFG16 L21 2 1 +1.5V
H_REQ#_0 H_REQ#1 CFG17 CFG_16 R1120

GRAPHICS VID
K13 H_REQ#1 <6> <11> CFG17 H21
H_REQ#_1 H_REQ#2 CFG18 CFG_17 10K_0402_5%~D
F13 H_REQ#2 <6> <11> CFG18 P29
H_REQ#_2 H_REQ#3 CFG19 CFG_18 D25
H_REQ#_3 B13 H_REQ#3 <6> <11> CFG19 R28 CFG_19
<6> H_RESET# H_RESET# C12 B14 H_REQ#4 CFG20 T28 B33 2 1
H_CPUSLP# H_CPURST# H_REQ#_4 H_REQ#4 <6> <11> CFG20 CFG_20 GFX_VID_0 T30 SYSON <26,32,33,36,41>
<7> H_CPUSLP# E11 B32 T31
H_CPUSLP# H_RS#0 GFX_VID_1 CH751H-40PT_SOD323-2
B6 H_RS#0 <6> G33 T32
H_RS#_0 H_RS#1 GFX_VID_2 SM_PWROK
F12 H_RS#1 <6> F33 T33 DDR3_SM_PWROK <41>
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_3 B
H_RS#_2 C8 H_RS#2 <6> <22> PM_BMBUSY# R29 PM_SYNC# GFX_VID_4 E33 T34
+H_VREF A11 H_DPRSTP# B7
H_AVREF <7,21,43> H_DPRSTP# PM_EXTTS#0 PM_DPRSTP#
B11 <15> PM_EXTTS#0 N33
H_DVREF PM_EXTTS#1 PM_EXT_TS#_0
<16> PM_EXTTS#1 P32
PM_EXT_TS#_1

PM
CANTIGA ES_FCBGA1329 PM_PWROK AT40 C34
<22,32> PM_PWROK PWROK GFX_VR_EN T35 +VCCP
<20,25,26,27> PLT_RST# 1 2 AT11
R41 1 THERMTRIP# RSTIN#
2 100_0402_5% T20
Layout note: <6,21> H_THERMTRIP#
<22,43> DPRSLPVR R42 0_0402_5% DPRSLPVR R32
THERMTRIP#
DPRSLPVR

1
Route H_SCOMP and H_SCOMP# with trace CL_CLK0
AH37 R43
width, spacing and impedance (55 ohm) same CL_CLK CL_CLK0 <22>
0.1U_0402_16V4Z

AH36 CL_DATA0 1K_0402_1%

CL_DATA M_PWROK CL_DATA0 <22>
as FSB data traces 1 @ BG48 NC CL_PWROK AN36 M_PWROK <22,32>
C55 BF48 AJ35 CL_RST#

2
NC CL_RST# +CL_VREF CL_RST# <22>
BD48 AH34

ME
NC CL_VREF
Layout Note: Layout Note: V_DDR_MCH_REF BC48
NC

1
2 BH47 0621 add CLK and DAT for DVI
NC 1
H_RCOMP / H_VREF / H_SWNG trace width and spacing is 20/20. BG47 C56 R44
NC 0.1U_0402_16V4Z 499_0402_1%
trace width and spacing is 10/20 BE47 N28 T36
NC DDPC_CTRLCLK
BH46 M28 T37
+1.5V NC DDPC_CTRLDATA HDMICLK_NB 2
BF46 G36

2
NC SDVO_CTRLCLK HDMICLK_NB <35>

NC
+V_DDR_MCH_REF generated by DC-DC BG45 E36 HDMIDAT_NB
+VCCP NC SDVO_CTRLDATA CLKREQ#_7 HDMIDAT_NB <35>
BH44 NC CLKREQ# K36 CLKREQ#_7 <17>
1

MISC
+VCCP BH43 H36 MCH_ICH_SYNC#
NC ICH_SYNC# MCH_ICH_SYNC# <22>
R45 BH6
NC
1K_0402_1%

221_0603_1%

10K_0402_1% BH5 1 R737 2 56_0402_5% +VCCP *R44*Follow

NC
1

BG4 B12 TSATN#

NC TSATN# TSATN# <32> Intel feedback
R46 R47 BH3
2

V_DDR_MCH_REF NC
BF3 NC
BH2
NC
1
0.1U_0402_16V4Z

BG2 B28
2

+H_VREF H_RCOMP +H_SWNG NC HDA_BCLK HDA_BITCLK_NB <21>

1 R48 BE2 B30 R210
NC HDA_RST# HDA_RST#_NB <21>
C57 10K_0402_1% BG1 NC HDA_SDI B29 HDA_SDIN2_NB 1 2 HDA_SDIN2 <21>
24.9_0402_1%

A A
0.1U_0402_16V4Z

BF1 NC HDA_SDO C29 HDA_SDOUT_NB <21>

1

1
100_0402_1%
0.1U_0402_16V4Z

1 1 BD1 A28 33_0402_5%

2

2 NC HDA_SYNC HDA_SYNC_NB <21>

2K_0402_1%

HDA
R52 C58 R54 R55 C59 BC1 NC
F1 NC
A47 NC
0830 Add pull-up and pull-down resistor.
2 2
2

CANTIGA ES_FCBGA1329

： follow check list ver:1.5 change to 10K ohm

PV：
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
within 100 mils from NB Near B3 pin Cantiga(1/6)-AGTL/DMI/DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 9 of 45
 5 4 3 2 1

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D D

<15> DDR_A_D[0..63] <16> DDR_B_D[0..63]

U2D U2E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
DDR_A_D1 SA_DQ_0 SA_BS_0 DDR_A_BS1 DDR_A_BS0 <15> DDR_B_D1 SB_DQ_0 SB_BS_0 DDR_B_BS1 DDR_B_BS0 <16>
AJ41 BG18 DDR_A_BS1 <15> AH46 BB17 DDR_B_BS1 <16>
DDR_A_D2 SA_DQ_1 SA_BS_1 DDR_A_BS2 DDR_B_D2 SB_DQ_1 SB_BS_1 DDR_B_BS2
AN38 AT25 DDR_A_BS2 <15> AP47 BB33 DDR_B_BS2 <16>
DDR_A_D3 SA_DQ_2 SA_BS_2 DDR_B_D3 SB_DQ_2 SB_BS_2
AM38 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 BB20 DDR_A_RAS# <15> AJ46
DDR_A_D5 SA_DQ_4 SA_RAS# DDR_A_CAS# DDR_B_D5 SB_DQ_4 DDR_B_RAS#
AJ40 SA_DQ_5 SA_CAS# BD20 DDR_A_CAS# <15> AJ48 SB_DQ_5 SB_RAS# AU17 DDR_B_RAS# <16>
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# DDR_A_WE# <15> SB_DQ_6 SB_CAS# DDR_B_CAS# <16>
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# <16>
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
DDR_A_D10 SA_DQ_9 DDR_A_DM[0..7] <15> DDR_B_D10 SB_DQ_9
AU40 SA_DQ_10 BA48 SB_DQ_10
DDR_A_D11 AT38 AM37 DDR_A_DM0 DDR_B_D11 AY48
DDR_A_D12 SA_DQ_11 SA_DM_0 DDR_A_DM1 DDR_B_D12 SB_DQ_11 DDR_B_DM0 DDR_B_DM[0..7] <16>
AN41 SA_DQ_12 SA_DM_1 AT41 AT47 SB_DQ_12 SB_DM_0 AM47
DDR_A_D13 AN39 AY41 DDR_A_DM2 DDR_B_D13 AR47 AY47 DDR_B_DM1
DDR_A_D14 SA_DQ_13 SA_DM_2 DDR_A_DM3 DDR_B_D14 SB_DQ_13 SB_DM_1 DDR_B_DM2
AU44 SA_DQ_14 SA_DM_3 AU39 BA47 SB_DQ_14 SB_DM_2 BD40
DDR_A_D15 AU42 BB12 DDR_A_DM4 DDR_B_D15 BC47 BF35 DDR_B_DM3
DDR_A_D16 SA_DQ_15 SA_DM_4 DDR_A_DM5 DDR_B_D16 SB_DQ_15 SB_DM_3 DDR_B_DM4
AV39 SA_DQ_16 SA_DM_5 AY6 BC46 SB_DQ_16 SB_DM_4 BG11
DDR_A_D17 AY44 AT7 DDR_A_DM6 DDR_B_D17 BC44 BA3 DDR_B_DM5
DDR_A_D18 SA_DQ_17 SA_DM_6 DDR_A_DM7 DDR_B_D18 SB_DQ_17 SB_DM_5 DDR_B_DM6
BA40 SA_DQ_18 SA_DM_7 AJ5 BG43 SB_DQ_18 SB_DM_6 AP1

A
DDR_A_D19 BD43 DDR_B_D19 BF43 AK2 DDR_B_DM7

B
SA_DQ_19 DDR_A_DQS[0..7] <15> SB_DQ_19 SB_DM_7
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] <16>
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
DDR_A_D23 BC40 BC37 DDR_A_DQS3 DDR_B_D23 BF41 BG41 DDR_B_DQS2
DDR_A_D24 SA_DQ_23 MEMORY SA_DQS_3 DDR_A_DQS4 DDR_B_D24 SB_DQ_23 SB_DQS_2 DDR_B_DQS3

MEMORY
AY37 SA_DQ_24 SA_DQS_4 AW12 BG38 SB_DQ_24 SB_DQS_3 BG37
DDR_A_D25 BD38 BC8 DDR_A_DQS5 DDR_B_D25 BF38 BH9 DDR_B_DQS4
DDR_A_D26 SA_DQ_25 SA_DQS_5 DDR_A_DQS6 DDR_B_D26 SB_DQ_25 SB_DQS_4 DDR_B_DQS5
AV37 SA_DQ_26 SA_DQS_6 AU8 BH35 SB_DQ_26 SB_DQS_5 BB2
DDR_A_D27 AT36 AM7 DDR_A_DQS7 DDR_B_D27 BG35 AU1 DDR_B_DQS6
DDR_A_D28 SA_DQ_27 SA_DQS_7 DDR_A_DQS#0 DDR_A_DQS#[0..7] <15> DDR_B_D28 SB_DQ_27 SB_DQS_6 DDR_B_DQS7
AY38 SA_DQ_28 SA_DQS#_0 AJ43 BH40 SB_DQ_28 SB_DQS_7 AN6 DDR_B_DQS#[0..7] <16>
C DDR_A_D29 DDR_A_DQS#1 DDR_B_D29 DDR_B_DQS#0 C
BB38 SA_DQ_29 SA_DQS#_1 AT43 BG39 SB_DQ_29 SB_DQS#_0 AL46
DDR_A_D30 AV36 BA44 DDR_A_DQS#2 DDR_B_D30 BG34 AV47 DDR_B_DQS#1
DDR_A_D31 SA_DQ_30 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D31 SB_DQ_30 SB_DQS#_1 DDR_B_DQS#2
AW36 SA_DQ_31 SA_DQS#_3 BD37 BH34 SB_DQ_31 SB_DQS#_2 BH41
DDR_A_D32 BD13 AY12 DDR_A_DQS#4 DDR_B_D32 BH14 BH37 DDR_B_DQS#3
DDR_A_D33 SA_DQ_32 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D33 SB_DQ_32 SB_DQS#_3 DDR_B_DQS#4
AU11 SA_DQ_33 SA_DQS#_5 BD8 BG12 SB_DQ_33 SB_DQS#_4 BG9
DDR_A_D34 BC11 AU9 DDR_A_DQS#6 DDR_B_D34 BH11 BC2 DDR_B_DQS#5
DDR_A_D35 SA_DQ_34 SA_DQS#_6 DDR_A_DQS#7 DDR_B_D35 SB_DQ_34 SB_DQS#_5 DDR_B_DQS#6
BA12 SA_DQ_35 SA_DQS#_7 AM8 DDR_A_MA[0..14] <15> BG8 SB_DQ_35 SB_DQS#_6 AT2
DDR_A_D36 AU13 DDR_B_D36 BH12 AN5 DDR_B_DQS#7
SYSTEM

SA_DQ_36 SB_DQ_36 SB_DQS#_7

SYSTEM
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11 DDR_B_MA[0..14] <16>
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 BC24 BF8 AV17
DDR_A_D39 SA_DQ_38 SA_MA_1 DDR_A_MA2 DDR_B_D39 SB_DQ_38 SB_MA_0 DDR_B_MA1
BC12 BG24 BG7 BA25
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BB9 BH24 BC5 BC25
DDR_A_D41 SA_DQ_40 SA_MA_3 DDR_A_MA4 DDR_B_D41 SB_DQ_40 SB_MA_2 DDR_B_MA3
BA9 BG25 BC6 AU25
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 SA_DQ_42 SA_MA_5 BA24 AY3 SB_DQ_42 SB_MA_4 AW25
DDR_A_D43 AV9 BD24 DDR_A_MA6 DDR_B_D43 AY1 BB28 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 BG27 BF6 AU28
DDR_A_D45 SA_DQ_44 SA_MA_7 DDR_A_MA8 DDR_B_D45 SB_DQ_44 SB_MA_6 DDR_B_MA7
BD9 BF25 BF5 AW28
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 AW24 BA1 AT33
DDR_A_D47 SA_DQ_46 SA_MA_9 DDR_A_MA10 DDR_B_D47 SB_DQ_46 SB_MA_8 DDR_B_MA9
BA6 BC21 BD3 BD33
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
AV5 BG26 AV2 BB16
SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10
DDR

DDR_A_D49 AV7 BH26 DDR_A_MA12 DDR_B_D49 AU3 AW33 DDR_B_MA11

SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11

DDR
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 AV1
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AT5 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 AR1
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AM11 SA_DQ_56 AL1 SB_DQ_56
DDR_A_D57 AM5 DDR_B_D57 AL2
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AJ9 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 AH1
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AN12 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 10 of 45
 5 4 3 2 1

WWW.AliSaler.Com
U2C

1
R148
2 ENBKL
Strap Pin Table
R57 +VCC_PEG
100K_0402_5%
L32 L_BKLT_CTRL 000 = FSB 1066MHz
<32> ENBKL ENBKL G32 T37 1 2 CFG[2:0] FSB Freq
R58 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 1 2 10K_0402_5% M32 L_CTRL_CLK PEG_COMPO T36 49.9_0402_1%
select
R59 1 2 10K_0402_5%
011 = FSB 667MHz
DDC2_CLK
M33 L_CTRL_DATA PEGCOMP trace width
<19> DDC2_CLK K33 L_DDC_CLK PEG_RX#_0 H44 Others = Reserved
<19> DDC2_DATA
DDC2_DATA J33 J46 and spacing is 20/25 mils.
L_DDC_DATA PEG_RX#_1
L44
PEG_RX#_2
PEG_RX#_3
L40 CFG[4:3] Reserved
<19> ENAVDD ENAVDD M29 N41
R60 1 L_VDD_EN PEG_RX#_4
2 4.75K_0402_1% C44
LVDS_IBG PEG_RX#_5
P48 0 = DMI x 2
D D
Follow Intel DG & B43 N44 CFG5 (DMI select) 1 = DMI x 4
Checklist
E37
E38
LVDS_VBG
LVDS_VREFH
PEG_RX#_6
PEG_RX#_7
T43
U43
*
0 = The iTPM Host Interface is enable
LVDS_VREFL PEG_RX#_8

LVDS
LVDS_ACLK- C41 Y43 CFG6
LVDS_ACLK+ LVDSA_CLK# PEG_RX#_9
C40 Y48 1 = The iTPM Host Interface is disable
T80
LVDS_BCLK-
LVDS_BCLK+
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_10
PEG_RX#_11
Y36
AA43 0 =(TLS)chiper suite with no confidentiality
*
T81 LVDSB_CLK PEG_RX#_12
LVDS_A0- PEG_RX#_13
AD37 CFG7 (Intel Management
Engine Crypto strap) 1 =(TLS)chiper suite with confidentiality
H47 AC47
LVDS_A1-
LVDS_A2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15
AD39 *
LVDS_A3- LVDSA_DATA#_2
T38 A40 LVDSA_DATA#_3 PEG_RX_0 H43
PEG_RX_1 J44 CFG8 Reserved

GRAPHICS
LVDS_A0+ H48 L43
LVDS_A1+ LVDSA_DATA_0 PEG_RX_2 TMDS_B_HPD#
D45 LVDSA_DATA_1 PEG_RX_3 L41 TMDS_B_HPD# <35>
LVDS_A2+ F40 N40 CFG9 (PCIE Graphics 0 = Reverse Lane,15->0, 14->1
LVDS_A3+ LVDSA_DATA_2 PEG_RX_4
T39 B40 LVDSA_DATA_3 PEG_RX_5 P47
N43 Lane Reversal) 1 = Normal Operation,Lane Number in
T72
LVDS_B0-
LVDS_B1-
A41
H38
LVDSB_DATA#_0
PEG_RX_6
PEG_RX_7 T42
U42
order *
T73 LVDS_B2- LVDSB_DATA#_1 PEG_RX_8
T74 G37 LVDSB_DATA#_2 PEG_RX_9 Y42
LVDS_B3- J37 W47 CFG10 (PCIE 0 = Enable
T40 LVDSB_DATA#_3 PEG_RX_10
PEG_RX_11 Y37
LVDS_B0+ B42 AA42 Lookback 1 = Disable
T75
T77
LVDS_B1+
LVDS_B2+
G38
F37
LVDSB_DATA_0
LVDSB_DATA_1
PEG_RX_12
PEG_RX_13 AD36
AC48 CFG11
enable)
Reserved
*
T79 LVDS_B3+ LVDSB_DATA_2 PEG_RX_14
T41 K37 LVDSB_DATA_3 PEG_RX_15 AD40
TV_COMPS 00 = Reserved

PCI-EXPRESS
T48 TV_LUMA TMDS_BDATA2#
J41 C274 1 2 0.1U_0402_10V7K TMDS_B_DATA2# <35> CFG[13:12] (XOR/ALLZ) 01 = XOR Mode Enabled
T49 TV_CRMA PEG_TX#_0 TMDS_BDATA1#
M46 C275 1 2 0.1U_0402_10V7K TMDS_B_DATA1# <35> 10 = All Z Mode Enabled
T50 PEG_TX#_1 TMDS_BDATA0#
F25 M47 C276 1 2 0.1U_0402_10V7K 11 = Normal Operation (Default)
TVA_DAC PEG_TX#_2 TMDS_B_DATA0# <35>
*
1

H25 M40 TMDS_BCLK# C277 1 2 0.1U_0402_10V7K

TVB_DAC PEG_TX#_3 TMDS_B_CLK# <35>
75_0402_1%

75_0402_1%

75_0402_1%

C C
Follow Intel DG & K25 TVC_DAC PEG_TX#_4 M42

TV
R61 R62 R63 R48 CFG[15:14] Reserved
Checklist PEG_TX#_5
H24 TV_RTN PEG_TX#_6 N38
T40
2

PEG_TX#_7
PEG_TX#_8 U37 CFG16 (FSB Dynamic ODT) 0 = Disabled
11/10 Disable TV out U40 1 = Enabled
@ R64 1 2 2.2K_0402_5%
C31
E32
TV_DCONSEL_0
PEG_TX#_9
PEG_TX#_10 Y40
AA46
*
+3VS TV_DCONSEL_1 PEG_TX#_11
R406 1 2 0_0402_5% AA37 CFG[18:17] Reserved
M_BLUE PEG_TX#_12
<18> M_BLUE AA40
M_GREEN PEG_TX#_13
<18> M_GREEN AD43
M_RED PEG_TX#_14
AC46 CFG19 (DMI Lane Reversal) 0 = Normal Operation
<18> M_RED PEG_TX#_15
(Lane number in Order) *
1

1
150_0402_1%

150_0402_1%

150_0402_1%

E28 J42 TMDS_BDATA2 C278 1 2 0.1U_0402_10V7K TMDS_B_DATA2 <35>

CRT_BLUE PEG_TX_0 TMDS_BDATA1 C279 0.1U_0402_10V7K
Follow Intel DG & PEG_TX_1
L46 1 2 TMDS_B_DATA1 <35> 1 = Reverse Lane
R65 R66 R67 G28 M48 TMDS_BDATA0 C280 1 2 0.1U_0402_10V7K
CRT_GREEN PEG_TX_2 TMDS_B_DATA0 <35>
Checklist M39 TMDS_BCLK C281 1 2 0.1U_0402_10V7K TMDS_B_CLK <35>
PEG_TX_3
J28 M43
2

CRT_RED PEG_TX_4
VGA
R47 CFG20 (PCIE/SDVO 0 = Only PCIE or SDVO is operational.
G29
CRT_IRTN
PEG_TX_5
PEG_TX_6
N37
T39 concurrent) 1 = PCIE/SDVO are operating simu.
*
3VDDCCL PEG_TX_7
<18> 3VDDCCL H32 U36
3VDDCDA CRT_DDC_CLK PEG_TX_8
<18> 3VDDCDA J32 CRT_DDC_DATA PEG_TX_9 U39
CRT_HSYNC R68 1 2 HSYNC J29 Y39
<18> CRT_HSYNC CRT_HSYNC PEG_TX_10
30.1_0402_1% E29 Y46
CRT_VSYNC R69 1 VSYNC CRT_TVO_IREF PEG_TX_11 +3VS
<18> CRT_VSYNC 2 L29
CRT_VSYNC PEG_TX_12
AA36
30.1_0402_1% AA39
PEG_TX_13
PEG_TX_14 AD42
1

AD46
PEG_TX_15

1
R70 @ R71 +3VS
1.02K_0402_1% 4.02K_0402_1%
CANTIGA ES_FCBGA1329
B B
2

@ R72 1 2

2
CFG5 <9> CFG16
4.02K_0402_1%
<9> CFG5

1
@ R73 1 2
<9> CFG19
@ R74 4.02K_0402_1%
2.21K_0402_1%
@R75
@R75 1 2
<9> CFG20
4.02K_0402_1%

2
@R76
@R76 1 2
Solve 3G WWAN issue <9> CFG11
2.21K_0402_1%

LVDS_ACLK+
、
04/29 MV-1 Delete CFG5、
<19> LVDS_ACLK+ 1 @ R77 1 2
@ CFG7、、CFG12、 、CFG13、 、CFG16 <9> CFG12
2.21K_0402_1%
C60
LVDS_ACLK- 0.1U_0402_10V6K @ R78 1 2
<19> LVDS_ACLK- 2 <9> CFG13
<19> LVDS_A0+ LVDS_A0+ 1 2.21K_0402_1%
@ @R79
@R79 1 2
<9> CFG6
C61 2.21K_0402_1% @R80
@R80 1 2
LVDS_A0- 0.1U_0402_10V6K <9> CFG14
<19> LVDS_A0- 2.21K_0402_1%
LVDS_A1+ 2 @ R81 1 2
<19> LVDS_A1+ 1 <9> CFG7
@ 2.21K_0402_1% @R82
@R82 1 2
<9> CFG15
C62 2.21K_0402_1%
LVDS_A1- 0.1U_0402_10V6K @R83
@R83 1 2
<19> LVDS_A1- 2 <9> CFG8
LVDS_A2+ 1 2.21K_0402_1%
<19> LVDS_A2+
@
C63 @R84
@R84 1 2 @R85
@R85 1 2
LVDS_A2- 0.1U_0402_10V6K <9> CFG9 <9> CFG17
<19> LVDS_A2- 2.21K_0402_1% 2.21K_0402_1%
2
A @R86
@R86 @R87
@R87 A
<9> CFG10 1 2 <9> CFG18 1 2
2.21K_0402_1% 2.21K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 11 of 45
 5 4 3 2 1

WWW.AliSaler.Com
+3VS_DAC_BG

1
R88
2
+3VS **RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable Guidelines~ +VCCP
+1.05VS_DPLLA
+VCCP

0.022U_0402_16V7K
BLM18PG181SN1D_0603
+VCCP

0.1U_0402_16V4Z

10U_0805_10V4Z
+V1.05VS_AXF
1

@ 1 1 1 U2H 1 2 R93
0_0603_5%

C68

C69

C70
R90 1 2
R89

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
852mA VTT U13 1 @ 10U_FLC-453232-100K_0.25A_10% 0_0603_5%

4.7U_0805_10V4Z

220U_D2_4VM

C73

C74
73mA VTT T13 1 1 1
2 2 2

220U_6.3V_M
+

C77
B27 U12 1 1 1
2

VCCA_CRT_DAC VTT

C71
+

C72

C78

C79
+3VS_DAC_CRT A26 VCCA_CRT_DAC VTT T12
VTT U11
2.68mA 2 2 2
VTT T11
2 2 2 2
+3VS_DAC_BG A25 U10

CRT
VCCA_DAC_BG VTT
B25 VSSA_DAC_BG VTT T10
D
+3VS_DAC_CRT VTT U9 D
+3VS T9
R91 VTT
VTT U8
1 2 +1.05VS_DPLLA F47 VCCA_DPLLA
64.8mA VTT T8
0.022U_0402_16V7K

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
BLM18PG181SN1D_0603 U7

VTT
VTT +1.5V_SM_CK
0.1U_0402_16V4Z

L48 64.8mA T7 1 1 1 +1.5V

PLL
+1.05VS_DPLLB VCCA_DPLLB VTT
1

+1.05VS_DPLLB +VCCP
C75

C76

1 1 U6 R95
VTT
@

0_0603_5%

24mA R94

C80

C81

C82
+1.05VS_HPLL AD1 VCCA_HPLL VTT T6 1 2

10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
U5 1 2 0_0805_5%
VTT 2 2 2
R92

0.1U_0402_16V4Z
+1.05VS_MPLL AE1 VCCA_MPLL
139.2mA VTT T5 10U_FLC-453232-100K_0.25A_10% 1 @ 1 1
2 2

C86

C87

10U_0805_10V4Z

C83

C84

C85
V3
2

VTT
13.2mA U3 1 1

A LVDS
VTT
+1.8V_TXLVDS J48 VCCA_LVDS VTT V2
2 2 2
1 VTT U2
C88 J47 T2
VSSA_LVDS VTT 2 2
VTT V1
@ R96 1000P_0402_50V7K 414uA VTT U1
2
+3VS 1 2
0_0603_5% AD48
+1.5VS_PEG_BG VCCA_PEG_BG
R97

A PEG
+1.5VS 1 2 +1.5VS_TVDAC
0_0603_5% 50mA +1.05VS_HPLL +VCCP +1.5VS
1 +1.05VS_PEGPLL AA48 R98 R99
C89 VCCA_PEG_PLL
1 2 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
MBK2012121YZF_0805 0_0805_5%
0.1U_0402_16V4Z AR20
2 VCCA_SM

0.1U_0402_16V4Z

10U_0805_10V4Z
AP20 VCCA_SM 1 1 1 1

C90

C91
AN20 720mA
VCCA_SM
POWER

C92

C93
AR17 VCCA_SM
AP17 VCCA_SM
+VCCP 2 2 2 2
+1.05VS_A_SM AN17 VCCA_SM
AT16 VCCA_SM
R100 AR16 VCCA_SM

A SM
C
1 2 AP16 VCCA_SM C
10U_0805_10V4Z

1 0_0805_5%
1 1 1
C94

C95

+ C96 C97
+VCC_PEG +VCCP
220U_D2_4VM 4.7U_0805_10V4Z
2 2 2 2 321.35mA +1.05VS_MPLL +VCCP R102
1U_0603_10V4Z AP28 R101 1 2
VCCA_SM_CK 0_0805_5%
AN28 VCCA_SM_CK VCC_AXF B22 +V1.05VS_AXF 1 2

10U_0805_10V4Z
AP25 26mA B21 MBK2012121YZF_0805 1

AXF
+1.05VS_A_SM_CK VCCA_SM_CK VCC_AXF

220U_D2_4VM
R103 AN25 A21 1
VCCA_SM_CK VCC_AXF +

C101
1 2 AN24 VCCA_SM_CK
26mA 1 1
1U_0603_10V4Z

0.1U_0402_16V4Z

C98
0_0603_5% AM28 124mA C99 C100
VCCA_SM_CK_NCTF
10U_0805_10V4Z

AM26 VCCA_SM_CK_NCTF 2 2
1 1 1 1 AM25 VCCA_SM_CK_NCTF A CK 0.1U_0402_16V4Z
2 2
10U_0805_10V4Z
C103

C104

C105

C102 AL25 BF21 +1.5V_SM_CK

SM CK
VCCA_SM_CK_NCTF VCC_SM_CK
AM24 VCCA_SM_CK_NCTF VCC_SM_CK BH20
1U_0603_10V4Z AL24 BG20
2 2 2 2 VCCA_SM_CK_NCTF VCC_SM_CK
AM23 VCCA_SM_CK_NCTF VCC_SM_CK BF20
AL23 VCCA_SM_CK_NCTF
118.8mA
TVA 24.15mA +1.05VS_DMI
TVB 39.48mA K47 +1.05VS_PEGPLL +VCCP +VCCP
VCC_TX_LVDS +1.8V_TXLVDS
B24 TVX 24.15mA L1 R104
VCCA_TV_DAC +3VS_HV
A24 C35 1 2 1 2
TV

+3VS_TVDAC VCCA_TV_DAC VCC_HV

105.3mA VCC_HV B35 BLM18PG121SN1D_0603 0_0603_5%

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
A35
HV

VCC_HV
1 1

0.1U_0402_16V4Z

C106

C108
Check Again!!! +1.5VS A32 50mA 1
HDA

VCC_HDA

C109
VCC_PEG V48 +VCC_PEG 1

C107
1732mA U48
VCC_PEG 2 2
V47
PEG

VCC_PEG 2
U47
D TV/CRT

VCC_PEG 2
+1.5VS_TVDAC M25 VCCD_TVDAC
58.67mA VCC_PEG U46

B +1.5VS_QDAC L28 48.363mA B

VCCD_QDAC
VCC_DMI AH48 +1.05VS_DMI
+1.05VS_HPLL AF1 VCCD_HPLL
157.2mA VCC_DMI AF48
AH47
DMI

VCC_DMI
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL
50mA VCC_DMI AG47
+VCCP_D
456mA
M38
LVDS

VCCD_LVDS D3 R105 R106

+1.8V_LVDS L37 A8
VTTLF

VCCD_LVDS VTTLF
VTTLF L1 +VCCP 2 1 1 2 1 2 +3VS_HV
60.31mA AB2 10_0402_5% 0_0402_5%
VTTLF CH751H-40PT_SOD323-2
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

+3VS
1 1 1
C110

C111

C112

CANTIGA ES_FCBGA1329

2 2 2

+1.8V_LVDS +1.8V_TXLVDS
40 mils
R107 R108
1 2 +1.8V 1 2 +1.8V

@ R109

10U_0805_10V4Z

1U_0603_10V4Z

@ R110

1000P_0402_50V7K
0_0603_5% 0_0603_5%

1
+1.5VS_QDAC 1 1 1 @
+1.5VS

0_0603_5%

C113

C114

0_0603_5%

C116

220U_D2_4VM
+3VS_TVDAC 1
+3VS +

C115
R111 R112
2 2
1 2 1 2 2

2
2 2
0.022U_0402_16V7K

0.022U_0402_16V7K

BLM18PG181SN1D_0603 100_0603_1%
1

A A
@ R113

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 @
1
0_0603_5%

C117

C118

@ R114

C119

C120

220U_D2_4VM

1 1 1 1
0_0603_5%

C121

+
2

2 2 2 2 2
2

Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WWW.AliSaler.Com
Date: Saturday, July 18, 2009 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

WWW.AliSaler.Com
U2G +VCCP
0421 Change size to B2 for DFX 3000mA
Extnal Graphic: 1210.34mA request AP33 W28
VCC_SM VCC_AXG_NCTF
AN33 VCC_SM VCC_AXG_NCTF V28
integrated Graphic: 1930.4mA +1.5V BH32 W26 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
U2F VCC_SM VCC_AXG_NCTF
BG32 V26
VCC_SM VCC_AXG_NCTF

330U_B2_2.5VM_R15M

0.01U_0402_16V7K
+VCCP BF32 W25
VCC_SM VCC_AXG_NCTF 1 1 1

10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 V25 C127 C128 C129
VCC_SM VCC_AXG_NCTF
1 1 2 BC32 W24
VCC_SM VCC_AXG_NCTF

@
C126

C122

C130

C123
D
AG34 + BB32 V24 D
VCC VCC_SM VCC_AXG_NCTF 2 2 2
AC34 BA32 W23
VCC VCC_SM VCC_AXG_NCTF
AB34 AY32 V23
VCC 2 2 2 1 VCC_SM VCC_AXG_NCTF 0.22U_0402_10V4Z
AA34 AW32 AM21
VCC VCC_SM VCC_AXG_NCTF
Y34 AV32 AL21
VCC VCC_SM VCC_AXG_NCTF
V34 AU32 AK21
VCC VCC_SM VCC_AXG_NCTF
U34 AT32 W21
VCC 0317 change value VCC_SM VCC_AXG_NCTF
AM33 AR32 V21
VCC VCC_SM VCC_AXG_NCTF
AK33 VCC AP32 VCC_SM VCC_AXG_NCTF U21

POWER
AJ33 AN32 AM20
VCC VCC_SM VCC_AXG_NCTF
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 BH31 AK20
VCC VCC_SM VCC_AXG_NCTF
220U_D2_4VM

10U_0805_10V4Z

1 AF33 BG31 W20

VCC CORE
VCC VCC_SM VCC_AXG_NCTF
1 1 1 1 BF31 VCC_SM VCC_AXG_NCTF U20
C131

C124

C132

C133

+ C125
AE33 VCC BG30 VCC_SM VCC_AXG_NCTF AM19
AC33 VCC BH29 VCC_SM VCC_AXG_NCTF AL19
AA33 VCC BG29 VCC_SM VCC_AXG_NCTF AK19
2 2 2 2 2 Y33 BF29 AJ19
VCC VCC_SM VCC_AXG_NCTF
W33 VCC BD29 VCC_SM VCC_AXG_NCTF AH19
V33 BC29 AG19

VCC SM
VCC VCC_SM VCC_AXG_NCTF
U33 VCC BB29 VCC_SM VCC_AXG_NCTF AF19
AH28 VCC BA29 VCC_SM VCC_AXG_NCTF AE19
AF28 VCC AY29 VCC_SM VCC_AXG_NCTF AB19
AC28 VCC AW29 VCC_SM VCC_AXG_NCTF AA19
AA28 VCC AV29 VCC_SM VCC_AXG_NCTF Y19
AJ26 VCC AU29 VCC_SM VCC_AXG_NCTF W19
AG26 VCC AT29 VCC_SM VCC_AXG_NCTF V19
AE26 VCC AR29 VCC_SM VCC_AXG_NCTF U19
AC26 VCC AP29 VCC_SM VCC_AXG_NCTF AM17
AH25 VCC VCC_AXG_NCTF AK17
AG25 VCC BA36 VCC_SM/NC VCC_AXG_NCTF AH17
AF25 VCC BB24 VCC_SM/NC VCC_AXG_NCTF AG17
AG24 VCC BD16 VCC_SM/NC VCC_AXG_NCTF AF17
C
AJ23 +VCCP BB21 AE17 C
VCC VCC_SM/NC VCC_AXG_NCTF
AH23 VCC AW16 VCC_SM/NC VCC_AXG_NCTF AC17
AF23 VCC AW13 VCC_SM/NC VCC_AXG_NCTF AB17
POWER
VCC_NCTF AM32 AT13 VCC_SM/NC VCC_AXG_NCTF Y17
T32 VCC VCC_NCTF AL32 VCC_AXG_NCTF W17
VCC_NCTF AK32 6326.84mA VCC_AXG_NCTF V17

VCC GFX NCTF

VCC_NCTF AJ32 VCC_AXG_NCTF AM16
AH32 Y26 AL16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AG32 AE25 AK16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AE32 AB25 AJ16
VCC_NCTF +VCCP VCC_AXG VCC_AXG_NCTF
AC32 AA25 AH16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AA32 AE24 AG16
VCC_NCTF 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_AXG VCC_AXG_NCTF
Y32 AC24 AF16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
VCC_NCTF W32 AA24 VCC_AXG VCC_AXG_NCTF AE16

330U_D2E_2.5VM_R7
U32 Y24 AC16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AM30 1 1 1 1 1 AE23 AB16
VCC_NCTF C134 C136 C137 C138 VCC_AXG VCC_AXG_NCTF
AL30 AC23 AA16
VCC_NCTF + C135 VCC_AXG VCC_AXG_NCTF
AK30 AB23 Y16
VCC_NCTF 1U_0603_10V4Z VCC_AXG VCC_AXG_NCTF
AH30 AA23 W16
VCC_NCTF 2 2 2 2 VCC_AXG VCC_AXG_NCTF
AG30 AJ21 V16
VCC_NCTF 2 VCC_AXG VCC_AXG_NCTF
AF30 AG21 U16
VCC_NCTF 10U_0805_10V4Z VCC_AXG VCC_AXG_NCTF
AE30 AE21
VCC_NCTF VCC_AXG
VCC_NCTF AC30 AC21 VCC_AXG
AB30 AA21
VCC_NCTF VCC_AXG
AA30 Y21
VCC_NCTF VCC_AXG
Y30 AH20
VCC NCTF

VCC_NCTF VCC_AXG
W30 AF20
VCC_NCTF VCC_AXG
VCC_NCTF V30 AE20 VCC_AXG
U30 AC20
VCC_NCTF VCC_AXG
AL29 AB20
VCC_NCTF VCC_AXG
AK29 AA20
VCC_NCTF VCC_AXG
AJ29 T17
B VCC_NCTF VCC_AXG B
VCC_NCTF AH29 T16 VCC_AXG
AG29 AM15
VCC_NCTF VCC_AXG
AE29 AL15
VCC_NCTF VCC_AXG
AC29 AE15
VCC_NCTF VCC_AXG
AA29 AJ15
VCC_NCTF VCC_AXG
Y29 AH15
VCC_NCTF VCC_AXG
W29 AG15
VCC_NCTF VCC_AXG
V29 AF15
VCC_NCTF VCC_AXG
AL28 AB15
VCC_NCTF VCC_AXG
AK28 AA15
VCC_NCTF VCC_AXG
AL26 Y15

VCC GFX
VCC_NCTF VCC_AXG
VCC_NCTF AK26 V15 VCC_AXG
AK25 U15
VCC_NCTF VCC_AXG
AK24 AN14
VCC_NCTF VCC_AXG
AK23 AM14
VCC_NCTF VCC_AXG
U14 AV44 VCCSM_LF1
VCC_AXG VCC_SM_LF
T14 BA37 VCCSM_LF2

VCC SM LF
VCC_AXG VCC_SM_LF
AM40 VCCSM_LF3
VCC_SM_LF
AV21 VCCSM_LF4
VCC_SM_LF
AY5 VCCSM_LF5
VCC_SM_LF
AM10 VCCSM_LF6
VCC_SM_LF
CANTIGA ES_FCBGA1329
VCC_SM_LF BB13 VCCSM_LF7

C139 0.1U_0402_16V4Z

C140 0.1U_0402_16V4Z

C141

C142

C143

C144

C145
1 1 1 1 1 1 1

PAD T42 AJ14

VCC_AXG_SENSE
PAD T43 AH14
VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
A A

CANTIGA ES_FCBGA1329

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 13 of 45
 5 4 3 2 1

WWW.AliSaler.Com U2J
U2I BG21 AH8
VSS VSS
L12 VSS VSS Y8
AU48 VSS VSS AM36 AW21 VSS VSS L8
AR48 VSS VSS AE36 AU21 VSS VSS E8
AL48 VSS VSS P36 AP21 VSS VSS B8
BB47 VSS VSS L36 AN21 VSS VSS AY7
AW47 J36 AH21 AU7
VSS VSS VSS VSS
AN47 F36 AF21 AN7
VSS VSS VSS VSS
AJ47 B36 AB21 AJ7
VSS VSS VSS VSS
AF47 AH35 R21 AE7
D VSS VSS VSS VSS D
AD47 AA35 M21 AA7
VSS VSS VSS VSS
AB47 Y35 J21 N7
VSS VSS VSS VSS
Y47 U35 G21 J7
VSS VSS VSS VSS
T47 T35 BC20 BG6
VSS VSS VSS VSS
N47 BF34 BA20 BD6
VSS VSS VSS VSS
L47 AM34 AW20 AV6
VSS VSS VSS VSS
G47 AJ34 AT20 AT6
VSS VSS VSS VSS
BD46 AF34 AJ20 AM6
VSS VSS VSS VSS
BA46 VSS VSS AE34 AG20 VSS VSS M6
AY46 W34 Y20 C6
VSS VSS VSS VSS
AV46 B34 N20 BA5
VSS VSS VSS VSS
AR46 VSS VSS A34 K20 VSS VSS AH5
AM46 VSS VSS BG33 F20 VSS VSS AD5
V46 VSS VSS BC33 C20 VSS VSS Y5
R46 VSS VSS BA33 A20 VSS VSS L5
P46 VSS VSS AV33 BG19 VSS VSS J5
H46 VSS VSS AR33 A18 VSS VSS H5
F46 VSS VSS AL33 BG17 VSS VSS F5
BF44 VSS VSS AH33 BC17 VSS VSS BE4
AH44 VSS VSS AB33 AW17 VSS
AD44 P33 AT17 BC3
AA44
Y44
VSS
VSS
VSS
VSS
VSS
VSS
L33
H33
R17
M17
VSS
VSS
VSS
VSS VSS
VSS
VSS
AV3
AL3
U44 VSS VSS N32 H17 VSS VSS R3
T44 K32 C17 P3
M44
F44
VSS
VSS
VSS
VSS VSS
VSS
VSS
F32
C32 BA16
VSS

VSS
VSS
VSS
VSS
F3
BA2
BC43 VSS VSS A31 VSS AW2
AV43 VSS VSS AN29 AU16 VSS VSS AU2
AU43 VSS VSS T29 AN16 VSS VSS AR2
AM43 VSS VSS N29 N16 VSS VSS AP2
J43 VSS VSS K29 K16 VSS VSS AJ2
C C
C43 VSS VSS H29 G16 VSS VSS AH2
BG42 VSS VSS F29 E16 VSS VSS AF2
AY42 VSS VSS A29 BG15 VSS VSS AE2
AT42 VSS VSS BG28 AC15 VSS VSS AD2
AN42 VSS VSS BD28 W15 VSS VSS AC2
AJ42 VSS VSS BA28 A15 VSS VSS Y2
AE42 VSS VSS AV28 BG14 VSS VSS M2
N42 AT28 AA14 K2
VSS VSS VSS VSS
L42 AR28 C14 AM1
VSS VSS VSS VSS
BD41 AJ28 BG13 AA1
VSS VSS VSS VSS
AU41 AG28 BC13 P1
VSS VSS VSS VSS
AM41 AE28 BA13 H1
VSS VSS VSS VSS
AH41 AB28
VSS VSS
AD41 VSS VSS Y28 VSS U24
AA41 P28 AN13 U28
VSS VSS VSS VSS
Y41 K28 AJ13 U25
VSS VSS VSS VSS
U41 H28 AE13 U29
VSS VSS VSS VSS
T41 F28 N13
VSS VSS VSS
M41 C28 L13
VSS VSS VSS
G41 BF26 G13 AF32
VSS VSS VSS VSS_NCTF
B41 AH26 E13 AB32
VSS VSS VSS VSS_NCTF
BG40 AF26 BF12 V32
VSS VSS VSS VSS_NCTF
BB40 VSS VSS AB26 AV12 VSS VSS_NCTF AJ30
AV40 AA26 AT12 AM29
VSS VSS VSS VSS_NCTF
AN40 C26 AM12 AF29
VSS VSS VSS VSS_NCTF
H40 B26 AA12 AB29

VSS NCTF
VSS VSS VSS VSS_NCTF
E40 BH25 J12 U26
VSS VSS VSS VSS_NCTF
AT39 VSS VSS BD25 A12 VSS VSS_NCTF U23
AM39 BB25 BD11 AL20
VSS VSS VSS VSS_NCTF
AJ39 AV25 BB11 V20
VSS VSS VSS VSS_NCTF
AE39 AR25 AY11 AC19
VSS VSS VSS VSS_NCTF
N39 AJ25 AN11 AL17
B VSS VSS VSS VSS_NCTF B
L39 VSS VSS AC25 AH11 VSS VSS_NCTF AJ17
B39 Y25 AA17
VSS VSS VSS_NCTF
BH38 N25 Y11 U17
VSS VSS VSS VSS_NCTF
BC38 L25 N11
VSS VSS VSS
BA38 J25 G11
VSS VSS VSS
AU38 G25 C11 BH48

VSS SCB
VSS VSS VSS VSS_SCB
AH38 E25 BG10 BH1
VSS VSS VSS VSS_SCB
AD38 BF24 AV10 A48
VSS VSS VSS VSS_SCB
AA38 AD12 AT10 C1
VSS VSS VSS VSS_SCB
Y38 AY24 AJ10 A3
VSS VSS VSS VSS_SCB
U38 AT24 AE10
VSS VSS VSS
T38 VSS VSS AJ24 AA10 VSS NC E1
J38 AH24 M10 D2
VSS VSS VSS NC
F38 AF24 BF9 C3
VSS VSS VSS NC
C38 AB24 BC9 B4
VSS VSS VSS NC
BF37 R24 AN9 A5
VSS VSS VSS NC
BB37 VSS VSS L24 AM9 VSS NC A6
AW37 K24 AD9 A43
VSS VSS VSS NC
AT37 J24 G9 A44
VSS VSS VSS NC
AN37 G24 B9 B45

NC
VSS VSS VSS NC
AJ37 F24 BH8 C46
VSS VSS VSS NC
H37 VSS VSS E24 BB8 VSS NC D47
C37 BH23 AV8 B47
VSS VSS VSS NC
BG36 AG23 AT8 A46
VSS VSS VSS NC
BD36 Y23 F48
VSS VSS NC
AK15 B23 E48
VSS VSS NC
AU36 A23 C48
VSS VSS NC
VSS AJ6 NC B48

CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 14 of 45
 5 4 3 2 1

WWW.AliSaler.Com <10> DDR_A_DQS#[0..7]

+V_DDR3_DIMM_REF 1
JDIMM1
VREF_DQ VSS1 2
DDR_A_D4
<10> DDR_A_D[0..63] 3 VSS2 DQ4 4

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C166

C167
1 1 DDR_A_D1 7 8
<10> DDR_A_DM[0..7] DQ1 VSS3
9 10 DDR_A_DQS#0
DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
<10> DDR_A_DQS[0..7] 11 DM0 DQS0 12
13 VSS5 VSS6 14
2 2 DDR_A_D2 15 16 DDR_A_D6
<10> DDR_A_MA[0..14] DQ2 DQ6
DDR_A_D3 17 18 DDR_A_D7
DQ3 DQ7
Layout Note: DDR_A_D8
19
VSS7 VSS8
20
DDR_A_D12
21 22
Place these 4 caps near Command DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
D DQ9 DQ13 D
and Control signals of DIMMA DDR_A_DQS#1
25
VSS9 VSS10
26
DDR_A_DM1
Layout Note: DDR_A_DQS1
27
DQS#1 DM1
28
SM_DRAMRST#
29 30 SM_DRAMRST# <9,16>
Place near DQS1 RESET#
31 32
DDR_A_D10 VSS11 VSS12 DDR_A_D14
JDIMM1 33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 44
+1.5V DDR_A_DQS#2 VSS15 VSS16 DDR_A_DM2
45 46
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
VSS18 DQ22

330U_D2E_2.5VM_R7
DDR_A_D18 51 52 DDR_A_D23
DQ18 DQ23
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
1 1 1 1 1 1 1 1 1 1 55 VSS20 DQ28 56
C152

C147

C153

C154

C155

C158

C156

C148

C149

C157

C150
+ DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
2 2 2 2 2 2 2 2 2 2 2 DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<9> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <9>
+1.5V 75 VDD1 VDD2 76 +1.5V
77 78 @ R1107 1 2 0_0402_5%
DDR_A_BS2 NC1 A15 DDR_A_MA14
<10> DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
C DDR_A_MA12 DDR_A_MA11 C
Layout Note: DDR_A_MA9
83 A12/BC# A11 84
DDR_A_MA7
85 A9 A7 86
Place near JDIMM1.203 & JDIMM1.204 87 88
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
99 100
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
<9> M_CLK_DDR0 101 102 M_CLK_DDR1 <9>
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
<9> M_CLK_DDR#0 103 104 M_CLK_DDR#1 <9>
CK0# CK1#
105 106
+0.75V DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 <10>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<10> DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# <10>
111 112
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
113 114 DDR_CS0_DIMMA# <9>
<10> DDR_A_WE# WE# S0#
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

DDR_A_CAS# 115 116 M_ODT0

<10> DDR_A_CAS# CAS# ODT0 M_ODT0 <9>
117 118
DDR_A_MA13 VDD15 VDD16 M_ODT1
1 1 1 1 1 119 120 M_ODT1 <9>
A13 ODT1
C159

C160

C161

C162

C163

DDR_CS1_DIMMA# 121 122

<9> DDR_CS1_DIMMA# S1# NC2
123 124
VDD17 VDD18 +V_DDR3_DIMM_REF
125 126
2 2 2 2 2 NCTEST VREF_CA
127 VSS27 VSS28 128
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37
133 134 1 1
DDR_A_DQS#4 VSS29 VSS30 DDR_A_DM4
135 136
DQS#4 DM4

C146

C151
DDR_A_DQS4 137 138
DQS4 VSS31 DDR_A_D38
139 140
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_A_D44
145 146
B DDR_A_D40 VSS34 DQ44 DDR_A_D45 B
147 DQ40 DQ45 148
+1.5V DDR_A_D41 149 150
DQ41 VSS35 DDR_A_DQS#5
151 152
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
1

155 156
R1108 DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
1K_0402_1% DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
+V_DDR3_DIMM_REF DQ43 DQ47
161 162
DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
2

+V_DDR3_DIMM_REF DDR_A_D49 DQ48 DQ52 DDR_A_D53

<16> +V_DDR3_DIMM_REF 165 166
DQ49 DQ53
167 168
VSS41 VSS42
1
2.2U_0805_16V4Z

0.1U_0402_16V4Z

DDR_A_DQS#6 169 170 DDR_A_DM6

DDR_A_DQS6 DQS#6 DM6
1 1 171 172
DQS6 VSS43
C164

C165

R1109 173 174 DDR_A_D54

1K_0402_1% DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
2

2 2 DQ51 VSS45 DDR_A_D60

179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_A_DQS#7
185 186
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
R116 1 VSS51 VSS52 PM_EXTTS#0
2 10K_0402_5% 197 198 PM_EXTTS#0 <9>
SA0 EVENT# CLK_SMBDATA
+3VS 199 200 CLK_SMBDATA <16,17,24>
VDDSPD SDA CLK_SMBCLK
201 SA1 SCL 202 CLK_SMBCLK <16,17,24>
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

203 204 +0.75V

VTT1 VTT2
1 10K_0402_5%

1 1
205 206
G1 G2
C171

C172

R115

A TYCO_C-2013289 A
2 2 CONN@
2

SO-DIMM A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.ComMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 15 of 45
 5 4 3 2 1

WWW.AliSaler.Com <10> DDR_B_DQS#[0..7]

+V_DDR3_DIMM_REF

JDIMM2
<10> DDR_B_D[0..63] <15> +V_DDR3_DIMM_REF 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
<10> DDR_B_DM[0..7] 5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
<10> DDR_B_DQS[0..7] 9 VSS4 DQS#0 10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
<10> DDR_B_MA[0..14] 1 1 13 VSS5 VSS6 14

C173

C182
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 18
DQ3 DQ7
19 20
2 2 DDR_B_D8 VSS7 VSS8 DDR_B_D12
D
Layout Note: DDR_B_D9
21
DQ8 DQ12
22
DDR_B_D13 D
23 24
Place these 4 caps near Command DQ9 DQ13
25 26
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
Layout Note: and Control signals of DIMMB DDR_B_DQS1
27
DQS#1 DM1
28
SM_DRAMRST#
29 30 SM_DRAMRST# <9,15>
Place near DQS1 RESET#
31 32
DDR_B_D10 VSS11 VSS12 DDR_B_D14
JDIMM2 DDR_B_D11
33
DQ10 DQ14
34
DDR_B_D15
35 36
DQ11 DQ15
37 38
DDR_B_D16 VSS13 VSS14 DDR_B_D20
39 DQ16 DQ20 40
DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS15 VSS16 DDR_B_DM2
45 DQS#2 DM2 46
+1.5V DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
49 VSS18 DQ22 50
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
55 56 DDR_B_D28
DDR_B_D24 VSS20 DQ28 DDR_B_D29
1 1 1 1 1 1 1 1 1 1 57 DQ24 DQ29 58
C174

C175

C176

C183

C177

C184

C178

C179

C180

C181
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
2 2 2 2 2 2 2 2 2 2 DM3 DQS3
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<9> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <9>
+1.5V 75 VDD1 VDD2 76 +1.5V
77 78 @ R1110 1 2 0_0402_5%
NC1 A15

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_BS2 79 80 DDR_B_MA14
C <10> DDR_B_BS2 BA2 A14 C
81 VDD3 VDD4 82 1 1
Layout Note: DDR_B_MA12 83 84 DDR_B_MA11
A12/BC# A11

C190

C191
DDR_B_MA9 85 86 DDR_B_MA7
Place near JDIMM2.203 & JDIMM2.204 A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6 2 2
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
<9> M_CLK_DDR2 101 102 M_CLK_DDR3 <9>
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
<9> M_CLK_DDR#2 103 104 M_CLK_DDR#3 <9>
+0.75V CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 A10/AP BA1 108 DDR_B_BS1 <10>
DDR_B_BS0 109 110 DDR_B_RAS#
<10> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <10>
111 112
VDD13 VDD14
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

DDR_B_WE# 113 114 DDR_CS2_DIMMB#

<10> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <9>
DDR_B_CAS# 115 116 M_ODT2
<10> DDR_B_CAS# CAS# ODT0 M_ODT2 <9>
1 1 1 1 1 117 118
VDD15 VDD16
C185

C186

C187

C188

C189

DDR_B_MA13 119 120 M_ODT3

DDR_CS3_DIMMB# A13 ODT1 M_ODT3 <9>
<9> DDR_CS3_DIMMB# 121 122
S1# NC2
123 124
2 2 2 2 2 VDD17 VDD18
125 NCTEST VREF_CA 126 +V_DDR3_DIMM_REF
127 128
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 130
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134
DDR_B_DQS#4 VSS29 VSS30 DDR_B_DM4
135 DQS#4 DM4 136
DDR_B_DQS4 137 138
DQS4 VSS31 DDR_B_D38
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 142
DDR_B_D35 DQ34 DQ39
143 144
B DQ35 VSS33 DDR_B_D44 B
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 152
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_B_D60
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_B_DQS#7
185 186
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
R1111 2 VSS51 VSS52 PM_EXTTS#1
1 10K_0402_5% 197 198 PM_EXTTS#1 <9>
SA0 EVENT# CLK_SMBDATA
+3VS 199 VDDSPD SDA 200 CLK_SMBDATA <15,17,24>
R1112 2 1 10K_0402_5% 201 202 CLK_SMBCLK
+3VS SA1 SCL CLK_SMBCLK <15,17,24>
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

203 204 +0.75V

VTT1 VTT2
1 1
205 G1 G2 206
C192

C1403

A A
TYCO_C-2013310
2 2 CONN@

SO-DIMM B
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.ComMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 16 of 45
 5 4 3 2 1

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FSC FSB
CLKSEL2 CLKSEL1 CLKSEL0 MHz
FSA CPU SRC
MHz
PCI
MHz
REF
MHz
DOT_96
MHz
USB
MHz
+3VS
R121
1 2
+3VS_CK505

1 1 1 1 1 1 1
0_0805_5% C199 C200 C201 C202 C203 C204 C205
0 0 0 266 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
Routing the trace at least 10mil +VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0
CLK_XTAL_OUT
D CLK_XTAL_IN
Place close to U51 D
0 1 1 166 100 33.3 14.318 96.0 48.0 R122
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
Y1 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 1 2 C206 C207 C208 C209 C210 C211 C212
14.318MHZ_16PF_7A14300083
2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
1 1 0 400 100 33.3 14.318 96.0 48.0 C213 C214
18P_0402_50V8J 18P_0402_50V8J
1 1
1 1 1 Reserved
Vendor suggests 22pF
R123 +3VS_CK505 +1.05VS_CK505
1 2 +VCCP
1

56_0402_5% XDP/ITP
CLRP1
NO SHORT PADS R126 1 2 475_0402_1% R_CLKREQ#_7 R_MCH_3GPLL R127 1 2 0_0402_5%
2

<9> CLKREQ#_7 R_MCH_BCLK# R_MCH_3GPLL# CLK_MCH_3GPLL <9>

R128 R130 1 2 0_0402_5% R131 1 2 0_0402_5% 3G_PLL
FSA <9> CLK_MCH_BCLK# R_MCH_BCLK R_CLKREQ#_6 CLK_MCH_3GPLL# <9>
1 2 1 2 NB R132 1 2 0_0402_5% R133 1 2 475_0402_1%
MCH_CLKSEL0 <9> <9> CLK_MCH_BCLK CLKREQ#_6 <26>
2.2K_0402_5% R129 R134 1 2 0_0402_5% R_CPU_BCLK# R_CLK_PCIE_MCARD2 R135 1 2 0_0402_5%
<6> CLK_CPU_BCLK# R_CPU_BCLK R_CLK_PCIE_MCARD2# CLK_PCIE_MCARD2 <26>
R138 1K_0402_5% CPU R136 1 2 0_0402_5% R137 1 2 0_0402_5% MiniCard_2(WLAN)
<6> CLK_CPU_BCLK CLK_PCIE_MCARD2# <26>
<7> CPU_BSEL0 1 2 +3VS_CK505
0_0402_5%
1

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
R139 U3
1K_0402_5% +3VS_CK505 +1.05VS_CK505

VDD_CPU_IO

VDD_SRC_IO
CPU_0
CPU_0#

CPU_1
CPU_1#

CLKREQ_7#

SRC_8#/CPU_ITP#

SRC_7
SRC_7#

CLKREQ_6#
SRC_6
SRC_6#
SRC_8/CPU_ITP
VDD_CPU

VSS_CPU

VSS_SRC

VDD_SRC
C C
2

@ R141 1 2 0_0402_5%
<22,43> VGATE @ R142 1 2 0_0402_5%
+VCCP <43> CLK_ENABLE# R140 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI# 2MiniC@
<22> CK_PWRGD FSB CKPWRGD/PD# PCI_STOP# H_STP_CPU# H_STP_PCI# <22>
2 53 2MiniC@
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# <22>
3 VSS_REF VDD_SRC_IO 52
2

@ No Debug port anymore CLK_XTAL_OUT 4 51 R_CLK_PCIE_MCARD0# R144 1 2 0_0402_5%

XTAL_OUT SRC_10# CLK_PCIE_MCARD0# <26>
R143 CLK_XTAL_IN R_CLK_PCIE_MCARD0 R145 2 0_0402_5%
5
XTAL_IN SRC_10
50
R_CLKREQ#_10
1 CLK_PCIE_MCARD0 <26> MiniCard_0
1K_0402_5% 6 49 R146 1 2 475_0402_1%
FSC VDD_REF CLKREQ_10# R_CLK_SRC11 CLKREQ#_10 <26>
R147 1 2 33_0402_1% 7 48 R725 1 2 0_0402_5%
<22> CLK_14M_ICH REF1 REF_0/FS_C/TEST_ SRC_11 R_CLK_SRC11# R726 1 CLK_SRC11 <27>
8 47 2 0_0402_5% Cardreader
1

FSB CLK_SMBDATA REF_1 SRC_11# CLK_SRC11# <27>

1 2 <15,16,24> CLK_SMBDATA T44 9 46
MCH_CLKSEL1 <9> SDA CLKREQ_11#
R150 CLK_SMBCLK 10 45 R_CLK_PCIE_LAN# R152 1 2 0_0402_5%
<15,16,24> CLK_SMBCLK SCL SRC_9# R_CLK_PCIE_LAN CLK_PCIE_LAN# <25>
R154 1K_0402_5% 11 44 R153 1 2 0_0402_5% LAN
NC SRC_9 R_CLKREQ#_9 CLK_PCIE_LAN <25>
1 2 12 43 R738 1 2 475_0402_1%
<7> CPU_BSEL1 PCI2_1 VDD_PCI CLKREQ_9# CLKREQ#_9 <25>
0_0402_5% R393 1 2 39_0402_1% 13 42
PCI_1 VSS_SRC
1

<26> CLK_DEBUG_PORT_1
CLK_DEBUG_PORT_0 R155 1 2 39_0402_1% PCI2_TME 14 41 R_CLKREQ#_4 R156 1 2 475_0402_1%
PCI_2 CLKREQ_4# CLKREQ#_4 <26>
@ R158 1 2 33_0402_1% 27_SEL 15 40 R_CLK_PCIE_NCARD# R159 1 2 0_0402_5%
<32> CLK_PCI_EC PCI_CLK3 PCI_3 SRC_4# R_CLK_PCIE_NCARD CLK_PCIE_NCARD# <26>
R157 16 39 R160 1 2 0_0402_5% New Card
PCI_4/SEL_LCDCL SRC_4 CLK_PCIE_NCARD <26>

USB_1/CLKREQ_A#
0_0402_5% R161 1 2 33_0402_1% ITP_EN 17 38

LCDCLK#/27M_SS
<20> CLK_PCI_ICH PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
18 37 R_CLKREQ#_C R162 1 2 475_0402_1%
2

VSS_PCI CLKREQ_3# CLKREQ#_C <22>

SRC_0/DOT_96

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A

VDD_PLL3

VSS_PLL3
NewC@

VSS_SRC
+VCCP

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48
NewC@

VSS_IO

SRC_2

SRC_3
Change 33M and 48M damping to 39M by EMI request
1

@
R163 SLG8SP553VTR_QFN72_10x10

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1K_0402_5% +3VS_CK505

B R164 R_PCIE_SATA# R166 0_0402_5% B

1 2
2

FSC FSA R_PCIE_SATA CLK_PCIE_SATA# <21>

1 2 1 2 R167 1 2 39_0402_1% R168 1 2 0_0402_5% SATA
MCH_CLKSEL2 <9> <22> CLK_48M_ICH R_CLK_48M_CRUSB CLK_PCIE_SATA <21>
10K_0402_5% R165
R171 1K_0402_5% T76 R_PCIE_ICH# R170 1 2 0_0402_5%
CLK_PCIE_ICH# <22>
1 2 R_PCIE_ICH R172 1 2 0_0402_5% ICH
<7> CPU_BSEL2 +1.05VS_CK505 CLK_PCIE_ICH <22>
0_0402_5% +1.05VS_CK505
1

R173 1 2 0_0402_5% R_MCH_DREFCLK

<9> CLK_MCH_DREFCLK R_MCH_DREFCLK# SSCDREFCLK#
@ NB (UMA) R175 1 2 0_0402_5% R176 1 2 0_0402_5%
<9> CLK_MCH_DREFCLK# SSCDREFCLK MCH_SSCDREFCLK# <9>
R174 R177 0_0402_5%
1 2 MCH_SSCDREFCLK <9> NB_SSC (UMA)
0_0402_5%
2

+3VS

+3VS
0 = SRC8/SRC8#
ITP_EN +3VS
02/13 Add 12P on CLK_14M_ICH for WWAN noise
1 = ITP/ITP# R178 R179
0 = Enable DOT96 & SRC1(UMA) 2.2K_0402_5% 2.2K_0402_5%
PCI_CLK3 @ C215 CLK_48M_ICH
1 = Enable SRC0 & 27MHz(DIS) 2 1
2

Q3A 5P_0402_50V8C
C216 2 1 CLK_14M_ICH
<22,26> ICH_SMBDATA 6 1 CLK_SMBDATA 12P_0402_50V8J
+3VS +3VS @ C217 2 1 CLK_PCI_ICH
5

SB, MINI PCI Q3B 2N7002DW-7-F_SOT363-6 4.7P_0402_50V8C

@ C218 2 1 CLK_PCI_EC
1

@ 3 4 CLK_SMBCLK 4.7P_0402_50V8C
<22,26> ICH_SMBCLK
R180 R181 @ C219 2 1 CLK_DEBUG_PORT_0
10K_0402_5% 10K_0402_5% 2N7002DW-7-F_SOT363-6 5P_0402_50V8C
A A
2

<BOM Structure>
ITP_EN PCI_CLK3
1

@
R182 R183
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
Clock Generator CK505
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 17 of 45
 A B C D E

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BLUE
GREEN
RED
Place close to
@ D5 @ D6 @ D7
JCRT1

1
1 +5VS +RCRT_VCC +CRTVDD 1

DAN217T146_SC59-3

DAN217T146_SC59-3

DAN217T146_SC59-3
D4 F1
2 1 1 2 W=40mils
CRT Connector RB491D_SC59-3 1.1A_6VDC_FUSE
1

3
+CRTVDD
0.1U_0402_16V4Z
C220 2
JCRT1
6
11
RED 1
<34> RED
7
12
GREEN 2
<34> GREEN
8
13
<34> D_HSYNC BLUE 3
<34> BLUE
9
<34> D_VSYNC 14
4 16
+5VS +5VS 10 17
15
C221 C222 5
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2 SUYIN_070546FR015S263ZR
CONN@
+3VS
+CRTVDD +CRTVDD +3VS
5
1

U4
SN74AHCT1G125GW_SOT353-5 R184
OE#
P

1
1
2 CRT_HSYNC HSYNC_G_A D_HSYNC 2
<11> CRT_HSYNC 2 A Y 4 1 2 0_0603_5%
R185 R186 R187 R188
G

5
1

2.2K_0402_5% 2.2K_0402_5%

2
R189 2.2K_0402_5% 2.2K_0402_5%
OE#
P
3

CRT_VSYNC 2 4 VSYNC_G_A 1 2 0_0603_5% D_VSYNC

2
2
<11> CRT_VSYNC A Y D_DDCDATA 3VDDCDA
6 1 3VDDCDA <11>
G

U5 1 @ 1 @
SN74AHCT1G125GW_SOT353-5 C223 C224
3

Q5A

5
5P_0402_50V8C 5P_0402_50V8C 2N7002DW-7-F_SOT363-6
2 2 D_DDCCLK 3 4 3VDDCCL
3VDDCCL <11>

Q5B
2N7002DW-7-F_SOT363-6

D_DDCDATA <34>
D_DDCCLK <34>

CRT Termination/EMI Filter 11/07 Change CRT lounting NB-->Docking-->CRT connector

3 3

C_RED L2 1 2 RED
<11> M_RED
HLC0603CSCCR11JT_0603

C_GRN L3 1 2 GREEN
<11> M_GREEN
HLC0603CSCCR11JT_0603

C_BLU L4 1 2 BLUE
<11> M_BLUE
HLC0603CSCCR11JT_0603
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1

1
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1 1 1 1
R195

R196

R197
2

2 2 2 2 2 2

@ C225 @ C226 @C227

@ C227 C228 C229 C230

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

A B
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
E
Sheet 18 of 45
 5 4 3 2 1

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+3VS +LCDVDD INVPWR_B+

C235 C236 C237

D
LVDS CONN & USB Camera + Dig Mic D
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
1 02/20 Change to 0805 size
1

1
+LCDVDD +3VS
+LCDVDD +LCDVDD +5VALW Q7
SI2301BDS-T1-E3_SOT23-3
2

2
2

1
JLVDS1 1 3

S
D

4.7U_0805_10V4Z
1 2 LVDS_A2- 1
1 2 LVDS_A2+ LVDS_A2- <11>
3 4 1 1 R198 R199
3 4 LVDS_A1- LVDS_A2+ <11>
5 6 C231 C232 470_0805_5% 1M_0402_5% C233 1

G
2
5 6 LVDS_A1+ LVDS_A1- <11>
7 8 4.7U_0805_10V4Z

6 2

2
7 8 LVDS_A0- LVDS_A1+ <11> 2
9 10 0.1U_0402_16V4Z 0.1U_0402_16V4Z C234
9 10 LVDS_A0+ LVDS_A0- <11> 2 2
11 11 12 12 LVDS_A0+ <11>
USB20_P4 13 14 LVDS_ACLK- 2
<22> USB20_P4 USB20_N4 13 14 LVDS_ACLK+ LVDS_ACLK- <11>
15 16 R200
<22> USB20_N4 15 16 LVDS_ACLK+ <11>
17 17 18 18 2 2 1
+3VS 19 19 20 20 11/07 Change R727 to 0805 size
21 22 2N7002DW-7-F_SOT363-6 100K_0402_5%

1
21 22 DMIC_DAT C238
23 23 24 24 DMIC_DAT <28> Q8A
25 26 DMIC_CLK
25 26 +3V_LOGO DMIC_CLK <28> 0.047U_0402_16V7K
27 28 R727 1 2 +5VS
27 28 INV_PWM
29 29 30 30 100_0805_5%
INV_PWM <32> 02/13 Reserve

3
31 32 BKOFF# BKOFF# <32> Limited Current < 1A 01/03 Change to 0.047u to meet T1 timing
31 32 DAC_BRIG
11/17 Delete LVDS B 33 33 34 34 DAC_BRIG <32> BKOFF#
35 36 +USB_CAM Q8B
35 36 DDC2_CLK 2N7002DW-7-F_SOT363-6
37 37 38 38 DDC2_CLK <11> <11> ENAVDD 5
39 40 DDC2_DATA
39 40

1
41 42 DDC2_DATA <11>

4
GND GND @ R245 R201
ACES_88242-4001 10K_0402_5% 100K_0402_5%
CONN@
C C

2
1 1
C435 C434
680P_0402_50V7K 680P_0402_50V7K Avoid Panel display garbage after power on.
2 2

0308_Install all cap for EMI request.

B+ INVPWR_B+

+3VS 、 26
Must close JLVDS1pin 24、 @
L5 0_0805_5%
1 2

DMIC_CLK
L6 1 2
DMIC_DAT FBMA-L11-201209-221LMA30T_0805
2

LVDS_ACLK+ @ C1399 1 2 100P_0402_50V8J

LVDS_ACLK- @ C1400 1 2 100P_0402_50V8J R202 R203 1 1 0308_Reserve L10 and install L11.
DDC2_CLK @ C1401 1 2 100P_0402_50V8J 2.2K_0402_5% 2.2K_0402_5% @ C302 @ C303
DDC2_DATA @ C1402 1 2 100P_0402_50V8J
220P_0402_25V8J 220P_0402_25V8J
1

DDC2_CLK 2 2
DDC2_DATA
0831 EMI request
11/09 EMI reserver
B B

USB Camera
+5VALW +5VS +USB_CAM
1

U42
1

@ PJP6 PJP5
PAD-OPEN 2x2m PAD-OPEN 2x2m 1 5 R1091
IN OUT 215K_0603_1%
2
GND
1
2

3 4 C1391
SHDN BYP
1
1

C1392 G916-390T1UF_SOT23-5 10U_0805_6.3V6M

2

10U_0805_6.3V6M R1093 2
R440 100K_0402_1%
2 0_0402_5%
2
1

@ R441 1 2 0_0402_5%
<22> GPIO20

A
11/07 Change U42 to 3.9V LDO(Adjustable) A

， R1093 to 100K
11/07 Change R1091 to 215K，
、 C1392 to 0805 size
11/08 Change C1391、

+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm +USB_CAM=1.25(1+R1091/R1093)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 19 of 45
 5 4 3 2 1

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+3VS

R272 1 2 8.2K_0402_5% PCI_DEVSEL#

R273 1 2 8.2K_0402_5% PCI_STOP#

R274 1 2 8.2K_0402_5% PCI_TRDY#

R275 1 2 8.2K_0402_5% PCI_FRAME# U12B

D11 F1 PCI_REQ0#
R276 1 PCI_PLOCK# AD0 REQ0# PCI_GNT0#
2 8.2K_0402_5% C8
AD1 GNT0#
G4
D PCI_REQ1# D
R277 1 2 8.2K_0402_5% PCI_IRDY#
D9
E12
AD2 PCI REQ1#/GPIO50
B6
A7
AD3 GNT1#/GPIO51 PCI_REQ2#
E9 F13
R278 1 PCI_SERR# AD4 REQ2#/GPIO52
2 8.2K_0402_5% C9
AD5 GNT2#/GPIO53
F12
E10 E6 PCI_REQ3#
R279 1 PCI_PERR# AD6 REQ3#/GPIO54 PCI_GNT3#
2 8.2K_0402_5% B7 F6
AD7 GNT3#/GPIO55
C7
AD8
C5 D8
AD9 C/BE0#
G11 AD10 C/BE1# B4 Place closely pin D4
F8 D6
AD11 C/BE2#
F11 A5
AD12 C/BE3# CLK_PCI_ICH
E7 AD13
A3 D3 PCI_IRDY#
AD14 IRDY#

1
+3VS D2 E3 @
AD15 PAR PCI_RST# R280
F10 AD16 PCIRST# R1 PCI_RST# <32>
D5 C6 PCI_DEVSEL# 10_0402_5%
R281 1 PCI_PIRQA# AD17 DEVSEL# PCI_PERR#
2 8.2K_0402_5% D10 AD18 PERR# E4
B3 C2 PCI_PLOCK#

2
R282 1 PCI_PIRQB# AD19 PLOCK# PCI_SERR#
2 8.2K_0402_5% F7 AD20 SERR# J4 PCI_SERR# <32>
C3 A4 PCI_STOP# 1
R283 1 PCI_PIRQC# AD21 STOP# PCI_TRDY#
2 8.2K_0402_5% F3 AD22 TRDY# F5 @
F4 D7 PCI_FRAME# C425
R284 1 PCI_PIRQD# AD23 FRAME#
2 8.2K_0402_5% C1 AD24
8.2P_0402_50V
G7 C14 PLT_RST# 2
AD25 PLTRST# PLT_RST# <9,25,26,27>
R285 1 2 8.2K_0402_5% PCI_PIRQE# H7 D4 CLK_PCI_ICH
AD26 PCICLK PCI_PME# CLK_PCI_ICH <17>
D1 AD27 PME# R2 PCI_PME# <32>
R286 1 2 8.2K_0402_5% PCI_PIRQF# G5 AD28
H6 AD29 3/28 PCI_PME# Remvoe 8.2k pull high +3VALW
R287 1 2 8.2K_0402_5% PCI_PIRQG# G1
H3
AD30 resistance.
R288 2 PCI_PIRQH# AD31
1 8.2K_0402_5%
C C
PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
R289 1 PCI_REQ0# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
2 8.2K_0402_5% E1 K6
PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
J6 PIRQC# PIRQG#/GPIO4 F2
R290 1 2 8.2K_0402_5% PCI_REQ1# PCI_PIRQD# C4 G2 PCI_PIRQH# 1 2
PIRQD# PIRQH#/GPIO5 ACCEL_INT <24>
R291 0_0402_5%
R292 1 2 8.2K_0402_5% PCI_REQ2# ICH9-M ES_FCBGA676 GS@

R293 1 2 8.2K_0402_5% PCI_REQ3#

A16 swap override Strap

B
Boot BIOS Strap B
Low= A16 swap override Enble
PCI_GNT3# High= * PCI_GNT0# SPI_CS#1 Boot BIOS Location
Default
@R294 0 1 SPI
PCI_GNT3# 1 2
1K_0402_5%
1 0 PCI

1 1 LPC *

+3VALW

@ R295
SPI_CS1#_R 1 2
<22> SPI_CS1#_R
1K_0402_5%
@ R296
PCI_GNT0# 1 2
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 20 of 45
 5 4 3 2 1

WWW.AliSaler.Com
+RTCVCC
ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5,
： follow check list ver:1.5 change to 8.2K ohm
PV：

VccCL1.5) +3VS

SM_INTRUDER#
ICH_INTVRMEN Low = Internal VR Disabled R298
1 2
R297 1M_0402_5% High = Internal VR Enabled(Default) GATEA20 1 2
1 2 LAN100_SLP 8.2K_0402_5%
R299 330K_0402_5%
1 2 ICH_INTVRMEN ICH8M LAN100 SLP Strap R301
R300 330K_0402_5% KB_RST# 1 2
1 2 ICH_SRTCRST# (Internal VR for VccLAN1.05 and VccCL1.05) 10K_0402_5%
R302 180K_0402_5%

1
0_0402_5%

0_0402_5%
D D
1
C426 @ @ ICH_LAN100_SLP Low = Internal VR Disabled +VCCP
R303 R304
0.1U_0402_16V4Z High = Internal VR Enabled(Default) @ R305
2 H_DPRSTP# 1 2

2
56_0402_5%
LPC_AD[0..3] <26,32>
U12A @ R306
ICH_RTCX1 C23 K5 LPC_AD0 H_DPSLP# 1 2
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
C24 K4
R307 RTCX2 FWH1/LAD1 LPC_AD2
L6
ICH_RTCRST# FWH2/LAD2 LPC_AD3
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2
20K_0402_5% ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <26,32>
+VCCP

RTC
1

LPC
1
C427 CLRP2 ICH_INTVRMEN B22 J3
SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1U_0603_10V4Z T54 PAD

2
2 GATEA20
E25 GLAN_CLK A20GATE N7 GATEA20 <32>
AJ27 H_A20M# R308
A20M# H_A20M# <6>
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R309 H_DPRSTP#
DPRSTP# AJ25 1 2 H_DPRSTP# <7,9,43>
F14 AE23 H_DPSLP# 0_0402_5%

1
LAN_RXD0 DPSLP# H_DPSLP# <7>
G13 LAN_RXD1
12P_0402_50V8J D14 AJ26 R_H_FERR# R310 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# <6>

LAN / GLAN
C331 1 2 HDA_BITCLK 56_0402_5%
D13 AD22 H_PWRGOOD 3/28 add 56ohm
+1.5VS LAN_TXD_0 CPUPWRGD H_PWRGOOD <7>
D12 LAN_TXD_1
R311 E13 AF25 H_IGNNE#
LAN_TXD_2 IGNNE# H_IGNNE# <6>
24.9_0402_1% within 2" from R379
1 2 GLAN_COMP B10 AE22 H_INIT#
GPIO56 INIT# H_INTR H_INIT# <6> +VCCP
R312 33_0402_5% 1 2 R259 AG25

CPU
C <28> HDA_BITCLK_CODEC HDABITCLK 1 INTR KB_RST# H_INTR <6> C
R313 33_0402_5% 1 2 2 B28 L3
<29> HDA_BITCLK_MDC GLAN_COMPI RCIN# KB_RST# <32>
R207 33_0402_5% 1 2 0_0402_5% B27
<9> HDA_BITCLK_NB GLAN_COMPO

1
R316 33_0402_5% 1 2 AF23 H_NMI
<28> HDA_SYNC_CODEC HDA_BITCLK NMI H_SMI# H_NMI <6>
R314 33_0402_5% 1 2 AF6 AF24 R315
<29> HDA_SYNC_MDC HDA_SYNC HDA_BIT_CLK SMI# H_SMI# <6>
R208 33_0402_5% 1 2 AH4 56_0402_5%
<9> HDA_SYNC_NB HDA_SYNC H_STPCLK#
R317 33_0402_5% 1 2 AH27
<28,32> HDA_RST#_CODEC STPCLK# H_STPCLK# <6>
R318 33_0402_5% 1 2 HDARST# AE7

2
<29> HDA_RST#_MDC HDA_RST#
R209 33_0402_5% 1 2 AG26 THRMTRIP_ICH# R319 1 2 54.9_0402_1%
<9> HDA_RST#_NB THRMTRIP# H_THERMTRIP# <6,9>
HDA_SDIN0 AF4
<28> HDA_SDIN0 HDA_SDIN1 HDA_SDIN0
<29> HDA_SDIN1 AG4
HDA_SDIN1 TP12
AG27 placed within 2"
HDA_SDIN2 AH3
<9> HDA_SDIN2 HDA_SDIN2 from ICH9M
AE5

IHDA
R320 33_0402_5% HDA_SDIN3
<29> HDA_SDOUT_MDC 1 2 AH11 SATA_RXN4_C <24>
R321 33_0402_5% HDA_SDOUT SATA4RXN 0.01U_0402_16V7K
<28> HDA_SDOUT_CODEC 1 2 AG5 HDA_SDOUT SATA4RXP AJ11 SATA_RXP4_C <24>
SATA_TXN4_C SATA_TXN4
<9> HDA_SDOUT_NB
R204 33_0402_5% 1 2
AG7
SATA4TXN
AG12
AF12 SATA_TXP4_C
PR@
PR@
2
2
1 C428
1 C429 SATA_TXP4 SATA_TXN4 <24> ODD
PAD T55 HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TXP4 <24>
PAD T56 AE8
HDA_DOCK_RST#/GPIO34 0.01U_0402_16V7K
SATA_LED# AG8
<33> SATA_LED# SATALED#
AH9 SATA_RXN5_C <30>
SATA5RXN
<24> SATA_RXN0_C
0.01U_0402_16V7K
AJ16
AH16
SATA0RXN SATA5RXP
AJ9
AE10 SATA_TXN5_C 2
0.01U_0402_16V7K
1 C430 SATA_TXN5 SATA_RXP5_C <30> e-SATA
<24> SATA_RXP0_C SATA0RXP SATA5TXN SATA_TXN5 <30>
SATA_TXN0 C431 1 2 SATA_TXN0_C AF17 AF10 SATA_TXP5_C 2 1 C432 SATA_TXP5 De-feature disable
P- HDD <24> SATA_TXN0 SATA_TXP0 C433 1 2 SATA_TXP0_C AG17
SATA0TXN SATA5TXP ESATA@ 0.01U_0402_16V7K
SATA_TXP5 <30>
<24> SATA_TXP0 SATA0TXP CLK_PCIE_SATA#
AH18 ESATA@
SATA_CLKN CLK_PCIE_SATA# <17>

SATA
0.01U_0402_16V7K AH13 AJ18 CLK_PCIE_SATA
<24> SATA_RXN1_C SATA1RXN SATA_CLKP CLK_PCIE_SATA <17>
0.01U_0402_16V7K AJ13 AJ7
<24> SATA_RXP1_C SATA1RXP SATARBIAS#
SATA_TXN1 C820 1 2 Multi@ SATA_TXN1_C AG14 AH7 R322 1 2
<24> SATA_TXN1 SATA_TXP1 SATA_TXP1_C SATA1TXN SATARBIAS
C821 1 2 Multi@ AF14 24.9_0402_1%
<24> SATA_TXP1 SATA1TXP
0.01U_0402_16V7K Within 500 mils
ICH9-M ES_FCBGA676
B B

Add 12p on HDA_SDOUT and HDA_SDOUT

02/13 Reserve cap on HDA_BITCLK for WWAN noise
issue
+1.5VS +1.5VS
HDA_SDOUT_MDC @ C311 1 2 12P_0402_50V8J
@ U8 +1.5VS HDA_BITCLK_CODEC C67 1 2 33P_0402_50V8K
HDA_SDOUT_CODEC @ C312 1 2 12P_0402_50V8J @ R260 2 1 10K_0402_5% 7 1 HDA_BITCLK
VDD CLKIN

1
HDA_BITCLK_MDC C239 1 2 33P_0402_50V8K
HDA_SDOUT_NB @ C66 1 2 12P_0402_50V8J @ C327 1 2 12P_0402_50V8J6 2 @ R263 1 2 @ R261
CLKOUT NC 10K_0402_5% 10K_0402_5% HDA_BITCLK_NB C242 1 33P_0402_50V8K
2
HDABITCLK 1 2 5 8 BATT1
@ R264 33_0402_5% SSON NC
2

4 3
GND SS
XOR CHAIN ENTRANCE STRAP:RSVD ASM3P623S00BF-08TR_TSSOP8
2

1
+3VS @C328
@C328 @ R262 @ CR2032 RTC BATTERY
10K_0402_5%
0.1U_0402_16V4Z +RTCVCC +3VL
@ R325 2
1

1 2 HDA_SDOUT_CODEC BATT1.1
1K_0402_5% D8
@ R326 R329 W=20mils 2
1 2 ICH_RSVD 03/18 Reserve SSC for EMI 1 2 1 R330 JBATT1
ICH_RSVD <22> W=20mils
1K_0402_5% ICH_RTCX1 3 1 2 1
0_0402_5% W=20mils W=20mils 1
2 2
R328 1 DAN202U_SC70 1K_0402_5% 3
ICH_RTCX2 HDA_BITCLK C438 GND
1 2 4
GND
1

10M_0402_5% @ 2.2U_0603_6.3V4Z ACES_85205-02001

A R327 2 CONN@ A
ICH_RSVD HDA_SDOUT_CODEC 1 1
C436 C437 10_0402_5% Place near ICH9
15P_0402_50V8J 15P_0402_50V8J
2

2 2
0 0
1
@
0 1 Y2 C439 Security Classification Compal Secret Data Compal Electronics, Inc.
1 4 10P_0402_25V8K 2007/08/28 2006/03/10 Title
2 Issued Date Deciphered Date
1 0 2 3 ICH9(2/4)_LAN,HD,IDE,LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
32.768KHZ_12.5P_MC-146 Custom Montevina Blade UMA LA4105P 1.0
1 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5
0821 Change C436 and C437 to 15PF
4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 21 of 45
 5 4 3 2 1

WWW.AliSaler.Com
04/29 MV-1 add R337 clock REQ pull high
+3VS +3VALW R331 1
R332 1
2 2.2K_0402_5%
2 2.2K_0402_5%

ICH_SMBCLK
U12C
GPIO21
11/09 Change Gsensor control from SB
Place closely
pin AF3
CLK_48M_ICH
Place closely
pin H1
CLK_14M_ICH
<17,26> ICH_SMBCLK G16 SMBCLK SATA0GP/GPIO21 AH23
SIRQ ICH_SMBDATA HDDHALT_LED#
R333
1 2
10K_0402_5%
<17,26> ICH_SMBDATA LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19 AF19
AE21 GPIO36 HDDHALT_LED# <33>

SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

1
1 2 PM_CLKRUN# ME_EC_CLK1 C17 AD20 GPIO37
R334 8.2K_0402_5% ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37 @ R342 @ R343
B18 SMLINK1
1 2 OCP# H1 CLK_14M_ICH
+3VS ICH_RI# CLK14 CLK_48M_ICH CLK_14M_ICH <17>
R335 10K_0402_5% F19 clocks AF3 10_0402_5% 10_0402_5%
THERM_SCI# RI# CLK48 CLK_48M_ICH <17>
1 2

2
@ R336 8.2K_0402_5% PAD T57 SUS_STAT# R4 P1 ICH_SUSCLK T58 PAD
CLKREQ#_C XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
1 2 <6> XDP_DBRESET# G19
SYS_RESET# 1 1

1
R337 10K_0402_5% C16 SLP_S3# @ C440 @ C441
D PM_BMBUSY# PM_BMBUSY# SLP_S3# SLP_S4# SLP_S3# <32> D
1 2 @ R339
@R339 @ R340 M6 E16
<9> PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S5# SLP_S4# <32,36>
@R338
@ R338 8.2K_0402_5% 10K_0402_5% 10K_0402_5% G17 4.7P_0402_50V8C 4.7P_0402_50V8C
SLP_S5# <32>

SYS / GPIO
EC_SCI# EC_LID_OUT# SLP_S5# 2 2
1 2 <32> EC_LID_OUT# A17
SMBALERT#/GPIO11
R341 8.2K_0402_5% C10 S4_STATE#

2
CR_CPPE# H_STP_PCI# S4_STATE#/GPIO26
1 2 <17> H_STP_PCI# A14
STP_PCI#
R344 8.2K_0402_5% R345 1 2 0_0402_5% R_STP_CPU# E19 G20 PM_PWROK R346 10K_0402_5%
CR_WAKE# <17> H_STP_CPU# STP_CPU# PWROK PM_PWROK <9,32>
1 2 1 2
R356 8.2K_0402_5% PM_CLKRUN# L4 M2 R348 1 2 0_0402_5% DPRSLPVR <9,43>

Power MGT
GPIO18 CLKRUN# DPRSLPVR/GPIO16
1 2
R349 8.2K_0402_5% ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
HDDHALT_LED# <25,26> ICH_PCIE_WAKE# SIRQ WAKE# BATLOW#
1 2 <32> SIRQ M5
SERIRQ
R350 8.2K_0402_5% THERM_SCI# AJ23 R3 PWRBTN_OUT# 11/17 Add +3VALW GD to
GPIO20 <32> THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# <32>
1 2
R351 8.2K_0402_5%
<17,43> VGATE
VGATE D21 D20 R_EC_RSMRST# <39>
EC_RSMRST# to fix Battery mode
GPIO21 VRMPWRGD LAN_RST#
1 2 can't boot issue
R352 8.2K_0402_5% R353 1 2 PAD T59 A20 D22 R_EC_RSMRST# R354 1 2 100_0402_5%
GPIO36 TP11 RSMRST# EC_RSMRST# <32>
1 2 100K_0402_5% R355 1 2 10K_0402_5%
R357 8.2K_0402_5% OCP# AG19 R5 CK_PWRGD
<6> OCP# GPIO1 CK_PWRGD CK_PWRGD <17>
1 2 GPIO37 CR_CPPE# AH21
<27> CR_CPPE# GPIO6
R358 8.2K_0402_5% <32> EC_SCI# R225 1 2 0_0402_5% EC_SCI#_SB AG21 R6 M_PWROK
GPIO39 EC_SMI# GPIO7 CLPWROK M_PWROK <9,32>
1 2 <32> EC_SMI# A21 GPIO8
R359 10K_0402_5% @ R226 1 2 0_0402_5% EC_SCI#_GPIO12 C12 B16 +3VS
GPIO48 GPIO12 SLP_M#
1 2 PAD T46 C21 GPIO13
@R361
@ R361 8.2K_0402_5% 17/14 AE18 F24 CL_CLK0 R360
GPIO17 CL_CLK0 CL_CLK0 <9>
1 2 GPIO57 GPIO18 K1 B19 1 2

GPIO
GPIO18 CL_CLK1

Controller Link

0.1U_0402_16V4Z
R362 8.2K_0402_5% GPIO20 AF8
<19> GPIO20 GPIO20

1
CR_WAKE# AJ22 F22 CL_DATA0 3.24K_0402_1%
<27> CR_WAKE# DIS/UMA SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <9>
A9 GPIO27 CL_DATA1 C19 1
PAD T47 D19 C442 R363
CLKREQ#_C GPIO28 CL_VREF0_ICH 453_0402_1%
<17> CLKREQ#_C L1 SATACLKREQ#/GPIO35 CL_VREF0 C25
+3VS 1 2 GPIO38 AE19 A19 CL_VREF1_ICH

2
GPIO49 R364 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1 2 NA lead free
1 2 AG22 SDATAOUT0/GPIO39
C @R365
@ R365 10K_0402_5% @R739
@ R739 1 2 GPIO48 AF21 F21 CL_RST# +3VALW C
<26> EXP_CPPE# SDATAOUT1/GPIO48 CL_RST0# CL_RST# <9>
0_0402_5% GPIO49 AH24 D18
GPIO57 GPIO49 CL_RST1# R367
A8 GPIO57/CLGPIO5
+3VS @ R366 1 2 1K_0402_5% A16 XMIT_OFF 1 2
SB_SPKR MEM_LED/GPIO24 GPIO10 XMIT_OFF <26>

0.1U_0402_16V4Z
<28> SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18
MCH_ICH_SYNC# AJ24 C11 GPIO14 3.24K_0402_1%

MISC
<9> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT

1
+3VALW ICH_RSVD B21 C20 LAN_WOL_EN
<21> ICH_RSVD TP3 WOL_EN/GPIO9 1
AH20 C443 R368
TP8 R370 453_0402_1%
AJ20
LINKALERT# TP9
1 2 R366 05/08 MV-1 Delete R739 AJ21
TP10 2 1 +3VALW 2
R369 10K_0402_5% Low

2
1 2 ICH_LOW_BAT# High -->No ICH9-M ES_FCBGA676 100K_0402_5%
R371 8.2K_0402_5% -->default
1 2 ICH_PCIE_WAKE# boot U12D
R372 1K_0402_5% PCIE_RXN1 N29 V27 DMI_RXN0
<26> PCIE_RXN1 PERN1 DMI0RXN DMI_RXN0 <9>
1 2 ICH_RI# PCIE_RXP1 N28 V26 DMI_RXP0
<26> PCIE_RXP1 PERP1 DMI0RXP DMI_RXP0 <9>
R374 10K_0402_5% TV Tuner <26> PCIE_TXN1 C445 1 2 0.1U_0402_16V4Z PCIE_C_TXN1 P27
PETN1 DMI0TXN
U29 DMI_TXN0 DMI_TXN0 <9>
1 2 XDP_DBRESET# C444 1 2 0.1U_0402_16V4Z PCIE_C_TXP1 P26 U28 DMI_TXP0 D22

Direct Media Interface

<26> PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 <9>
R375 10K_0402_5% 2MiniC@ PM_PWROK 2 1 R_EC_RSMRST#
1 2 S4_STATE# 2MiniC@ L29 Y27 DMI_RXN1
PERN2 DMI1RXN DMI_RXN1 <9>
R376 10K_0402_5% L28 Y26 DMI_RXP1 CH751H-40PT_SOD323-2
PERP2 DMI1RXP DMI_RXP1 <9>
1 2 ME_EC_CLK1 11/17 Swap PCIE LAN and New card M27 W29 DMI_TXN1
PETN2 DMI1TXN DMI_TXN1 <9>
R377 10K_0402_5% M26 W28 DMI_TXP1 DMI_TXP1 <9> #PV PWROK sequence issue
ME_EC_DATA1 PETP2 DMI1TXP
1 2
PCIE_RXN3

PCI - Express
R378 10K_0402_5% J29 AB27 DMI_RXN2
<26> PCIE_RXN3 PERN3 DMI2RXN DMI_RXN2 <9>
1 2 GPIO10 PCIE_RXP3 J28 AB26 DMI_RXP2
<26> PCIE_RXP3 PERP3 DMI2RXP DMI_RXP2 <9>
R379 10K_0402_5% WLAN <26> PCIE_TXN3 C448 1 2 0.1U_0402_16V4Z PCIE_C_TXN3 K27 AA29 DMI_TXN2
DMI_TXN2 <9>
EC_LID_OUT# PETN3 DMI2TXN
1 2 <26> PCIE_TXP3 C449 1 2 0.1U_0402_16V4Z PCIE_C_TXP3 K26 PETP3 DMI2TXP AA28 DMI_TXP2 DMI_TXP2 <9>
R373 10K_0402_5%
1 2 EC_SMI# GLAN_RXN G29 AD27 DMI_RXN3
<25> GLAN_RXN PERN4 DMI3RXN DMI_RXN3 <9>
R380 8.2K_0402_5% GLAN_RXP G28 AD26 DMI_RXP3
<25> GLAN_RXP PERP4 DMI3RXP DMI_RXP3 <9>
1 2 GPIO14 LAN <25> GLAN_TXN C452 1 2 0.1U_0402_16V4Z GLAN_TXN_C H27 AC29 DMI_TXN3 DMI_TXN3 <9>
B R381 8.2K_0402_5% C453 1 0.1U_0402_16V4Z GLAN_TXP_C H26 PETN4 DMI3TXN DMI_TXP3 B
<25> GLAN_TXP 2 PETP4 DMI3TXP AC28 DMI_TXP3 <9>
PCIE_RXN5 E29 T26 CLK_PCIE_ICH#
<27> PCIE_RXN5 PCIE_RXP5 PERN5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# <17>
<27> PCIE_RXP5 E28 T25 CLK_PCIE_ICH <17>
+3VS +3VS PERP5 DMI_CLKP
Board ID Card <27> PCIE_TXN5 C816 1 2 0.1U_0402_16V4Z PCIE_C_TXN5 F27
PETN5
<27> PCIE_TXP5 C817 1 2 0.1U_0402_16V4Z PCIE_C_TXP5 F26 AF29 R382 24.9_0402_1% Within 500 mils
Reader PETP5 DMI_ZCOMP DMI_IRCOMP
AF28 1 2 +1.5VS
DMI_IRCOMP
2

PCIE_RXN4 C29
<26> PCIE_RXN4 PCIE_RXP4 PERN6/GLAN_RXN USB20_N0
<26> PCIE_RXP4 C28 AC5 USB20_N0 <30>
PERP6/GLAN_RXP USBP0N
@ R745
@R745 @ R747 New Card <26> PCIE_TXN4 C450 1 2 0.1U_0402_16V4Z PCIE_C_TXN4 D27
PETN6/GLAN_TXN USBP0P
AC4 USB20_P0
USB20_P0 <30> USB-0 Right side
10K_0402_5% 10K_0402_5% <26> PCIE_TXP4 C451 1 2 0.1U_0402_16V4Z PCIE_C_TXP4 D26 AD3 USB20_N1
USB20_N1 <30>
NewC@ PETP6/GLAN_TXP USBP1N USB20_P1
AD2 USB-1 Right side
1

DIS/UMA 17/14 SPI_CLK_SB NewC@ USBP1P USB20_N2 USB20_P1 <30>

<31> SPI_CLK_SB @ R417 1 2 15_0402_5% D23 AC1
SPI_SB_CS# SPI_CLK USBP2N USB20_P2 USB20_N2 <30>
<31> SPI_SB_CS# D24
SPI_CS0# USBP2P
AC2 USB20_P2 <30> USB-2 Left side(with ESATA)
2

SPI_CS1#_R F23 AA5 USB20_N3

<20> SPI_CS1#_R SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 <34>
AA4 USB20_P3 USB-3 Dock
USBP3P USB20_P3 <34>
R746 R748 SPI_SI @ R416 1 2 15_0402_5% USB20_N4
10K_0402_5% 10K_0402_5%
<31> SPI_SI
SPI_SO_R
D25 SPI_MOSI SPI USBP4N AB2
USB20_P4 USB20_N4 <19>
<31> SPI_SO_R E23
SPI_MISO USBP4P
AB3
USB20_N5 USB20_P4 <19> USB-4 Camera
AA1
1

USB_OC#0 USBP5N USB20_P5 USB20_N5 <26>

11/20 Add HDCP ROM for USB_OC#1
N4
OC0#/GPIO59 USBP5P
AA2
USB20_N6 USB20_P5 <26> USB-5 WLAN
R383 1 2 0_0402_5% N5 W5
ICH9M <30> BT_OFF USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6 USB20_N6 <30>
RP27 WXMIT_OFF#
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3 USB20_N7 USB20_P6 <30> USB-6 Bluetooth
USB_OC#6 <26> WXMIT_OFF# USB_OC#4 OC3#/GPIO42 USBP7N USB20_P7 USB20_N7 <30>
USB_OC#1
4 5 +3VALW USB_OC#5
M1
OC4#/GPIO43 USBP7P
Y2
USB20_N8 USB20_P7 <30> USB-7 Finger Printer
3 6 N2
OC5#/GPIO29 USBP8N
W1 USB20_N8 <26>
USB_OC#2 2 7 USB_OC#6 M4 W2 USB20_P8 USB-8
OC6#/GPIO30 USBP8P USB20_P8 <26>
USB_OC#4 1 8 USB_OC#7 M3 V2 USB20_N9
USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9 USB20_N9 <26> MiniCard(WWAN/TV)
10K_1206_8P4R_5% USB_OC#9
N3 OC8#/GPIO44 USBP9P V3 USB20_P9 <26> USB-9 Express
N1 U5
USB_OC#10 OC9#/GPIO45 USBP10N card
P5 U4
RP28 USB_OC#11 OC10#/GPIO46 USBP10P
P3 U1
USB_OC#7 OC11#/GPIO47 USBP11N
4 5 USBP11P U2
A USB_OC#8 3 6 +3VS USBRBIAS AG2 A
USB_OC#9 USBRBIAS
2 7 AG1 USBRBIAS#
1

USB_OC#0 1 8 Within 500 mils

1 2 SPI_SB_CS# ICH9-M ES_FCBGA676
10K_1206_8P4R_5% @ R399 10K_0402_5% R384
22.6_0402_1%
RP29 1 2 SPI_SI
2

WXMIT_OFF# 4 5 @ R429 10K_0402_5%

USB_OC#5
USB_OC#10
3 6
Security Classification Compal Secret Data Compal Electronics, Inc.
2 7 1 2 SPI_SO_R Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
USB_OC#11 1 8 @ R430 10K_0402_5%
01/03 Change HDCP ROM to +3VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(3/4)_DMI,USB,GPIO,PCIE
10K_1206_8P4R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 22 of 45
 5 4 3 2 1

+RTCVCC

WWW.AliSaler.Com
+VCCP U12E
U12F AA26 H5
VSS[001] VSS[107]
20 mils A23 G3: 6uA A15 AA27 J23
VCCRTC VCC1_05[01] VSS[002] VSS[108]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1634mA B15 AA3 J26
ICH_V5REF_RUN VCC1_05[02] VSS[003] VSS[109]
1 1 A6 2mA C15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
V5REF VCC1_05[03] VSS[004] VSS[110]

C462

C454
VCC1_05[04] D15 1 1 AB1 VSS[005] VSS[111] AC22
E15 C457 C455 AA23 K28
ICH_V5REF_SUS VCC1_05[05] VSS[006] VSS[112]
AE1 2mA F15 AB28 K29
2 2 V5REF_SUS VCC1_05[06] VSS[007] VSS[113]
VCC1_05[07] L11 AB29 VSS[008] VSS[114] L13
646mA 2 2
AA24 VCC1_5_B[01] VCC1_05[08] L12 AB4 VSS[009] VSS[115] L15
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB5 VSS[010] VSS[116] L2
AB24 L16 AC17 L26
VCC1_5_B[03] VCC1_05[10] VSS[011] VSS[117]
AB25 L17 AC26 L27
R387 VCC1_5_B[04] VCC1_05[11] VSS[012] VSS[118]
AC24 L18 AC27 L5
10U_0805_10V4Z VCC1_5_B[05] VCC1_05[12] R385 VSS[013] VSS[119]
+1.5VS 1 2 40 mils AC25
VCC1_5_B[06] VCC1_05[13]
M11 AC3
VSS[014] VSS[120]
L7
D CHB1608U301_0603 0.01U_0402_16V7K D
1 AD24 M18 1 2 +1.5VS AD1 M12
VCC1_5_B[07] VCC1_05[14] CHB1608U301_0603 VSS[015] VSS[121]
AD25 P11 AD10 M13

CORE
1 1 1 VCC1_5_B[08] VCC1_05[15] VSS[016] VSS[122]

220U_D2_4VM
+ C459 C460 C456 AE25 P18 AD12 M14
VCC1_5_B[09] VCC1_05[16] 1 1 VSS[017] VSS[123]

C458
AE26 T11 C461 C463 AD13 M15
VCC1_5_B[10] VCC1_05[17] VSS[018] VSS[124]
AE27 T18 AD14 M16
2 2 2 2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[019] VSS[125]
AE28 U11 AD17 M17
VCC1_5_B[12] VCC1_05[19] 2 2 VSS[020] VSS[126]
AE29 U18 AD18 M23
+5VS +3VS 10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[20] VSS[021] VSS[127]
F25 V11 AD21 M28
VCC1_5_B[14] VCC1_05[21] VSS[022] VSS[128]
G25 VCC1_5_B[15] VCC1_05[22] V12 AD28 VSS[023] VSS[129] M29
H24 V14 AD29 N11
VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[130]
1

H25 V16 AD4 N12

R386 D9 VCC1_5_B[17] VCC1_05[24] VSS[025] VSS[131]
J24 VCC1_5_B[18] VCC1_05[25] V17 +VCCP AD5 VSS[026] VSS[132] N13

VCCA3GP

22U_0805_6.3VAM
J25 VCC1_5_B[19] VCC1_05[26] V18 AD6 VSS[027] VSS[133] N14
100_0402_5% CH751H-40_SC76 K24 1 AD7 N15
VCC1_5_B[20] C464 VSS[028] VSS[134]
K25 AD9 N16
2

VCC1_5_B[21] VSS[029] VSS[135]

L23 VCC1_5_B[22] AE12 VSS[030] VSS[136] N17
ICH_V5REF_RUN L24 R29 AE13 N18
VCC1_5_B[23] VCCDMIPLL 2 VSS[031] VSS[137]
1 20 mils L25 VCC1_5_B[24] AE14 VSS[032] VSS[138] N26
C465 M24 W23 AE16 N27
VCC1_5_B[25] 23mA VCC_DMI[1] +VCCP VSS[033] VSS[139]
M25 VCC1_5_B[26] VCC_DMI[2] Y23 AE17 VSS[034] VSS[140] P12
0.1U_0402_10V6K N23 AE2 P13
2 VCC1_5_B[27] VSS[035] VSS[141]
N24 VCC1_5_B[28] V_CPU_IO[1] AB23 AE20 VSS[036] VSS[142] P14
N25 48mA AC23 AE24 P15
VCC1_5_B[29] V_CPU_IO[2] VSS[037] VSS[143]

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P24 VCC1_5_B[30] AE3 VSS[038] VSS[144] P16
P25 AG29 +3VS AE4 P17
VCC1_5_B[31] VCC3_3[01] 1 1 1 VSS[039] VSS[145]
+5VALW +3VALW

C466

C467

C468
R24 2mA AJ6 AE6 P2
VCC1_5_B[32] VCC3_3[02] VSS[040] VSS[146]
R25 VCC1_5_B[33] VCC3_3[07] AC10 AE9 VSS[041] VSS[147] P23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R26 VCC1_5_B[34] AF13 VSS[042] VSS[148] P28
1

2 2 2
R27 VCC1_5_B[35] VCC3_3[03] AD19 1 1 1 AF16 VSS[043] VSS[149] P29

VCCP_CORE
R388 D10 T24 AF20 AF18 P4
VCC1_5_B[36] VCC3_3[04] VSS[044] VSS[150]

C469

C470

C471
T27 VCC1_5_B[37] VCC3_3[05] AG24 AF22 VSS[045] VSS[151] P7
10_0402_5% CH751H-40_SC76 T28 AC20 AH26 R11
C VCC1_5_B[38] VCC3_3[06] +3VS 2 2 2 (DMI) VSS[046] VSS[152] C
T29 AF26 R12
2

VCC1_5_B[39] VSS[047] VSS[153]

ICH_V5REF_SUS U24 VCC1_5_B[40]
308mA AF27 VSS[048] VSS[154] R13
20 mils U25 B9 0.1U_0402_16V4Z AF5 R14
VCC1_5_B[41] VCC3_3[08] +1.5VS VSS[049] VSS[155]
1 V24 VCC1_5_B[42] VCC3_3[09] F9 1 AF7 VSS[050] VSS[156] R15
C472 V25 G3 C473 AF9 R16
VCC1_5_B[43] VCC3_3[10] VSS[051] VSS[157]
U23 VCC1_5_B[44] VCC3_3[11] G6 AG13 VSS[052] VSS[158] R17

2
PCI
0.1U_0402_10V6K W24 J2 AG16 R18
2 VCC1_5_B[45] VCC3_3[12] 2 R212 @ VSS[053] VSS[159]
W25 J7 AG18 R28
VCC1_5_B[46] VCC3_3[13] VSS[054] VSS[160]
K23 K7 0_0402_5% AG20 T12
VCC1_5_B[47] VCC3_3[14] VSS[055] VSS[161]
Y24 AG23 T13
VCC1_5_B[48] VSS[056] VSS[162]
Y25 AG3 T14

1
VCC1_5_B[49] VSS[057] VSS[163]
47mA 11mA AJ4 0.1U_0402_16V4Z +1.5VS AG6 T15
VCCHDA R740 VSS[058] VSS[164]
1 AG9 T16
VSS[059] VSS[165]
R389 11mA AJ3 0.1U_0402_16V4Z 1 2 180_0402_1% +3VALW C474 AH12 T17
VCCSUSHDA VSS[060] VSS[166]
+1.5VS 1 2 AJ19 1 AH14 T23
VCCSATAPLL VSS[061] VSS[167]

1
1U_0603_10V4Z

CHB1608U301_0603 C475 AH17 B26

2 VSS[062] VSS[168]
10U_0805_10V4Z

AC8 R741 AH19 U12

VCCSUS1_05[1] T65 VSS[063] VSS[169]
1 1 +1.5VS AC16
VCC1_5_A[01] VCCSUS1_05[2]
F17
T66 2
150_0402_1% +1.5VALW AH2
VSS[064] VSS[170]
U13
C476

C477

AD15 AH22 U14

0316 change design VCC1_5_A[02] VSS[065] VSS[171]
1 AD16 AH25 U15

2
VCC1_5_A[03] VSS[066] VSS[172]
C478 AE15 AD8 VCCSUS1_5_ICH_1 AH28 U16
2 2 VCC1_5_A[04] VCCSUS1_5[1] T67 VSS[067] VSS[173]
ARX

AF15 AH5 U17

1U_0603_10V4Z VCC1_5_A[05] VCCSUS1_5_ICH_2 VSS[068] VSS[174]
AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 AH8 VSS[069] VSS[175] AD23
2 AH15 T68 +3VALW AJ12 U26
VCC1_5_A[07] VSS[070] VSS[176]
AJ15 AJ14 U27
VCC1_5_A[08] 0.1U_0402_16V4Z VSS[071] VSS[177]
A18 AJ17 U3
VCCSUS3_3[01] VSS[072] VSS[178]

0.1U_0402_16V4Z
AC11 212mA D16 1 1 AJ8 V1
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] VSS[073] VSS[179]

AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 B11 VSS[074] VSS[180] V13

C479

C480
AE11 E22 B14 V15
+1.5VS VCC1_5_A[11] VCCSUS3_3[04] VSS[075] VSS[181]
AF11 B17 V23
VCC1_5_A[12] 2 2 VSS[076] VSS[182]
ATX

1 AG10 B2 V28
C481 VCC1_5_A[13] VSS[077] VSS[183]
AG11 B20 V29
B VCC1_5_A[14] VSS[078] VSS[184] B
AH10 VCC1_5_A[15] B23 VSS[079] VSS[185] V4
1U_0603_10V4Z AJ10 AF1 B5 V5
2 VCC1_5_A[16] VCCSUS3_3[05] VSS[080] VSS[186]
B8 W26
VSS[081] VSS[187]
AC9 1342mA
VCC1_5_A[17]
C26
VSS[082] VSS[188]
W27
C27 W3
VSS[083] VSS[189]
AC18 E11 Y1
VCC1_5_A[18] VSS[084] VSS[190]
AC19 E14 Y28
VCC1_5_A[19] VSS[085] VSS[191]
T1 E18 Y29
VCCSUS3_3[06] VSS[086] VSS[192]
AC21 T2 E2 Y4
VCC1_5_A[20] VCCSUS3_3[07] VSS[087] VSS[193]
T3 E21 Y5
VCCSUS3_3[08] +3VALW VSS[088] VSS[194]
+1.5VS G10 T4 E24 AG28
VCC1_5_A[21] VCCSUS3_3[09] VSS[089] VSS[195]
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 E5 VSS[090] VSS[196] AH6
1 11mA 11mA VCCSUS3_3[11]
T6 E8
VSS[091] VSS[197]
AF2
C483 AC12 U6 F16 B25
VCCPUSB

+1.5VS VCC1_5_A[23] VCCSUS3_3[12] 1 VSS[092] VSS[198]

1 AC13 U7 C482 F28
0.1U_0402_16V4Z C484 VCC1_5_A[24] VCCSUS3_3[13] VSS[093]
AC14 V6 F29
2 VCC1_5_A[25] VCCSUS3_3[14] 4.7U_0603_6.3V6M VSS[094]
VCCSUS3_3[15] V7 G12 VSS[095]
0.1U_0402_16V4Z AJ5 W6 2 G14 A1
2 VCCUSBPLL VCCSUS3_3[16] VSS[096] VSS_NCTF[01]
W7 G18 A2
VCCSUS3_3[17] VSS[097] VSS_NCTF[02]
USB CORE

AA7 Y6 G21 A28

VCC1_5_A[26] VCCSUS3_3[18] VSS[098] VSS_NCTF[03]
AB6 Y7 G24 A29
VCC1_5_A[27] VCCSUS3_3[19] VSS[099] VSS_NCTF[04]
AB7 VCC1_5_A[28] VCCSUS3_3[20] T7 G26 VSS[100] VSS_NCTF[05] AH1
AC6 G27 AH29
VCC1_5_A[29] VSS[101] VSS_NCTF[06]
AC7 G8 AJ1
VCC1_5_A[30] VSS[102] VSS_NCTF[07]
H2 AJ2
T69 VCC_LAN1_05_INT_ICH_1 VSS[103] VSS_NCTF[08]
A10 H23 AJ28
T70 VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VCCCL1_05_ICH VSS[104] VSS_NCTF[09]
A11 G22 H28 AJ29
+3VS VCCLAN1_05[2] VCCCL1_05 T71 VSS[105] VSS_NCTF[10]
VCCCL1_5 G23 H29 VSS[106] VSS_NCTF[11] B1
A12 B29
VCCLAN3_3[1] 19/78/78mA 19/73/73mA VSS_NCTF[12]
B12
VCCLAN3_3[2]
0.1U_0402_16V4Z

1 23mA A24 +3VS 1 @

C485 R390 CHB1608U301_0603 VCCCL3_3[1] C486 ICH9-M ES_FCBGA676
VCCCL3_3[2] B24
GLAN POWER

A 1U_0603_10V4Z A
1 2 A27 VCCGLANPLL
+1.5VS R391 4.7U_0805_10V4Z 80mA
2 2
10U_0805_10V4Z

2.2U_0603_6.3V4Z

+1.5VS 1 2 D28 VCCGLAN1_5[1]

D29 VCCGLAN1_5[2]
1 1 CHB1608U301_0603 E26
C487 C488 VCCGLAN1_5[3]
1 E27 VCCGLAN1_5[4]
1mA
A26
2 2
0316 change design
C489
2
+3VS VCCGLAN3_3
ICH9-M ES_FCBGA676
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 23 of 45
 5 4 3 2 1

WWW.AliSaler.Com +3VS_ACL
Pleace near HDD CONN (JP3)
HDD Connector +5VS
ACCELEROMETER (ST)

10U_0805_6.3V6M
0.1U_0402_16V4Z
C713

C714
10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
JP3 1 1 1 1 1 1
+3VS +3VS_ACL +3VS_ACL_IO

C490
C491 C492 C493
1
GND SATA_TXP0 GS@ D23 GS@ R564
2 SATA_TXP0 <21>
A+ 2 2 2 2 2 2

GS@

GS@
3 SATA_TXN0 0_0603_5%
A- SATA_TXN0 <21>
4 0.01U_0402_16V7K 2 1 1 2
D GND SATA_RXN0 2 D
B-
5 1 C494 SATA_RXN0_C SATA_RXN0_C <21>
6 SATA_RXP0 2 1 C495 SATA_RXP0_C CH751H-40PT_SOD323-2
B+ SATA_RXP0_C <21>
7 0.01U_0402_16V7K
GND
Near CONN side.
8
V33 +3VS_HDD1
9
V33
V33
10 Pleace near HDD CONN
GND 11
12 +3VS_HDD1 CLK_SMBCLK
GND CLK_SMBCLK <15,16,17>
13 @ R392
GND GS@ 0011101b

14
V5 14 +3VS 1 2

1000P_0402_50V7K

1U_0603_10V4Z
0.1U_0402_16V4Z
V5 15
16
+5VS 0_0805_5% VDDIO absolute man U29
1 1 1

SCL / SPC
V5
GND 17 @ C496 @ C497 @ C498 rating is VDD+0.1
Reserved 18
GND 19
20 2 2 2 1 13 CLK_SMBDATA
V12 +3VS_ACL_IO Vdd_IO SDA / SDI / SDO CLK_SMBDATA <15,16,17>
V12 21
22 GS@ R568 2 12 R570 GS@
V12 0_0402_5% GND SDO 0_0402_5%
1 2 3 11 1 2
SUYIN_127072FR022G523_RV Reserved Reserved
CONN@ 4 10
GND GND
5 GND INT 2 9

+3VS_ACL 6 Vdd INT 1 8 ACCEL_INT <20>

C
CD-ROM Connector C

CS
LIS302DLTR_LGA14_3x5

7
+5VS 2 1
GS@ R569 10K_0402_5%
JP5
Placea caps. near ODD Must be placed in the center of the system.
13 CONN. 02/12 Change SM bus to VS
GND SATA_TXP4
12 SATA_TXP4 <21>
A+ SATA_TXN4
A-
11 SATA_TXN4 <21> 04/23 Change part number from SA00001U600 to SA00002B600

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
10 0.01U_0402_16V7K
GND SATA_RXN4
B- 9 2 1 C510 SATA_RXN4_C SATA_RXN4_C <21> 1 1 1 1
8 SATA_RXP4 2 1 C511 SATA_RXP4_C C512 C513 C514 C515
B+ SATA_RXP4_C <21>
7 0.01U_0402_16V7K PR@ PR@ PR@ PR@
GND
Near CONN side. 2 2 2 2
6 PR@
DP PR@
5
V5
V5
MD
4
3
+5VS ACCELEROMETER (Bosch)
GND 2
1
GND

SUYIN_127382FR013GX09ZR
CONN@

B B

U14 @
BMA150
Multi Bay ACCEL_INT 4
INT
VDDIO
VDD
9
2
+3VS_ACL_IO
+3VS_ACL

+3VS_ACL 1 2 G_CS# 5 3
+5VS @ R571 10K_0402_5% CSB GND
Placea caps. near Multi Bay CLK_SMBCLK 6 1
+5VS SCK RSVD
10
JP12 CONN. RSVD
7
SDO
2 1
VCC5 GND
150U_B_6.3VM_R40M

4 3 SATA_TXP1 CLK_SMBDATA 8 11
VCC5 TX+ SATA_TXN1 SATA_TXP1 <21> SDI RSVD
6 5 SATA_TXN1 <21> 12
VCC5 TX- RSVD
1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

8 7 1
VCC3 GND SATA_RXN1 C822 2 SATA_RXN1_C BMA150_LGA12
10
VCC3 RX-
9
SATA_RXP1 C823 2
1
SATA_RXP1_C SATA_RXN1_C <21> 1 1 1 1
+ 02/12 Correct SM bus
12 11 1 C297 C298 C299 C300 C330
VCC3 RX+ SATA_RXP1_C <21>
14 13 Multi@
GND GND Multi@ Multi@ Multi@ Multi@ Multi@ Multi@
16 15
GND GND 0.01U_0402_16V7K 2 2 2 2 2
18 17 0.01U_0402_16V7K
GND GND
TYCO_2023087-3
CONN@

A A
04/29 MV1 add C330 , avoid
multibay hot plug shut down

ZZZ2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
PCB-MB DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 24 of 45
 5 4 3 2 1

WWW.AliSaler.Com
LAN Conn.
JRJ45
Place Close to Chip R697 +3V_LAN 13
U44 300_0402_5% Yellow LED+
LAN_ACTIVITY# 2 1 LANLED_ACT# 14
Yellow LED-
<22> GLAN_RXP C240 2 1 0.1U_0402_16V7K PCIE_PTX_IRX_P2 20
HSOP LED3/EEDO
33 LAN_DO 1 SHLD1
16
34 LAN_DI 8
D LED2/EEDI/AUX PR4- D
<22> GLAN_RXN C241 2 1 0.1U_0402_16V7K PCIE_PTX_IRX_N2 21
HSON LED1/EESK
35 LAN_SK_LAN_LINK# C268
DETECT PIN1
9
32 LAN_CS 0.1U_0402_16V4Z 7
EECS 2 PR4+
<22> GLAN_TXP 15
HSIP LAN_ACTIVITY# RJ45_MIDI1-
38 6
LED0 PR2-
<22> GLAN_TXN 16
HSIN LAN_MDI0+
RTL8103EL MDIP0
2 02/25 EMI request 5
PR3-
17 3 LAN_MDI0-
<17> CLK_PCIE_LAN REFCLK_P MDIN0
18 5 LAN_MDI1+ 4
<17> CLK_PCIE_LAN# REFCLK_M MDIP1 PR3+
6 LAN_MDI1-
MDIN1 RJ45_MIDI1+
<17> CLKREQ#_9 25 8 3
CLKREQB NC PR2+
9
NC RJ45_MIDI0-
<9,20,26,27> PLT_RST# 27 PERSTB NC 11 2 PR1-
NC 12 DETCET PIN2 10
2 RJ45_MIDI0+ 1
R688 1 PR1+
2 2.49K_0402_1% 46 RSET NC 4 C269
SHLD1 15
0.1U_0402_16V4Z +3V_LAN 11
VCTRL12 Green LED+
<22,26> ICH_PCIE_WAKE# 26 LANWAKEB VCTRL12A 48
ISOLATEB 28 LAN_SK_LAN_LINK# 1 2 1 LANLED_LINK# 12
ISOLATEB Green LED-
VDDTX 19 +EVDD12
LAN_X1 41 30 +LAN_VDD12 R698 FOX_JM36113-P1122-7F
+3VS LAN_X2 CKXTAL1 DVDD12 300_0402_5% CONN@
42 CKXTAL2 DVDD12 36
13 LANLED_ACT#
DVDD12 LANGND
DVDD12 10
1

LANLED_LINK# 1 1
R215 39 C271 C272
1K_0402_1% NC

2
23 44 0.1U_0402_16V4Z 4.7U_0805_10V4Z
NC NC 2 2
24 45 +LAN_VDD12
2

ISOLATEB NC VCTRL12D D20

7 29 +3V_LAN @ PACDN042_SOT23~D
GND VDD33
14 GND VDD33 37
31

1
C GND C
R216 47 GND AVDD33 1 02/12 Reserve to
15K_0402_5% 40
22
NC
43
prevent ESD issue
GNDTX NC
as other project.
RTL8103EL-GR_LQFP48_7X7

10/29 update U46

LAN_MDI0+ 1 16 RJ45_MIDI0+
RD+ RX+ RJ45_MIDI0+ <34>
LAN_MDI0- 2 15 RJ45_MIDI0- R693
RD- RX- RJ45_MIDI0- <34>
C247 1 2 0.01U_0402_16V7K LAN_CT0 3 14 RJ45_CT0 75_0402_1%
CT CT
PJP4 4 13 C257 1 2 0.01U_0603_100V7-M RJ45_CT0_C 1 2
NC NC
1 2 5 NC NC 12 C258 1 2 0.01U_0603_100V7-M RJ45_CT1_C 1 2 RJ45_GND
+3VALW C248 1 2 0.01U_0402_16V7K LAN_CT1 6 11 RJ45_CT1
PAD-OPEN 4x4m LAN_MDI1+ CT CT RJ45_MIDI1+ R694
7 10 RJ45_MIDI1+ <34> 1
LAN_MDI1- TD+ TX+ RJ45_MIDI1- 75_0402_1% C259
8 9 RJ45_MIDI1- <34>
TD- TX-
40 mils
S

1000P_1206_2KV7K
D

3 1 +3V_LAN
LEF8423A-R 2
2
@
G
2

C255 Q19
SI2301BDS-T1-E3_SOT23-3
1
<32> LAN_POWER_OFF 1 2
R218 10K_0402_5% 0.1U_0402_16V4Z

1 2 +3V_LAN
R695 3.6K_0402_5%
B B

U45 @
LAN_DO 4 5 2
LAN_DI DO GND C256
3 6
+LAN_VDD12 +3V_LAN LAN_SK_LAN_LINK# DI NC
Close to Pin10,13,30,36 Close to Pin1,37,29 2
SK NC
7 0.1U_0402_16V4Z
LAN_CS 1 8 +3V_LAN
CS VCC 1
AT93C46-10SI-2.7_SO8
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C Delete
2 2 2 2 2 2 2 2 1
C249 C250 C251 C252 C253 C254 C261 R696 10K_0402_5%

1 1 1 1 1 1 1

Y3
Close to Pin19 Close to Pin45 Close to Pin48 LAN_X1 2 1 LAN_X2

+EVDD12 +LAN_VDD12 25MHz_20pF_6X25000017

VCTRL12
10/09 update
1 1
C244 C245 Change the PCB Footprint from
10U_0805_10V4Z

0.1U_0402_16V4Z

Y_KDS_1BX25000CK1A_2P to
10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0402_6.3V4Z

@ 1 2 27P_0402_50V8J
@ 1 C262 C263 2 27P_0402_50V8J 2
C266
2
C267
2
C264
2
C265
Y_6X25000017_2P
A 2 1 A
1 1 1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2007/06/30 Title
RTL8103EL LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 25 of 45
 A B C D E

WWW.AliSaler.Com
Mini Card 0--TV SIM card Connector Mini Card
tuner/WWAN/Robson +3VALW +3VS_WWAN
2---WLAN +3VS_WLAN +3VALW +1.5VS_WLAN

0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z

0.1U_0402_16V4Z
0.01U_0402_16V7K 4.7U_0805_10V4Z JP4 1
1 1 1 C568 1 1 1 +1.5VS R431 1 2 0_0805_5% +1.5VS_WLAN
UIM_PWR 1 C566 C567 C569 C570 C571
2
2
0.1U_0402_16V4Z
1 1 1 1 UIM_DATA 3
C572 C573 C574 C575 UIM_CLK 3 2
4
2MiniC@ 2MiniC@ 2MiniC@ 2MiniC@ UIM_RST 4 2 2 2 2 2 R432 1 0_0805_5%
5 +3VS 2 +3VS_WLAN
1 UIM_VPP 5 4.7U_0805_10V4Z 1
6 8
2 2 2 2 6 G1 0.1U_0402_16V4Z
7 9
7 G2
0.1U_0402_16V4Z ACES_88266-07001
+3VS_WWAN CONN@ 02/13 Change WLAN and WWAN 0402 resistor to
JP6 0805, and WLAN change to +3VS power plane
ICH_PCIE_WAKE# 1 2 JP7
CH_DATA 1 2 ICH_PCIE_WAKE#
3 3 4 4 1 1 2 2 +3VS_WLAN
CH_CLK 5 6 CH_DATA 3 4
5 6 +1.5VS_WLAN <30> CH_DATA 3 4
<17> CLKREQ#_10 CLKREQ#_10 7 8 UIM_PWR CH_CLK 5 6 +1.5VS_WLAN
7 8 UIM_DATA_R <30> CH_CLK CLKREQ#_6 5 6
9 10 <17> CLKREQ#_6 7 8 R699 1 2 0_0402_5% DEBUG@
9 10 UIM_CLK 7 8 LPC_FRAME# <21,32>
11 12 9 10 R700 1 2 0_0402_5% DEBUG@
<17> CLK_PCIE_MCARD0# 11 12 UIM_RST CLK_PCIE_MCARD2# 9 10 LPC_AD3 <21,32>
13 14 11 12 R701 1 2 0_0402_5% DEBUG@
<17> CLK_PCIE_MCARD0 13 14 UIM_VPP <17> CLK_PCIE_MCARD2# CLK_PCIE_MCARD2 11 12 LPC_AD2 <21,32>
15 16 13 14 R702 1 2 0_0402_5% DEBUG@
15 16 <17> CLK_PCIE_MCARD2 13 14 LPC_AD1 <21,32>
17 18 15 16 R703 1 2 0_0402_5% DEBUG@
17 18 M_WXMIT_OFF# PLT_RST# 15 16 LPC_AD0 <21,32>
2MiniC@ 19 20 17 18
2MiniC@ 0_0402_5% 19 20 PLT_RST# 17 18 XMIT_OFF#
21 21 22 22 <17> CLK_DEBUG_PORT_1 19 19 20 20
<22> PCIE_RXN1 R419 1 2 PCIE_C_RXN1 23 23 24 24 @R420
@ R420 1 2 0_0805_5% +3VALW 21 21 22 22 PLT_RST#
<22> PCIE_RXP1 1 2 PCIE_C_RXP1 25 25 26 26 R422 1 2 0_0805_5% +3VS_WWAN <22> PCIE_RXN3 R423 1 2 0_0402_5% PCIE_C_RXN3 23 23 24 24 @R424
@ R424 1 2 0_0805_5% +3VALW
R421 0_0402_5% 27 28 2MiniC@ +1.5VS_WLAN <22> PCIE_RXP3 R425 1 2 0_0402_5% PCIE_C_RXP3 25 26 R426 1 2 0_0805_5% +3VS_WLAN
27 28 ICH_SMBCLK 25 26
29 29 30 30 27 27 28 28 +1.5VS_WLAN
PCIE_TXN1 31 32 ICH_SMBDATA 29 30 ICH_SMBCLK
<22> PCIE_TXN1 PCIE_TXP1 31 32 PCIE_TXN3 29 30 ICH_SMBDATA
33 33 34 34 <22> PCIE_TXN3 31 31 32 32
<22> PCIE_TXP1 PCIE_TXP3
35 35 36 36 USB20_N8 <22> 33 33 34 34
R427 0_0603_5% <22> PCIE_TXP3
37 37 38 38 USB20_P8 <22> 35 35 36 36 USB20_N5 <22>
+3VS_WWAN 1 2 39 39 40 40 37 37 38 38 USB20_P5 <22>
1 2 41 41 42 42 WW_LED# <33> 39 39 40 40
R428 0_0603_5% 43 44 +3VS_WLAN 41 42
2MiniC@ 43 44 41 42
45 45 46 46 43 43 44 44 WL_LED# <33>
2MiniC@ R1129 47 48 +1.5VS_WLAN 45 46
47 48 45 46
<32> UTX 1 2 49 49 50 50 47 47 48 48 +1.5VS_WLAN
2 33_0402_1% 2
51 51 52 52 +3VS_WWAN 49 49 50 50
04/29 MV-1 add clock REQ pull high 20090616 Gobi2 solution 51 51 52 52 +3VS_WLAN
53 GND1 GND2 54
R10 R750 53 54
CLKREQ#_10 22_0402_5% GND1 GND2 +3VALW
+3VS 1 2
FOX_AS0B226-S40N-7F UIM_DATA_R 1 2 UIM_DATA
CONN@ FOX_AS0B226-S40N-7F
10K_0402_5% CONN@

1
+3VS_WWAN
0821 Change +3VS to +3VS_WWAN
@
@ R400 @ R433 R434
0811 Pins 37 and 43 connect to GND and remove 1 2 10K_0402_5% 100K_0402_5%
0_0603_5% 2MiniC@
+1.5VS

2
D11 +3VS XMIT_OFF#
1 2 M_WXMIT_OFF# R418 UIM_CLK
<22> WXMIT_OFF#

1
D
S

D19 @
D

+3VALW 3 1 1 2 1
CH751H-40_SC76 0_1206_5% C824 @ 04/29 MV-1 add clock REQ pull high 1 2 2 Q10
<22> XMIT_OFF
2MiniC@ @ Q52 18P_0402_50V8J G 2N7002_SOT23-3
SI2301BDS_SOT23 R11 CH751H-40_SC76
G

S
2

3
2 1 2 CLKREQ#_6
<32> WWAN_POWER_OFF +3VS

01/03 Prevent WLAN leakage R435

10K_0402_5%
1 2
0_0402_5%

Near to Express Card slot.

Close to
3 New Card JEXP JEXP1
+3VS_PEC 3

Express Card Power NewC@ 1

+1.5VS R436 USB9- GND
Switch <22> USB20_N9 1 2 0_0402_5% 2 1 1
C576 NewC@ R437 USB9+ USB_D-
<22> USB20_P9 1 2 0_0402_5% 3
EXP_CPPE# USB_D+
1 2 0.1U_0402_16V4Z U16 NewC@ NewC@ 4 C577 C578
CPUSB# 0.1U_0402_16V4Z 4.7U_0805_10V4Z
12 11 +1.5VS_PEC 5
+3VS 1.5Vin 1.5Vout RSV NewC@ 2 2 NewC@
14 13 6
1.5Vin 1.5Vout ICH_SMBCLK RSV
<17,22> ICH_SMBCLK 7
NewC@ ICH_SMBDATA SMB_CLK
<17,22> ICH_SMBDATA 8
C579 1 SMB_DATA
2 0.1U_0402_16V4Z 2 3.3Vin 3.3Vout 3 +3VS_PEC +1.5VS_PEC 9 +1.5V
NewC@ 4 5 R438 10 +1.5VS_PEC
3.3Vin 3.3Vout +1.5VS_PEC PCIE_PME#_R +1.5V
C580 1 2 0.1U_0402_16V4Z <22,25> ICH_PCIE_WAKE# 1 2 11
0_0402_5% WAKE#
+3VALW 17 15 +3V_PEC 12
AUX_IN AUX_OUT NewC@ +3V_PEC PERST# +3.3VAUX
13 1 1
PLT_RST# PERST#
<9,20,25,27> PLT_RST# 6 SYSRST# OC# 19 +3VS_PEC 14 +3.3V
15 C581 C582
SYSON PERST# CLKREQ#_4 +3.3V 0.1U_0402_16V4Z 4.7U_0805_10V4Z
<9,32,33,36,41> SYSON 20 8 <17> CLKREQ#_4 16
SHDN# PERST# EXP_CPPE# CLKREQ# NewC@ 2 2 NewC@
17
SUSP# CPPE#
<28,32,36,38,40> SUSP# 1 16 <17> CLK_PCIE_NCARD# 18
STBY# NC REFCLK-
<17> CLK_PCIE_NCARD 19 REFCLK+
+3VALW @ R439 1 2 100K_0402_5% 10 7 20
CPPE# GND GND
<22> PCIE_RXN4 21
EXP_CPPE# PERn0
<22> EXP_CPPE# 9 <22> PCIE_RXP4 22
CPUSB# PERp0
23
GND +3V_PEC
18 <22> PCIE_TXN4 24
RCLKEN PETn0
<22> PCIE_TXP4 25 PETp0
05/08 MV-1 Delete R439 R5538D001-TR-F_QFN20_4X4~D 26
GND
04/29 MV-1 add clock REQ pull high
27 29
internal pull high to 3.3Vaux-in R12 28
GND GND
30 C583
1 1
C584
4 CLKREQ#_4 GND GND 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4
1 2
EC need setting at Hi-Z & output Low +3VS
SANTA_130801-5_LT NewC@ NewC@
CONN@ 2 2
10K_0402_5%
01/03 New card PTH connector
GND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN, WWAN, New Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

A B
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
E
Sheet 26 of 45
 5 4 3 2 1

WWW.AliSaler.Com 09/26 (JMicron)recommend C1328/1000pF close to U36 pin5

09/26 (JMicron)recommend place C1329/0.1uF near by C1328
+1.8VS_CR
09/26 (JMicron)recommend (APVDD, 20 mil width, less than 120mil long)
+3VS
1 1 1 1 11/07 Stuff for JMB385 internal LDO
R1042 1 2 4.7K_0402_5% XDCD0#_SDCD# C1326 C1329 +VCC_OUT +VCC_4IN1
R1041 1 2 4.7K_0402_5% XDCD1#_MSCD# 10U_0805_10V4Z 0.1U_0402_16V4Z R704
2 2 C1327 2 C1328 2 0_0603_5%
09/26 (JMicron)recommend
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2
D +VCC_4IN1 width/length: 12mil / +3VS D
<250mil for PREXT signal 1

1
+3VS C1325
R1044 2 1 10K_0402_5% XDWP#_SDWP# (pin 7) C1324 0.1U_0805_50V7M
R1043 2 1 10K_0402_5% XD_RB# U36 1 10U_0805_10V4Z

2
2
1 1
3 5 C1336
<17> CLK_SRC11# APCLKN APVDD
11/07 Change to 10K(vender) 4 10 0.1U_0402_16V4Z C1334 C1335
+3VS <17> CLK_SRC11 APCLKP APV18 2
30 0.1U_0402_16V4Z 0.1U_0402_16V4Z
TAV33 2 2
<22> PCIE_TXN5 9 APRXN
R709 1 2 10K_0603_5% XD_CLE <22> PCIE_TXP5 8 APRXP DV33 19
20
Use 0603 type and over 20
+3VS DV33 +1.8VS_CR
<22> PCIE_RXN5
C1321 2
C1322 2
1 0.1U_0402_16V4Z PCIE_C_RXN5 11 APTXN DV33 44 mils trace width on both side
<22> PCIE_RXP5 1 0.1U_0402_16V4Z PCIE_C_RXP5 12 APTXP DV18 18
@ 37 09/26 (JMicron)recommend change to 0805 Size
R1048 1 DV18
2 10K_0603_5% XD_ALE 11/07 Change to 8.2K(vender) R402 1 2 8.2K_0402_5% PREXT 7 APREXT 1 1
48 XD_SD_MS_D0 09/26 (JMicron)recommend +VCC_OUT >30mil
R248 1 MDIO0
2 10K_0603_5% XD_ALE
MDIO1 47 XD_SD_MS_D1 C1332 C1333
+3VS R972 1 2 10K_0402_5% XIN 38 46 XD_SD_MS_D2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCIES_EN MDIO2 XD_SD_MS_D3 2 2
01/03 Change Cardreader LED control 39 PCIES JMB385 MDIO3
MDIO4
45
43 SDCMD_MSBS_XDWE#
02/13 XD_ALE Change to LED low active 09/26 (JMicron)recommend add a 42 SDCLK_MSCLK_XDCE#
MDIO5 XDWP#_SDWP#
41
XD_RE# R1046 1 2 200K_0402_5% 、14
test point for pin 13、 MDIO6
40 XD_CLE
MDIO7 XD_D4 +VCC_OUT +VCC_4IN1
MDIO8 29
1 28 XD_D5
<9,20,25,26> PLT_RST# XRSTN MDIO9 XD_D6
2 XTEST MDIO10 27
26 XD_D7 40mil
XDCE# MDIO11 XD_RE# +3VS @ U37
2 1 2 1 MDIO12 25
@ R706 @ C788 <22> CR_CPPE# @ R404 1 2 0_0402_5% 13 23 XD_RB#
100_0402_5% 100P_0402_25V8K T78 SEEDAT MDIO13 XD_ALE
14 SEECLK MDIO14 22 3 IN OUT 1
4 EN OUT 5
C SDCLK 1 2 1 2 34 C
NC 1

1
@ R707 @ C789 D18 XDCD1#_MSCD# 15 35 2 1
100_0402_5% 100P_0402_25V8K XDCD0#_SDCD# CR1_CD1N NC C1330 GND
<22> CR_WAKE# 1 2 16 CR1_CD0N NC 36
CH751H-40PT_SOD323-2 0.1U_0402_16V4Z G5250C2T1U_SOT23-5
MSCLK 2 @ R1050
1 2 1 2 APGND 6
@ R708 @ C790 11/09 Reserve D18 for cardreader wake up +VCC_OUT 17 C1331 2 150K_0402_5%

2
100_0402_5% 100P_0402_25V8K CR1_PCTLN 1U_0603_10V4Z
use for PWR_EN# GND 24
02/13 Add D18 CR_LED# GND 31
21 CR1_LEDN GND 32
8mA sink current GND 33
SDCLK_MSCLK_XDCE# R710 1 2 22_0402_5% SDCLK reserved power circuit
R711 1 2 22_0402_5% MSCLK
R712 1 2 22_0402_5% XDCE#
JMB385-LGEZ0A_LQFP48_7X7 11/07 Change U37 correct PCBFootprint SOT23
D41
11/07 BOM delete for JMB385 internal LDO
XDCD1#_MSCD# 2
1 1 XD_CD#
XDCD0#_SDCD# 3
C1047
DAN202U_SC70 270P_0402_50V7K
2

Card Reader Connector

JREAD1 delete +1.8VS_CR R
+VCC_4IN1 3 XD-VCC SD-VCC 21 +VCC_4IN1
B White LED: VF=3V, IF = 5mA, Res = 56ohm XD_SD_MS_D0 32
MS-VCC 28
B
XD_SD_MS_D1 XD-D0 SDCLK
10 XD-D1 7 IN 1 CONN SD_CLK 20
11/09 don't support DIM function XD_SD_MS_D2 9 14 XD_SD_MS_D0
+5VS XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
8 XD-D3 SD-DAT1 12
XD_D4 7 30 XD_SD_MS_D2
XD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
6 XD-D5 SD-DAT3 29
1

XD_D6 5 27 XD_D4
R719 XD_D7 XD-D6 SD-DAT4 XD_D5
4 XD-D7 SD-DAT5 23
470_0402_5% 18 XD_D6
SDCMD_MSBS_XDWE# SD-DAT6 XD_D7
34 XD-WE SD-DAT7 16
XDWP#_SDWP# 33 25 SDCMD_MSBS_XDWE#
2

XD_ALE XD-WP SD-CMD XDCD0#_SDCD#

35 XD-ALE SD-CD-SW 1
XD_CD# 40 XD-CD
2

XD_RB# 39 2 XDWP#_SDWP#
D15 White XD_RE# XD-R/B SD-WP-SW
38 XD-RE
HT-F196BP5_WHITE XDCE# 37
XD_CLE XD-CE MSCLK
36 XD-CLE MS-SCLK 26
17 XD_SD_MS_D0
R249 MS-DATA0 XD_SD_MS_D1
11 15
1

0_0402_5% 7IN1 GND MS-DATA1 XD_SD_MS_D2

31 7IN1 GND MS-DATA2 19
1 2 24 XD_SD_MS_D3
MS-DATA3 XDCD1#_MSCD#
MS-INS 22
13 SDCMD_MSBS_XDWE#
MS-BS
1

@ Q101 D
41 7IN1 GND
2N7002_SOT23-3 2 CR_LED# 42
G 7IN1 GND
2

S TAITW_R015-B10-LM
3

R194 @ CONN@
4.7K_0402_5%
11/17 Update CIS library
1

A A

01/03 Change Cardreader LED control

02/13 Direct driver LED
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB CardReader&CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, July 18, 2009 Sheet 27 of 45
5 4 3 2 1

WWW.AliSaler.Com
 A B C D E

WWW.AliSaler.Com CODEC POWER

(4.75V(4.56~4.94V))
+1.5VS_HDA +1.5VS 300mA
+3VDD_CODEC +VDDA_CODEC_R +5VALW +VDDA_CODEC
W=40Mil U39
R1051 R1052 R1053
1 2 +3VS 1 2 1 2 +VDDA_CODEC C1341 1 2 1
IN

2.2U_0805_16V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
BLM18BD601SN1D_0603 BLM18BD601SN1D_0603 0_0603_5% 0.1U_0402_16V4Z 5
OUT

0.1U_0402_16V4Z

1U_0603_10V4Z
1 1 1 1 2 1
GND

C1342
1

C1343
1 1
<26,32,36,38,40> SUSP# 3 SHDN BYP
4
2 2 2 2 2

C1337

C1338

C1339

C1340
G9191-475T1U_SOT23-5 1
2 C1344
11/07 Change to 4.75V
0.1U_0402_16V4Z
LDO 2

U38

9 47 EAPD_CODEC
+3VDD_CODEC DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 EAPD_CODEC <32>
1 DVDD_CORE VOL_UP/DMIC_0/GPIO 1 2 DMIC_DAT <19>

VOL_DN/DMIC_1/GPIO 2 4
+VDDA_CODEC_R 25 AVDD1*
GPIO 3 30
38 AVDD2**
VREFOUT-E / GPIO 4 31
HDA_BITCLK_CODEC
+1.5VS_HDA 3 DVDD_IO GPIO 5 43
1

@
R1054 32 44
47_0402_5% MONO_OUT GPIO 6
45 SPDIF_OUT
2 HDA_BITCLK_CODEC SPDIF OUT1 / GPIO 7 SPDIF_OUT <34> 2
6
2

<21> HDA_BITCLK_CODEC BITCLK

1
HDA_SDOUT_CODEC SPDIF OUT0 48 01/03 Change SPDIF to SPDIF1
@ 5
<21> HDA_SDOUT_CODEC SDO
C1345
33P_0402_50V8K
<21> HDA_SDIN0
R1055 1 2 HDA_SDIN0_CODEC 8
2 33_0402_5% SDI_CODEC VREFOUT_B
VREFOUT-B 28 VREFOUT_B <29>
HDA_SYNC_CODEC 10
<21> HDA_SYNC_CODEC SYNC +VDDA_CODEC_R
11/09 reserve HDA_RST#_CODEC VREFOUT-C
29
<21,32> HDA_RST#_CODEC 11
EC_BEEP @ R445
@R445 RESET# R1056 1 2 5.1K_0402_1%
47K_0402_5% R1057 1 2 20K_0402_1% EXTMIC_DET# <29>
EC_BEEP 1 2 13 SENSE R1059 1 2 39.2K_0402_1% JACK_DET# <29,34> 11/07 Change R1059
<32> EC_BEEP SENSE_A
R1058 1 2 22_0402_5% 46 R683 1 2 10K_0402_1% INTMIC_DET# <29>
<19> DMIC_CLK DMIC_CLK 39.2K
C1346 1 2 0.1U_0402_16V4Z
R1060 1 2 47K_0402_5% C1347 2 1 33 41 HP_OUTR
<22> SB_SPKR HP_OUTR <29>
1U_0603_10V4Z CAP2 PORTA_R
HP Jack & Dock
R1061 1 2 10K_0402_5% 1 2 MONO_INR 12 PCBEEP 39 HP_OUTL
PORTA_L HP_OUTL <29>
C1348 0.1U_0402_16V4Z
C1349 1 2 0.1U_0402_16V4Z
22 MIC_EXTR 1 2
PORTB_R MIC_EXT_R <29>
@ C1358 40 C1350 1U_0603_10V6K Jack MIC
R1062 1 NC / OTP MIC_EXTL
1 2 +VDDA_CODEC_R 2 5.1K_0402_1% 21 1 2 MIC_EXT_L <29>
0.1U_0402_16V4Z R1063 1 SENSEB# PORTB_L
<34> SENSE_B# 2 39.2K_0402_1% 34 SENSE_B / NC
C1351 1U_0603_10V6K 1 2 MIC_IN_R <29>
1 C1352 0.022U_0402_16V7K

1
@ C1359 37 24 MIC_INR
NC PORTC_R
1 2 C1353
MIC_INL
@ R1064
@R1064 11/08 Change C1352、 、 C1354
0.1U_0402_16V4Z 0.1U_0402_16V4Z 18 23 0_0603_5%
2 NC PORTC_L (recommend)
Internal MIC
@ C1360 19

2
NC LINE_OUT_R
1 2 PORTD_R
36 LINE_OUT_R <29> 1 2 MIC_IN_L <29>
0.1U_0402_16V4Z 20 C1354 0.022U_0402_16V7K
NC LINE_OUT_L
3 PORTD_L
35 LINE_OUT_L <29> Internal SPKR. 3
@ C1361 C1355
1 2 10U_0805_10V4Z
0.1U_0402_16V4Z 1 2 VC_REFA 27 15 DOCK_MICR 1 2 DOCK_MICR_C R733 1 2 10K_0402_5%
VREFFILT PORTE_R DOCK_MIC_R <34>
C1356 1U_0603_10V6K DOCK MIC
C1362 26 14 DOCK_MICL 1 2 DOCK_MICL_C R734 1 2 10K_0402_5%
AVSS1* PORTE_L DOCK_MIC_L <34>
1 2 C1357 1U_0603_10V6K
0_0402_5% 42
AVSS2**

1
17
R1065 PORTF_R R735 R736
7
DVSS** 1.21K_0402_1% 1.21K_0402_1%
1 2 PORTF_L
16
0_1206_5%
1/10*Vin

2
R596
1 2 92HD71B7X5NLGXA1X8_QFN48_7X7 need close to
GNDA <29,34>
0_1206_5% Codec

GND GNDA
11/07 Stuff 0 Ohm for AGND and
GND

SENSE A SENSE B

Port Resistor Port Resistor

4
A 39.2K E 39.2K 4

B 20K F 20K

C 10K G 10K Security Classification Compal Secret Data

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
Codec_IDT9271B7
D 5.11K H 5.11K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

A B
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
E
Sheet 28 of 45
 A B C D E

WWW.AliSaler.Com GAIN0 GAIN1 Av(inv)

SPEAKER
JP60
+5VAMP +5VS
0 0 6dB 6 GND2
5 GND1
R394 0 1 10dB SPKR- R1105 1 2 0_0603_5% 4 4
0.1U_0402_16V4Z 1 2 SPKR+ R1104 1 2 0_0603_5% 3
SPKL- R1103 1 0_0603_5% 3
2 2
2
1 1 1 0_1206_5% 1 0 15.6dB SPKL+ R1102 1 2 0_0603_5% 1
1

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
C282 C283 C284
+5VS ACES_88231-04001
1
1 1 1 1 1
10U_0805_10V4Z
2 2 2
1 1 21.6dB CONN@
15.6 dB

C1378

C1377

C1376

C1375
0.1U_0402_16V4Z 11/17 Change to15.6 dB

2
2 2 2 2

16
15
6

1
U40 11/07Change JP60 PCB
@ D55

PVDD1
PVDD2
VDD
@ R395 R396 PSOT24C_SOT23-3 Footprint from
100K_0402_5% 100K_0402_5% ACES_85204-04001_4P to

1
2

2
C285 1 2 0.022U_0603_25V7K 7 RIN+ GAIN0
2 8/31EMI request ACES_88231-04001_4P
1 2
C286 47P_0402_50V8J 3
GAIN1 D56 @

1
C287 1 2 0.022U_0603_25V7K17 PSOT24C_SOT23-3
<28> LINE_OUT_R RIN- SPKR+
1 2 ROUT+ 18
C288 47P_0402_50V8J R397 @ R398
100K_0402_5% 100K_0402_5%
14 SPKR-

2
C289 ROUT-
1 2 0.022U_0603_25V7K 9
1 2
LIN+ Audio/B & CIR

2N7002DW-7-F_SOT363-6
C290 47P_0402_50V8J 4 SPKL+
LOUT+ <28,34> JACK_DET#
C291 1 2 0.022U_0603_25V7K 5 B+ JP49
<28> LINE_OUT_L LIN- SPKL- +3VALW MIC_EXT_R
1 2 LOUT- 8 1 1

3
C292 47P_0402_50V8J MIC_EXT_L 2 2

1
Q16B 3 3

2
DOCK@ R678 04/29 MV-1 add 2 2N7002 for Docking issue HP_OUT_R 4
+3VALW R676 330K_0402_5% HP_OUT_L 4
5 5
10K_0402_5% DOCK@ 5
NC 12 6 6
DOCK@ <28> EXTMIC_DET# EXTMIC_DET# 7

2
7

2
THERMAL PAD
10 Keep 10 mil width HP_DET# 8

1
2 EC_MUTE# BYPASS R401 8 2
19 SHUTDOWN 9 9
<32> EC_MUTE# 10K_0402_5%
1 10 10

2N7002DW-7-F_SOT363-6
1 CIR_IN 11
<32,34> CIR_IN 11

6
GND1
GND2
GND3
GND4

C293 +5VL 12

1
1U_0805_25V6K Q16A Q46 C270 12
13 13

1
2 DOCK@ D 2N7002_SOT23-3 0.01U_0402_25V7K 14 14
HP_DET# 2 2 DOCK@ 2
DOCK@
20
13
11
1

21

G ACES_87213-1400G
TPA6017A2_TSSOP20 11/07 Add 10K S CONN@
HP OUT

3
12/18 Shut down pop noise PU Q17B Q14B

5
DOCK@ DOCK@ DOCK@
C295 R409
2 47_0402_5%

+
<28> HP_OUTR 3 4 4 3 1 2 1 DOCK_LOUT_R <34>
DOCK@
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 150U_B_6.3VM_R40M

R684
<28> VREFOUT_B 2 1 C787 1 2 Q17A Q14A HP OUT For Docking

2
0_0402_5% DOCK@ DOCK@ DOCK@
1U_0603_10V4Z C296 R410
1

2 47_0402_5%

+
<28> HP_OUTL 6 1 1 6 1 2 1 DOCK_LOUT_L <34>
R685 R686 DOCK@
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 150U_B_6.3VM_R40M
4.7K_0402_5% 4.7K_0402_5%
11/07 Add Capacitor avoid DC lever to Docking
2

audio
MIC_EXT_R C785 1 HP_OUT_R

+
<28> MIC_EXT_R 2
150U_B_6.3VM_R40M
<28> MIC_EXT_L MIC_EXT_L EXTMIC IN
3 3
HP OUT For M/B
OPP@
R192 C786 1 HP_OUT_L

+
2
JACK_DET# 1 2 HP_DET# 150U_B_6.3VM_R40M

0_0402_5%
+VDDA_CODEC
R1077 C1379
+VDDA_CODEC 1K_0402_5% 1U_0603_10V4Z INTMIC IN
MDC 1.5 Conn. 2 1 1 2

2
1

1
R951
+1.5VS R1078 R1079 10K_0402_5%
JP8 1 2 +1.5VS 4.7K_0402_5% 4.7K_0402_5%
R475 0_0603_5%

1
1 2 1 2 +3VS JP51

2
GND1 RES0
1000P_0402_50V7K
C619

C620

@C621
0.1U_0402_16V4Z

4.7U_0805_10V4Z

<21> HDA_SDOUT_MDC HDA_SDOUT_MDC 3 4 @ R476 0_0603_5% 1

IAC_SDATA_OUT RES1 1
5 6 +3VS 1 1 1 <28> MIC_IN_L 2
HDA_SYNC_MDC GND2 3.3V 2
<21> HDA_SYNC_MDC 7 IAC_SYNC GND3 8 <28> MIC_IN_R 3 3
<21> HDA_SDIN1 1 2 HDA_SDIN1_MDC 9 10 4
R477 33_0402_5% IAC_SDATA_IN GND4 4
<21> HDA_RST#_MDC 11 12 HDA_BITCLK_MDC <21> +3VS 2 1
IAC_RESET# IAC_BITCLK 2 2 2 R681 10K_0402_5% 5
GND1
2 1 1 2 <32> ANA_MIC_DET 6
@ R478 @C618
@ C618 GND2
GND
GND
GND
GND
GND
GND

2N7002DW-7-F_SOT363-6
10_0402_5% 10P_0402_25V8K <28> INTMIC_DET# ACES_88231-04001

3
2N7002DW-7-F_SOT363-6
H12 H14 Q18B CONN@

6
HOLEA HOLEA ACES_88018-124G Q18A
13
14
15
16
17
18

5
4 4
Connector for MDC Rev1.5 2
1

4
CONN@

1
MDC Standoff

Security Classification Compal Secret Data

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

A B
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
E
Sheet 29 of 45
 5 4 3 2 1

WWW.AliSaler.Com
Left side USB Power Switch Left side ESATA/USB combination Connector
+5VALW

USB_VCCC
U41 USB_VCCC
1
GND OUT
8 W=100mils JP53
2 7 1 USB
IN OUT VBUS

1000P_0402_50V7K
D D

150U_D_6.3VM

0.1U_0402_16V4Z
3 6 1 R1080 1 2 0_0402_5% USB20_N2_R 2
USB_EN# IN OUT <22> USB20_N2 R1081 1 USB20_P2_R D-
1 4
EN# OC#
5 1 1 2 0_0402_5% 3
D+
<22> USB20_P2

C1380

C1382

C1383
C1381 + 4
TPS2061IDGNR_MSOP8 GND
5
2 2 2 2 SATA_TXP5 GND
<21> SATA_TXP5 6
SATA_TXN5 A+ ESATA
<21> SATA_TXN5 7
A-
8
GND
4.7U_0805_10V4Z
<21> SATA_RXN5_C
C1385 2 1 0.01U_0402_16V7K SATA_RXN5 9 B-
<21> SATA_RXP5_C
C1384 2 1 0.01U_0402_16V7K SATA_RXP5 10
B+
ESATA@ 11
R1083 GND
1 2 10K_0402_5% +5VALW ESATA@
12 GND
13 GND
14 GND
15 GND
TYCO_1759576-1
CONN@
D45

+5VALW 4 2 USB20_N2
VIN IO1
USB20_P2 D46
3 IO2 GND 1
+5VALW 4 2 SATA_TXP5
@ PRTR5V0U2X_SOT143-4 VIN IO1
SATA_TXN5 3 1
IO2 GND
@ PRTR5V0U2X_SOT143-4

C C

Finger printer BT Connector Need change to New version

JP57
02/12 Change BT connector type
04/28 MV1 Change to +3VS
10 8 +3VAUX_BT
@ GND 8
7
R627 7 USB20_P6_R
1 2 0_0603_5% 6 6 R1084 2 1 0_0402_5% USB20_P6 <22>
5 USB20_N6_R R1085 2 1 0_0402_5%
+3VS 5 USB20_N6 <22>
20070209 Add for FPR 4
4 BT_LED <33>
R628 FP@ 3 @ R1086 1 2 1K_0402_5%
3 CH_DATA <26>
S

@ R1087 1 1K_0402_5%
D

+3VALW 3 1 1 2 2 2 CH_CLK <26>

0_0603_5% 2
1 9 1
GND 1
@ Q31 C756 FP@ 0612 no install
SI2301BDS_SOT23 0.1U_0402_16V4Z ACES_87213-0800G
G
2

USB_EN# D47
CONN@
2 JP24 USB20_P6_R
+5VALW 4 VIN IO1 2
1
R634 1 USB20_N7_R 1 USB20_N6_R
<22> USB20_N7 2 0_0402_5% 2 3 1
R635 1 USB20_P7_R 2 IO2 GND
<22> USB20_P7 2 0_0402_5% 3
3
FP@ 4 +3VS @ PRTR5V0U2X_SOT143-4
4
3

FP@ @ R405 5 R235

5
1 2 6 1 2
0_0402_5% 6
7
@D30
@ D30 GND +3VALW 0_0603_5% +3VAUX_BT
8
PACDN042_SOT23-3~D GND Q105 SI2301BDS_SOT23
B ACES_85201-06051 @ R236 B
1

0.1U_0402_16V4Z

S
CONN@

D
1 2 3 1

11/07 Change PCB Footprint 0_0603_5%

G
1 1 1 1

2
to ACES_85201-06051_6P C1387 C1388 C1389
C1386 @ R1090
1U_0603_10V4Z 100K_0402_5%
2 2 2 2

2
0.01U_0402_16V7K 4.7U_0805_10V4Z

C1390
R1092 1 2 10K_0402_5% 1 2
USB cable connector for Right side <22> BT_OFF
0.1U_0402_16V4Z

JP55
+5VALW 1
1
2
2 01/03 Change BT power to +3VS
3
USB_EN# 3
<32> USB_EN# 4 4 02/12 Change to 10K
5
<22> USB20_N0 5
6
<22> USB20_P0 6
7
7
8
<22> USB20_N1 8
9
<22> USB20_P1 9
10 10

11 GND1
A A
12 GND2
ACES_87213-1000G
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 30 of 45
 5 4 3 2 1

WWW.AliSaler.Com

D
SPI ROM D

+3VL
U27
20mils 8 4
VCC VSS
1
C712 3
0.1U_0402_16V4Z W
7 HOLD
2
1 2 SPI_FSEL# 1
<32> FSEL# S
R553 10_0402_5%
1 2 SPI_CLK_R 6
<32> SPI_CLK C
R554 10_0402_5%
<32> FWR# 1 2 SPI_FWR# 5 2 SPI_SO 1 2 FRD# FRD# <32>
R556 10_0402_5% D Q R555 0_0402_5%
WIESON G6179 8P SPI

SP07000F500 S SOCKET WIESON G6179-100000 8P

SPIFLASH
R230 C307
SPI_FSEL# 2 1 2 1 WIESO_G6179-100000_8P

33_0402_5% 22P_0402_50V8J

R231 C308
SPI_CLK_R 2 1 2 1

33_0402_5% 22P_0402_50V8J
+3VL +3VL
R232 C309
SPI_FWR# 2 1 2 1

1
C C
1
33_0402_5% 22P_0402_50V8J @ C711
R552 @
0.1U_0402_16V4Z 100K_0402_5%
2 U28 @
12/27EMI
Remove LPC Debug Port

2
request
8 VCC A0 1 11/16 Change TO
7 WP A1 2
<32,33,37> SMB_EC_CK1 6 3 +3VALW
02/18 Change TO
<32,33,37> SMB_EC_DA1 5
SCL
SDA
AT24C16AN-10SI-2.7_SO8
A2
GND
4
+3VL
02/18 Delete KBC EEPROM 20090618

1 R557 @
100K_0402_5%
2

HDCP ROM
+3VS

+3VS

1
B @ R411 1 2 SPI_WP# +3VS @ C304 B
3.3K_0402_5% 0.1U_0402_16V4Z
2
@ R412 1 2 SPI_HOLD# U6 @
2

3.3K_0402_5% 8 4
@ R413 VCC VSS
1K_0402_5% SPI_WP# 3
W
SPI_HOLD# 7
1

@ R414 HOLD
SPI_SB_CS# 1 2 1
<22> SPI_SB_CS# S
SPI_CLK_SB 15_0402_5% 6
<22> SPI_CLK_SB C @ R415
SPI_SI 5 2 SPI_SO_L 1 2 SPI_SO_R
<22> SPI_SI D Q SPI_SO_R <22>
SST25LF080A_SO8-200mil 15_0402_5%

11/17 Add SB HDCP

ROM Change HDCP ROM to +3VS
01/03
02/13 Sparate SPI_CLK between SB and
EC

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 31 of 45
 WWW.AliSaler.Com
C301
+3VL_EC +1.5VS
BATT_OVP 2 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K +3VS
1 1 1 1 1 100P_0402_50V8J

1
C715 C716 C717 C718 C719 +3VL +3VL_EC +EC_AVCC R250 11/09 EC recommend
56_0402_5% R251
2 2 2 2 2 R572 10K_0402_5%
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2

2 2
04/22 MV1 Change SMbus1 power to +3VL 0_0805_5%

2
B
For EMI

111
125

E
+3VL +3VS HDA_RST#_EC

22
33
96

67
<21,28> HDA_RST#_CODEC 3 1

C
U30 KSO15 @C792
@ C792 1 2 100P_0402_50V8J
SMB_EC_DA1 R573 1 2 4.7K_0402_5% Q21

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R577 1 2 4.7K_0402_5% Current limit MMBT3904_NL_SOT23-3 KSO10 @C793
@ C793 1 2 100P_0402_50V8J
SMB_EC_DA2 R574 1 2 4.7K_0402_5%
SMB_EC_CK2 R575 1 2 4.7K_0402_5% 02/13 Add HDA level KSO11 @C794
@ C794 1 2 100P_0402_50V8J
GATEA20 1 21 R1130 1 2 22_0402_5%
<21> GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F FAN_PWM INV_PWM <19>shift KSO14
03/28 PV2 Change SM bus power to +3VL 2 23 @C795
@ C795 1 2 100P_0402_50V8J
<21> KB_RST# SIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP FAN_PWM <6>
<22> SIRQ 3 26 EC_BEEP <28>
LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF KSO13 @C796
@ C796 1
<21,26> LPC_FRAME# 4 27 ACOFF <38> 2 100P_0402_50V8J
@ C722 @ R576 LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 0.01U_0402_16V7K
<21,26> LPC_AD3 5 LAD3
1 2 1 2 <21,26> LPC_AD2 LPC_AD2 7 PWM Output C720 1 2 ECAGND KSO12 @C797
@ C797 1 2 100P_0402_50V8J
33_0402_5% LPC_AD1 LAD2 BATT_TEMP
<21,26> LPC_AD1 8 63 BATT_TEMP <37>
15P_0402_50V8J LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP KSO3
LAD0 LPC & MISC
<21,26> LPC_AD0 10 64 @C798
@ C798 1 2 100P_0402_50V8J
BATT_OVP/AD1/GPIO39 ADP_I BATT_OVP <37>
ADP_I/AD2/GPIO3A 65 ADP_I <38>
CLK_PCI_EC 12 AD Input 66 ADP_ID KSO6 @C799
@ C799 1 2 100P_0402_50V8J
<17> CLK_PCI_EC PCI_RST# PCICLK AD3/GPIO3B TP_BTN# ADP_ID <37>
<20> PCI_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75 TP_BTN# <33>
1 2 ECRST# 37 76 ANA_MIC_DET KSO8 @C800
@ C800 1 2 100P_0402_50V8J
+3VL ECRST# SELIO2#/AD5/GPIO43 ANA_MIC_DET <29>
R578 47K_0402_5% 20
<22> EC_SCI# HDA_RST#_EC R403 1 SCI#/GPIO0E KSO7
2 0_0402_5% 38 CLKRUN#/GPIO1D
@C801
@ C801 1 2 100P_0402_50V8J
68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG <19>
1

2 1 J1 11/09 Delete 70 VCTRL KSO4 @C802

@ C802 1 2 100P_0402_50V8J
EN_DFAN1/DA1/GPIO3D IREF VCTRL <38>
C721 0.1U_0402_16V4Z DA Output 71
JOPEN CLKRUN# KSI0 IREF/DA2/GPIO3E AC_SET IREF <38> KSO2 @C803
@ C803 1
11/09 Add HDA_RST# to EC 55 72 2 100P_0402_50V8J
2

KSI1 KSI0/GPIO30 DA3/GPIO3F AC_SET <38>

56 KSI1/GPIO31
11/17 Change to KSI2 57 +5V_TP KSI0 @C804
@ C804 1 2 100P_0402_50V8J
KSI3 KSI2/GPIO32 EC_MUTE#
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <29>
+3VALW
04/29 MV1 Change to KSI4 59 84 USB_EN#
USB_EN# <30>
R579 1 2 10K_0402_5% KSO1 @C805
@ C805 1 2 100P_0402_50V8J
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B I2C_INT R580 1
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 2 10K_0402_5%
+3VL KSI6 MUTE_LED I2C_INT <33> KSO5
+3VALW +3VL
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
MUTE_LED <34>
@C806
@ C806 1 2 100P_0402_50V8J
SYSON SUSP# PCI_RST# +3VS KSI7 62 87 TP_CLK
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <33> KSI3 @C807
@ C807 1
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <33> 2 100P_0402_50V8J
KSO1 40 KSO1/GPIO21
2

KSO2 41 02/13 Correct AC_LED control by EC KSI2 @C808

@ C808 1 2 100P_0402_50V8J
KSO2/GPIO22
1

R213 R581 R713 KSO3 42 97 R582 1 2 0_0402_5%

KSO3/GPIO23 SDICS#/GPXOA00 AC_LED# <37>
1

8.2K_0402_5% 8.2K_0402_5% 100K_0402_5% KSO4 43 98 DOCK_VOL_UP# KSO0 @C809

@ C809 1 2 100P_0402_50V8J
@R124
@ R124 R583 R721 KSO5 KSO4/GPIO24 SDICLK/GPXOA01 DOCK_VOL_DWN# DOCK_VOL_UP# <34>
10K_0402_5% 10K_0402_5% 10K_0402_5% KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 DOCK_VOL_DWN# <34> 11/09 don't stuff when use KSI5 @C810
@ C810 1
45 KSO6/GPIO26 Matrix 109 2 100P_0402_50V8J
1

KSO7 SDIDI/GPXID0 C0
46 SPI Device Interface
2

KSO8 KSO7/GPIO27 KSI4 @C811

@ C811 1
47 2 100P_0402_50V8J
2

KSO9 KSO8/GPIO28 FRD#

48 KSO9/GPIO29 SPIDI/RD# 119 FRD# <31>
KSO10 49 120 R227 1 2 33_0402_5% FWR# KSO9 @C812
@ C812 1 2 100P_0402_50V8J
LID_SW# TP_BTN# KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK FWR# <31>
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 R228 1 2 47_0402_5%
SPI_CLK <31>
01/03 Change to KSO12 51 128 R229 1 2 33_0402_5% FSEL# KSI6 @C813
@ C813 1 2 100P_0402_50V8J
KSO12/GPIO2C SPICS# FSEL# <31>
11/07 Add SYSON and SUSP# PD KSO13 52
+3VS KSO14 KSO13/GPIO2D R720 KSI7
53 1 2 10K_0402_5% +5VL @C814
@ C814 1 2 100P_0402_50V8J
+3VL +3VALW KSO15 KSO14/GPIO2E CIR_IN
54 73 CIR_IN <29,34>
KSO15/GPIO2F CIR_RX/GPIO40 KSI1 @C815
@ C815 1
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 11/09 PU +5VL move to M/B 2 100P_0402_50V8J
82 89 FSTCHG SPI_CLK
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <38>
90 STD_ADP 10K_0402_5%
BATT_CHGI_LED#/GPIO52 STD_ADP <38>
2

91 CAPS_LED# 1 2 2
CAPS_LED#/GPIO53 CAPS_LED# <33>

4.7U_0603_6.3V6K
@ R585 R191 SMB_EC_CK1 77 GPIO 92 BAT_LED# R1132
<31,33,37>
10K_0402_5% SMB_EC_CK1 SMB_EC_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 ON/OFFBTN_LED# BAT_LED# <33>
10K_0402_5% 78 93 C818
<31,33,37> SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# <33>

100K_0402_5%
+3VS

C1408
11/15 Delete PCI_PME# SMB_EC_CK2 79 SM Bus 95 1 22P_0402_50V8J R407
<6> SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56

1
SMB_EC_DA2 80 121 VR_ON 1 10K_0402_5%
1

<6> SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <43>

R1133
127 AC_IN DOCK_VOL_UP# 2 1
@ R589 1 EC_PME# AC_IN/GPIO59 SYSON
<20> PCI_PME# 2 2 1
0_0402_5% R586 10K_0402_5% 2 <9,26,33,36,41> DOCK_VOL_DWN# 2 1
SLP_S3# 6 100 EC_RSMRST# R408

2
EC_PME# <22>
SLP_S5# SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <22>
R190 1 2 14 101 R588 1 2 10K_0402_5%
<33> WL_BLUE_BTN <22> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <22>
OPP@ 0_0402_5% EC_SMI# 15 102 EC_ON 0_0402_5%
<22> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <39> R254
LID_SW# 16 103 WL_BLUE_LED# 100_0402_5%
<33>
ESB_CLK_R 17
LID_SW# LID_SW#/GPIO0A
SUSP#/GPIO0B
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
104 PM_PWROK_R WL_BLUE_LED# <33>
1 2
PM_PWROK <9,22>
14" INT_KBD
R592 1 2 ON/OFFBTN ESB_DAT_R 18 GPO 105 R1131 1 2
<34> DOCK_SLP_BTN#
0_0402_5%
@ R591
EC_PME#
0_0603_5%
19
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D GPIO
BKOFF#/GPXO08
WL_OFF#/GPXO09
106 M_PWROK
TP_LED# M_PWROK <9,22>
22_0402_5% BKOFF# <19>
CONN.( TYPE "D"
11/07 Connect DOCK_SLP_BTN# to <9> TSATN# 1 2 25 107 PV PWROK sequence issue
ON/OFFBTN <34> CONA#
CONA#
WWAN_POWER_OFF 29
28
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
GPXO10
GPXO11 108
TP_LED# <33>
KB)
<26> WWAN_POWER_OFF UTX FANFB2/GPIO15 Current limit
<26> UTX 30
R5931 LAN_POWER_OFF_R EC_TX/GPIO16 SLP_S4# JP19
+3VL 2
ON/OFFBTN
31
EC_RX/GPIO17 PM_SLP_S4#/GPXID1
110
ENBKL
11/07 Add SLP_S4#
SLP_S4# <22,36> to South bridge KSO15
4.7K_0402_5% 32 112
EC_PME# PCI_RST# <33> ON/OFFBTN DIM_LED ON_OFF/GPIO18 ENBKL/GPXID2 EAPD_CODEC ENBKL <11> KSO10 1
<36> DIM_LED 34 114 EAPD_CODEC <28>
NUM_LED# PWR_LED#/GPIO19 GPXID3 THERM_SCI# KSO11 2
<33> NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 THERM_SCI# <22> 3
1 1 116 SUSP# KSO14
C723 GPXID5 PWRBTN_OUT# SUSP# <26,28,36,38,40> KSO13 4
117 PWRBTN_OUT# <22>
C324 C325 15P_0402_50V8J GPXID6 NMI_DBG# +3VL KSO12 5
118
0.1U_0402_16V4Z 0.1U_0402_16V4Z CRY2 GPXID7 D16 KSO3 6
1 2 122
2 2 XCLK1 +3VL ADP_ID KSO6 7
123 XCLK0 V18R 124 2 1 8
1 KSO8
9
1

AGND

Y5 CH751H-40PT_SOD323-2 KSO7
GND
GND
GND
GND
GND

10

1
3 4 @ C724 R714 KSO4
NC OUT R595 4.7U_0603_6.3V6K 10K_0402_5% KSO2 11
20M_0402_5% KB926QFB0_LQFP128_14X14 2 KSI0 12
2 1
11
24
35
94
113

69

NC IN KSO1 13
03/13 PV2 Add EMI
2

32.768KHZ_12.5P_1TJS125DJ2A073 D14 KSO5 14

For C

2
solution NMI_DBG# 15
1 2 PCI_SERR# PCI_SERR# <20>
KSI3
CRY1 Revision KSI2 16
1 2
+3VL_EC +3VL CH751H-40PT_SOD323-2 KSO0 17
C725 KSI5 18
ECAGND

15P_0402_50V8J KSI4 19
11/07 Correct direction pretect leakage 20
1

1
R715 KSO9
EC DEBUG +EC_AVCC L30 150K_0402_5% 04/29 MV1 Change to KSI6 21
22
0_0603_5% KSI7
UTXport
@ R233 2 1 150K KSI1 23
0_0805_5% L31 D13 24
2

2
R443 1 2 1 2 AC_IN 2 1 ACIN ACES_85201-2405
LAN_POWER_OFF_R ACIN <38>
1 2 C726 0.1U_0402_16V4Z 0_0603_5% CONN@
<25> LAN_POWER_OFF
CH751H-40PT_SOD323-2
0_0402_5% 1 2
+3VL +3VL C791 100P_0402_50V8J
Vendor
Recommend
1

1
R1099
R1100 4.7K_0402_5% C315 @
4.7K_0402_5%
2
10P_0402_25V8K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
2

R731 1 2 33_0402_5% ESB_CLK_R

<33> ESB_CLK
<33> ESB_DAT
R732 1 2 33_0402_5% ESB_DAT_R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB Conn.
02/20 PV EMI reserve Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
C315 near EC MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WWW.AliSaler.Com
Date: Saturday, July 18, 2009 Sheet 32 of 45
 A B C D E

WWW.AliSaler.Com
System
LED D50
White R1095 T/P Board (Inculde T/P_ON/OFF) TP ON/OFF
1 2 1 2
<32> CAPS_LED#
HT-F196BP5_WHITE 470_0402_5%
+5VS_LED
Cap lock TouchPAD ON/OFF LED
+5V_TP

1
1 2 +5VS_LED
+3VL +3VL_CAP
R611 @
1 D52
White R1097 PJP703 10K_0402_5% 1

<32> BAT_LED# 1 2 1 2 +5VALW_LED Battery PAD-OPEN 2x2m SW1

1
+5VL TJG-533-V-T/R_6P

2
+3VL_CAP
HT-F196BP5_WHITE

D53
200_0402_5%
Charge LED @
R253
@ U7
R610
200_0402_5%
R609
200_0402_5%
3 1 TP_BTN# <32>
1 2 3 4 4 2
White R1098 SHDN# BP

2
200_0402_5% 10K_0603_1%
White 2
PA PR

5
6
GND

QSMF-C16E_AMBER-WHITE
1 2 1 2 +5VS_LED
<21> SATA_LED#
1
VIN VOUT
5 11/07 Change part number

2
GS@ +5VS D12
3 4 1 2 HDD LED 1
@ C316 APL5151-33BC-TRL SOT23 5P 3.3V PA@
AMBER White
<22> HDDHALT_LED# +3VS

Amber

White

Amber

White
R728 1U_0603_10V4Z
AMBER AMBER White D21

1
200_0402_5% @ C317 PR@
Amber 2 0.33U_0603_10V7K R718

1
QSMF-C16E_AMBER-WHITE 02/13 Add PR TP LED

1
10K_0402_5%

2
QSMF-C16E_AMBER-WHITE
D17
White R980 TP_LED#
ON/OFFBTN_LED# 1 2 1 2 +5VALW_LED System #PV reserve LDO for capacitor sensor board
TP_LED# <32>

1
D
HT-F196BP5_WHITE 200_0402_5%
Power LED 03/28 PV2 Delete LDO 2
G
Q4 S On (TP_LED#=L)-> White

3
2N7002_SOT23-3
Off (TP_LED#=H)-> Amber
02/22 Add C on +3VL
04/29 MV1
2
Capacitor +5VS_LED +3VL_CAP +5VALW_LED
Delete C322
+3VL
TP_DATA
TP_CLK 2

Sensor
02/13 Add Conn
ON/OFFBTN_LED# and ON/OFFBTN T/P Board Conn
1

2
1
on Cap board connector for OPP R51 R53 D28
0_0805_5% 0_0805_5% + C322 @ PSOT24C_SOT23-3
Main@ OPP@ 22U_A_4VM
+5VALW +5V_TP
2

2
OPP@ R151 2
1 2 0_0402_5% R691 1 2 0_0603_5%

1
<32> WL_BLUE_BTN +5V_TP
WL_BLUE_LED# OPP@ R169 1 2 0_0402_5% JP59
1
EMI request
1

S
OPP@ R237 0_0402_5%

D
<32> ON/OFFBTN_LED# 1 2 2 3 1
SMB_EC_CK1 Main@ R729 0_0402_5% 2
<31,32,37> SMB_EC_CK1 ESB_CLK
1 2 3
3 1 02/25 EMI request
Main@ R56 1 2 33_0402_5% 4 Q23 @ C729
<32> ESB_CLK 4 Add D28 and C729

1
ENE ESB_DAT Main@ R149 33_0402_5% SI2301BDS-T1-E3_SOT23-3 0.1U_0402_16V4Z

G
1 2 5

2
<32> ESB_DAT 5
6 @ R612
<32> I2C_INT 6 2
7 10K_0402_5% JP23
Main@ 7 NUM_LED# I2C_INT
<32> NUM_LED# 8 1
SMB_EC_DA1 R730 8 1 TP_CLK
1 2 0_0402_5% 9 2 TP_CLK <32>

2
<31,32,37> SMB_EC_DA1 9 2

15P_0402_50V8J

0.1U_0402_16V4Z
OPP@ R238 1 2 0_0402_5% 10 1 1 5 3 TP_DATA
<32> ON/OFFBTN 10 G1 3 TP_DATA <32>
1 11 6 4
GND G2 4

C329

C326
Cypress 12
GND
@

C323 1 ACES_85201-04051

1
2 2 D

@
R234 C310 15P_0402_50V8J 4.7U_0603_6.3V6K ACES_85201-1005N CONN@ 1 1
ESB_CLK 2 CONN@ SYSON 2 @ Q24
2 1 2 1 <9,26,32,36,41> SYSON
C313 G 2N7002_SOT23-3 @ C730 @C731
@ C731
33_0402_5% 15P_0402_50V8J 2 S 100P_0402_50V8J 100P_0402_50V8J

3
2 2

01/03 02/25 03/13 PV2 Add

EMI EMI EMI solution
3 request request 3

ON/OFF Button Connector Keyboard backlight Mini card LED +3VS

1
Conn R193
10K_0402_5%

2
+5VALW_LED
@ R205 JP9
JP10 1 2 1 WL_BLUE_LED# <32>
+5VS_LED 1
1 2 Q11
ON/OFFBTN 1 0_0805_5% 2 2N7002_SOT23-3
2 3 5
2 3 G1

1
ON/OFFBTN_LED# D
3 5 4 6
3 G1 4 G2
4 4 G2 6 <30> BT_LED 2
ACES_85201-04051 G

1
ACES_85201-04051 CONN@ S

3
CONN@ R716
100K_0402_5%

2
01/03 Keyboard backlight reserve a 0805
D24 CH751H-40PT_SOD323-2
size resistor <26> WL_LED# 1 2
R257

Lid Switch ESB_DAT

@ R252
@R252
2 1
@ C260
2 1
<26> WW_LED# 1

D58
2

CH751H-40PT_SOD323-2
1 2 0_0402_5% WL_LED

4 Connector +3VL

1
JP11
33_0402_5% 15P_0402_50V8J
02/20 PV change to doide 4

1
<32> LID_SW# 2 2 02/20
3 3 G1 5
EMI
10P_0402_25V8K

0.1U_0402_16V4Z

1 1 4 4 G2 6 01/03 Change Lid switch connector type 11/20 Reserve WW_LED function
request
C246

ACES_85201-04051 02/18 Support Hall sensor module, move

C243

CONN@
2 2 C243、、 C246 to M/B Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
03/18 Delete Lid switch pin 1 KBD, ON/OFF, SW, CIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
04/29 MV1 Change LID switch power to +3VL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

A B
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
E
Sheet 33 of 45
WWW.AliSaler.Com Atlas/ Saturn Dock

JDOCK1

RED 38 39 12/18 Correct

<18> RED GREEN CRT_Red Digital gnd
<18> GREEN BLUE
40
CRT_Green TV Luma
37
GND 02/13 Add 33 ohm for isolate
<18> BLUE D_DDCDATA
34
CRT_Blue TV chroma
35 11/07 Delete TVout function from
<18> D_DDCDATA 36 33
D_DDCCLK DDC_DATA TV composite VGA_GNDDocking
DOCK_PWR_ON Spec <18> D_DDCCLK D_HSYNC
30
32
DDC_Clock TV ground
31
29 CIR_IN
<18> D_HSYNC Hsync CIR input CIR_IN <29,32>
0V = Notebook S4/S5, Dock <18> D_VSYNC
D_VSYNC
USB20_N3
26
Vsync PWR_ON
27 DOCK_PWRON
D_MUTE_LED R246 1
<22> USB20_N3 28
USB- Mute_LED
25 2 33_0402_5% MUTE_LED <32>
off <22> USB20_P3
USB20_P3 22
USB+ Sleep Botton
23 D_DOCK_SLP_BTN# R247 1 2 33_0402_5% DOCK_SLP_BTN# <32>
24 21 JACK_DET#
2.5V = Notebook S3, Dock on 12/18 Correct 18
Digital gnd
MDI3-
Jack Detect
VOL_up
19 R_VOL_UP# R617 1 2 200_0402_5%
JACK_DET# <28,29>
DOCK_VOL_UP# <32>
DOCK@ D57 20 17 R_VOL_DWN# R618 1 2 200_0402_5%
4V = Notebook
R974 1 S0, Dock on
2 1K_0402_5% 2 GND 14
MDI3+ VOL_down
15 SPDIFO_L DOCK@
DOCK_VOL_DWN# <32>
+5VS MD2I- SPDIF
DOCK@ 1 DOCK_PWRON 16 13 AUDIO_OGND GNDA DOCK@
R975 1 RJ45_MIDI1- MDI2+ Audio Output gnd DOCK_LOUT_R
+3VALW 2 1K_0402_5% 3 <25> RJ45_MIDI1- 10 MDI1- Right headphone 11 DOCK_LOUT_R <29>
RJ45_MIDI1+ 12 9 DOCK_LOUT_L DOCK_LOUT_L <29>
<25> RJ45_MIDI1+ RJ45_MIDI0- MDI1+ Left headphone DOCK_MIC_R_C
DAN202U_SC70 6 7
<25> RJ45_MIDI0- RJ45_MIDI0+ MDI0- Mic_Right DOCK_MIC_L_C
DOCK@ 8 5
<25> RJ45_MIDI0+ MDI0+ Mic_Left
1

2 3 AUDIO_IGND GNDA
Battery out Mic gnd
1

D +V_BATTERY DOCK_PRESENT R620 1

4 Battery out Dock_present 1 2 2K_0402_5%
2 R976
<36,42> SYSON# PJP3 +DOCKVIN
G 10K_0402_5% 41
Q58 DOCK@ GND
S B+ 1 2 42
3

2N7002_SOT23-3 GND
45 GND GND 43
DOCK@ 46 44 +DOCKVIN
PAD-OPEN 2x2m GND GND
C305 1 2
CONN@ FOX_QL1122L-H212AR-7F @ 1000P_0402_50V7K
1
C306 1 2
@ 1000P_0402_50V7K C734
1000P_0402_50V7K
2 DOCK@
11/12 Change to
+3VL GNDA
Dock +3VL
11/17 Reserve
PRESENT
2

R621
10K_0402_5%
MIC_Dock R_VOL_UP# DOCK_LOUT_R
1

R_VOL_DWN# DOCK_LOUT_L
<32> CONA#
Need 600 Ohm 500 mA 1 1

1000P_0402_50V7K

1000P_0402_50V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
1

R979 D
1 1
DOCK_PRESENT 1 2 2 L36 DOCK@ C740 C741
G Q27 FBM-11-160808-601-T_0603 DOCK@ 2 2 DOCK@
22_0402_5% S 2N7002_SOT23-3 <28> DOCK_MIC_R 1 2 DOCK_MIC_R_C C744 C745
3
1

DOCK@ DOCK@ DOCK@ 2 2 DOCK@

R623 1 2 DOCK_MIC_L_C
<28> DOCK_MIC_L
2K_0402_5% L37 DOCK@
DOCK@ FBM-11-160808-601-T_0603 1 1 GNDA GNDA
2

C754 C755
220P_0402_50V7K 220P_0402_50V7K 11/17 Recommend
DOCK@ 2 2 DOCK@

GNDA GNDA
+3VS

SENSE_B# <28> +1.5VS_HDA

2
2

R625
R626 10K_0402_5%

2
10K_0402_5% DOCK@

1
DOCK@ D R722 @

1
2 Q29 33_0402_5%
1

1 G 2N7002_SOT23-3
C S DOCK@

1 1
Q32 2 C64 R977
MMBT3904_NL_SOT23-3 B D DOCK@ DOCK@
1

R632 DOCK@ C E @ Q55 2 1 2 1 2 SPDIF_OUT <28>

3

DOCK_MIC_L_C 1 2 2 Q30 2N7002_SOT23-3 G 220_0402_5%

10K_0402_5% B MMBT3904_NL_SOT23-3 S 0.1U_0402_16V7K

3
2

DOCK@ 2 E DOCK@ R723

3

1
DOCK@ 1
C757 SPDIFO_L 1 2
R633 0_0603_5% C819 R978
47K_0402_5% 1 220P_0402_25V8J 110_0402_5%
1

DOCK@ DOCK@ 2 DOCK@

2
1U_0603_10V6K
DOCK@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WWW.AliSaler.Com
Date: Saturday, July 18, 2009 Sheet 34 of 45
 5 4 3 2 1

WWW.AliSaler.Com +3VS_LS +3VS_LS

R648
<11> TMDS_B_DATA2# TMDS_B_DATA1 <11>
<11> TMDS_B_DATA2 TMDS_B_DATA1# <11> +3VS 1 2 +3VS_LS

10U_0805_6.3V6M
0.01U_0402_16V7K

0.1U_0402_10V6K

0.1U_0402_10V6K
EQUALIZATION SETTING: 0_0603_5%
<11> TMDS_B_CLK# TMDS_B_DATA0 <11>
[PC1,PC0]=00,8dB <11> TMDS_B_CLK TMDS_B_DATA0# <11>
[PC1,PC0]=01,4dB (Recommanded) 2 1 1 1
[PC1,PC0]=10,12dB

C321

C320

C319

C318
[PC1,PC0]=11,0dB 1 2 2 2

48

47

46

45

44

43

42

41

40

39

38

37
U43
D D

IN_D4-

IN_D3-

IN_D2-

IN_D1-
IN_D4+

IN_D3+

IN_D2+

IN_D1+
VCC3V

VCC3V
GND

GND
PV 02/20 follow datasheet
+3VS_LS +3VS_LS
1
GND GND
36 PV 02/20 follow datasheet
+3VS_LS 2 35
VCC3V FUNCTION4
11/07 Enable DDC_EN pin
R255 1 2 4.7K_0402_5% 3 PC0 34
FUNCTION1 FUNCTION3
Follow Intel @R256
@ R256 1 2 4.7K_0402_5% 4 PC1 33 +3VS_LS R651 2 1 0_0402_5% +3VS_LS
FUCNTION2 VCC3V

1
Feedback putting R649 R650 5 32 @ R652 2 1 0_0402_5%
2.2K_0402_5% 2.2K_0402_5% R653 GND DDC_EN
2.2K ohm
2 1 475_0402_1% 6 ANALOG1(REXT) GND 31

2
TMDS_B_HPD 7 30 HDMI_DETECT
HPD_SOURCE HPD_SINK
8 29 HDMIDAT
<9> HDMIDAT_NB SDA_SOURCE SDA_SINK
9 28 HDMICLK
<9> HDMICLK_NB SCL_SOURCE SCL_SINK
10 ANALOG2 GND 27

+3VS_LS 11 26 +3VS_LS @ R654 2 1 0_0402_5% +3VS_LS

VCC3V VCC3V
+3VS_LS R9
12 25 R655 2 1 0_0402_5%
TMDS_B_HPD 1 TMDS_B_HPD# GND OE*
2

OUT_D4+

OUT_D3+

OUT_D2+

OUT_D1+
OUT_D4-

OUT_D3-

OUT_D2-

OUT_D1-
VCC3V

VCC3V
1

GND

GND
@ R742 0_0402_5%
20K_0402_5%
C C

13

14

15

16

17

18

19

20

21

22

23

24
CH7318A-BF-TR_QFN48_7X7
2

TMDS_B_HPD#
TMDS_B_HPD# <11>
HDMI_TX_0-
1

D @ Q28 @C769 @ R656 @R657

@ R657 @C770
@C770
1

TMDS_B_HPD 2 HDMICLK+ 1 2 1 2 HDMI_TX_0+

G R744 68_0402_5% 68_0402_5%
1

S 7.5K_0402_1% HDMICLK- 0.5P_0402_50V8B +3VS_LS +3VS_LS 0.5P_0402_50V8B

3

@ R743 2N7002_SOT23-3
20K_0402_5% HDMI_TX_1-
2

@C771 @ R658 @R659

@ R659 @C772
@C772
HDMI_TX_2+ 1 2 1 2 HDMI_TX_1+
2

@ 68_0402_5% 68_0402_5%
HDMI_TX_2- 0.5P_0402_50V8B 0.5P_0402_50V8B
Follow Vendor
Feedback
11/07 correct TMDS_B_HPD# connection to North
bridge 、 C314
02/20 PV EMI request add C273、

R1121

L38
1 2 0_0402_5%
HDMI Connector +5VS
@
C273
1 2
HDMICLK- 1 2 HDMI_CLK-
1 2
2200P_0402_25V7K

2
WCM-2012-670T_0805
HDMICLK+ 4 3 HDMI_CLK+
B 4 3 RB411D T146 _SOT23-3 B
Vendor suggests 4K D31
R1122 1 2 0_0402_5% PU
11/07 Follow recommend change to 3.9K

1
+5VS_HDMI
R1123 1 2 0_0402_5%
1 1
L39

3.9K_0402_1%

3.9K_0402_1%
HDMI_TX_0- 1 2 HDMI_TX0- 0.1U_0402_16V4Z C314 @
1 2

1
C773 2200P_0402_25V7K
WCM-2012-670T_0805 2 2

R49

R50
HDMI_TX_0+ 4 3 HDMI_TX0+
4 3

2
R1124 1 2 0_0402_5%
JHDMI1
R1125 1 2 0_0402_5% 18
HDMIDAT +5V
16 SDA CEC 13
L41 R665 L40 HDMICLK 15 14
HDMI_TX_1- HDMI_TX1- HDMI_DETECT SCL Reserved
1 2 1 2 1 2 19
1 2 1K_0402_1% HP_DET
2
GND
1

1
WCM-2012-670T_0805 FBML10160808121LMT_0603 1 HDMI_CLK- 12 5
HDMI_TX_1+ HDMI_TX1+ HDMI_CLK+ CK- GND
4 4 3 3 10 CK+ GND 8
D32 R666 HDMI_TX0- 9 11
SKS10-04AT_TSMA 10K_0402_1% C774 HDMI_TX0+ D0- GND
7 20
R1126 0_0402_5% 330P_0402_50V7K 2 HDMI_TX1- D0+ GND
1 2 6 21
2

HDMI_TX1+ D1- GND

4 22
R1127 0_0402_5% HDMI_TX2- D1+ GND
1 2 3 23
HDMI_TX2+ D2- GND
1 D2+ DDC/CEC_GND 17
L42
HDMI_TX_2- 1 2 HDMI_TX2-
1 2 SUYIN_100042MR019S153ZL
WCM-2012-670T_0805 CONN@
A HDMI_TX_2+ HDMI_TX2+ A
4 4 3 3

R1128 1 2 0_0402_5%

01/03 Reserver 0 ohm co lay with common

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
choke HDMI LS & Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 35 of 45
 5 4 3 2 1

WWW.AliSaler.Com
+5VALW to +5VS Transfer +3VALW to +3VS Transfer DIM LED
+5VALW +5VS B+ +3VALW +3VS

B+ U32 U33 +5VALW +5VALW_LED

10U_0805_10V4Z Q33
8 1 8 1
D S D S

1
10U_0805_10V4Z
7 2 1 7 2 SI2301BDS-T1-E3_SOT23-3
D S D S

10U_0805_10V4Z
0.1U_0402_16V4Z
1 6 3 R636 C759 6 3
D S D S
1

S
C760

D
5 4 1 1 5 4 1 1 3 1
D R223 D G C761 C762 330K_0402_5% 10U_0805_10V4Z D G C763 C764 D

1
AO4466_SO8 2 AO4466_SO8 1

2
330K_0402_5% 2 R637 C758

G
2
2 2 2 2 10K_0402_5% 0.1U_0402_16V4Z
2

RUNON_3VS

1
2

2
3
RUNON R638 0.1U_0402_16V4Z DIM_LED#

1
6

470_0402_5% +5VS +5VS_LED

Q15

1
R224 SUSP D
5

2
470_0402_5% 1 2 Q35 SI2301BDS-T1-E3_SOT23-3
SUSP <32> DIM_LED
2 01/03 Sparate+5VS C765 G 2N7002_SOT23-3

S
Q34B

D
S 3 1

3
1 and +3VS power 0.01U_0402_16V7K
1

Q34A 2
C65
timing 2N7002DW-7-F_SOT363-6
1
C294

G
2
2N7002DW-7-F_SOT363-6 4700P_0402_25V7K 0.1U_0402_16V4Z
2 DIM_LED#
2

+1.5V to +1.5VS Transfer +3VALW +1.8V

+1.5V +1.5VS +3VL +3VL

B+ U34
U47

1
8 D S 1
1 7 2 1 5 R639 R640

10U_0805_10V4Z
C D S IN OUT C
0.1U_0402_16V4Z

C766 6 3 R1114
D S
1

10U_0805_10V4Z
5 4 1 2 C1405 2 47K_0402_1% 100K_0402_5% 100K_0402_5%
D G GND

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
R647 10U_0805_10V4Z @ R1115 1

2
2
C1404

AO4466_SO8 0_0201_5% 3 4 SYSON# SUSP

SHDN BYP <34,42> SYSON# SUSP <42>

C1407
330K_0402_5%
2 1 G916-390T1UF_SOT23-5
2

3
1 2 2
<22,32> SLP_S4#
Q13A Q13B
RUNON_1.5VS R1116 R1117
0_0402_5% 100K_0402_1% 2 5 SUSP#
<9,26,32,33,41> SYSON SUSP# <26,28,32,38,40>
1

4
R1113
1K_0402_5%
1

D
2

SUSP 2
G 1
Q44
S
VOUT=1.25(1+R912/R913)
3

2N7002_SOT23-3 C1406
0.1U_0402_25V4K
2 VOUT=1.25(1+100k/215k)=1.83V

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
Discharge circuit

1
+5VS +3VS +1.5VS +VCCP +1.5V +0.75V
B B
H15 H16 H17 H18 H19 H20 H11
1

1
HOLEA HOLEA HOLEA HOLEA HOLEC HOLEC HOLEA
R641 R642 R644 R645 R643 R646

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

1
2

2
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
6

3
FM1 FM2 FM3 FM4
Q6A Q6B Q9A Q9B Q12A Q12B 1 1 1 1
SUSP 2 SUSP 5 SUSP 2 SUSP 5 SYSON# 2 SUSP 5
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 36 of 45
 A B C D

WWW.AliSaler.Com
+3VALW
PQ3

3
TP0610K-T1-E3_SOT23-3
+3VL
1 PR9 2
100K_0402_5% connect to KBC pin97 BATT
1 2 AC_LED# <32> 1

340K_0402_1%
PR1 1
+5VALW
ADP_ID <32>

0.01U_0402_25V7K
2 1

PC12

2
1

1
PC1
PR8 PD4 @1000P_0402_50V7K

499K_0402_1%
PR4 1
2K_0402_5% PR2
10K_0402_5%
VIN +DOCKVIN

2
1

2
ACES_88334-057N RLZ3.6B_LL34
ADP_SIGNAL 1 2

8
5 PR3 PR5
5 10K_0402_5% 10K_0402_5%
4 3

P
4 PL1 PL2 +
3 3 0 1 2 1 BATT_OVP <32>
2 SMB3025500YA_2P SMB3025500YA_2P 2
2 -

G
ADPIN

105K_0402_1%
1 1 1 2 2 1

PR6 1
0.01U_0402_25V7K

4
1
PJP1 PU1A

PC6
LM358ADT_SO8
100P_0402_50V8J

1000P_0402_50V7K

2
2

PD1

100P_0402_50V8J

2
1

1
PC5
PC4
PC3
2

2
PC2

1000P_0402_50V7K
@PJSOT24C_SOT23-3
1

2 2

VMB
PL3 BATT
PJP2 HCB2012KF-121T50_0805
8 8 1 2
PL4
7 7
6 EC_SMD PD2 HCB2012KF-121T50_0805
PH1 under CPU botten side :
6 EC_SMC @SM05_SOT23
5 5
4 3
1 2 CPU thermal protection at 90 +-3 degree C
4
1

3 3 1
2 2 2
1 PC8 PC9
2

1 1000P_0402_50V7K 0.01U_0402_50V4Z PR7

GND 9
10 +5VS 604K_0402_1%
GND
3

3 SUYIN_200275MR008GXOLZR CPU 1 2
3
1
1

1
PD3
1

PR14 @SM24.TC_SOT23-3 PH1

PR13 100_0402_5% 10K_TH11-3H103FT_0603_1%
100_0402_5%
2

EN0_TRIP <39>
2

2
SMB_EC_DA1 SMB_EC_DA1 <31,32,33> PR10

8
200K_0402_1%
D

1
1 2 5

P
SMB_EC_CK1 + PQ1
SMB_EC_CK1 <31,32,33> 0 7 2
+5VALW 1 2 6 G SSM3K7002FU_SC70-3
-

G
BAT_ID <38> PR11 PU1B S

3
1 150K_0402_1%

4
1

1
LM358ADT_SO8

1
PC10 PR12
PR16 2.49K_0402_1%
6.49K_0402_1% +3VL 0.22U_0603_10V7K PR15
2

1 2 150K_0402_1% PC11
2

2
1000P_0402_50V7K ENTRIP2 <39>

2
1

1
PR17
1K_0402_5% 2 PQ2
G @SSM3K7002FU_SC70-3
BATT_TEMP <32>
2

3
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

A B
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Date: Saturday, July 18, 2009
D
Sheet 37 of 45
 A B C D

WWW.AliSaler.Com
P4 B+

BATT
VIN P2
PQ102
FDS6675BZ_SO8
1 8
PQ101 PQ103 PR102 PL101 2 7

@1000P_0402_50V7K
1 1
SI4835DDY-T1-E3_SO8 SI4459ADY 0.012_2512_1% HCB2012KF-121T50_0805 3 6

1
8 1 1 8 1 2 1 2 CHG_B+ 5
PR103

PC132
7 2 2 7

1
6 3 3 6 47K_0402_5%

2
5 5 PC133 1 2 1 2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PR101 470P_0402_50V7K VIN

1
47K_0402_5% PR104 ACDET PC102
47P_0402_50V8J

1
0_0402_5%

PC103

PC104

PC105
1 2 1U_0603_6.3V6M

0.1U_0603_25V7K
<32> AC_SET 1 2 ACSET

2
1

3
PR105
PC101

1
10K_0402_5%

0.1U_0603_25V7K

PC108
1

1
2

2
1
2 PC107 PR140 PC109 ACOFF#

200K_0402_5%

2
1

@0.01U_0402_16V7K 100K_0402_5% @0.1U_0603_25V7K

PC106

PR106

270P_0402_50V7K
2

1
470P_0402_50V7K
1000P_0402_50V7K
2

2
PR107 CHGEN# CHG_B+

2
47K_0402_1% PQ104 PR108

PC129

PC130
1 2 2 DTA144EUA_SC70-3 10_1206_5%
1

1
1 2 2 ACOFF <32>

LPMD

ACN

CHGEN
LPREF

ACSET

ACDET

ACP

1
PQ105

PC134
29

5
6
7
8
DTC115EUA_SC70-3 PR110 TP PC110
<26,28,32,36,40> SUSP#
3

PQ107 0_0402_5% 1U_0805_25V6K

3
1

SSM3K7002FU_SC70-3 D PR109 PC128 PQ106

1 2 8 28 1 2
150K_0402_5% IADSLP PVCC DTC115EUA_SC70-3
2 1 2
G PC111 PQ108

2
S @180P_0402_50V8J 9 27 BST_CHG 1 2 4 AO4466_SO8
3

AGND BTST
PC112 BQ24740VREF PU101 0.1U_0402_10V7K
PACIN_1 <39> 1 2 10 BQ24740RHDR_QFN28_5X5 26 DH_CHG BATT
VREF HIDRV PL102 PR112

3
2
1
PR111 PQ109 1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
1

3K_0402_1% D LX_CHG
11 25 1 2 1 2
PACIN SSM3K7002FU_SC70-3 VDAC PH
1 2 2

1
G PD102

5
6
7
8
S PR113 VADJ 12 24 REGN 2 1 PR141
3

PD101 143K_0402_1% VADJ REGN 4.7_1206_5%

ACOFF# 1 2 PR114 RLS4148_LL34-2

@1000P_0402_50V7K
2 2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
@0_0402_5% 13 23 DL_CHG
2

2 2
EXTPWR LODRV

1
1SS355_SOD323-2<32> VCTRL 1 2

PC113

PC114

PC115

PC116

PC136

PC131
4
1

14 22 FDS6690AS_NL_SO8 PC135

2
ISYNSET PGND
1

470P_0603_50V8J

DPMDET

1
1
PC117 PR115 PQ110

IADAPT
1 2

SRSET

CELLS

1
1U_0603_10V6K 100K_0402_1% PC119

SRN

SRP
2

3
2
1
BAT
PR116
2

15K_0402_1% 1U_0603_10V6K PC118

2
0.1U_0402_10V7K

15

16

17

18

19

20

21
PR117
100K_0402_5% BQ24740VREF

IADAPT
PR118
Charge Detector 1 2

1
10K_0402_5%
1 2
<32> ADP_I 47K_0402_5%

1
D PR119

100P_0402_50V8J
0.22U_0603_10V7K
1

1
PQ111 2 BAT_ID <37>

2
SSM3K7002FU_SC70-3
PC120

PC121
G
S

BATT
2

0.1U_0603_25V7K

@0.1U_0603_25V7K
VIN
PR120
2 1 IREF <32>

PC122
133K_0402_1%

PC124
2

1
PC123
1

PD104 0.1U_0402_10V7K PR122

2
1SS355_SOD323-2 PR121 681K_0402_1%
200K_0402_1% 1 2
2

PR123
1

1M_0402_5%
3
1 2 3
1VIN_1

PR124
+3VL VIN 1K_0402_5%
VIN 1 2
PR125 +3VL ACIN <32>

1
47_1206_5%
PR126
1

100K_0402_1% PR127
10K_0402_5%
2

VIN PR130 10K_0402_1%

1

8
+3VL 2.15K_0402_1% PU102B
PR128
10K_0402_1%

2
1 2 5

P
+
1

PACIN
PR129

7
2
1

O
PR131 6
100K_0402_5%

1
-

G
133K_0402_1% PC125 CHGEN#
2

1
0.1U_0603_25V7K PC126 LM393DG_SO8
PR132
2

4
PR133

1
0.047U_0402_16V7K 10K_0603_0.1%
2

PR134
2

2
1

D PD103
3 10K_0402_5%
P

2
+ PQ112 RLZ4.3B_LL34
1 2
O
1

2 G SSM3K7002FU_SC70-3

2
-
G

PU102A S
PR135
3

LM393DG_SO8 FSTCHG#
4

10K_0603_0.1% PR136
60.4K_0402_1%
2

D VIN_1
1 2
1.24VREF <32> FSTCHG 2 PQ113
G SSM3K7002FU_SC70-3
S
3

STD_ADP <32>
PU104

4 3 1.24VREF
ACDET REF CATHODE
1 2

1
PC127 2
PR137 NC
22P_0402_50V8J
1

4 4
20K_0402_1% 5 1
100K_0402_1%

2
ANODE NC
PR138

LMV431ACM5X_SOT23-5
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, July 18, 2009 Sheet 38 of 45
A B C D
 A B C D E

WWW.AliSaler.Com
2VREF_51125

0.22U_0603_10V7K

1
1 1

PC302

2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
PR305 PR306
2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6
4.7U_0805_25V6-K

100K_0402_1% 140K_0402_1%
1

1
PC316

PC301

PC303

PC317
1 2 1 2

10U_1206_25V6M
2200P_0402_50V7K
10U_0805_6.3V6M

1
PC304

PC305
2

2
PQ301

2
6

5
6
7
8
PU301

PC306

1
1 8 UG1_3V

ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
VREF
D1 1G PQ302
2 D1 1S/2D 7 25 P PAD
2 3 6 AO4466_SO8 2

2
G2 1S/2D
4 S2 1S/2D 5
7 VO2 VO1 24 4

UG1_5V
AO4932_2N_SO8 PR308 PC308
8 VREG3 PGOOD 23
PR307 2.2_0402_5% 0.1U_0402_10V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
0_0402_5% VBST2 VBST1
PL302 PC307 UG_3V 10 21 UG_5V PL303
3.3UH_SIQB74B-4R7PF_5.9A_20% 0.1U_0402_10V7K DRVH2 DRVH1 10U_LF919AS-100M-P3_4.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1

5
6
7
8
LG_3V 12 19 LG_5V +5VALWP
DRVL2 DRVL1

SKIPSEL

4.7_1206_5%
@4.7_1206_5%

VREG5

150U_D_6.3VM
1
1

1
VCLK
1

GND
B++

EN0

VIN
+ PR309
PC309
220U_6.3VM_R15

+
PR315

PR316

PC310
1 2 4
1M_0402_1%

13

14

15

16

17

18
2 TPS51125RGER_QFN24_4X4
2

2
2

1
<37> EN0_TRIP
@680P_0603_50V7K

680P_0603_50V7K

3
2
1
VL PQ304

191K_0402_1%
1

1
FDS6690AS_NL_SO8
PC314

PC315
PR311
2

2
1

PC311
10U_0805_10V6K
2
3 3

<37> ENTRIP2

1
PR318
B++
ENTRIP1

1 2

0.1U_0603_25V7K
0_0805_5% R_EC_RSMRST# <22>

2
PC312
2VREF_51125
D D
1

PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
+5VL
3

VL
PJP304
2 1
PJP302 PAD-OPEN 2x2m
1 2
VL +5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
PR313 +3VLP +3VL
PAD-OPEN 4x4m
PQ308 100K_0402_5% PJP301
D D
1

@SSM3K7002FU_SC70-3 PQ307 PJP303

2 1
<38> PACIN_1 1 2 2 2 +3VALWP 1 2 +3VALW (3A,120mils ,Via NO.= 6)
G G PAD-OPEN 2x2m
PR317 S S SSM3K7002FU_SC70-3
@0.047U_0402_16V7K

EC_ON <32> PAD-OPEN 4x4m

3

@604K_0402_1%
1

1
PC318

4 4
100K_0402_5%
2

PR314
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, July 18, 2009 Sheet 39 of 45
A B C D E
 A B C D

WWW.AliSaler.Com

1 1

PR401
0_0402_5%
1 2 PL401
2,36,38> SUSP#
HCB1608KF-121T30_0603
1

PR410 1.05V_B+ 1 2 B+
1

@10K_0402_5%

2200P_0402_50V7K
0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC401
@1000P_0402_50V7K
2

5
6
7
8

1
+5VALW
2

PC406

PC414

PC403

PC404

PC405
BST_1.05V
1 2 BST1_1.05V1 2 @680P_0402_50V7K

2
PR402 PC402
1

0_0402_5% 0.1U_0402_10V7K 4
PR403

15

14
1
316_0402_1% PU401
PR404

EN_PSV

TP

VBST
2 255K_0402_1% PQ401 2
PR411
2

3
2
1
1 2 2 13 DH_1.05V 1 2 AO4466_SO8 PL402
TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
PR405 0_0402_5%
+1.05V_VCCP 2 1 3 12 LX_1.05V 1 2 +1.05V_VCCP
VOUT LL

220U_6.3VM_R15
0_0402_5%

1
4 V5FILT TRIP 11 1 2

5
6
7
8
PR406 PR407
1
5 10 +5VALW 15.4K_0402_1% 4.7_1206_5%
VFB V5DRV +

PC408
1

PC409 6 9 PC415

2 2
PGOOD DRVL

1
PGND
1U_0603_10V6K 4.7U_0805_10V6K

GND
2
4
2

PC412

2
+1.05V_VCCP TPS51117RGYR_QFN14_3.5x3.5 220P_0603_50V8J
PR408
7

1
1 2
10.5K_0402_1% PQ402

3
2
1
DL_1.05V FDS6690AS_NL_SO8
1

PR409
25.5K_0402_1%
2

3 3

PJP401
+1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.=12)
PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05V_VCCP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

A B
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Date: Saturday, July 18, 2009
D
Sheet 40 of 45
 5 4 3 2 1

WWW.AliSaler.Com

D D

B+++ B+
PR521 PL502
2 1 HCB1608KF-121T30_0603
<9,26,32,33,36> SYSON 2 1
0_0402_5% PC524

1
@1000P_0402_50V7K

2
PR510 PC511

4.7U_0805_25V6-K
0_0402_5% 0.1U_0402_10V7K

2200P_0402_50V7K

0.1U_0402_25V6
4.7U_0805_25V6-K
BST_1.5V 1 2 1 2

1
5
6
7
8

1
PC516

1
PC504

PC505

PC521
15

14

2
1
PU502 PQ501

2
PR523 PR508 AO4466_SO8

EN_PSV

TP

VBST

2
255K_0402_1% 0_0402_5%
1 2 2 13 UG_1.5V 1 2 UG1_1.5V 4
C TON DRVH C

+1.5VP 1 2 3 12 LX_1.5V
PR520 0_0402_5% VOUT LL
+5VALW 1 PR515 13.7K_0402_1%
+5VALW 2 4 11 1 2

3
2
1
V5FILT TRIP
PR522 PR501 +1.5VP
+1.5VP 1 2 5 10 +5VALW +5VALW PL501
316_0402_1% VFB V5DRV 2.2UH +-20% PCMC063T-2R2MN 8A
10.2K_0603_0.1%
1

1
6 9 LG_1.5V 1 2
PGOOD DRVL

PGND
PC522 PC523

GND
1U_0603_10V6K 4.7U_0805_10V6K
2

5
6
7
8
7

8
1

1
TPS51117RGYR_QFN14_3.5x3.5 1
PR502 PR516

330U_2V_M_R15M
2
10K_0603_0.1% @4.7_1206_5% +

PC508
PC510
4 4.7U_0805_6.3V6K

1 2

1
2

PQ503
+1.5V PC519 FDS6690AS_SO8

3
2
1
@680P_0603_50V7K

1
PR503
@10K_0402_5%
B B

2
DDR3_SM_PWROK <9>

PJP501
1 2

PAD-OPEN 4x4m

PJP502
+1.5VP 1 2 +1.5V (8A,320mils ,Via NO.= 16)
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, July 18, 2009 Sheet 41 of 45
5 4 3 2 1
 5 4 3 2 1

WWW.AliSaler.Com

D D

+1.5V

PU601
1 VIN VCNTL 6 +5VALW

@10U_0805_10V4Z
2 GND NC 5

PC602

1
PC601 3 7
VREF NC

1
10U_0805_10V4Z

2
PR601 PC603
4 VOUT NC 8
1K_0402_1% 1U_0603_16V6K

2
9

2
TP
G2992F1U_SO8

<34,36> SYSON# 1 2
PR602 +0.75VP

0.1U_0402_16V7K
1
@0_0402_5%
PQ601
SSM3K7002FU_SC70-3 PR603

1
D
1K_0402_1%
1 2 2 PC605
<36> SUSP

2
G 10U_0805_6.3V6M

PC604
PR604

2
0_0402_5% S

3
1
C PC606 C

2
@0.1U_0402_16V7K

PJP601

+0.75VP 1 2 +0.75V (2A,80mils ,Via NO.= 4)

PAD-OPEN 3x3m

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, July 18, 2009 Sheet 42 of 45
5 4 3 2 1

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 5 4 3 2 1

WWW.AliSaler.Com +5VS

B+
CPU_B+

2
<7>

<7>

<7>

<7>

<7>

<7>

<7>
CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR202 PL201

<32>
SMB3025500YA_2P

VR_ON
1_0603_5%
2 1

PC241
470P_0402_50V7K

2200P_0402_50V7K

1000P_0402_50V7K

2200P_0402_50V7K
47P_0402_50V8J
68U_25V_M_R0.44

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

470P_0402_50V7K
1 1 1

1
PC233

PC234

PC205

PC206
PR201 499_0402_1%

68U_25V_M_R0.44
D D

1
+ + +

PC242

PC204

PC207

PC239

PC208

PC240
<9,22> DPRSLPVR 1 2 PC203

PC237

PC243
PC202 2.2U_0603_6.3V6K

68U_25V_M_R0.44
2

2
PR203 0_0402_5% 0.022U_0402_16V7K

2
2 2 2

PR208

PR209

PR210

PR211

PR212

PR205

PR213
PR207
<7,9,21> H_DPRSTP# 1 2 PQ201

PR204 0_0402_5% RQW130N03_PSO8

<17> CLK_ENABLE# 1 2 4

1
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
PR206 0_0402_5%
+3VS 1 2

3
2
1
+3VS

1U_0603_6.3V6M

2
2
1.91K_0402_1%
2.2_0603_5% 0.22U_0603_10V7KUGATE_CPU1-2 PL202

1
PC201
PR214 PC209 0.36UH_PCMC104T-R36MN1R17_30A_20%

1
BOOT_CPU1 1 2 1 2 2 1 +VCC_CORE
2

5
6
7
8

5
6
7
8
PR216
PR215

1
10K_0402_1%

47P_0402_50V8J
4.7_1206_5%

4.7_1206_5%

3.65K_0805_1%

1
PR218

PR245

PR219

PR220
@499_0402_1%

49

48

47

46

45

44

43

42

41

40

39

38

37
1 2
0_0603_5% PR223
2

1
PR217 1_0402_5%

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

PC244
4 4 PR224

1 2

2200P_0603_50V7K 2

2
1 36 @0_0603_5%

2
<17,22> VGATE PGOOD BOOT1 PQ202 1 2

PC210
<7> H_PSI# 2 35 UGATE_CPU1-1 FDS8672S_SO8 VSUM PC211
PSI# UGATE1
1 2

3
2
1

3
2
1

2
1 PR221 2 3 34 PHASE_CPU1 PQ203 VCC_PRM
@0_0402_5% PR222 147K_0402_1% PMON PHASE1 FDS8672S_SO8 ISEN1
1 2 4 33 0.22U_0603_10V7K CPU_B+
RBIAS PGND1
VR_TT# 5 32 LGATE_CPU1
VR_TT# LGATE1

2200P_0402_50V7K
5
C C

47P_0402_50V8J
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
6 NTC PVCC 31

1
PC212

PC213

PC235

PC236
7 30 LGATE_CPU2 PQ204
SOFT LGATE2

1
PC214
ISL6266ACRZ-T_QFN48_7X7 RQW130N03_PSO8

PC238
8 29

2
0.022U_0603_25V7K PC215 OCSET PGND2
4

2
1 2 9 28 PHASE_CPU2
VW PHASE2 PR225
PR226 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2
COMP UGATE2 0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR227 PL203
1 2

5
6
7
8

5
6
7
8

47P_0402_50V8J
4.7_1206_5%

4.7_1206_5%
1000P_0402_50V7K PC216 2.2_0603_5% PC217
DROOP

12 FB2 NC 25

1
VSUM

ISEN2

ISEN1
VDIFF

VSEN

10K_0402_1%
PR229

PR246

3.65K_0805_1%
PR228 13K_0402_1% 0.22U_0603_10V7K
GND

VDD
RTN

DFB

1
VIN

PR231
PR232
VO

1 2

1
PR230

PC245
1 2 PU201
13

14

15

16

17

18

19

20

21

22

23

24

1 2

2
4 4 1_0402_5%

2
PC218 1000P_0402_50V7K

2
PC219
2200P_0603_50V7K
ISEN1 PQ205 PR233 @0_0603_5%
ISEN2 FDS8672S_SO8 1 2

2
1 PR236 2
@0_0402_5%

PR235 97.6K_0402_1% PC220 1 2 +5VS PQ206

3
2
1

3
2
1
2 PR237 1
1K_0402_1%

1 2 2 1 FDS8672S_SO8 VSUM PC223

1

PR234 1_0603_5% 1 2
270P_0402_50V7K PC221
1 2 1U_0402_6.3V6K
2

0.22U_0603_10V7K
PC222 100P_0402_50V8J VCC_PRM
PR239 ISEN2
100_0402_1% PC224 2200P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 CPU_B+
B B
1

PR238 1 2 PC225
0.1U_0603_25V7K
PR240 1K_0402_1%
2

PC226 330P_0603_50V8
<7> VCCSENSE 1 2
VSUM
1

2.61K_0402_1%

PC227 PC228
PR241

330P_0603_50V8 0.01U_0603_50V7K
2

<7> VSSSENSE
2
1

11K_0402_1%

PC229 180P_0402_50V8J
PR242

1 2
2

10KB_0603_5%_ERTJ1VR103J
1 2 1 2 PH201
2

PR243 1K_0402_1% PR244 3.57K_0402_1%

PC230 0.1U_0402_16V7K
1

VCC_PRM 1 2

PC232 0.22U_0402_6.3V6K
PC231 2 1 2 1
0.22U_0603_10V7K

A A

Compal Electronics, Inc.

Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Saturday, July 18, 2009 Sheet 43 of 45
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Version Change List ( P. I. R. List ) for Power Circuit
Item Page# Title Date Request Issue Description Solution Description Rev.
Owner
1 1
3.3VALWP/5VALWP Add PC316, PC317
1 37 5/4 Compal RF solution

2 40 +1.05V_VCCP 5/4 Compal RF solution Add PC414

3 41 +1.5VP 5/4 Compal RF solution Add PC521

2 2

3 3

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Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0

A B
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Date: Saturday, July 18, 2009
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Item Fixed Issue (Reason for change) PAGE Modify List Date Phase

85 DDR2 change to DDR3 09 V_DDR_MCH_REF change to +1.5V 03/31 1.4DB

86 DDR2 change to DDR3 09 SMRCOMP_VOH change to +1.5V 03/31 1.4DB

87 DDR2 change to DDR3 09 SMRCOMP change to +1.5V 03/31 1.4DB

D D

88 DDR2 change to DDR3 09、41 Add AND gate (U48) and R1119~R1120, C1408 for SM_RWOK 03/31 1.4DB

89 DDR2 change to DDR3 12 VCC_SM_CK change to +1.5V 03/31 1.4DB

90 DDR2 change to DDR3 13 VCC_SM change to +1.5V 03/31 1.4DB

91 DDR2 change to DDR3 15、16 Change to DDR3 SODIMM 03/31 1.4DB

92 36 Delete reserve +1.8V DC-DC, and add +1.5V DC-DC 03/31 1.4DB
DDR2 change to DDR3
93 DDR2 change to DDR3 36 Add LDO for +1.8V_LVDS 03/31 1.4DB

94 DDR2 change to DDR3 27 delete +1.8VS_CR, card reader internal LDO can provide +1.8VS 03/31 1.4DB

C C

Gobi RF test and UTX for debug card. 26 modify R750 netname trace, add R1129 for UTX. 06/19 1.4PVR

EMI solution for ENE cap. board. 32 modify R731 and R732 to 33 ohm. BOM change. 06/19 1.4PVR

EMI solution for ENE cap. board. 33 modify R234 ,R56 and R149 to 33 ohm , C310 to 15pF. BOM change. 06/19 1.4PVR

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR 3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0

5 4
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Date: Saturday, July 18, 2009
1
Sheet 45 of 45