Deberjeet Usham 2K21/VLS/05 Exp No.

Experiment No. 9 3 bit parity checker

AIM:
To Design 3 Bit Even Parity checker using Dataflow ,Behvioural and Structural Modelling
APPARATUS REQUIRED:

 PC with Windows OS
 XILINX Vivado

THEORY:
The 3 bit parity checker is a combinational logic circuit that takes in an input of 3 bits and checks
the parity of the input. If the input number is of even parity( meaning the number of ones is
even), the output gives a logic high otherwise zero.

Functional Table:

A B C OUT
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

As seen from the truth table, in this even parity checker,  if the number of 1’s in the input are
even, the output is 1 .  If the number of 1’s in input is odd, the output is 0.  By closely observing
the truth table, it can be understood that the output expression can be given as
OUT= A xor B xnor C

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Deberjeet Usham 2K21/VLS/05 Exp No.9

Verilog Code for 3 Bit Even Parity checker Using Dataflow Modelling

Simulation Results

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Deberjeet Usham 2K21/VLS/05 Exp No.9

RTL Schematic Representaion for 3 Bit Even Parity Checkerusing Dataflow Modelling

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Deberjeet Usham 2K21/VLS/05 Exp No.9

Verilog Code for 3 Bit Even Parity checker Using Behavioural Modelling

Simulation Results

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Deberjeet Usham 2K21/VLS/05 Exp No.9

RTL Schematic Representaion for 3 Bit Even Parity Checkerusing Behavioural Modelling

Verilog Code for 3 Bit Even Parity checker Using Structural Modelling
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Deberjeet Usham 2K21/VLS/05 Exp No.9

Simulation Results

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Deberjeet Usham 2K21/VLS/05 Exp No.9

RTL Schematic Representaion for 3 Bit Even Parity Checkerusing Structural Modelling

RESULT:
The 3 Bit Even Parity Checker was implemented successfully using behavioural modeling,
structural modeling and dataflow modeling