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❖ Encode 03
❖ Decoder 04
❖ Multiplexer 06
❖ DE multiplexer 08
❖ Comparator 10
❖ Adder 12
❖ Parallel Adder 14
❖ Register 20
❖ Encoder
The code which is has Infinity input and output depend on input .One input goes go on at a time. Therefore,
the encoder encodes 2m input lines with ‘n’ bits. It is optional to represent the enable signal in
encoders.
4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block diagram of 4 to 2
Encoder:
Figure:4x2
Encoder
At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output. The Truth table of 4 to 2 encoder is shown below:
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Application of Encoder:
⮚ Purpose of monitoring or controlling motion parameters such as speed, rate, direction, distance or position.
❖ Decoder
Decoder is a combinational circuit that change a code into a set of signal. It’s reverse of encoder.
The equation is n = 2n
2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block diagram of 2 to 4
decoder is shown in the following figure.
Figure: 2 to 4 Decoder
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One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’. The Truth
table of 2 to 4 decoder is shown below:
Inputs Outputs
A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Y3=A1.A0
Y2=A1.A0′
Y1=A1′.A0
Y0=A1′.A0′
Application of Decoder:
❖ Multiplexer
Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection lines and
single output line. One of these data inputs will be connected to the output based on the values of
selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So,
each combination will select only one data input. Multiplexer is also called as Mux.
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The
block diagram of 4x1 Multiplexer is shown in the following figure:
One of these 4 inputs will be connected to the output based on the combination of inputs present
at these two selection lines. Truth table of 4x1 Multiplexer is shown below:
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit
diagram of 4x1 multiplexer is shown in the following figure.
⮚ Communication system
⮚ Computer memory
⮚ Telephone number
⮚ Satellite
⮚ Graphics Controller
⮚ Waveform generator.
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❖ De-Multiplexer
De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has
single input, ‘n’ selection lines and maximum of 2n outputs. The input will be connected to one of
these outputs based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So,
each combination can select only one output. De-Multiplexer is also called as De-Mux.
The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of
selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below:
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit
diagram of 1x4 De-Multiplexer is shown in the following figure.
Application of De Multiplexer:
❖ Comparator
A comparator is a device that compares two voltages or currents and outputs a digital signal indicating
which is larger.
S0 S1 X1 X2 X3
1 0 1 0 0
A parity bit, or check bit, is a bit added to a string of binary code to ensure that the total number of 1-bits in the
string is even or odd.
There are two types of parity bit generators based on the type of parity bit being generated.
Priority Bit Generator 2 types:
P=W′X′Y+W′XY′+WX′Y′+WXY
E= (W⊕X) ⊕ (Y⊕P)
Truth Table:
A B E
0 0 0
0 1 1
1 0 1
1 1 0
The following figure shows the circuit diagram of even parity checker:
Assume a 3-bit binary input, WXY is transmitted along with odd parity bit, P. So, the resultant
word (data) contains 4 bits, which will be received as the input of odd parity checker.
The same procedure of an even parity checker for implementing an odd parity checker. The circuit
diagram of odd parity checker is shown in the following figure.
Half Adder:
A half adder is used to add two binary digits together, A and B. It produces S, the sum of A and B,
and the corresponding carry out C. Although by itself, a half adder is not extremely Useful, it can be
used as a building block for larger adding circuits (FA). One possible
Implementation is using two AND gates, two inverters, and an OR gate instead of a XOR gate
as Shown in Fig.
Half
AS
Adder
BC
Truth Table:
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
C= A.B
Full Adder:
A full adder is a combinational circuit that performs the arithmetic sum of three bits: A, B
and a carry in, C. In the case of the half adder, the full adder produces the corresponding sum, S, and a carry
out C. As mentioned previously a full adder designed by two half adders in series as shown below in:
Figure:
Full Adder
SUM = (A ⊕ B) ⊕ C in C= A.B + C in (A ⊕ B)
A B C in S C out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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Parallel Adder:
A single full adder performs the addition of two one bit numbers and an input carry. But a Parallel Adder is a
digital circuit capable of finding the arithmetic sum of two binary numbers that is greater than one bit in length by
operating on corresponding pairs of bits in parallel
A = A3 A2 A1 A0
B = B3 B2 B1 B0
Sum S = A B C
Carry C = AB+BC+CA
Boolean expression dealing with the full adder. The Propagate P and generate G in a full-adder, is given as: Pi = Ai
⊕ Bi Carry propagate Gi = AiBi Carry generate Notice that both propagate and generate signals depend only on the
input bits and thus will be valid after one gate delay.
The new expressions for the output sum and the carryout are given by:
Pi = Ai ⊕ Bi
Gi = AiBi
So Sum S = Ai ⊕ Bi ⊕ Ci
Carry C = Ai.Bi.Ci
Difference between normal adder and carry look Adder:
Normal Adder Can Add 2 input and 1 Carry Look Adder Can Add multiple bit
carry bit as like Parallel adder.
Application of Adder:
Flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is
a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control
inputs and will have one or two outputs. It is the basic storage element in sequential logic.
NAND gate Latch:
0 0 No Change
0 1 0 (Reset)
1 0 1 (Set)
1 1 Invalid
SR Flip Flop:
SR flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, SR
latch operates with enable signal. The circuit diagram of SR flip-flop is shown in the
following figure.
This circuit has two inputs S & R and two outputs Q & Q’. The operation of SR flip flop is similar to
SR Latch. But, this flip-flop affects the outputs only when positive transition of the clock signal (E)
Calk(E)
0 0 Q
0 1 0
1 0 1
1 1 ID
J k Flip flop:
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock transitions or
negative clock transitions. The circuit diagram of JK flip-flop is shown in the following figure.
This circuit has two inputs J & K and two outputs Q & Q’. The operation of JK flip-flop is similar to
SR flip-flop. SR flip-flop for 4 combinations of inputs.
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Calk(E)
0 0 Q
0 1 0
1 0 1
1 1 Toggle
D flip-flop:
D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, D
latch operates with enable signal. That means, the output of D flip-flop is insensitive to the
changes in the input, D except for active transition of the clock signal. The circuit diagram of D
flip-flop is shown in the following figure.
Figure: D flip flop
This circuit has single input D and two outputs Q (t) & Q (t)’. The operation of D flip-flop is similar
to D Latch. But, this flip-flop affects the outputs only when positive transition of the clock signal is
applied instead of active enable.
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0 0 Storage
1 1 Toggle
SR flip flop is single stage flip flop JK flip flop is multistage flip flop
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❖ Register
Flip-flop can store one-bit of information. In order to store multiple bits of information, we require
multiple flip-flops. The group of flip-flops, which are used to hold (store) the binary data is known
as register.
Based on Operation:
1. Shift Register.
2. Storage register.
Shift register:
The shift register, which allows serial input and produces serial output is known as Serial In –
Serial out (SISO) shift register. The block diagram of 4-bit SISO shift register is shown in the
following figure: