Dual-phase Charge-based Capacitance Measurement

Technique

Himanshu Joshi and Kalpesh Vaghasiya Thomas Matthews

Micron Technology, Inc. Dept. of Electrical and Electronics Engineering
Boise, ID, USA. California State University, Sacramento
Sacramento, CA, USA.

Abstract—A dual-phase charge-based capacitance
measurement technique enables accurate measurement of
interconnect parasitic capacitances on integrated circuits (ICs)
via a simple test structure. This measurement technique
models the capacitor under test as having an unknown
parasitic capacitance to the substrate (ground) at each
terminal. The technique significantly reduces the effect of these
terminal capacitances on the measurement of the capacitor
under test, even if they are mismatched. The measurement
setup is very simple and does not require any reference
capacitor. Another advantage is that the capacitor under test is
not required to have a grounded terminal.
coupling parasitic capacitance between two adjacent metal
lines on the same metal layer. Both of the zero-shoot-
through inverters are exactly identical in every manner.
Zero-shoot-through function is obtained by the application
of non-overlapping input pulses at the gate terminals of all
four transistors of the test structure. Non-overlapping input
pulses ensure that for each zero-shoot-through inverter, only
one of the transistors is on at any given time. Thus, inverter
shoot-through current is eliminated.

I. INTRODUCTION
The ability to accurately measure parasitic capacitances
on modern integrated circuits (ICs) is becoming increasingly
important as silicon process technologies shrink.
Interconnect capacitance characterization is an important
aspect of current and future process development as well as
circuit design [1]. While parasitic capacitances due to CMOS
transistor terminals are substantial, those due to metal
interconnects are on the rise. Smaller chips require more
metal layers with dense metal routing on each layer. This is
continually increasing the interlayer parasitic capacitances
between metal layers, as well as coupling parasitic
capacitances between adjacent metal lines on the same metal
layer. Various techniques can characterize these interconnect
parasitic capacitances. Some of the drawbacks of other
techniques include the need for a reference capacitor and/or Figure 1. Basic test structure
the need for a complex test structure design and
measurement setup [2], [3], or the requirement that the Fig. 2 shows the test structure with an unknown parasitic
capacitor under test must have a grounded terminal [1]. capacitance to substrate (ground) connected to each plate of
the capacitor under test. These additional terminal
capacitances include the layout parasitic capacitances that
II. TEST STRUCTURE we wish to distinguish from the capacitor under test. Non-
The proposed test structure is shown in Fig. 1. The overlapping input pulses drive the test structure in two
capacitor under test is driven by zero-shoot-through different modes of operation. In one mode, the zero-shoot-
inverters at each terminal. The capacitor under test can be an through inverters are driven in-phase; in the other mode,
interlayer parasitic capacitance between two metal layers or they are driven out-of-phase.
between a metal layer and the substrate. It can also be a

0-7803-9197-7/05/$20.00 © 2005 IEEE. 1000


Figure 2. Test structure with terminal capacitances added
Fig. 3 shows basic non-overlapping input pulses, VP1 and
VP2. The zero-shoot-through inverters are driven in-phase
when the gate terminal of the PMOS transistor of each
inverter is driven by the input pulse VP1 and the gate
terminal of the NMOS transistor of each inverter is driven
by the input pulse VP2. The zero-shoot-through inverters
are driven out-of-phase by the application of the input
pulses shown in Fig. 4. Input pulses VP1, VP2, VP3, and
VP4 drive the gate terminals of transistors M1, M2, M3 and
M4 respectively.
Figure 3. Basic non-overlapping pulses that drive the inverters in-phase
Figure 4. Non-overlapping pulses that drive the inverters out-of-phase
1001
When the zero-shoot-through inverters are driven out-of-
phase, a pair of transistors–comprised of a PMOS transistor
and an NMOS transistor from different inverters–turn on.
The other pair of transistors remains off during this time,
ensuring no shoot-through current through either of the
inverters. Later during the cycle, the pair of transistors that
initially remained off turns on. The pair that was initially on
turns off, ensuring no shoot-through current through either of
the inverters. There is a net change in charge for all three
capacitors during this mode of operation [4].
III. MEASUREMENT & RESULTS
The charge-based measurement technique relates the
average current supplied to the inverters to the frequency of
the clock and the value of its load capacitance. As a result,
this technique only requires measurement of an average DC
current over a period of time. An ammeter can be used to
measure the average charging current at the source terminal
of the PMOS transistors, or alternatively, the average
discharging current at the source terminal of the NMOS
transistors.
When the zero-shoot-through inverters are driven in-phase,
the average currents measured at the source of the PMOS
transistors represent charge due only to the terminal
capacitances C2 and C3. When the zero-shoot-through
inverters are driven out-of-phase, the average currents
measured at the source of the PMOS transistors represent
charge due to the terminal capacitances C2 and C3 as well as
the capacitor under test. The currents measured during the
in-phase mode ( I IP ) and the out-of-phase mode ( I OP ) can
be used to calculate the value of the capacitor under test
using the formulas below.
I AV = I OP − I IP (1)
 I 
C =  AV  (2)
 VDD * f 
I AV is the average current representing the charge due to
the capacitor under test since the charge due to the terminal
capacitances is removed. The proposed test structure was
simulated using SPICE. It was also laid out in the MOSIS
AMI 0.6µm process technology. Layout verifications,
parasitic extraction, and post-parasitic extraction
simulations were carried out. The proposed technique was
found to be practically realizable on an IC.
Table 1 presents calculated values of a capacitor under test
at different frequencies with matched as well as unmatched
values of terminal capacitances C2 and C3.
 TABLE I. MEASURED VALUES FOR A 20FF CAPACITOR UNDER TEST AT DIFFERENT FREQUENCIES AND TERMINAL CAPACITANCE VALUES

Calculated Capacitance Value (fF)

Terminal Capacitor Terminal
Capacitance under Test C1 Capacitance At frequencies of…
C2 (fF) (fF) C3 (fF) 14.28 10.00 5.55 3.33 2.00
MHz MHz MHz MHz MHz
2 20 2 20.09 19.56 19.40 19.24 19.24
4 20 4 20.26 20.45 19.94 19.79 19.78
2 20 4 20.27 20.15 19.57 19.48 19.48
2 20 10 20.72 20.69 20.13 19.94 19.94
20 20 20 20.76 20.43 20.63 20.25 20.25

A 20fF capacitor under test was measured using the
presented technique with an average error of
±1.7 percent across the frequency range of 2.00 to 14.28
MHz. It can be said that with minimal effect of the terminal
capacitances, the capacitor under test can be calculated using
the presented measurement technique.
IV. CONCLUSION
The dual-phase charge-based capacitance measurement
technique presented in this paper significantly reduces the
effect of the terminal capacitances on the measurement of the
capacitor under test, even if they are mismatched. The
technique has a very simple measurement setup; a reference
capacitor is not necessary. Also, the capacitor under test is
not required to have a grounded terminal. If the drive signals
for the inverters are supplied off-chip, the compactness of the
presented test structure makes it an ideal candidate for scribe
line implementation. The presented technique can also
provide a rough estimate of the value of the terminal
capacitances at each plate of the capacitor under test.
REFERENCES
[1] Dennis Sylvester, James C. Chen, and Chenming Hu, “Investigation
of Interconnect Capacitance Characterization Using Charge-based
Capacitance Measurement (CBCM) Technique and Three-
Dimensional Simulation,” in IEEE Journal of Solid-State Circuits,
vol. 33, no. 3, Mar. 1998.J. Clerk Maxwell, A Treatise on Electricity
and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68–73.
[2] A. Khalkhal and P. Nouet, “On-chip Measurement of Interconnect
Capacitances in a CMOS Process,” in Proc. IEEE 1995 Int.
Conference on Microelectronic Test Structures, vol. 8, Mar. 1995.
[3] G.J. Stanton and I.G. Daniels, “Efficient Extraction of Metal Parasitic
Capacitances,” in Proc. IEEE Int. Conf. on Microelectronic Test
Structures, vol. 8, Mar. 1995.
[4] Himanshu Joshi and Kalpeshkumar Vaghasiya, “Dual-phase Charge-
based Capacitance Measurement Technique” in EEE 500 project
report at the California State University, Sacramento, May 2005.

1002