204 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO.
2, MAY 1998
An On-Chip, Interconnect
Capacitance Characterization Method
with Sub-Femto-Farad Resolution
James C. Chen, Student Member, IEEE, Dennis Sylvester, Student Member, IEEE, and Chenming Hu, Fellow, IEEE
Abstract— A simple, accurate method of measuring intercon-
nect capacitances is presented. The test structure has excellent
resolution, needs only DC measurements, and is compact enough
for scribe-line implementation. These qualities make it suitable
for measurement-based, interconnect capacitance characteriza-
tion in a comparable fashion to current characterization efforts
for MOSFET devices. The entire characterization scheme is
demonstrated for a production 0.5-m, three-level metal tech-
nology. The method not only provides an accurate assessment of
actual capacitance variation but provides valuable feedback on
the variability of physical parameters such as interlevel dielectric
(ILD) thickness and drawn width reductions for process control
as well.
Index Terms— Capacitance measurement, integrated circuit
interconnections, modeling, monitoring, test structures.
I. INTRODUCTION
T HE RECENT trend toward interconnect performance
characterization has been brought about by the fact that
modern circuits are increasingly laden with more metal layers
as well as more routing within each layer. Interconnect ca-
pacitances, particularly, have received more than their share
of the attention. Past techniques have relied on either a
reference capacitor [1], a complicated test-structure design [2]
or measurement setup [3], [4], and poor resolution capabilities.
In this paper, we will introduce a new test structure that
alleviates the above problems. This interconnect capacitance
characterization scheme is called charge-based capacitance
measurement (CBCM). We will show that CBCM’s ability
to easily collect capacitance data makes it an ideal candi-
date for use in process monitoring. Specifically, CBCM test
structures can be used to collect capacitance data for inter-
connect parameter (i.e., interlevel dielectric (ILD) thicknesses
and CD’s) extraction in much the same manner as current
device test structures are used for I–V data measurement and
SPICE model parameter characterization (Fig. 1). This overall
capability provides a new level of interconnect capacitance
modeling accuracy.
II. TEST STRUCTURE AND MEASUREMENT SCHEME
The test structure consists of a pair of NMOS and PMOS
Manuscript received September 24, 1997; revised November 28, 1997.
The authors are with the Department of Electrical Engineering and
Computer Science, University of California, Berkeley, CA 94720-1772
USA (e-mail: jamesc@eecs.berkeley.edu; dennis@eecs.berkeley.edu;
hu@eecs.berkeley.edu).
Publisher Item Identifier S 0894-6507(98)02931-5.
0894–6507/98$10.00  1998 IEEE
transistors. Fig. 2 shows two such test structures. The structure
on the left is identical to the one on the right in every manner
except that it does not include the target capacitance to be
characterized. For example, if a single Metal 1 to Metal 2
overlap capacitance is to be measured, the left structure of
Fig. 2 should not include this overlap configuration.
The left and right structures are both driven by two nonover-
lapping signals and as shown in Fig. 3. These can be
either generated off-chip or on-chip. The purpose of these
nonoverlapping waveforms is to ensure that only one of the
two transistors on either the left or right side is conducting
current at any given time. When the PMOS transistor turns
on, it will draw charge from to charge up the target
interconnect capacitance. This amount of charge will then be
subsequently discharged through the NMOS transistor into
ground. An ammeter can be placed at the source of the
PMOSFET (or, alternatively at the source of the NMOSFET)
to measure this charging current. The actual waveform of this
charging current is not important—only its DC or average
current value needs to be measured. DC current can be
easily obtained from any modern current meter. The difference
between the two DC current values is used to extract the target
interconnect capacitance as shown by
(1)
(2)
In order to extract capacitance values, can be plotted
as a function of for specific frequency values (see Fig. 4).
Referring to (2), the value of can then be extracted by di-
viding the slope of the fitted line by the appropriate frequency
value. (Alternatively, can also be plotted as a function of
frequency for specific values of If multiple frequencies
are used, an average of all the capacitance values is then taken
to be the final extracted capacitance value.
From (2), it appears that the value of can be simply
obtained from a single pair of and frequency values. This
calculation scheme is too sensitive to equipment inaccuracies
and should not be used. For example, if the voltage source
has an error of 5%, this simplified calculation scheme would
also yield a capacitance value that has an error of 5%. If
capacitance is instead calculated from the slope of (2), it then
relies on the relative change of given a to a change in
This source of error is almost completely eliminated.
Since only DC currents are measured from the left and right
nodes of Fig. 2, all other input pads and
CHEN et al.: INTERCONNECT CAPACITANCE CHARACTERIZATION METHOD 205

Fig. 1. Interconnect characterization should parallel in strategy with present efforts for device characterization.

Fig. 3. The nonoverlapping signals ensure that no short-circuit current is

0
present. It is important to ensure that t2 t3 is large enough to charge the
target capacitance.

Fig. 2. CBCM test structure. The left and right test structures are identical
in every manner except for the target capacitance to be measured.

ground) can be shared between multiple test structures. In

fact, only one unique pad is needed for each test structure.
This efficient layout pattern is also helped by the fact that
CBCM has very fine resolution, can measure small capaci-
tances, which translates into savings in layout area. Given the
many possible combinations interconnect patterns, CBCM can
integrate many test structures in a given amount of space. This
makes it attractive for scribe-line implementations.

III. RESOLUTION LIMIT

The resolution limit of the proposed method resides mainly
in the mismatch of the drain junction and overlap capacitances
Fig. 4. Interconnect capacitance can be extracted from the slope. This
between the left and right test structures of Fig. 2. The method allows the extracted value to be insensitive to errors in the Vdd
measured DC current for the test structure with and without source supply.
the target interconnect capacitance is given by

(3) parasitic capacitances, due to and matching. This

(4)
is the unknown capacitance to be measured and is
the MOSFET gate to drain overlap capacitance plus drain
junction capacitance plus any other parasitic capacitances.
If the two structures are perfectly matched, the term
would be completely subtracted out and would not impose
a resolution limit. In reality, there is mismatch between the
value is uniquely determined by the process technology.
In order to minimize this error, the W/L sizes of the NMOS
and PMOS transistors should be drawn with dimensions that
are optimal for achieving precise matching characteristics.
We recommend and not equal to
To determine the degree of mismatch for any technology,
Fig. 2 should be modified to have two, identical, unloaded test
structures. The measured difference in current between the two
206 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 2, MAY 1998

Fig. 6. Interlayer capacitance between M 2 and the substrate. Two capaci-

Fig. 5. Additional capacitance for an isolated wire due to the presence of a
2
nearby line. The dimensions of each wire is 135 m 1.5 m 2 1 m.
tance components can be easily determined.

sources can then be used to determine the mismatch in

via (2). For a production, 0.5- m three-level technology, this
mismatch was determined to be 0.016 fF or 16 aF.
Lastly, some important comments about achieving the best
resolution limit with the proposed CBCM test structure. First,
it is necessary to measure the currents and with the same
ammeter. This is to avoid the mismatch between different
ammeters should two be used to measure these DC currents.
Second, if one ammeter is used, it is important to note that
the subtraction scheme [i.e., (1)] as well as the the extraction
strategy (i.e., Fig. 4) of this test structure provide robust
protection against possible measurement errors from the single
ammeter. For example, if all current values are in error
by the slope of Fig. 4 is unaffected. The final, extracted
capacitance value is also unaffected. Both these observations
Fig. 7. CBCM and three-dimensional (3-D) EM simulator (RAPHAEL)
make CBCM unique and different from similar test structures agree on the saturating effect of this test structure. Error bars represent limits
proposed in the past [5]. of RAPHAEL simulation results due to ILD variations.

IV. CHARACTERIZATION FLEXIBILITY fringing and area components. The

CBCM can be used to directly measure the capacitance of
many different interconnect geometries. To demonstrate this
a test chip was designed in a production 0.8 m double
metal technology with many interconnect test structures. One
of these structures was a single overlap between Metal 1 and
Metal 2 with an area of 1.5 m 1.5 m or 2.25 m (Fig. 2).
The proposed measurement/extraction scheme (Figs. 3 and 4)
was used and yielded an average capacitance value of 0.4431
fF. The error for this value was 0.5%.
This technique was also applied to characterize the crosstalk
capacitance between two parallel Metal 2 lines (each 135
m long) as a function of their separation distance, over
silicon substrate. Fig. 5 shows the increase in total capacitance
due to the presence of a nearby metal line. Results from
RAPHAEL [6] simulations are also included. Both show a
dependence.
Next, the interlayer capacitance between Metal 2 and the
silicon substrate was measured as a function of drawn width
(Fig. 6). Assuming a simple parallel plate model as in (5), a
straight line can be drawn through these points to extract the
(5)
difference between measured and simulated results are pri-
marily the result of ILD thickness variation and linewidth
reduction. Both of these issues will be addressed in Section V.
Lastly, a unique interlayer capacitance structure between
Metal 1 and Metal 2 was characterized (Fig. 7). A long, fixed
length of Metal 2 was placed over constant width strips of
Metal 1. The spacing between these strips was subsequently
varied. The result reveals a saturating effect as the spacings
between the Metal 1 strips became smaller (i.e., more
strips under This suggests that a dense array of Metal
1 strips behaves as if it were a continuous plate. To see
whether this interpretation was correct, the same structures
were simulated. A saturating effect can again be seen, thus
verifying our assumptions.
While both methods displayed the same saturating effect,
they differ in predicting when this effect occurs. This dis-
crepancy highlights a difficulty in performing interconnect
simulations. It is difficult to generate precise input files due to
CHEN et al.: INTERCONNECT CAPACITANCE CHARACTERIZATION METHOD
Fig. 8. Example of how measured capacitance values from CBCM can be
1
used to extract interconnect parameters such as ILD thickness and W; drawn
width reduction.
the variance of ILD thicknesses and other physical intercon-
nect parameters. This variance can be said to be comprised
of random and deterministic components. The former can
attributed to the stochastic nature of semi-conductor equipment
and processing conditions. The latter can be described by the
fact that ILD thicknesses increase as the spacings between
parallel metal lines decrease (and vice versa). In order for the
simulator to account for these observations, the ILD thickness
(between and was varied at the extremes according
to process specifications. The results are denoted by the error
bars in Fig. 7. It is reassuring to note that the measured results
(CBCM) fall within the process specifications. Nonetheless,
this example points to the importance of measured data pro-
vided by CBCM. ILD thickness variations, if present, are
implicitly included in all measurements.
V. APPLICATION TO INTERCONNECT PARAMETER EXTRACTION
As we have shown, the ability to provide accurate sim-
ulation parameter values is critical for simulation results to
match those of measured data. For interconnect simulation
this means proper ILD thicknesses, CD (i.e., width reduction),
and metal height specifications. The extraction of these values
should parallel the current practice for SPICE model parameter
extraction for MOSFET devices (Fig. 1). Measured data, here
obtained from CBCM, is used to extract interconnect param-
eters. When simulated, these should reproduce the measured
data to within a certain degree of accuracy.
This kind of interconnect characterization scheme (measure-
ment, extraction, and simulation) is unique in many ways.
First, it permits efficient extraction of various interconnect
parameters without the use of SEM’s. Second, the ease with
which these extracted parameters can be obtained allows them
to be used for process monitoring and critical dimension
control. Third, the resulting extracted parameters automatically
“tune” the simulator to reflect actual, silicon data. Once
this is done, the simulator can be used to more accurately
simulate other, more specific interconnect geometries to either
formulate interconnect models [7], [8] or generate interconnect
capacitance databases for full chip parasitic extraction [9].
207
TABLE I
CBCM MEASURED RESULTS FOR ALL COMBINATIONS OF INTERLAYER
CAPACITANCES FOR A 0.5-m; THREE-LEVEL METAL PRODUCTION TECHNOLOGY.
(a) Carea RESULTS AND (b) Cfringe RESULTS. FIRST ROW DENOTES IDENTITY
OF TOP PLATE. ALL UNITS ARE aF=m2 AND aF=m; RESPECTIVELY
(a) (b)
One example of an extraction scheme is shown in Fig. 8
for characterizing interlayer metal capacitances. The required
data consists of measured capacitances for a wide and narrow
test structure (denoted by and respectively in Fig. 6).
ILD thickness and width reduction, parameters will
be extracted. The exact interlayer capacitance structure will
duplicated in the simulator. The extraction process progresses
as follows. First, nominal process values are used to initialized
the two interconnect parameters. Second, since a wide test
structure is more sensitive to changes in ILD than it will
be used to extract the ILD value. The extracted ILD value
will be the value which yields a simulated capacitance value
equal to that of the measured capacitance of the wide structure.
This intermediate ILD value is then used in the simulation
and extraction of for the measured narrow test structure.
This newly determined value, along with the previously
determined ILD thickness, is next used to simulate the wide
structure again. If the error between measured and simulated
value is within a user-specified threshold, the extraction se-
quence is completed. Otherwise, it continues again with the
re-extraction of ILD for the wide structure starting with the
ILD and values of the previous extraction step.
Other interconnect parameters such as metal heights and
dielectric constants were not extracted in the example ex-
traction sequence. Metal height was not extracted because its
sensitivity to interlayer capacitance is not as significantly as
ILD and (i.e., the metal height would have to change
quite substantially in order to achieve the same amount of
capacitance perturbation from a slight change in ILD thick-
ness). Erroneous values for metal heights would ensue if we
blindly included it in the extraction scheme. These comments
would not be true if the characterization effort was targeted at
modeling a different capacitance (i.e., the crosstalk capacitance
between two parallel wires) where the impact of metal height
is more significant. Similarly considerations hold for the di-
electric constant of SiO It was not extracted due to its known
process uniformity. Although it is possible to change dielectric
208 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 2, MAY 1998

(a) (b)
1 2 1
Fig. 9. Extracted ILD and W results for M to M interlayer capacitances. ILD results tend to conform to process specs better than 1 W: Results
can be used as valuable process feedback information.

values instead of ILD or during the extraction process, the Five measured capacitance values for each interlayer com-
results would not be a realistic reflection of the actual source bination were plotted as a function of their drawn widths. A
of variability. Overall, the determination of which interconnect best fit line was drawn through these points, as in Fig. 6, to
parameters are to be extracted requires a careful examination obtain and values. Table I shows the results. The
of the test structure design and the identification of which measured mean is listed together with the fab value. Since 25
physical quantity is most likely to be responsible for the dies of this test chip were available, a sigma value was also
measured interconnect capacitance variation. calculated.
Overall, the results match closely with those given by the
fab (only was available for this comparison). The sigma
VI. RESULTS for was also rather small in comparison to the mean
As a demonstration of the entire CBCM measurement, value. This probably denotes that ILD thicknesses are rather
extraction and simulation scheme, a test chip was design in well controlled. The spread for however, was slightly
a production 0.5- m three-level metal process. One of the larger. Again, ILD variation is one of the causes. In addition,
goals of this test chip was to determine the actual spread of variation can also cause the value to vary. This can be
all possible interlayer capacitances and as well visualized from Fig. 6. If each width was offset by then
as the extent of variation for their corresponding interconnect the intercept (i.e., would change. It is also important
parameters (ILD and to note that only 25 samples were taken to calculate each
With three levels of metal plus one polysilicon layer, there sigma value. Since the confidence level for the estimate of
are ten possible combinations of interlayer capacitances. The sigma decreases with the with being the number
results are listed in Table I. To determine and of samples, a larger sample size would yield more useful
components for each interlayer combination, a set of five information.
test structures with different widths for the top interlayer A comment should be made with regards to the magnitude
capacitance plate was designed. An additional reference test of and values in relation to the resolution limit.
structure with a zero width was also designed for each set [this For example, the value of 25.6 aF m for to
is the structure for measuring in (4)]. The bottom layer Substrate does not seem to be much bigger than the resolution
or ‘plate’ was the constant size for all test structures. The limit of 16 aF. This is misleading. The total value for
first, nonzero width structure was drawn with the narrowest this structure is aF m m aF—well
allowable width with each successive structure doubling in above the resolution limit. A similar comment can be also
width (i.e., the last width is 16 times as wide as the first one). made with respect to The measured capacitance
The length was kept constant at 50.1 m In all, a total of for to Substrate is aF m m m
six test structures were designed for each of the ten interlayer aF. The resolution limit accounts for only 2% of this value.
capacitance combinations. In its most compact form, only six The percentage for other interlayer capacitance values is even
pads are required—each node of the test structure was less.
allotted one pad—for each interlayer combination. The other The repeatability of each capacitance measurement should
four signals and ground) can be shared amongst also be examined. This is an important aspect of any measure-
all ten interlayer capacitance combinations. ment methodology and should not be overlooked. Three sepa-
CHEN et al.: INTERCONNECT CAPACITANCE CHARACTERIZATION METHOD
rate measurements on the same test structure were performed.
The percent difference between the largest and smallest capac-
itance value was less than 2%.
The cause for the observed extent of and
variation for interlayer capacitances needs to be more carefully
examined. As previously discussed, due to the design of
the capacitance test structures (essentially a parallel plate
capacitor), the most dominant parameters were determined to
be ILD and Metal height and dielectric constants were
assumed not to vary and were set to their nominal values
from the fab.
The extraction sequence of Fig. 8 was used to extract ILD
and parameters. For each interlayer combination, the
measured capacitance values for the widest and narrowest
capacitors became fitting targets. The three-dimensional (3-
D) EM simulator, RAPHAEL, was used as the simulator.
The extraction routine assures that the final extracted set of
ILD and values will fit both measured input values.
The fit for intermediate geometry widths were all found to
be excellent—within 2% error. Error less than this were also
observed. However, this is not very meaningful since the
error (or repeatability) for each of the intermediate measured
capacitance values is about 2% as mentioned above.
A complete extraction was performed for all ten interlayer
capacitances. Only the results for the to combination
are shown in Fig. 9 for all 25 dies. The extraction time depends
on the speed of RAPHAEL simulations. Typically, one set of
ILD and values took 5 min on a Sun UltraSparc 1. Those
extracted results which tend to deviate more from the nominal
values tend to take more time.
A distributive nature can be seen for each of the interconnect
parameter. In the case of extracted ILD thicknesses, the entire
distribution (except for one data point) remained within the
upper and lower process specifications. Unfortunately, this
was not the case for Roughly half of the distribution
was outside the process window. This group of data displayed
relatively large, negative values. This means that the
actual metal width increased
and the magnitude was larger than what was expected. One
plausible explanation for this technology is that a mask bias
was applied to the Metal 2 layer in order to compensate for
overetching. This compensation mask made all lines wider
by a constant amount. Unfortunately, the amount of etching
was not constant between die to die, and the end result was
that some metal lines were over-compensated. Nonetheless,
this is an effective way to gauge the amount of mask bias and
provide feedback on the process variation of the etching step
in question.
VII. CONCLUSION
We have introduced a simple, accurate method of measuring
interconnect capacitances. The test structure has excellent
resolution, needs only DC measurements, and is compact
enough for scribe-line implementation. These qualities make
it suitable for measurement-based, interconnect capacitance
209
characterization. The entire characterization scheme from test
structure design to measurement to interconnect capacitance
extraction is demonstrated for a production 0.5- m three-level
metal technology. The method not only provides an accurate
assessment of actual capacitance variation but provides valu-
able feedback on the variability of physical parameters such
as ILD thicknesses and drawn width reductions for process
control as well.
REFERENCES
[1] C. Kortekaas, “On-chip quasistatic floating gate capacitance,” in Proc.
IEEE 1990 Int. Conf. on Microelectronic Test Structures, vol. 3, Mar.
1990.
[2] P. Nouet and A. Toulouse, “A new test structure for interconnect capac-
itance monitoring,” in Proc. IEEE 1997 Int. Conf. on Microelectronic
Test Structures, vol. 10, Mar. 1997.
[3] J. B. Shyu, G. C. Temes, and F. Krummenacher, “Random effects
in matched MOS capacitors and current sources,” IEEE J. Solid State
Circuits, vol. SC-19, Dec. 1984.
[4] G. J. Gaston and I. G. Daniels, “Efficient extraction of metal parasitic ca-
pacitances,” in Proc. IEEE Int. Conf. on Microelectronic Test Structures,
Mar. 1995, vol. 8.
[5] B. Laquai, H. Richter, and B. Hofflinger, “A new method and test
structure for easy determination of femto-farad on-chip capacitances in a
MOS process,” in Proc. IEEE Int. Conf. Microelectronic Test Structures,
Mar. 1992, vol. 5.
[6] RAPHAEL Ver. 4.0, Avant! Corporation, 1997.
[7] N. D. Arora, K. V. Raol, R. Schumann, and L. M. Richardson,
“Modeling and extraction of interconnect capacitances for multilayer
VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 58–67,
Jan. 1996.
[8] T. Sakurai and K. Tamaru, “Simple formulas for twoand three-
dimensional capacitances,” IEEE Trans. Electron Devices, vol. ED-30,
Feb 1983.
[9] S. Y. Oh, K. Okasaki, J. Moll, N. S. Nakagawa, K. Rahmat, and N.
Chang, “3D GIPER: Global interconnect parameter extractor for full-
chip global critical path analysis,” in Proc. IEEE Int. Electron Devices
Meeting, Dec. 1996.
James C. Chen (S’96) received the B.S. and M.S degrees (high honors) in
electrical engineering and computer science from the University of California,
Berkeley, in 1993 and 1995, respectively. Since 1995, he has been pursuing
his Ph.D. studies at UC-Berkeley and plans to graduate by May 1998.
He has interned with Hewlett-Packard and Hyundai Electronics. His re-
search interests lie in the area of statistical modeling with emphasis on
deep-submicron MOSFET’s and metal interconnects for process optimization
and improving circuit functional yields.
Mr. Chen is a member of Tau Beta Pi and Eta Kappa Nu.
Dennis Sylvester (S’96) received the B.S. degree in electrical engineering
(summa cum laude) from the University of Michigan, Ann Arbor, in 1995 and
the M.S. degree in electrical engineering from the University of California,
Berkeley in 1997. He is currently pursuing the Ph.D. degree at UC-Berkeley.
His research interests include interconnect characterization and modeling,
on-chip crosstalk, and CMOS delay modeling.
Mr. Sylvester is a 1997 Semiconductor Research Corporation Graduate
Fellow.
210 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 2, MAY 1998

Chenming Hu (S’71–M’76–SM’83–F’90) received

the B.S. degree from the National Taiwan Uni-
versity, Taipei, Taiwan, R.O.C., and the M.S. and
Ph.D. degrees in electrical engineering from the
University of California, Berkeley, in 1970 and
1973, respectively.
From 1973 to 1976, he was an Assistant Pro-
fessor at Massachusetts Institute of Technology,
Cambridge. In 1976, he joined the University of
California, Berkeley, as Professor of Electrical En-
gineering and Computer Sciences. He is also the
Director of Industrial Liaison Program. While on industrial leave from
the university in 1980 and 1981, he was Manager of nonvolatile memory
development at National Semiconductor. Since 1973, he has served as a
consultant to the electronics industry. He has also been an advisor to
many government and educational institutions. His present research areas
include VLSI devices, silicon-on-insulator devices, hot electron effects, thin
dielectrics, electromigration, circuit reliability simulation, and nonvolatile
semiconductor memories. He has also conducted research on electro-optics,
solar cells, and power electronics. He has been awarded several patents on
semiconductor devices and technology. He has authored or coauthored three
books and over 400 research papers. He has delivered dozens of keynote
addresses and invited papers at scientific conferences. He serves on the
editorial board of Semiconductor Science and Technology, Institute of Physics,
U.K.
Dr. Hu is an Honorary Professor of Beijing University, China, of Tsinghua
University, China, and of the Chinese Academy of Science. He has been a
guest editor of PROCEEDINGS OF THE IEEE and of the IEEE TRANSACTIONS ON
ELECTRON DEVICES. He was Associate Editor of the IEEE TRANSACTIONS ON
ELECTRON DEVICES from 1986 to 1988, and Vice Chairman of IEEE Electron
Devices Society, Santa Clara Valley Chapter, from 1980 to 1982. He was the
first National Science Council Invited Chair Lecturer, R.O.C., in 1987. He
was Board Chairman of East San Francisco Bay Chinese School from 1988
to 1991. He received the 1991 Design News Excellence in Design Award and
the 1991 Semiconductor Research Corporation Technical Excellence Award
for leading the development of IC reliability simulator, BERT. He has also
received five best-paper awards. He has been listed in Who’s Who in America,
American Men and Women of Science, Who’s Who in Science and Engineering,
and Who’s Who in American Education.