Experiment # 2, Week 2, Day 3: Date: 23/01/22

Understanding Flip-Flop and Memory, Toggle state

1. Verify truth table of J-K flip flop and draw the timing diagram. Make Asynchronous up counter circuit
with IC 74LS73E and count number of pulses given into circuit. Verify your results with digital display

Student ID: MS19179 Name: Nimish Ramteke Section:

Aim of Experiment:
1. To verify truth table of JK flip flop and draw the timing
diagram.
2.To make a asynchronous up counter and display the count
on digital display.

Components Used:
7-segment common annode display, 7447 decoder, logictoggle,
logic probe, NAND gate, 7476.

Marks Viva Experiment Group discussion

Full Marks 15 75 10
Obtained Marks

1
Group
2
Members

Instructor’s Signature
 Experimental #2: Week 2: Day 3
Use only logic IC 74LS73E (JK flip flop). Verify & fill following table for JK flip flop and draw timing diagram

Fig. 1

PR (set) CLR CLOCK J K Ǫ Ǭ comment

0 1 any thing any state any state 1 0 preset
0 0 any thing any state any state 1 1 invalid
1 1 0 0 Q Q' memory
1 1 1 0 1 0 set
1 1 0 1 0 1 set
1 1 1 1 Q' Q toggle
1 1 0 any state any state Q Q' memory

Timing Diagram (PR=1, CLR=1, and last data when CLR=0)

Circuit Verified Result verified Photograph of circuit

attached
 Experimental #2: Week 2: Day 3
Use only logic IC 74LS73E (JK flip flop). Make timing diagram with a given number pulse and verify the counter
with display using 7447 IC and seven segment display

Circuit verified

Result verified

Ckt Photo took

Q1

Q2

Q3

Q4

Display
No.