This document is an internal exam for a Digital System Design course. It contains 4 questions, with 2 parts each, assessing different course outcomes. Question 1 covers basic digital logic concepts like counters and shift registers. Question 2 involves designing specific counter circuits using JK flip-flops. Question 3 requires creating state diagrams for synchronous counters that count up and down. Question 4 involves analyzing sequential circuits and developing Mealy state diagrams for modulo counters. The maximum marks are distributed across the different course outcomes assessed in the questions. Diagrams of state machines are provided for reference in the analysis questions.
This document is an internal exam for a Digital System Design course. It contains 4 questions, with 2 parts each, assessing different course outcomes. Question 1 covers basic digital logic concepts like counters and shift registers. Question 2 involves designing specific counter circuits using JK flip-flops. Question 3 requires creating state diagrams for synchronous counters that count up and down. Question 4 involves analyzing sequential circuits and developing Mealy state diagrams for modulo counters. The maximum marks are distributed across the different course outcomes assessed in the questions. Diagrams of state machines are provided for reference in the analysis questions.
This document is an internal exam for a Digital System Design course. It contains 4 questions, with 2 parts each, assessing different course outcomes. Question 1 covers basic digital logic concepts like counters and shift registers. Question 2 involves designing specific counter circuits using JK flip-flops. Question 3 requires creating state diagrams for synchronous counters that count up and down. Question 4 involves analyzing sequential circuits and developing Mealy state diagrams for modulo counters. The maximum marks are distributed across the different course outcomes assessed in the questions. Diagrams of state machines are provided for reference in the analysis questions.
Department of Electronics and Communication Engineering INTERNAL-III III Semester Course : Digital System Design Course Code : 18EC34 Date : 15/02/2021 Session : Sep 20-Feb 2021 Duration : 75 Mins. Max. Marks : 30 Note: Answer any TWO questions selecting at least ONE from each Module MODULE-1 Marks CO BTL
1. a. Explain with a neat diagram a 4-bit ripple binary counter. 6 CO1 L2
Design a clocked sequential circuit which operates according to state b. 9 CO3 L3 diagram given in Fig 1 using positive edge triggered JK flip flop. OR Explain with a neat diagram and truth table, a 4-bit parallel-in 2. a. 6 CO1 L2 unidirectional shift register. Design a modulo-6 counter, that counts 0, 2, 4, 6, 8, 10 using positive edge b. 9 CO3 L3 triggered JK flip flop. MODULE-2 Create the state diagram for a synchronous decade counter. The counter is to count up or down, in binary, depending on the value of a mode control input signal. When the mode control input M=0, the counter is to count up; 3. a. when M = 1, the counter is to count down. The counter is to repeat. The 5 CO2 L3 counter output y is to be a 1 if counting up and the terminal count is reached. Another output z is to be a 1 at the terminal count if counting down. Analyze the sequential machine given in figure 2 and derive the CO4 b. 8+2 L3 characteristics equations and develop the state diagram for the same. CO2 OR Develop the Mealy state diagram for modulo-8 counter that will count the 4. a. number of occurrences of an input; that is, the number of it is a 1. The 5 CO2 L3 input variable x must be coincident with the clock to be counted. Analyze the sequential machine given in figure 3 and derive the CO4 b. 8+2 L3 characteristics equations and develop the state diagram for the same. CO2
MAXIMUM MARKS ALLOTTED FOR
Q. No CO1 CO2 CO3 CO4 CO5 1a 6 1b 9 2a 6 2b 9 3a 5 3b 2 8 4a 5 4b 2 8 Total MARKS ALLOTED PER 6 7 9 8 CO Figure 1 Figure 2
Figure 3
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