MOS Characterization

(Small-Signal)

Lab 2 Common Source

Amplifier with Resistor Load
and Source Degeneration

A Laboratory Report Presented to

Prof. Aileen Caberos-Gumera
Faculty, DEET
College of Engineering and Technology, MSU-IIT

Submitted By:
Christian Allan G. Lumakin

In Partial Fulfillment for the course

ECE 130 - Introduction to Analog Integrated Circuit Design
 INTRODUCTION
Common-source amplifier is one of three basic single-stage field - effect
transistor amplifiers. Common-source amplifier can be used as either a transconductance
amplifier or a voltage amplifier. It can provide high power gain, medium current, and
voltage gains according to the input and output impedances. 

HSPICE codes/syntax used in this experiment

.lib – Use the following syntax for library calls

.op – Compute the DC operating points

.probe – To designate the desired value to be used

.dc – DC Sweep or Parameterized Sweep for Vdd

.alter – Used to re-run simulation with a modified netlist

.end – Last statement in the input netlist file

.tran – Transient analysis with the sampling time and total time

.tf – To calculate the following small signal characteristics

.meas – Modify information and define the results of successive simulations

 PROCEDURE AND RESULTS

Step 1: Simulate the Vin-Vout DC transfer curve and the frequency response.

Circuit simulation code: Circuit simulation code:

step1_CSAmp(DC) step1_CSAmp(AC)

m1 vout vin gnd gnd nch l=0.18u w=1u m1 vout vg gnd gnd nch l=0.18u w=1u
vdd vdd gnd dc 1.8V vdd vdd gnd dc 1.8V
vin vin gnd dc 0.5V vin vin gnd ac 1.62V
r1 vdd vout 10k vg vg vin dc 0.5V
cload vout gnd 10p ic=0 r1 vdd vout 10k
cload vout gnd 10p ic=0
.op
.dc vin 0V 1.8V 0.001V .op
.probe v(vout) .probe v(vout)
.lib 'mm018.l' TT .option post probe
.ac dec 100 10 10g
.end .plot ac vdb(vout)
.meas ac gb when vdb(vout)=0
.lib 'mm018.l' TT

.alter
vg vg vin dc 0.75V
.alter
vg vg vin dc 1V

.end
DC Analysis of Common Source Amplifier:

AC Analysis of Common Source Amplifier:

Step 2: Change the value of R in figure 4.1 and simulate the resulting waveform.

Circuit simulation code:

step2_CSAmp

m1 vout vg gnd gnd nch l=0.18u w=1u

vdd vdd gnd dc 1.8V
vin vin gnd ac 1V
vg vg vin dc 0.95V
r1 vdd vout 5k
cload vout gnd 10p ic=0

.op
.probe v(vout)
.option post probe
.ac dec 100 10 10g
.plot ac vdb(vout)
.meas ac gb when vdb(vout)=0
.tf v(vout) vin
.pz v(vout) vin
.lib 'mm018.l' TT

.alter
vg vg vin dc 0.75V
r1 vdd vout 10k
.alter
vg vg vin dc 0.70V
r1 vdd vout 20k

.end
 AC Analysis of Common Source Amplifier with different values of R:

Table 1

(W/L) = 1u / 0.18u , Cload = 10p

R(kΩ) Rout(kΩ) Vin-DC A(dB) -3dB(Hz) G.B.

(Hz)

5 4.5184 0.95 6.8 3.5M 6.9M

10 8.91 0.75 11.4 1.8M 6.4M

20 16.40 0.70 15.4 0.9M 5.7M

As seen in the table, as the R value goes up, so is the output resistance. That is
because the R or the resistive load is near the output side of the amplifier. It also
increases the gain of the common source amplifier. In which to get it the gain is
V
A= out =−gm ∙ R out =−gm∙( R∨¿ r o ) . But, the higher the R, the smaller the G.B.
V¿
which is G . B .= A ∙ BW
Step 3: Following the circuit of figure 4.5, simulate the Vin-Vout Dc transfer curve
and the frequency response.

Circuit simulation code: Circuit simulation code:

step3_CSAmp(DC) step3_CSAmp(AC)

m1 vout vin vs gnd nch l=0.18u w=1u m1 vout vg vs gnd nch l=0.18u w=1u
vdd vdd gnd dc 1.8V vdd vdd gnd dc 1.8V
vin vin gnd dc 0.83V vin vin gnd ac 1V
rd vdd vout 10k vg vg vin dc 0.83V
cload vout gnd 10p ic=0 rd vdd vout 10k
rs vs gnd 0.5k cload vout gnd 10p ic=0
rs vs gnd 0.5k
.op
.dc vin 0V 1.8V 0.001V .op
.probe v(vout) .probe v(vout)
.lib 'mm018.l' TT .option post probe
.ac dec 100 10 10g
.end .plot ac vdb(vout)
.meas ac gb when vdb(vout)=0
.lib 'mm018.l' TT

.end
DC Analysis of Common Source Amplifier with Source Degeneration:

AC Analysis of Common Source Amplifier with Source Degeneration:

Step 4: Change the value of Rs in figure 4.5 and simulate the waveforms.

Circuit simulation code:

step4_CSAmp

m1 vout vg vs gnd nch l=0.18u w=1u

vdd vdd gnd dc 1.8V
vin vin gnd ac 1V
vg vg vin dc 0.83V
rd vdd vout 10k
cload vout gnd 10p ic=0
rs vs gnd 0.5k

.op
.probe v(vout)
.option post probe
.ac dec 100 10 10g
.plot ac vdb(vout)
.meas ac gb when vdb(vout)=0
.lib 'mm018.l' TT

.alter
vg vg vin dc 0.88
rs vs gnd 1.0k
.alter
vg vg vin dc 0.93
rs vs gnd 1.5k

.end
 AC Analysis of with different value of Rs:

Table 2

(W/L) = 1u / 0.18u , Cload = 10p

Rs(kΩ) Rout(kΩ) Vin-DC A(dB) -3dB(Hz) G.B.

(Hz)

0.5 8.98 0.83 9.5 1.77M 5.0M

1.0 9.12 0.88 7.9 1.74M 4.0M

1.5 9.22 0.93 6.6 1.72M 3.3M

In this table, as the Rs increases the gain decreases, and when the gain decreases, the gain
bandwidth also decreases. With this idea, to have a higher gain is to have a smaller Rs, ideally,
the Rs should be equal or closer to 0.
Step 5: Change the value of Rs in figure 4.5 and simulate the waveforms.

Circuit simulation code:

step5_CSAmp

m1 vout vin vs gnd nch l=0.18u w=1u

vdd vdd gnd dc 1.8V
vin vin gnd dc 0.83V
rd vdd vout 10k
cload vout gnd 10p ic=0
rs vs gnd 0.0k

.op
.dc vin 0v 1.8V 0.001V
.probe i1(m1)
.lib 'mm018.l' TT

.alter
rs vs gnd 0.5k
.alter
rs vs gnd 1.0k
.alter
rs vs gnd 1.5k

.end

Ids-Vin characteristic curve with different Rs:

Step 6: Following the amplifier configuration of figure 4.11, with an input signal of
ideal sinusoidal wave with 0.05V amplitude, and frequency of 100kHz. Perform FFT
analysis to Vin to get the frequency spectrum.

Circuit simulation code:

step6_CSAmp

m1 vout vin gnd gnd nch l=0.18u w=1u

vdd vdd gnd dc 1.8V
v1 v1 gnd sin(0 0.05 100k 0 0)
vg vin v1 dc 0.83V
rd vdd vout 10k
cload vout gnd 10p ic=0

.op
.option post probe
.tran 625ns 10.24ms
.fft v(vin) start=0 stop=10.24ms np=16384
.lib 'mm018.l' TT

.end

FFT Analysis of Vin:

Step 7: Perform the FFT analysis in the circuit of figure 4.11 while changing the
value of Rs, get the frequency spectrum.

Circuit simulation code:

step7_CSAmp

m1 vout vin vs gnd nch l=0.18u w=1u

vdd vdd gnd dc 1.8V
v1 v1 gnd sin(0 0.05 100k 0 0)
vg vin v1 dc 0.83V
rd vdd vout 10k
cload vout gnd 10p ic=0
rs vs gnd 0

.op
.option post probe
.tran 625ns 10.24ms
.fft v(vout) start=0 stop=10.24ms np=16384
.lib 'mm018.l' TT
.tf v(vout)v1

.alter
rs vs gnd 0.5k
.alter
vg vin v1 dc 0.88V
rs vs gnd 1.0k
.alter
vg vin v1 dc 0.93V
rs vs gnd 1.5k

.end
 FFT Analysis of Vout without Rs:

FFT Analysis of Vout with Rs = 0.5k:

FFT Analysis of Vout with Rs = 1k:

 FFT Analysis of Vout without Rs = 1.5k:

Table 3

(W/L) = 1u / 0.18u , Cload = 10p

2nd 3rd
Rs(kΩ) Vin-DC Vin-AC A(dB) Vout(dB) harmonic harmonic
(dB) (dB)

0 0.83 0.05 11.481 -14 -56 -70

0.5 0.83 0.05 9.575 -16 -73 -77

1.0 0.88 0.05 7.971 -18 -83 -73

1.5 0.93 0.05 6.626 -20 -85 -70

As seen in the table, the value of Rs is inversely proportional to the value of gain.
Also, the effect of input voltage and resistance increasing results into a decrease of the
output voltage, 2nd harmonic and etc.
Questions:

1. How to increase the gain of common-source amplifier with resistive load?

- As observed in table 1, to increase the gain of common-source amplifier with

resistive load is to increase the value of the resistive load and lower its input
voltage, this also affects the performance of output impedance to increase its
value.

2. Replace Rs in figure 4.11 by a diode-connected NMOS. Using the steps we

followed before, what is the DC gain of this circuit?
- If the Rs is replaced by a diode-connected NMOS device or another NMOS
device, the gain of the amplifier decreases. The gain of the circuit is -8.29dB, by
changing 0.83V to 1.15V of the input voltage.

3. Using the configuration of question 2, perform the FFT analysis of Vin and Vout
to get the frequency spectrum of these waves. What happens to the circuit
linearity? Is there any difference with figure 4.11?
- In circuit linearity, there is a decrease in the value of harmonics with
respect to the FFT analysis. But, the circuit linearity stays the same.

CONCLUSION

In conclusion, I have observed that from the simulations that having a high
resistive load is important due to the fact that it also provide high gain in the circuit. Also
if the Rs is present, by decreasing the Rs increases the gain of the circuit, and ideally, the
value of the Rs should be zero.