This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2963277, IEEE Journal
of Emerging and Selected Topics in Power Electronics
Xilinx System Generator-based Rapid
Prototyping of Solid-State Transformer for On-
Grid Renewable Energy Integration
Haritha G.a, Student Member, IEEE, Kumaravel S.b,1, Senior Member, IEEE and
Ashok S.c, Senior Member, IEEE
National Institute of Technology Calicut, Kerala, India
Abstract-- At present, there is a need for reliable,
sustainable and effective integration of distributed energy
sources into the utility grid. Excess heating, de-rating due
to harmonics, etc., are the major drawbacks of the
conventional transformers. Such drawbacks led to the
development of Solid-State Transformers (SST). This
paper focuses on Xilinx System Generator (XSG) based
rapid prototyping of SST. Here, a Single Active Bridge
(SAB) is used for integrating renewable energy sources
with the utility grid. For safe starting and mode selection
with effective protection schemes of the SST, a dedicated
algorithm is developed and implemented in XSG along
with the controllers. The various controllers for the stable
operation of the SST are implemented in the XSG. A 3
kVA, 400 V, 3φ laboratory prototype of the SST is
fabricated. The developed prototype is tested successfully
and the results are presented in this paper. The faster
control execution, with parallel operation at a clock
frequency of 40 MHz on a controller platform enables
reliable operation of the system, which is highly susceptible
to sudden dynamic conditions. A study on the effect of
cooling system on the efficiency of the SST has been
conducted and the results are reported.
Index Terms-- rapid prototyping, single active bridge,
solid state transformer, Xilinx system generator
I. INTRODUCTION
THE growing demand for electric power has escorted to an
increase in the riddling of renewable energy sources into the
existing power grid. Distributed energy resources (DER) such
as wind, solar, battery, etc., are generally integrated into the
power grid through the conventional transformers at the point
of common coupling (PCC). Though these transformers
function satisfactorily till the recent past, their performance
may degrade due to the integration of the DER. The bulky
size, heavy weight, core saturation, etc., are the major
limitations of these transformers. Inability of the conventional
transformer to support reactive power, effects of harmonics,
heavy inrush of current, unbalanced loading, forced to replace
them with solid-state transformer (SST) [1-5].
Different converter configurations for the SST have been
reported in the recent past. Out of those configurations, the
1
CorrespondingAuthor: Tel:+91-9645654204
Email Address: kumaravel_s@nitc.ac.in
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1
isolated dual active bridge (DAB) converters with high-
frequency transformers are widely reported in the literature for
the integration of the DERs. Performance characterization of a
high-power DAB converter is reported in [6]. A power
electronic-based distribution transformer, viz., high-frequency
modulated AC/AC transformer is presented in [7]. Two
different bidirectional isolated DC–DC converters are reported
in [8] for interconnecting two 6.6 kV back-to-back systems.
Apart from the applications of SST in distribution system, a
novel DAB structure for metro vehicle system is presented in
[9]. Integration of different energy sources in microgrid
system using a typical SST structure is reported in [10].
Voltage and power balance control for SST in microgrid
application is presented [11].
The analysis and design of a series-resonant type DAB,
which ensures soft-switching transitions of all semiconductor
devices are discussed in [12]. An improved DC transformer
based on the switched capacitor with reduced switches is
proposed in [13]. However, a bidirectional buck-boost DC-DC
converter is added as a front converter which decreases the
efficiency and increases the volume of the system. In order to
improve the flexibility, SiC-based cascaded multilevel
converter (CMC) with forward-DAB topology is proposed in
[14] for PV applications. A modular SiC high-frequency solid-
state transformer for medium-voltage application is reported in
[15]. An auxiliary resonant circuit based soft-switching SST is
proposed in [16] where an intermediate DC voltage link is not
used. It can realize zero voltage switching (ZVS) for all main
devices, higher power density, and longer life. A modular
three-stage SST based on a cascaded H-bridge topology is
discussed in [17-18]. Here, energization of auxiliary power
supplies is reported to prevent undesired transients. Though
the DAB is highly used in the SST, as an interfacing device to
integrate the DERs in [12-18], most of them do not require a
bi-directional power flow.
The DAB of the SST uses a phase shift control that limits
the ZVS range and increases the transformer RMS current.
This limitation is overcome by implementing duty cycle
control in one side of the DAB with dual-phase shift
modulation [19]-[23]. Here, a voltage-based PI controller is
used to control the DAB. A minimum back-flow power based
extended-phase shift control strategy that determines the
optimal phase shift pairs to improve the efficiency, and reduce
circulating power flow and current stress is reported in [24].
Energy feed-forward control for the DAB of an SST is used in
[25] that consider the energy change in the inductor to reduce
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2963277, IEEE Journal
of Emerging and Selected Topics in Power Electronics
the voltage deviations and the transition time. An adaptive
control strategy that reduces the circulating current in an SST
by matching the virtual impedance of SST and system output
impedance is proposed in [26]. Different power management
schemes are also incorporated by modulating the three-phase
inverter controller to achieve power flow schemes [27-28].
The real-time hardware implementation of the grid
interfaced SST system faces many challenges. In [29], the
single-phase SST system was implemented using a Digital
Signal Processor (DSP) and a PIC microcontroller. A Field
Programmable Gate Array controller (FPGA) with a DSP is
reported in [12], [18], [30] for the real-time implementation of
an SST in the grid interfacing application. Here,
communication delay is a major problem among the two
different controllers. Such controller development is a time-
consuming process and prior knowledge about the controller is
required. In [31], an OPAL-RT deployed hardware-in-loop
platform is used to study and analyze the stability and
resonance damping of SST. Thus, there is a need for the rapid
prototyping platform to implement the controller of the SST in
real time. By using XSG based prototyping on FPGA [32], the
rapid prototype of the SST system can be achieved with the
control strategies of the converters implemented with parallel
processing and executed at very high sampling rate. In the
XSG platform, all the controllers are represented by the
hardware model of actual elements which is directly
implemented on the FPGA board.
This paper discusses a real-time implementation of an SST
for integrating DERs with the utility grid. The real time
implementation of the system is done using the FPGA
controller where the code is generated using the XSG. The
power management scheme, overcurrent, and overvoltage
protection scheme, various control strategy of SST, the phase
lock loop (PLL) and PWM pulse generation are modeled in
XSG platform and implemented in FPGA Zynq 7000 board.
II. SOLID-STATE TRANSFORMER FOR INTEGRATION OF
DERS INTO THE UTILITY GRID
The generalized block diagram of the SST for the
integration of DERs into the utility grid is shown in Fig 1. A
Single Active Bridge (SAB) is used in the SST to transfer the
power available in the DERs into the utility grid. The SAB-
based SST allows unidirectional power flow from DERs
intothe grid and hence finds more application in interfacing
LVDC Bus
Distributed Energy Resources (DERs)
DC
DC
Solar PV System MPPT Converter
DC
DC
Wind Energy System 50 Hz Rectifier
To Single Phase VSI
DC
DC
Fuel Cell MPPT Converter
Fig. 1. Generalized block diagram of DERs integration into the utility grid through SST using FPGA controller
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2
sources such as solar PV, wind, fuel cell, etc. The SAB
consists of a single-phase voltage source inverter (VSI), a
high-frequency transformer and a high-frequency diode bridge
rectifier. The DERs pump the power into the low voltage DC
(LVDC) bus. The power available in the LVDC bus is
transferred into the high voltage DC (HVDC) bus through the
SST. Here, the voltage regulation, one of the basic challenges
in renewable energy integration is achieved by controlling the
single-phase VSI of the SST using a PI controller. This
voltage regulation at the HVDC bus of the SAB makes the
controller less complex and improves the power density of the
switches compared to the DAB topology where the phase shift
control is used.
The power from the HVDC bus is then transferred into the
PCC where the utility grid is interfaced using a three-phase
VSI. This VSI is operated at 400 V (L-L), 50 Hz and the
inductor filters are used in the output side of this VSI to
suppress the current harmonics. A power management scheme
is proposed for the SST to manage the power available with
the DERs and the utility grid effectively. Accordingly, the
consumer load connected at PCC receives power from the
DERs and the utility grid. The power management scheme for
the SST also meets the reactive power requirement of the load
without disturbing the utility grid.
III. SINGLE ACTIVE BRIDGE TOPOLOGY FOR SST
An SST with SAB topology that facilitates unidirectional
power flow is presented as an interfacing device for
integrating DERs. The presented topology uses a minimum
number of controlled switches than the DAB. This reduces the
complexity of the circuit and has more reliability, lesser
weight, lower volume, and higher power density compared to
the DAB-based SSTs. The SAB also ensures harmonic
isolation, reactive power compensation and fault protection
with instantaneous line regulation and load regulation [33].
The three-phase output from the DERs is fed into a
rectifier bridge. The unregulated low voltage DC obtained
from the rectifier bridge is connected as an input to the SAB.
The SAB has a high frequency, controlled single-phase
inverter and a diode bridge rectifier which are coupled through
a high-frequency transformer. By controlling the high-
frequency inverter, a regulated voltage is obtained across the
HVDC capacitor. The three-phase AC output voltage at grid
frequency is obtained from the VSI from the HVDC-link. The
AC Bus
HF Rectifier Lf
ipri (25 kHz) isec HVDC Bus
Single Phase Lf
VSI Three Phase
v1 v2 Cdc
(25 kHz) VSI Lf
1:n
HF Transformer
To Three Phase VSI Consumer # 1
Consumer # 2
DC Link Voltage Consumer # n
A / D converter
Load Power Residential Loads PCC
Peak Demand
FPGA Controller
Grid Frequency
(Xlinx System Generator)
Grid Voltage
HFT primary current
Utility Grid
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high-frequency transformer plays a vital role in converting the
LVAC produced by the high-frequency inverter received at
the primary side into an HVAC across the secondary side [34].
According to the level of voltage conversion from primary to
secondary and power transfer capacity, the transformer is
designed. A single-phase transformer with uniform,
symmetrical and concentric layer winding structure is
designed with the symmetrical distribution of flux on both
sides of the limbs. The numerical design of the transformer
core is done based on the following equation.
𝑃 the SAB-based SST is presented in this paper as shown in Fig.
𝐴𝑐 . 𝐴𝑤 =
2𝐾𝑤 𝐵𝑚 𝑓𝑠 𝐽
where Ac is the cross-section area of the core, Aw is the
window area, P is the total power capacity of the core, Kw is
the transformer winding factor, 𝐵𝑚 is the maximum flux
density,𝑓𝑠 and J is the operating frequency and current density
of the core respectively. The specification of the designed
transformer is enlisted in Table 1.
The designed high-frequency transformer used in the SAB
converter is required to satisfy the design constraints in terms
of magnetic flux density distribution and core saturation
limits. The design parameters of the ferrite transformer
obtained by numerical design equation have to be validated for
the feasible operation of the transformer which satisfies the
design constraints. The validation is carried out by developing
a two-dimensional (2D) model of the transformer in ANSYS
software as shown in Fig. 2 (a). The solution of magnetic flux
density in the geometry by Maxwell's equations using the
finite element method (FEM) is obtained through simulation
in ANSYS software. The low voltage (LV) winding of the
transformer is excited by the rated current of 28.28 A (peak
value) and the high voltage (HV) winding is excited by 14.14
A (peak value) to analyze the flux distribution in the winding
geometry and to validate the design constraints at the critical
excitation limits. The magnetic flux distribution in the
geometry is solved by Maxwell's equations as follows.
∇×H=J
∇. 𝐵 = 0
The simulated flux distribution in the transformer geometry is
shown in Fig. 2 (b). The simulation results show that flux
distribution in the core is highest in the region near the
windings. Further, the analysis of simulated flux density (B) in
the geometry as described in Fig. 3 (a) shows that the peak
flux density in the core is limited to 0.16 Wb/m2 under peak
current excitation of the winding. This validation shows the
reliability of the designed transformer for the considered
specifications. The feasibility of the proposed design leads to
the fabrication of the transformer with ferrite core (N87
material) of specification EE 71/33/32, frequency of 25 kHz,
primary to secondary voltage of 300 V / 600 V. Based on the
designed parameters of the high-frequency transformer which
is validated using FEM analysis, a high frequency (HF)
transformer is fabricated. Copper wire of gauge SWG 28 with
skin depth of 0.414 mm is used to wind the transformer. The
fabricated HF transformer is shown in Fig. 3(b).
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of Emerging and Selected Topics in Power Electronics
3
IV. CONTROLLERS DESIGN FOR SST
There are two controllers involved in the SAB-based SST
to transfer the power from the DERs into the utility grid. i) a
controller for high-frequency inverter and ii) a controller for
the grid side three-phase VSI.
A. Design of Controller for High-Frequency Inverter of SAB
The primary objective of controlling the high-frequency
inverter of the SAB is to regulate the voltage across the high
voltage DC-link capacitor. A peak current mode controller for
(1)
4. This controller is faster than the conventional voltage
controller because it does not have a compensator in the inner
loop. It also enables instantaneous control of the transformer
primary current within one switching cycle. Here, the switches
of one leg are operated with a duty cycle of 50% and the
switches of the other leg are controlled using the peak current
mode controller. The voltage across the high voltage DC-link
capacitor is measured and compared with the reference
voltage. The error voltage obtained from the comparison is fed
into a PI controller which generates a reference current signal.
Finally, the required PWM pulse for the other leg of the
inverter is generated from a hysteresis controller using the
reference current signal and the current sensed from the
primary side of the transformer.
B. Control of Three-Phase Voltage Source Inverter at Utility
Grid Side
The closed loop voltage oriented current control based on
synchronous DQ frame is used to control the grid side three-
phase voltage source inverter as shown in Fig. 5. This control
uses a DQ frame rotating at the angular speed, ω where the d-
axis is aligned on the grid voltage vector. The output of the
three-phase VSI inverter current is transformed to a DQ frame,
where the d and q axes DC quantities are compared with the
respective references generated according to the required
amount of active and reactive power at any instant. This error
signal is fed to a PI controller. The reference current in the d
(2) component, 𝑖𝑑∗ is used to manage the active power flow to the
(3) utility grid/load and that in the q component, 𝑖𝑞∗ controls the
reactive power requirement of the load. With the assumption
that the d-axis component is perfectly in alignment with the
grid voltage, the value of eqis equal to zero. Hence, the active
and reactive power equations are expressed as,
3
𝑃 = 𝑒𝑑 𝑖𝑑 (4)
2
3
𝑄 = 𝑒𝑑 𝑖𝑞 (5)
2
TABLE I
TRANSFORMER DESIGN PARAMETERS
Parameter Value Parameter Value
Rated power 3 kVA Frequency 25 kHz
Winding factor 0.6 Turns ratio 1:2
Maximum flux
density Bmax
0.4 T Wire selected SWG 28
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of Emerging and Selected Topics in Power Electronics
4

HV winding
V. POWER MANAGEMENT STRATEGY FOR SST
The main objective of the power management strategy is to
utilize the maximum power available from DERs without
compromising the stability and power quality issues. It is used

Core EE 71/33/32
to provide uninterrupted power supply to the consumer despite
any dynamic conditions such as fault or transients in DERs
and at the utility grid side. The proposed power management
strategy is shown in Fig. 6. According to the status of the gird
LV winding
and power generated from DERs, there are three modes of
(a) (b) operations considered here: i) SST enabled-islanded mode, ii)
Fig.2 (a) FEM 2D model of HF transformer (b) Flux lines SST reactive power support mode-disabling SAB and iii) grid
obtained from FEM activated mode. The maximum power than can be safely
transferred by the SST into the load side without violating any
stability constraints is Psafemax, and P is the actual active power
generated from DERs.
When the grid is not available and the status of power at
DERs is Psafemin ≤ P ≤ Psafemaxsuch that the stability constraints
of the system are met, the SST is enabled in islanded mode.
Here, the load current is the reference for the three-phase VSI
at the AC bus, which uses the direct current synchronous
(a) (b) control for generating sinusoidal PWM pulses. The HVDC-
Fig. 3 (a) Flux density in transformer geometry obtained from link voltage is regulated by the SAB converter. The active
FEM simulation. (b) Fabricated high frequency transformer. power required is transferred from the DERs through the SST
and the reactive power is generated by the three-phase VSI.
When the grid is available and the status of power at DERs
is Psafemin ≥ P or P ≥ Psafemax, SST-reactive power support mode
LVDC Link capacitor

HVDC Link capacitor

is activated. The SST is disabled by masking the PWM pulses

to the SAB converter. The three-phase VSI at the grid side
Vo maintains the voltage at the HVDC bus and satisfies the
reactive power demand of the load, whereas, the required
active power is pumped from the grid. This mode helps in
improving the power quality at the grid side, thereby
improving the grid stability.
Hysteresis Iprimary Reference
e When the grid is available and the status of power at DERs
+-
Current current

25kHz pulses
Controller
Iref
generator
is Psafemin ≤ P ≤ Psafemax,the grid-connected mode is activated.
with 50%
0.5 Vref
The reference current of the VSI of SST present at the grid
dutycycle
Comparator end is set to inject the maximum active power available with
DERs. According to this active power magnitude, the
Fig. 4. Controller for SAB-based DC-DC converter
remaining kVA capacity of the SST is utilized to inject the
reactive power into the grid by setting the iqr*.
αβ
-+ This power management strategy helps to provide
abc uninterrupted power supply to the load and reactive power
αβ -wL compensation from the SST.
abc
abc
wL αβ
VI. HARDWARE IMPLEMENTATION OF SAB-BASED SST
A. Hardware of SST
-
+
The 3kVA prototype of the SAB-based SST has been
designed and fabricated. The assembled laboratory setup of
the fabricated SST is shown in Fig. 7. The SST consists of a
αβ
PLL high-frequency transformer of 300 V / 600 V, 25 kHz and the
abc primary side of the transformer is connected to the high-
frequency inverter. This high-frequency inverter uses two
ultra-fast IGBT modules of SKM 400GB125D with the
maximum voltage of 1200 V and switching frequency up to 40
Fig.5. Control of three-phase VSI at utility side in the SST kHz. The heat sink is selected for the safer current value of
enabled mode. 50 A. Snubber capacitors of 0.47 µF/1500 V DC are provided
for transient voltage protection. The dead time required to
avoid the shoot-through state of the VSI has been provided as
3 µs. As per the data sheet, the on-time and off-time of the

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2963277, IEEE Journal
of Emerging and Selected Topics in Power Electronics
5

IGBT module are respectively, 70 ns and 50 ns at 25 °C. In the
experimental setup, the dead time for the IGBT modules of the
VSI is provided using built-in feature of the SKYPER32R
IGBT gate drivers. Two series connected DC-link capacitors
each of, 4700 µF / 450 V, make total capacitor voltage value
of 900 V at the input of the high-frequency inverter. Bleeder
resistor of 27 kΩ is provided across each of the DC-link
capacitors at the input side to provide a discharge path to the
capacitor when the power supply is turned off.
A high-frequency diode bridge rectifier which uses four
SKKD 162/18 diode switches with VRRM of 1800 V is
connected at the secondary side of the transformer. A parallel
RC snubber circuit of 0.22 µF / 2500 V and 33 Ω is provided
across each diode switch for protection towards transient
voltages. The output side of the high-frequency diode bridge
rectifier (i.e., HVDC bus) is connected to a three-phase IGBT
based VSI (grid side inverter). Two capacitors of each 4700
µF / 450 V are connected across the DC-link of the HVDC bus
to form the capacitance of 2350 µF with a voltage of 900 V. A
bleeder resistor of 27 kΩ of 20 W connected across each
capacitor enables a discharging path when the power supply is
switched off and allows voltage sharing.
The grid side inverter uses the three IGBT modules of
SKM 75GB12T4 with rated voltage of 1200 V and the
switching frequency up to 20 kHz. The heat sink is selected
for a rated value of 50 A current. Snubber capacitors of 0.22
µF / 1500V DC are provided for transient voltage protection.
The gate drive card of SKYPER32R is used to drive the
according to the modes of operation are first modeled and then
the controllers are implemented using MATLAB®2014b/
XILINX blocks. It uses basic elementary, control logical,
indexed, data type and mathematical operations to design the
control structure. Each of the converter control logics is
enabled only after the real-time monitoring of the voltage and
current values from the sensors, thus the fault isolation is
provided within a few microseconds. The reset ports are
enabled for every PI control logic implementation at different
schemes once the PWM signal generation for various modes is
disabled. The required delay for the controller implementation
is provided using the register blocks and cast blocks are used
to convert fixed point format to high precision floating point
format.
The protection scheme for the high frequency isolated
DC/DC converter is shown in Fig. 8(a). When the SST mode
of power flow control, is enabled, the voltage and the current
sensors sense the real time HVDC link voltage across the
capacitor and the peak primary current of the high frequency
Idle State
[ GSC disabled , SSIT disabled ]
GSC with proposed grid voltage
synchronous dq control enable
HVAC Contactor switch on
LVAC Contactor switch on
Time delay (three phase
controlled VSI)
Time delay ( SAB DC-DC
converter)
PLL ENABLE

IGBT. An inductor filter of 38 mH is used in the output side of SAB enable (Peak current mode
control enable)
the grid side inverter to suppress the current harmonics. Thus,
Psaf emin P Psaf emax
the prototype of the SST is assembled in the laboratory
environment. HVDC link
voltage within
For the testing purpose, a three-phase AC source of 300 V, limit
Grid side VSI with HVDC link
50 Hz is connected to the LVDC bus through a diode bridge control enabled
rectifier. To vary the voltage of the input source, a three-phase
auto transformer is used. The grid side inverter is connected to Transformer
primary current
400 V, 50 Hz three-phase utility grid. Also, a three-phase load HVDC link within limit
voltage within
of 5 kW is connected across the utility grid as given in Fig. 1. limit

B. Controller implementation in Xilinx system generator Run State

SST reactive power support
The real-time integration of the system with a three-phase mode

utility grid at 400 V, 50 Hz is done by utilizing a high- Fig. 6 Start-up logic for the SST controller implemented with
frequency ferrite transformer operating at 25 kHz. The XSG
HVDC-link capacitor voltage is regulated at 600 V DC. The
controller for the SAB converter, current protection and the 1 Diode bridge rectifiers 2 HF inverters
three-phase VSI controller based on synchronous PI DQ 3 HF Transformer
current control along with power management scheme are 4 HF Rectifiers
implemented on Zynq 7000 FPGA module using XSG. HVDC-Link LVDC-Link
5 VSI
The operating switching frequency of the solid-state Capacitors Capacitors
transformer is considered as 25 kHz. Hence, the clock period R
5 a
of the FPGA is set to 40 MHz which is 1600 time higher than Y 4 2
3 1 b
the frequency of SST. This 40 MHz frequency selection of B
FPGA is a fast-enough sample period for the controller for the c
SST application. The considered processor supports higher
clock frequencies, if required. The system algorithm for the L-filters
implementation of PLL, generation of PWM pulses for the Driver circuits
for grid side VSI
HVDC voltage regulation in the SAB converter incorporating Driver circuits for HF inverter
the protection schemes and the grid side inverter controller
with required protection and power management scheme
Fig.7. Hardware implementation of the SST

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2963277, IEEE Journal
of Emerging and Selected Topics in Power Electronics
6

transformer. The real time current and voltage values hence
measured are compared across preset reference values and
enable the PWM pulses to the converter if they are within
safer limits. The PWM pulse input to the SAB converter is
reset to zero and the converter is protected against voltage and
current surges. The computation time of the FPGA being 25ns,
the converter is isolated within the time range of a few
microseconds.
The implementation of the PI controller as in Fig. 8(b) is
achieved by using the mathematical equation,
𝑡 Various parts of the control algorithm for the VSI converter
𝑣(𝑡) = 𝐾𝑝 𝑒(𝑡) + 𝐾𝑖 ∫0 𝑒(𝑡)𝑑𝑡
where v(t) is the control signal and e(t) is the error signal in
the time domain. Kp and Ki are the proportional and the
integral time constant respectively. In the controller
implementation using XSG, the Kp and Ki values can be
provided either through software interface which allows easier
tuning of the controller for different Kp and Ki values using
input registers or using XSG constant blocks where once the
code is generated it remains a fixed value. On multiplying the
error signal with the Kp and Ki values the required precision
and arithmetic type of the input and output values need to be
accurately defined. The correction time of an integral part of
the PI controller determines the updating time for which the
integral controller updates the output values. Here, the
correction time is taken to be 25µs, hence, the error signal is
integrated and value is updated after every 25µs.Also, every
time the mode of power flow is selected, the particular PI
controller is also enabled. For changes in the power flow
strategy, the integral part of the PI controller is reset so that
once the mode is selected again, the PI controller starts from
the zero point.
Fig. 8(c). shows the VSI converter of SST with power
management strategy being modeled in the XSG platform.
(6)
are also marked for reference in Fig. 8(c).The configuration of
digital control for the real-time integration of SAB-based SST
in FPGA is depicted in Fig.9. Here, the ARM core is used to
deal with complex tasks and it contains a dedicated Gigabit
Ethernet peripheral. It is being used for host communication,
i.e., run-time transfer of control and data, and it communicates
to dedicated Ethernet controller directly. All the real-time
control functions along with hardware I/O interactions
(sensors, encoders, etc.) are handled by FPGA. The FPGA
control logic is mapped to ARM as a peripheral with a data
transfer rate of 200 ksps.

Integral part of PI
Controller

Proportional part

(a) (b)

1 Enable signal to the three phase VSI 4 Mode selection for power flow management

2 Real time voltage sensing and monitoring 5 Synchronous DQ frame based voltage oriented
current controller for SST enabled mode
6
3 Generation of Id ref in SST disabled reactive 6 Sinusoidal PWM generation for three phase VSI
power support mode
5
(c)
Fig.8.Implementation of (a) protection scheme (b) PI controller (c) Modeling of VSI converter of SST with power management
strategy in XSG platform

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2963277, IEEE Journal
of Emerging and Selected Topics in Power Electronics
7

Real-Time
Probe Peak current mode MPPT controller
Registers controller for SAB for AC/DC rectifiers

Digital
Control loops for Digital

I/O
Real-Time three phase VSI I/O port
ARM® Cortex -A9
Input
MPCore Output Logics related to PWM

ADCs
Registers (PLL,voltage protection, current protection) ADC control
registers

DAC control PWM generators Fault control

(Fixed duty cycle PWM, Varied duty cycle registers
registers PWM, SPWM, Enable /Disable)
Ethernet interface

Monitoring DACs Optical Isolation

& Control

Fig.9. Configuration of digital control for the real-time integration of SAB -based SST in FPGA.
Once the modeling and simulation analysis are done with
the help of the power circuit, the next step involves the
automatic code generation of hardware description language.
XSG supports both VHDL and Verilog. In Verilog, the
language is more compact, as the Verilog language is more of
a hardware modeling language. Hence,Veriloghas been chosen
as the hardware language code.This is followed with the
generation of the bit stream file, which is downloaded, into
Zynq 7000 FPGA embedded chip.The control model
developed for the SST is synthesized independently to obtain
its area usage. The area usage of FPGA is obtained from the
VIVADO project flow as shown in Fig. 10. From the
utilization summary it is analyzed that the controller used 20%
of flip-flop, 29% Look-up table (LUT), 4% of Memory LUT,
46% of Inputs/Outputs (I/O) 42% of Block RAM (BRAM),
26% of DSP48, 16% of Global Buffer and 25% of Mixed-
mode clock manager (MMCM). Execution cycle of the FPGA
is calculated manually from the implemented controller of the
SST. The control models developed in XSG are bit and cycle
accurate. The number of cycles required by the control models
to generate the final three-phase PWM pulses for three-phase
VSI is 85 cycles with an execution period of 2.125 µs, where
25 ns is the FPGA clock period for execution of 1 cycle.
50
45
40
35
% Utilization
desired time for a timing path. From the obtained timing
performance, the Worst Negative Slack (WNS), Worst Hold
Stack (WHS) and Worst Pulse Width Slack (WPWS) are
observed as positive, and the Total Negative Slack (TNS),
Total Hold Slack (THS) and Total Pulse Width Negative Slack
(TPWNS) are observed as zero. Hence, the above timing
performance of the controller is found satisfactory.
VII. RESULTS AND DISCUSSIONS
A series of experiments have been conducted on the laboratory
prototype of the SAB-based SST. First, the performance of the
SST enabled mode is verified experimentally. The three-phase
AC voltage of 300 V (L-L), 50 Hz is applied as an input to the
three-phase diode bridge rectifier. A three-phase load of 1kW
and 300 VAr is set and it is connected to the grid-side AC bus.
The load is turned on at an instant t and the steady-state
waveforms from various part of the SST are observed using
the digital storage oscilloscope (DSO).
Fig. 11(a) shows that the three-phase input source supplies
the active power of 1.25 kW. The source current wave shape
shown in the figure and the power factor of the source side can
be improved using a suitable compensation method. The
voltage and current waveforms of the primary and secondary
side of the high-frequency transformer is shown in Fig. 11(b).
The Fig.11(c) shows the voltage and current of both the
LVDC and HVDC links, with HVDC-link voltage, maintained
at 600 V DC. The current delivered by the SST into the AC

30 bus, output voltage of SST, source current, and the HVDC-

25 link voltage is depicted in Fig. 11(d). When the power is
20 delivered by the SST, the controller at the SAB maintains the
15 HVDC-link voltage constant. The required reactive power
10 support of 300 VAr is provided by the three-phase VSI at the
5 grid end. The percentage of total harmonic distortion (THD)
0 for the SST output current and output voltage are shown in
FF LUT MemoryLUT I/O BRAM DSP48 BUFG MMCM Fig. 12(ii) for 40% loading.
Fig. 10 Area usage of FPGA obtained from VIVADO project The performance of reactive power support mode of SST is
flow assessed by disabling the SAB. Fig.12.(i(a)) shows the
The timing performance of implemented code in FPGA is transformer secondary voltage when the SAB is disabled. The
also obtained from the VIVADO project flow. The slack in any grid side inverter controller maintains the HVDC-link voltage
system means the time difference between the actual time and at 600 V DC for the corresponding power management

2168-6777 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2963277, IEEE Journal
of Emerging and Selected Topics in Power Electronics
8

Natural Air cooling Forced air cooling

95
Vprimary
94
Vab Vbc Vca 93
Iprimary

Efficiency (%)
Vsecondary 92
ia 91
90
Isecondary 89
88
(a) (b) 87
VLVDC 16 36 56 76 96
Percentage Loading
IDC at LV source Ia

VHVDC Fig. 14 Efficiency profile for natural and forced air cooling
VHVDC scheme and the inverter output voltage and current with an
VRY exact 90° phase shift. Fig.12.(i(b)) shows the inverter output
IHVDC voltage and current waveforms before and after the inductive
IR filter. The three-phase current and voltage output of the SST is
depicted in Fig.12.(i(c)) and the waveform confirms that the
(c) (d)
SST supplies the reactive power of 1kVAr. Fig. 13(a) shows
Fig.11 Steady state waveforms for the SST enabled mode the dynamic state variation of the system in the SST enabled
Vsecondary
mode, where the apparent power generated by the SST follows
the variation in load demand from 1 kVA to 0.76 kVA by
VHVDC regulating the HVDC-link and grid voltages. The dynamic
Vinverter RY Iinverter R state results with varying reactive power demand are given in
Fig.13(b). The effect of cooling system on the SST efficiency
VRY
IR VRY is analyzed experimentally on the developed prototype. Two
IR
cases have been considered for the analysis. i) SST with
natural cooling ii) SST with forced air cooling at 85 m3/h. The
values of input and output power are measured using the
i(a) i(b) power quality meters experimentally. The efficiency profile of
the SST is obtained for the two cases by varying the
percentage load. Fig. 14 shows the obtained efficiency profile
of the SST. It proves that the forced air-cooling method
VRY significantly reduces the power loss, as the resistance of the
switching devices reduces due to the reduction in the
temperature.

IR IY IB
VIII. CONCLUSION

(ii)
This paper discussed the XSG-based rapid prototyping of
i(c)
SST. Here, a Single Active Bridge (SAB) is used for
Fig.12.(i) Steady-state waveforms for the SST reactive power
interfacing distributed energy sources with the utility grid. The
support mode, disabling the SAB. (ii) THD analysis of SST
rapid prototyping of the SST system is done using the FPGA
output voltage and current in SST enabled mode.
controller where the code is generated using the XSG. The
Apparent Power gen. Vsecondary power management scheme, overcurrent and overvoltage
Apparent Power Ref protection scheme, various control strategy of the SST, the
VHVDC VHVDC PLL and the PWM pulse generation are done on XSG
VRY platform using basic elementary, control logical, indexed, data
type, mathematical operations, and implemented in FPGA
Zynq 7000 board. A series of experiments have been
VRY conducted on the laboratory prototype of the SAB-based SST
IR
by considering a three-phase input voltage of 300 V (L-L) and
the output voltage of 400 V (L-L). The waveforms are
observed for the steady state and dynamic state conditions of
(a) (b) the SST under different modes of operation of the power
Fig. 13(a) Dynamic state waveforms for SST enabled mode management scheme. The observed waveforms prove that the
and (b) SST reactive power support mode, disabling the SAB. control strategy effectively regulates the HVDC link voltage at
600 V for the sudden change in load. From the experiment, the
value of voltage THD of the SST is found as 2% and the
current THD to be 4.3% at 40% loading for a 3kVA system.

2168-6777 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2963277, IEEE Journal
of Emerging and Selected Topics in Power Electronics
The efficiency profile of the system under study is also carried
out for the two different cases of cooling methods. For the
system provided with forced air-cooling at 85m3/h, the highest
recorded value of efficiency is 93.5%.
IX. Acknowledgement
The work has been carried out in partial fulfillment of the
funded project entitled, “Development of Solid State
Transformer as a Renewable Energy Integrating Device”,
sponsored by the Central Power Research Institute, Bangalore,
India, with R&D Management Code no:
RSOP/2015/DG/9/15122015 and FAS. (HO) Project ID: 117).
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