Acer Aspire 3500 Esquema

5 4 3 2 1
D D
C C
Sonoma Dothan EAL50_1

LA2362 Schematic
B B
A A
Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
<Title>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2362 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 11, 2005 Sheet 1 of 52
5 4 3 2 1
5 4 3 2 1
Compal confidential Block Diagram

Dothan
D Clock Generator D
uFCPGA CPU ICS
Memory
HA#(3..31) HD#(0..63) BUS(DDR) Fan Control X1
System Bus
400 / 533MHz Dual Channel
CRT CONN. 2.5V 333MHz SO-DIMM X 1
BANK 0, 1
VGA & TV-OUT Alviso Intel 915 PM/GM SO-DIMM X 1 LED/B
BANK 2, 3
Board GMCH-M Channel A
Internal GM
ATI VGA 1257 FC-BGA SW LED BD
VGA CONN. PCI-E 16X
C
External PM C
T/P
DMI
1.5V
MINI PCI 100MHz BT+MDC DC IN
3.3V 24.576MHz AC-LINK BATT IN/+2.5V

3.3V 33MHz PCI BUS 3.3V 33MHz
IDSEL:AD17
ICH6
(PIRQA/B#,GNT#2,REQ#2)
609 BGA
RTL 8110SBL AC97 CODEC 1.5V/1.05V(+VCCP)
VIA6301 CardBus / G 8100CL / ATA100 RTL 250
1394 Controller 100
B ENE CB712 B
5V/3.3V/15V
HDD CDROM
Transformer
1394 SDIO Slot 0 & RJ45 AMP &
CONN. CONN. LPC BUS
3.3V 33MHz Phone/ MIC
USBPORT 0 Jack 1.8V / 0.9V
JUSBP2
USBPORT 1
JUSBP3
48MHz / 480Mb USBPORT 2
USB2.0 BT
X BUS USBPORT 3 VCORE
JUSBP1
USBPORT 4
SIO JUSBP1
KB910 USBPORT 5
LPC47N217D RESERVED CHARGER
SST39VF080 USBPORT 6
RESERVED
A
USBPORT 7 A
RESERVED
FIR PIO Touch Pad Int.KBD

<Title>
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomLA-2362 1
5 4 3 2 1
5 4 3 2 1
I2C / SMBUS ADDRESSING
External PCI Devices
DEVICE IDSEL # REQ/GNT # PIRQ PCB Rev Data
LAN AD17 0 F Bringup-Build 0.1

CARD BUS AD20 1 A SST-Build
D Power Managment table D
Cardreader B PT-Build
1394 AD16 2 E
Wireless LAN(MINI PCI) AD18 3 G,H
ST-Build
Signal
+CPU_CORE
+VCCP QT-Build
+5VS
+3VS
State +2.5V +2.5VS
+12VALW +3V +1.8VS
+3VALW +5V +1.25VS
+5VALW +12V +1.5VS
@ Depop S0 ON ON ON
1@ EAL51
S1 ON ON ON
2@ EAL50 SCHEMATICS VERSION LIST
S3 ON ON OFF
1@ EAL51 VALUE (DELETE SIO/1394) VERSION ISSUE DATE REMARK
S5 S4/AC ON OFF OFF

0.0A First Release
S5 S4/AC don't exist OFF OFF OFF
C C
Ceramic Capacitor Spec

Guide:
Temperature Characteristics:
Symbol 0 1 2 3 4 5 6 7
CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R
8 9 A B C D E F G
NP0 C0G BJ CH CJ CK SH SJ
H I J
UJ UK SL
Tolerance:
Symbol A B C D F G H J
CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%
B B
K M N P Q V X Z
+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20%
SMBUS Control Table
THERMAL THERMAL VGA Thermal

SOURCE INVERTER BATT SERIAL SENSOR SENSOR SODIMM CLK CHIP MINI PCI LCD
EEPROM (CPU) (LM75) ADM1032
SMB_EC_CK1 PC87591L
SMB_EC_DA1
SMB_EC_CK2 PC87591L
SMB_EC_DA2
ICH_SMBCLK
ICH6-M
ICH_SMBDATA
LCD_DDCCLK Alviso
A LCD_DDCDATA GM-GP A

<Title>
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-2362 1
5 4 3 2 1
5 4 3 2 1
ACIN
32ms
+3/5/12VALW
D D
ON/OFF#
t<=10 ms
8.5/2.44/3.792ms
EC_ON#
t=100 ms
364us
t=109 ms
PWRBTN_OUT#
438ms
SYSON
3/5V 400us 2.5V(1.8ms)
+12/2.5/3/5V
7.856ms
C RSMRST# t<110 ms C
117ms
SLP_S3/4/5#
92.88ms
SUSP# t>0
1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)

+1.25/1.5/1.8/2.5/3/5VS
2.166ms
1.3ms PGD
+VCCP
5.6ms
VR_ON#
B B
CPU_VID t<100 us
726us
+CPU_CORE
815.2us t<110 ms
Vgate
99ms
SYSPOK
PCIRST/PLTRST# 1.036ms 2<t<3 RTCCLK
61us
CPU_RST#
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+3V
<8> H_A#[3..31] H_D#[0..63] <8>
JCPU1A R79
150_0402_5%
Dothan
H_A#3 P4 A19 H_D#0 1 2 ITP_DBRESET#
H_A#4 A3# D0# H_D#1
U4 A4# D1# A25
H_A#5 V3 A22 H_D#2
H_A#6 A5# D2# H_D#3
H_A#7
R3
V2
A6# D3# B21
A24 H_D#4
Test pad as closed as posible +VCCP
H_A#8 A7# D4# H_D#5 R90
W1 B26
H_A#9 A8# D5# H_D#6 54.9_0603_1%
T4 A21
D H_A#10 A9# D6# H_D#7 ITP_DBRESET# PAD T7 ITP_TDO D
W2 B20 1 2
H_A#11 A10# D7# H_D#8 R76
Y4 C20
H_A#12 A11# D8# H_D#9 ITP_BPM#0 PAD T6 54.9_0603_1%
Y1 B24
H_A#13 A12# D9# H_D#10 H_RESET#
U1 D24 1 2
H_A#14 A13# D10# H_D#11 ITP_BPM#1 PAD T8
AA3 E24
H_A#15 A14# D11# H_D#12 ITP_BPM#5
Y3 C26 1 2
H_A#16 A15# D12# H_D#13 ITP_BPM#2 PAD T10 R745 56_0402_5%
AA2 B23
H_A#17 A16# D13# H_D#14
AF4 E23
H_A#18 A17# D14# H_D#15 Place near JITP 0.5" ITP_BPM#3 PAD T9
AC4 C25
H_A#19 A18# D15# H_D#16
AC7 H23
H_A#20 A19# D16# H_D#17 ITP_BPM#4 PAD T12 +VCCP R479 39.4
AC3 G25
H_A#21 A20# D17# H_D#18 R74 37.4_0402_1%
AD3 A21# D18# L23
H_A#22 AE4 M26 H_D#19 22.6_0402_1% ITP_BPM#5 PAD T11 1 2 ITP_TMS
H_A#23 A22# D19# H_D#20 H_RESET# PAD T4 R85
AD2 A23# D20# H24 1 2
H_A#24 AB4 F25 H_D#21 ITP_TCK PAD T17 150_0402_5%
H_A#25 A24# D21# H_D#22 ITP_TDI
AC6 A25# ADDR GROUP DATA GROUP D22# G24 1 2
H_A#26 AD5 J23 H_D#23 R87 This shall place near CPU
H_A#27 A26# D23# H_D#24 22.6_0402_1% CLK_ITP_R PAD T19 R100
AE2 A27# D24# M23
H_A#28 AD6 J25 H_D#25 ITP_TDO 1 2 PAD T15 680_0402_5%
H_A#29 A28# D25# H_D#26 ITP_TRST#
AF3 A29# D26# L26 1 2
H_A#30 AE1 N24 H_D#27 R106
H_A#31 A30# D27# H_D#28 27.4_0402_1%
<8> H_REQ#[0..4] AF1 A31# D28# M25
H26 H_D#29 ITP_TRST# PAD T16 1 2 ITP_TCK
H_REQ#0 D29# H_D#30 ITP_TMS PAD T13
R2 REQ0# D30# N25
H_REQ#1 P3 K25 H_D#31 ITP_TDI PAD T14
H_REQ#2 REQ1# D31# H_D#32
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 H_D#33
REQ3# D33#
CLK_ITP_R#
R1101 2 0_0402_5%
H_REQ#4 T1 REQ4# D34# T25
U23
H_D#34
H_D#35 Check ITP connector.
CLK_ITP_R
R1121 H_ADSTB#0 D35# H_D#36
2 0_0402_5% <8> H_ADSTB#0 U3 ADSTB0# D36# V23
@ H_ADSTB#1 AE5 R24 H_D#37
<8> H_ADSTB#1 ADSTB1# D37# H_D#38 +VCCP
@ D38# R26
C H_D#39 C
D39# R23
CLK_ITP @ R1111 2 0_0402_5% CPU_CK_ITP A16 AA23 H_D#40 1
<18> CLK_ITP CLK_ITP# ITP_CLK0 D40#
<18> CLK_ITP#
@ R1091 2 0_0402_5% CPU_CK_ITP# A15 ITP_CLK1 D41# U26 H_D#41 C359
V24 H_D#42
CLK_CPU_BCLK D42# H_D#43 0.1U_0402_10V6K
<18> CLK_CPU_BCLK B15 BCLK0 D43# U25
CLK_CPU_BCLK# B14 HOST CLK V26 H_D#44 2
<18> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
AA26
D46# H_D#47
Y25
H_ADS# D47# H_D#48
<8> H_ADS# H_BNR#
N2
ADS# D48#
AB25
H_D#49
Place near JITP
<8> H_BNR# L1 AC23
H_BPRI# BNR# D49# H_D#50
<8> H_BPRI# J3 AB24
H_BR0# BPRI# D50# H_D#51
<8> H_BR0# N4 AC20
H_DEFER# BR0# D51# H_D#52
<8> H_DEFER# L4 AC22
H_DRDY# DEFER# D52# H_D#53 +3VS
<8> H_DRDY# H2 AC25
H_HIT# DRDY# D53# H_D#54
<8> H_HIT# K3 AD23
H_HITM# HIT# D54# H_D#55
56_0402_5% R78
<8> H_HITM# K4
HITM# CONTROL GROUP D55#
AE22
+VCCP
1 2 H_IERR# A4 AF23 H_D#56
+VCCP IERR# D56#
1
H_LOCK# J2 AD24 H_D#57
<8> H_LOCK# H_RESET# LOCK# D57# H_D#58
B11 AF20 R132
<8> H_RESET# RESET# D58# H_D#59
AE21 1K_0402_5%
D59# H_D#60
<8> H_RS#[0..2] AD21
H_RS#0 D60# H_D#61
H1 AF25
2
RS0# D61#
1
H_RS#1 K1 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 R124
L2 AF26
H_TRDY# RS2# D63#
<8> H_TRDY# M3 56_0402_5%
TRDY#
PROCHOT# <32>
D25
2
DINV0# H_DINV#0 <8>
1
J26 R123 C
ITP_BPM#0 DINV1# H_DINV#1 <8>
C8 T24 56_0402_5% 2 Q6
ITP_BPM#1 BPM0# DINV2# H_DINV#2 <8> B
B8 AD20 2SC2411K_SC59
ITP_BPM#2 BPM1# DINV3# H_DINV#3 <8> E
A9
3
B ITP_BPM#3 BPM2# B
C9
2
BPM3# H_DSTBN#[0..3] <8>
C23 H_DSTBN#0
ITP_DBRESET# DSTBN0# H_DSTBN#1 H_PROCHOT#
A7 K24
H_DBSY# DBR# DSTBN1# H_DSTBN#2
<8> H_DBSY# M2 W25
H_DPSLP# DBSY# DSTBN2# H_DSTBN#3
<20> H_DPSLP# B7 AE24 H_DSTBP#[0..3] <8>
H_DPRSLP# DPSLP# DSTBN3# H_DSTBP#0
<20> H_DPRSLP# G1 C22
DPRSTP# DSTBP0# H_DSTBP#1
<8> H_DPWR# C19 L24
ITP_BPM#4 DPWR# DSTBP1# H_DSTBP#2
A10
PRDY# MISC DSTBP2#
W24
ITP_BPM#5 B10 AE25 H_DSTBP#3
H_PROCHOT# PREQ# DSTBP3#
B17
PROCHOT#
<20> H_PWRGOOD E4
H_CPUSLP# PWRGOOD
<8,20> H_CPUSLP# A6
ITP_TCK SLP#
A13
ITP_TDI TCK H_A20M#
C12 C2 H_A20M# <20>
ITP_TDO TDI A20M# H_FERR#
A12 D3 H_FERR# <20>
T5 PAD TEST1 TDO FERR# H_IGNNE#
C5 A3 H_IGNNE# <20>
T39 PAD TEST2 TEST1 IGNNE# H_INIT#
F23 B5 H_INIT# <20>
ITP_TMS TEST2 INIT# H_INTR
C11 D1 H_INTR <20>
ITP_TRST# TMS LINT0 H_NMI
B13 D4 H_NMI <20>
TRST# LINT1
LEGACY CPU
THERMAL R458 Add pullups for PWRGOOD and THERMTRIP per INTEL
H_THERMDA B18 C6 H_STPCLK# 200_0402_5%
<34> H_THERMDA H_THERMDC THERMDA DIODE STPCLK# H_SMI# H_STPCLK# <20>
<34> H_THERMDC A18
THERMDC SMI#
B4 H_SMI# <20> 1 2 H_PWRGOOD
+VCCP
<8,20> H_THERMTRIP# C17
THERMTRIP#
TYCO_1612365-1_Dothan
R530
A TEST2 A
1 2
@ 1K_0402_5%
R464
TEST1 1 2
@ 1K_0402_5%
<Title>
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
JCPU1C
R470 JCPU1B
@ 54.9_0402_1% F20 T26
+VCCA_PROC VCCSENSE VCC VSS
1 2 AE7 VCCSENSE VSS A2 F22 VCC VSS U2
1 2 VSSSENSE AF6 A5 G5 U6
R465 VSSSENSE VSS VCC VSS
VSS A8 G21 VCC VSS U22
J2 @ 54.9_0402_1% A11 H6 U24
+1.5VS VSS VCC VSS
2 1 F26
VCCA0 VSS
A14 H22
VCC VSS
V1
10U_1206_6.3V6M
B1 A17 J5 V4
D @ PAD-OPEN 2x2m VCCA1 VSS VCC VSS D
N1 A20 J21 V5
VCCA2 VSS VCC VSS
0.01U_0402_16V7K
1 1 AC26 A23 K22 V21
VCCA3 VSS VCC VSS
SHORT
For test only ,Cmos output +VCCP VSS
A26 U5
VCC VSS
V25
C516
C150
P23 B3 V6 W3
VCCQ0 VSS VCC VSS
W4 B6 V22 W6
2 2 VCCQ1 VSS VCC VSS
B9 W5 W22
+VCCP VSS VCC VSS
CPU Voltage ID Dothan VSS
B12 W21
VCC VSS
W23
D10
D12
VCCP
VCCP
VSS
VSS
B16
B19
Y6
Y22
VCC
VCC
Dothan VSS
VSS
W26
Y2
R412 10K_0402_5%
R411 10K_0402_5%
R410 10K_0402_5%
R409 10K_0402_5%
R408 10K_0402_5%
R413 10K_0402_5%
D14 B22 AA5 Y5
VCCP VSS VCC VSS
D16 B25 AA7 Y21
@ @ @ @ @ @ VCCP VSS VCC VSS
E11 VCCP VSS C1 AA9 VCC VSS Y24
1
E13 VCCP VSS C4 AA11 VCC VSS AA1
E15 VCCP VSS C7 AA13 VCC VSS AA4
POWER, GROUNG, RESERVED SIGNALS AND NC

F10 VCCP VSS C10 AA15 VCC VSS AA6
F14 C15 AA19 AA10
2
VCCP VSS VCC VSS
K6 VCCP VSS C21 AB6 VCC VSS AA14
H_VID0 R433 2 1 0_0402_5% L5 C24 AB8 AA16
VID0 <45> VCCP VSS VCC VSS
L21 VCCP VSS D2 AB10 VCC VSS AA18
H_VID1 R434 2 1 0_0402_5% M6 D5 AB12 AA20
M22 VCCP VSS D7 AB14 VCC VSS AA22
H_VID2 R435 2 1 0_0402_5% N5 D9 AB16 POWER, GROUND AA25
N21 VCCP VSS D11 AB18 VCC VSS AB3
H_VID3 R436 2 1 0_0402_5% P6 D13 AB20 AB5
P22 VCCP VSS D15 AB22 VCC VSS AB7
H_VID4 R437 2 1 0_0402_5% R5 D17 AC9 AB9
R21 VCCP VSS D19 AC11 VCC VSS AB11
H_VID5 R438 2 1 0_0402_5% T6 D21 AC13 AB13
T22 VCCP VSS D23 AC15 VCC VSS AB15
U21 VCCP VSS D26 AC17 VCC VSS AB17
2
2
C C
VSS E3 AC19 VCC VSS AB19
R427 R426 R425 R424 R423 R422 E6 AD8 AB21
+CPU_CORE VSS VCC VSS
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% D6 VCC VSS E8 AD10 VCC VSS AB23
D8 VCC VSS E10 AD12 VCC VSS AB26
D18 E12 AD14 AC2
1
1
VCC VSS VCC VSS
D20 VCC VSS E14 AD16 VCC VSS AC5
D22 VCC VSS E16 AD18 VCC VSS AC8
@ @ @ @ @ @ E5 E18 AE9 AC10
VCC VSS VCC VSS
E7 E20 AE11 AC12
VCC VSS VCC VSS
E9 E22 AE13 AC14
VCC VSS VCC VSS
E17 E25 AE15 AC16
VCC VSS VCC VSS
E19 F1 AE17 AC18
VCC VSS VCC VSS
OPEN OPEN OPEN OPEN OPEN OPEN E21
VCC VSS
F4 AE19
VCC VSS
AC21
F6 F5 AF8 AC24
VCC VSS VCC VSS
F8 F7 AF10 AD1
VCC VSS VCC VSS
F18 F9 AF12 AD4
VCC VSS VCC VSS
F11 AF14 AD7
VSS VCC VSS
F13 AF16 AD9
H_PSI# VSS VCC VSS
<45> PSI# E1 F15 AF18 AD11
PSI# VSS VCC VSS
F17 AD13
H_VID0 VSS VSS
E2 F19 AD15
+VCCP H_VID1 VID0 VSS VSS
F2 F21 AD17
H_VID2 VID1 VSS VSS
F3 F24 AD19
VID2 VSS VSS
R_A H_VID3 G3
VID3 VSS
G2
VSS
AD22
1
H_VID4 G4 G6 M4 AD25
H_VID5 VID4 VSS VSS VSS
Layout close CPU H4
VID5 VSS
G22 M5
VSS VSS
AE3
R155 G23 M21 AE6
+V_CPU_GTLREF 1K_0402_1% VSS VSS VSS
G26 M24 AE8
VSS VSS VSS
+V_CPU_GTLREF AD26 H3 N3 AE10
2
GTLREF VSS VSS VSS

Layout Note: VSS
H5 N6
VSS VSS
AE12
H21 N22 AE14
VSS VSS VSS
R_B 500 mil max length <18> CPU_BSEL0
CPU_BSEL0 C16
BSEL0 VSS
H25 N23
VSS VSS
AE16
1
B CPU_BSEL1 B
<18> CPU_BSEL1 C14 J1 N26 AE18
BSEL1 VSS VSS VSS
J4 P2 AE20
R153 COMP0 VSS VSS VSS
P25 J6 P5 AE23
2K_0402_1% 20 mils COMP1 COMP0 VSS VSS VSS
P26 J22 P21 AE26
5 mils COMP2 COMP1 VSS VSS VSS
AB2 J24 P24 AF2
2
20 mils COMP3 COMP2 VSS VSS VSS

AB1 K2 R1 AF5
COMP3 VSS VSS VSS
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
5 mils K5 R4 AF9
VSS VSS VSS
K21 R6 AF11
VSS VSS VSS
K23 R22 AF13
VSS VSS VSS
1
T3 PAD B2 K26 R25 AF15

RSVD VSS VSS VSS
Resistor placed within T2 PAD C3
RSVD VSS
L3 T3
VSS VSS
AF17
R156
R157
R416
R417
T20 PAD E26 L6 T5 AF19

0.5" of CPU pin.Trace RSVD VSS VSS VSS
T31 PAD AF7 L22 T21 AF21
RSVD VSS VSS VSS
should be at least 25 AC1 L25 T23 AF24
2
T29 PAD RSVD VSS VSS VSS

M1
miles away from any VSS
TYCO_1612365-1_Dothan
other toggling signal. TYCO_1612365-1_Dothan
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+CPU_CORE +CPU_CORE
1 1 1 1 1 1 1 1 1 1
C482 C483 C460 C446 C431 C422 C518 C470 C459 C445
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2 2 2
D D
+CPU_CORE +CPU_CORE
1 1 1 1 1 1 1 1 1 1
C430 C421 C415 C416 C480 C481 C113 C108 C104 C99
2 2 2 2 2 2 2 2 2 2
+CPU_CORE +CPU_CORE
1 1 1 1 1 1 1 1 1 1
C100 C105 C109 C114 C91 C92 C121 C120 C383 C522
2 2 2 2 2 2 2 2 2 2
+CPU_CORE
X7R
1 1 1 1 1
10uF 1206 X5R -> 85 degree High Frequence Decoupling
C512 C507 C502 C469 C442
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C 2 2 2 2 2 C
Near VCORE regulator.

+CPU_CORE
ESR <= 3m ohm
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1 1 1 1
C358
C378
C377
C357
Capacitor > 880 uF
+ + + +
B B
2 2 2 2
+VCCP
1 1 1 1 1 1 1 1 1 1
C664 C665 C666 C667 C668 C669 C670 C671 C672 C673
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2
+VCCP
1
1 1 1 1 1 1 1 1 1 1
+ C525
150U_D2_6.3VM C498 C499 C504 C500 C503 C463 C441 C424 C450 C398
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2 2
A A

<Title>
5 4 3 2 1
5 4 3 2 1
Layout Guide
will show these Alviso CFG[17:3] has internal pull-up
signals routed
differentially. U5B
DMI_TXN0 AA31 G16 CFG0

<21> DMI_TXN0 DMI_TXN1 DMIRXN0 CFG0 MCH_CLKSEL1
<21> DMI_TXN1 AB35 H13 MCH_CLKSEL1 <18>
U5A DMI_TXN2 DMIRXN1 CFG1 MCH_CLKSEL0
<5> H_A#[3..31] H_D#[0..63] <5> <21> DMI_TXN2 AC31 G14 MCH_CLKSEL0 <18>
DMI_TXN3 DMIRXN2 CFG2
<21> DMI_TXN3 AD35
DMIRXN3 CFG3
F16 PAD T25 @
Alviso
D H_A#3 H_D#0 D
G9
HA3# HD0#
E4
CFG4
F15 PAD T26 @
H_A#4 C9 E1 H_D#1 DMI_TXP0 Y31 G15 CFG5
H_A#5 HA4# HD1# H_D#2 <21> DMI_TXP0 DMI_TXP1 DMIRXP0 CFG5 CFG6
E9 F4 <21> DMI_TXP1 AA35 E16
H_A#6 HA5# HD2# H_D#3 DMI_TXP2 DMIRXP1 CFG6 CFG7
B7 H7 <21> DMI_TXP2 AB31 D17
H_A#7 HA6# HD3# H_D#4 DMI_TXP3 DMIRXP2 CFG7
A10 E2 <21> DMI_TXP3 AC35 J16
H_A#8 HA7# HD4# H_D#5 DMIRXP3 CFG8 CFG9
F9 F1 D15
H_A#9 HA8# HD5# H_D#6 DMI_RXN0 CFG9
D8 E3 <21> DMI_RXN0 AA33 E15
H_A#10 HA9# HD6# H_D#7 DMI_RXN1 DMITXN0 CFG10
B10 D3 <21> DMI_RXN1 AB37 D14
DMI
H_A#11 HA10# HD7# H_D#8 DMI_RXN2 DMITXN1 CFG11 CFG12
E10 K7 <21> DMI_RXN2 AC33 E14
H_A#12 HA11# HD8# H_D#9 DMI_RXN3 DMITXN2 CFG12 CFG13
G10 F2 <21> DMI_RXN3 AD37 H12
H_A#13 HA12# HD9# H_D#10 DMITXN3 CFG13
D9 J7 C14
H_A#14 HA13# HD10# H_D#11 DMI_RXP0 CFG14
E11 J8 Y33 H15
CFG/RSVD
H_A#15 HA14# HD11# H_D#12 <21> DMI_RXP0 DMI_RXP1 DMITXP0 CFG15 CFG16
F10 HA15# HD12# H6 <21> DMI_RXP1 AA37 DMITXP1 CFG16 J15
H_A#16 G11 F3 H_D#13 DMI_RXP2 AB33 H14
H_A#17 HA16# HD13# H_D#14 <21> DMI_RXP2 DMI_RXP3 DMITXP2 CFG17 CFG18
G13 HA17# HD14# K8 <21> DMI_RXP3 AC37 DMITXP3 CFG18 G22
H_A#18 C10 H5 H_D#15 G23 CFG19
H_A#19 HA18# HD15# H_D#16 CFG19
C11 HA19# HD16# H1 CFG20 D23
H_A#20 D11 H2 H_D#17 DDR_CLK0 AM33 G25
H_A#21 HA20# HD17# H_D#18 <13> DDR_CLK0 DDR_CLK1 SM_CK0 RSVD21
C12 HA21# HD18# K5 <13> DDR_CLK1 AL1 SM_CK1 RSVD22 G24
H_A#22 B13 K6 H_D#19 AE11 J17
H_A#23 HA22# HD19# H_D#20 DDR_CLK3 SM_CK2 RSVD23
A12 HA23# HD20# J4 <14> DDR_CLK3 AJ34 SM_CK3 RSVD24 A31
H_A#24 F12 G3 H_D#21 DDR_CLK4 AF6 A30
H_A#25 HA24# HD21# H_D#22 <14> DDR_CLK4 SM_CK4 RSVD25
G12 HA25# HD22# H3 AC10 SM_CK5 RSVD26 D26
H_A#26 E12 HA26# HD23# J1 H_D#23 Layout Note: RSVD27 D25
H_A#27 C13 L5 H_D#24 DDR_CLK0# AN33
H_A#28 HA27# HD24# H_D#25 Rote as short <13> DDR_CLK0# DDR_CLK1# SM_CK0#
DDR MUXING
B11 HA28# HD25# K4 <13> DDR_CLK1# AK1 SM_CK1#
H_A#29 D13 HA29# HD26# J5 H_D#26 as possible AE10 SM_CK2#
H_A#30 A13 P7 H_D#27 DDR_CLK3# AJ33
H_A#31 HA30# HD27# H_D#28 <14> DDR_CLK3# DDR_CLK4# SM_CK3#
F13 L7 AF5 R57
HA31# HD28# <14> DDR_CLK4# SM_CK4#
T1 PAD J3 H_D#29 AD10 56_0402_5%
TP_H_PCREQ# HD29# H_D#30 SM_CK5# H_THERMTRIP#
A11 P5 1 @ 2 +VCCP
<5> H_REQ#[0..4]
HOST
H_REQ#0 HPCREQ# HD30# H_D#31 DDR_CKE0
A7 HREQ#0 HD31# L3 <13> DDR_CKE0 AP21 SM_CKE0
C H_REQ#1 H_D#32 M_OCDOCMP0 DDR_CKE1 C
D7 HREQ#1 HD32# U7 <13> DDR_CKE1 AM21 SM_CKE1
H_REQ#2 B8 V6 H_D#33 M_OCDOCMP1 DDR_CKE2 AH21
H_REQ#3 HREQ#2 HD33# H_D#34 <14> DDR_CKE2 DDR_CKE3 SM_CKE2
C7 HREQ#3 HD34# R6 <14> DDR_CKE3 AK21 SM_CKE3
H_REQ#4 A8 R5 H_D#35 J23
HREQ#4 HD35# BM_BUSY# PM_BMBUSY# <21>
40.2_0402_1%
40.2_0402_1%
H_ADSTB#0 B9 P3 H_D#36 DDR_SCS#0 AN16 J21 PM_EXTTS#0
<5> H_ADSTB#0 HADSTB#0 HD36# <13> DDR_SCS#0 SM_CS0# EXT_TS0#
1
H_ADSTB#1 E13 T8 H_D#37 DDR_SCS#1 AM14 H22 PM_EXTTS#1
<5> H_ADSTB#1 HADSTB#1 HD37# <13> DDR_SCS#1 SM_CS1# EXT_TS1#
R7 H_D#38 DDR_SCS#2 AH15 F5
HD38# <14> DDR_SCS#2 SM_CS2# THRMTRIP# H_THERMTRIP# <5,20>
R477
R476
AB1 R8 H_D#39 DDR_SCS#3 AG16 AD30
<18> CLK_MCH_BCLK# HCLKN HD39# H_D#40 <14> DDR_SCS#3 SM_CS3# PWROK PLTRST_R# VGATE <18,21,45>
AB2 U8 AE29 1 2
CLK PM
<18> CLK_MCH_BCLK HCLKP HD40# H_D#41 M_OCDOCMP0 RSTIN# PLTRST_MCH# <19>
R4 AF22 R492 100_0402_1%
2
<5> H_DSTBN#[0..3] H_DSTBN#0 HD41# H_D#42 M_OCDOCMP1 SM_OCDCOMP0
G4 T4 AF16 R384 2 1 10K_0402_5%
H_DSTBN#1 HDSTBN#0 HD42# H_D#43 SM_OCDCOMP1
Layout Guide will show K1
HDSTBN#1 HD43#
T5 AP14
SM_ODT0 DREF_CLKN
A24 DREFCLK# <18>
H_DSTBN#2 R3 R1 H_D#44 AL15 A23 @
these signals routed H_DSTBN#3 HDSTBN#2 HD44# H_D#45 @ @ SM_ODT1 DREF_CLKP DREFCLK <18>
V3 T3 AM11 D37
differentially. <5> H_DSTBP#[0..3] H_DSTBP#0 G5
HDSTBN#3 HD45#
V8 H_D#46 +2.5V AN10
SM_ODT2 DREF_SSCLKP
C37
SSC_DREFCLK <18>
H_DSTBP#1 HDSTBP#0 HD46# H_D#47 SM_ODT3 DREF_SSCLKN SSC_DREFCLK# <18>
K2 U6 R387 2 1 10K_0402_5%
H_DSTBP#2 HDSTBP#1 HD47# H_D#48 R484 1 80.6_0402_1% SMRCOMPN
R2 W6 2 AK10
H_DSTBP#3 HDSTBP#2 HD48# H_D#49 SMRCOMPP SMRCOMPN
W4 U3 AK11 AP37 @
HDSTBP#3 HD49# SMRCOMPP NC1
0.1U_0402_16V4Z
H8 V5 H_D#50 AF37 AN37
<5> H_DINV#0 HDINV#0 HD50# +SDREF_DIMM SMVREF0 NC2
0.1U_0402_16V4Z
K3 W8 H_D#51 AD1 AP36
<5> H_DINV#1 HDINV#1 HD51# SMVREF1 NC3
1
T7 W7 H_D#52 +VCCP AE27 AP2
<5> H_DINV#2 HDINV#2 HD52# 1 1 SMXSLEWIN NC4
U5 U2 H_D#53 AE28 AP1 R366 +2.5VS
<5> H_DINV#3 HDINV#3 HD53# SMXSLEWOUT NC5
C428
C419
U1 H_D#54 R489 AF9 AN1 10K_0402_5%
HD54# H_D#55 80.6_0402_1% SMYSLEWIN NC6 PM_EXTTS#0
Y5 AF10 B1 2 1
H_RESET# HD55# H_D#56 2 2 SMYSLEWOUT NC7
H10 Y2 A2
2
<5> H_RESET# HCPURST# HD56# NC8
1
+VCCP
54.9_0402_1%
54.9_0402_1%
V4 H_D#57 B37 R365
H_ADS# HD57# H_D#58 NC9 10K_0402_5%
NC
<5>
H_ADS# F8 Y7 A36
HADS# HD58# NC10
100_0402_1%
R41
R66
H_TRDY# B5 W1 H_D#59 A37 PM_EXTTS#1 2 1
<5>
H_TRDY# HTRDY# HD59# NC11
1
G6 W3 H_D#60
<5>
H_DPWR# HDPWR# HD60#
R372
H_DRDY# F7 Y3 H_D#61
2
2
<5>
H_DRDY# H_DEFER# HDRDY# HD61# H_D#62 +VCCP
E6 Y6 ALVISO_BGA1257
<5>
H_DEFER# TP_H_EDRDY# F6 HDEFER# HD62# H_D#63
@ W2
T27 PAD HEDRDY# HD63#
B H_HITM# D6 Refer to sheet 6 for FSB CFG0 R367 2 1 10K_0402_5% B
2
<5> H_HITM# HHITM#
<5> H_HIT#
H_HIT# D4
HHIT# HVREF
J11 H_VREF CFG[2:0] frequency select
0.1U_0402_16V7K
H_LOCK# B3 C1 H_XRCOMP CFG6 R369 1 2 2.2K_0402_5%
<5> H_LOCK# HLOCK# HXRCOMP
200_0402_1%
H_BR0# E7 C2 H_XSCOMP 1
<5> H_BR0# HBREQ0# HXSCOMP
1
<5> H_BNR#
H_BNR# A5
HBNR# HYRCOMP
T1 H_YRCOMP Low = DMI x 2 CFG5 R370 1 2 2.2K_0402_5%
CFG5
C379
R376
H_BPRI# D5 L1 H_YSCOMP
<5> H_BPRI# HBPRI# HYSCOMP
High = DMI x 4
*
H_DBSY# C6 D1 H_SWNG0 CFG7 R368 1 2 2.2K_0402_5%
<5> H_DBSY# H_R_CPUSLP# HDBSY# HXSWING H_SWNG1 2
G8 P1
HCPUSLP# HYSWING
H_RS#0 A4 Low = DDR-II CFG9 R394 1 2 @ 2.2K_0402_5%
2
HRS0#
CFG6
24.9_0402_1%
24.9_0402_1%
H_RS#1 C5
HRS1#
1
High = DDR-I
*
H_RS#2 B4
HRS2#
<5> H_RS#[0..2]
Low = DT/Transportable CPU
R77
R44
ALVISO_BGA1257 CFG7
High = Mobile CPU
*
CFG12 R374 1 2 @ 2.2K_0402_5%
2
10/20 mils
Low = Reverse Lane CFG13 R375 1 2 @ 2.2K_0402_5%
CFG9
High = Normal Operation
*
R418 CFG16 R430 1 2 @ 2.2K_0402_5%
0_0402_5% CFG[17:3] have internal pull-up
<5,20> H_CPUSLP#
H_CPUSLP# 1 2 H_R_CPUSLP#
+VCCP +VCCP
00 = Reserved
01 = XOR Mode Enabled
CFG[13:12] 10 = All Z Mode Enabled
11 = Normal Operation (Default)
*
221_0603_1%
221_0603_1%
1
+2.5VS
Note: CFG16
Low = Disabled
R397
R67
"Do not install R for Dothan-A, (FSB Dynamic 3.5 k reserve for choose
High = Enabled
Install R97 for Dothan-B" ODT)
* CFG18 R36 1 2 @ 1K_0402_5%
2
CFG18 Low = 1.05V (Default)

*
H_SWNG0 H_SWNG1 CFG19 1 2
0.1U_0402_16V4Z
R37 @ 1K_0402_5%
A (VCC Select) High = 1.5V A
0.1U_0402_16V4Z
2.2K_0402_5% @ 2 1 R35
1
1
100_0402_1%
100_0603_1%
1 1 CFG[19:18] have internal pull-down

CFG19 Low = 1.05V (Default)
R388
R73
*
2.2K_0402_5% @ 2 1 R38
(VTT Select) High = 1.2V

C362
C385
3.5 k reserve for choose

2 2
2

<Title>
5 4 3 2 1
5 4 3 2 1
D D
U5C U5D
DDR_A_BS#0 DDR_A_D0 DDR_A_D[0..63] <13> DDR_B_BS#0
<13> DDR_A_BS#0 AK15 AG35 <14> DDR_B_BS#0 AJ15 AE31
DDR_A_BS#1 SA_BS0# SADQ0 DDR_A_D1 DDR_B_BS#1 SB_BS0# SBDQ0
<13> DDR_A_BS#1 AK16 AH35 <14> DDR_B_BS#1 AG17 AE32
DDR_A_BS#2 SA_BS1# SADQ1 DDR_A_D2 DDR_B_BS#2 SB_BS1# SBDQ1
AL21 AL35 AG21 AG32
T38 PAD SA_BS2# SADQ2 DDR_A_D3 T37 PAD SB_BS2# SBDQ2
<13> DDR_A_DM[0..7] AL37 AG36
DDR_A_DM0 SADQ3 DDR_A_D4 SBDQ3
AJ37 AH36 AF32 AE34
DDR_A_DM1 SA_DM0 SADQ4 DDR_A_D5 SB_DM0 SBDQ4
AP35 SA_DM1 SADQ5 AJ35 AK34 SB_DM1 SBDQ5 AE33
DDR_A_DM2 AL29 AK37 DDR_A_D6 AK27 AF31
AP24 SA_DM3 SADQ7 AL34 AK24 SB_DM3 SBDQ7 AF30
DDR_A_DM4 AP9 AM36 DDR_A_D8 AJ10 AH33
AP4 SA_DM5 SADQ9 AN35 AK5 SB_DM5 SBDQ9 AH32
DDR_A_DM6 AJ2 AP32 DDR_A_D10 AE7 AK31
AD3 SA_DM7 SADQ11 AM31 AB7 SB_DM7 SBDQ11 AG30
AM34 DDR_A_D12 AG34
<13> DDR_A_DQS[0..7] DDR_A_DQS0 SADQ12 DDR_A_D13 SBDQ12
AK36 SA_DQS0 SADQ13 AM35 This Symbol as same AF34 SB_DQS0 SBDQ13 AG33
DDR_A_DQS1 AP33 AL32 DDR_A_D14 AK32 AH31
DDR_A_DQS2 SA_DQS1 SADQ14 DDR_A_D15
as Intel CRB SB_DQS1 SBDQ14
AN29 SA_DQS2 SADQ15 AM32 AJ28 AJ31
DDR_A_DQS3 AP23 AN31 DDR_A_D16 schematic, So Layout AK23
SB_DQS2 SBDQ15
AK30
DDR_A_DQS4 SA_DQS3 SADQ16 DDR_A_D17 Guide will show these SB_DQS3 SBDQ16
AM8 SA_DQS4 SADQ17 AP31 AM10 SB_DQS4 SBDQ17 AJ30
DDR_A_DQS5 AM4 AN28 DDR_A_D18 signals routed AH6 AH29
DDR_A_DQS6 SA_DQS5 SADQ18 DDR_A_D19 SB_DQS5 SBDQ18
AJ1 SA_DQS6 SADQ19 AP28 differentially. AF8 SB_DQS6 SBDQ19 AH28
DDR_A_DQS7 AE5 AL30 DDR_A_D20 AB4 AK29
SA_DQS7 SADQ20 DDR_A_D21 SB_DQS7 SBDQ20
SADQ21 AM30 SBDQ21 AH30
AK35 AM28 DDR_A_D22 AF35 AH27
DDR SYSTEM MEMORY B

SA_DQS0# SADQ22 DDR_A_D23 SB_DQS0# SBDQ22
AP34 AL28 AK33 AG28
DDR MEMORY SYSTEM A

AN30 SA_DQS2# SADQ24 AP27 AK28 SB_DQS2# SBDQ24 AF24
AN23 AM27 DDR_A_D25 AJ23 AG23
C SA_DQS3# SADQ25 DDR_A_D26 SB_DQS3# SBDQ25 C
AN8 SA_DQS4# SADQ26 AM23 AL10 SB_DQS4# SBDQ26 AJ22
AM5 AM22 DDR_A_D27 AH7 AK22
AH1 SA_DQS6# SADQ28 AL23 AF7 SB_DQS6# SBDQ28 AH24
AE4 AM24 DDR_A_D29 AB5 AH23
<13> DDR_A_MA[0..13] SADQ30 AN22 <14> DDR_B_MA[0..13] SBDQ30 AG22
DDR_A_MA0 AL17 AP22 DDR_A_D31 DDR_B_MA0 AH17 AJ21
DDR_A_MA1 SA_MA0 SADQ31 DDR_A_D32 DDR_B_MA1 SB_MA0 SBDQ31
AP17 SA_MA1 SADQ32 AM9 AK17 SB_MA1 SBDQ32 AG10
DDR_A_MA2 AP18 AL9 DDR_A_D33 DDR_B_MA2 AH18 AG9
AM17 AL6 AJ18 AG8
AN18 AP7 AK18 AH8
AM18 AP11 AJ19 AH11
AL19 AP10 AK19 AH10
AP20 AL7 AH19 AJ9
AM19 AM7 AJ20 AK9
AL20 AN5 AH20 AJ7
AM16 AN6 AJ16 AK6
AN20 AN3 AG18 AJ4
AM20 AP3 AG20 AH5
AM15 AP6 AG15 AK8
SA_MA13 SADQ44 DDR_A_D45 SB_MA13 SBDQ44
AM6 AJ8
DDR_A_CAS# SADQ45 DDR_A_D46 DDR_B_CAS# SBDQ45
<13> DDR_A_CAS# AN15 AL4 <14> DDR_B_CAS# AH14 AJ5
DDR_A_RAS# SA_CAS# SADQ46 DDR_A_D47 DDR_B_RAS# SB_CAS# SBDQ46
<13> DDR_A_RAS# AP16 AM3 <14> DDR_B_RAS# AK14 AK4
T36 PAD TP_MA_RCVENIN# SA_RAS# SADQ47 DDR_A_D48 T33 PAD TP_MB_RCVENIN# SB_RAS# SBDQ47
AF29 AK2 AF15 AG5
T35 PAD TP_MA_RCVENOUT# SA_RCVENIN# SADQ48 DDR_A_D49 T34 PAD TP_MB_RCVENOUT# SB_RCVENIN# SBDQ48
AF28 AK3 AF14 AG4
DDR_A_WE# SA_RCVENOUT# SADQ49 DDR_A_D50 DDR_B_WE# SB_RCVENOUT# SBDQ49
<13> DDR_A_WE# AP15 AG2 <14> DDR_B_WE# AH16 AD8
SA_WE# SADQ50 DDR_A_D51 SB_WE# SBDQ50
AG1 AD9
SADQ51 DDR_A_D52 SBDQ51
AL3 AH4
AM2 AG6
AH3 AE8
AG3 AD7
AF3 AC5
AE3 AB8
B SADQ57 DDR_A_D58 SBDQ57 B
AD6 AB6
AC4 AA8
AF2 AC8
AF1 AC7
AD4 AA4
AD5 AA5
SADQ63 SBDQ63
ALVISO_BGA1257 ALVISO_BGA1257
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+2.5VS
+1.5VS_PCIE
R40
R29 @ 3K_0402_5% U5G 24.9_0603_1%
1 2 H24 SDVOCTRL_DATA D36 PEGCOMP 1 2
EXP_COMPI
1 2 R30 H25 SDVOCTRL_CLK
EXP_ICOMPO
D34
@ 3K_0402_5% AB29 PEG_RXN[0..15]
MISC
D <18> CLK_MCH_3GPLL# GCLKN PEG_RXN[0..15] <16> D
AC29 GCLKP E30 PEG_RXN0
<18> CLK_MCH_3GPLL EXP_RXN0/SDVO_TVCLKIN# PEG_RXN1
F34
EXP_RXN1/SDVO_INT# PEG_RXN2
G30
EXP_RXN2/SDVO_FLDSTALL# PEG_RXN3
<17> Y/G A15 H34
TVDAC_A EXP_RXN3 PEG_RXN4
<17> COMP/B C16 J30
TVDAC_B EXP_RXN4 PEG_RXN5
<17> C/R A17 K34
TVDAC_C EXP_RXN5 PEG_RXN6
J18 L30
TV_REFSET EXP_RXN6
1
1
B15 M34 PEG_RXN7
TV_IRTNA EXP_RXN7
150_0402_1%
150_0402_1%
150_0402_1%
B16 N30 PEG_RXN8

1@ 1@ 1@ 1@ TV_IRTNB EXP_RXN8 PEG_RXN9
B17 P34
TV
R428 R392 TV_IRTNC EXP_RXN9 PEG_RXN10
R30
EXP_RXN10
R32
R33
R34
4.99K_0603_1% 0_0402_5% T34 PEG_RXN11

2
EXP_RXN11 PEG_RXN12 +2.5VS

1 2 EXP_RXN12 U30
V34 PEG_RXN13
EXP_RXN13 PEG_RXN14
EXP_RXN14 W30
CLK_DDC2 E24 Y34 PEG_RXN15
<17> CLK_DDC2 DAT_DDC2 DDCCLK EXP_RXN15 PEG_RXP[0..15]
<17> DAT_DDC2 E23 DDCDATA PEG_RXP[0..15] <16>
E21 D30 PEG_RXP0
<17> CRT_BLU BLUE EXP_RXP0/SDVO_TVCLKIN PEG_RXP1
D21 BLUE# EXP_RXP1/SDVO_INT E34
C20 F30 PEG_RXP2 1 2 LCD_CLK
<17> CRT_GRN GREEN EXP_RXP2/SDVO_FLDSTALL
B20 G34 PEG_RXP3 R362 2.2K_0402_5%
GREEN# EXP_RXP3 PEG_RXP4 LCD_DAT
<17> CRT_RED A19 RED EXP_RXP4 H30 This Symbol as same 1 2
B19 J34 PEG_RXP5 R363 2.2K_0402_5%
RED# EXP_RXP5 PEG_RXP6
as Intel CRB LCTLA_CLK
H21 K30 1 2
VGA
<17> VSYNC VSYNC EXP_RXP6 PEG_RXP7 schematic, So Layout
G21 L34 R385 2.2K_0402_5%
<17> HSYNC HSYNC EXP_RXP7 Guide will show these
PCI - EXPRESS GRAPHICS

1 2 J20 M30 PEG_RXP8 1 2 LCTLB_DAT
R429 REFSET EXP_RXP8 PEG_RXP9 R364 2.2K_0402_5%
EXP_RXP9 N34 signals routed
255_0402_1% P30 PEG_RXP10 1 2 CLK_DDC2
<16,32> BIA EXP_RXP10 PEG_RXP11 differentially. R360 2.2K_0402_5%
EXP_RXP11 R34
T30 PEG_RXP12 1 2 DAT_DDC2
<16> BK_EN EXP_RXP12 PEG_RXP13
U34 R361 2.2K_0402_5%
EXP_RXP13 PEG_RXP14
EXP_RXP14 V30
C R396 100K_0402_1% PEG_RXP15 C
EXP_RXP15 W34
1 2 BIA E25 PEG_TXN[0..15]
BK_EN LBKLT_CTL PEG_TXN0 PEG_TXN[0..15] <16>
1 2 F25 LBKLT_EN EXP_TXN0/SDVOB_RED# E32
LCTLA_CLK C23 F36 PEG_TXN1
R404100K_0402_1% LCTLB_DAT LCTLA_CLK EXP_TXN1/SDVOB_GREEN# PEG_TXN2
C22 LCTLB_DATA EXP_TXN2/SDVOB_BLUE# G32
LCD_CLK F23 H36 PEG_TXN3
<16> LCD_CLK LDDC_CLK EXP_TXN3/SDVOB_CLKN
LCD_DAT F22 J32 PEG_TXN4
<16> LCD_DAT LDDC_DATA EXP_TXN4/SDVOC_RED#
EN_LCDVDD F26 K36 PEG_TXN5
<16> EN_LCDVDD LVDD_EN EXP_TXN5/SDVOC_GREEN# PEG_TXN6
2 1 C33
LIBG EXP_TXN6/SDVOC_BLUE#
L32
C31 M36 PEG_TXN7
R3781.5K_0402_1% LVBG EXP_TXN7/SDVOC_CLKN PEG_TXN8
F28 N32
LVREFH EXP_TXN8 PEG_TXN9
F27 P36
LVREFL EXP_TXN9 PEG_TXN10
R32
LVDS_AC- EXP_TXN10 PEG_TXN11
<16> LVDS_AC- B30 T36
LVDS_AC+ LACLKN EXP_TXN11 PEG_TXN12
<16> LVDS_AC+ B29 U32
LACLKP EXP_TXN12
LVDS
LVDS_BC- C25 V36 PEG_TXN13

<16> LVDS_BC- LBCLKN EXP_TXN13
LVDS_BC+ C24 W32 PEG_TXN14
<16> LVDS_BC+ LBCLKP EXP_TXN14
Y36 PEG_TXN15
LVDS_A0- EXP_TXN15
<16> LVDS_A0- B34
LVDS_A1- LADATAN0 PEG_TXP[0..15]
<16> LVDS_A1- B33 PEG_TXP[0..15] <16>
LVDS_A2- LADATAN1 PEG_TXP0
<16> LVDS_A2- B32 D32
LADATAN2 EXP_TXP0/SDVOB_RED PEG_TXP1
E36
EXP_TXP1/SDVOB_GREEN PEG_TXP2
F32
LVDS_A0+ EXP_TXP2/SDVOB_BLUE PEG_TXP3
<16> LVDS_A0+ A34 G36
LVDS_A1+ LADATAP0 EXP_TXP3/SDVOB_CLKP PEG_TXP4
<16> LVDS_A1+ A33 H32
LVDS_A2+ LADATAP1 EXP_TXP4/SDVOC_RED PEG_TXP5
<16> LVDS_A2+ B31 J36
LADATAP2 EXP_TXP5/SDVOC_GREEN PEG_TXP6
K32
EXP_TXP6/SDVOC_BLUE PEG_TXP7
L36
EXP_TXP7/SDVOC_CLKP PEG_TXP8
M32
LVDS_B0- EXP_TXP8 PEG_TXP9
<16> LVDS_B0- C29 N36
LVDS_B1- LBDATAN0 EXP_TXP9 PEG_TXP10
<16> LVDS_B1- D28 P32
LVDS_B2- LBDATAN1 EXP_TXP10 PEG_TXP11
<16> LVDS_B2- C27 R36
B LBDATAN2 EXP_TXP11 PEG_TXP12 B
T32
EXP_TXP12 PEG_TXP13
U36
EXP_TXP13 PEG_TXP14
V32
LVDS_B0+ EXP_TXP14 PEG_TXP15
<16> LVDS_B0+ C28 W36
LVDS_B1+ LBDATAP0 EXP_TXP15
<16> LVDS_B1+ D27
LVDS_B2+ LBDATAP1
<16> LVDS_B2+ C26
LBDATAP2
ALVISO_BGA1257
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+3VS
Close B26,B25,A25
0.022U_0402_16V7K
U5F
W=20 mils
0.1U_0402_16V4Z
K13 AM37 V1.8_DDR_CAP1 1 1
VTT0 VCCSM0
C355
J13 AH37 V1.8_DDR_CAP2
VTT1 VCCSM1 V1.8_DDR_CAP5 U5E +1.5VS
K12 VTT2 VCCSM2 AP29
W11 VTT3 VCCSM3 AD28
2 2
C366
V11 VTT4 VCCSM4 AD27 +VCCP T29 VCC0 VCCA_TVDACA0 F17
C339 0.022U_0402_16V7K
U11 VTT5 VCCSM5 AC27 R29 VCC1 VCCA_TVDACA1 E17
0.022U_0402_16V7K
T11 VTT6 VCCSM6 AP26 N29 VCC2 VCCA_TVDACB0 D18
10U_1206_6.3V6M
POWER
C336 0.022U_0402_16V7K
0.1U_0402_16V4Z
R11 AN26 V1.8_DDR_CAP1 M29 C18
VTT7 VCCSM7 VCC3 VCCA_TVDACB1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P11 AM26 V1.8_DDR_CAP2 K29 F18 1 1 1 1 1 1 +1.5VS_PM
VTT8 VCCSM8 VCC4 VCCA_TVDACC0
C372
N11 AL26 V1.8_DDR_CAP5 1 1 J29 E18 +2.5VS_PM
VTT9 VCCSM9 VCC5 VCCA_TVDACC1
0.1U_0402_16V4Z
10U_1206_6.3V6M
C393
C388
0.1U_0402_16V4Z
M11 AK26 1 1 1 V28
VTT10 VCCSM10 VCC6
POWER
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.01U_0402_16V7K
D D
0.1U_0402_16V4Z
L11 AJ26 U28 H18
VTT11 VCCSM11 VCC7 VCCA_TVBG 2 2 2 2 2 2 +2.5VS
C478
C443
C468
C353
C341
K11 AH26 T28 G18 1 1
VTT12 VCCSM12 2 2 VCC8 VSSA_TVBG
C349
W10 AG26 R28
VTT13 VCCSM13 2 2 2 VCC9
C354
V10 AF26 P28 D19 1 1
VTT14 VCCSM14 VCC10 VCCD_TVDAC
C346
C352
0.1U_0402_16V4Z
+VCCP U10 AE26 N28 H17
VTT15 VCCSM15 VCC11 VCCDQ_TVDAC 2 2
10U_1206_6.3V6M
T10 AP25 M28 1@
VTT16 VCCSM16 VCC12
R10 AN25 L28 B26 R736 1 2 0_0603_5% +1.5VS
VTT17 VCCSM17 VCC13 VCCD_LVDS0 +1.5VS_PM 2@ R737 1 2 2
P10
VTT18 VCCSM18
AM25 K28
VCC14 VCCD_LVDS1
B25 2 0_0603_5% 1 1
C334
C342
N10 AL25 J28 A25
VTT19 VCCSM19 VCC15 VCCD_LVDS2
2.2U_0805_10V6K
4.7U_0805_6.3V6K
M10 AK25 H28 +2.5VS_PM 2@ R738 1 2 0_0603_5%

VTT20 VCCSM20 VCC16
K10 AJ25 G28 A35 R739 1 2 0_0603_5% +2.5VS
VTT21 VCCSM21 VCC17 VCCA_LVDS 1@ 2 2
1 1 J10 VTT22 VCCSM22 AH25 Note : All VCCSM pin V27 VCC18 +2.5VS
C392
C391
Y9 VTT23 VCCSM23 AG25 U27 VCC19 VCCHV0 B22 +2.5VS

W9 AF25 shorted internally. T27 B21 R740 1 2 0_0603_5% 1@
VTT24 VCCSM24 VCC20 VCCHV1
2
U9 AE25 R27 A21 +2.5VS_LVDSPM
2 2 VTT25 VCCSM25 VCC21 VCCHV2 C329 R741
R9 VTT26 VCCSM26 AE24 P27 VCC22 1 1
P9 AE23 N27 B28 4.7U_0805_6.3V6K C340 0_0603_5%
VTT27 VCCSM27 V1.8_DDR_CAP6 VCC23 VCCTX_LVDS0 0.1U_0402_16V4Z
N9 VTT28 VCCSM28 AE22 M27 VCC24 VCCTX_LVDS1 A28 2@
M9 AE21 V1.8_DDR_CAP4 L27 A27 +1.5VS_DDRDLL L14 +1.5VS
1
VTT29 VCCSM29 VCC25 VCCTX_LVDS2 2 2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L9 AE20 V1.8_DDR_CAP3 K27
VTT30 VCCSM30 VCC26
J9 VTT31 VCCSM31 AE19 1 1 1 J27 VCC27 VCCA_SM0 AF20 2 1
C429
C465
C475
0.1U_0402_16V4Z
N8 AE18 H27 AP19 0_0603_5%
VTT32 VCCSM32 VCC28 VCCA_SM1 +1.5VS_PCIE +1.5VS
100U_D2_6.3VM
0.1U_0402_16V4Z
M8 VTT33 VCCSM33 AE17 K26 VCC29 VCCA_SM2 AF19 1
N7 AE16 H26 AF18 1 L26 1
VTT34 VCCSM34 2 2 2 VCC30 VCCA_SM3
C473
M7 AE15 K25 + 1 2
VTT35 VCCSM35 VCC31
C131
C140
0.47U_0603_16V7K
0.1U_0402_16V4Z
N6 AE14 J25 AE37 0_0603_5%
VTT36 VCCSM36 VCC32 VCC3G0 +1.5VS_3GPLL +1.5VS
10U_1206_6.3V6M
10U_1206_6.3V6M
M6 AP13 K24 W37 R134 L13
VTT37 VCCSM37 VCC33 VCC3G1 2 2 2
220U_D2_4VM
A6 AN13 K23 U37 1 0.5_0805_1% CHB1608U301_0603 1
VTT38 VCCSM38 VCC34 VCC3G2
N5 VTT39 VCCSM39 AM13 Note: Place near chip. K22 VCC35 VCC3G3 R37 1 1 1 2 3GRLL_R 2 1
10U_1206_6.3V6M
C380
C433
C438
+
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 M5 VTT40 VCCSM40 AL13 K21 VCC36 VCC3G4 N37
C29
N4 VTT41 VCCSM41 AK13 W20 VCC37 VCC3G5 L37

+2.5V 2
C452
M4 VTT42 VCCSM42 AJ13 U20 VCC38 VCC3G6 J37 1 1 1
2 2 2
C128
C C
N3 VTT43 VCCSM43 AH13 T20 VCC39
2
C399
C126
M3 VTT44 VCCSM44 AG13 K20 VCC40
N2 VTT45 VCCSM45 AF13 V19 VCC41 2 2 2
10U_1206_6.3V6M
10U_1206_6.3V6M
M2 VTT46 VCCSM46 AE13 U19 VCC42 VCCA_3GPLL0 Y29

330U_D2E_2.5VM
B2 VTT47 VCCSM47 AP12 1 K19 VCC43 VCCA_3GPLL1 Y28
V1 VTT48 VCCSM48 AN12 1 1 W18 VCC44 VCCA_3GPLL2 Y27
C127
C135
C130
N1 AM12 + V18 +2.5VS_3GBG +2.5VS

VTT49 VCCSM49 VCC45 L9
M1 AL12 T18
VTT50 VCCSM50 VCC46
G1 AK12 K18 F37 2 1
VTT51 VCCSM51 2 2 2 VCC47 VCCA_3GBG
AJ12 K17 G37 1 1
VCCSM52 VCC48 VSSA_3GBG 0_0603_5%
1 1 1 AH12
VCCSM53
C28
C74
C52
0.47U_0603_16V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
AG12 AC1 H20 VCC_SYNC C365 C31

VCCSM54 +1.5VS VCCD_HMPLL1 VCC_SYNC
AF12 AC2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCCSM55 VCCD_HMPLL2 2 2
AE12 +1.5VS_DPLLA B23 F19 +2.5VS
2 2 2 VCCSM56 VCCA_DPLLA VCCA_CRTDAC0
AD11 +1.5VS_DPLLB C35 E19
VCCSM57 VCCA_DPLLB VCCA_CRTDAC1
0.1U_0402_16V4Z
AC11 +1.5VS_HPLL AA1 G19
VCCSM58 VCCA_HPLL VSSA_CRTDAC
AB11 +1.5VS_MPLL AA2
VCCSM59 VCCA_MPLL
AB10
VCCSM60
VCCSM61
AB9 1 1 Route VSSA3GBG gnd from GMCH to
C367
AP8 V1.8_DDR_CAP6 ALVISO_BGA1257
VCCSM62
AM1 V1.8_DDR_CAP4 decoupling cap ground lead and
VCCSM63
VCCSM64
AE1 V1.8_DDR_CAP3
2 2 C363 then connect to the gnd plane.
0.022U_0402_16V7K
ALVISO_BGA1257 +2.5VS
1
+VCCP +2.5V R28
0_0402_5% +VCCP
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
B VCC_SYNC B
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1
1
10U_1206_6.3V6M
0.1U_0402_16V4Z
1 1 1 1 1 1
C674
C675
C676
C677
C678
C413
C412
C408
C411
C418
C420
R31
C680
C681
C682
C683
C684
C685
1 1 @ 0_0402_5%
2 2 2 2 2 2 2 2 2 2 2
C30
C371
2 2 2 2 2 2
2 2 2
L19 +1.5VS_DPLLB L11 +1.5VS_HPLL L23 +1.5VS_MPLL L20 +1.5VS_DPLLA

CHB1608U301_0603 CHB1608U301_0603 CHB1608U301_0603 CHB1608U301_0603
+1.5VS 1 2 +1.5VS 1 2 +1.5VS 1 2 +1.5VS 1 2
0.1U_0402_16V4Z
330U_D2E_2.5VM
0.1U_0402_16V4Z
330U_D2E_2.5VM
330U_D2E_2.5VM
0.1U_0402_16V4Z
0.1U_0402_16V4Z
330U_D2E_2.5VM
1 1 1 1
1 1 1 1
C348
C347
C81
C404
C330
C345
C403
C409
+ + + +
2 2 2 2 2 2 2 2
A A
+VCCP +2.5VS +VCCP +3VS

R805 R806
D21 D22
1 2 2 1 1 2 2 1 Security Classification Compal Secret Data
10K_0402_5% 1N4148_SOD80 10K_0402_5% 1N4148_SOD80 Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
<Title>
@ @ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@ @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 4 3 2 1
5 4 3 2 1
+VCCP U5H +2.5V
D D
L12 AB12
VTT_NCTF17 VCCSM_NCTF31
M12 AC12
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
N12 AD12
P12 AB13 1 1 1 1 1 1
R12 AC13
C686
C687
C688
C689
C690
C691
T12 AD13
U12 AC14
VTT_NCTF11 VCCSM_NCTF25 2 2 2 2 2 2
V12 AD14
W12 AC15
VTT_NCTF9 VCCSM_NCTF23 U5I U5J
L13 AD15
M13 AC16
N13 VTT_NCTF6 VCCSM_NCTF20 AD16 Y1 VSS271 AL24 VSS267
P13 VTT_NCTF5 VCCSM_NCTF19 AC17 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
R13 VTT_NCTF4 VCCSM_NCTF18 AD17 G2 VSS269 A26 VSS265 VSS66 AD32
T13 VTT_NCTF3 VCCSM_NCTF17 AC18 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
U13 VTT_NCTF2 VCCSM_NCTF16 AD18 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33
VCCSM_NCTF13 AC20 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33
VCCSM_NCTF12 AD20 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
VSS
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
VSS
AA12 VSS_NCTF67 VCCSM_NCTF10 AD21 AH2 VSS254 VSS188 D12 AA27 VSS126 VSS58 J33
Y13 VSS_NCTF66 VCCSM_NCTF9 AC22 AL2 VSS253 VSS187 J12 AB27 VSS125 VSS57 K33
AA13 VSS_NCTF65 VCCSM_NCTF8 AD22 AN2 VSS252 VSS186 A14 AF27 VSS124 VSS56 L33
L14 VSS_NCTF64 VCCSM_NCTF7 AC23 A3 VSS251 VSS185 B14 AG27 VSS123 VSS55 M33
M14 VSS_NCTF63 VCCSM_NCTF6 AD23 C3 VSS250 VSS184 F14 AJ27 VSS122 VSS54 N33
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
C C
W14 VSS_NCTF56 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
Y14 VSS_NCTF55 VCC_NCTF78 L17 +VCCP P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
AA14 VSS_NCTF54 VCC_NCTF77 M17 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
AB14 VSS_NCTF53 VCC_NCTF76 N17 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
L15 VSS_NCTF52 VCC_NCTF75 P17 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
M15 T17 AN4 K16 G29 AB34
NCTF
VSS_NCTF51 VCC_NCTF74 VSS238 VSS172 VSS110 VSS42

N15 VSS_NCTF50 VCC_NCTF73 U17 E5 VSS237 VSS171 AL16 H29 VSS109 VSS41 AC34
P15 V17 W5 C17 L29 AD34
R15 W17 AL5 G17 P29 AH34
T15 L18 AP5 AF17 U29 AN34
U15 M18 B6 AJ17 V29 B35
V15 N18 J6 AN17 W29 D35
W15 P18 L6 A18 AA29 E35
Y15 R18 P6 B18 AD29 F35
AA15 Y18 T6 U18 AG29 G35
AB15 L19 AA6 AL18 AJ29 H35
L16 M19 AC6 C19 AM29 J35
M16 N19 AE6 H19 C30 K35
N16 P19 AJ6 J19 Y30 L35
P16 R19 G7 T19 AA30 M35
R16 Y19 V7 W19 AB30 N35
T16 L20 AA7 AG19 AC30 P35
U16 M20 AG7 AN19 AE30 R35
V16 N20 AK7 A20 AP30 T35
W16 P20 AN7 D20 D31 U35
Y16 R20 C8 E20 E31 V35
AA16 Y20 E8 F20 F31 W35
AB16 L21 L8 G20 G31 Y35
R17 M21 P8 V20 H31 AE35
Y17 N21 Y8 AK20 J31 C36
AA17 P21 AL8 C21 K31 AA36
AB17 T21 A9 F21 L31 AB36
B VSS_NCTF25 VCC_NCTF48 VSS212 VSS146 VSS84 VSS16 B
AA18 U21 H9 AF21 M31 AC36
AB18 V21 K9 AN21 N31 AD36
AA19 W21 T9 A22 P31 AE36
AB19 L22 V9 D22 R31 AF36
AA20 M22 AA9 E22 T31 AJ36
AB20 N22 AC9 J22 U31 AL36
R21 P22 AE9 AH22 V31 AN36
Y21 R22 AH9 AL22 W31 E37
AA21 T22 AN9 H23 AD31 H37
AB21 U22 D10 AF23 AG31 K37
Y22 V22 L10 B24 AL31 M37
AA22 W22 Y10 D24 A32 P37
AB22 L23 AA10 F24 C32 T37
Y23 M23 F11 J24 Y32 V37
AA23 N23 H11 AG24 AA32 Y37
AB23 P23 Y11 AJ24 AB32 AG37
VSS_NCTF9 VCC_NCTF32 +VCCP VSS196 VSS130 VSS68 VSS0
Y24 R23
VSS_NCTF8 VCC_NCTF31
AA24 T23
AB24 U23
VSS_NCTF6 VCC_NCTF29 ALVISO_BGA1257 ALVISO_BGA1257
Y25 V23
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
AA25 W23
AB25 L24 1 1 1 1 1 1
Y26 M24
C692
C693
C694
C695
C696
C697
AA26 N24
AB26 P24
VSS_NCTF0 VCC_NCTF23 2 2 2 2 2 2
R24
VCC_NCTF22
V25 T24
VCC_NCTF10 VCC_NCTF21
W25 U24
L26 V24
M26 W24
N26 L25
VCC_NCTF6 VCC_NCTF17 +VCCP
P26 VCC_NCTF5 VCC_NCTF16 M25
A A
R26 VCC_NCTF4 VCC_NCTF15 N25
T26 VCC_NCTF3 VCC_NCTF14 P25
U26 VCC_NCTF2 VCC_NCTF13 R25
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
V26 VCC_NCTF1 VCC_NCTF12 T25

W26 VCC_NCTF0 VCC_NCTF11 U25 1 1 1 1
C698
C699
C702
C703
ALVISO_BGA1257
2 2 2 2 Security Classification Compal Secret Data
<Title>
5 4 3 2 1
A B C D E F G H
DDR_A_MA[0..13]
<9> DDR_A_MA[0..13]
DDR_A_D[0..63]
<9> DDR_A_D[0..63] DDR_D[0..63] +2.5V
DDR_A_DM[0..7] DDR_D[0..63] <14>
+SDREF_DIMM
<9> DDR_A_DM[0..7] DDR_DM[0..7] +2.5V
DDR_A_DQS[0..7] DDR_DM[0..7] <14>
JDIMM2 R227
<9> DDR_A_DQS[0..7] DDR_DQS[0..7]
DDR_DQS[0..7] <14> 1 VREF VREF 2 2 1 +SDREF
3 VSS VSS 4 1
DDR_D0 5 6 DDR_D1 0_0402_5%
DDR_D4 DQ0 DQ4 DDR_D5 C237
7 8
DQ1 DQ5 0.1U_0402_16V4Z
9 10
1 DDR_A_D4 DDR_D4 DDR_DQS0 VDD VDD DDR_DM0 2 1
1 2 11 12
DDR_A_D1 R647 10_0402_5% DDR_D1 DDR_D6 DQS0 DM0 DDR_D7
1 2 13
DQ2 DQ6
14
DDR_A_D5 R257 1 2 10_0402_5% DDR_D5 15 16
DDR_A_D2 R256 10_0402_5% DDR_D2 DDR_D2 VSS VSS DDR_D3
1 2 17 18
DDR_A_DM0 R650 10_0402_5% DDR_DM0 DDR_D8 DQ3 DQ7 DDR_D13
1 2 19 20
DDR_A_D3 R255 10_0402_5% DDR_D3 DQ8 DQ12
1 2 21
VDD VDD
22
DDR_A_DQS0 R253 1 2 10_0402_5% DDR_DQS0 DDR_D12 23 24 DDR_D9
DDR_A_D0 R648 10_0402_5% DDR_D0 DDR_DQS1 DQ9 DQ13 DDR_DM1
1 2 25
DQS1 DM1
26
DDR_A_D7 R646 1 2 10_0402_5% DDR_D7 27 28
1 2 29 30
R649 10_0402_5% DDR_D10 DQ10 DQ14 DDR_D11
31 32
DDR_A_D13 DDR_D13 DQ11 DQ15
1 2 33 VDD VDD 34
DDR_A_D11 R252 1 2 10_0402_5% DDR_D11 35 36
<8> DDR_CLK0 CK0 VDD
DDR_A_D10 R248 1 2 10_0402_5% DDR_D10 37 38
DDR_A_D8 DDR_D8 <8> DDR_CLK0# CK0# VSS
R655 1 2 10_0402_5% 39 40
DDR_A_D9 R651 10_0402_5% DDR_D9 VSS VSS
1 2
DDR_A_DM1 R251 1 2 10_0402_5% DDR_DM1
DDR_A_D12 R250 1 2 10_0402_5% DDR_D12 DDR_D16 41 42 DDR_D17
DDR_A_DQS1 R652 10_0402_5% DDR_DQS1 DDR_D20 DQ16 DQ20 DDR_D21
1 2 43 DQ17 DQ21 44
DDR_A_D14 R653 1 2 10_0402_5% DDR_D14 45 46
DDR_A_D15 R654 10_0402_5% DDR_D15 DDR_DQS2 VDD VDD DDR_DM2
1 2 47 DQS2 DM2 48
R249 10_0402_5% DDR_D18 49 50 DDR_D19
DDR_A_D20 DDR_D20 DQ18 DQ22
1 2 51 VSS VSS 52
DDR_A_D16 R246 10_0402_5% DDR_D16 DDR_D24 DQ19 DQ23 DDR_D25
1 2 55 56
DDR_A_D17 R656 10_0402_5% DDR_D17 DQ24 DQ28
1 2 57 VDD VDD 58
DDR_A_DQS2 R247 1 2 10_0402_5% DDR_DQS2 DDR_D28 59 60 DDR_D29
DDR_A_D18 R658 10_0402_5% DDR_D18 DDR_DQS3 DQ25 DQ29 DDR_DM3
1 2 61 DQS3 DM3 62
DDR_A_DM2 R659 1 2 10_0402_5% DDR_DM2 63 64
1 2 65 DQ26 DQ30 66
DDR_A_D19 R243 10_0402_5% DDR_D19 DQ27 DQ31
1 2 69 VDD VDD 70
2 R244 10_0402_5% 2
71 CB0 CB4 72
DDR_A_D28 1 2 DDR_D28 73 74
DDR_A_D24 R662 10_0402_5% DDR_D24 CB1 CB5
1 2 75 VSS VSS 76
DDR_A_D29 R661 1 2 10_0402_5% DDR_D29 77 78
DDR_A_DQS3 R241 10_0402_5% DDR_DQS3 DQS8 DM8
1 2 79 CB2 CB6 80
DDR_A_D25 R663 1 2 10_0402_5% DDR_D25 81 82
DDR_A_DM3 R242 10_0402_5% DDR_DM3 VDD VDD
1 2 83 CB3 CB7 84
DDR_A_D31 R240 1 2 10_0402_5% DDR_D31 85 86
DDR_A_D26 R238 10_0402_5% DDR_D26 DU DU/RESET#
1 2 87
VSS VSS
88
DDR_A_D30 R664 1 2 10_0402_5% DDR_D30 89 90
DDR_A_D27 R665 10_0402_5% DDR_D27 CK2 VSS
1 2 91
CK2# VDD
92
R239 10_0402_5% 93 94
DDR_CKE1 VDD VDD DDR_CKE0
<8> DDR_CKE1 95 96 DDR_CKE0 <8>
DDR_A_D36 DDR_D36 DDR_A_MA13 CKE1 CKE0
1 2 97 98
DDR_A_D37 R666 10_0402_5% DDR_D37 DDR_A_MA12 DU DU DDR_A_MA11
1 2 99
A12 A11
100
DDR_A_D33 R237 1 2 10_0402_5% DDR_D33 DDR_A_MA9 101 102 DDR_A_MA8
DDR_A_D32 R667 10_0402_5% DDR_D32 A9 A8
1 2 103 104
DDR_A_D34 R236 10_0402_5% DDR_D34 DDR_A_MA7 VSS VSS DDR_A_MA6
1 2 105
A7 A6
106
DDR_A_D38 R669 10_0402_5% DDR_D38 DDR_A_MA3 A5 A4 DDR_A_MA2
1 2 109
A3 A2
110
DDR_A_DQS4 R670 10_0402_5% DDR_DQS4 A1 A0
1 2 113 114
DDR_A_DM4 R668 10_0402_5% DDR_DM4 DDR_A_MA10 VDD VDD DDR_A_BS#1
1 2 115 116 DDR_A_BS#1 <9>
R235 10_0402_5% DDR_A_BS#0 A10/AP BA1 DDR_A_RAS#
<9> DDR_A_BS#0 117 118 DDR_A_RAS# <9>
DDR_A_D44 DDR_D44 +1.25VS DDR_A_WE# BA0 RAS# DDR_A_CAS#
1 2 <9> DDR_A_WE# 119 120 DDR_A_CAS# <9>
DDR_A_D41 R274 10_0402_5% DDR_D41 DDR_SCS#0 WE# CAS# DDR_SCS#1
1 2 <8> DDR_SCS#0 121 122 DDR_SCS#1 <8>
DDR_A_D40 R679 10_0402_5% DDR_D40 S0# S1#
1 2 123
DU/A13 DU
124
DDR_A_D45 R273 1 2 10_0402_5% DDR_D45 125 126
DDR_A_DQS5 R680 10_0402_5% DDR_DQS5 DDR_A_MA13 DDR_D36 VSS VSS DDR_D37
1 2 1 2 127 128
DDR_A_D43 R681 10_0402_5% DDR_D43 R673 56_0402_5% DDR_A_MA12 DDR_D33 DQ32 DQ36 DDR_D32
1 2 1 2 129 130
DDR_A_D42 R271 10_0402_5% DDR_D42 R296 56_0402_5% DDR_A_MA11 DQ33 DQ37
1 2 1 2 131 132
DDR_A_D46 R683 10_0402_5% DDR_D46 R282 56_0402_5% DDR_A_MA9 DDR_DQS4 VDD VDD DDR_DM4
1 2 1 2 133 134
3 DDR_A_D47 R682 10_0402_5% DDR_D47 R674 56_0402_5% DDR_A_MA7 DDR_D35 DQS4 DM4 DDR_D38 3
1 2 1 2 135
DQ34 DQ38
136
DDR_A_DM5 R270 1 2 10_0402_5% DDR_DM5 R675 1 56_0402_5%
2 DDR_A_MA8 137 138
R272 10_0402_5% R281 56_0402_5% DDR_A_MA6 DDR_D39 VSS VSS DDR_D34
1 2 139
DQ35 DQ39
140
DDR_A_D53 1 2 DDR_D53 R280 1 56_0402_5%
2 DDR_A_MA3 DDR_D41 141 142 DDR_D44
DDR_A_D48 R685 10_0402_5% DDR_D48 R676 56_0402_5% DDR_A_MA10 DQ40 DQ44
1 2 1 2 143 144
DDR_A_D52 R268 10_0402_5% DDR_D52 R677 56_0402_5% DDR_A_MA0 DDR_D45 VDD VDD DDR_D40
1 2 1 2 145 146
DDR_A_D49 R684 10_0402_5% DDR_D49 R278 56_0402_5% DDR_A_MA1 DDR_DQS5 DQ41 DQ45 DDR_DM5
1 2 1 2 147 148
DDR_A_D55 R269 10_0402_5% DDR_D55 R294 56_0402_5% DDR_A_MA2 DQS5 DM5
1 2 1 2 149 150
DDR_A_D54 R266 10_0402_5% DDR_D54 R288 56_0402_5% DDR_A_MA4 DDR_D46 VSS VSS DDR_D43
1 2 1 2 151 152
DDR_A_D50 R687 10_0402_5% DDR_D50 R279 56_0402_5% DDR_A_MA5 DDR_D42 DQ42 DQ46 DDR_D47
1 2 1 2 153
DQ43 DQ47
154
DDR_A_D51 R688 1 2 10_0402_5% DDR_D51 R295 56_0402_5% 155 156
DDR_A_DM6 R265 10_0402_5% DDR_DM6 VDD VDD
1 2 157 158 DDR_CLK1# <8>
DDR_A_DQS6 R267 10_0402_5% DDR_DQS6 DDR_A_WE# VDD CK1#
1 2 1 2 159
VSS CK1
160 DDR_CLK1 <8>
R686 10_0402_5% R293 1 56_0402_5%
2 DDR_A_BS#0 161 162
DDR_A_D58 DDR_D58 R286 56_0402_5% DDR_A_RAS# DDR_D52 VSS VSS DDR_D49
1 2 1 2 163
DQ48 DQ52
164
DDR_A_D63 R690 1 2 10_0402_5% DDR_D63 R276 1 56_0402_5%
2 DDR_A_CAS# DDR_D53 165 166 DDR_D48
DDR_A_D61 R261 10_0402_5% DDR_D61 R287 56_0402_5% DDR_A_BS#1 DQ49 DQ53
1 2 1 2 167 168
DDR_A_D57 R264 10_0402_5% DDR_D57 R277 56_0402_5% DDR_DQS6 VDD VDD DDR_DM6
1 2 169 170
DDR_A_D56 R692 10_0402_5% DDR_D56 DDR_D54 DQS6 DM6 DDR_D55
1 2 171 172
DDR_A_DM7 R263 10_0402_5% DDR_DM7 DDR_CKE0 DQ50 DQ54
1 2 1 2 173
VSS VSS
174
DDR_A_D59 R262 1 2 10_0402_5% DDR_D59 R283 1 56_0402_5%
2 DDR_CKE1 DDR_D50 175 176 DDR_D51
DDR_A_D62 R693 10_0402_5% DDR_D62 R672 1 56_0402_5% DDR_SCS#1 DDR_D60 DQ51 DQ55 DDR_D61
1 2 2 177
DQ56 DQ60
178
DDR_A_D60 R260 1 2 10_0402_5% DDR_D60 R275 1 56_0402_5%
2 DDR_SCS#0 179 180
DDR_A_DQS7 R689 10_0402_5% DDR_DQS7 R678 56_0402_5% DDR_D56 VDD VDD DDR_D58
1 2 181
DQ57 DQ61
182
R691 10_0402_5% DDR_DQS7 183 184 DDR_DM7
DQS7 DM7
185 186
DDR_D57 VSS VSS DDR_D63
187 188
DDR_D59 DQ58 DQ62 DDR_D62
189 190
DQ59 DQ63
191 192
CK_SDATA VDD VDD
<14,18> CK_SDATA 193 194
CK_SCLK SDA SA0
<14,18> CK_SCLK 195 196
SCL SA1
+3VS 197 VDD_SPD SA2 198
4 4
199 VDD_ID DU 200
TYCO_1612560-1

<Title>
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-2362 1
A B C D E F G H
A B C D E
+2.5V +2.5V
DDR_D[0..63] DDR_B_MA[0..13] +SDREF_DIMM
DDR_D[0..63] <13><9> DDR_B_MA[0..13]
JDIMM1
DDR_DM[0..7] 1 2
DDR_DM[0..7] <13> VREF VREF
3 VSS VSS 4 1
DDR_DQS[0..7] DDR_D0 5 6 DDR_D1
+1.25VS DDR_DQS[0..7] <13> DDR_D4 DQ0 DQ4 DDR_D5
7 8 C188
DQ1 DQ5 0.1U_0402_16V4Z
9 VDD VDD 10
DDR_DQS0 11 12 DDR_DM0 2
DDR_D6 DQS0 DM0 DDR_D7
13 DQ2 DQ6 14
DDR_D4 1 2 1 2 DDR_D44 15 16
DDR_D1 R597 56_0402_5% R183 56_0402_5% DDR_D41 DDR_D2 VSS VSS DDR_D3
1 2 1 2 17 18
DDR_D5 R596 56_0402_5% R574 56_0402_5% DDR_D40 DDR_D8 DQ3 DQ7 DDR_D13
1 2 1 2 19 20
DDR_D2 R215 56_0402_5% R182 56_0402_5% DDR_D45 DQ8 DQ12
1 2 1 2 21
VDD VDD
22
DDR_DM0 R600 1 56_0402_5%
2 R573 1 56_0402_5%
2 DDR_DQS5 DDR_D12 23 24 DDR_D9
1 DDR_D3 R598 56_0402_5% R181 56_0402_5% DDR_D43 DDR_DQS1 DQ9 DQ13 DDR_DM1 1
1 2 1 2 25 26
DDR_DQS0 R599 56_0402_5% R179 56_0402_5% DDR_D42 DQS1 DM1
1 2 1 2 27
VSS VSS
28
DDR_D0 R214 1 56_0402_5%
2 R577 1 56_0402_5%
2 DDR_D46 DDR_D14 29 30 DDR_D15
DDR_D7 R216 56_0402_5% R180 56_0402_5% DDR_D47 DDR_D10 DQ10 DQ14 DDR_D11
1 2 1 2 31 32
DDR_D6 R212 56_0402_5% R576 56_0402_5% DDR_DM5 DQ11 DQ15
1 2 1 2 33 34
R213 56_0402_5% R575 56_0402_5% VDD VDD
<8> DDR_CLK3 35 36
DDR_D13 DDR_D53 CK0 VDD
1 2 1 2 <8> DDR_CLK3# 37 38
DDR_D11 R211 56_0402_5% R579 56_0402_5% DDR_D48 CK0# VSS
1 2 1 2 39
VSS VSS
40
DDR_D10 R210 1 56_0402_5%
2 R178 1 56_0402_5%
2 DDR_D52
DDR_D8 R602 1 56_0402_5%
2 R176 1 56_0402_5%
2 DDR_D49
DDR_D9 R601 1 56_0402_5%
2 R582 1 56_0402_5%
2 DDR_D55 DDR_D16 41 42 DDR_D17
DDR_DM1 R209 56_0402_5% R174 56_0402_5% DDR_D54 DDR_D20 DQ16 DQ20 DDR_D21
1 2 1 2 43 DQ17 DQ21 44
DDR_D12 R603 1 56_0402_5%
2 R578 1 56_0402_5%
2 DDR_D50 45 46
DDR_DQS1 R208 56_0402_5% R177 56_0402_5% DDR_D51 DDR_DQS2 VDD VDD DDR_DM2
1 2 1 2 47 DQS2 DM2 48
DDR_D14 R605 1 56_0402_5%
2 R175 1 56_0402_5%
2 DDR_DM6 DDR_D18 49 50 DDR_D19
DDR_D15 R207 56_0402_5% R581 56_0402_5% DDR_DQS6 DQ18 DQ22
1 2 1 2 51 52
R604 56_0402_5% R580 56_0402_5% DDR_D22 VSS VSS DDR_D23
53 DQ19 DQ23 54
DDR_D20 1 2 1 2 DDR_D58 DDR_D24 55 56 DDR_D25
DDR_D21 R607 56_0402_5% R169 56_0402_5% DDR_D63 DQ24 DQ28
1 2 1 2 57 VDD VDD 58
DDR_D16 R205 1 56_0402_5%
2 R591 1 56_0402_5%
2 DDR_D61 DDR_D28 59 60 DDR_D29
DDR_D17 R606 56_0402_5% R173 56_0402_5% DDR_D57 DDR_DQS3 DQ25 DQ29 DDR_DM3
1 2 1 2 61 DQS3 DM3 62
DDR_DQS2 R206 1 56_0402_5%
2 R595 1 56_0402_5%
2 DDR_D56 63 64
DDR_D18 R204 56_0402_5% R172 56_0402_5% DDR_DM7 DDR_D26 VSS VSS DDR_D27
1 2 1 2 65 DQ26 DQ30 66
DDR_DM2 R203 1 56_0402_5%
2 R170 1 56_0402_5%
2 DDR_D59 DDR_D30 67 68 DDR_D31
DDR_D22 R608 56_0402_5% R171 56_0402_5% DDR_D62 DQ27 DQ31
1 2 1 2 69 70
DDR_D23 R202 56_0402_5% R594 56_0402_5% DDR_D60 VDD VDD
1 2 1 2 71 CB0 CB4 72
DDR_D19 R610 1 56_0402_5%
2 R592 1 56_0402_5%
2 DDR_DQS7 73 74
R609 56_0402_5% R593 56_0402_5% CB1 CB5
75 VSS VSS 76
DDR_D28 1 2 77 78
DDR_D24 R200 56_0402_5% DQS8 DM8
1 2 79 CB2 CB6 80
DDR_D29 R201 1 56_0402_5%
2 81 82
DDR_DQS3 R612 56_0402_5% VDD VDD
1 2 83 CB3 CB7 84
2 DDR_D25 R199 56_0402_5% 2
1 2 85 DU DU/RESET# 86
DDR_DM3 R611 1 56_0402_5%
2 87 88
DDR_D31 R613 56_0402_5% VSS VSS
1 2 89 CK2 VSS 90
DDR_D26 R197 1 56_0402_5%
2 91 92
DDR_D30 R198 56_0402_5% CK2# VDD
1 2 93 VDD VDD 94
DDR_D27 R614 1 56_0402_5%
2 DDR_CKE3 95 96 DDR_CKE2
<8> DDR_CKE3 CKE1 CKE0 DDR_CKE2 <8>
R615 56_0402_5% DDR_B_MA13 97 98
DDR_D36 DDR_B_MA12 DU/A13 DU/BA2 DDR_B_MA11
1 2 99 100
DDR_D37 R195 56_0402_5% DDR_B_MA9 A12 A11 DDR_B_MA8
1 2 101
A9 A8
102
DDR_D33 R584 1 56_0402_5%
2 103 104
DDR_D32 R196 56_0402_5% DDR_B_MA7 VSS VSS DDR_B_MA6
1 2 105
A7 A6
106
DDR_D34 R583 1 56_0402_5%
2 DDR_B_MA5 107 108 DDR_B_MA4
DDR_D35 R194 56_0402_5% DDR_B_MA3 A5 A4 DDR_B_MA2
1 2 109
A3 A2
110
DDR_D38 R193 1 56_0402_5%
2 DDR_B_MA1 111 112 DDR_B_MA0
DDR_D39 R587 56_0402_5% A1 A0
1 2 113
VDD VDD
114
DDR_DQS4 R586 1 56_0402_5%
2 DDR_B_MA10 115 116 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 <9>
DDR_DM4 R192 1 56_0402_5%
2 DDR_B_BS#0 117 118 DDR_B_RAS#
<9> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <9>
R585 56_0402_5% DDR_B_WE# 119 120 DDR_B_CAS#
<9> DDR_B_WE# WE# CAS# DDR_B_CAS# <9>
DDR_SCS#2 121 122 DDR_SCS#3
<8> DDR_SCS#2 S0# S1# DDR_SCS#3 <8>
123 124
DU DU
125 126
+1.25VS DDR_D36 VSS VSS DDR_D37
127 128
129 130
DQ33 DQ37
131 132
DDR_DQS4 VDD VDD DDR_DM4
133 134
DDR_B_MA12 DDR_D35 DQS4 DM4 DDR_D38
1 2 135 136
R189 56_0402_5% DDR_B_MA11 DQ34 DQ38
1 2 137
VSS VSS
138
R565 1 56_0402_5%
2 DDR_B_MA9 DDR_D39 139 140 DDR_D34
R188 56_0402_5% DDR_B_MA7 DDR_D41 DQ35 DQ39 DDR_D44
1 2 141 142
R168 56_0402_5% DDR_B_MA8 DQ40 DQ44
1 2 143 144
R566 56_0402_5% DDR_B_MA6 DDR_D45 VDD VDD DDR_D40
1 2 145 146
R567 56_0402_5% DDR_B_MA3 DDR_DQS5 DQ41 DQ45 DDR_DM5
1 2 147 148
3 R167 56_0402_5% DDR_B_MA10 DQS5 DM5 3
1 2 149
VSS VSS
150
R185 1 56_0402_5%
2 DDR_B_MA0 DDR_D46 151 152 DDR_D43
R569 56_0402_5% DDR_B_MA1 DDR_D42 DQ42 DQ46 DDR_D47
1 2 153
DQ43 DQ47
154
R186 1 56_0402_5%
2 DDR_B_MA2 155 156
R568 56_0402_5% DDR_B_MA4 VDD VDD
1 2 157 158 DDR_CLK4# <8>
R562 56_0402_5% DDR_B_MA5 VDD CK1#
1 2 159 160 DDR_CLK4 <8>
R187 56_0402_5% DDR_B_MA13 VSS CK1
1 2 161 162
R190 56_0402_5% DDR_D52 VSS VSS DDR_D49
163 164
DDR_B_WE# DDR_D53 DQ48 DQ52 DDR_D48
1 2 165 166
R184 56_0402_5% DDR_B_BS#0 DQ49 DQ53
1 2 167
VDD VDD
168
R166 1 56_0402_5%
2 DDR_B_RAS# DDR_DQS6 169 170 DDR_DM6
R571 56_0402_5% DDR_B_CAS# DDR_D54 DQS6 DM6 DDR_D55
1 2 171 172
R572 56_0402_5% DDR_B_BS#1 DQ50 DQ54
1 2 173
VSS VSS
174
R570 56_0402_5% DDR_D50 175 176 DDR_D51
DDR_CKE3 DDR_D60 DQ51 DQ55 DDR_D61
1 2 177
DQ56 DQ60
178
R191 1 56_0402_5%
2 DDR_CKE2 179 180
R564 1 56_0402_5% DDR_SCS#2 DDR_D58 VDD VDD DDR_D56
2 181 182
R165 1 56_0402_5% DDR_SCS#3 DDR_DQS7 DQ57 DQ61 DDR_DM7
2 183 184
R563 56_0402_5% DQS7 DM7
185 186
DDR_D57 VSS VSS DDR_D63
187 188
189 190
DQ59 DQ63
191 192
CK_SDATA VDD VDD
<13,18> CK_SDATA 193 194
CK_SCLK SDA SA0 +3VS
<13,18> CK_SCLK 195 196
SCL SA1
197 198
+3VS VDD_SPD SA2
199 200
VDD_ID DU
KLINK_5763-2-111
4 4

<Title>
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-2362 1
A B C D E
A B C D E
Layout note :
Distribute as close as possible
to DDR-SODIMM.
+2.5V
1 1 1 1 1 1 1 1 1 1 1
1 1
C190 C191 C189 C193 C218 C217 C216 C215 C230 C229 C228
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2
+2.5V +2.5V
1 1 1 1 1 1 1 1
C227 C267 C266 C263 C262 C214 + +
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C163 C238
2 2 2 2 2 2 150U_D2_6.3VM 150U_D2_6.3VM
2 2
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C253 C252 C251 C590 C589 C588 C247 C246 C245 C244
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C243 C242 C578 C579 C580 C256 C255 C254 C582 C581
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C250 C249 C248 C576 C585 C583 C584 C575 C586 C587
3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C200 C201 C202 C531 C530 C529 C535 C544 C536 C208
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C646 C647 C648 C649 C650 C651 C652 C653 C654 C655
2 2 2 2 2 2 2 2 2 2
4 4

<Title>
A B C D E
5 4 3 2 1
ACES_88328-4000
Inverter
42 GND GND 41
JVGA1 LVDS_A0+
<10> LVDS_A0+ 40 39
2 1 LVDS_A0-
2 1 <10> LVDS_A0- 38 37
PEG_TXN152@ C97 1 2 0.1U_0402_16V4Z PEG_A_TXN_15 4 3 PEG_RXN15 LVDS_A1+ +3VS
4 3 <10> LVDS_A1+ 36 35
PEG_TXP15 2@ C94 1 2 0.1U_0402_16V4Z PEG_A_TXP_15 6 5 PEG_RXP15 LVDS_A1-
6 5 <10> LVDS_A1- 34 33
8 7 LVDS_A2-
8 7 <10> LVDS_A2- 32 31
PEG_TXN142@ C93 1 2 0.1U_0402_16V4Z PEG_A_TXN_14 10 9 PEG_RXN14 LVDS_A2+
10 9 <10> LVDS_A2+ 30 29
PEG_TXP14 2@ C88 1 2 0.1U_0402_16V4Z PEG_A_TXP_14 12 11 PEG_RXP14 LCDP_CLK
12 11 LVDS_AC- 28 27 LCDP_DAT
14 14 13 13 <10> LVDS_AC- 26 25
D PEG_TXN132@ C87 1 2 0.1U_0402_16V4Z PEG_A_TXN_13 16 15 PEG_RXN13 LVDS_AC+ D
16 15 <10> LVDS_AC+ 24 23
PEG_TXP13 2@ C83 1 2 0.1U_0402_16V4Z PEG_A_TXP_13 18 17 PEG_RXP13
18 17 22 21 DAC_BRIG <32>
20 19 LVDS_B0- PWM
20 19 <10> LVDS_B0- 20 19
22 21 LVDS_B0+ DISPLAYOFF#
22 21 <10> LVDS_B0+ 18 17
PEG_TXN122@ C82 1 2 0.1U_0402_16V4Z PEG_A_TXN_12 24 23 PEG_RXN12 LVDS_B2- INVPWR_B+
24 23 <10> LVDS_B2- 16 15
PEG_TXP12 2@ C80 1 2 0.1U_0402_16V4Z PEG_A_TXP_12 26 25 PEG_RXP12 LVDS_B2+ R722 1@
26 25 <10> LVDS_B2+ 14 13
28 27 LVDS_B1- INVPWR_B+++ 1 2
28 27 <10> LVDS_B1- 12 11
PEG_TXN112@ C79 1 2 0.1U_0402_16V4Z PEG_A_TXN_11 30 29 PEG_RXN11 LVDS_B1+
30 29 <10> LVDS_B1+ 10 9
PEG_TXP11 2@ C77 1 2 0.1U_0402_16V4Z PEG_A_TXP_11 32 31 PEG_RXP11 KC FBM-L11-201209-221LMAT_0805 +LCDVDD
32 31 LVDS_BC- 8 7
34 34 33 33 <10> LVDS_BC- 6 5
PEG_TXN102@ C76 1 2 0.1U_0402_16V4Z PEG_A_TXN_10 36 35 PEG_RXN10 LVDS_BC+
36 35 <10> LVDS_BC+ 4 3
PEG_TXP10 2@ C73 1 2 0.1U_0402_16V4Z PEG_A_TXP_10 38 37 PEG_RXP10
38 37 2 1
40 40 39 39 1 1
42 41 +3VS 1@ 1@
PEG_TXN9 2@ C72 42 41 JLVDS1
1 2 0.1U_0402_16V4Z PEG_A_TXN_9 44 44 43 43 PEG_RXN9 1@ C318
PEG_TXP9 2@ C71 1 2 0.1U_0402_16V4Z PEG_A_TXP_9 46 45 PEG_RXP9 C320 0.1U_0402_16V4Z
46 45 2 2
48 48 47 47
1
PEG_TXN8 2@ C70 1 2 0.1U_0402_16V4Z PEG_A_TXN_8 50 49 PEG_RXN8 1@ 1@ 0.1U_0402_16V4Z
PEG_TXP8 2@ C67 1 50 49
2 0.1U_0402_16V4Z PEG_A_TXP_8 52 52 51 51 PEG_RXP8 R336 R335
54 53 2.2K_0402_5% 2.2K_0402_5%
PEG_TXN7 2@ C66 54 53
1 2 0.1U_0402_16V4Z PEG_A_TXN_7 56 56 55 55 PEG_RXN7
PEG_TXP7 2@ C65 1 2 0.1U_0402_16V4Z PEG_A_TXP_7 58 57 PEG_RXP7 +LCDVDD
2
58 57 +12VALW +LCDVDD +3VS
60 60 59 59 Q26
62 62 61 61
SI2302DS_SOT23
D
PEG_TXN6 2@ C64 1 2 0.1U_0402_16V4Z PEG_A_TXN_6 64 63 PEG_RXN6 3 1 LCDP_CLK
64 63 <10> LCD_CLK
PEG_TXP6 2@ C61 1 2 0.1U_0402_16V4Z PEG_A_TXP_6 66 65 PEG_RXP6 Q20
66 65
D
68 67 BSS138_SOT23 3 1
PEG_TXN5 2@ C59 68 67
2 0.1U_0402_16V4Z PEG_A_TXN_5 PEG_RXN5 +2.5VS R344 R356 R355
G
1 70 69
2
PEG_TXP5 2@ C57 1 70 69 LCD EEPROM
2 0.1U_0402_16V4Z PEG_A_TXP_5 72 72 71 71 PEG_RXP5
1@
470_0402_5% 100K_0402_5% 100K_0402_5% 1@
C 1@ 1@ 1@ C323 C
G
74 73
2
74 73
2
G
PEG_TXN4 2@ C56 1 2 0.1U_0402_16V4Z PEG_A_TXN_4 76 75 PEG_RXN4 1@ 0.1U_0402_16V4Z
PEG_TXP4 2@ C55 1 76 75
2 0.1U_0402_16V4Z PEG_A_TXP_4 78 78 77 77 PEG_RXP4
80 79 Q21 3 1 LCDP_DAT
80 79 <10> LCD_DAT
1
PEG_TXN3 2@ C54 D D
2 0.1U_0402_16V4Z PEG_A_TXN_3 PEG_RXN3 BSS138_SOT23 1@ C321
D
1 82 82 81 81
PEG_TXP3 2@ C51 1 2 0.1U_0402_16V4Z PEG_A_TXP_3 84 83 PEG_RXP3 Q22 2 2 Q23 0.1U_0402_16V4Z
84 83 2N7002_SOT23 G G 2N7002_SOT23
86 86 85 85
1
PEG_TXN2 2@ C50 1 2 0.1U_0402_16V4Z PEG_A_TXN_2 88 87 PEG_RXN2 S S R354
3
PEG_TXP2 2@ C49 1 88 87 1@
2 0.1U_0402_16V4Z PEG_A_TXP_2 90 90 89 89 PEG_RXP2 1@ Q24 1@ 1@ 150K_0402_5%
92 91 DTC124EK_SC59
PEG_TXN1 2@ C48 92 91
1 2 0.1U_0402_16V4Z PEG_A_TXN_1 94 94 93 93 PEG_RXN1
PEG_TXP1 2@ C44 1 2 0.1U_0402_16V4Z PEG_A_TXP_1 96 95 PEG_RXP1 2
96 95 <10> EN_LCDVDD
98 98 97 97
100 100 99 99
PEG_TXN0 2@ C43 1 2 0.1U_0402_16V4Z PEG_A_TXN_0 102 101 PEG_RXN0 1@
PEG_TXP0 2@ C39 1 102 101
20.1U_0402_16V4Z PEG_A_TXP_0 104 103 PEG_RXP0
3
104 103
106 106 105 105
SMB_EC_CK2 108 107 RUNPWROK
<32,34> SMB_EC_CK2 108 107 RUNPWROK
SMB_EC_DA2 110 109 PLTRST_VGA#
<32,34> SMB_EC_DA2 110 109 PLTRST_VGA# <19,21>
112 111 THERMATRIP_VGA# INVPWR_B+
<24,32,33,37,42> SUSP# 112 111 THERMATRIP_VGA# <32>
114 113 SUSP
<17> C/R_VGA 114 113 SUSP <37,43,44> FBM-201209-121LMA40T PEG_RXP[0..15]
116 115 B+ B+I
<17> COMP/B_VGA 116 115 Q1 PEG_RXP[0..15] <10>
118 117 CLK_PCIE_VGA# L33
<17> Y/G_VGA 118 117 CLK_PCIE_VGA# <18> FDS4435_SO8
B+I 120 119 CLK_PCIE_VGA FBM-L11-201209-121LMA05T_0805 PEG_RXP0
120 119 CLK_PCIE_VGA <18>
2@ R328 VSYNC_VGA 122 121 1 2 1 8 PEG_RXP1
<17> VSYNC_VGA 122 121
FBM-L11-160808-800LMT_0603 JVGAP1 HSYNCVGA 124 123 2 7 PEG_RXP2
<17> HSYNC_VGA 124 123 DAC_BRIG <32>
1 2 B+P 1 1 126 126 125 125 BKOFF# <32> 1 3 6 PEG_RXP3
1 2 2 2 VGA_BLU 128 127 R27 5 PEG_RXP4
<17> VGA_BLU 128 127 INVT_PWM <32>
2@ R329 3 3 VGA_GRN 130 129 C717 100K_0402_5% PEG_RXP5
B <17> VGA_GRN 130 129 10U_1206_25V6M B
FBM-L11-160808-800LMT_0603 4 4 VGA_RED 132 131 +5VS C716 1@ PEG_RXP6
<17> VGA_RED
4
132 131 0.1U_0603_50V4Z 2 C27 PEG_RXP7
5 5 134 134 133 133
6 6 SMBCLK_VGA 136 135 0.1U_0603_50V4Z C23 PEG_RXP8
+3VS <17> SMBCLK_VGA 136 135 +5VALW
7 7 SMBDAT_VGA 138 137 0.1U_0603_50V4Z PEG_RXP9
<17> SMBDAT_VGA 138 137
8 8 140 139 +12VALW 1@ PEG_RXP10
+2.5V 140 139
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2@ 2@ 9 9 PEG_TXP[0..15] PEG_RXP11
PEG_TXP[0..15] <10> Q25
1 1 10 10 2@ FOX_QTS0140A-3021 PEG_TXP0 1@ PEG_RXP12
PEG_TXP1 2N7002_SOT23 PEG_RXP13
C704
C705
2@ ACES_85205-1000 PEG_TXP2 R357 75K_0402_5% PEG_RXP14

PEG_TXP3 1 3 PEG_RXP15
S
2 2 +5VS PEG_TXP4
PEG_TXP5 1@ 1@
PEG_TXP6
G
2
5
Modify for 1.8vs move to VGA BD U1 PEG_TXP7 PEG_RXN[0..15] +5VS PEG_TXN[0..15]

PEG_RXN[0..15] <10> <10> PEG_TXN[0..15]
1 A PEG_TXP8
P
<10> BK_EN
B+P B+I 4DISPLAYOFF# PEG_TXP9 PEG_RXN0
O PEG_TXP10 PEG_RXN1 PEG_TXN0
2
0.1U_0603_50V4Z
0.1U_0603_50V4Z
0.1U_0603_50V4Z
0.1U_0603_50V4Z
<32> BKOFF# B
G
PEG_TXP11 PEG_RXN2 PEG_TXN1

2 2 2 2 PEG_TXP12 PEG_RXN3 PEG_TXN2
3
NC7ST08P5X_SC70-5
C307
C313
C308
C314
1@ PEG_TXP13 PEG_RXN4 PEG_TXN3

1 2@ 1 2@ 1 2@ 1 2@ PEG_RXN7 PEG_TXN6
R4
1@ PEG_RXN8 PEG_TXN7
+3VS 1 2 PWM PEG_RXN9 PEG_TXN8
<32> INVT_PWM
PEG_RXN10 PEG_TXN9
PEG_RXN11 PEG_TXN10
0_0402_5%
5
+3VS U2 PEG_RXN12 PEG_TXN11

R3
PEG_RXN13 PEG_TXN12
P
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
A A
2 4 1 2 PEG_RXN14 PEG_TXN13
<10,32> BIA A Y PEG_RXN15 PEG_TXN14
G
1 1 1 @ PEG_TXN15
0_0402_5%
C309
C310
C311
NC7SZ14M5X_SOT23-5
3
2 2 2 Security Classification Compal Secret Data

R7
@ 2005/03/01 2006/03/01 Title
Issued Date Deciphered Date <Title>
1 2
0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 4 3 2 1
5 4 3 2 1
1@
R25 1 2 0_0402_5% C/R_C 1 2
<10> C/R
L8
FLM1608081R8K_0603 2
1
R26 1 2 0_0402_5% 1
<16> C/R_VGA
R19 C17
2@ 150_0402_1% C22 82P_0603_50V8J
82P_0402_50V8J 1
D 2 D
2
JTV1
SVIDEO_C 7
1@ 6
R23 COMP/B_C SVIDEO_CVBS 5
<10> COMP/B 1 2 0_0402_5% 1 2 4
L7
FLM1608081R8K_0603 3
R24 2
<16> COMP/B_VGA 1 2 0_0402_5% 2 1
1
1 SVIDEO_Y
2@ R18 C16 SUYIN_33007SR-07T1-C
150_0402_1% C21 82P_0603_50V8J
82P_0402_50V8J 1
2
1
D12 D11 D10
1@
R21 1 2 0_0402_5% Y/G_C 1 2
3
<10> Y/G +3VS
L6
1
1 FLM1608081R8K_0603 2
R22 1 2 0_0402_5% R17
<16> Y/G_VGA
150_0402_1% C20 C15 @ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59
2@ 82P_0402_50V8J 82P_0603_50V8J
2 1
2
C +5VS C
+5VS
+3VS +2.5VS
1
1
2.7K_0402_5%
C304 R321 R325
1
0.1U_0402_16V4Z 2K_0402_5% 2K_0402_5%
2 R330 R334
0_0402_5% R331 2.7K_0402_5%
2
+5VS
2
R322
2@ 0_0402_5% 2@
R16 1 2 0_0402_5% 1 2
<16> VGA_RED SMBDAT_VGA <16>
2
R333
G
2@ DDC_MONID0 1 0_0402_5%
R14 1 2 0_0402_5% 1 3 1 2 1@
<16> VGA_GRN DAT_DDC2 <10>
1
MSEN# D9 D8 D7 C306
S
<32> MSEN#
2
2@ 0.1U_0402_16V4Z R326
R12 1 2 0_0402_5% 3.3P_0603_50V8J 2 Q18 0_0402_5% 2@
<16> VGA_BLU RB751V_SOD323 2N7002_SOT23 1 2 SMBCLK_VGA <16>
2
@1 D20 R332
G
1 1
DAN217_SC59 DAN217_SC59 DAN217_SC59 0_0402_5%
1
@ C14 C13 C12 @ +2.5VS 1 3 1 2 1@ CLK_DDC2 <10>
3.3P_0603_50V8J 3.3P_0603_50V8J JCRT1 Q19
S
2 2 2 @ @ @ 2N7002_SOT23
6
11
<10> CRT_RED
R11 1 2 0_0402_5% CRT_R 1 L3 2 CRTR 1
FBM-11-160808-121-T_0603 7
1@ 12
<10> CRT_GRN
R13 1 2 0_0402_5% CRT_G 1 L4 2 CRTG 2
B FBM-11-160808-121-T_0603 B
8
1@ 13 CRT Connector
<10> CRT_BLU
R15 1 2 0_0402_5% CRT_B 75_0603_1% 1 L5 2 CRTB 3
R339 FBM-11-160808-121-T_0603 9
1
1@ 1K_0402_5% 1 1 1 14 16
+5VS 1 2 4 17
R10 R9 R8 C8 C9 C10 10
2@ 75_0603_1% 75_0603_1% 3.3P_0603_50V8J 3.3P_0603_50V8J 3.3P_0603_50V8J 15
R342 1 2 0_0402_5% 2 2 2 5
2
<16> HSYNC_VGA
5
FOX_DZ11A91-L7
OE#
P
<10> HSYNC
R343 1 2 0_0402_5% CRT_HSYNC 2 4 1 2
A Y L1
G
1@ FBM-11-160808-121-T_0603
U25
3
1 2
SN74AHCT1G125GW_SOT353-5 +5VS L2 1 1 1 1 1 1
FBM-11-160808-121-T_0603
1 C5 C6 C3 C303 C4 C302
27P_0402_50V8J 27P_0402_50V8J 100P_0402_50V8J
2@ C305 2 2 2 2 2 2
R340 1 2 0_0402_5% 0.1U_0402_16V4Z
<16> VSYNC_VGA
5
2
100P_0402_50V8J
OE#
P
R341 1 2 0_0402_5% CRT_VSYNC 2 4 100P_0402_50V8J

<10> VSYNC A Y 100P_0402_50V8J
G
1@
U24
3
SN74AHCT1G125GW_SOT353-5
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+3VS +CK_VDD_MAIN
+3VS
0.1U_0402_16V4Z
1 2
10K_0402_5%
10K_0402_5%
L25 2 1 1 1 1 CLK_MCH_BCLK 2 1
1
1 CHB1608U301_0603 C457 C505 R528 49.9_0402_1%
C137 C523 C511 0.047U_0402_16V7K CLK_MCH_BCLK# 2 1
R119
R121
C456
10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K R535 49.9_0402_1%
1 2 2 2 2 CLK_CPU_BCLK 2 1
2 R515 49.9_0402_1%
2
CLK_CPU_BCLK# 2 1
ICH_SMBDATA CK_SDATA R522 49.9_0402_1%
S
<21> ICH_SMBDATA 1 3 CK_SDATA <13,14>
Q4 CLK_ITP 2 1
2N7002_SOT23 R540 49.9_0402_1%
Place near each pin CLK_ITP# 2 1
G
2
R545 49.9_0402_1%
D CLK_PCIE_VGA D
+3VS
+CK_VDD_MAIN2 W>40 mil CLK_PCIE_VGA#
1
R552
2
49.9_0402_1%
1 2
2
R557 49.9_0402_1%
G
1 2
<21> ICH_SMBCLK
ICH_SMBCLK 1
Q5
3 2N7002_SOT23 CK_SCLK
CK_SCLK <13,14>
L24
CHB1608U301_0603
2
C444
1 1
Place near CK410M CLK_PCIE_ICH 1
R542
2
49.9_0402_1%
C479 C466 CLK_PCIE_ICH# 1 2
S
10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K R547 49.9_0402_1%
1 2 2 CLK_MCH_3GPLL 1 2
D
0.047U_0402_16V7K
R145 R550 49.9_0402_1%
CK_VDD_A CK_VDD_48 CK_VDD_REF 2.2_0603_5% CLK_MCH_3GPLL# 1 2
1
0.047U_0402_16V7K
1 1 1 1 1 1 2 CK_VDD_A R555 49.9_0402_1%
0.047U_0402_16V7K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
U31
G 2 3 S
C139
C508
C134
21 VDD_SRC0
2 2 2 2 2
28 VDD_SRC1 VDD_A 37
2N7002
C133
C123
34 SSC_DREFCLK 1 2
VDD_SRC2 R146 49.9_0402_1%
VSS_A 38
1 SSC_DREFCLK# 1@
1 2
VDD_PCI0 R537 49.9_0402_1%
7 VDD_PCI1
55 H_STP_PCI# DREFCLK 1
1@ 2
PCI_STOP# H_STP_PCI# <21>
R519 49.9_0402_1%
0 0 1 for Dothan-A 533Mhz Place crystal within CPU_STOP# 54 H_STP_CPU#
H_STP_CPU# <21,45>
DREFCLK# 1
1@ 2
500 mils of CK410 R525 49.9_0402_1%
1 0 1 for Dothan-A 400Mhz C476
33P_0402_50V8J 1
42
2 CK_VDD_REF
48
VDD_CPU 1@
CK_XTAL_IN R126 VDD_REF
2 1
FSC FSB FSA CPU SRC PCI 1_0603_5%
CPU1 41 CK_CPU1 1 2 CLK_MCH_BCLK
CLK_MCH_BCLK <8>
1
X3 14.318MHZ_20P_1BX14318CC1A 1 2 CK_VDD_4811 VDD_48
R527 33_0402_5%
CLKSEL0 CLKSEL1 CLKSEL2 MHz MHz MHz R128
2.2_0603_5% CPU1# 40 CK_CPU1# 1
R534
2
33_0402_5%
CLK_MCH_BCLK#
CLK_MCH_BCLK# <8>
C487 50
2
XTAL_IN
C
0 0 0 266 100 33.3 33P_0402_50V8J
CK_XTAL_OUT CK_CPU0 CLK_CPU_BCLK
C
2 1 49 44 1 2 CLK_CPU_BCLK <5>
XTAL_OUT CPU0 R514 33_0402_5%
0 0 1 133 100 33.3
*
43 CK_CPU0# 1 2 CLK_CPU_BCLK#
CLK_48M_ICH CLKSEL2 CPU0# CLK_CPU_BCLK# <5>
R511 2 1 33_0402_5% 12 R521 33_0402_5%
<21> CLK_48M_ICH FSA/USB_48
0 1 0 200 100 33.3 CLKSEL1
CLK_14M_CODEC
16 FSB/TEST_MODE
<29> CLK_14M_CODEC 2 1
CLKSEL0 33_0402_1% R493 53 36 CK_CPU2 1 2 CLK_ITP
FSC/TEST_SEL CPU_2_ITP/SRC_7 CLK_ITP <5>
0 1 1 166 100 33.3 CK_CPU2#
R539 33_0402_5%
CLK_ITP#
<27> CLK_33M_1394 2 1 CPU_2_ITP/SRC7#
35 1 2 CLK_ITP# <5>
R501 12.1_0402_1% R544 33_0402_5%
1 0 0 333 100 33.3 <26> CLK_33M_CBS
CLK_33M_CBS 2 1 PCICLK5 5
PCI5
R502 12.1_0402_1%
CLK_33M_LPCSIO 2 1 PCICLK4 4 33
<31> CLK_33M_LPCSIO PCI4 SRC6
1 0 1 100 100 33.3 CLK_33M_MPCI
R497 33_0402_5%
PCICLK3
<28> CLK_33M_MPCI 2 1 3 32
R498 33_0402_5% PCI3 SRC6#
1 1 0 400 100 33.3 <24> CLK_33M_LAN
CLK_33M_LAN 2 1 PCICLK2 56
PCI2 SCR5 CLK_MCH_3GPLL
R491 33_0402_5% 31 1 2
CLK_33M_ICH PCICLKF1 SRC5 CLK_MCH_3GPLL <10>
2 1 9 R549 33_0402_5%
<19> CLK_33M_ICH PCIF1
1 1 0 RESERVED CLK_33M_LPCEC
R508 33_0402_5%
SRC5#
30 SRC5# 1 2 CLK_MCH_3GPLL#
CLK_MCH_3GPLL# <10>
2 1 R554 33_0402_5%
<32> CLK_33M_LPCEC
Table : ICS 954201 / Cypress CY28411 R506 33_0402_5%
PCICLKF0 SRC4 CLK_PCIE_VGA
+3VS 1 2 8 26 1 2 CLK_PCIE_VGA <16>
R509 10K_0402_5% PCIF0/ITP_EN SRC4 R553 33_0402_5%
CK_SCLK 46 27 SRC4# 1 2 CLK_PCIE_VGA#
SCLOCK SRC4# CLK_PCIE_VGA# <16>
R558 33_0402_5%
+VCCP
CK_SDATA 47 24
SDATA SRC3
2
R486 25
B @ 10K_0402_5% CLKIREF SRC3# B
1 2 39
IREF
R131 475_0603_1%
22
1
SRC2
23
CLKSEL0 SRC2#
1 2 MCH_CLKSEL0 <8>
R488 19 SRC1 1 2 CLK_PCIE_ICH
SRC1 CLK_PCIE_ICH <21>
1K_0402_5% R543 33_0402_5%
20 SRC1# 1 2 CLK_PCIE_ICH#
<6> CPU_BSEL0 SRC1# CLK_PCIE_ICH# <21>
13 R548 33_0402_5%
VSS_48
2
+3VS
R482 29 17 SRC0 1 2 SSC_DREFCLK
VSS_SRC SRC0 SSC_DREFCLK <8>
10K_0402_5% R142 1@ 33_0402_5%
2
@ 2 18 SRC0# 1 2 SSC_DREFCLK#
VSS_PCI0 SRC0# SSC_DREFCLK# <8>
R513 R538 1@ 33_0402_5%
1
10K_0402_5% 45
VSS_CPU DREFCLK
14 1 2 DREFCLK <8>
DOT96 R520 33_0402_5% DREFCLK# +3VS
51 15 1 2
1
CLKSEL2 VSS_REF DOT96# DREFCLK# <8>

R5261@ 33_0402_5%
6 1@
VSS_PCI1
2
1
+VCCP R512 R742
10K_0402_5% 10K_0402_5%
@
2
2
R531 10
10K_0402_5% VTT_PWRGD#/PD
R744
1
@ R533 CLKREF CLK_14M_ICH D
52 1 2 CLK_14M_ICH <21>
1K_0402_5% REF R499 12.1_0402_1% 2 1 2
1
Q45 2N7002_SOT23
G VGATE <8,21,45>
CLKSEL1 1 2 ICS954206AG 1 2 CLK_14M_SIO
CLK_14M_SIO <31> S
3
A MCH_CLKSEL1 <8> 10K_0402_5% A
R503 12.1_0402_1% 1
C635
<6> CPU_BSEL1 0.047U_0402_16V4Z
2
2
R524
10K_0402_5%
@ Security Classification Compal Secret Data
1
<Title>
5 4 3 2 1
5 4 3 2 1
RP4
+3VS 1 8 PCI_SERR#
2 7 PCI_FRAME#
3 6 PCI_TRDY#
4 5 PCI_STOP#
8.2K_0804_8P4R_5% U7B
<24,26,27,28> PCI_AD[0..31]
PCI_AD0 E2 L5 PCI_REQ0#
AD[0] REQ[0]# PCI_REQ0# <24>
PCI_AD1
PCI_AD2
E5
C2
AD[1] PCI GNT[0]# C1
B5
PCI_GNT0#
PCI_REQ1# PCI_GNT0# <24>
PCI_AD3 AD[2] REQ[1]# PCI_GNT1# PCI_REQ1# <26>
F5 B6 PCI_GNT1# <26>
RP5 PCI_AD4 AD[3] GNT[1]# PCI_REQ2#
F3 M5 PCI_REQ2# <27>
PCI_AD5 AD[4] REQ[2]# PCI_GNT2#
E9 F1 PCI_GNT2# <27>
D +3VS PCI_IRDY# PCI_AD6 AD[5] GNT[2]# PCI_REQ3# D
1 8 F2 B8 PCI_REQ3# <28>
PCI_PLOCK# PCI_AD7 AD[6] REQ[3]# PCI_GNT3#
2 7 D6
AD[7] GNT[3]#
C8 PCI_GNT3# <28>
3 6 PCI_DEVSEL# PCI_AD8 E6 F7 PCI_REQ4#
PCI_PERR# PCI_AD9 AD[8] REQ[4]#/GPI[40] PCI_GNT4#
4 5 D3 E7
PCI_AD10 AD[9] GNT[4]#/GPO[48] PCI_REQ5#
A2 E8
8.2K_0804_8P4R_5% PCI_AD11 AD[10] REQ[5]#/GPI[1]
D2 F6
RP3 PCI_AD12 AD[11] GNT[5]#/GPO[17] PCI_REQ6#
D5 B7
PCI_AD13 AD[12] REQ[6]#/GPI[0]
H3 D8
+3VS PCI_PIRQD# PCI_AD14 AD[13] GNT[6]#/GPO[16]
1 8 B4
AD[14]
2 7 PCI_PIRQB# PCI_AD15 J5 J6 PCI_C_BE0#
PCI_PIRQH# PCI_AD16 AD[15] C/BE[0]# PCI_C_BE1# PCI_C_BE0# <24,26,27,28>
3 6 K2
AD[16] C/BE[1]#
H6 PCI_C_BE1# <24,26,27,28>
4 5 PCI_PIRQC# PCI_AD17 K5 G4 PCI_C_BE2#
PCI_AD18 AD[17] C/BE[2]# PCI_C_BE3# PCI_C_BE2# <24,26,27,28>
D4 AD[18] C/BE[3]# G2 PCI_C_BE3# <24,26,27,28>
8.2K_0804_8P4R_5% PCI_AD19 L6
PCI_AD20 AD[19] PCI_IRDY#
G3 AD[20] IRDY# A3 PCI_IRDY# <24,26,27,28>
PCI_AD21 H4 E1 PCI_PAR
PCI_AD22 AD[21] PAR PCI_PCIRST# PCI_PAR <24,26,27,28>
H2 AD[22] PCIRST# R2
PCI_AD23 H5 C3 PCI_DEVSEL#
PCI_AD24 AD[23] DEVSEL# PCI_PERR# PCI_DEVSEL# <24,26,27,28>
B3 AD[24] PERR# E3 PCI_PERR# <24,26,27,28>
8.2K_0402_5% 1 2 R480 PCI_PIRQE# PCI_AD25 M6 C5 PCI_PLOCK#
AD[25] PLOCK# R756
8.2K_0402_5% 1 2 R475 PCI_PIRQF# PCI_AD26 B2 G5 PCI_SERR#
PCI_PIRQG# PCI_AD27 AD[26] SERR# PCI_STOP# PCI_SERR# <24,26,28>
8.2K_0402_5% 1 2 R84 K6 J1 1 2
PCI_PIRQA# PCI_AD28 AD[27] STOP# PCI_TRDY# PCI_STOP# <24,26,27,28>
8.2K_0402_5% 1 2 R72 K3 J2
PCI_AD29 AD[28] TRDY# PCI_TRDY# <24,26,27,28>
A5 0_0402_5%
PCI_AD30 AD[29]
L1 AD[30]
PCI_AD31 Q46
K4 AD[31]
R5 PLTRST# 2N7002_SOT23
PLTRST# CLK_33M_ICH PLTRST# <21>
PCICLK G6 CLK_33M_ICH <18>
D
+3VS 8.2K_0402_5% 1 2 R447 PCI_REQ0# PCI_FRAME# J3 P6 3 1 ICH_PME#
<24,26,27,28> PCI_FRAME# FRAME# PME# ICH_PME# <24,26,27,28,31,32>
8.2K_0402_5% 1 2 R70 PCI_REQ1#
8.2K_0402_5% 1 2 R88 PCI_REQ3# Interrupt I/F
8.2K_0402_5% R473 PCI_REQ4# PCI_PIRQA# PCI_PIRQE#
G
1 2 N2 D9
2
C <26> PCI_PIRQA# PCI_PIRQB# PIRQ[A]# PIRQ[E]#/GPI[2] PCI_PIRQF# PCI_PIRQE# <27> C
<26> PCI_PIRQB# L2 PIRQ[B]# PIRQ[F]#/GPI[3] C7 PCI_PIRQF# <24>
PCI_PIRQC# M1 C6 PCI_PIRQG# R757
PIRQ[C]# PIRQ[G]#GPI[4] PCI_PIRQG# <28>
1
PCI_PIRQD# L3 M3 PCI_PIRQH# 10K_0402_5%
PIRQ[D]# PIRQ[H]#/GPI[5] PCI_PIRQH# <28>
@
AC5
RESERVED +3V
+3VS 8.2K_0402_5% PCI_REQ2# SATA[1]RXN/RSVD[1]
1 2 R448 AD5
2
8.2K_0402_5% PCI_REQ5# SATA[1]RXP/RSVD[2]
1 2 R478 AF4
8.2K_0402_5% PCI_REQ6# SATA[1]TXN/RSVD[3]
1 2 R86 AG4
SATA[1]TXP/RSVD[4]
AC9
+3VALW ICH_PME# SATA[3]RXN/RSVD[5] @
1 2 AD9
SATA[3]RXP/RSVD[6]
R724 10K_0402_1% AF8
SATA[3]TXN/RSVD[7]
AG8
SATA[3]TXP/RSVD[8]
U3
TP[3]/RSVD[9]
ICH6_BGA609
CLK_33M_ICH
C350
0.1U_0402_16V4Z
+3V 2 1 +3V
2
14
U29D R472
14
U29A R443 13 10_0402_5%
P
PLTRST# 33_0402_5% A @
1 11
P
A PCIRSTB1# O
3 1 2 12
1
O PLTRST_VGA# <16,21> B
G
2
B G 74VHC08MTC_TSSOP14
CLK_ICH_TERM
CHGRTC 74VHC08MTC_TSSOP14
7
R774
0_0402_5% @
@ 1 2
+RTCVCC
B R775 B
0_0402_5%
+3V 1 2
2
14
1
U29B R446
4 33_0402_5% C410
P
BAS40-04_SOT23 A PCIRSTB2# @ 8.2P_0402_50V8J~D

6 1 2 PLTRST_SIO# <31>
D16 O 2
5
B
G
R445
1
74VHC08MTC_TSSOP14 33_0402_5%
7
BATT1 1 2 PLTRST_MCH# <8>

2 1 @
ML1220T13RE R758
0_0402_5%
1 2
+3V
14
U29C R389
PCI_PCIRST# 10 33_0402_5%
P
A PCIRSTB3#
8 1 2 PCIRST# <24,26,27,28,32>
O
9
B
G
74VHC08MTC_TSSOP14
7
A @ A

<Title>
5 4 3 2 1
5 4 3 2 1
C62
10P_0603_50V8J
2 1 ICH_RTCX1
10M_0402_5%
2
1
X1
R68
Package +VCCP
9.6X4.06 mm
32.768KHZ_12.5P_MC-306 U7A R143
2
D LPC_LAD[0..3] <31,32> D
C68 56_0402_5%
1
10P_0603_50V8J Y1 P2 LPC_LAD0 H_FERR# 2 1
RTCX1 LAD[0]/FWH[0]
RTC
+RTCVCC
2 1 ICH_RTCX2 Y2
RTCX2 LAD[1]/FWH[1]
N3
N5
LPC_LAD1
LPC_LAD2 Note : R169 Do not populate for R546
LAD[2]/FWH[2]
1 2 ICH_RTCRST# AA2 N4 LPC_LAD3
Dothan-A, Populte for Dothan-B. 56_0402_5%
LPC
+RTCVCC RTCRST# LAD[3]/FWH[3]
R467 H_DPRSLP# 2 1
180K_0402_5% INTRUDER# AA3 N6 LPC_LDRQ0#
INTRUDER# INTRUDER# LDRQ[0]# LPC_LDRQ0#
1
AA5 P4 LPC_LDRQ1#
INTVRMEN LDRQ[1]#/GPI[41] LPC_LDRQ1# <31>
R469
1M_0402_5% CMOS_CLR1 R474 0_0402_5% P3 LPC_LFRAME#
LFRAME#/FWH[4] LPC_LFRAME# <31,32>
SHORT PADS~D 1 2 D12
EE_CS
B12
2
EE_SHCLK
1
INTRUDER# R471 D11 AF22 GATEA20
EE_DOUT A20GATE GATEA20 <32>
@ F13 AF23 A20M# R135 2 1 0_0402_5% H_A20M#
0_0402_5% EE_DIN A20M# H_A20M# <5>
1 1 2 2
Note : R423 must be stuff for
LAN
CPUSLP# R161 0_0402_5% H_CPUSLP#
CPU
F12 LAN_CLK CPUSLP# AE27 2 1 H_CPUSLP# <5,8>
Dothan-A, no-stuff for Dothan-B.
2
B11 AE24 DPRSLP# R551 2 1 0_0402_5% H_DPRSLP#
LAN_RSTSYNC DPRSLP#/TP[4] DPSLP# H_DPSLP# H_DPRSLP# <5>
@ AD27 R162 2 1 0_0402_5%
DPSLP#/TP[2] H_DPSLP# <5>
E12 LANRXD[0]
C400 E11 AF24 FERR# R144 2 1 56_0402_5%
LANRXD[1] FERR# H_FERR# <5>
0.1U_0402_16V4Z C13 LANRXD[2]
1 2
C12
CPUPWRGD/GPO[49] AG25 H_PWRGOOD
H_PWRGOOD <5> Note : R168 populate 56 ohm for
LANTXD[0]
C11
E13
LANTXD[1] IGNNE# AG26
AE22
IGNNE# R148 2 1 0_0402_5% H_IGNNE#
H_IGNNE# <5> Dothan-A, Populte zero ohm for
LANTXD[2] INIT3_3V#
INIT# AF27
AG24
ICH4_INIT#
INTR
R159
R139
2
2
1 0_0402_5%
1 0_0402_5%
H_INIT#
H_INTR H_INIT# <5> Dothan-B.
INTR H_INTR <5>
<29,35> IAC_BITCLK C10 ACZ_BIT_CLK
AC-97/AZALIA
1 2 ICH_AC_SYNC_R B9 AD23 KBRST#
<29> IAC_SYNC ACZ_SYNC RCIN# KBRST# <32>
33_0402_5% R91
C ICH_AC_RST_R# NMI R147 H_NMI C
<29> IAC_RST# 1 2 A10 ACZ_RST# NMI AF25 2 1 0_0402_5% H_NMI <5>
2
33_0402_5% R104 AG27 SMI# R151 2 1 0_0402_5% H_SMI#

IAC_SDATAI1 SMI# H_SMI# <5>
R483 F11
<29> IAC_SDATAI1 IAC_SDATAI2 ACZ_SDIN[0] STPCLK# H_STPCLK#
10_0402_5% F10 AE26 R160 2 1 0_0402_5%
<35> IAC_SDATAI2 ACZ_SDIN[1] STPCLK# H_STPCLK# <5>
@ B10
R95 ACZ_SDIN[2] THRMTRIP_ICH# H_THERMTRIP#
AE23 1 2 R541
ICH_AC_BITCLK_TERM 1
ICH_AC_SDOUT_R THRMTRIP# 56_0402_5%

<29> IAC_SDATO 1 2 C9 ACZ_SDO
33_0402_5% AC16 IDE_DA0
DA[0] IDE_DA1 IDE_HDA0 <23>
AC19 AB17 IDE_HDA1 <23>
SATALED# DA[1] IDE_DA2
AC17 IDE_HDA2 <23>
DA[2]
AE3 AD16 IDE_DCS1#
SATA[0]RXN DCS1# IDE_DCS3# IDE_HDCS1# <23>
AD3 AE17 IDE_HDCS3# <23>
SATA[0]RXP DCS3#
AG2
SATA[0]TXN
AF2 IDE_HDD[0..15] <23>
SATA[0]TXP IDE_HDD0
AD14
DD[0]
SATA
2 AD7 AF15 IDE_HDD1
SATA[2]RXN DD[1]
PIDE
AC7 AF14 IDE_HDD2
C458 SATA[2]RXP DD[2] IDE_HDD3
AF6 AD12
@ 10P_0402_50V8J SATA[2]TXN DD[3] IDE_HDD4
AG6 AE14
1 SATA[2]TXP DD[4] IDE_HDD5
AC11
DD[5] IDE_HDD6
AC2 AD11
SATA_CLKN DD[6] IDE_HDD7
AC1 AB11
SATA_CLKP DD[7] IDE_HDD8
AE13
DD[8] IDE_HDD9
AG11 AF13
SATARBIAS# DD[9] IDE_HDD10
1 2 AF11
SATARBIAS DD[10]
AB12
R101 AB13 IDE_HDD11
24.9_0603_1% DD[11] IDE_HDD12
AC13
R96 DD[12] IDE_HDD13
AE15
33_0402_5% DD[13] IDE_HDD14
AG15
DD[14]
<35> IAC_SDATO_MDC 1 2 ICH_AC_SDOUT_R <23> IDE_HIORDY
IDE_HDIORDY AF16 AD13 IDE_HDD15
B IDE_HIRQ IORDY DD[15] B
<23> IDE_HIRQ AB16
R92 IDE_HDDACK# IDEIRQ
<23> IDE_HDACK# AB15
33_0402_5% IDE_HDIOW# DDACK# IDE_DDREQ IDE_HDREQ
<23> IDE_HDIOW# AC14 AB14 1 2 IDE_HDREQ <23>
DIOW# DDREQ
<35> IAC_SYNC_MDC 1 2 ICH_AC_SYNC_R <23> IDE_HDIOR#
IDE_HDIOR# AE16
DIOR#
R496
33P_0402_50V8J
0_0402_5%
R105 2
33_0402_5% ICH6_BGA609
C461
<35> IAC_RST#_MDC 1 2 ICH_AC_RST_R#
1 R762
+3VS +3VS 47K_0402_5%
+CPU_CORE 1 2
MAINPWRON <39,41,44>
1
R561
1
R114 R504 @ 47K_0402_5% C
4.7K_0402_5% 10K_0402_5% 1 2 2 Q39
+VCCP B 2SC2411K_SC59
1 2 E
2
3
IDE_HDIORDY IDE_HIRQ @ C526
0.68U_0603_10V6K
1 2 H_THERMTRIP#
+VCCP R494
75_0402_5%
<5,8> H_THERMTRIP#
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+3VS +3VSUS
10K_0402_5%
10K_0402_5%
1
1
R117
R71
2
2
U7C
ICH_RI# T2 H25 OVCUR#0 R781 1 2 10K_0402_5%
D RI# PERn[1] PAD T21 +3VSUS D
H24 @ OVCUR#1 R782 1 2 10K_0402_5%
PERp[1] PAD T40 OVCUR#2
R120 @1 2 33_0402_5% AF17 G27 @ R783 1 2 10K_0402_5%
SATA[0]GP/GPI[26] PETn[1] PAD T23 OVCUR#3
AE18 G26 @ R784 1 2 10K_0402_5%
+3VSUS SATA[1]GP/GPI[29] PETp[1] PAD T22
+3VSUS AF18 @
SATA[2]GP/GPI[30]
AG18 K25
SATA[3]GP/GPI[31] PERn[2]
K24
ICH_SMBCLK PERp[2]
Y4 J27
SMBCLK PETn[2]
2.2K_0402_5%
2.2K_0402_5% ICH_SMBDATA W5 J26
PCI-EXPRESS
SMBDATA PETp[2]
10K_0402_5%
10K_0402_5%
LINKALERT# Y5 OVCUR#4 R785 1 2 10K_0402_5%
ICH_SMLINK0 LINKALERT# OVCUR#5 R786 10K_0402_5%
W4 M25 1 2
SMLINK[0] PERn[3]
2
GPIO
ICH_SMLINK1 U6 M24 OVCUR#6 R787 1 2 10K_0402_5%
SMLINK[1] PERp[3]
2
2
MCH_SYNC# AG21 L27 OVCUR#7 R788 1 2 10K_0402_5%
MCH_SYNC# PETn[3]
R461
R460
SPKR F8 L26
<30> SPKR SPKR PETp[3]
R449
R450 T30 PAD W3 P24

1
@ SUS_STAT#/LPCPD# PERn[4]
P23
1
1 SYS_RESET# PERp[4]
U2 SYS_RESET# PETn[4] N27
PETp[4] N26
ICH_SMBDATA PM_BMBUSY# AD19
<18> ICH_SMBDATA ICH_SMBCLK <8> PM_BMBUSY# BM_BUSY#/GPI[6] DMI_RXN0
<18> ICH_SMBCLK 1 2 T25 DMI_RXN0 <8>
ICH_SMLINK0 @ R729 0_0402_5% R510 1 DMI[0]RXN DMI_RXP0
+3VS 2 10K_0402_5% AE19 GPI[7] DMI[0]RXP T24 DMI_RXP0 <8>
ICH_SMLINK1 EC_SMI# R1 R27 DMI_TXN0
<32> EC_SMI# GPI[8] DMI[0]TXN DMI_TXP0 DMI_TXN0 <8>
DMI[0]TXP R26 DMI_TXP0 <8>
ACINA
S
<32,40,41> ACIN 1 3 W6 SMBALERT#/GPI[11]
DIRECT MEDIA INTERFACE

Q47 V25 DMI_RXN1
DMI[1]RXN DMI_RXP1 DMI_RXN1 <8>
<32> LID_SWOUT# M2 GPI[12] DMI[1]RXP V24 DMI_RXP1 <8>
2N7002_SOT23 EC_SCI# R6 U27 DMI_TXN1
G
2
+3V <32> EC_SCI# GPI[13] DMI[1]TXN DMI_TXP1 DMI_TXN1 <8>
DMI[1]TXP U26 DMI_TXP1 <8>
H_STP_PCI# AC21
<18> H_STP_PCI# STP_PCI#/GPO[18]
R761 1 2 10K_0402_5% Y25 DMI_RXN2
AB21 GPO[19] DMI[2]RXP Y24 DMI_RXP2 <8>
W27 DMI_TXN2
C H_STP_CPU# DMI[2]TXN DMI_TXP2 DMI_TXN2 <8> C
<18,45> H_STP_CPU# AD22 STP_CPU#/GPO[20] DMI[2]TXP W26 DMI_TXP2 <8>
AB24 DMI_RXN3
+3V R507 1 2 @ 10K_0402_5% AD20 AB23
GPO[21] DMI[3]RXP DMI_TXN3 DMI_RXP3 <8>
<16,19> PLTRST_VGA# 1 2 AD21 GPO[23] DMI[3]TXN AA27 DMI_TXN3 <8>
R536 @ 0_0402_5% AA26 DMI_TXP3
DMI[3]TXP DMI_TXP3 <8>
<23> IDE_HRESET# V3 GPIO[24]
AD25 CLK_PCIE_ICH#
DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# <18>
<23> IDE_DRESET# P5 AC25 CLK_PCIE_ICH <18>
GPIO[25] DMI_CLKP
R3
GPIO[27]
<33> EC_FLASH# T3
CLKRUN# GPIO[28]
<24,26,28,31,32> CLKRUN# AF19 F24
CLKRUN#/GPIO[32] DMI_ZCOMP R517 24.9_0603_1%
AF20
GPIO[33] DMI_IRCOMP
AC18 F23 1 2 +1.5VS
GPIO[34] DMI_IRCOMP
ICH_PCIE_WAKE# U5 C23 OVCUR#4
WAKE# OC[4]#/GPI[9] OVCUR#4 <36>
D23 OVCUR#5 closed to 500 mils
SIRQ R7461 OC[5]#/GPI[10] OVCUR#6
<26,31,32> SIRQ 20_0402_5% AB20
SERIRQ OC[6]#/GPI[14]
C25
C24 OVCUR#7
SIO_THRM# OC[7]#/GPI[15]
AC20
THRM# OVCUR#0
C27 OVCUR#0 <36>
VGATE OC[0]# OVCUR#1
<8,18,45> VGATE AF21 B27 OVCUR#1 <36>
VRMPWRGD OC[1]# OVCUR#2
B26
+3VS CLK_14M_ICH OC[2]# OVCUR#3
E10 C26 OVCUR#3 <36>
CLK14 OC[3]#
CLK_48M_ICH A27 C21 USBP0-
CLOCK
CLK48 USBP[0]N USBP0- <36>
1
(PCI Express Wake Event) T32 D21 USBP0+ USBP0+ <36>

R125 PAD ICH_SUSCLK USBP[0]P USBP1-
V6 A20 USBP1- <36>
10K_0402_5% @ SUSCLK USBP[1]N USBP1+
B20 USBP1+ <36>
SLP_S3# USBP[1]P USBP2-
<32> SLP_S3# T4 D19 USBP2- <35>
SLP_S4# SLP_S3# USBP[2]N USBP2+
T5 C19 USBP2+ <35>
2
CLKRUN# <32> SLP_S4# SLP_S5# SLP_S4# USBP[2]P USBP3-
USB
<32> SLP_S5# T6 A18 USBP3- <36>
B SLP_S5# USBP[3]N USBP3+ B
B18 USBP3+ <36>
ICH_PWRGD USBP[3]P USBP4-
<32> ICH_PWRGD AA1 E17 USBP4- <36>
PWROK USBP[4]N
POWER MGT
D17 USBP4+ USBP4+ <36>
PM_DPRSLPVR USBP[4]P USBP5-
<45> PM_DPRSLPVR AE20 B16 USBP5-
DPRSLPVR/TP[1] USBP[5]N USBP5+
A16 USBP5+
ICH_BATLOW# USBP[5]P USBP6-
<32> ICH_BATLOW# V2 C15 USBP6-
BATLOW#/TP[0] USBP[6]N USBP6+
D15 USBP6+
PWRBTN_OUT# USBP[6]P USBP7-
<32> PWRBTN_OUT# U1 A14 USBP7-
PWRBTN# USBP[7]N USBP7+
B14 USBP7+
PLTRST# USBP[7]P
<19> PLTRST# V5
LAN_RST# USBRBIAS
A22 1 2
RSMRST# USBRBIAS#
<32> RSMRST# Y3 B22
RSMRST# USBRBIAS R141
10K_0402_5%
10K_0402_5%
ICH6_BGA609 22.6_0603_1%
1
CLK_14M_ICH
<18> CLK_14M_ICH
CLK_48M_ICH
<18> CLK_48M_ICH
R75
R459
R457
2
+3VS 10K_0402_5% R529 D15

1 2 LINKALERT# 8.2K_0402_5%
+3VSUS
10_0402_5%
10_0402_5%
1 2 SIO_THRM# 2 1
+3VS EC_THRM# <32>
2
2
1K_0402_5%
R69
R516
R487
R556
10K_0402_5% R130
SYS_RESET# 10K_0402_5% RB751V_SOD323
+3VSUS 1 2
+3VS 1 2 MCH_SYNC#
@ @ R456
1
@ 10K_0402_5% R518
ACINA
CK_14M_ICH_TERM
CK_48M_ICH_TERM
+3VSUS 1 2 10K_0402_5% R725 39K_0402_5%

PM_DPRSLPVR 1 2 SIRQ 1 2
+3VS
R455
100K_0402_5%
10K_0402_5%
1
A ICH_BATLOW# A
+3VSUS 1 2
R523
@ R451
4.7P_0402_50V8C
4.7P_0402_50V8C
680_0402_5%
1 2 ICH_PCIE_WAKE#
+3VSUS
2
2 2
C455
C520
1 1 Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title

May need pulldown for DPRSLPVR in case <Title>
@ @
the ICH6m does not set this value in time AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
for boot. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomLA-2362 1
5 4 3 2 1
5 4 3 2 1
+1.5VS
C497
0.1U_0402_16V4Z
Near PIN F27(C968), 1 2
+1.5VS
L27 0_0603_5% P27(C949), AB27(C950) U7E C477
0.1U_0402_16V4Z U7D
+5VS +3VS 1 2 +1.5VRUN_L AA22 F9 1 2 E27 F4
+1.5VS VCC1_5[1] VCC1_5[98] VSS[172] VSS[86]
220U_D2_4VM
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 AA23 VCC1_5[2] VCC1_5[97] U17 Y6 VSS[171] VSS[85] F22
D4 2 2 2 AA24 U16 C471 Y27 F19
VCC1_5[3] VCC1_5[96] VSS[170] VSS[84]
2
2
+ AA25 U14 0.1U_0402_16V4Z Y26 F17
VCC1_5[4] VCC1_5[95] VSS[169] VSS[83]
C521
C513
C501
R103 AB25 U12 1 2 Y23 E25
VCC1_5[5] VCC1_5[94] VSS[168] VSS[82]
C524
10_0402_5% AB26 U11 W7 E19
D 2 1 1 1 VCC1_5[6] VCC1_5[93] C491 VSS[167] VSS[81] D
RB751V_SOD323 AB27 T17 W25 E18
VCC1_5[7] VCC1_5[92] 0.1U_0402_16V4Z VSS[166] VSS[80]
F25 T11 W24 E15
1
VCC1_5[8] VCC1_5[91] VSS[165] VSS[79]

F26 P17 1 2 W23 E14
ICH_V5REF_RUN VCC1_5[9] VCC1_5[90] VSS[164] VSS[78]
F27 P11 W1 D7
VCC1_5[10] VCC1_5[89] C492 VSS[163] VSS[77]
2 2 2 G22 M17 V4 D22
CORE
C115 C485 VCC1_5[11] VCC1_5[88] 0.1U_0402_16V4Z VSS[162] VSS[76]
G23 M11 V27 D20
1U_0603_10V4Z 0.1U_0402_16V4Z C439 VCC1_5[12] VCC1_5[87] VSS[161] VSS[75]
G24 L17 1 2 V26 D18
0.1U_0402_16V4Z VCC1_5[13] VCC1_5[86] VSS[160] VSS[74]
G25 L16 V23 D14
1 1 1 VCC1_5[14] VCC1_5[85] C474 VSS[159] VSS[73]
H21 L14 U25 D13
H22 L12 U24 D10
VCC1_5[16] VCC1_5[83] VSS[157] VSS[71]
J21 L11 1 2 U23 D1
VCC1_5[17] VCC1_5[82] VSS[156] VSS[70]
J22 VCC1_5[18] VCC1_5[81] AA21 U15 VSS[155] VSS[69] C4
K21 AA20 C454 U13 C22
K22 VCC1_5[20] VCC1_5[79] AA19 T7 VSS[153] VSS[67] C20
PCIE
L21 VCC1_5[21] 1 2 T27 VSS[152] VSS[66] C18
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L22 VCC1_5[22] T26 VSS[151] VSS[65] C14
1 1 1 1 1 1 M21 AA10 +3VS C453 T23 B25
VCC1_5[23] VCC3_3[21] VSS[150] VSS[64]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M22 AG19 0.1U_0402_16V4Z T16 B24
VCC1_5[24] VCC3_3[20] VSS[149] VSS[63]
C706
C707
C708
C709
C710
C711
N21 VCC1_5[25] VCC3_3[19] AG16 2 2 1 2 T15 VSS[148] VSS[62] B23
C462
C484
N22 VCC1_5[26] VCC3_3[18] AG13 T14 VSS[147] VSS[61] B21
2 2 2 2 2 2 C464
N23 VCC1_5[27] VCC3_3[17] AD17 T13 VSS[146] VSS[60] B19
N24 AC15 Near PIN 0.1U_0402_16V4Z T12 B15
VCC1_5[28] VCC3_3[16] 1 1 VSS[145] VSS[59]
N25 AA17 1 2 T1 B13
IDE
VCC1_5[29] VCC3_3[15] AG13, AG16 VSS[144] VSS[58]
P21 VCC1_5[30] VCC3_3[14] AA15 R4 VSS[143] VSS[57] AG7
+5VALW +3VSUS P25 AA14 C434 R25 AG3
P26 VCC1_5[32] VCC3_3[12] AA12 R24 VSS[141] VSS[55] AG22
D5 P27 1 2 R23 AG20
VCC1_5[33] VSS[140] VSS[54]
2
R21 VCC1_5[34] R17 VSS[139] VSS[53] AG17

R129 R22 P1 +3VS C515 R16 AG14
VCC1_5[35] VCC3_3[11] VSS[138] VSS[52]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10_0402_5% T21 M7 2 2 2 0.01U_0402_16V7K R15 AG12
VCC1_5[36] VCC3_3[10] VSS[137] VSS[51]
C396
RB751V_SOD323 T22 VCC1_5[37] VCC3_3[9] L7 1 2 R14 VSS[136] VSS[50] AG1
C394
C425
U21 L4 R13 AF7
1
C ICH_V5REF_SUS VCC1_5[38] VCC3_3[8] VSS[135] VSS[49] C

U22 VCC1_5[39] VCC3_3[7] J7
1 1 1 Near PIN A25 R12 VSS[134] VSS[48] AF3
2 2 V21 VCC1_5[40] VCC3_3[6] H7 R11 VSS[133] VSS[47] AF26
C136 C506 C493
PCI
V22 VCC1_5[41] VCC3_3[5] H1 P22 VSS[132] VSS[46] AF12
1U_0603_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
GROUND
W21 VCC1_5[42] VCC3_3[4] E4 P16 VSS[131] VSS[45] AF10
1 1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN 1 2 P15 VSS[130] VSS[44] AF1
Y21 VCC1_5[44] VCC3_3[2] A6 P14 VSS[129] VSS[43] AE7
Y22 A2-A6, D1-H1 Near PIN AA19 P13 AE6
VCC1_5[45] VSS[128] VSS[42]
U7 P12 AE25
VCCSUS1_5[3] +1.5VR VSS[127] VSS[41]
AA6 R7 N7 AE21
+1.5VS VCC1_5[46] VCCSUS1_5[2] VSS[126] VSS[40]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AB4 N17 AE2
VCC1_5[47] VSS[125] VSS[39]
0.1U_0402_16V4Z
AB5 2 1 N16 AE12

VCC1_5[48] VSS[124] VSS[38]
USB
2 AB6 G19 +1.5VR N15 AE11
VCC1_5[49] VCCSUS1_5[1] VSS[123] VSS[37]
0.1U_0402_16V4Z
AC4 N14 AE10
VCC1_5[50] VSS[122] VSS[36]
C405
C440
C435
AD4 G20 1 N13 AD6
VCC1_5[51] VCC1_5[78] 1 2 VSS[121] VSS[35]
AE4 F20 N12 AD24
1 VCC1_5[52] VCC1_5[77] VSS[120] VSS[34]
Near PIN AG5 AE5
VCC1_5[53] VCC1_5[76]
E24 N11
VSS[119] VSS[33]
AD2
SATA
Replacing by this circuit? AF5
VCC1_5[54] VCC1_5[75]
E23
2
N1
VSS[118] VSS[32]
AD18
C488
USB CORE
AG5 E22 M4 AD15
VCC1_5[55] VCC1_5[74] VSS[117] VSS[31]
E21 M27 AD10
VCC1_5[73] VSS[116] VSS[30]
Note: Intel will update design guide. +1.5VS
AA7
VCC1_5[56] VCC1_5[72]
E20 Near PIN U7 M26
VSS[115] VSS[29]
AD1
0.1U_0402_16V4Z
AA8 D27 M23 AC6

VCC1_5[57] VCC1_5[71] VSS[114] VSS[28]
AA9 D26 M16 AC3
VCC1_5[58] VCC1_5[70] VSS[113] VSS[27]
2 AB8 D25 M15 AC26
VCC1_5[59] VCC1_5[69] VSS[112] VSS[26]
C426
AC8 D24 +1.5VS M14 AC24

ICH_V5REF_RUN VCC1_5[60] VCC1_5[68] VSS[111] VSS[25]
+5V 1 2 Near PIN AG9 AD8
VCC1_5[61] +2.5VS
M13
VSS[110] VSS[24]
AC23
AE8 G8 M12 AC22
R97 1 VCC1_5[62] VCC1_5[67] VSS[109] VSS[23]
AE9 L25 AC12
10_0402_5% VCC1_5[63] VSS[108] VSS[22]
AF9 AB18 L24 AC10
VCC1_5[64] PCI/IDE RBP VCC2_5[4] VSS[107] VSS[21]
@ AG9 P7 L23 AB9
VCC1_5[65] VCC2_5[2] VSS[106] VSS[20]
0.1U_0402_16V4Z
L15 AB7
ICH6_VCCPLL AC27 ICH_V5REF_RUN VSS[105] VSS[19]
AA18 1 L13 AB2
VCCDMIPLL V5REF[2] VSS[104] VSS[18]
E26 A8 K7 AB19
B +3VS VCC3_3[1] V5REF[1] VSS[103] VSS[17] B
K27 AB10
VSS[102] VSS[16]
0.1U_0402_16V4Z
AE1 F21 ICH_V5REF_SUS K26 AB1

+1.5VS VCCSATAPLL V5REF_SUS 2 VSS[101] VSS[15]
C486
1 2 ICH_V5REF_SUS 2 AG10 K23 AA4
+5VALW +3VS VCC3_3[22] +3VSUS VSS[100] VSS[14]
C514
0.1U_0402_16V4Z
2 A25 +1.5VS K1 AA16

R127 VCCUSBPLL VSS[99] VSS[13]
A13 A24 J4 AA13
VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] VSS[98] VSS[12]
C395
10_0402_5% F14 J25 AA11

1 +3VS VCCLAN3_3/VCCSUS3_3[2] +3VSUS VSS[97] VSS[11]
@ G13 AB3 +RTCVCC J24 A9
1 VCCLAN3_3/VCCSUS3_3[3] VCCRTC C660 VSS[96] VSS[10]
+3VALW +3V +3VSUS
G14
VCCLAN3_3/VCCSUS3_3[4] Near PIN AB18 0.1U_0402_16V4Z
J23
VSS[95] VSS[9]
A7
G11 H27 A4
VCCLAN1_5/VCCSUS1_5[2] VSS[94] VSS[8]
A11 G10 +1.5VS 1 2 H26 A26
VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] VSS[93] VSS[7]
Near PIN U4
VCCSUS3_3[2]
H23
VSS[92] VSS[6]
A23
R779 V1 AG23 C661 G9 A21
+3VSUS 0_0805_5% U8 APL5301-15DC_3P E26, E27 VCCSUS3_3[3] V_CPU_IO[3] 0.1U_0402_16V4Z VSS[91] VSS[5]
@
V7
VCCSUS3_3[4] V_CPU_IO[2]
AD26 +VCCP Near PIN AG23 G7
VSS[90] VSS[4]
A19
Near PIN AE1 W2
VCCSUS3_3[5] V_CPU_IO[1]
AB22 1 2 G21
VSS[89] VSS[3]
A15
0.1U_0402_16V4Z
2 Vin +1.5VR
Vout 3
Y7 G12 A12
GND
R778 +3VSUS VCCSUS3_3[6] C397 VSS[88] VSS[2]

1 1 G16 1 G1 A1
0_0805_5% VCCSUS3_3[19] 0.1U_0402_16V4Z VSS[87] VSS[1]
A17 G15
VCCSUS3_3[7] VCCSUS3_3[18]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C111 C110 B17 F16 1 2 ICH6_BGA609

1
C509
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 C17 F15
2 2 VCCSUS3_3[9] VCCSUS3_3[16] 2 C436
F18 E16
C490
C489
G17 D16 0.1U_0402_16V4Z

G18 C16 1 2
1 1 VCCSUS3_3[12] VCCSUS3_3[13] +3VS +RTCVCC
C467 C472
ICH6_BGA609 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near PIN A17
L28 C510 1 1
R559 CHB1608U301_0603 C447 0.1U_0402_16V4Z
1 2 1 2 ICH6_VCCPLL 1 2 1 2
+1.5VS
0.01U_0402_16V7K
2 2
C401
C417
0.1U_0402_16V4Z
1_0402_5% 0.1U_0402_16V4Z Near PIN A24

A A
2 1
C517
C519
Near PIN AG10

1 2

Near PIN Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
<Title>
AC27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
5 4 3 2 1
A B C D E F G H
+3VS
1
IDE_HDD0
IDE_HDD1
IDE_HDD[0..15] <20>
R813
0_0402_5%
CD-ROM Connector
@
IDE_HDD2
2
1 IDE_HDD3 1
IDE_HDD4 C595 C594
IDE_HDD5 1 2 1 2
HDD Connector
2
IDE_HDD6
@ <29> INT_CD_L
IDE_HDD7 47P_0402_25V8K 47P_0402_25V8K
IDE_HDD8 RB751V_SOD323
IDE_HDD9 D27 <29> CD_GNA
JCDR1
IDE_HDD10 C593 47P_0402_50V8J Q48
1
IDE_HDD11 2N7002_SOT23 1 2 INT_CD_R <29>
JHDD1 1 2
IDE_HDD12 IDE_HRESET# 3 4 IDE_HDD8
<21> IDE_HRESET# 2 1
IDE_HDD13 IDE_HDD7 2 1 IDE_HDD8 IDE_DRESET# IDE_HDD7 5 6 IDE_HDD9
S
4 3 <21> IDE_DRESET# 1 3
IDE_HDD14 IDE_HDD6 4 3 IDE_HDD9 IDE_HDD6 7 8 IDE_HDD10
6 6 5 5 9 10
IDE_HDD15 IDE_HDD5 8 7 IDE_HDD10 IDE_HDD5 IDE_HDD11
IDE_HDD4 8 7 IDE_HDD11 IDE_HDD4 11 12 IDE_HDD12
10 9 2 1
G
2
IDE_HDD3 10 9 IDE_HDD12 +5VS IDE_HDD3 13 14 IDE_HDD13
12 11 0_0402_5% R814
IDE_HDD2 12 11 IDE_HDD13 IDE_HDD2 15 16 IDE_HDD14
14 14 13 13 17 18
IDE_HDD1 16 15 IDE_HDD14 +5VMOD IDE_HDD1 IDE_HDD15
IDE_HDD0 16 15 IDE_HDD15 IDE_HDD0 19 20 IDE_HDREQ
18 18 17 17 21 22
10K_0402_5%
20 19 IDE_HDIOR#
20 19 23 24
2
IDE_HDREQ 22 21 IDE_HDIOW#
<20> IDE_HDREQ 22 21 25 26
R703
IDE_HDIOW# 24 23 IDE_HIORDY IDE_HDACK#
<20> IDE_HDIOW# IDE_HDIOR# 24 23 IDE_HIRQ 27 28
<20> IDE_HDIOR# 26 26 25 25 29 30
IDE_HIORDY 28 27 R308 1 2 470_0402_5% IDE_HDA1 PDIAG#
<20> IDE_HIORDY IDE_HDACK# 28 27 IDE_HDA0 31 32 IDE_HDA2
30 29
1
<20> IDE_HDACK# IDE_HIRQ 30 29 IDE_DCS1# 33 34 IDE_HDCS3#
32 31 R310 1 2 10K_0402_5% @
<20> IDE_HIRQ 32 31 35 36
2
IDE_HDA1 34 33 PDIAG# HDD_ACT#
<20> IDE_HDA1 IDE_HDA0 34 33 IDE_HDA2 37 38
36 35 R702
<20> IDE_HDA0 IDE_DCS1# 36 35 IDE_HCS3# IDE_HDA2 <20> 39 40
<20> IDE_HDCS1# 38 38 37 37 IDE_HDCS3# <20> +5VMOD 41 42 +5VMOD
2
1 2 HDD_ACT# 40 39 4.7K_0402_5%
R318 10K_0402_5% 40 39 R315 43 44
42 41 +5VHDD
1
+5VHDD 42 41 SEC_CSEL 45 46
44 43 @ 10K_0402_5%
44 43 47 48
2 49 50 Layout Note: W=80 mils 2
46 45
1
GNDGND OCTEK_CDR-50JE2
ALLTOP_C17866-14405
IRQ how to assign
+5VHDD Source
@ R815
+5VS 1 2
1U_0603_10V4Z
0.1U_0402_16V4Z
HDD_ACT#
HDD_ACT# <33>
1 1 0_0805_5%
C656
C657
Q17 +5VHDD
2 2
AO3413_SOT23 Layout Note: Place close to HDD CONN.
S
3 1
G
2
+12VALW
1000P_0402_50V7K
10U_0805_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
1 1 1 1
1
C293
C296
C301
C294
R314
3 100K_0402_5% 3
2 2 2 2
+5VS
2
2
R317
470_0402_5% C292
1
0.01U_0402_16V7K
1
D
1
2 Q16 1
G 2N7002_SOT23
S R316
3
150K_0603_5%
+5VMOD Source +5VMOD

2
G
Layout Note: Place close to CD-ROM CONN.

+5VS 3 1
S
D
1U_0603_10V4Z
0.1U_0402_16V4Z
AO3413_SOT23
Q14
1000P_0402_50V7K
1 1
C658
10U_0805_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
C659
1 1 1 1
C281
2 2
C279
C278
C280
R816
2 2 2 2
1 2
4 4
0_0805_5%
@

<Title>
A B C D E F G H
5 4 3 2 1
LAN_IO LAN_IO
closed to chip about 200 mils
LAN_IO 1 1 1 1 1 2
C85 C86 C84 C69 C53 C35
2 2 2
C75 C63 C37 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 1
0.1U_0402_10V6K 0.1U_0402_10V6K
1 1 1
0.1U_0402_10V6K
+3VALW LAN_IO
R39
D 1 2 D
1 1
C33 0_0805_5% C40
LAN_IO
1U_0603_10V6K L10 @ 1U_0603_10V6K
2 2
1 2
KC FBM_L11-201209-601LMT 0805
1
R82
3.6K_0402_5%
2
2
U4 U6 C103
PCI_AD[0..31] PCI_AD0 104 108 4 5 0.1U_0402_10V6K
<19,26,27,28> PCI_AD[0..31] AD0 EEDO DO GND 1
PCI_AD1 103 109 3 6
PCI_AD2 AD1 AUX/EEDI DI NC
102 AD2 EESK 111 SK2 NC 7
PCI_AD3 98 106 1 8
AD3 EECS CS VCC LAN_IO
PCI_AD4 97 Y1
PCI_AD5 AD4 LAN_ACT# AT93C46-10SI-2.7_SO8 CLKOUT XTALFB
96 AD5 LED0 117 LAN_ACT# <25> 1 2
PCI_AD6 95 115 SPD_10_100_G#
AD6 LED1 SPD_10_100_G# <25>
PCI_AD7 93 114 25MHZ_20P_1BX25000CK1A
PCI_AD8 AD7 LED2
90 AD8 NC/LED3 113 1 2
PCI_AD9 89 C58 C60
PCI_AD10 AD9 LAN_TX0+
87 AD10 TXD+/MDI0+ 1 LAN_TX0+ <25>
PCI_AD11 86 2 LAN_TX0- 27P_0402_50V8J 27P_0402_50V8J
AD11 TXD-/MDI0- LAN_TX0- <25> 2 1
PCI_AD12 85 5 LAN_RX1+
AD12 RXIN+/MDI1+ LAN_RX1+ <25> +3VS
PCI_AD13 83 6 LAN_RX1-
AD13 RXIN-/MDI1- LAN_RX1- <25>
PCI_AD14 82
PCI_AD15 AD14 LAN_TX2+
79 AD15 NC/MDI2+ 14 LAN_TX2+ <25>
1
PCI_AD16 59 15 LAN_TX2-
AD16 NC/MDI2- LAN_TX2- <25>
PCI_AD17 58 18 LAN_TX3+ R43
AD17 NC/MDI3+ LAN_TX3+ <25>
PCI_AD18 57 19 LAN_TX3- 1K_0402_1%
AD18 NC/MDI3- LAN_TX3- <25>
PCI_AD19 55 @ R46
PCI_AD20 AD19 XTALFB @15K_0402_1%
53 121
2
PCI_AD21 AD20 X1 CLKOUT
C
50 AD21 X2 122 1 2 C
PCI_AD22 49
PCI_AD23
PCI_AD24
47
43
AD22
AD23
AD24
PCI I/F LWAKE
ISOLATE#
105
23 SUSP# <16,32,33,37,42>
PCI_AD25 42 127 R421 1 2 2.49K_0603_1%
PCI_AD26 AD25 RTSET
PCI_AD27
40
39
AD26 NC/SMBCLK 72
74
5.6k for 8100C
PCI_AD28 AD27 NC/SMBDATA closed to chip
37 AD28
PCI_AD29 36 88 R81 1 2 1K_0402_1%
PCI_AD30 AD29 NC/M66EN @ R721
34
PCI_AD31 AD30 0_0402_5% LAN_IO
33 10
AD31 NC/AVDDH 2@ 1
120 2
NC/HV
<19,26,27,28> PCI_C_BE0# 92
C/BE#0 R420 0_0402_5%
<19,26,27,28> PCI_C_BE1# 77 11 1 2
C/BE#1 NC/HSDAC+ R64 0_0402_5% +1.2V_LAN
<19,26,27,28> PCI_C_BE2# 60 123 1 2
C/BE#2 NC/HG R59 0_0402_5%
<19,26,27,28> PCI_C_BE3# 44 124 1 2
C/BE#3 NC/LG2 R58 0_0402_5%
126 1 2
R65 NC/LV2
PCI_AD17 1 2 0_0402_5% 46 2@
IDSEL
LAN I/F
<19,26,27,28> PCI_PAR 76
PAR +3VALW
<19,26,27,28> PCI_FRAME# 61 9
FRAME# NC/VSS
<19,26,27,28> PCI_IRDY# 63 13
IRDY# NC/VSS
<19,26,27,28> PCI_TRDY# 67
TRDY#
<19,26,27,28> PCI_DEVSEL# 68
DEVSEL#
<19,26,27,28> PCI_STOP# 69 22
STOP# NC/GND
48
NC/GND
3
<19,26,27,28> PCI_PERR# 70 62
PERR# NC/GND Q32 +2.5V_LAN
<19,26,28> PCI_SERR# 75 73
SERR# NC/GND CTL25
112 1 2SB1188_SOT89
NC/GND
<19> PCI_REQ0# 30 118
REQ# NC/GND
<19> PCI_GNT0# 29 1 2
GNT#
2 1 L21 0_0805_5% 2
2
25 C328 C356
<19> PCI_PIRQF# INTA#
8 CTL25 C332
CTRL25 LAN_IO 0.1U_0402_10V6K 10U_1206_6.3V6M 0.1U_0402_10V6K
<19,26,27,28,31,32> ICH_PME# 31
PME# CTL12 1 2 1
B 125 B
RTT3/CRTL18
3
PCIRST# 27
<19,26,27,28,32> PCIRST# RST#
26 Q33
CLK_PCI_LAN VDD33 CTL12
<18> CLK_33M_LAN 28 41 1 2SB1188_SOT89
CLK VDD33
<21,26,28,31,32> CLKRUN# 2 1 65
CLKRUN# VDD33
56
R80 71
0_0402_5% @ VDD33
84 1 2 1
2
VDD33 0.1U_0402_10V6K 0.1U_0402_10V6K
94
VDD33 C335 +1.2V_LAN
107
VDD33
2
4 C333 10U_1206_6.3V6M C364

GND/VSS 1@ +2.5V_LAN 2 1 2
17
CLK_PCI_LAN GND/VSS R386
128 1 2
GND/VSS R379 2@ L22 0_0805_5%
3 0_0603_5%
AVDD33/AVDDL
1
7 0_0603_5%
1
R45 @ AVDD33/AVDDL
21 20 2 2 1 2
GND/VSSPST AVDD33/AVDDL
2
10_0402_5% 38 16 C36 C38

GND/VSSPST NC/AVDDL 1@
51
GND/VSSPST 0.1U_0402_10V6K 0.1U_0402_10V6K R390 +1.2V_LAN
66
2
GND/VSSPST 1 1
81
1
@ GND/VSSPST VDD25/VDD18 32 0_0603_5%
91
VDD25/VDD18 54
1
C34 GND/VSSPST 2@ 2
101
4.7P_0402_50V8B GND/VSSPST VDD25/VDD18 78 R395
1
0_0603_5%
119 99 2 2
GND/VSSPST VDD25/VDD18
2
2 R399 C89 C90

Power
35 24 2@ 0_0603_5% 0.1U_0402_10V6K
GND NC/VDD18 1 1
52 45
GND NC/VDD18
80 64
1
GND NC/VDD18 0.1U_0402_10V6K

100 110
GND NC/VDD18
116
NC/VDD18
12
AVDD25/HSDAC-
RTL8100CL_LQFP128 LAN_IO +2.5V_LAN
A A
R48 0_0402_5%
1 2
2@
R47 0_0402_5%
1 2
1@

<Title>
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CustomLA-2362 1
5 4 3 2 1
5 4 3 2 1
T28
C3751 2 0.1U_0402_16V4Z V_DAC 1 24 2@ R789 1 2 75_0402_1% C32
2@ TCT1 MCT1 2@ R790 75_0402_1% 1000P_1206_2KV7K
1 2
LAN_TX3+ 2 1:1 23 RJ45_TX3+ 2@ R791 1 2 75_0402_1%
<24> LAN_TX3+ TD1+ MX1+ 2@ R792 1 2 75_0402_1% 2 1
JLAN1
<24> SPD_10_100_G# 12
LAN_TX3- Amber LED-
<24> LAN_TX3- 3 22 RJ45_TX3-
D TD1- MX1- T=10mil D
LAN_IO 1 2 11
C3741 V_DAC Amber LED+
2 0.1U_0402_16V4Z 4
TCT2 MCT2
21 R5
SHLD4
16
2@ RJ45_TX3-
300_0603_5% 8
LAN_TX2+ PR4-
<24> LAN_TX2+ 5 1:1 20 RJ45_TX2+ 15
TD21+ MX2+ RJ45_TX3+ SHLD3
7
PR4+
RJ45_RX1- 6
PR2-
LAN_TX2- 6 19 RJ45_TX2- RJ45_TX2- 5
<24> LAN_TX2- TD2- MX2- PR3-
C3731 2 0.1U_0402_16V4Z V_DAC 7 18 RJ45_TX2+ 4
TCT3 MCT3 PR3+
LAN_RX1+ 8 1:1 17 RJ45_RX1+ RJ45_RX1+ 3
<24> LAN_RX1+ TD3+ MX3+ PR2+
RJ45_TX0- 2 PR1-
SHLD2 14
RJ45_TX0+ 1
LAN_RX1- PR1+
<24> LAN_RX1- 9 TD3- MX3- 16 RJ45_RX1- SHLD1 13
<24> LAN_ACT# 10 Green LED-
C3701 2 0.1U_0402_16V4Z V_DAC 10 15
TCT4 MCT4 T=10mil
LAN_IO 1 2 9 Green LED+
LAN_TX0+ 11 1:1 14 RJ45_TX0+ R20 300_0603_5%
<24> LAN_TX0+ TD4+ MX4+ TYCO_1566597-1
LAN_TX0- 12 13 RJ45_TX0-
<24> LAN_TX0- TD4- MX4-
2@ 24HST1041A-3_24P R50 49.9_0402_1%C45 0.01U_0402_16V7K
LAN_TX0+ 1 2 1 2
C
RTL8110SBL used the 24HST1041A-3_24P R49 49.9_0402_1%
C
LAN_TX0- 1 2
RTL8100CL used the 24ST0023-3_24P
R52 49.9_0402_1%C46 0.01U_0402_16V7K
Layout Note LAN_RX1+ 1 2 1 2
24HST1041A-3 pls close to conn. R51 49.9_0402_1%
LAN_RX1- 1 2
Termination plane should be copled to chassis ground

R54 49.9_0402_1%C47 0.01U_0402_16V7K
and also depends on safety concern LAN_TX2+ 1 2 1 2
R53 49.9_0402_1%
T41 1:1 LAN_TX2- 1 2@ 2 2@
LAN_TX0- 8 9 RJ45_TX0- R56 49.9_0402_1%C42 0.01U_0402_16V7K
LAN_TX0+ TD- TX- RJ45_TX0+ LAN_TX3+
7 10 1 2@ 2 1 2
V_DAC TD+ TX+
1 2 0_0402_5% 6 11
1@ R811 CT CT R55 49.9_0402_1%
LAN_TX3- 1 2@ 2 2@
V_DAC 3 14
LAN_RX1- CT CT RJ45_RX1-
2 15
LAN_RX1+ RD- RX- RJ45_RX1+
1 16 2@
RD+ RX+
1
1 V_DAC 1 2 +2.5V_LAN
R759 R760
NS0013_16P 75_0402_1% 75_0402_1% R405 0_0402_5%
2@
2
1@
1@ 1@
B B
C1
1 2
0.1U_0402_16V4Z
C2
1 2
0.1U_0402_16V4Z
Termination plane should be copled
to chassis ground and also depends C19
on safety concern 1 2
0.1U_0402_16V4Z
Please close to LAN IC C11

1 2
0.1U_0402_16V4Z
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+3V +12VALW
+3V +12V +CBS_VCC
U30
+3V 13
+CBS_VCC +3V VCC
VCC 12
1
1 9 12V VCC 11
0.1U_0402_16V4Z
VPPEN0 R60 R61 R62 R63
VPPEN1 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% C407 +CBS_VPP 1
0.1U_0402_16V4Z
C427
CBS_VCCD0# 0.1U_0603_50V4Z
1
CBS_VCCD1# D 2
2
2 Q3 +5V 10 1
VPP 2
C414
G AO3400_SOT23
M13
M12
G13
N13
N12
D12
H11
1
D
G1
C8
N4
A7
B4
K2
F3
L9
L6
S 5
3
5V
0.1U_0402_16V4Z
U28 SD_EN# 1 2 2 Q2 6
D2 G AO3400_SOT23 5V 2
1
VCCD1#
VCCD0#
VPPD1
VPPD0
VCCA2
VCCA1
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
+SD_VCC
C386
D CBS_VCCD0# D
S 1
3
RB751V_SOD323 VCCD0 CBS_VCCD1#
1 1 VCCD1 2
15 VPPEN0
2 VPPD0
C78
C96
MS_EN# 1 2 14 VPPEN1
<19,24,27,28> PCI_AD[0..31] PCI_AD31 CBS_CAD31 VPPD1
C2 B2 D3 +3V
PCI_AD30 AD31 CAD31/D10 CBS_CAD30 2 2
C1 C3 3
AD30 CAD30/D9 RB751V_SOD323 3.3V
0.1U_0402_16V4Z
PCI_AD29 D4 B3 CBS_CAD29 4 8
AD29 CAD29/D1 3.3V OC
SHDN
PCI_AD28 D2 A3 CBS_CAD28 1
GND
AD28 CAD28/D8
C389
PCI_AD27 D1 C4 CBS_CAD27
PCI_AD26 AD27 CAD27/D0 CBS_CAD26 CP2211C1_SSOP16
E4 A6
AD26 CAD26/A0
Place close to JCBUS PCI_AD25 E3 D7 CBS_CAD25
16
PCI_AD24 AD25 CAD25/A1 CBS_CAD24 2
E2 AD24 CAD24/A2 C7
PCI_AD23 F2 A8 CBS_CAD23 +3V
+CBS_VCC PCI_AD22 AD23 CAD23/A3 CBS_CAD22
F1 AD22 CAD22/A4 D8
PCI_AD21 G2 A9 CBS_CAD21
+CBS_VPP PCI_AD20 AD21 CAD21/A5 CBS_CAD20 +CBS_VCC
G3 AD20 CAD20/A6 C9
PCI_AD19 H3 A10 CBS_CAD19 +CBS_VCC
AD19 CAD19/A25
47K_0402_5%
0.01U_0402_16V7K
0.01U_0402_16V7K
10U_0805_10V4Z
PCI_AD18 H4 B10 CBS_CAD18

AD18 CAD18/A7
47K_0402_5%
1 1 1 PCI_AD17 J1 D10 CBS_CAD17
PCI_AD16 AD17 CAD17/A24 CBS_CAD16 JCBS1
J2 AD16 CAD16/A17 E12
1
C423
C437
C432
PCI_AD15 N2 F10 CBS_CAD15

AD15 CAD15/IOWR#
47K_0402_5%
47K_0402_5%
R116
R122
PCI_AD14 M3 E13 CBS_CAD14 1 35
2 2 2 PCI_AD13 AD14 CAD14/A9 CBS_CAD13 CBS_CAD0 GND GND CBS_CCD1#
N3 AD13 CAD13/IORD# F13 2 D3 CD1# 36
1
PCI_AD12 K4 F11 CBS_CAD12 CBS_CAD1 3 37 CBS_CAD2
AD12 CAD12/A11 D4 D11
R490
R462
PCI_AD11 M4 G10 CBS_CAD11 @ CBS_CAD3 4 38 CBS_CAD4
2
PCI_AD10 AD11 CAD11/OE# CBS_CAD10 CBS_CAD5 D5 D12 CBS_CAD6
K5 AD10 CAD10/CE2# G11 5 D6 D13 39
PCI_AD9 L5 G12 CBS_CAD9 CBS_CAD7 6 40 CBS_RSVD/D14
PCI_AD8 AD9 CAD9/A10 CBS_CAD8 CBS_CC/BE0# D7 D14 CBS_CAD8 @
M5 H12 7 41
2
PCI_AD7 AD8 CAD8/D15 CBS_CAD7 CBS_CAD9 CE1# D15 CBS_CAD10
K6 AD7 CAD7/D7 H10 8 A10 CE2# 42
PCI_AD6 M6 J11 CBS_CAD6 CBS_CAD11 9 43 CBS_CVS1
PCI_AD5 AD6 CAD6/D13 CBS_CAD5 CBS_CAD12 OE# VS1# CBS_CAD13
N6 AD5 CAD5/D6 J12 10 A11 IORD# 44
PCI_AD4 M7
CARDBUS K13 CBS_CAD4 CBS_CAD14 11 45 CBS_CAD15
C PCI_AD3 AD4 CAD4/D12 CBS_CAD3 CBS_CC/BE1# A9 IOWR# CBS_CAD16 C
N7 AD3 CAD3/D5 J10 12 A8 A17 46
PCI_AD2 L7 K10 CBS_CAD2 CBS_CPAR 13 47 CBS_RSVD/A18
PCI_AD1 AD2 CAD2/D11 CBS_CAD1 CBS_CPERR# A13 A18 CBS_CBLOCK#
K7 AD1 CAD1/D4 K12 14 A14 A19 48
PCI_AD0 N8 L13 CBS_CAD0 CBS_CGNT# 15 49 CBS_CSTOP#
AD0 CAD0/D3 CBS_CINT# WE# A20 CBS_CDEVSEL#
16 IREQ# A21 50
PCI_C_BE3# E1 B7 CBS_CC/BE3# 17 51
<19,24,27,28> PCI_C_BE3# CBE3# CCBE3#/REG# +CBS_VCC VCC VCC +CBS_VCC
PCI_C_BE2# J3 A11 CBS_CC/BE2# +3V +CBS_VPP 18 52 +CBS_VPP
<19,24,27,28> PCI_C_BE2# CBE2# CCBE2#/A12 VPP1 VPP2
PCI_C_BE1# N1 E11 CBS_CC/BE1# CBS_CCLK 19 53 CBS_CTRDY#
<19,24,27,28> PCI_C_BE1# PCI_C_BE0# CBE1# CCBE1#/A8 CBS_CC/BE0# CBS_CIRDY# A16 A22 CBS_CFRAME#
<19,24,27,28> PCI_C_BE0# N5 H13 20 54
CBE0# CCBE0#/CE1# CBS_CC/BE2# A15 A23 CBS_CAD17
21 55
A12 A24
10U_0805_10V4Z
0.1U_0402_16V4Z
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
PCIRST# G4 B9 CBS_CRST# CBS_CAD18 22 56 CBS_CAD19
<19,24,27,28,32> PCIRST# PCIRST# CRST#/RESET A7 A25
PCI_FRAME# J4 B11 CBS_CFRAME# CBS_CAD20 23 57 CBS_CVS2
<19,24,27,28> PCI_FRAME# FRAME# CFRAME#/A23 A6 VS2#
PCI_IRDY# K1 A12 CBS_CIRDY# 2 1 1 1 1 1 1 1 1 CBS_CAD21 24 58 CBS_CRST#
<19,24,27,28> PCI_IRDY# PCI_TRDY# IRDY# CIRDY#/A15 CBS_CTRDY# CBS_CAD22 A5 RESET CBS_CSERR#
<19,24,27,28> PCI_TRDY# K3 A13 25 59
PCI_DEVSEL# L1 TRDY# CTRDY#/A22 CBS_CDEVSEL# CBS_CAD23 A4 WAIT# CBS_CREQ#
<19,24,27,28> PCI_DEVSEL# B13 26 60
PCI_STOP# DEVSEL# CDEVSEL#/A21 CBS_CSTOP# CBS_CAD24 A3 INPACK# CBS_CC/BE3#
<19,24,27,28> PCI_STOP# L2 C12 27 61
PCI_PERR# STOP# CSTOP#/A20 CBS_CPERR# 1 2 2 2 2 2 2 2 2 CBS_CAD25 A2 REG# CBS_CAUDIO
<19,24,27,28> PCI_PERR# L3 C13 28 62
PERR# CPERR#/A14 A1 SPKR#
C344
C324
C376
C381
C382
C325
C360
C338
PCI_SERR# M1 A5 CBS_CSERR# CBS_CAD26 29 63 CBS_CSTSCHNG
<19,24,28> PCI_SERR# SERR# CSERR#/WAIT# A0 STSCHG#
C351
PCI_PAR M2 D13 CBS_CPAR CBS_CAD27 30 64 CBS_CAD28
<19,24,27,28> PCI_PAR PCI_REQ1# PAR CPAR/A13 CBS_CREQ# CBS_CAD29 D0 D8 CBS_CAD30
<19> PCI_REQ1# A1 B8 31 65
PCI_GNT1# PCIREQ# CREQ#/INPACK# CBS_CGNT# CBS_RSVD/D2 D1 D9 CBS_CAD31
<19> PCI_GNT1# B1 C11 32 66 R481 C451
PCIGNT# CGNT#/WE# CBS_CCLK CBS_CCLKRUN# D2 D10 CBS_CCD2#
<18> CLK_33M_CBS H1 B12 33 67
PCICLK CCLK/A16 IOIS16# CD2# SDCLK
34 68 1 2 1 2
CBS_CSTSCHNG GND GND
<19,24,27,28,31,32> ICH_PME# L8 C5
RIOUT#_PME# CSTSCHG/BVD1_STSHG# CBS_CCLKRUN#
+3V 1 2 L11 D5
R406 10K_0402_5% SUSPEND# CCLKRUN#/WP_IOIS16# CBS_CCD2# SUPER_AC4-3000-250-3_RT 0_0402_5% 10P_0402_25V8K
PCI_AD20 1 2 CBS_IDSEL F4 D11 CBS_CCLK_INTERNAL 2 1 CBS_CBLOCK# CBS_CCD1# @ @
IDSEL CBLOCK#/A19
2
0_0402_5%
100_0402_5% R382 R377 47_0402_5%
R466 C402
R358
cardbus R7471 20_0402_5% K8 D6 CBS_CINT#
<19> PCI_PIRQA# MFUNC0 CINT#/READY_IREQ# MSCLK
N9 100K_0402_5% 2 1 R440 +3V R400 1 2 1 2
R7481 MFUNC1 CBS_SPK#
20_0402_5% K9 M9 0_0402_5%
1394 <19> PCI_PIRQB# N10
MFUNC2 SPKROUT
B5 CBS_CAUDIO CBS_SPK# <30>
1
B <21,31,32> SIRQ MFUNC3 CAUDIO/BVD2_SPKR# 0_0402_5% 10P_0402_25V8K B
L10
R7501 MFUNC4 CBS_CCD2#_INTERNAL +SD_VCC @ @
<33> CR_LED# 20_0402_5%N11 MFUNC5 CCD2#/CD2#
A4
2 1 M11 L12 CBS_CCD1#_INTERNAL @ @
<21,24,28,31,32> CLKRUN# MFUNC6 CCD1#/CD1# CBS_CVS2 SDDAT2
R751 @ 0_0402_5% D9 2 2 1 2 SD/ MMC/ MS
CVS2/VS2#
C322
270P_0402_50V7K
C361
270P_0402_50V7K
1 2 CBS_GRST#M10 C6 CBS_CVS1 43K_0402_5%1 2 R454 SDCMD +SD_VCC
CBS_RST# GRST# CVS1/VS1#
R442 43K_0402_5%1 2 R468 SDDAT0
@ 0_0402_5% 43K_0402_5%1 2 R495 SDDAT3 JSD1
1 1 43K_0402_5%1 2 R463 SDDAT1 SDDAT1 SD_8
43K_0402_5% R500 SDDAT0 SD_8
SD_7
SD_7
D3 SD_6
GND1 SDCLK SD_6
H2 SD_5
GND2 SD_5
L4 SD_4
GND3 SD_4
M8 SD_3
GND4 MSBS SDCMD SD_3
K11 2 1 SD_2
GND5 MSDATA0 R432 SD_2
GND6
F12 2 143K_0402_5% SD_1
SD_1
C10 MSDATA3 R419 2 143K_0402_5% SDDAT2 SD_9
GND7 MSDATA2 R402 SD_9
B6 2 143K_0402_5%
GND8 CBS_RSVD/D14 MSDATA1 R414 Footprint need to change for #3 <-->#13
J13 2 143K_0402_5% MS_1
CRSV1/D14 CBS_RSVD/A18 R431 43K_0402_5% MSBS MS_1
E10 MS_2 22
CRSV2/A18 CBS_RSVD/D2 MSDATA1 MS_2GND
A2 MS_3 23
CRSV3/D2 MSDATA0 MS_3GND
MS_4
MSDATA2 MS_4
MS_5
MSINS# MS_5
MS_6
CBS_CCLK +3V MSDATA3 MS_6
J9 H6 MS_7
MFUNC7 RSVD4 MSCLK MS_7
CLK_33M_CBS SD RSVD3
J7
J6 CBS_CCD2# CBS_CCD1# SDDAT3
MS_8
MS_9
MS_8
RSVD2 MS_9
1
+3V E7 J5 MS_10
@ +SD_VCC VCC_SD RSVD1 MS_10
100K_0402_5%
G5 R83
GND_SD
1
10_0402_5%
0_0402_5% 1 1 2 1 SDWP# SD_WP

SD_WP
1
R42
E6 SDDAT0 R505 2 43K_0402_5%

1 SDCD# SD_CD
SDPWREN33#
SDDAT0 SD_CD
R441
SDCD# SDDAT1 C368 C143 R439 43K_0402_5%

MSPWREN#
E8 F7
2
MSINS# SDCD# SDDAT1 SDDAT2 10P_0402_25V8K 10P_0402_25V8K PROCO_MDR019-20-1000

MSDATA3
MSDATA2
MSDATA1
MSDATA0
CK33M_CBS_TERM
H7 MSINS# SDDAT2 F5
A SDDAT3 2 2 A
SDCMD
SDCLKI
G6
MSCLK
SDCLK
1
2
SDDAT3
SDWP
MSBS
@
2
C95 @ @
CBS_GRST# 10P_0402_25V8K
CB712_LFBGA169 2
E9
F6
E5
F8
H5
H8
J8
G7
F9
G8
H9
G9
@
1U_0603_10V4Z
4.7P_0402_50V8C
1 @
MSCLK
C384
SDCLK
MS_EN#
SD_EN#
2
C41
SDCMD MSDATA0 2005/03/01 2006/03/01 Title

2 SDWP# MSDATA1
Issued Date Deciphered Date <Title>
MSDATA2
1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 MSDATA3 Size Document Number Rev
43K_0402_5% R391 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomLA-2362 1
MSBS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
+3VS
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K +3VS

1 1 1 1 1 1 1 1 1
C129 C149 C138 C146 C147 C125 C142 C117 C148
0.1U_0402_16V7K U11
2 2 2 2 2 2 2 2 2 R150
1 8 510_0402_5%
A0 VCC
2 A1 WP 7 2 1
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 3 A2 SCL 6 1394SCL
4 GND SDA 5 1394SDA
AT24C02N-10SI-2.7_SO8
D D
+3VS
+3VS
CLK_33M_1394 +3VS
1
2
110
122
111
100
108
118
126
112
2
R102 R108
46
36
99
17
32
21
30
31
47
91
13
23
33
22
38
5
6
22_0402_5% U12 L12 2K_0402_5%
@ 0_0805_5%
PVD
PVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
<19,24,26,28> PCI_AD[0..31] @
PCI_AD0 25
2
1
PCI_AD1 AD0
1 24
1
PCI_AD2 AD1 XCPS
20 AD2
C102 PCI_AD3 19
15P_0402_50V8D PCI_AD4 AD3 0.1U_0402_10V6K
18 AD4 PVA 59
1
2
Power
@ PCI_AD5 16 62 1 1 1 1
PCI_AD6 AD5 PVA R113
15 AD6 PVA 72
PCI_AD7 14 73 C107 C119 C106 C116 1K_0402_5%
PCI_AD8 AD7 PVA 0.1U_0402_10V6K 0.1U_0402_10V6K
11 AD8 PVA 86
PCI_AD9 10 87 2 2 2 2
2
PCI_AD10 AD9 PVA
9 AD10
PCI_AD11 8
PCI_AD12 AD11 0.1U_0402_10V6K
7 AD12
PCI_AD13 4 61
C PCI_AD14 AD13 GND C
3 AD14 GND 65
PCI_AD15 2 66
PCI_AD16 AD15 GND
117 AD16 GND 79
PCI_AD17 116 80 +3VS
PCI_AD18 AD17 GND
115 AD18 GND 56
PCI_AD19 114
PCI_AD20 AD19
113 AD20 R723
IEEE 1394
PCI_AD21 109 @
PCI_AD22 AD21
107 26 1 2
AD22 EECS
PCI_AD23
PCI_AD24
106
103
AD23 EEPROM EEDO
27
28 1394SDA
PCI_AD25 102
AD24
AD25 I/F EEDI/SDA
EECK/SCL
29 1394SCL 4.7K_0402_5%
VT6301S
PCI_AD26 101
PCI Bus
PCI_AD27 AD26 54.9_0402_1% 270P_0402_50V7K
98
PCI_AD28 97
AD27
AD28
PM & Test R98
1 2 1 2
PCI_AD29 96 34 C101
AD29 PME# ICH_PME# <19,24,26,28,31,32>
PCI_AD30 95
PCI_AD31 AD30 XCPS 54.9_0402_1% 4.99K_0402_1%
94 60
AD31 XCPS R99 R89
1 2 C112 1 2 1 2
PCI_C_BE0# 12 63 1 2 47P_0402_25V8K J139A1
<19,24,26,28> PCI_C_BE0# PCI_C_BE1# CBE0# XREXT
1 R107 SUYIN_020204FR004S506ZL
<19,24,26,28> PCI_C_BE1# CBE1#
Differential Pairs
PCI_C_BE2# 119 67 6.34K_0603_1% TPB0- 1 1
<19,24,26,28> PCI_C_BE2# PCI_C_BE3# CBE2# TPB0M TPB0+
<19,24,26,28> PCI_C_BE3# 104 68 2 2
CBE3# TPB0P
GND1
GND2
GND3
GND4
69 TPA0- 3 3
PCI_AD16 R115 1 100_0402_5% 1394_IDSEL TPA0M TPA0+
2 105 70 4 4
PCI_FRAME# IDSEL TPA0P 54.9_0402_1%
<19,24,26,28> PCI_FRAME# 120 71
PCI_IRDY# FRAME# TPBIAS0 R94
121 1 2
5
6
7
8
<19,24,26,28> PCI_IRDY# IRDY#
PCI_TRDY# 123
<19,24,26,28> PCI_TRDY# PCI_DEVSEL# TRDY# 54.9_0402_1%
<19,24,26,28> PCI_DEVSEL# 124 1 2 0.33U_0603_10V7K
PCI_STOP# DEVSEL# R93
<19,24,26,28> PCI_STOP# 125
PCI_PERR# STOP#
<19,24,26,28> PCI_PERR# 127 1 2
PCI_PAR PERR#
<19,24,26,28> PCI_PAR 128
B PCI_REQ2# PAR B
<19> PCI_REQ2# 93 C98
REQ#
NC
PCI_GNT2# 92
<19> PCI_GNT2# GNT#
<19> PCI_PIRQE# 88
INTA#
<19,24,26,28,32> PCIRST# 89
90
PCIRST#
OSC PHYRESET#
55 2 1
CARDEN
<18> CLK_33M_1394 PCICLK C122
I2CEN 0.1U_0402_10V6K
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
XO
1394
XI
VT6301S-CD_LQFP128
41
42
45
48
49
50
37
51
52
53
54
40
39
35
74
75
76
77
78
64
81
82
83
84
85
43
44
57
58
24.576MHz_16P_3XG-24576-43E11 2 C118
1
Y2 10P_0402_50V8J
2
R118
+3VS 1M_0402_5%
2
R133
2
4.7K_0402_5% 1 2 C124
10P_0402_50V8J
1
A A

<Title>
5 4 3 2 1
5 4 3 2 1
+3VS +3VS
JMPCI1
1 1 2 2
KEY KEY
3 3 4 4
5 5 6 6
7 8
7 8
9 10
WLAN_ACT1 9 10 WLAN_ACT2
11 12
D HW_RADIO_DIS# 11 12 D
<32,33,35> HW_RADIO_DIS# 1 2 13 14
R801 0_0402_5% 13 14
15 16
PCI_PIRQH# 15 16
<19> PCI_PIRQH# 17 18 +5VS
17 18 PCI_PIRQG#
19 20 PCI_PIRQG# <19>
19 20 R780 0_0402_5%
21 22
21 22
23 24 +3V
CLK_33M_MPCI 23 24 PCIRST#
<18> CLK_33M_MPCI 25 26 PCIRST# <19,24,26,27,32>
25 26
27 28 2 2
PCI_REQ3# 27 28 PCI_GNT3# C286 C285
<19> PCI_REQ3# 29 30 PCI_GNT3# <19>
29 30 0.1U_0402_16V4Z 0.1U_0402_16V4Z
31 32
PCI_AD31 31 32 SYS_PME#
33 34 ICH_PME# <19,24,26,27,31,32>
PCI_AD29 33 34 1 1
35 36 R312 1 2 0_0402_5% COEX1_BT_ACTIVE <35>
35 36 PCI_AD30 R311
37 37 38 38
R320 PCI_AD27 39 40 10K_0402_5%
PCI_AD25 39 40 PCI_AD28
0_0402_5% 41 42 2 1
41 42 PCI_AD26
<35> COEX2_WLAN_ACTIVE 1 2 43 44
PCI_C_BE3# 43 44 PCI_AD24
<19,24,26,27> PCI_C_BE3# 45 45 46 46
PCI_AD23 47 48 MINIDSEL 1 2 PCI_AD18
47 48
49 49 50 50
PCI_AD21 51 52 PCI_AD22 R313
PCI_AD19 51 52 PCI_AD20 100_0402_5%
53 53 54 54
55 56 PCI_PAR
PCI_AD17 55 56 PCI_AD18 PCI_PAR <19,24,26,27>
57 57 58 58
PCI_C_BE2# 59 60 PCI_AD16
<19,24,26,27> PCI_C_BE2# PCI_IRDY# 59 60
<19,24,26,27> PCI_IRDY# 61 61 62 62
63 64 PCI_FRAME#
CLKRUN# 63 64 PCI_TRDY# PCI_FRAME# <19,24,26,27>
<21,24,26,31,32> CLKRUN# 65 65 66 66 PCI_TRDY# <19,24,26,27>
PCI_SERR# 67 68 PCI_STOP#
<19,24,26> PCI_SERR# 67 68 PCI_STOP# <19,24,26,27>
69 69 70 70
PCI_PERR# 71 72 PCI_DEVSEL#
<19,24,26,27> PCI_PERR# PCI_C_BE1# 71 72 PCI_DEVSEL# <19,24,26,27>
<19,24,26,27> PCI_C_BE1# 73 73 74 74
C 75 76 PCI_AD13 C
77 77 78 78
PCI_AD10 79 80
81 81 82 82
83 84 PCI_AD9
PCI_AD8 83 84 PCI_C_BE0#
85 85 86 86 PCI_C_BE0# <19,24,26,27>
PCI_AD7 87 88
87 88 PCI_AD6
89 89 90 90
91 92 PCI_AD2
93 94
95 96
95 96
97 98
+5VS PCI_AD1 97 98
99 100
99 100
101 102
101 102
103 104
103 104
105 106
105 106
107 108
107 108
109 110
109 110
111 112
111 112
113 114
113 114
115 116
115 116
117 118
117 118
119 120
119 120
121 122
121 122
123 124 +3V
+5VS 123 124
2 QTC_C102A-056B11-01
C607 2
0.1U_0402_16V4Z C291
1 0.1U_0402_16V4Z
1
B PCI_AD[0..31] <19,24,26,27> B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
CK_33M_MINPCI_TERM
CLK_33M_MPCI PCI_AD13
PCI_AD14
2
+3VS PCI_AD15
R319 PCI_AD16
@ 10_0402_5% PCI_AD17
PCI_AD18
2 2 2 2 2 2 2 2 PCI_AD19
1
C297 C298 C290 C299 C300 C289 C288 C287 PCI_AD20

PCI_AD21
2 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z PCI_AD22
1 1 1 1 1 1 1 1 PCI_AD23
C295 PCI_AD24
@4.7P_0402_50V8C PCI_AD25
1 PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
A PCI_AD31 A

<Title>
5 4 3 2 1
A B C D E
AC97 Codec
+5VS
U14 (+VDDA~=4.79V)
4 5 +VDDA
VIN VOUT +VDDA
1 1
1
C192 2 6 1
DELAY SENSE or ADJ R222
10U_0805_10V4Z 7 1 C219
2 2 ERROR CNOISE 150K_0603_1% 10U_0805_10V4Z
1 1
2
8 3 1
2
C210 SD GND
0.1U_0402_16V4Z SI9182DH-AD_MSOP8
1
2 R223
C209 51K_0603_1%
0.1U_0402_16V4Z
2
+AVDD_AC97
L18
+VDDA 1 2
0_0805_5%
+3VS
1 1 1 1
C574 C240 C271
C258
2 0.1U_0402_16V4Z 10U_0805_10V4Z 10U_0805_10V4Z 2
2 2 2 2
When Project need implement Headphone channel output from
0.1U_0402_16V4Z Audio Codec pin 39 & 41, it must have another driver to support JD
25
38
9
U16 function to change signal path from LINE_OUT_L & LINE_OUT_R to
2 1
HP_OUT_L & HP_OUT_R when headphone insert.
AVDD1
AVDD2
DVDD1
DVDD2
C276 1000P_0402_50V7K
2 1
C268 1000P_0402_50V7K
For ALC250 disable HW EQ when Headphone plug-in. 14 AUX_L LINE_OUT_L 35 LINEL 1 2 LEFT
LEFT <30>
C269 4.7U_0805_10V4Z
R228 15 36 LINER 1 2 RIGHT
AUX_R LINE_OUT_R RIGHT <30>
0_0402_5% C275 4.7U_0805_10V4Z 14.318MHz External Ra stuff, Rb, Cb, and Xb empty.
1 2 HP_SENSE 16 37 C577 1 2 1U_0805_25V4Z
<30> NBA_PLUG JD2 MONO_OUT/VREFOUT3 MD_MIC <35>
1 2 17 JD1 HP_OUT_L 39 24.576MHz Crystal Rb, Cb, and Xb stuff, Ra empty.
1 2 C233 @ 0.1U_0402_16V4Z
R639 6.8K_0402_5% C232 1
or External Colck
2 0.1U_0402_16V4Z 23 LINE_IN_L HP_OUT_R 41
1 2
R642 6.8K_0402_5% C231 1 2 0.1U_0402_16V4Z 24 LINE_IN_R R285 1
BIT_CLK 6 2 22_0402_5% IAC_BITCLK <20,35> 1 2 CLK_14M_COMPAL <38>
1 2 CD_L_R 1 2 18 R763
<23> INT_CD_L CD_L
R640 20K_0402_5% C569 1U_0603_10V4Z 8 R284 1 2 22_0402_5% 0_0402_5%
SDATA_IN IAC_SDATAI1 <20>
1 2 CD_R_R 1 2 20
<23> INT_CD_R CD_R
R641 20K_0402_5% C570 1U_0603_10V4Z 2 XTL_IN 1 2 CLK_14M_CODEC
XTL_IN CLK_14M_CODEC <18>
1
CD_GNA 1 2 19 R298
<23> CD_GNA CD_GND
C568 1U_0603_10V4Z R292 0_0402_5%
1 2 C236 <30> MIC
MIC 1 2 C_MIC 21 MIC1
@ 1M_0402_5% Rb Ra R297
0.01U_0402_16V7K C234 1U_0603_10V4Z @ 10_0402_5%
3 XTL_OUT 3
1 2 22 3
2
R229 2.4K_0402_5% MIC2 XTL_OUT
1
1 2 1 2 C_MD_SPK 13 29 2 1 C277
<35> MD_SPK PHONE AFILT1
R230 10K_0402_5% C235 1U_0603_10V4Z C259 1000P_0402_50V7K
12 30 2 1 @ 15P_0402_50V8J
<30> MONO_IN PC_BEEP AFILT2 2
C265 1000P_0402_50V7K
VREFOUT 28 +AUD_VREF
<20> IAC_RST# 11 RESET#
VREF 27
10 +AUD_VREF
<20> IAC_SYNC SYNC
DCVOL 32
<20> IAC_SDATO 5 SDATA_OUT 1 1
1
C241 C571
45 31 R643 1 1
NC NC
XTLSEL MODE 46 XTLSEL VREFOUT2 33
@ 0_0402_5% 2
0.1U_0402_16V4Z
2
4.7U_0805_10V4Z
C257
C573
VAUX 34
* LOW 14.318MHz External <30> EAPD 47 43 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2
SPDIFI/EAPD SCK 2 2
SDA 44
24.576MHz Crystal 48 SPDIFO
Floating or External Colck NC 40 If Project need to implement Realtek Power Off CD play function.
1
4 DVSS1 AVSS1 26 It must be supplied power for AVDD(Pin25 & 38) &
R633 R299 7 42 1 2
20K_0402_5% 0_0402_5% DVSS2 AVSS2 VAUX(Pin34) & power off for DVDD(Pin1 & 9). R164 0_0805_5%
1 2 CD_GNA When AVDD & VAUX powered and DVDD without power,
ALC250_LQFP48
it will bypass CD_L & CD_R to LINE_OUT_L & LINE_OUT_R.
2
1 2
1
POWER OFF R217 0_0805_5%

R632 R638 MODE SHUT DOWN CD Play NORMAL NORMAL
4
@ 0_0402_5% 6.8K_0402_5% 1 2 4
DVDD(1/9) 0 0 1 1 R694 0_0805_5%
2
VAUX(34) 0 1 0 1

<Title>
A B C D E
A B C D E
+5VAMP
1
R617
+5VS +5VAMP 100K_0402_5%
L16
1 2 W=40Mil
2
0_0805_5% SHUTDOWN#
1 1 C547 Q40
1
C548 D 2N7002_SOT23
4.7U_0805_10V4Z 2 EAPD <29>
0.1U_0402_16V4Z G
HIGH PIN 6,20 ACTIVE 2 2 S +5VAMP
1 1
3
Pin 2
LOW PIN 5,23 ACTIVE
2
JSPK1
R220 INTSPK_L1 1
INTSPK_L2 1
100K_0402_5% 2 2
U34 INTSPK_R1 3
INTSPK_R2 3
7 22 4
1
PVDD SHUTDOWN# NBA_PLUG 4
18 PVDD SE/BTL# 15
19 14 1 2 ACES_85205-0400
VDD PC-BEEP C549 0.1U_0402_16V4Z
11
22P_0402_25V8K
22P_0402_25V8K
22P_0402_25V8K
22P_0402_25V8K
NBA_PLUG BYPASS INTSPK_L2
<29> NBA_PLUG 2 HP/LINE# LOUT- 9
VOL_AMP 3 16 INTSPK_R2 1 1 1 1
VOLUME ROUT-
C162
C161
C160
C159
INTSPK_L1 C553 4 10
0.47U_0603_16V4Z INTSPK_R1 0.47U_0603_16V4Z LOUT+ LIN
21 ROUT+ RIN 8
LEFT C557 1 2LEFT_1 1 2 LEFT_2 5
<29> LEFT LLINEIN 2 2 2 2
RIGHT_2 23 1
RIGHT RLINEIN GND
<29> RIGHT 1 2RIGHT_1 1 2 6 LHPIN GND 12
C556 C552 20 13 2 2 2
0.47U_0603_16V4Z 0.47U_0603_16V4Z RHPIN GND C561 C559 C560
GND 24
+5VAMP C212 0.47U_0603_16V4Z 17
HP_L CLK 1U_0603_10V4Z
1 2 @ @ @ @
TPA0232PWP_TSSOP24 1 1 0.47U_0603_16V4Z
1
1
1 2 HP_R 1 0.47U_0603_16V4Z
R219 1
C213 0.47U_0603_16V4Z C546
1
10K_0402_5% C558 0.047U_0603_16V7K (0.47U~1U)
2
2
VOL_AMP R624 R623 2 0.1U_0402_16V4Z

2 (0.65V -> 10dB ) 1.3K_0603_5% 1.3K_0603_5% 2
1
2
R625
1.5K_0402_1%
AMP_1-1470184-2
fo=1/(2*3.14*R*C)=260Hz C555 CS
2
R=1.3K / C=0.47U 150U_D2_6.3VM

R218 NBA_PLUG CN
47_0402_5% L15
INTSPK_R1 1 2 INTSPK_R1-2 1 2 INTSPK_R1-3 1 2 INTSPK_R1-4 1
FBM-11-160808-700T_0603 3
+
INTSPK_L1 1 2 INTSPK_L1-2 1 2 INTSPK_L1-3 1 2 INTSPK_L1-4 4
R221 L17 5
+
C564 47_0402_5% FBM-11-160808-700T_0603 1 1
+3V +3V 150U_D2_6.3VM JHP1
C226 C211
+VDDA 330P_0402_50V7K 330P_0402_50V7K
1
2 2
R258 1 2
<32> BEEP#
1
+3V 100K_0402_5%
C554
0.1U_0402_16V4Z R231
14
14
2
1
U15A R232 U35A R635 10K_0402_5%

8.2K_0402_5% SN74LVC14APWLE_TSSOP14 560_0402_5%
OE#
P
2 I O 3 1 2 1 I O 2 1 2 1 2
1
G
1 C566
SN74LVC125APWLE_TSSOP14 C567 +3V POWER 1U_0603_10V4Z C224
7
0.22U_0603_10V7K R225 10U_0805_10V4Z

3 +3V POWER 2 3
2
2
10K_0402_5%
1 2 MONO_IN
MONO_IN <29>
R630 C239
1
560_0402_5% C 1U_0603_10V4Z
2
1 2 1 2 2 Q10
<26> CBS_SPK# B 2SC2411K_SC59 R226
C565 E 2.4K_0402_5%
3
1U_0603_10V4Z
1 2 +AUD_VREF
1
R644 0_0402_5%
+3V
1
AMP_1-1470184-2
R645 R671 CS
2.2K_0402_5% 2.2K_0402_5%
EXT.
14
CN
R628
2
560_0402_5% 1
P
<21> SPKR 3 I O 4 1 2 1 2 3
4
MICPHONE
G
+3V POWER C563 MIC

1U_0603_10V4Z
<29> MIC
L29
1 2 5 JACK
7
U35B FBM-11-160808-700T_0603 JMIC1

1
SN74LVC14APWLE_TSSOP14
R627 D19 C572
10K_0402_5% RB751V_SOD323 220P_0402_50V7K
2
2
4 4

<Title>
A B C D E
A B C D E
FIR Module (60mil)

+3VS
R138
CLK_PCI_SIO CLK_14M_SIO 4.7_1206_5%
1 2 +IR_ANODE
1
1
R403 R380 +3VS 1 2 (60mil)
10_0402_5% 10_0402_5% C337 R137
@ @ 1U_0603_10V4Z 4.7_1206_5%
2
2
2
1 1 1 R152 U10 1
47_1206_5% 1
C369 C343 IRED_A IRTXOUT
2 IRED_C TXD 3
@ 18P_0402_50V8K @ 10P_0402_25V8K IRRX 4 5 IRMODE
1
RXD SD/MODE
1
2 2 +IR_3VS 6 VCC MODE 7 1 2
1 1 (30mil) R381 8 GND
R154 0_0402_5%
10K_0402_5% Reserved
@
C144 IR_VISHAY_TFDU6101E-TR4_8P
C145 0.1U_0402_16V4Z PCB Footprint : TFDU6101E
2
LPC_LAD[0..3] 2 2
<20,32> LPC_LAD[0..3]
10U_0805_10V4Z
U27
LPC_LAD0 10 62 SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
LPC_LAD1 LAD0 RXD1
12 63
SERIAL I/F
LPC_LAD2 LAD1 TXD1 MODE: HIGH/LOW SPEED SELECT
13 LAD2 DSR1# 64
LPC_LAD3 14 1
LAD3 RTS1#
CTS1# 2
LPC_LFRAME# 15 3
<20,32> LPC_LFRAME# LFRAME# DTR1#
LPC_LDRQ1# 16 4
<20> LPC_LDRQ1# LDRQ# RI1#
LPC I/F
+3VS 5
PLTRST_SIO# DCD1#
<19> PLTRST_SIO# 17 PCI_RESET#
SIO_PD# 18 37 IRRX
LPCPD# IRRX2
R415 10K_0402_5% FIR IRTX2 38 IRTXOUT
PM_CLKRUN# 19 39 IRMODE
<21,24,26,28,32> CLKRUN# CLKRUN# IRMODE/IRRX3
CLK_PCI_SIO 20
<18> CLK_33M_LPCSIO PCI_CLK
SIRQ 21 41 INIT#
<21,26,32> SIRQ SER_IRQ INIT#
SIO_PME# 6 42 SLCTIN#
<19,24,26,27,28,32> ICH_PME# IO_PME# SLCTIN#
44 LPD0
2 CLK_14M_SIO PD0 LPD1 2
<18> CLK_14M_SIO 9 CLK14 PD1 46
CLOCK PD2 47 LPD2
+3VS +3VS 23 48 LPD3
GPIO40 PD3
PARALLEL I/F
24 49 LPD4
GPIO41 PD4 LPD5
25 GPIO42 PD5 50
1
27 51 LPD6
R398 R393 GPIO43 PD6 LPD7
GPIO
28 GPIO44 PD7 53
10K_0402_5% 10K_0402_5% 29 55 LPTSLCT
@ GPIO45 SLCT LPTPE
30 GPIO46 PE 56
31 57 LPTBUSY
2
GPIO47 BUSY LPTACK#

32 GPIO10 ACK# 58
SIO_GPIO11 33 59 LPTERR#
GPIO11/SYSOPT ERROR#
1
SIO_SMI# 34 60 LPTAFD#
R401 GPIO12/IO_SMI# ALF# LPTSTB#
35 GPIO13/IRQIN1 STROBE# 61
10K_0402_5% 36 +5V_PRN
GPIO14/IRQIN2
1
40 C331
GPIO23 1U_0603_10V4Z
2
8 7 +3VS D1
VSS VTR
22 VSS VCC 11 1 1 +5VS 2 1
R383 43 POWER 26
2
10K_0402_5% VSS VCC

52 VSS VCC 45 RB420D_SOT23
GPIO11 1= 4E 0=2E 54 R2
LPC47N217_STQFP64
VCC 2 2 Parallel Port R1
2.2K_0402_5%
C7
C326 33_0402_5% 220P_0402_25V8K
1U_0603_10V4Z LPTSTB# 1 2
INIT# 1 2 LPTINIT#
R323 33_0402_5% AFD#/3M# AFD#/3M# C6111 2 220P_0402_25V8K
R327 FOX_DZ11391-H7 FD0 C6121 2 220P_0402_25V8K
3 +5V_PRN +5V_PRN SLCTIN# LPTSLCTIN# 33_0402_5% LPTERR# C6131 3
1 2 1 2 220P_0402_25V8K
R324 33_0402_5% LPTAFD# 1 2 14 FD1 C6141 2 220P_0402_25V8K
LPTACK# AFD#/3M# FD0 2
LPTBUSY FD0 LPTERR# 15 27
LPTPE LPTERR# FD1 3 26
LPTSLCT FD1 LPTINIT# 16 LPTSLCT C6151 2 220P_0402_25V8K
FD2 4 LPTPE C6161 2 220P_0402_25V8K
RP1 LPTSLCTIN# 17 LPTBUSY C6171 2 220P_0402_25V8K
RP9 RP8 FD3 LPTACK# C6181 2 220P_0402_25V8K
10
10
5
9
8
7
6
9
8
7
6
LPD0 8 1 FD0 18
LPD1 7 2 FD1 FD4 6
LPD2 6 3 FD2 19
LPD3 5 4 FD3 FD5 7 LPTINIT# C6191 2 220P_0402_25V8K
RP7 20 FD2 C6201 2 220P_0402_25V8K
33_0804_8P4R_5% FD6 8 LPTSLCTIN# C6211 2 220P_0402_25V8K
LPD4 8 1 FD4 21 FD3 C6221 2 220P_0402_25V8K
LPD5 7 2 FD5 FD7 9
1
2
3
4
5
1
2
3
4
5
2.7K_1206_10P8R_5% 2.7K_1206_10P8R_5% LPD6 6 3 FD6 22

+5V_PRN +5V_PRN LPD7 5 4 FD7 LPTACK# 10
23 FD4 C6231 2 220P_0402_25V8K
FD7 FD3 33_0804_8P4R_5% LPTBUSY 11 FD5 C6241 2 220P_0402_25V8K
FD6 LPTSLCTIN# 24 FD6 C6251 2 220P_0402_25V8K
FD5 FD2 LPTPE 12 FD7 C6261 2 220P_0402_25V8K
FD4 LPTINIT# 25
LPTSLCT 13
JP1
4 4

<Title>
A B C D E
A B C D E
M/B_ID 1 2 C598 ECAGND +3VALW

+3VALW 0.01U_0402_16V7K
BATT_TEMP 1 2 C600 ECAGND
1
0.01U_0402_16V7K
1
BATT_OVP 1 2 C597 ECAGND R704 M/B Ver. 0.1 0.2
L31 +3VALW 0.01U_0402_16V7K 100K_0603_5%
0_0603_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K Voltage 0.0 0.4 0.8 1.2 1.6
2
1 1 1 1 1 M/B_ID
2
+EC_AVCC
L30 C604 C608 C596 C592 C606 1
1
1 2 ECAGND 1 2
C591 0_0603_5% 2 2 2 2 2 R705 C599 BORAD ID
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K +EC_AVCC 13K_0603_5%
2
1 1
2
+3VALW LPC_LAD[0..3]
<20,31> LPC_LAD[0..3]
0.1U_0402_16V4Z
105
127
141
11
26
37
75
1
U37 +3VALW
R720 GATEA20 1 71 BATT_TEMP
VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC
EC_AVCC / AVCC
KBRST# GA20/ GPIO00/GA20 BATTEMP/AD0/GPIO38 BATT_OVP BATT_TEMP <39>
47K_0402_5% 2 72
KBRST#/GPIO01/KBRST# BATT OVP/AD1/GPIO39 M/B_ID BATT_OVP <40> USER_BTN2#
R7531 20_0402_5% 3 73 R734 1 2 10K_0402_5%
LFRAME# <21,26,31> SIRQ LFRAME# SERIRQ ADP_I/AD2/GPIO3A M/B_ID USER_BTN1#
+3VS @ 1 2 5 74 R735 1 2 10K_0402_5%
2
<20,31> LPC_LFRAME# LPC_FRAME# / LFRAME# AD BID0/AD3/GPIO3B USER_BTN2# <33>

ECRST# R718 10K_0402_5% LPC_LAD3 6
LPC_LAD2 9 LPC AD3/LAD3 AD INtput or GPI
LPC_LAD1 10 LPC AD2/LAD2 Host
1 LPC AD1/LAD1 INTERFACE
LPC_LAD0 12
C610 LPC AD0/LAD0
<18> CLK_33M_LPCEC 14 CLK_PCI_EC/PCICLK DAC_BRIG/DA0/GPIO3D 76 DAC_BRIG <16>
0.1U_0402_16V4Z PCIRST# 15 PWR 78
2 <19,24,26,27,28> PCIRST# PCIRST# EN DFAN1/DA1/GPIO3D EN_FAN1 <34>
C609 1 2 1 2 ECRST# 42 79
ECRST# EC_SCI# EC RST#/ ECRST# IREF2/DA2 ICH_PWRGD IREF <40>
R719 33_0402_5% 24 80
<21> EC_SCI# PM_CLKRUN# EC SCI#/SCI#/GPIO0E EN DFAN2/DA3/ GPIO3F ICH_PWRGD <21>
15P_0402_50V8D @ 44 +3VALW
<21,24,26,28,31> CLKRUN# PM_CLKRUN#/ CLKRUN# DA output or GPO
@
Reserved for 87591L FAN/PWM
25 KBA1 1 2
<33> KSI[0..7] KSI0 INVT_PWM/GPIO0F/PWM1 INVT_PWM <16> KBA2
JP4 63 27 R700
1 2 10K_0402_5%
<33> KSO[0..15] KSI1 KSI0/GPIO30 BEEP#/GPIO10/PWM2 ICH_BATLOW# BEEP# <30> KBA3
1 64 30 R699
1 2@ 10K_0402_5%
1 EC_TINIT# +3VALW KSI2 KSI1/GPIO31 OUT BEEP/GPIO12/PWM3 ICH_BATLOW# <21> KBA5
2 65 31 R698
1 2@ 10K_0402_5%
2 EC_TCK KSI3 KSI2/GPI032 ACOFF/GPIO18/PWM4 ACOFF <40>
3 66 32 R697 @ 10K_0402_5%
3 EC_TDO KSI4 KSI3/GPIO33 FAN SPEED1/GPIO14/FANFB1 FAN1SPD <34>
4 4 67 KSI4/GPIO34 FAN SPEED2/GPIO15/FANFB2 33 BIA <10,16>
5 EC_TDI KSI5 68
5 EC_TMS KSI6 KSI5/GPI035
6 6 69 KSI6/GPIO36
7 KSI7 70 91 PSCLK1T
7 KSI7/GPIO37 PSCLK1
8 8 ECDEBUG key Matrix
PSDAT1 92 PSDAT1T For NS 87591L
9 SCROLLLOCK# KSO0 47 scan 93 PSCLK2
9 EN_WOL# KSO1 KSO0/GPIO20 PS2 interface PSCLK2 PSDAT2
10 10 48 KSO1/GPIO21 PSDAT2 94
2 KSO2 PSCLK3 2
49 KSO2/GPIO22 PSCLK3 95
E&T_96212-1011S KSO3 50 96 PSDAT3
KSO4 KSO3/GPIO23 PSDAT3
51 KSO4/GPIO24
@ KSO5 52 125 ADB0
KSO6 KSO5/GPIO25 ADB0/D0 ADB1
53 KSO6/GPIO26 ADB1/D1 126 R259
KSO7 54 128 ADB2
KSO8 KSO7/GPIO27 Data ADB2/D2 ADB3 MSEN#
55 KSO8/GPIO28 ADB3/ D3 130 1 2
KSO9 56 BUS 131 ADB4
KSO10 KSO9/GPIO29 ADB4/D4 ADB5
57 132
KSO11 KSO10/GPIO2A ADB5/D5 ADB6 100K_0402_5%
58 133
+5VS @ R730 PSCLK1T KSO12 KSO11/GPIO2B ADB6/D6 ADB7
<33> PSCLK1 1 2 0_0402_5% 59
KSO12/GPIO2C ADB7/D7
134
+5VALW @ R731 1 2 0_0402_5% PSDAT1T KSO13 60 111 KBA0 ADB[0..7]
<33> PSDAT1 KSO13/GPIO2D KBA0/A0 ADB[0..7] <33>
PSCLK2 KSO14 61 112 KBA1
PSCLK2 PSDAT2 KSO15 KSO14/GPIO2E KBA1/A1 KBA2 KBA[0..19]
PSDAT2 62 113 KBA[0..19] <33>
R732 PSCLK3 EC_TCK KSO15/GPIO2F KBA2/A2 KBA3
1 2 0_0402_5% 89
EC URXD/KSO16/GPIO48 KBA3/A3
114
1
R733 1 2 0_0402_5% PSDAT3 EC_TDO 90 115 KBA4

R793 R794 EC UTXD/KSO17/GPIO49 KBA4/A4 KBA5
116
0_0402_5% 0_0402_5% KBA5/A5 KBA6
117
SMB_EC_DA2 88 Address KBA6/A6 KBA7
<16,34> SMB_EC_DA2 118
@ SMB_EC_CK2 87 EC SMD2/ GPIO47/SDA2 BUS KBA7/A7 KBA8
119
2
<16,34> SMB_EC_CK2 SMB_EC_DA1 86 EC SMC2/GPIO46/SCL2 SM BUS KBA8/A8 KBA9

<33,38,39> SMB_EC_DA1 120
SMB_EC_CK1 85 EC SMD1/GPIO44/SDA1 KBA9/A9 KBA10
<33,38,39> SMB_EC_CK1 121
EC SMC1/GPIO44/SCL1 KBA10/A10
10K_0402_5% 2 1 @R795 PSCLK1T 10K_0402_5% 2 1R802HW_RADIO_DIS# HW_RADIO_DIS# <28,33,35> 122 KBA11
KBA11/A11
10K_0402_5% 2 1 @R796 PSDAT1T 1 2 HW_RADIO_LED# HW_RADIO_LED# <33> 123 KBA12
10K_0402_5% R797 PSCLK2 R803 0_0402_5% ECDEBUG KBA12/A12 KBA13
2 1 34 124
10K_0402_5% R798 PSDAT2 SCROLLLOCK# PCM_SPK#/EMAIL_LED#/ GPIO16 KBA13/A13 KBA14
2 1 <33> SCROLLLOCK# 35 110
SB_SPKR/PWR_SUSP_LED#/ GPIO17 KBA14/A14 KBA15 +3VALW
<33> PWR_LED# 38 109
PWRLED#/ GPIO19 KBA15/A15 KBA16
<33> NUMLOCK# 40 108
PSCLK3 NUMLED#/ GPIO1A KBA16/A16 KBA17 FSEL#
1 2 <33> CHARGE_LED# 99 107 1 2
R696 10K_0402_5% BATT CHGI LED#/ E51CS# KBA17/A17 KBA18 FRD# R300 10K_0402_5%
<33> BATT_LED# 101 106 1 2
PSDAT3 BATT LOW LED#/ E51MR0 KBA18/A18 KBA19 R302 10K_0402_5%
1 2 <33> CAPLOCK# 100 98
R695 10K_0402_5% CAPS LED#/ E51TMR1 KBA19/A19 EC_SMI#
<33> PAD_LOCK# 102 1 2
3 +3VS ARROW LED#/ E51 INT0 R707 10K_0402_5% 3
<37,42> SYSON 104 84 +VCCP_PWRGD <42>
SYSON/GPIO56/ E51 INT1 SELIO2#/ GPIO43
97 COMPAL_INT# <38>
SELIO#/ GPIO50
<21> RSMRST# 4 135 FRD# <33>
EC_RSMRST#/ GPIO02 FRD#/RD#
<16> BKOFF# 7 136 FWR# <33>
BKOFF#/GPIO03 FWR#/WR#
2
<21> SLP_S3# 8
PM SLP S3#/GPIO04 FSEL#/SELMEM#
144 FSEL# <33> For KB910
R714 R715 16
<21> LID_SWOUT# EC LID OUT#/GPIO06 PCIRST#
10K_0402_5% 10K_0402_5% 17 41 1 R711
2
<21> SLP_S5# EC_SMI# PM SLP S05#/ GPIO07 EC ON/ GPIO1B EC_ON <33>
18 43 100K_0402_5%
<21> EC_SMI# EC SMI#/GPIO08 AC IN/ GPIO1C ACIN <21,40,41>
19 29
1
EC SWI#/GPIO09 ECTHERM#/GPIO11 EC_THRM# <21>

GATEA20 20 36
<20> GATEA20 <33> LID_SW# LID SW#/ GPIO0A ONOFF/GPIO18 SLP_S4# ON/OFF <33>
<16,24,33,37,42> SUSP# 21 45 SLP_S4# <21>
SUSP#/GPIO0B PCMRST#/GPIO1E +3VALW
<21> PWRBTN_OUT# 22 46 USER_BTN1# <33>
PBTN_OUT#/GPIO0C WL OFF#/GPIO1F
<19,24,26,27,28,31> ICH_PME# 23
EC PME#/GPIO0D MSEN#
<20> KBRST# 81 MSEN# <17>
ALI/MH#/GPIO40
82 FSTCHG <40>
FSTCHG/GPIO41 EC_TINIT#
83 VR_ON <37,45> 1 2
VR ON/ GPIO42 THERMATRIP_VGA# R701 100K_0402_5%
137 THERMATRIP_VGA# <16>
CRY1 GPIO57/GPIO57
140 142 PROCHOT# <5>
XCLKO GPIO58/GPIO58
AGND
+5VALW CRY2 138 143
GND
GND
GND
GND
GND
GND
XCLKI GPIO59/GPIO59
KB910L A1_LQFP144
139
129
103
13
28
39
77
1
R709
R712 R710
4.7K_0402_5% 4.7K_0402_5%
R713 ECAGND
2
SMB_EC_DA1 Pin8, 22, 54, 82, 84, 89 and 172 is diffrence define with 87591
SMB_EC_CK1 R181, R191, R192 and R193 are reserved for KB910.
4.7K_0402_5% SMB_EC_DA2 R187 & R176 are reserced for 87591L
4.7K_0402_5% SMB_EC_CK2 BTDIS# signal is reservedfor BT modula,
4 CRY1 4
BTON# signal is reserved for MDC\BT module
1 2 CRY2
R706 20M_0402_5%
@
Y3
2 1 2 1
1 1 R708 0_0603_5% Security Classification Compal Secret Data
32.768KHZ_12.5PF_6HT3 2005/03/01 2006/03/01 Title
Issued Date Deciphered Date
C602 C601 <Title>
10P_0402_50V8J 10P_0402_50V8J
2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROPRIETARY NOTE Size Document Number Rev
Close to RTC pad DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomLA-2362 1
A B C D E
A B C D E
KSI[0..7] Killer switch

<32> KSI[0..7] KSO[0..15]
<32> KSO[0..15]
KeyBoard DS-1208_3P
SW2 1 2 LID_SW#
LID_SW# <32>
+3V
3 4
JP2 Power BTN
1
KSI1 1 25 KSI1 1 2 100P_0402_25V8K SW1
KSI7 1 25 KSI7 C164 C165 1 SPPB530600_4P +3VALW
2 26 2 100P_0402_25V8K
1
2 26
2
KSI6 3 27 KSI6 C166 1 2 100P_0402_25V8K @ R726 10K_0402_1%
KSO9 3 27 KSO9 C167 1
4 4 28 28 2 100P_0402_25V8K 1 2
1
KSI4 5 29 KSI4 1 2 100P_0402_25V8K
KSI5 5 29 KSI5 C168 C169 1 100P_0402_25V8K DAN217_SC59 R346
1 6 6 30 30 2 1
KSO0 7 31 KSO0 C170 1 2 100P_0402_25V8K D6 100K_0402_5%
KSI2 7 31 KSI2 C171 1
8 32 2 100P_0402_25V8K D14
1
KSI3 8 32 KSI3
9 33 1 2 100P_0402_25V8K +3V
2
KSO5 9 33 KSO5 C172 C173 1 100P_0402_25V8K ON/OFF
10 10 34 34 2 3 ON/OFF <32>
KSO1 11 35 KSO1 C174 1 2 100P_0402_25V8K ON/OFFBTN# 1
11 35
1
KSI0 12 36 KSI0 C175 1 2 100P_0402_25V8K 2
12 36 51ON# <44>
KSO2 13 37 KSO2 1 2 100P_0402_25V8K HW_RADIO_DIS#
13 37 HW_RADIO_DIS# <28,32,35> +3VALW
KSO4 14 38 KSO4 C176 C177 1 2 100P_0402_25V8K R306
KSO7 14 38 KSO7 C178 1 DAN202U_SC70
15 15 39 39 2 100P_0402_25V8K Q27
KSO8 16 40 KSO8 C179 1 2 100P_0402_25V8K
2
16 40
1
KSO6 17 41 KSO6 1 2 100P_0402_25V8K DTC124EK_SC59
1 D13
17 41
1
KSO3 18 42 KSO3 C180 C181 1 2 100P_0402_25V8K 100K_0402_5% R349
KSO12 18 42 KSO12 C182 1
19 19 43 43 2 100P_0402_25V8K 22K_0402_5%
KSO13 20 44 KSO13 C183 1 2 100P_0402_25V8K
KSO14 20 44 KSO14 2 C319
21 45 1 2 100P_0402_25V8K RLZ20A_LL34
2
KSO11 21 45 KSO11 C184 C185 1
22 22 46 46 2 100P_0402_25V8K <32> EC_ON
EC_ON 1 2 2 1000P_0402_50V7K
KSO10 23 47 KSO10 C186 1 2 100P_0402_25V8K R347
KSO15 23 47 KSO15 C187 1
24 24 48 48 2 100P_0402_25V8K 22K_0402_5%
ACES_85203-2402
3
+5VS
T/P +5VS
2 JTP1 2
1 7
2 8
3 9
4 10 +3VALW
<32> PSDAT1
<32> PSCLK1
5
6
11
12
PSDAT1 <32>
PSCLK1 <32> SW Board +3VALW
1
ACES_85203-0602 R301
JPSWP1 100K_0402_5%
SUSP# <16,24,32,37,42>
1 2 USER_BTN1# <32>
2
+5VALW +5VALW
G
3 4 USER_BTN2# <32>
5
ON/OFFBTN#
2
5 6 NUM_LED# 2 1 3
P
+3VALW 7 8 NUMLOCK# <32> I0 EC_FLASH# <21>
1
C284 SCROL_LED# FWE# 4
S
9 10 SCROLLLOCK# <32> O
1 2 0.1U_0402_16V4Z R309 +3VS 11 12
CAPS_LED#
CAPLOCK# <32> I1 1
G
Q15
13 14 HDD_ACT# <23>
100K_0402_5% 0_0402_5% U17 2N7002_SOT23
3
U19 15 16 R359 TC7SH32FU_SSOP5
1 2 CR_LED# <26>
2
17 18
8 VCC A0 1 19 20 PAD_LOCK# <32> FWR# <32>
7 WP A1 2
6 3 SUYIN_80065AR-020G2T
<32,38,39> SMB_EC_CK1 SCL A2
<32,38,39> SMB_EC_DA1 5 SDA GND 4
AT24C16N-10SI-2.7_SO8
1
R305
3
100K_0402_5%
LED Board 3
2
ADB[0..7]
ADB[0..7] <32>
KBA[0..19]
KBA[0..19] <32> +3VALW JLED1
1 1 9 9
2 2
U38 3
+5VALW <32> PWR_LED# 3
<32> CHARGE_LED# 4 4
KBA11 1 32 FRD# 5
A11 OE# FRD# <32> <32> BATT_LED# 5
KBA9 2 31 KBA10 6
KBA8 A9 A10 FSEL# HW_RADIO_LED# 6
3 A8 CE# 30 FSEL# <32> <32> HW_RADIO_LED# 7 7
+3VALW KBA13 4 29 ADB7 8 10
+3VBIOS KBA14 A13 DQ7 ADB6 8 10
5 A14 DQ6 28
C283 KBA17 6 27 ADB5
10U_1206_10V4Z FWE# A17 DQ5 ADB4 ACES_85205-0800
7 WE# DQ4 26
1 2 8 25 ADB3
R304 0_0603_5% KBA18 VCC DQ3
1 1 9 A18 VSS 24
KBA16 10 23 ADB2
KBA15 A16 DQ2 ADB1
11 A15 DQ1 22
KBA12 12 21 ADB0
C282 2 2 KBA7 A12 DQ0 KBA0
13 A7 A0 20
0.1U_0402_16V4Z KBA6 14 19 KBA1
KBA5 A6 A1 KBA2
15 A5 A2 18
KBA4 16 17 KBA3
A4 A3
4 4
SST39VF040-70-4C-WH_TSOP32

<Title>
A B C D E
5 4 3 2 1
D D
+3VS
1
C132
0.1U_0603_25V7M
1
2
R149
H_THERMDA 10K_0402_5%
<5> H_THERMDA U9
1
2 1
2
C141 D+ VDD1
H_THERMDC 2200P_0402_50V7K 3 6
<5> H_THERMDC 2 D- ALERT#
SMB_EC_CK2 8 4
<16,32> SMB_EC_CK2 SCLK THERM#
SMB_EC_DA2 7 5
<16,32> SMB_EC_DA2 SDATA GND
ADM1032ARM_RM8
1
R136 R140
8.2K_0402_5% 8.2K_0402_5%
C C
2
+3VS R799 0_0402_5% @
1 2
+3VALW R800 0_0402_5%

1 2
+5VALW +5VS
FAN1 Control and Tachometer
1
R807 R808
B 0_0603_5% 0_0603_5% B
+3V +3VS
@
2
C 1 +12VALW
1
R809 R163
B E 2 3 10K_0402_5% @ 10K_0402_5%
1
2
5
6
R622 U33A
100K_0402_5% D Q41
2
1 2 FAN1VREF 3 G
<32> EN_FAN1 +IN
2222 SYMBOL(SOT23-NEW) OUT
1 FAN1_ON 3 FAN1SPD <32>
1U_0603_10V4Z
FAN1_VFB 2 S SI3456DV-T1_TSOP6
-IN
1
1 1
4
G
C551
R810 C156
LM358A_SO8 0_0402_5%
4
+5VS @ 0.01U_0402_16V7K
2 2
2
FAN1SPDC <38>
C545
2200P_0402_50V7K
1 1 2 @ R812 0_0402_5%
1 2 FAN1_VOUTC <38>
C527 R590
0.1U_0402_16V4Z 100K_0402_5% JFAN1
2 2 1 FAN1_VOUT
D17 1
U32 1 2
1000P_0402_50V7K
SMB_EC_DA2 1 8 @ C537 1
<16,32> SMB_EC_DA2 SDA VCC 3
150K_0402_5%
SMB_EC_CK2 2 7
<16,32> SMB_EC_CK2 SCL A0
2
C155
3 6 ACES_85205-0300
OS# A1 2
4 5 1 2
GND A2 RB751V_SOD323 2
R616
R560 1K_0402_5%
2
LM75CIMMX-5_MSOP8 @ 22U_1206_16V4Z_V1 FAN1
1
A A
@

<Title>
5 4 3 2 1
5 4 3 2 1
+3VS
1
L32
0_0603_5%
2
D D
1
C605
0.1U_0402_16V4Z
BT_PWR
2
FM2 FM1 FM3 FM5 FM4 FM6
JBTP1 @ @ @ @ @ @
USB2+ 1
1
<21> USBP2+ 2
T24 USB2-
<21> USBP2- COEX3 3 CF3 CF9 CF1 CF7 CF4 CF10 CF11 CF2
@ PAD
COEX1_BT_ACTIVE 4 @ @ @ @ @ @ @ @
<28> COEX1_BT_ACTIVE
HW_RADIO_DIS# R8041 5 11
<28,32,33> HW_RADIO_DIS# 2 10K_0402_5% @
6 12
COEX2_WLAN_ACTIVE
1
<28> COEX2_WLAN_ACTIVE 7
8
BT_ACTIVE 9
10 CF8 CF6 CF5 CF13 CF12 CF16 CF15 CF14
JST_BM10B-SRSS-TB @ @ @ @ @ @ @ @
1
H10 H23 H22 H25 H24 H13 H4 H3 H2
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @ @ @
1
H7 H6 H5 H12 H11 H1
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
C C
0_0402_5%@ 2 1 R626
1
+5VS
0.1U_0402_16V4Z
C562 1 2
@
H8 H9 H16 H15
HOLEA HOLEA HOLEA HOLEA
JP3 ACES_88021-3001
1
<29> MD_MIC 1 2
MONO_OUT/PC_BEEP AUDIO_PWDN
3 4 MD_SPK <29>
GND MONO_PHONE H21 H17 H19 H18
5 6
AUXA_RIGHT Bluetooth Enable HOLEA HOLEA HOLEA HOLEA
7 8
AUXA_LEFT GND
9 10
CD_GND +5V @ @
11 12
CD_RIGHT USB Data+
13 14
1
CD_LEFT USB Data- Definition
15 16 1 2 +3V
GND PRIMARY DN R629 10K_0402_5%
17 18
+3V 3.3Vaux 5Vd
19 20
GND GND H20 H14 M1
21 22 1 2 IAC_SYNC_MDC <20>
3.3Vmain AC97_SYNC R631 0_0402_5% 1
<20> IAC_SDATO_MDC 23 24 2 @ IAC_SDATAI2 <20>
HOLEA HOLEA HOLEA
AC97_SDATA_OUT AC97_SDATA_IN1 22_0402_5% 1 R634 @ @ @
<20> IAC_RST#_MDC 25 26 2
AC97_RESET# AC97_SDATA_IN0 22_0402_5% R636
27 28 R637
GND GND
29 30 1 2
1
AC97_MSTRCLK AC97_BITCLK IAC_BITCLK <20,29>
22_0402_5%
GND1
GND2
GND3
GND4
GND5
GND6
MDC CONN.
31
32
33
34
35
36
B B
A A

<Title>
5 4 3 2 1
A B C D E
+USB_CS
+USB_CS
470P_0402_50V7K 470P_0402_50V7K
+5VS
1 1
1 1
U3 + C316 C317 +
1 8 C26 C25
GND OUT 150U_D2_6.3VM @ @ 150U_D2_6.3VM
2 IN OUT 7
2 2 2 2
1 3 IN OUT 6
C18 4 5 R754 1 2 0_0402_5%
EN# OC# OVCUR#3 <21>
1 1
1
0.1U_0402_16V4Z TPS2061IDGN_MSOP8 R755 1 2 0_0402_5%
2 OVCUR#4 <21>
R6 JUSBP1
100K_0402_5% 1 5
VCC VCC
<21> USBP4- 2 D0- D1- 6 USBP3- <21>
<21> USBP4+ 3 7 USBP3+ <21>
2
D0+ D1+
1 1 4 VSS VSS 8 1 1
3
C629 C630 10 9 C631 C632
10P_0402_25V8K 10P_0402_25V8K G2 G1 10P_0402_25V8K 10P_0402_25V8K
PSOT24C_SOT23 12 G4 G3 11 PSOT24C_SOT23
2 2 2 2
D23 SUYIN_020122MR008S540ZU D24
@ @ @ @
1
@ @
+USB_AS
470P_0402_50V7K
1
1
+ C528
C157
2 +USB_AS 150U_D2_6.3VM 2
+5VS 2 2
U13
1 GND OUT 8
2 7 JUSBP2
IN OUT
1 3 IN OUT 6 1 VCC
C154 4 5 2
EN# OC# OVCUR#0 <21> <21> USBP0- D-
<21> USBP0+ 3 D+
1
0.1U_0402_16V4Z TPS2061IDGN_MSOP8 1 1 4 GND
3
2 R158
100K_0402_5% C627 C628 5
10P_0402_25V8K 10P_0402_25V8K GND1
PSOT24C_SOT23 6 GND2
2 2
2
D25 SUYIN_2569AR-04G5T
@ @
1
@
+USB_BS
470P_0402_50V7K
1
1
+ C312
C24
150U_D2_6.3VM
3 2 2 3
+USB_BS
+5VS
JUSBP3
U26 1 VCC
1 GND OUT 8 <21> USBP1- 2 D-
2 IN OUT 7 <21> USBP1+ 3 D+
1 3 IN OUT 6 1 1 4 GND
3
C315 4 5
EN# OC# OVCUR#1 <21>
C633 C634 5 GND1
1
0.1U_0402_16V4Z TPS2061IDGN_MSOP8 10P_0402_25V8K 10P_0402_25V8K 6

2 R345 2 2 PSOT24C_SOT23 GND2
100K_0402_5% D26 SUYIN_020173MR004S512ZL
@ @
1
2
4 4

<Title>
A B C D E
5 4 3 2 1
+3VALW +3VS
+3VALW to +3VS Transfer
Q8
8 D S 1
7 2 +3VALW +CPU_CORE
C221 D S
6 D S 3
22U_1206_10V4Z 5 4 R224
D G C220 C225 470_0402_5%
AO4422_SO8 22U_1206_10V4Z 0.1U_0402_16V4Z R373
C222 C223 @ R371 330_0603_5%
D 22U_1206_10V4Z 10U_1206_10V4Z 100K_0402_5% @ D
Q9
1
D
RUNON 2 SUSP
1
2N7002_SOT23
G D
S 2 Q30
3
G 2N7002_SOT23
S @
3
1
D
VR_ON 2 Q31
<32,45> VR_ON
G 2N7002_SOT23
@
+3VALW to +3V Transfer S
3
+3VALW +3V
Q38
8 D S 1
7 D S 2
6 3 +5VALW
C494 D S R407 +12VALW
5 D G 4
10U_1206_10V4Z C449 C448 470_0402_5%
C495 AO4422_SO8 22U_1206_10V4Z 0.1U_0402_16V7K
1
10U_1206_10V4Z +12VALW
1
C496 R618
10U_1206_10V4Z R619 10K_0402_1%
1
D 47K_0402_5%
1
Q34
2 SYSON#
2
SUSON 2N7002_SOT23
G R620
2
C 47K_0402_5% SUSP C
S
3
SUSON <16,43,44> SUSP
1
D D
1
SYSON# 2 Q43 1 SUSP# 2 Q42
<16,24,32,33,42> SUSP#
G 2N7002_SOT23 G 2N7002_SOT23
1
D C550
S S
3
2 Q44 0.01U_0402_16V7K
+5VALW to +5VS Transfer <32,42> SYSON
G 2N7002_SOT23 R621 2
2
+5VALW S 1M_0402_5%
3
2
3
+5VS D18
SM05_SOT23
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_1206_10V4Z
C273 @ @ Q13
C274
10U_1206_10V4Z 1 1 8 1 @
D S C264
7 2
1
+12VALW D S
C712
C713
6 3 0.1U_0402_16V7K
D S R290
5 4 1
2 2 D G 470_0402_5%
1
AO4422_SO8 C272
R291 22U_1206_10V4Z
100K_0402_5% 2 +12VALW +12VALW
2
RUNON
1
1
R289 D Q11 2
1M_0402_5% 2 SUSP R452
1
D 2N7002_SOT23
G +5VALW C387 100K_0402_5% Q37
SUSP Q12 C260 Q35 +5V 0.1U_0402_16V4Z NDS352AP P-CHANNEL_SOT23
2 S
3
3
G 2N7002_SOT23 0.01U_0402_16V7K AO3400_SOT23 1 S
2
G
S 2
3
B B
S
1 3
D +12V
1
R453
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@ @ 1
C663 51K_0402_5%
1 1
G
2
C662 C390
C714
C715
10U_1206_10V4Z 0.1U_0402_16V4Z
10U_1206_10V4Z 2
1
1
2 2 D
SUSON 2 C406
G 4.7U_1206_16V6K
Q36 S 2
3
SUSON 2N7002_SOT23
+2.5V +2.5VS
+2.5V to +2.5VS Transfer
Q7
8 1
D S
7 2
D S
6 3
D S C151
5 4
D G C152 0.1U_0402_16V7K
AO4422_SO8 22U_1206_10V4Z
C158
10U_1206_10V4Z
RUNON
A C153 A
0.1U_0402_16V7K

<Title>
5 4 3 2 1
5 4 3 2 1
+5VS
VIN_FAN2
1
1
R764 C636 +5VS
100K_0402_5% 1U_0603_10V4Z LDO1_VOUT PAD VOUT_LDO1
D D
1
1
2
@
2
FAN2_GATE R765 C637
18
32
42
6
@ U39 10K_0402_1% 22U_1206_10V4Z
@ 2
AVCC1/5V
VCC2/5V
VCC2/5V
VCC2/5V
VIN_LDO1 PAD VIN_LDO1 1 4
2
LDO1_VINA LDO1_VOUTB LDO1_VOUT LDO1_FB @
48 3
LDO1_FB LDO1_VINB LDO1_VOUTA
@ 5
1
LDO1_FB @
2 R766
LDO1EN1 PAD LDO1_EN LDO1 10K_0402_1%
9
LDO1EN LDO2_VOUTB
LDO1EN2 PAD@ 12 10 LDO2_VOUT
LDVO2_VINA LDO2_VOUTA
13
2
LDO2_FB LDVO2_VINB
@ 8
LDO2_FB
+5VS 11 @
LDO2EN1 PAD LDO2_EN LDO2 29 PAD CP_OUT
VIN_FAN1 charge pump CP_OUT LDO2_VOUT
@ 26 28 PAD CP_EN1 PAD VOUT_LDO2
FAN1_VINA CP_EN
25 30 @ 1 1
FAN1_VINB CPP
1
1
1 2 1 C641 @ 22U_1206_10V4Z 24 @ @
C638 FAN1_VOUTA C639 R768 C640
<34> FAN1_VOUTC 23
R767 FAN1_VOUTB 1U_0603_10V4Z 10K_0402_1% 22U_1206_10V4Z
33
100K_0402_5% 1U_0603_10V4Z FAN1_GATE CPN 2 2
27
2 FAN1_GATE
<34> FAN1SPDC 46
2
2
FAN1_GATE FAN1_TACHFB/GPIO8 FAN @ LDO2_FB @
14
@ VIN_FAN2 GPIO0
35 15
1
@ FAN2_VINA GPIO1 @
36 16
FAN2_VINB GPIO2 R769
37 17
FAN2_VOUT1 PAD FAN2_OUTA GPIO3 10K_0402_1%
1 38 20
FAN2_OUTB GPIO4
@ 21
C642 FAN2_GATE GPIO5
34 22
2
22U_1206_10V4Z FAN2_GATE GPIO6
47
2 FAN2_TACHFB/GPIO9
44 COMPAL_INT# <32>
1
RESET# INT# @
45
@ RESET# R770
19
VSS2(GND) 4.7K_0402_5%
<29> CLK_14M_COMPAL 39 31
SCL CLK14M VSS2(GND)
<32,33,39> SMB_EC_CK1 40 43
SDA SCL VSS2(GND)
C 41 7 +5VS C
2
<32,33,39> SMB_EC_DA1 SDA VSS1/AGND
@
@
C643
+5VS
+5VS R771 1 2 RESET# 1 2
4.7K_0402_5%
+5VS R772 1 @ 2 SCL 1 1
4.7K_0402_5% 0.1U_0402_16V4Z C644 C645
+5VS R773 1 @ 2 SDA
4.7K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ 2 2
@
@ @
B B
A A

<Title>
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-2362 1
5 4 3 2 1
A B C D
1 1
BATT+
BATT++
FBM-L18-453215-900LMA90T_1812 VIN PL2
BATT+
PJPD1 P1 PL1 HCB4532K-800T90_1812
1 P1 1 2 1 2 BATT++
1
G 2 PR5
10_1206_5% PC7 PC8
560P_0402_50V7K
12P_0402_50V8J
12P_0402_50V8J
560P_0402_50V7K
G
3 0.01U_0402_25V7Z 1000P_0402_50V7K
2
1
1 2
PC1
PC2
PC3
PC4
SINGA_2DC-S756B200
1 2 BATT_TEMP
2
2
PD30 BATT_TEMP <32>
RLZ24B_LL34 PR15
PJP1 PR18 1K_0402_5%
2
BATT+ 1
2
PJPB1 battery connector ID 2
3
1K_0402_5%
2 1 2
B/I
SMART TS 4
5
Battery: 9
SMD
G SMC 6
1.BAT+ 8 G GND 7 1 2
+3VALWP
2.ID SUYIN_200275MR007G113ZL PR21
3.B/I
25.5K_0402_1%
4.TS
5.SMD 1 2 SMB_EC_DA1 <32,33,38>
6.SMC PR22
100_0402_5%
7.GND
1 2 SMB_EC_CK1 <32,33,38>
PR14 PR25
VL 2.2M_0402_5% 100_0402_5%
2 1
VS
B+
1
3 3
1
PR16
100K_0402_1% PR17
PU1A 499K_0402_1%
LM393M_SO8
2
20,41,44> MAINPWRON PD2

2
2 3
P
+
1 1 O
<40> ACON 3 - 2 PR10
G
1.5K_1206_5%
1
RB715F_SOT323 PR19 1 2
1000P_0402_50V7K
4
1
PR20 PC10
1000P_0402_50V7K
PC12
PC11 191K_0402_1% 499K_0402_1%

2
0.1U_0603_25V7K
2
PRG++ 2
PD1 PR11
VIN 1N4148_SOD80
2 1 VIN+
1.5K_1206_5%
1 2
B+
RHU002N06_SOT323
ACIN PQ1 47K_0402_5%
1
D PR24 PR12
Precharge detector VL 2 1
G
2 2 1 PACIN
PACIN <40>
1.5K_1206_5%
1 2
1
Min. typ. Max. PR23 S

3
34K_0402_1%
1
H-->L 14.589V 14.84V 15.243V PQ2

DTC115EUA_SC70
PR13
1.5K_1206_5%
L-->H 15.562V 15.97V 16.388V PR26
66.5K_0402_1%
2 +5VALWP 1 2
4 4
2
BATT ONLY
3
Precharge detector
Min. typ. Max.
Compal Electronics, Inc.
H-->L 6.138V 6.214V 6.359V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
L-->H 7.196V 7.349V 7.505V SECRET INFORMATION. THIS SHEET MAY NOT BE
CUSTODY OF THE COMPETENT DIVISION
TRANSFERRED FROMOFTHE
R&D DEPARTMENT EXCEPT AS
DCIN & DETECTOR & Precharge
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number Rev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY B LA-2362 1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC. Date: Friday, March 11, 2005 Sheet 39 of 52
A B C D
A B C D E
Charger
Iadp=0~3A(65W)
P2
PQ31 PQ32 B+ PL16 PQ33
AO4407_SO8 AO4407_SO8 P3 HCB4532K-800T90_1812 AO4407_SO8
PR157
VIN 8 1 1 8 2 1 1 2 1 8
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
7 2 2 7 2 7
6 3 3 6 4 3 3 6
220U_25V_M
5 5 1 5
1
PC14
1 1
0.01_2512_1%
PC138
PC139
PC140
0.1U_0603_25V7K
0.1U_0603_25V7K
+
4
1
47K_0402_5%
PC158
PC159
DTA144EUA_SC70
2
1
1
200K_0402_1%
PQ34 PR160
1
2
PR158
47K_0402_5%
2
PR159
0.1U_0603_25V7K
1 2
2
47K VIN
1
2
2
47K
2
PC141
PR161
2
1
@ 10K_0402_5% PD32
2
@ @ RLZ22B_LL34
2
<32> ACOFF
1
1
2 ACOFF#
2
1SS355_SOD323 PD24
1
@ 1SS355_SOD323
PD25
1
D PQ35
2 DTC115EUA_SC70 VIN 2 1 PU13
3
G PR162 MAX1908ETI_QFN28 10K
1
1
S 150K_0402_5% 1 DCIN PQ38 2 1 2
3
1
PC143 27 8 1
PC142 0.1U_0603_25V7K
PR163 CSSP G2 D2
7 2
2
1U_0603_10V6K 0_0402_5% D1/S2/K D2 10K PD26
6 3
2
2
D1/S2/K G1 1SS355_SOD323
2 1 17 5 4
3
PQ37 150K_0402_1% CELLS D1/S2/K S1/A
CSSN 26
RHU002N06_SOT323 PR164 PQ36
2 1 4 AO4912_SO8 DTC114EKA_SC59
REF BATT+
DHI 25 2 1
3 PR165
CLS PC18 0.015_2512_1%
1908LDO
23 1000P_0402_50V7K 1 2 1 2
LX
1
100K_0402_1%
RHU002N06_SOT323 2 1 2 1 12 REFIN
1
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
2 PL17 2
2
PR167
PQ39 PC144 PR166 PR184 21 16UH_D104C-919AS-160M_3.7A_20%

DLO
1
D 0.1U_0402_16V7K
9.31K_0402_1% 15K_0402_1%
2
1
2 15 PC145
2
1
VCTL
PC146
PC147
PC148
G 2 1 13 24 1 2 0.1U_0603_25V7K
PD28 ICTL BST
S
3
2
1
1
1SS355_SOD323 0_0402_5% 11 PR1 0_0402_5%
PC149 ACOK# PD27
8 22
ACOFF# PR168 0.01U_0402_16V7K SHDN# DLOV
1 2 2 1 10 1SS355_SOD323
2
ACIN
9 2 2 1
0_0402_5% ICHG LDO
2 1
2
<39> ACON ACON <32> IREF PR169 28
IINP
PR170
@ 0_0402_5% 7 1908LDO 33_1206_5%
CCV
19
CSIP
2
PGND
PR190 18
GND
CCS
CSIN
2
1908LDO
CCI
16 PC151
BATT 1U_0603_10V6K PC150
1
1K_0402_1%
1U_0805_25V4Z
14
20
1
2
1
PR174
PR172
MAX1908-CCS
1000P_0402_50V7K
PR171 10K_0402_5%
1000P_0402_50V7K
22K_0402_5%
1
1
1 2
2
<39> PACIN
2
PC152
PACIN PR173
PC153
100K_0402_1%
1
1
ACIN <21,32,41>
2
1
ACIN 1 2 PR175
2
1
PR4 @ 158K_0603_1% 2
10K_0402_5%
3 PD31 BATT+ 3
2
RLZ4.3B_LL34 PQ40 PC154

DTC115EUA_SC70 PR177 0.1U_0402_16V7K
2
0_0402_5%
1 2
<32> FSTCHG
BATT+
2
2
10K_0402_5%
PR193
Charge voltage
1
1
PR178
100K_0402_5%
2P4S:4300mAH/cell PC155 VS PR179
1
0.1U_0402_16V7K 845K_0603_1%
4S CC-CV MODE : 16.8V
2
0.7C=3.0A
0.01U_0402_25V7Z
1
VIN
2
1
PC156
1
PR180
OVP voltage : 150K_0402_1% PR181
2
300K_0603_0.1%
PU14A
2
LI-3S :17.8V----BATT-OVP=1.9758V LM358A_SO8
2
8
PACIN 1 2
3
P +
1
BATT-OVP=0.111*BATT+ PR194
681K_0603_1% PR182 <32> BATT_OVP
1
0
2
-
G
20K_0402_1%
1
4
+2.5V
1
2
PC157
VS 0.01U_0402_25V7Z
2
1
PR183
2
4 PR191 143K_0402_1% 4
PU14B 10K_0402_1%
LM358A_SO8
2
+ 5
+SDREF 7 0
1
- 6
PR192
10K_0402_1% Compal Electronics, Inc.
Title
Charger
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B LA-2362 1

A B C D E
A B C D E
+3.3V/+5V/+12V
+3VALWP Choke DCR = 26.5mΩ. 10U_1210_25V6M
PC160
B+
Current limit Threshold Min.=80 mV Mx.=120mV. 1 2
OCP Min.= 80mV/1.27K*(1.27K+1.27K)/26.6=6.038A
1
OCP Max.=120mV/1.27K*(1.27K+1.27K)/26.5=9.056A PD29
2
EC11FS2_SOD106
PC161
1 @470P_0805_100V7K 1
2
2
PL8
PC71
FBM-L18-453215-900LMA90T_1812 0.1U_0603_25V7K SNB 2 1 FLYBACK
1 2 BST31 BST51
1
PR186
2
@ 22_1206_5%
PL9
10uH_SDT-1205P-100-118_5A_20%
0.1U_0603_25V7K
PC72
3
B+++ 1 2
3
PQ17 PD14
1 8 DAP202U_SOT323
D2 G2
2 D2 D1/S2/K 7
3 6 B+++
G1 D1/S2/K
@ 2200P_0402_50V7K
4 5 +12VALWP
1
S1/A D1/S2/K VS VL PQ18
AO4912_SO8 8 1
G2 D2
7 D1/S2/K D2 2
1
6 D1/S2/K G1 3
2
PC73
PC74 PR89 5 4
D1/S2/K S1/A
@2200P_0402_50V7K
4.7U_1206_25V6K 0_0402_5%
2
4.7U_1206_25V6K
1
@ 2.7K_1206_5%
PD15 AO4912_SO8
1
1SS355_SOD323 PC75
1 1
PR187
PC76
PC77
4.7U_0805_6.3V6K
2
2
2 LX3 PR2 2
DH3
1
33_1206_5%
1
DL3 PR91 PC79
1
PC162 0_0402_5% 47P_0402_50V8J
2
1
PC81 D 4.7U_1206_25V6K
1
1
47P_0402_50V8J ACIN 2
2
1 2 PC78 G
0.1U_0603_25V7K S
3
PR92 PQ41
1
1
1M_0402_1%
1.27K_0402_1% @ RHU002N06_SOT323
2
PL10
22
21
10UH_D104C-919AS-100M_4.5A_20% PR93 PU6
PR94
1.27K_0402_1% 25 4
V+
VL
BST3 12OUT
1
0.47U_0603_16V7K 5
2
VDD BST5 PR95

27 18
2
PC82 DH3 BST5 DH5 2M_0402_1%

16
DH5 LX5
2 1 26 17
LX3 LX5 DL5
24 19
2
DL3 DL5
20
PR97 MAX1902EAI_SSOP28 PGND
14 2 1
619_0402_1% CSH5
1 13
CSH3 CSL5 PR96
1 2 2 12
CSL3 FB5 1.54K_0402_1%
+3VALWP 3 15
FB3 SEQ
1
<21,32,40> ACIN 1 2 10 9 2.5VREF
SKIP# REF
1
23 6 PR99
SHDN# SYNC
1
PR98 11 PC83
RST#
SKUL30-02AT_SMA
10K_0402_5% 7 698_0402_1%
2
TIME/ON5
3.57K_0402_1%
0.47U_0603_16V7K
2
2
1
PD17
PR100 28
GND
RUN/ON3
2
PR101
PC85 1 PC84 @ 300K_0402_5% PR102

2
1
1
100P_0402_50V8J 0_0402_5%
2
+
150U_D2_6.3VM_R45
PC86 PC87 +5VALWP

8
3 1000P_0402_50V7K 4.7U_0805_6.3V6K 3
1
2
1
2
2
1
10.2K_0402_1%
1
1
+
PC89
PR103
100P_0402_50V8J PD18 PC88
2
2
VS SKS10-04AT_TSMA 2 150U_D2_6.3VM_R45
2
10K_0402_1%
2
PR104
PR105
1
0_0402_5%
MAINPWRON <20,39,44>
2
1
PR106
1
10K_0402_1%
PC90
1
2.2U_0805_10V6K
2
2
PC91
@1U_0805_25V4Z
+5VALWP Choke DCR = 40mΩ.
2
Current limit Threshold Min.=80 mV Mx.=120mV.

OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A
4 OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A 4
RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3)
L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56)

Title
3.3V / 5V / 12V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2362 0.1
A B C D E
5 4 3 2 1
Vin=19V,Vo=2.5V,Io=4.5A,Fs=255KHZ,L=4.7UH
Mosfet Rds(on) tpy.=19.7mΩ Max=24mΩ,Delta I =1.8115A
Mosfet Rds(on) tpy.=19.7mΩ Max=24mΩ,Delta I =0.6118A
Iimit=ILIM(V)/10/Rds(on)+1/2 delta I
Iimit=ILIM(V)/10/Rds(on)+1/2 delta I
Iimit Min=1.98V*100K/(100K+33K)/10/31.2mΩ+0.905=5.6765A
Iimit Min=1.98V*100K/(100K+15K)/10/31.2mΩ+0.3059=5.824A
Iimit Max=2.02V*100K/(100K+33K)/10/19.7mΩ+0.905=8.614A
Iimit Max=2.02V*100K/(100K+15K)/10/19.7mΩ+0.3059=9.821A
D
+2.5VP = 5.6765A ~ 8.614A D
+VCCPP = 5.824A ~ 9.821A
MAX8743_B+
PL3
FBM-L18-453215-900LMA90T_1812
1 2 B+
2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_1206_25V6K
1
2
PC36
PC34
PC5 PC6
2
PC35
+5VALW @ 0.1U_0603_25V7K @ 1U_0805_50V4Z

2
1
C C
1
4.7U_0805_6.3V6K
1
0.1U_0603_25V7K
@
2200P_0402_50V7K
PC39
4.7U_1206_25V6K
4.7U_1206_25V6K
1
2
PD7
2
PC42
PC41
DAP202U_SOT323
PC40
PC43
PQ12
1 8
1
D2 G2
2 7
3
2
D2 D1/S2/K BST2.5B PQ13
3 6
G1 D1/S2/K @
4 5 8 1
S1/A D1/S2/K 1U_0805_25V4Z G2 D2
7 2
0.1U_0603_25V7K PC44 D1/S2/K D2
6 3
AO4912_SO8 PC38 PR53 D1/S2/K G1
1 2 5 4
20_0603_5% D1/S2/K S1/A
PR54 1 2
PL5 0_0402_5% AO4912_SO8 PL6
1
4.7UH_D104C-919AS_4R7N_5.2A_20% PR55 PC47 4.7UH_D104C-919AS_4R7N_5.2A_20%
+2.5VP
+VCCPP 0_0402_5% 0.1U_0603_25V7K
1 2 2 1 2 1 2 2 1 LX2.5 1 2
2
150U_D2_6.3VM_R45
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
PC46
22
1
150U_D2_6.3VM_R45
0.1U_0603_25V7K PU4 BST2.5A 1
1
PC50
+ 25 21
V+
UVP
VCC
BST1 VDD
1
PC51
PC49
PC48
+
26 19
2
2 DH1 BST2 DH2.5

18
2
DH2
1
27 17 2
LX1 LX2 DL2.5
24 20
B @ DL1 DL2 @ B
16
28 MAX8743EEI_QSOP28 CS2
PR61 CS1
1 15
2
499_0402_1% OUT1 OUT2

14
FB2
2 12
FB1 ON2
1
7
PGOOD
5
PR64 TON
2 1 11
10K_0402_1% <16,24,32,33,37> SUSP# ON1
13
PR68 ILIM2
3 1 2
SKIP
GND
OVP
REF
2
0_0402_5% ILIM1 SYSON <32,37>

1
PR67
PC54 PR58 0_0402_5%
8
23
10
@ 0.01U_0402_25V8K 33K_0402_1%
2
2 1
PR59
2 1 +3VALWP
100K_0402_1%
1
100K_0402_1%
15K_0402_1%
1
PR65
PR66
2
PC45
0.22U_0603_10V7K PR69
2
10K_0402_5%
2
1
+VCCP_PWRGD <32>
PD3
RB751V_SOD323
A A
SUSP# 1 2
1
PC17
@ 1000P_0402_50V7K
2
COMPAL ELECTRONICS, INC

Title
+2.5VP & +VCCPP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2362 1
5 4 3 2 1
5 4 3 2 1
D D
PJP2 PJP3 +2.5VP

3MM 2MM PU9
1 2 1 2 1 VIN VCNTL 6 +3VALW
+5VALWP +5VALW +12VALWP +12VALW
1
2 GND NC 5
1
PC92
C PC93 PR107 1U_0603_16V6K C
3 7
2
10U_1206_6.3V7K 1K_0402_1% VREF NC
2
PJP4 PJP7
4 VOUT NC 8
3MM 3MM
2
1 2 1 2 TP 9
+3VALWP +3VALW +VCCPP +VCCP
APL5331KAC-TR_SO8
1
PJP6
PC97
3MM 0.1U_0603_25V7K
2
1 2
+2.5VP +2.5V PR108
2
1K_0402_1%
PJP8
3MM
1
+1.25VS D
+1.25VSP 1 2
1 2 2 PQ20
<16,37,44> SUSP G RHU002N06_SOT323
S
3
PR109
PJP10
0_0402_5%
3MM
+1.25VSP
1 2 1
+1.5VSP +1.5VS
1
+
PC98 PC99
@
150U_D2_6.3VM 4.7U_0805_6.3V6K
2
2
B B
A A

Title
+1.25VSP
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2362
1
5 4 3 2 1
A B C D
Ipeak=Iocset*Rocset/RDS(ON)high side
PH2 under CPU botten side :
Iocset=40uA, Pocset=4.12K RDS(on)=25.5mΩ
CPU thermal protection at 80 degree C
Ipeak min=40uA*4.12/(25.5*1.3)=4.97A
Recovery at 44(45) degree C
Ipeak max=40uA*4.12/25.5=6.46A
1 PR72 1
47K_0402_1%
VL 1 2 VL
2
VS
1 PR71
47K_0402_1% +5VALW
1
PR74
1
2.15K_0402_1% PC55
PR73 0.1U_0603_25V7K
2
2
16.9K_0402_1%
8
PU1B
1 2 5
P
+
7 MAINPWRON <20,39,41>
TM_REF1 O
6 -
G
LM393M_SO8
1
PC58
PC60 4.7U_0805_6.3V6K
1U_0805_16V7K
2
10KB_0603_1%_TH11-3H103FT
PC57 0.1U_0402_16V7K
1
2 1
1
PC56
1000P_0402_50V7K
1
2 1 PR78
VL
2
2
PH1
2.2_0402_5%
1
PR75 PR77
2
150K_0402_1% PC59 4.12K_0402_1% PQ15
2
2
2 470P_0402_50V7K PD12 8 1 2
2
G1 D1
1
1SS355_SOD323 7 2
PR76 S1/D2 D1
6 3
2
150K_0402_1% S1/D2 G2
5 S1/D2 S2 4
1
5
PU8 SI4814DY_SO8
2
VCC
BOOT 1
1
7 OCSET PC61
0.1U_0402_16V7K
2
PR189 2
VIN 0_0402_5% UGATE PL7
1
D 4.7UH_D104C-919AS_4R7N_5.2A_20%
6
2 1 2
FB +1.5VSP
<16,37,43> SUSP G 8 1 2
PHASE
2
3
PD9 PQ42
1N4148_SOD80 RHU002N06_SOT323 1
4.7U_0805_6.3V6K
1
3 GND LGATE 4
1
PD10 PR82 + PC62
1 1
2 1 8.87K_0603_1% 150U_D2_6.3VM_R45
BATT+
1
APW7057KC-TR_SOP8
2
2
PC64
RB751V_SOD323 PR79 PC66
2
TP0610K_SOT23 33_1206_5%
2
PQ16 0.1U_0402_16V7K
@
2
3 2 1 3 1 VS
3
1
PR80
1
200_0805_5% PR84
PC63 10K_0402_1%
2
0.1U_0603_25V7K
2
2
1
PR81
2
100K_0402_5% PC65
0.22U_1206_25V7K
1
<33> 51ON# 1 2
PR83
22K_0402_5%
RTCVREF
PU7
4 G920AT24U_SOT89 4
CHGRTCP 2 3 1 2 1 2 CHGRTC
IN OUT
PR85 PR86
GND 300_0402_5% 300_0402_5%
1
PC67 1 PC68 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
1U_0805_25V4Z 4.7U_0805_6.3V6K OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
2
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE

CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
RTC Battery & OTP & +1.5VP
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number Rev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY B LA-2362 1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC. Date: Friday, March 11, 2005 Sheet 44 of 52
A B C D
5 4 3 2 1
B+
CPU_B+
+5VS
FBM-L18-453215-900LMA90T_1812
PL13
PR121 10_0402_5%
+3V
1 2
PD20
4.7U_1206_25V6K
4.7U_1206_25V6K
0.1U_0603_25V7K
0.01U_0402_25V7Z
1
EP10QY03
68U_25V_M
1U_0805_50V4Z
1
2
PC118
+
PC9
PC13
PC117
33K_0402_5%
2200P_0402_50V7K
PC114
PC115
PC116
2 1
1
D D
2
1
2 @
PR122
PC120 @ @
5
6
7
8
2.2U_0603_6.3V6K
PQ23
2
AO4408_SO8
1
PC121 PU12
1U_0603_16V6K PC122
1
0.01U_0402_25V7Z 4
2
VCC 10 30 PC123
PR123 0_0402_5% VCC VDD 0.22U_0603_16V7K
2
<6> VID0 2 1 24 D0 V+ 36
PR124 0_0402_5%
3
2
1
<6> VID1 2 1 23 D1 BSTM 26 1 2
PR126 0_0402_5% PR6 0_0402_5% PL14 +CPU_CORE
2 1 22 28 PR125 2_0402_5% 2 1 PR3 0.56UH_ETQP4LR56WFC_21A_20%
<6> VID2 PR128 0_0402_5% D2 DHM 4.7K_1206_5% PR129
<6> VID3 2 1 21 D3 LXM 27 1 2 1 2
5
6
7
8
PR130 0_0402_5%
2 1 20 29 PQ24 0.001_2512_5%
<6> VID4 D4 DLM
2
PR131 0_0402_5%
909_0402_1%
@100K_0402_1%
AO4410_SO8
1
2 1 19 31 CPU VCC SENSE
<6> VID5 D5 PGND
1
PR133 0_0402_5%
EC31QS04
1 2 25 VROK CMP 37 4
<8,18,21> VGATE
PD21
499_0402_1%
499_0402_1%
680P_0603_50V7K
1 1
1
4 38 PC124
2
PR138 S0 CMN
2
PC15
0_0402_5% PR139 VCC OAIN+
PR134
5 17 1 2
1000P_0402_50V7K
3
2
1
S1 OAIN+
2
@ 100K_0402_5% @
PR132
C C
2
OAIN-
3K_0603_1%
1 2 6 16
2
PR140 30.1K_0402_1% SHDN# OAIN- 0.47U_0603_16V7K
PR137
1
FB
PR135
PR136
PC125
VR_ON <32,37> 1 2 2 1 1 15
1
TIME FB
1 2 PC126 12 CCV CCI 14 1 2 PC127 PR141 909_0402_1%
270P_0402_50V7K 470P_0402_50V7K 1 2
1 2 2 35 @
TON BSTS
PR144 PR142 1 2 PC128 8 33
78.7K_0603_1% 470K_0402_5% 0.22U_0603_16V7K REF DHS
1 2
1 2 9 34 PR143
ILIM LXS 3K_0603_1%
+5VS
FB 1 2 7 32 1 2 1 2
OFS DLS
PR145 100K_0402_1% 3 40 PC129 PR146
10.7K_0402_1%
SUS CSP
2
1 2 0.022U_0402_16V7K 0_0402_5%
PC130
PR147
18 SKIP CSN 39
100P_0402_50V8J
2
1
2
D PD22 CPU_B+
2_0402_5%
11 GND GNDS 13
1
D EP10QY03
PR148
2
RHU002N06_SOT323
1
G 2
<18,21> H_STP_CPU#
S G
3
PQ25 S MAX1532AETL_TQFN40
2200P_0402_50V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
0.01U_0402_25V7Z
3
2
PQ26
RHU002N06_SOT323 PC131 <BOM Structure>
5
6
7
8
1
27P_0402_50V8J PQ27 PR150
PR149 AO4408_SO8
PC132
PC135
100K_0402_1%
0_0402_5%
PC133
PC134
@
2
<21> PM_DPRSLPVR 1 2
1
1
B PR7 0_0402_5% B
PC136 2 1 4
1 2 0.22U_0603_16V7K
+5VS
2
PR151
2
20K_0402_1% PL15
3
2
1
2
PR153 OAIN+ 2 1 0.56UH_ETQP4LR56WFC_21A_20%

PR154 10K_0402_1% 1 2
100K_0402_1% PC19
1000P_0402_50V7K PQ28
1 1
5
6
7
8
AO4410_SO8
4.7K_1206_5%
1
1
PQ29 D
909_0402_1%
2
OAIN+
PR155
EC31QS04
2 2 1
PR8
G RHU002N06_SOT323
PD23
S PC20
3
1
C 1000P_0402_50V7K 4
2
<6> PSI# 2
1
B @ 1 2
E PQ30
3
HMBT2222A_SOT23 PC137
3
2
1
1
0.47U_0603_16V7K
PC16
680P_0603_50V7K
2
Current sense tpy.=1mΩ Max=1.1mΩ,Delta I =8.12A 1 2
A A
Iimit=ILIM(V)/20/DCR+1/2 delta I PR156
Iimit Min={1.99V*78.7K/(78.7K+470K)/20/1.01mΩ+4.22A}*2=36.69A 909_0402_1%
Iimit Max={2.01V*78.7K/(78.7K+470K)/20/0.99mΩ+4.22A}*2=37.56A
Title
+CPU_CORE
B
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2
D
Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase D
ICH_PME# pull up +3VALW add R 10K

1
0.2 DVT
LID_SW# pull up +3VALW add R 10K

0.2 DVT
2
3 SB +1.5V regulator footprint error 0.2 DVT
4 SB +1.5V regulator footprint error U8 need to reverse

0.2 DVT
5 R76 take off

0.2 DVT
6 PR191 power plane 2.5vref change to +2.5V

0.2 DVT
7 R398 remove to R401

0.2 DVT
C C
8 H_DPRSLP# add pull up to +vccp power plane POP R546

0.2 DVT
9 POP U9 for lose and foot print error

0.2 DVT
10 U3 pin6 & pin 7 need to swap

0.2 DVT
11 Add R476/7 40.2 Ohm for memory

0.2 DVT
12 R259 short
0.2 DVT
13 PR122 chang power plane to +3V for EC voltage leakage

0.2 DVT
14 Add R224/R290/R407 470ohm and Q34/9/11 2N7002

0.1 DVT-2
15 ADD R 39K//220p to GND at R518 for modify SIRQ

0.1 DVT-2
B B
16 Reverse the JHP1 & JMIC1 Symble error

0.1 DVT-2
17 Modify NB FSB speed select for Dothan

0.1 DVT-2
18 Modify ACIN for SB

0.1 DVT-2
19 CardReader pin swap for flash memory

0.1 DVT-2
20 Reverse the JHP1 & JMIC1 Symbl

0.1 DVT-2
21 Add VCCP noise cap. at CPU C664/5/6/7/8/9 C670/1/2

0.2 DVT-3
22 Change R362/3 2.2K to 10K for Panel select

0.2 DVT-3
A A

Title
PIR
1
5 4 3 2 1
5 4 3 2 1
Item Fixed Issue Reason for change Rev. PG# Modify List B.Ver# Phase
Add C674/5/6/7/8 C680/1/2/3/4/5 C686/7/8/9
D D
C690/1/2/3/4/5/6/7/8/9 C702/3 for NB VCCP

23
0.2 DVT-3
noise cap.
ADD C646/7/8/9 C650/1/2/3/4/5 for DDR RAM
24
0.2 DVT-3
1.25V noise cap
25 ADD C704/5 for JVGAP1 2.5V for noise 0.2 DVT-3
26 Change R17/8/9 from 75 to 150 OHM for TV-out signal

0.2 DVT-3
27 ADD R774/5 for cost down U29 parts

0.2 DVT-3
Change SB(U5) sus power from V plane to Always power plane and
28
0.2 DVT-3
R457 R69 R456 R455 R456 R451 U7.T2 +1.5VR
29 R154 remove for FIR function

0.2 DVT-3
C C
ADD C656/7 C659/8 for +5VS HDD CDROM power

30
0.2 DVT-3
noise
31 U9 replace the new package to RM8 and remove to TOP
0.2 DVT-3
32 ADD C706/7/8/9/10/11 for SB 1.5Vrun noise

0.2 DVT-3
33 R129 change to +5VALW

0.2 DVT-3
34 Q3 cahnge to AO3400 for current rating not enough

0.2 DVT-3
35 JMPCI1 P.24 change to +3V for wireless power

0.2 DVT-3
36 Remove KB910 & 39VF080 ROM

0.2 DVT-3
37 R705 change to 13K for MB ID

0.2 DVT-3
B B
Change the Killer switch circuit for EC detect method

38
0.2 DVT-3
then light on the LED
39 Move U32 to near NB
0.2 DVT-3
40 ADD 5VALW noise cap. C714/5/2/3,

0.2 DVT-3
41
42
43
44
A A

Title
PIR
1
5 4 3 2 1
A B C D E
1 1.Delete the PU5 IC LM393M (SM). 1
1 0.2 38 2.Delete PD1 S DIO 1N4148 (SM). 0.2 DVT

Delete the charge circuit. Delete the charge circuit.
3.Delete PR10,PR11,PR12,PR13 S RES 1/4W 1.5K +-5% 1206.
1.Delete PQ14 S TR DTC115EUA NPN (UMT3).

2..Delete PD8 S DIO 1SS355.
3.Change PR75 and PR76 from S RES 1/16W 100K +-1% 0402 to
S RES 1/16W 150K +-1% 0402.
Change the CPU OTP circuit from active H Change the CPU OTP circuit from active H
2 4.Change PR73 from S RES 1/16W 15K +-1% 0402 to S RES 0.2 DVT
to active L. to active L. 0.2 43
1/16W 16.9K +-1% 0402.
5.Change PC56 from S CER CAP .22U 16V K X7R 0603 to
S CER CAP 1U 16V K X7R 0805
6.Change PR74 from S RES 1/16W 3.4K +-1% 0402 to S
S RES 1/16W 2.15K +-1% 0402.
3 For cost down solution. To cost down for +1.5VP. 0.2 43 1.Change the PD12 from DIO 1N4148 (SM) to DIO 1SS355. 0.2 DVT
2 2
4 For cost down solution. To cost down for RTC charge circuit.. 0.2 43 1.Delete the PD33 S ZEN DIO RLZ4.3B (LL-34). 0.2 DVT
1.Change the PD17 from SCH DIO SKS10-04AT TSMA to

5 To prevent the KB-910 damag. To prevent the KB-910 damag. 0.2 40 0.2 DVT
SCH DIO SKUL30-02AT THIN SMA.
6 For cost down solution. To cost down for +1.5VP for +12VALWP circuit. 0.2 40 1.Delete PR187 S RES 1/8W 2.7K +-5% 1206 S7. 0.2 DVT
7 For cost down solution. To cost down for DDR 2.5V. 0.2 41 1.Delete PR62 S RES 1/16W 0 +-5% 0402. 0.2 DVT
8 For cost down solution. To cost down for CPU_CORE. 0.2 44 1.Delete PR127 and PR152 S RES 1/16W 0 +-5% 0402. 0.2 DVT
3
1.Deete PR127 and PR152 S RES 1/16W 0 +-5% 0402. 3
9 For cost down solution. To cost down for snubber circuit. 0.2 40 0.2 DVT
2.Delete the PC161 S CER CAP 470P 100V K X7R 0805.
39
0.2 1.Delete PC41,PC158 and PC159 S CER CAP .1U 25V K X7R 0603. 0.2 DVT
10 For cost down solution. To cost down for EMI capacitor. 40
2.Delete PC40,PC73 and PC76 CER CAP 2200P 50V K X7R 0402.
41
10 Don't has pull high resister on VGATE pin. Add pull high resister on VGATE pin. 0.2 44 1.Add the S RES 1/16W 100K +-5% 0402. 0.2 DVT
1.Change the PR60 from S RES 1/16W 681 +-1% 0402 to

VCCPP output voltage has error. Adjustment resistor divider. 0.2 41 0.2
10 S RES 1/16W 1.69K +-1% 0603. DVT
1.Change PL7 from 4.7UH_FDV0630-4.7UH_5.5A_20%

11. Choke Rating not enough for +1.5VP. Choke Rating not enough for +1.5VP. 0.2 43 0.2 DVT
4 to 4.7UH_D104C-919AS_4R7N_5.2A_20%. 4

Title
PIR
A B C D E
A B C D E
1 1
Don't has pull down resister on SHDN#
1 Add pull down resister on SHDN# pin. 0.2 39 1.Add PR193 the S RES 1/16W 100K +-5% 0402. 0.2 DVT
pin for charger.
1.Add the PQ40 S TR DTC115EUA NPN (UMT3).

2.Delete the PR3,PR4,PR8 and PR9 RES 1/16W 10K +-1% 0402.
3.Add the PR193,PR172 and PR173 RES 1/16W 100K +-5% 0402.
4.Delete PR6 the S RES 1/16W 22K +-1% 0402.
5.Delete PR1 the S RES 1/16W 1M +-1% 0402.
Change the Vin Detector from LM393 to Change the Vin Detector from LM393 to 6.Change PR182 from S RES 1/16W 150K +-1% 0402 to S
2
charger ACOK#. charger ACOK#. 0.2 38,39 S RES 1/16W 20K +-1% 0402. 0.2 DVT
7.Delete the PR7 S RES 1/16W 20K +-1% 0402.
8.Delete the PR2 S RES 1/16W 84.5K +-1% 0402.
9.Add the PR175 S RES 1/16W 158K +-1% 0402.
10.Add the PR175 S RES 1/16W 681K +-1% 0402.
2 11.Delete PC6 from S CER CAP .1U 25V K X7R 0603. 2
12..Delete PC5 from S CER CAP 1000P 50V +-10% X7R 0402.
3 For ACIN pin, ACIN pin don't have connect to system. 0.2 39 1.Add PR4 the 10K +-5% 0402 0.2 DVT
1.Change PU10 from S IC G965-18P1U SOP-8L REG to S IC

APW7057KC-TR SOP-8 PWM.
2.Add PR197 S RES 1/16W 12.7K +-1% 0402.
3.Add the PQ44 S TR RHU002N06 1N SOT323
4.Delete PQ43 the S TR AO4912 2N SO8 W/D
5.Add PD33 the S DIO 1SS355.
6.Add PR195 the S RES 1/16W 2.2 +-5% 0402
0.2 42 7.Add PR198 the S RES 1/16W 10K +-1% 0402. 0.2 DVT
4 +1.8VSP power rating not enough. +1.8VSP power rating isnot enough.
3
8.Add PR196 the S RES 1/16W 4.12K +-1% 0402 3
9.Add the PC167 the S CER CAP 4.7U 10V Z Y5V 0805.
10.Add the PC164 S CER CAP 470P 50V +-10% X7R 0402.
11.Add the PC163,PC165 and PC168 S CER CAP .1U 16V +-10%
X7R 0402
12.Delete PC96 the S CER CAP 10U 6.3V K X7R 1206.
13.Add the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR.
14.Add PL18 the S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A.
1.Change PC50 from S POLY CAP 150U 6.3V M V(D2) T520 LESR
to S POLY C 220U 4V M V(D2) T520 LESR.
5 VCCP's transients cannot meet spec. 0.2 41
VCCP's transients cannot meet spec. 2.Change PL6 from S COIL 4.7UH +-20% D104C-919AS-4R7M 5.2A 0.2 DVT
to S COIL 1.8UH +-30% D104C-919AS-1R8N 9.5A.
1.Change the PR125 and PR148 from S RES 1/16W 0 +-5% 0402S
6 For CPU_CORE's EMI, For CPU_CORE's EMI, 0.2 44 to RES 1/16W 2 +-5% 0402. 0.2 DVT
4 4

Title
PIR
A B C D E
A B C D E
1 1.Delete PC124 and PC137 the S CER CAP 0.47U 16V +-10% X7R 1
0603.
1. CPU's transients cannot meet spec. Add one current sense on phase 2. 0.2 44 2.Delete PR134,PR141,PR155 and PR156 the S RES 1/16W 0.2 DVT
909+-1% 0402.
3.Add PR134 S RES 1W 0.01 +-1%2512.
1.Delete PR175 the S RES 1/16W 158K+-1% 0402.

2. PACIN pin's high level is only 2.3V. To adjust PACIN pin's level. 0.2 39 2.Change the PR172 from S RES 1/16W 100K +-1% 0402 S 0.2 DVT
to RES 1/16W 10K +-1% 0402.
1.Change the PR105 from S RES 1/16W 47K +-1% 0402 S

to RES 1/16W 100K +-1% 0402.
3. The 5VALWP rising time is faster than To delay timer of 5VALWP. 0.3 40 0.3 DVT2
PACIN's. 2.Change the PC91 from S CER CAP .047U 25V M X7R 0603
to CAP 1U 25V Z F Y5V 0805..
4. The charge has error on change mode. To adjust input and output current 0.3 39 1.Change PC152 and PC153 from the S CER CAP 0.01U 16V +-10% 0.3 DVT2
regulation loop compensation. X7R to CER CAP 0.001U 16V +-10% X7R.
2 2
42
5. For cost down solution. 0.3 1.Change PC58,PC68,PC95 and PC99 from the S CER CAP 4.7U 0.3 DVT2
For cost down solution. 43 25V K X5R 1206 to CAP 4.7U 10V K X7R 0805.
6. The charger has EMI issue. Add a resistor on charger's boost for EMI. 0.3 39 1.Add the PR1 S RES 1/16W 0 +-5% 0402. 0.3 DVT2
Change the current limit's from sense To adjust current limit point for CPU_CORE. 0.3 44 1.Change the PR142 from S RES 1/16W 200K +-5% 0402 0.3 DVT2
7. DRC to resister. to S RES 1/16W 470K +-5% 0402.
To preven in-rush current for B+ of To preven in-rush current for B+ of 0.3 40 1.Add PR2 S RES 1/8W 33 +-5% 1206. 0.3 DVT2
8. MAX1902. MAX1902.
1.Add PQ26 SB502060000 S TR RHU002N06 1N SOT323.

2.Add PR134,PR141,PR155,PR156 S RES 1/16W 909 +-1% 0402.
0.3 44 3.Delete PL14 S COIL .5UH +-30% CXZT1050-R50 28A.
9. The CPU's dual choke will shortage. Change to single choke. 0.3 DVT2
4.Add the PL14,PL15 S COIL .56UH +-20% ETQP4LR56 WFC 21A.
5.Add the PC124,PC137 0.47U 16V +-10% X7R 0603 S8.
3 3
4.Add the PL14,PL15 S COIL .56UH +-20% ETQP4LR56 WFC 21A.
1.Delete the PU10 S IC APW7057KC-TR SOP-8 PWM.

2.Delete the PQ43 S TR AO4912 2N SO8 W/D.
3.Delete the PR188 S RES 1/16W 0 +-5% 0402.
4.Delete the PR195 S RES 1/16W 2.2 +-5% 0402
5.Delete the PR196 S RES 1/16W 4.12K +-1% 0402
6.Delete the PR198 S RES 1/16W 10K +-1% 0402
7.Delete the PR197 S RES 1/16W 12.7K +-1% 0402.
10. Delete the +1.8VSP on M/B. Delete the +1.8VSP on M/B.
0.3 42 8.Delete the PL18 S COIL 5.0UH +-20% TPRH6D38-5R0M-N 2.9A.
9.Delete the PC166 S POLY CAP 150U 6.3V M V(D2) T520 LESR.
0.3 DVT2
10.Change the PC75 and PC87 from S CER CAP 4.7U 10V Z Y5V
0805 to S CER CAP 4.7U 6.3V +-10% X5R 0805
11.Delete PC95 S CER CAP 4.7U 10V Z Y5V 0805.
12.Delete PC163,PC165,PC168 .1U 16V +-10% X7R 0402.
4 13.Delete PC164 S CER CAP 470P 50V +-10% X7R 0402. 4
14.Delete PD33 S DIO 1SS355.

Title
PIR
A B C D E
A B C D E
1 1.Add PQ1 SB502060000 S TR RHU002N06 1N SOT323. 1
2.Add PQ2 S TR DTC115EUA NPN (UMT3).

3.Add PD2 S SCH DIO RB715F UMD3.
4.Add PD1 S DIO 1N4148 (SM)
5.Add PR10,PR11,PR12 and PR13 S RES 1/4W 1.5K +-5% 1206.
6.Add PR16 S RES 1/16W 100K +-1% 0402.
7.Add PR17 and PR20 S RES 1/16W 499K +-1% 0402.
Max1902 protect When power cord fast 0.3 38 0.3 DVT2
1. plug-out and plug-in. Add the pre-chagre circuit. 8.Add PR19 S RES 1/16W 191K +-1% 0402.
9.Add PR23 S RES 1/16W 34K +-1% 0402.
10.Add PR26 S RES 1/16W 66.5K +-1% 0402.
11.Add PR14 S RES 1/16W 2.2M +-5% 0402.
12.Add PR24 S RES 1/16W 47K +-5% 0402.
13.Add PC10 and PC12 S CER CAP 1000P 50V +-10% X7R 0402.
14.Add PC11 S CER CAP .1U 25V K X7R 0603.
2 The 5VALWP choke rating is not enough. Change the choke. 0.3 40 1.Change the PL9 from S COIL 10UH +-30% SDT-1050P-100- 0.3 DVT2 2
2. 118 3.5A to S COIL 10uH +-20% SDT-1205P-100-118.
3. TP0610T will EOL. Change the part. 0.3 43 1.Change the PQ16 S TR TP0610T 1P SOT-23 to.S TR TP0610K 0.3 DVT2
1P SOT-23
3 3
4 4

Title
PIR
A B C D E
A B C D E
1 1. To adjust sequence for +5VALWP and +3VALWP. To adjust sequence for +5VALWP and +3VALWP. LA-2362-0.2 41 1.Change PC90 from .47U 16V X7R 0603 to 2.2U 10V X5R 0805. LA-2362-0.2 DVT3 1
2. Change the pull-high resistor for VGTE pin. For HW request. LA-2362-0.2 45 1.Change PR122 from 100K 0402 to 10K 0402. LA-2362-0.2 DVT3
The system has re-boot issue when running 1.Add the PL3 FBL-18-453215-900LM90T_1812.
3. the 3D mark. The HW has noise by interference from B+. LA-2362-0.2 42 LA-2362-0.2 DVT3
2.Add the PC35 and PC41 0.1U 25V X7R 0603,
The CPU's B+ has nosie issue when system The CPU's B+ has nosie issue when system LA-2362-0.2
4. into C3/C4. into C3/C4. 45 1.Add the PC14 220U 25V. LA-2362-0.2 DVT3
5. To cost down for 150uf/6.3V. To cost down for 150uf/6.3V. LA-2362-0.2 41,45 1.Change the vendor form KEMET to EPCOS. LA-2362-0.2 DVT3
6. Change the IC solution from ISL6227 to

MAX8743 for +2.5V and +VCCPP. The ISL6227 has shut down issue when windows idle. LA-2362-0.2 42 LA-2362-0.2 DVT3
2 2
3 3
4 4

Title
PIR
A B C D E

Acer Aspire 3500 Esquema

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Acer Aspire 3500 Esquema

Uploaded by

Copyright:

Available Formats

5 4 3 2 1

Sonoma Dothan EAL50_1

Security Classification Compal Secret Data

Compal confidential Block Diagram

uFCPGA CPU ICS

3.3V 24.576MHz AC-LINK BATT IN/+2.5V

Security Classification Compal Secret Data

I2C / SMBUS ADDRESSING

External PCI Devices

DEVICE IDSEL # REQ/GNT # PIRQ PCB Rev Data

LAN AD17 0 F Bringup-Build 0.1

S5 S4/AC ON OFF OFF

S5 S4/AC don't exist OFF OFF OFF

Ceramic Capacitor Spec

CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R

CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%

+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20%

SMBUS Control Table

THERMAL THERMAL VGA Thermal

Security Classification Compal Secret Data

1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)

Security Classification Compal Secret Data

POWER, GROUNG, RESERVED SIGNALS AND NC

GTLREF VSS VSS VSS

20 mils COMP3 COMP2 VSS VSS VSS

T3 PAD B2 K26 R25 AF15

T20 PAD E26 L6 T5 AF19

T29 PAD RSVD VSS VSS VSS

Security Classification Compal Secret Data

Near VCORE regulator.

ESR <= 3m ohm

Security Classification Compal Secret Data

DMI_TXN0 AA31 G16 CFG0

CFG18 Low = 1.05V (Default)

1 1 CFG[19:18] have internal pull-down

(VTT Select) High = 1.2V

3.5 k reserve for choose

Security Classification Compal Secret Data

DDR SYSTEM MEMORY B

DDR MEMORY SYSTEM A

Security Classification Compal Secret Data

B16 N30 PEG_RXN8

4.99K_0603_1% 0_0402_5% T34 PEG_RXN11

EXP_RXN11 PEG_RXN12 +2.5VS

PCI - EXPRESS GRAPHICS

LVDS_BC- C25 V36 PEG_TXN13

Security Classification Compal Secret Data

M10 AK25 H28 +2.5VS_PM 2@ R738 1 2 0_0603_5%

Y9 VTT23 VCCSM23 AG25 U27 VCC19 VCCHV0 B22 +2.5VS

N4 VTT41 VCCSM41 AK13 W20 VCC37 VCC3G5 L37

M2 VTT46 VCCSM46 AE13 U19 VCC42 VCCA_3GPLL0 Y29

N1 AM12 + V18 +2.5VS_3GBG +2.5VS

AG12 AC1 H20 VCC_SYNC C365 C31

L19 +1.5VS_DPLLB L11 +1.5VS_HPLL L23 +1.5VS_MPLL L20 +1.5VS_DPLLA

+VCCP +2.5VS +VCCP +3VS

+VCCP U5H +2.5V

VSS_NCTF51 VCC_NCTF74 VSS238 VSS172 VSS110 VSS42

V26 VCC_NCTF1 VCC_NCTF12 T25

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Security Classification Compal Secret Data

2@ ACES_85205-1000 PEG_TXP2 R357 75K_0402_5% PEG_RXP14

Modify for 1.8vs move to VGA BD U1 PEG_TXP7 PEG_RXN[0..15] +5VS PEG_TXN[0..15]