Digital Logic Circuit

UNIT - 1: NUMBER SYSTEMS

1. A number system with base „b‟ will have „b‟ different digits from 0 to (b-1)
2.
Number System Base (b) Digits
Binary 2 0,1
Octal 8 0, 1, 2, 3, 4, 5, 6, 7
Decimal 10 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
Hexadecimal 16 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
A, B, C, D, E, F.

3.
Decimal Hexadecimal Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111

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4. 4 bits = 1 nibble
8 bits = 1 Byte
5. Binary coded decimal code (BCD)
(i) In 4 bit binary formats
Possible representation = 24 = 16
Valid BCD codes = 10
Invalid BCD codes = 6
(ii) In 8 bit binary formats possible representation = 28
Valid BCD codes = 100
Invalid BCD codes = 156
6. Largest number that can be represented by using N bits = (2N − 1)10

UNIT – 2: LOGIC GATES

I/P O/P
1. NOT gate
A Y=A
0 1
1 0

I/P O/P
2. AND gate A B Y = AB
0 0 0
0 1 0
1 0 0
1 1 1

3. OR gate I/P O/P

A B Y = A+B
0 0 0
0 1 1
1 0 1
1 1 1

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4. NAND gate
I/P O/P
A B Y = AB
0 0 1
0 1 1
1 0 1
1 1 0

5. NOR gate I/P O/P

A B Y= A + B
0 0 1
0 1 0
1 0 0
1 1 0

6. EX-OR gate I/P O/P

A B Y=A⊕B

0 0 0
0 1 1
1 0 1
1 1 0

7. EX-NOR gate I/P O/P

A B Y = A⊙B

0 0 1
0 1 0
1 0 0
1 1 1
8.
No of NAND No of NOR gate
Logic Gates
gate required required
NOT 1 1
AND 2 3
OR 3 2
EX-OR 4 5
EX-NOR 5 4

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UNIT - 3: BOOLEAN ALGEBRA

1) Commutative law: 𝐴 + 𝐵 = 𝐵 + 𝐴
𝐴 .𝐵 = 𝐵 .𝐴
2) Associative law: 𝐴 + (𝐵 + 𝐶) = (𝐴 + 𝐵) + 𝐶 = 𝐴 + 𝐵 + 𝐶
𝐴. (𝐵 . 𝐶) = (𝐴 . 𝐵)𝐶 = 𝐴𝐵𝐶
3) Distributive law: 𝐴 (𝐵 + 𝐶) = 𝐴𝐵 + 𝐴𝐶
(𝐴 + 𝐵) (𝐶 + 𝐷) = 𝐴𝐶 + 𝐴𝐷 + 𝐵𝐶 + 𝐵𝐷
4) Boolean algebraic theorems
(i) 𝐴 . 𝐴 = 𝐴; 𝐴 .0 = 0
𝐴 .1 = 𝐴; 𝐴 . 𝐴 = 0
(ii) A = A
(iii) 𝐴 + 𝐴 = 𝐴; 𝐴 + 0 = 𝐴
𝐴 + 1 = 1; 𝐴 + 𝐴 = 1
(iv) Demorgan’s theorem,
1) 𝐴 . 𝐵 . 𝐶 = 𝐴 + 𝐵 + 𝐶 2) 𝐴 + 𝐵 + 𝐶 = 𝐴 . 𝐵 . 𝐶
(v) Transposition theorem
0 (𝐴 + 𝐵) (𝐴 + 𝐶) = 𝐴 + 𝐵𝐶
(vi) Distribution theorem
𝐴 + 𝐵𝐶 = (𝐴 + 𝐵) (𝐴 + 𝐶)
(vii) Consensus Theorem
𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 = 𝐴𝐵 + 𝐴𝐶

Other Theorems:

1) (𝐴 + 𝐵) . (𝐴 + 𝐵 ) = 𝐴 5) (𝐴 + 𝐵) (𝐴 + 𝐶) = 𝐴𝐶 + 𝐴𝐵
2) 𝐴 + 𝐵 + 𝐶 = 𝐴. 𝐵 . 𝐶 6) 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 = 𝐴𝐵 + 𝐴𝐶
3) 𝐴𝐵 + 𝐴𝐶 = (𝐴 + 𝐶) (𝐴 + 𝐵) 7) (𝐴 + 𝐵) (𝐴 + 𝐶) (𝐵 + 𝐶) = (𝐴 + 𝐵) (𝐴 + 𝐶)
4) 𝐴 . 𝐵 . 𝐶 = 𝐴 + 𝐵 + 𝐶

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5) Duality Theorem:-
(i) Change OR Sign to AND sign
(ii) Complement “0” to “1”
(iii) Keep literals as it
n
 For N variables, maximum possible self-dual function = 2(2 /2 )
 With N variables, maximum possible distinct logic functions = 22n
6) AND – OR logic ≡ NAND – NAND logic in SOP
OR – AND logic ≡ NOR – NOR logic in POS
7)
Dual Complement
1) AND ↔ OR 1) AND ↔ OR
2) 1 ↔ 0 2) 1 ↔ 0
3) Keep variable as it as 3) Complement each variable
8)
With „n‟ variable max possible logical expressions = 22n
n −1
With „n‟ variable max possible self dual expressions = 22
9) Digital Number Representation:-
(i) Unsigned magnitude representation = 0 to (2n - 1)
(ii) Signed magnitude representation = - (2n−1 - 1) to + (2n−1 - 1)
(iii) Range of 1‟s complement number = - (2n−1 - 1) to + (2n−1 - 1)
(iv) Range of 2‟s complement number = -2n−1 to + (2n−1 – 1)

UNIT - IV: COMBINATIONAL CIRCUITS

1.
Type of Circuit Logical Expressions
Sum = A⨁B
Half adder
Carry = AB
Difference = A⨁B
Half Subtractor
Borrow = AB
SUM = A⨁B⨁C
Full Adder
Carry = AB + BC + CA
Difference = A⨁B⨁C
Full Subtractor
Borrow = AB + AC + BC

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2.
Type of No of gates
circuit required
NAND NOR
Half adder 5 5
Half
subtractor 5 5
Full adder 9 9
Full subtractor 9 9

3. Full adder can be implemented with = Two half adder + one OR gate
4. Parallel adder [Ripple carry adder (or) Binary adder]
 n FA (or) (n – 1) FA & one HA FA → Full adder
(or) HA → Half adder
(2n -1) HA & (n – 1) OR
5. Delay time (𝐓𝐝𝐞𝐥𝐚𝐲 ):
 Tdelay = (n – 1) t cpd + max (t spd , t cpd )
Where t cpd → Carry propagation delay
t spd → Sum propagation delay

6. Multiplexer:
 Y0 = (ABI0 + A B I1 + A BI2 + A B I3 ) E
 m ≤ 2n (or) log 2 m ≤ n

7. 2 : 1 multiplexer applications:
Multiplexer Logical Expression

Y0 = A
(NOT)

Y0 = A B + A
=A+B
(OR)

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Y0 = A.0 + AB
Y0 = AB
(AND)
Y0 = AB + A.O
Y0 = A + B
(NOR)

Y0 = A.1 + AB
=A+B
Y0 = AB(NAND)

Y0 = A⨁B
(EX – OR)

Y0 = A⊙B
(EX – NOR)

8) Higher order mux using lower order mux:

Required Number
Given Mux Needed Mux
of Mux
2:1 4:1 3
4:1 16 : 1 4+1=5
4:1 64 : 1 16 + 4 + 1 = 21
8:1 64 : 1 8+1=9
8:1 256 : 1 32 + 4 + 1 = 37

9) Demultiplexer: (One to many circuit):

1 : 2 Demux

D0 = SA ; D1 = SA

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1 : 4 Demux
D0 = S1 S0 A
D1 = S1 S0 A
D2 = S1 S0 A
D3 = S1 S0 A

10. Higher order Demux using lower order Demux:

Given Needed
Required number of mux
Demux Demux
1:2 1:4 1+2=3
1:2 1:8 1+2+4=7
1:2 1 : 16 1 + 2 + 4 + 8 = 15
1:2 1 : 64 1 + 2 + 4 + 8 + 16 + 32 = 63
1:4 1 : 16 1+4=5

11. 2 ×4 Decoder :
E A B 𝐃𝟎 𝐃𝟏 𝐃𝟐 𝐃𝟑
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
Higher order decoder using lower order decoder:

Required
Needed
Given decoder number of
decoder
decoder
2:4 4 : 16 1+4=5
2:4 3:8 2 + Not gate
4 : 16 8 : 256 1 + 16 = 17

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12. Code Converters:

(i) BCD to Excess – 3 code : (BCD + 0011 = excess – 3 code)

Input (BCD) Output (Excess – 3 code)

A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0

(ii) Binary to gray converter

G3 = B3
G2 = B3 ⨁B2
G1 = B2 ⨁B1
G0 = B1 ⨁B0
(iii) Gray to Binary converter
B3 = G3
B2 = B3 ⨁G2
B1 = B2 ⨁G1
B0 = G1 ⨁G0
(iv) Magnitude Comparator

A B X Y Z
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
o/p Expression AB A⊙B AB

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UNIT - V: SEQUENTIAL CIRCUITS

Flip Flop Truth Table

1) SR Flip Flop
CLK S R Q 𝐐
0 X X Previous
1 0 0 Previous
1 0 1 0 1
1 1 0 1 0
1 1 1 NOT ALLOWED

2) J-K Flip Flop

CLK J K 𝐐𝐧 𝐐𝐧
0 X X Previous
1 0 0 Previous
1 0 1 0 1
1 1 0 1 0
1 1 1 Toggle

3) D Flip Flop
CLK D O/P
0 X Previous
1 0 0
1 1 1

4) T – Flip Flop CLK T 𝐐𝐧+𝟏

0 X Qn (Previous)
1 0 Qn (Previous)
1 1 Qn Toggle

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2) Characteristic Table
JK Flip Flop SR Flip Flop T Flip Flop

J K 𝐐𝐧 𝐐𝐧+𝟏 J K 𝐐𝐧 𝐐𝐧+𝟏 T 𝐐𝐧 𝐐𝐧+𝟏

0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 0 0 1 0 1
0 1 1 0 0 1 1 0 1 1 0
1 0 0 1 1 0 0 1 Qn+1 = T⨁𝑄𝑛
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 X
1 1 1 0 1 1 1 X

Qn+1 = JQn + KQn Qn+1 = S + R

3) Excitation Table
JK FF SR FF

𝐐𝐧 𝐐𝐧+𝟏 S R
𝐐𝐧 𝐐𝐧+𝟏 J K
0 0 0 X
0 0 0 X
0 1 1 0
0 1 1 X
1 0 0 1
1 0 X 1
1 1 X 0
1 1 X 0

D FF T - FF

𝐐𝐧 𝐐𝐧+𝟏 𝐃 𝐐𝐧 𝐐𝐧+𝟏 T

0 0 0 0 0 0

0 1 1 0 1 1

1 0 0 1 0 1

1 1 1 1 1 0

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4) Race-around condition:
(i) J = K = 1
(ii) 𝑡𝑝𝑑 𝐹𝐹 <𝑡𝑝𝑤
(iii) Flip – flop is level triggered

UNIT - VI: COUNTERS

1) N = total number of states

N = no of FF‟s → N ≤ 2n
2) If N = 2n → Binary counter
N <2n → Non-binary counter
3) For n FF ′ s → 2n states → called MOD - 2n counter capable of counting (2n - 1) states.
4) FOR MOD-N counter, I/P frequency = f
f
O/P frequency = N

5) If two counters cascaded

Modulus number =
𝑓𝑖
 Output freq. = 𝑥.𝑦

6) Binary ripple counter (Asynchronous Counter)

1
(i) fclk ≤ nt pd (FF )
t pd =Propagation delay
1
(ii) Maximum clock frequency, fclk = nt pd (FF )

7) Up/down counter

Clock
Triggering Counter
Connection
-ve edge Q Up counter
+ve edge 𝑄 Up counter
-ve edge 𝑄 Down counter
+ve edge Q Down counter

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8) Synchronous Counters:
(i) Ring counter: (non self starting counter)
 Modulus number = n
f
 fo = ni
 max count = 2n−1
 Tdelay = t pd
(ii) Johnson Counter: (Twisted Ring Counter)
 Modulus number = 2n
f
 fo = 2𝑛i
 max count = 2n − 1
(iii) Synchronous series carry counter (serial counter)
 Modulus number = 2n
f
 fo = 2ni
 max count = 2n -1
 Tdelay = t pd (FF ) + (n - 2) t pd
(iv) Parallel counter
 Modulus number = 2n
f
 fo = 2ni
 max count = 2n -1
 Tdelay = t pd ff + t pd
Where t pd FF ⇒ propagation delay of flip flop
t pd ⇒propagation delay of gate
Shift Registers
(i) I/P O/P Total
Serial in serial out (SISO) n n-1 2n-1
Serial in parallel out (SIPO) n 0 n
Parallel in serial out (PISO) 1 n-1 n
Parallel in parallel out (PIPO) 1 0 1

where n = no of F.F‟s
(ii) Interms of speed:
PIPO > PISO > SIPO > SISO

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UNIT – VII: DIGITAL CONVERTERS

1) Digital to Analog Converter (DAC):

Specifications:
vr
(i) Resolution = , vr = reference voltage ; n = number of bit
2n −1

(ii) Resolution × Decimal equivalent of binary data = Output Voltage

(iii) Analog O/P voltage
Vo = k 2N−1 bN−1 + 2N−2 bN−2 + ⋯ 21 b1 + b0
Where k → proportionality factor
bn →1 ; If nth bit of digital i/p is 1.
→ 0 ; If nth bit digital i/p is 0.
(iv) Full scale output voltage = Resolution × max decimal
Vr
(vFS ) = × (2n − 1) = Vr
2n −1
Resolution 1
% Resolution = × 100 = × 100
V FS 2n −1

2) Weighted Resistor DAC:

RF
(i) Output Voltage V0 = (2N−1 VN−1 + 2N−2 VN−2 + ⋯ 20 V2 )
2N −1 .R
RF
(ii) Proportionality factor k = VR
2 −1 .R
N

(iii) LSB Resistance = 2N−1 × 𝑀𝑆𝐵 𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒

(iv) For N bit DAC,
Number of different levels = 2N
Number of steps = 2N -1
3) R-2R ladder type DAC:
RF Vr Vr Vr
V0 = D2 × + D1 × + D0 ×
3R 2 4 8

4) Counter type DAC:

V FSC
(i) Resolution = 2n −1
1
(ii) % Resolution = × 100
2n −1
(iii) No of clock pulse required for n-bit conversion = 2n -1
(iv) Maximum conversion time = (2N − 1). TCIK
(v) VO = VDAC = R × (Decimal equivalent of binary)
(vi) VFSC = (2𝑛 − 1) × Step Size

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5) Flash type ADC:

It requires (i) 2n − 1 comparators
(ii) 2n resistors
(iii) One 2n × n priority encoder
6) Successive approximation type ADC:
(i) Number of clock pulse required = n
(ii) Maximum conversion time = n * TCIK
7) Dual slope integrating type ADC:
Va
(i) Count = 2n
VR

(ii) Tconv = (2n+1 -1)TC

1
(iii) fsamp = (2n +1 −1)T C

(iv) De-integration time

Va
(T2 - T1 ) = × Integration time (T1 )
VR

(v) T1 = 2n TC
𝐷𝑒−𝑖𝑛𝑡𝑒𝑔𝑟𝑎𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒
(vi) Va = × VR
𝐼𝑛𝑡𝑒𝑔𝑟𝑎𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒

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