Record RF performance of 45-nm SOI CMOS Technology
Sungjae Lee, Basanth Jagannathan*, Shreesh Narasimha*, Anthony Chou*, Noah Zamdmer*, Jim
Johnson, Richard Williams, Lawrence Wagner*, Jonghae Kim*, Jean-Olivier Plouchart*, John Pekarik,
Scott Springer and Greg Freeman*
IBM Systems and Technology Group, Essex Junction, VT 05452 USA, *Hopewell Junction, NY 12533 USA
Phone: +1-802-769-4574, Fax: +1-802-769-4139, e-mail:sungjae@us.ibm.com
Abstract
We report record RF performance in 45-nm silicon-on-
insulator (SOI) CMOS technology. RF performance scaling
with channel length and layout optimization is demonstrated.
Peak fT's of 485 GHz and 345 GHz are measured in floating-
body NFET and PFET with nearby wiring parasitics (i.e., gate-
to-contact capacitance) included after de-embedding, thus
representing FET performance in a real design. The measured
fT's are the highest ever reported in a CMOS technology. Body-
contacted FETs are also analyzed that have layout optimized
for high-frequency analog applications. Employing a notched
body contact layout, we reduce parasitic capacitance and gate
leakage current significantly, thus improving RF performance
with low power. For longer than minimum channel length and a
body-contacted NFET with notched layout, we measure a peak
fT of 245 GHz with no degradation in critical analog figures of
merit, such as self-gain.
Introduction
This high-performance 45-nm SOI technology features 1.16
nm gate oxide, dual stress liners (DSL), eSiGe PFET, advanced
activation annealing, and stress memorization techniques
(SMT) [1]. Advanced immersion lithography employed
provides good channel length control and supports multiple
gate pitches. To investigate the suitability of this high
performance CMOS technology for millimeter-wave digital
and analog system-on-chip (SoC) applications [2, 3, 4], S-
parameter measurements at frequencies up to 110 GHz were
performed to analyze RF/analog characteristics of partially-
depleted 5O0 NFET/PFETs in floating body and body contact
layout configurations.
Performance Results and Discussion
A. Floating-body SOI FETRE performance
Fig. 1 illustrates the FET layout with gate poly pitch and
source/drain contact pitch that can be optimized for RF
performance. Fig. 2 shows the current gain lH211 of a 30 gm
wide (1 tm by 30 gate fingers), 29 nm Lpoly NFET and a 30 tm
wide, 31 nm Lpoly PFET, where the expected -10 dB/dec slope
of H211 vs. frequency is achieved. As shown in Fig. 3, peakfT's
of 485 GIHz and 345 GIHz for NFET and PFET respectively are
the highest reported at any channel length in a CMOS
technology [2, 3, 4, 5]. It should be noted that the measured fT
(= gm / (22t(Cgs ± Cgd)) ) for this work includes near-FET wiring
parasitic resistance and gate-to-contact capacitance, thus
representing practical device performance in a circuit. Figs. 4
1-4244-0439-X/07/$25.00 © 2007 IEEE
and 5 highlight how relaxed gate pitch improves fT which
results from not only lower capacitance from wider gate-to-
contact spacing but also enhanced stress response (higher
transconductance gm) of the device. Fig. 6 shows peak fTvs.
I/Lpoly for SOI CMOS from 90 to 45-nm nodes,
demonstrating that RF performance scaling continues with
Lpoly in deep sub-lOOnm CMOS technologies. Figs. 7 and 8
show the gm and Cgate (= Cgs + Cgd) vs. I/Lpoly extracted at
peak fT condition for 45-nm SOI NFETs and PFETs,
indicating the well controlled channel with Lpoly.
Source/drain contact pitch as well as gate poly pitch can be
optimized for RF applications, and Figs. 9 and 10 show the
measuredfT and gm for minimum poly pitch SOI NFETs and
PFETs with an Lp of 31 nm as a function of gate bias,
where wider source/drain contact pitches result in higherfT,
due to the lowering of gate-to-contact capacitance with
fewer contacts. Note also in Figs. 9 and 10 that the gm of the
device is not affected much by the potential increase of
source/drain resistance with fewer contacts.
B. Body-contacted SQL FET analog/RF Performance
In high-frequency analog circuits, device self-gain (gm
over output conductance gds) and matching between
neighboring devices are important. For such consideration,
we investigate SOI NFETs with longer than minimum
channel length (for high self-gain) and a body contact (for
good matching due to reduced VBS fluctuation). Fig. 11
shows the measured self-gain as a function of gate bias for a
floating-body NFET with 32 nm Lp01y and body-contacted
NFET with 46 nm LpI. As shown in Fig. 11, higher self-
gain results from lower gds in longer Lpoly device. Body-
contacted SOI FETs, however, come with the parasitic
capacitance and leakage current penalties from the
additional poly and its overlap with oxide and silicon
underneath that compose its body contact. These inevitable
parasitics are carefully minimized from scaling with
advanced SOI technology, but as shown in Figs. 12 and 13,
fixed parasitic capacitance has significant impact on fT
performance, especially for narrower width device. By
comparing total input (gate) capacitance of different width
FETs having the same fixed body contact parasitics, the
contributions of intrinsic FET and body contact parasitics to
the total gate capacitance are separately determined, as
shown in Fig. 14 for a 13 gm wide (0.65 gm by 20 gate
fingers) body-contacted NFET with 46 nm Lp,,,y. Note that
capacitance from body contact associated parasitics is
comparable to the contribution from the intrinsic FET with
narrow finger width. To overcome these limitations, we take
the alternate layout approach to reduce capacitance and
255
leakage current. Fig. 15 compares body-contacted FET layout
with conventional rectangular body contact area (A) and
notched body contact area with its overlap under gate poly
minimized (B). Note that both layout styles, illustrated in Fig.
15, have the same footprint. Fig. 16 shows the significant
reduction in parasitic capacitance with notched body contact
layout, resulting in improved RF performance, as shown in
Figs. 17 and 18. Self-gain is not affected by employing notched
boycontact
body layout, as
contact layout, as shown in Fig.
shown in 19.
Fig. 19.
Conclusion
Record fT's of 485 GHz and 345 GHz are demonstrated for
SOI NFET*and
501 NFET and PFET in 45*nm microprocessor
in aa 45-nm microprocessor 501
SOI
technology. Technology design rules enable layout
optimization to maximize RF performance while maintaining
effective channel length control. Small-signal equivalent circuit
parameters of the device are extracted from the measured -
parameters to understand the contributions of intrinsic and
parasitic elements to the RF/analog performance. To overcome
the limitations of the body-contacted S01 FET with a
conventional body contact layout, we have employed a
notched body contact layout to minimize parasitic
capacitance and leakage current that achieves peak fT's of
245 GHz and 190 GHz for NFET and PFET, the highest
reported for a body-contacted SOI FET.
References
[1] s. Narasimha et al., "High performance 45-nm 501 technology with
enhanced strain, porous low-k BEOL, and immersion lithography," in
Int. Electron Devices Meeting Tech. Dig., 2006, pp. 689-692.
[2] S. Lee et al., "Record RF performance of sub-46 nm Lgate NFETs in
microprocessor SOI CMOS technologies," in Int. Electron Devices
[3] Meeting
I. Post etTech.
al., Dig., pp. 251-254.
2005,CMOS
"A 65nm SOC technology featuring strained
silicon transistors for RF applications," in Int. Electron Devices
Meeting Tech. Dig., 2005, late news.
[4] S. Lee et al., "SOI CMOS technology with 360GHz fT NFET,
260GHz fT PFET, and record circuit performance for millimeter-wave
digital and analog system-on-chip applications," in Symp. VLSI Tech.
Dig., 2007, pp. 54-55.
[5] H. Li et al., "Technology scaling and device design for 350 GHz RF
performance in a 45nm bulk CMOS process," in Symp. VLSI Tech.
Dig., 2007, 56-57.

40
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S PFET
Poly pitch 30

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(A) (B) (C) 10° 10o1 10o2 10
Frequency (GHz)
Fig. 1. FET layout schematic showing A: geometries (i.e., gate poiy pitch and Fig. 2. Current gain 111211 from measured S-
source/drain contact pitch) that can be optimized to improve RF performance, B: FET parameters for 30 Rim wide (1 Rim by 30 gate
layout with wider poiy pitch, C: FET layout with fewer source/drain contacts (with wider fingers) SOI NFET (Lp01y =29 nm) and SOI
contact pitch) PFET (Lotcp=3h1 nm) with relaxed poly pitch
at VGS 0.6 (-0.6) V, VDS =1.0 (-1.0) V.

256
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LN01y. [2]-[5])
Most of published results (see, 1.0 V) for 45-nm P01 NFET (LC1y =29 nm) =-1.0 V) for 45-nmC0. PFET (Lp01y =31
e.g., are measured from NFET. with (A) relaxed poly pitch and (B) minimum nm) with (A) relaxed poly pitch and (B)
poly pitch. obtained by extrapolating the minimum poly pitch. obtained by
value of IH211 at 10 GHz using -1I0 dB/dec extrapolating the value of IH211 at 10 GHz
slope after de-embedding. using -10 dB/dec slope after de-embedding.
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Fig. 7. 45-nm SO! NFET (and PFET) peak
fvs. I/Lp01y (measured at VDs =1 .0 and - (= Cgs ± Cgd) VS. 1I/Lpoly, measured at VGs
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=0 V), measured for rectangular VBS =0 V), measured for rectangular V), extracted from measured S-parameter
body-contacted SOI NFETs (Lpoly =46 body-contacted SOI PFETs (Lpoly =42 data at 10 GHz for 13 Rtm (0.65 Rtm by 20
nm) having three different widths. nm) having three different widths. gate fingers) SOI NFET with rectangular
body contact, comparing contributions from
intrinsic (active) FET and body contact
associated parasitic component.
30
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(A (B)ll| |||||||||||||||||||||||||||
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VGS (V)
Fig. 15. Layout schematic comparing A: rectangular silicon area for body contact Fig. 16. Gate capacitance vs. VGS (at VDS =1
region (used for body-contacted device plots in Figs. 11, 12, 13 and 14), B: V), extracted from measured S-parameter data
notched silicon area for body contact region. Both layout styles have the same at 10 GHz for 13 Rim (0.65 Rim by 20 gate
footprint, fingers) SOI NFET with notched body
contact, comparing contributions from
intrinsic (active) FET and body contact
associated parasitic component.

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GS (V) VGS (V) VGS (V)
Fig. 19. Measured self gamn(= gm/g VS. VGS
Fig. l7.fT vs. VGS (at VDS =1.0 V, VBS =O Fig. 18.fT vs. VGS (at VDS = 10V BS= gB
aD =1. V, gO () frmdS-prmee
V), measured for notched body contact V), measured for notched body contact daat10Gzfr3 m,by-oace
SOI NFETs (Lp01y =46 nm) having three SOI PFETs (Lpo01 42 nm) having three GH byr
Sata NFt (0. finers thd
m 20 gat wiy-ona
different widths.different
widths.~~~~~~ Lp01y 46 nm (A: rectangular body contact, B:
notched body contact).

258