por 3. Question No.1 12) 1-1 Draw a two-input NOR gate using two-input NAND gates only. A me “=p Question No.2 13,3] 2.1 Draw the truth table for a D flip-flop with PS and CLR asynchronous inputs on Fer > Mowe a= wt of operon, [Amenronons _ | Syren _ [eel [o> | «| @ Pit yn ehrenete x oD ast ef i | « ! Smet pe [x [se | ets prontat | © ° x x 1 7 see 1 7 Fi [? 1 o toee [ez fe ot je ge he Trveavot- IL seek te . . cam 65m Cy peste PU 2.2 Draw the truth table for a J-K flip-flop with PS and CL. asynchronous inputs. o~ super move -p_ | Qognarinee | Sy ron < open | ps cL wef oO] «© o f ° Pip erroros of! x fata ace papemorsa || ° a» fal x« ° / reek Peni niset ° ° apa] « , 1 ord 1 1 IiPool eo Ne chade . Reset v 7 aVye[ 2 J a : 7 a o 1 2 s oreed stent yogi i } SM 1 recy boo SL 2 vig fe oe brane, rege ay otoete rimeQuestion No.3 13,31 3.1 Convert the binary number in ato f to hexadecimal numbers. a> I 1100 B31 it . te 110011 ep @. 1010101 ee? 3 e. 10il e Me f WMNILL vo —v + olan > z x > Jere pe BORD FOND af sD e+ me 4 4) 10 ;0 10) <) mons oD noon Se > sO —~ e100 Oo} ee 2 cor ool) 3) 3a oo we 3 = = 5 4 3 Pose ) ~. oxr soto Hox?) 4102 2s anit a FF 3.2 Convert the hexadecimal number in a to ft binary numbers. aE b. 10 D a a0 BC LFS 2 Cie oon t 3 Quen ome) 2/2 2)? ) ZZ 1 3 ; ri ° - s— od J 7? 4—> “Lg >. (10 ex 1100 Gen 102). 4lre Gm 0D po ve 102 violQuestion Not 13.2.3.31 ‘41 Dobinary subtraction problems ato fusing the Is competent and nd-aound cary mcthod show your werk) 2 ior=cor? ; io. on tot : cio ny 6 “ine a ol . : / . ~ © 91's complem ew af 001! $1010 2 I'S comple OF OF 4110 emplerm Te; 11000 11001 : Li) a encore Ls cor 100) ! 2), 108 pore pore - 0181 a © @ mnt=se1 1 oe ‘int fore joo! ° ae si as Re —_—__.— loool! poor! To10 0 3158 ae : La —_— — WD ood —_— dvd cro) 42 List two methods of doing binary multiplication with digital clectronic circuits pes. OC Binary mudtiphier GQ wotare toe pouty ipriel using ph gate one hos art 43 Add the following 4-bit 2s complement numbers. Give each sum as 14-bit 2r complement number. Also give cach sim as signed Aocimal number, 0100+ 001 bonus 1101+ 110 4. 0101 + 001 £ nore Mole it @omianre Nol 1 ms. @) 21004001 Me 4 nel 4 1110 —— 0100 ee rere 4+ oo1l yr ot ——_— o~ Ore inal one 7 0io —> fee oli! ol —? F 3100 ee 2 1008 Cpnosanswer) .- 78 o. Signd a) —P @ eve +m vo en 4 1NO bio @ evr +0010 © ii, et! ool +e Ot . _ Gor? + 0010 Oreo Gre) 46 orl a . —_—_—— : a rand ane Lats <=500 fined arse 70013 24S 7 : sigv 949 1 Oreo yD F444 Subract the following 4bit 2s complement numbers. Give cach diffrence as a 4-hit 26 complement mumber. Also give each siference a signed decimal number. 0100 o01t tn ino © 110) -1101~ 4. 101 cove © tonto f oMo-un= Q omirmo= er v0 = ool ) a pos 4) 0100 - 00 D itor pe bbs ct e100 4 0010 at ek Got 410) @eoor (5000 ° Cc, oor 6001 ooo! 000 1 ———2frratanse ow =), 2 +1 ; @ wiemo (py merut> GB vroir 000 / - esol Jor? ene. +0010 pon ~ oa orl 112) ol oe —oolF ol 2 der - _ 2 _ 9.+3 23, J Question Noss val 5.1 Draw a logic symbol diagram for a 3-bit (asynchronous) ripple down counter. Use three J-K flip-flops inthis counter. Show your inputs CLA pulses, PS inputs, and three output indicators labeled C, Brandt me det % 7 “TEP “ snrb me om. - (|e -| e 4 ao. cu cue an tobe Asyremnerens rere centr 5.2 If the ripple down counter in Question 5.1 is recirculating type, what are the next three counts after 100, O11, and O10? sertmne coun 001 000 411 :-~ Question No 61 In Fig. 1 ist the 74194 shift repste's mode of operation during cach ofthe five clock puke Mone of sperasin 13,31 powediat Teast | S020. 871 Ship ovigne Erier ance toga sort G2! Senet e705, 20 62 List the contents ofthe register in Fig, 1 after each of the six clock pulses (4 left bit, D= right bit). ajee pobse aflec poise apler pulse agin pulse apie pune afte prt fool 2 cpa & a i= 0.000 bie 10e ei 10 ae "or Me e: ol f:Question No.7 13.4.3.31 7.1 Write the minterm Boolean expression that would deseribe Table 1 Dao not simplify the Boolean expression, Ys 68é5er AS COSHH ETH E+ BCE a. REC5e +AE COE 4 FEC SET SE acer + 40cbE +9 CRE AT eee 7.2 Simplify the Boolean expression in Question 7.1 by the use of a Karnaush map. Ce per ae re ge? arn 10 Oo “olol? orfar} itt 1) ai Leff el 2 or [ee uv nfo [ut ele nfepitel eo | roto] ol oO 1 ofe ovo J of} o Yeacbe+ 28+ acbe Ys (aue )cBe 4486 be G4 c6G- 73 Draw a logic circuit fiom the simplified Boolean expression in Question 7.2 (use AND, OR, and NOT ates). eo Ys at7cbe ° pe Ls 74 Realaw the logic cireuit in Question 7.3 using only seven two-nput INAND gates, Ae+cbE — ba rare b- a Te =D a Ie —pr ‘Question No. I 1.1 Draw a two-input XOR gate using two-input NAND gates only. Question No.2 2.1 Draw the truth table for a clocked R-S flip-flop. Draw the truth table for a J-K flip-flop without PS and CLR asynchronous inputs. Question No.3 3.1 Convert the binary number in a to fto octal numbers. a. 1100 b. TIE ec 10011 d. 1010101 e. 11110000 © wun ou (qe © 1082 : >) » po. @ 122, Cade oo —> / he 6 ee) — Gedy, > 1 In sy on 5 3 100 ——>. 4 2), OO ms 2 By @ 1010101 9645 @ 11119082 in 99 s ovo — Io waa yo} 2 no 3e or 8 o10 — 92 on 93 oo! ;3.2 Convert the octal number in a to fto binary numbers a * 10 © 6 a7 © 101 £ 41s 8) j10 ove ms © 7 an), @ 7—> (00 0°), OQ 6? — = ae 1 ov @r—C mn om 2(e 1 on OD 000? ) Jol— 101 0000% ef wif © Ce a | Gus © j9 00110!) o Question Nod 11,1,3,3,3), 411 Drow a bockdigram fra fll ar (abel thee inputs nd outputs). B= 028 cin a |= pe nee 2 come = a4 Co@nen ern 4.2 Draw a block diagram of a full subtractor (label three inputs and ‘two outputs). Aitference= AO ° suet faut = Ae 4.3 Do binary subtraction problems a to Fusing the 1s complement and end-around carry method (show your work): a. 0110 -0100= b. 111-0011 TLL 1001 1000-0111 = ot e. 1101 -0010= i oe). el f. 1100-0011 = : 4 7 a 4iel bo eon sone 1190 - . Four _—__— 11810 + fot 111 0 Ted Joe Lo Toot) Cor Ce, z 7200! ee — —, an Cor ore oer jor! ——— © eld 5 2010 1 1 7 4) 100 ae pre? =4.5 Subtract the following 4-bit 2s complement numbers. Give each difference as a 4-bit 2s complement number. Also give each u-% difference as a signed decimal number. a. 0110 -0010= 4- b. 1001 —1110= ec. 0010-1101 = 0102 i tor 0001 vit, © 4 Soe 0100-0111 fy vo! oo f. 1110-0110= © es t iil ! 1 tool 4001! a) eno 4 00! yy 1/00 =0010 atiol ee ov sae ar sari aw 3 th ° 2 wns D438 4) 17110 roo! i —— ert Question Nos 13,3] 3.1 Draw a logic symbol diagram for a 4-bit (asynchronous) ripple down counter. Use four J-K flip-flops in this counter. Show your inputs CLK pulses, PS inputs, and three output indicators labeled D, CB, and A net [ on [5 * 3. 4 « rp ee oP TUR TUR & oe * «2 oe cn D T [ asv 5.2 If the ripple down counter in question 5.1 is a recirculating type, ‘what are the next three counts after 0100, 0011, and 0010? No, "lo Wl No. fone 2 0001 e900 1117 a 0000 ibe ooo! 4 o1el ono on! 1002 ol 010 one eon O10! o10eQuestion No.6 6.1 In Fig. 1, list the 74194 st each of the six clock pulse. 13,3] register’s mode of operation during mode of op moe revasiet lont| Se Susp ig | Sezt guops tops | 5077 | Bi a7 Tobe beet Sez? | Syz? |__| —___ 6.2 List the contents of the register in Fig. 1 after each ofthe six clock pulses (4 = left bit, D = right bit), ‘OUTPUT INDICATORS afer prise Be 0000 apie pruse (7 TT OD 110 after pose ce TI ‘ ; - ile Ler purse h of = mo adhe grse® = ate puse fe 119!tion No. 134,331 71 Write the minterm Boolean expression that would describe Table Tae Do not simplify the Boolean expresion. 12 Simplify tie Boolean expression in Question 7.1 by the use of a Kanraugh ma. neo oo ot peor ot on a oo| 21% el | of 2 ° ole pute Draw a logic circuit from the simplified Boolean expression in Question 7.2 (use AND, OR, and NOT gates) D c 7.4 Redraw the logic circuit in Question 7.3 using only ten two-input NAND gates. (ep Ln, . [>>Question No.t 135] TL Draw a two-input XOR gate using two-input NAND gates only. Question No.2 OS 125, 2.8,25 | 2.1, Draw the wiring diagram for a clocked R-S flip-flop. Four NAND gates form a clocked R-S flip-flop. Show your inputs CLK pulses, outputs Q and Q, “ & é « 2.2 List the mode of operation of the 7475 four-bit latch for cach time brome Ge time bys dome dy &y S and R inputs. Also show (wo su period (1 through 4s) shown in Figure 1 ~~. time We bee tet oe 2.3, List the binary output (four-bit) at the output indicators of the 7475 four-bit latch for each time period (t; through fs) shown in Figure 1 ho Time) BINARY OUTPUT pata Nurs Sig liouat arene foietol Peteee teers! opto oo arenes oes oat me Le bes 1 ome by a biome 1 ° 1 bom tn 1 ° 1 hime is ° 1 oO 1 o)} cine tw 1 ot1) —> 1000— 100! 3.2 Subtract the following 4-bit 2s complement numbers. Give each difference as a 4-bit 2s complement number. Also give each , difference as a signed decimal number @ ove oro! @ o01-o1ll= = ————> 4 ‘T00r 700 . 0001-1101 ee ray a Page 2of 4 erry Ter ene 71108 ool = 4 1100 4 ©. 0011-0100 = Stam ) 0100-1101 eee @Q eee—1e © 0001 —0110= eayoeT oreo _) 4 ool fool 2) e001 + lobo + ileees Toll —0 100 =o1o!l a- Sy Question Not 1441 4.1, Draw a logic symbol diagram fora 4-bit (asynchronous) ripple up counter. Use four IK flip-flops in this mod-16 counter. Show your inputs CLK pulses, and four output indicators labeled D, C, 8, and, A. Assume PS=I and CLR=1, so you have no need show the PS. and CLR inputs of the J-K flip-flops. vee, Ll ale | re re e 4.2. Draw a logic symbol diagram for a mod-12 counter. Add a two- © input NAND gate to the mod-16 counter in Question 4.1, an the CLR inputs of the J-K flip-flops. wet t 3 oH aeQuestion No.S 55] 5.1. In Figure 2, list the 74194 shift register’s mode of operation during ‘each of the five clock pulse. Mode of sperete” mr pematiel (oot) Sozl | S12! Stig IG semt | 5 yr fepte $078 ae! et oe Ta toht got . 5.2. List the contents of the register in Figure 2 after each of the five clock pulses (4 = left bit, D= right bit) ovr woieatons pus poise 0000 ° : b fee pete & nee ° ¢ wine © to sua epee TTL TN, er] 2h 2 eb \121 90ST soasy ae 7LELIA as e109 cit putse Taeaieael 5S, oe ase f ol Hetil feu oth ol oT Lop 1 See aghr pwse © n 0 afer pune eeu Question No.s 6.1. Simplify the Boolean expression using a Karnaugh Y=A-B-C-D-E-F+A-B-C-D- EF $AB-C:D-ESF+A-B: $A-B-C-D-E-F+A-B-C-D- ‘A-B-C-D-E-F+A-B-C- noece, + * Y,2 60caee _ Ae race ee, ep cee Ey 0 ee Sued EF “Jolele| | elegy oa] d Ya 2 ag COEF ° 5 <-- 0 |e ; * ool oD Yue nae 4oacece VO 9 8) — Ww ioly (ole 4 Foo ol © ° 0 —T wot le woe Sot AOD eile le le | ovele | > |» viel? |e 18 ppl o |? L+—+-——_ OSE e sam eS Fs BTCHSL TOE +OBCD F a = (GE rade cber +Gavnd )eSEF 4 O9e Ye cher + GOs) cS eet OBEree erry coy Question No.7 nates [221 missing word or words in each statement. » multivibrator produces a string Fill in the blank with 7.1 Anastable, or of digital signals. 7.2. The circuit wired in Figure 3 is classed as a(n) _4."6/a/# multivibrator. at x em Question No.t [34 1.1 Draw a two-input XNOR gate using two-input NAND gates only. —_— ° see e Question No.2 [28,25 2.5] 2.1 Draw the wiring diagram for a D flip-flop. Four NAND gates and ‘one NOT gate form a D flip-flop. Show your inputs CLK pulses, and D input, Also show two outputs Q and Q. a, 7 2.2. List the mode of operation of the 7476 J-K flip-flop for each input pulse shown in Figure 1. nous sek (Or pres) ee ae monronoe pe MSE omy se be reek ce tool? ek CH cust) ise ee «no ¥ pene he ong pouscer stogel?23. List the binary outputs at the normal output (Q) of the 7476 J-K flip-flop for each of the pulses shown in the following figure. TLepT ta eof ieee aac Figure | ae wee | pee b 20 poe e >! ek 30 ro : wee re 3.2 Subtract the following 4-bit 2s complement numbers. Give each difference as a 4-bit 2s complement number. Also give each difference asa signed decimal number. a. 0100-0110= b. 0010-1100 = ©. 0011 1110= i a geo oe “we © ve 4000 ° ° m@ owe wows TiO ou =1 010 a Zoo! aan —. = 10°F a = o0le 7 ON 2-10 ach Question No 14,4] 4.1 Draw a logic symbol diagram for a 4-bit ripple down counter. Use four J-K flip-flops in this 4-bit down counter. Show your inputs CLK palses, PS input, and four output indicators labeled D, C, B. and A. Assume CLR=1, so you have no need to show the CLR inputs ofthe J-K flip-flops. @.° al ero ool por! = 18? a 70} -s be 7 ~ ae of Lb ee_} | b . é cv a ae awe Ue ow 5 ooo! ©, oie! 4 ole orl? ~ 9100! = 101? 5-194.2. Draw a logic symbol diagram for a 4-bit counter with self-stopping, feature. Add a four-input OR gate to the 4-bit down counter in. Question 4.1 Question No.5 15,51 5.1 In Figure 2, list the 74194 shift register’s mode of operation during «each of the five clock pulse. 5.2 List the contents of the register in Figure 2 after each of the five ‘lock pulses (4 = left bit, D = right bit). al mr pase r 0002 : poise 160 O eens 5 WSC mot reer lat r AAP pee D ot T 1 1 Lo pee rit TeoQuestion No.6 6.1. Simplify the Boolean expression Y = ASBSCSDERER + 4 4 ee eee 4 4 A-B-C-D-E-F+A-B-C-D-E-F ae he Foo of no ood ve oon oo oo o fo |e eet of} ef 7] 2 eo} of of o [Ff eto} ol} 2 li) lopped «foto tn ref fof of (ce Ameer ° B+ Anner l,2 BEDEF Tre oreo + a 2b w ve otiee ef nw eee of nw oe} of ofe fe oo efofeol ef]! 1 ) " of of > ’ " 1 Py ols to fo 10 ee Adper us ee er Yeo Yet Yst Ta fe ~ eee 2D Dr ree+ Feces 4bmoek 408" ba cet £ cc ew + (ome) OF 2 (BEr0n ref + dace ¢ 2 peF +8oc34 Ore Question No.7 12,2] Pine lnk with he missing won or worn ech attement TAA Refer to Figure 3. The bistable multivibrator is also called a fip- flop or_fat ch. JHicH Bisiable multvibrator sv72 Refer to Figure 4 The astblé multvibratoris lo called aa) free Tp ning pt! br od ‘Aswble | OUTPUT, Latins sv, T Figure 4 Question No.1 [15,1.5,15,4] 1-1 Convert the binary number in tof to hexadecimal numbers =i b 1101 100011 4. 1010110 e. 10000001 5 jov0000! 2 6/ 2. 2 (#6), — £ iomon po © 1eyeng 2 (een OE " ~ om © en oO ® 00D & m8 @ sien 9 (ae) nae 2 1.2. Convert the hexadecimal number in a to f to decimal numbers. 67 a E an b. 10 4 e 7c + @. AO tm ov 6% , ac vane 2 ow € ov. @ ce By writer? 2-64 a a eet 4.28 Aue tw ° °Y “ awe 2 ° 312 revel ane - 90 + 2 ise © Dent1.3 Convert the signed decimal numbers in a to f to 4-bit 2s complement form. ;—> 0001 a 47 5 0m oun b. +4 5 0100 $1 opi e 3 tre! 4 3 he 5s on! & 5S 4 yn fort f 6s jee! sere 1.4 Base 6 system is called ‘Senary number system’. Write the decimal numbers from 0 to 15 in senary. 6L > 3 os 0 —» © Le rg cht U ’ 1? o bye pe “4 te = s—— 3 ’ 1s Question No.2 11,3,3,2,3] 2.1 Draw both standard and special symbols of a two-input NOR gate. ro sy enemat eee ee >- D- 2.2. Write the minterm Boolean expression that would describe Table 1. Do not simplify the Boolean expression. - SS oon 23. Simply the Bolen expression in Quen 22 by the use ofa Sin he 8 ce 24 Drow she chet fo he singled Bolen expression ia Soet Question 2.3 (use AND, OR, and NOT gates). 2.5. Redraw the logic eireut in Question 2.4 using only cight two-input z NAND gates.Question No 12,11, 125, 1.78 | 3.1 Draw a block diagram of a three-bit parallel addersubtractor (ase pee three full adders, three XOR gates, and one AND gate). a ora, Pe ea ans tos 32 Draw the logic symbol for a D flipsop with PS and CLR asynchronous inputs, Make clear positive-edge tiggering or negatve-edge trigaering i our erent _— Namek Zr para iv Bes aft con FF cue © | —~ com premerry 3.3 Draw the logic symbol for a J-K flip-flop with PS and CLR asynchronous inputs. Make clear positive-edge triggering or nevative-edee triggering. reset ——7 oti od 1S 8 so nf ape one ob> FF secestpenin [Rae || OS é Come] one 7s ce jak 0 | @@ em ‘smiveree [PX ited [oe Px x Ta —_——_] on sisson . Coe Tea saan | feLaroi [cain 3.4 Draw the truth table for a D flip-flop with PS and CLR asynchronous inputs. i nemeniny ) Dyn chwonee pecs gape | Ay woes ~ eo jew a ayn chin ee ° 1 y hroben Org Chromeo, t ° a v Prd baht oO ° x v 7 see i ! ij o Oo t rene 1 v es3.5 Draw the truth table for a J-K flip-flop with PS and CLR asynchronous inputs. pe . seyn ono pr he em moo ve m cm ||? te \ Ss e ’ Kg x | i o Regn Orewa sek oO K 1 ppp venee 1 ° It AL « x| ° = pene Lal al | x| oO hott 1. | pore ee Tg5le Question No.4 [1.5,1,1.5,1.5] 4.1. List the binary output B and A for each of the six input pulses shown in Figure I. Assume PS=1 Figure 1 Page 4 of 10 Z a Pn > euse a o ° qetse 14 psec 1, 0 at ° \ pose ° posse’ ° peek 4.2 How man clock pulses are necessary to clear the 74194 shift register? “ ingle clade prise 1 ng clear ma 2usat gript TOgIOKe 259 ~ °as In Figure 2, list the 74194 shift register’s mode of operation during cach of the five clock pulses. ete OF epee peau wot | Soa | se? a1 | se? nit 7" Sos! wp lt wee Pe Pair cece Ven’ 44 List the contents of the register in Figure 2 after each of the six clock pulses (4 = left bit, D = right bit). ovrpuriypicators | Paral it TL Tey > Sih 9, se oo TL FT Lan Seah] sign Question No.5 [ 1.25, 2, 1.25, 15,2] 5.1 Give a descriptive name for the following ICs: a. TAHCOO —? quact 0 -/nout WN b. 741802. —P quad Tee i pe wor gee €. T4ALSOB —? Jun/ #22 tpt wv Oe d. 74832. 3 quad foo inpur of 6 ACR nd Ae ngit vod OME wD gore 5.2 Figure 3 shows input and output voltage levels from the 74HCO0 series. How much are the noise margins of HIGH and LOW for the TAHICOO series, respectively? pores mang” of gee) 4-73 ee oe sv " ov sv . eagn of T vnc nore meng! sav nich? aay 2 asv aavp pay Undefined Undefined aavp pew ay Ww tow. atv low \ GND ow GND ow 2 [0 ory 4 ov yrigwe a 5.3 Table 2 shows output drive and input loading characteristics for selected TTL and CMOS logic families. Referring to Table 2, calculate the fan-out when interfacing standard TTL series to TAALS series. Table 2 Device Family ‘Output Drive | Tnput Loading Standard TTL Series | Ton = 400 pA TALS Series T4ALS Series TTL 4000 Series T4HC00 Series Mos om Laneut = 5.4" List three important characteristics of semiconductor memory. D mer Vol osilshY DL) kardom aot D seatibirty 5.5 What are the functions of Multiplexer (MUX) and Demultiplexer (DEMUX)? : ee el pemestigient | ve signal sere ction & signee aise bin Darn roneing * — Date Seqerotm . — padre, He codtt SC Dae Crp anion padrexs 9Question No.6 [1.5,1.5, 1.5, 1.5, 15, 1.5] Fill in the blank with the missing word or words in each statement. 6.1 Refer to Figure 4. The bistable multivibrator is also called a flip- flop or_/**0# Guict OUTPUT ;, — t Bistable sv \ multivibrator T Spi Figure 4 6.2. Refer to Figure 5. The astable multivibrator is also called a(n) free cunning munity ober =. 45V H multivibrator Sv = 7 Figure 5 6.3. Refer to Figure 6, If the binary input to the D/A converter is 0111, the analog output will be |“ volts. ot bz azce! Kye 1s0kt Bree tee “e ee okra 0+ 4 oe ays vot - ovr6.4. Refer to Figure 6. If the binary input increases from 0001 to 0011, the analog output will increase by 6.4 volts. DIGITAL INPUT (8) 4s) 28) (Is) ANALOG DBC BA OUTPUT Summing amplifier Resistor network, Figure 6 ~. oooh act pve KE, TORE 0-e6be. Bo kr “gir Ts0K Lo Rens 150 1e® we vee s ayeure yo Osee™ > ond > ool aye #EL = poke Oh - 2 ask® wen One ee vow" 9 kere a - 2 ov ee ok + Er oe < crete 1 78 a ; zi 2 0-6-0 aot) 6.5. Refer to Figure 7. If the analog input voltage is 1.3 V, the binary output will be O10. Veep e304 see we 5 BX Lon 7 a 2 2 pm paw Vref WD te BO Wamper of lapse we ree 2: one + brnany olwpnt6.6 Refer to Figure 7. If the analog input voltage is 2.5 V, the binary output will be (20. BINARY, Vets 3 ouTPUT ve ae a 4 2s is Leese WSF 7 Se @® 2° a4 Dat ANALOG oe AD Neb yshps vin — Wee 1° Converter Te t B 0-3.2V t eee oe = Drs Figure 7 = 1100 piney ove Question Group B Question No.7 12.5,2.5,0.5] 7.1 For 4-to-1 multiplexer, draw the logic diagram, truth table and the logic symbol. Consider inputs as Do, D;, D2 and Ds and select line or conirol line as S; and >. Explain the logie diagram. If you want output as D3 what will be the logic for inputs and control line. os Se be » DL |__| ===) os oe ours Fre) yy, oY > be cjener 19 a selection op sig nat \ ve mmeaiplenet TO ne ope the De & & phere fe oe | tnadne otvet : we have do give atl to Jew and Same ferCups a bz We ar Five ADz-! Gort gre Ty we bound Jnerdn de get oveprt ao by 7.2 Implement following Boolean function 4-to-1 _ multiplexer F(A,B,C) = ¥(1,3,5,6), use A as input line and B and C as selection fine. Draw multiplexer implementation, truth table and implementation table. 4CA a6) 7 Oe So) om seecnen Ine ne! weRie2- D221 = el 2 % Le ~ 4) L_—_—— “Mur hm wh Got 4 © Om ® O°? be & fF a 7.3. How many control line and inputs are required to design 16-to-1 MUX? my corded tines leg 2Crp > dog Lib? 201 spe condo Wire 4. opoil ° Foppry tag 2) Ie. a 16! 1Question No 2511251) 9 9: 2 8.1 Draw the logie diagram and truth tables for 3-of8 decoder’ Explain the logic diagram. What is the only difference from de- mutpene? . Trem eel ft . oe mile \ ww zu Fy i-D—e oo ete opel |e |? Dp -4 cfete fet ° ‘ , ° ° ‘ e ° o =D- 2 pe |) |e | @ r,t (Oo ° ° ” t 1 1 d d | Dew T be Ho som | r—D- mn twee mer eie & caret gS eons wl | » Gm re gen 027, | " oe coctr 16 Bnet ° pt Pn tn mud Kplewe heh aig obgne 3 hp bn decochs 19 hes rwhp £2 Define even and odd parity with examples. Ifyou have binary umber 11100001, what wl be the output from checker? . evra in tan gt Sy Po, ewan poridg 1 F418 ep proceess of Coa wirg Gc el . a I's to oncure Mos Me gsajence fre tote ont hy bed ig ana . a in Pe sequence ef 1101 #9 keep pe seq “S wnpen on emir BY) ntote! Twa s oner j hor ap Coe oles err Ne karte Syste odd party prec fee % _ te ange no Seynem te qegr to be oot an emis 2 rd ” “"™ TeTshs = 1108090! r Illo0o)! Ne eg nays $A: iL)Spy usengee i. fat logic CTP aah Ser A gatn anc my, ge yboregnaet (2% Saquerent 4 Grips bine impor: . relacctes ett Universal Crift ragiles & angye ok SWt! rey mee ie por venatiing op epierasd aright cagister 1s a HIE 8.4. Draw 4-bit SISO shift register. Explain how entry of 4-bit binary number 1011 into the register, beginning with the left most bit. Show the shifting of bit till 5. seri err ae ; 1 Tre Veale resagtes rumen 1? pores Me process har “ ° Jett mo @ sist regsierion smrer~ 1000 C @ sencone n= 6100 ® 4 no ope @> 4m 4 note 200! @® smu n i= 1002 . numbe 10 1) np ue le regishy contr bine 8.5. From Figure 8 what will be the clock frequency if the period of the 1 waveform at C is 16pS. “Wee ow ee be 1 + a rf et pp e , ckann |} } ous 4k 4 Kk a Lk 4 M wp 62.8 uz A 8 é Figure 8ater 9 oe 9.2 Figure 9 is the monostable multivibrator built using 555 timer. Given the frequency, f = 2.4 KHz and C = 0.01uF. What will be the value of Ry if designer want to design with above given information? Figure 9 Page 9 of 10 cr ole pen vee FEE MEME fo =? qe bl kal - be = i. 9.3. Draw 3-bit weighted resistor DAC and derive the output voltage for it. What will be the output voltage if d,djd,-010? What is drawback for this circuit in terms of value of resistors? feriste 07 Aiyyered Valuy @71e Toque we94 Draw 4-bit R-2R ladder DAC and derive output voltage for dydsdpd}~0001 and dyd3d,d,-0010. wm 9.5 How many flip-flops are required to construct a mod-128 counter? What is the largest decimal number that can be stored in a mod-64 counter? 29 2 ant ee phe ler steed (7 larg 4 Cecim et number trod can Pe most-6u counter 16 63