820-1540 (Project Q45A)

8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
SCHEMATIC,MLB,Q45A ("Rous") I 355571 PRODUCTION RELEASED 12/13/04 ?
D
01/21/05 D
PAGE PDF CIRCUIT BLOCK PAGE PDF CIRCUIT BLOCK
1 1 TABLE OF CONTENTS 51 42 EXTERNAL TMDS TRANSMITTER
2 2 SYSTEM BLOCK DIAGRAM 52 43 GPU FRAME BUFFER
3 3 POWER BLOCK DIAGRAM 53 44 FRAME BUFFER TERMINATION
4 4 REVISION HISTORY 54 45 GRAPHICS DDR SDRAM A GRAPHICS
5 5 TABLE ITEMS 55 46 GRAPHICS DDR SDRAM B
6 6 FUNC TEST 56 47 GPU STRAPS
7 7 POWER CONNECTOR / POWER ALIAS 57 48 GPU DAC & CLOCKS
8 8 SIGNAL ALIAS 58 49 GPU DVI & STRAPS
9 9 2.5V VREG 59 50 EXT VGA & TMDS
10 10 1.2V VREG TOP 60 51 U3LITE HYPERTRANSPORT
11 11 3.3V/5V PWRON SWITCHING 62* 52 SHASTA HYPERTRANSPORT
HT
13* 12 SMU 64 53 HYPERTRANSPORT LA CONNECTORS
C 14 13 CPU LOGIC ANALYZER CONNECTOR 73 54 PCI SERIES TERMINATION C
16 14 FAN 1, 2 AND SYSTEM TEMP SENSOR 74* 55 SHASTA PCI
17 15 FAN 3 AND HARD DRIVE TEMP SENSOR 75* 56 BOOT ROM PCI
18 16 I2C CONNECTIONS 76 57 AIRPORT EXTREME
21* 17 INDICATOR LED 77* 58 USB2 PCI
22 18 U3LITE CORE 80* 59 SHASTA DISK
23 19 SHASTA CORE 83 60 DISK CONNECTORS
DISK
24 20 U3LITE MISC 84* 61 SHASTA ETHERNET
25* 21 SHASTA SERIAL 87 62 ETHERNET PHY & CONNECTORS
ETHERNET
26 22 PULSAR POWER 88* 63 SHASTA FIREWIRE
27 23 PULSAR CLOCKS 90 64 FIREWIRE A PHY & CONNECTORS
FIREWIRE
28 24 U3LITE APPLE PI 91* 65 USB HOST INTERFACE
29 25 NEO APPLE PI 92 66 USB DEVICE INTERFACE USB
B 30 26 CPU STRAPS 94 67 MODEM CONNECTOR MODEM B
31 27 NEO POWER & BYPASS PROCESSOR 95* 68 PCM3052 AUDIO CODEC
32 28 CPU BYPASS 96* 69 LINE IN AMP
33 29 CPU VREG 98* 70 LINE OUT AMP
34 30 CPU VREG 100* 71 SPEAKER AMP
AUDIO
35 31 CPU VREG OUTPUT CAPS 101* 72 AUDIO CONNECTORS
36 32 CPU DIODE CONDITIONER 102* 73 AUDIO POWER SUPPLIES
37 33 U3LITE MEMORY 103* 74 S/PDIF TRANSMITTER
38 34 SERIES TERMINATION
40 35 DIMMS MEMORY
44 36 PARALLEL TERMINATION
45 37 PARALLEL TERMINATION DIMENSIONS ARE IN MILLIMETERS
Apple Computer Inc.
METRIC
46 38 VTT VREG XX
A 48 39 U3LITE AGP X.XX

DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
49 40 GPU AGP GRAPHICS X.XXX
ENG APPD MFG APPD
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
50 41 GRAPHICS VREGS (GPU CORE & 1.5V) ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE
DO NOT SCALE DRAWING
* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC RELEASE SCALE SCH,MLB,IMG5

NONE
SIZE DRAWING NUMBER

MATERIAL/FINISH
NOTED AS D 051-6482 REV.
I
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FREQUENCIES LISTED ARE MAXIMUM DATA TRANSFER RATES SUPPORTED BY U3LITE
U2900
CPU
NEO 10S U1300
U1301
PAGE 29
J5900, J5901
J5902, J5903 SMU RTC
17",20" INVERTER
PAGE 13
TMDS 32-BIT PAGE 13
EXT VGA APPLE PI
D PAGE 59 ELASTIC INTERFACE D
1.2V/900MHZ
J4000
J4001
APPLE PI
MAIN MEMORY
PAGE 28
U5400, U5401
U4900
U3 SERIES
DIMMS PARALLEL
GPU
PAGE 37
64/128-BIT
AGP
FRAME 64-BIT
32-BIT MAIN MEMORY TERM TERM
BUFFER A
FRAME BUFFER
2.6V/540MHZ
8X AGP
PAGE
U3LITE 2.6V/400MHZ
PAGE 38 PAGES 44&45
NV18B/NV34 0.8V/533MHZ
48 CORE
PAGE 54 4X = 1.5V
I/O = 1.5V
PAGE 22
PAGE 49 PAGE 40 J9210/J9220/J9230
MISC HYPERTRANSPORT
PAGE 24 PAGE 60
USB
64-BIT
FRAME BUFFER
CONNECTORS
PAGE 92
2.6V/540MHZ 8-BIT
HYPERTRANSPORT J9400
1.2V/400MHZ To Shasta
MICRODASH MODEM
CONTROL = 2.5V SCCA
U2600 U5500, U5501
CONNECTOR
PULSAR FRAME PAGE 94
POWER CLOCKS BUFFER B I2C J6400

J6401
J9240
BLUETOOTH
C PAGE 26 PAGE 27 PAGE 55
PAGE 18
J6402
1 2 3 4 5
CONNECTOR
C
HT USB PAGE 92
DEBUG PAGE 91
PAGE 64 U7700
U7500 J7600
AIRPORT USB 2.0

BOOTROM EXTREME uPD720101
CONNECTOR PCI
PAGE 75 PAGE 76 PAGE 77
JXXXX
EDUCATION: NOT USED

SATA HYPERTRANSPORT
SATA1
PAGE 74
GOOD,BETTER,BEST: HARD DRIVE CONNECTOR SATA/150
PCI
PAGE 62
1.2V/1.5GHZ
PAGE 80
SATA
PAGE 83 32-bit PCI (5V-3.3V/33MHz)
U2300
J8302
SATA DEV
SATA2
GPIO/PCI64
FOR DEVELOPMENT ONLY
CONNECTOR SATA/150
SHASTA
PAGE 25
1.2V/1.5GHZ
PAGE 83
J8301
PAGE 80
UATA
J9401
B EDUCATION: HARD DRIVE UATA UATA/133 CORE NCs CTL-LESS / B
GOOD,BETTER,BEST: OPTICAL
CONNECTOR 3.3V/133MHZ PAGE 23 PAGE 91
SOFT MODEM
PAGE 83 ETHERNET FIREWIRE
I2S CONNECTOR
PAGE 25
PAGE 94
PAGE 84 PAGE 88 SCCA SCCB
I2S0 I2S1 I2S2
1394 OHCI (3.3V/98MHz)
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
8-bit TX/RX
U9500
S/PDIF OPTICAL OUT
J9803
AUDIO CODEC COMBO OUT
CONNECTOR
PCM3052 LINE OUT
PAGE 98
U8700 U9000
AMP LINE OUT
PAGE 95 PAGE 97
10/100 ETHERNET FIREWIRE A
J9801
BCM5221 802A
PAGE 90
SPEAKER
AMP
SPEAKER SYSTEM BLOCK DIAGRAM
A PAGE 87 0 1 LINE IN
AMP
PAGE 97
CONNECTOR
PAGE 98 NOTICE OF PROPRIETARY PROPERTY
A
PAGE 97
4 Diff pairs 2 Diff pairs
J8700 J9000, J9001
J9800 J9802 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ETHERNET FIREWIRE A LINE IN MIC II NOT TO REPRODUCE OR COPY IT
CONNECTOR CONNECTORS CONNECTOR CONNECTOR
PAGE 87 PAGE 90
SIZE DRAWING NUMBER REV.
PAGE 98 PAGE 98
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 2 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SYS_POWERUP_L
SMU
POWER SEQUENCE PIN
PULSAR_POWER_DOWN SMU_PWRSEQ_P1_4 13
MAKE_BASE=TRUE
J700 SYS_POWERUP_L 27 =PULSAR_POWER_DOWN
PAGE 7
POWER CONNECTOR 10
10
TURN_ON_SHASTA_CORE_L
TURN_ON_PP1V2_L
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
13
13
D PP24V_RUN PP12V_RUN PP5V_RUN PP5V_ALL PP3V3_RUN SMU_PWRSEQ_P9_5 13 (PWR_GOOD_SB_CORE) D

FW CONN 20" PANEL POWER HDD & OPTICAL PCI BUS SMU_PWRSEQ_P9_6 13 (PWR_GOOD_PP2V5)
20" LCD INVERTER 20" LCD INVERTER AUDIO CODEC
SMU_PWRSEQ_P1_2 13 (TURN_ON_VTT)
5V
PP3V3_ALL
PP3V3_ALL
LINEAR
PAGE 11
1
R331
10K
FW PHY 5%
3.3V SMU
1/16W
MF
2 402
PWR_GOOD_SB_CORE
=PP5V_RUN_CPU 6 7 8 31
PP5V_RUN_AUDIO CPU CORE PP2V5_RUN_CPU_AVDD PP5V_PWRON PP3V3_PWRON PP1V2_SHASTA_CORE

C LINEAR SWITCHER
ALIAS
CPU_AVDD_EN 31
LINEAR FET SWITCH FET SWITCH
GPU CORE
SWITCHER IN C
PAGE 31 PAGE 11 PAGE 11 PAGE 10 IRU3037ACS
SC2643VX*1
PAGE 99
PAGE 33 SC1211*4
2.8V CPU AVDD
5V USB CONN
3.3V ENET PHY SWITCHER 1.2V SHASTA CORE
5V HP/LINEOUT AMP
0.8~1.2V GPUL
UDASH MODEM USB2 HOST
PAGE 50 IRU3037CS
MODEM & BT
1.6/1.4V NV18B/NV34 3
11 RAIL_CTL_NEG 8 LM339A
V+ SOI
10 6 PPVCORE_PWRON_SB 14
R330 U1100
PP4V5_RUN_AUDIO 1
100K 2 COMPARE_SB_CORE 9 GND
LINEAR U3LITE CORE PP2V5_PWRON IN

5% 12
SWITCHER 1/16W
MF
1 C330
PAGE 99 SWITCHER 402 0.01UF
20%
16V
IRU3037CS IRU3037CS
4.5V AUDIO CODEC
PAGE 22 PAGE 9
SHASTA HT
PP1V2_PWRON PP1V2_RUN 2 CERM
402
1.53V U3LITE CORE 2.62V DDR DIMM FET SWITCH IN FET SWITCH IN
PP2V5_PWRON
PAGE 10 PAGE 10
IN
PWRON_SD HT BUS
PWRON_DISK_SB API BUS
PP2V5_RUN PP1V5_PWRON
FET SWITCH LINEAR PP5V_ALL
PAGE 9 PAGE 50 PP3V3_ALL
RAM TERM
1.5V PULSAR CORE 1
R342
B GRAPHIC FB
5%
150K 1
R341
B
1/16W
MF 10K
2 402 3
5%
1/16W
6 LM339A MF
PS_2V_REF 2 402
PP1V25_RAM_VTT PP1V5_RUN V+ SOI

1
R340 U1100 PWR_GOOD_PP2V5
LINEAR IN
POWER SW 1
100K 2
COMPARE_PP2V5 7 GND
PAGE 50 5% 12
PAGE 46 1/16W
MF 1 C340
1.25V RAM VTT
AGP BUS 402
0.01UF
1
R343
20%
16V 100K
2 CERM 5%
402 1/16W
MF
2 402
46 TURN_ON_VTT
POWER BLOCK DIAGRAM

A NOTICE OF PROPRIETARY PROPERTY
A
II NOT TO REPRODUCE OR COPY IT
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 3 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DATE DESCRIPTION
02/27/04 EVT3 RELEASE (REV 20) 05/06/04 DVT RELEASE (REV 24) 07/15/04 U3LITE PWR SEQ - CHANGED C915 TO 0.22UF
P/S TEMP SENSOR - NOSTUFF
03/05/04 GPU XTAL - C5700 AND C5719 -> 27PF FROM 22PF 05/07/04 TMDS - NEW PARALLEL TERMINATION RESISTORS R5869-R5872
REMOTE HD TEMP SENSOR CONNECTOR - NOSTUFF
I2C A - U1800 MOVED BACK TO PWRON RAIL CHECKIN 24001
PVT / PRODUCTION RELEASE 820-1540:A (SCH 051-6482 REV A)
HEATSINK ASSEMBLY - NEW PART NUMBERS
05/10/04 FRAME BUFFER CLOCKS - ADDED DIFF PAIR PROPERTIES
FAN 3 - STUFFING ON ALL CONFIGS 07/28/04 STUFFED TMDS CONNECTOR J5902 (ACCIDENTALLY OMITTED)
PCI_RESET - UPDATES FOR SCHEMATIC REUSE
FIREWIRE POWER DU JOUR FIREWIRE CRYSTAL - CHANGED R9061 TO 470 OHM
MASTER PAGE SYNC - ADDED S/PDIF XMITTER AND BITCLK DELAY
EVT3 - BOM REV 21 RELEASE 2.5V VREG - CHANGED SOFT START CAP TO 0.68UF
D 03/24/04 MASTER PAGE SYNC
CHECKIN 24002
AUDIO UPDATES
NEW P/N FOR HEATSINK ASSEMBLIES D
NOSTUFFED OPTICAL TEMP SENSOR
EVT3 REWORKS CHECKINS 24003-24005
STUFFED REMOTE HD TEMP SENSOR CONNECTOR
NOSTUFF R807 - SMU_BOOT_SCLK IS ALSO CPU_VID<5>
05/11/04 DVT RELEASE (REV 25) BOM RELEASE (REV B)
NOSTUFF R3691 & R828 - DIODE CAL RETURN PATH
MOVED MARTY SERIAL 0 OHM RESISTORS TO COMMON BOM 06/10/04 LAST MINUTE BOM CHANGES FOR DVT: 08/03/04 2.5V VREG - CHANGED SOFT START CAP TO 0.47UF
SMU - ADDED QREQ SUSPENDREQ LEVEL SHIFTER - R2419, R2420 CHANGED TO 330 OHM I/O CONNECTOR SHIELD CHANGE P/N TO 805-5664
GPU - ADDED DECOUPLING TO GPU_VTT FOR NV36 I2C A BUS PULLUPS - R1816,R1817 CHANGED TO 200 OHM NEW CPU P/N AND BINCODES FOR 1.10V VMIN
INVERTER CONTROL - ADDED AND GATES U5850 & U5851 TO CONTROL LCD_PWM AND FPD_PWR_ON USB PULL-DOWNS - R9403,R9404 MOVED TO COMMON BOM BOM RELEASE (REV C)
CHECKIN 21001 SMU CRYSTAL CAPS - C1304,C1305 CHANGED TO 18PF FROM 12PF
08/20/04 TMDS VCC - CHANGED C5918 TO 0.022UF TO LOWER INRUSH CURRENT
SMU RESET - CHANGED R1322 TO 150K FROM 100K
04/12/04 CPU - CHANGED CPU SYMBOL TO NEO-10S-REV2-76C (OLD IS OBSOLETE) POWER SWITCH SW703 - MADE FOXCONN 516S0248 AND SUYIN 516S0249 ALTERNATES
CPU HEATSINK ASSEMBLIES - NEW PART NUMBERS
SCHEMATIC REUSE - NETS THAT NEED ALIASES START WITH = (DOES NOT EFFECT NETLIST) PATA CONNECTOR J8301 - CHANGED TO 516S0264 TO MATCH REVERSED BOSSES ON FAB
TMDS POWER - CHANGED D5914 TO SURFACE MOUNT PART FROM THROUGH HOLE
3PHASE CPU POWER SUPPLY - ADDED TABLE FOR R3328 BOM RELEASE (REV D)
MOVED R714 TO R1303 FOR SCHEMATIC REUSE
INVERTER - ADDED RESISTORS R5860-1 AND CHANGED R5808-9 TO 47OHM
U1600,U1601,U1700 CHANGED TO 353S0890 FOR MORE SOURCES 08/27/04 NOSTUFF SDF700
TMDS POWER - ADDED R5960 AND D5914
MOVED CPU LOGIC ANALYZER RESISTORS TO DEVELOPMENT BOM SW703 - SUYIN WAS REMOVED AS ALTERNATE
DIODE CAL - ADDED OPTION TO POWER FROM PP5V_ALL AND PP3V3_ALL RAILS
CHECKIN 25001 BOM RELEASE (REV E)
CHECKIN 21002
06/11/04 MASTER PAGE SYNC - NOSUFFED EXTERNAL S/PDIF TRANSMITTER 09/14/04 CPU - WAVE5 PROCESSORS ADDED AS ALTERNATES (ARL, BPL, BRL)
04/12/04 MASTER PAGE SYNC - IN SYNC ON ALL PAGES EXCEPT PAGE 13
ADDED TABLES FOR: NEW 1.5V FET - LOWER RDS(ON) - Q5006 CPU P/S CAPS - AIR CHANNEL BY STUFFING C3427, C3332 AND NOSTUFFING C3327, C3428
EMI - REMOVED EMI700 & EMI9400
06/21/04 PATA CONN J8301 CHANGED TO 516S0235 (ADDED VENDOR) SATABR RESET - STUFFED PULLDOWN R2565
QREQ_L HACK - ADDED U2850, C2850, R2850, R2851
NEW SATA CONNECTER SOURCES J8300, J8302 CPU_INT_L - CHANGED R2578 TO 47 OHM TO CURRENT LIMIT
VOLTAGE SENSE FROM 12V - ADDED R3360, R3361
NEW TMDS CONNECTOR W/ BOSS J5902 BOM RELEASE (REV F)
CHECKIN 21003
REMOVED COIN CELL BATTERY AND I/O ALIGNMENT FIXTURE FROM MLB BOM (FATP ITEMS)
09/30/04 CPU - 1.6GHZ 1.20V PROCESSORS ADDED AS ALTERNATES (APA, APL)
04/13/04 MAIN MEMORY DQS PARALLEL TERM - CHANGED TO 100 OHM (LIKE EVT3) NEW BACKUP SMU_RESET CIRCUIT (SAME AS Q78)
REMOTE HD TEMP SENSOR CONN - CHANGED J1701 TO BLACK 518S0193
I/O ALIGNMENT FIXTURE - ADDED 815-8008 TO MLB BOM CHECKIN 25003
KEPT 518S0084 AS ALTERNATE
DIMM CONNECTORS - UPDATED 30 DEGREE SYMBOL
06/22/04 REPLACED Q5006 (FET FOR 1.5V) WITH 376S0254 FW SURGE RESISTORS - CHANGED R9056 & R9002 TO 1.3 OHM 107S0060
C GREEN LED - ADDED KINGBRIGHT AS ALTERNATE
VTT - NO LONGER POWER SEQUENCED - NO STUFFED R4610 AND R4603
FAN OPAMPS - REPLACED U1600 W/ SECOND OPAMP IN U1700
TIED INPUTS IN UNUSED OPAMP IN U1601
BOM RELEASE (REV G) C
HD TEMP SENSOR - STUFFED ON ALL CONFIGS 11/15/04 CPU - ADDED HP PROCESSORS AS ALTERNATES (ANA, BNA)
NOSTUFFED CPU VREG ELECTROLYTIC CAPS C3332, C3427, C3421
SMU PULLUPS CHANGES - R1312 -> 2K; R1311 -> 10K AUDIO GROUND - CHANGED R9813 & R9814 TO 0 OHM
NOSTUFFED R2775/6 (UNUSED CLOCKS)
SDF804 -> ZH804 HD TEMP CONN - REMOVED ALTERNATE CONNECTOR
CHECKIN 25004
CHECKIN 21004 BOM RELEASE (REV H)
06/22/04 "PROPERLY" TERMINATED UNUSED OPAMP IN U1601
04/14/04 RAM PARALLEL TERM - DQ RPAKS CHANGED TO 68 OHM 12/13/04 CPU DECOUPLING - NOSTUFFED EXTRA_C BOM OPTION
06/23/04 BOM RELEASE REV 26
STROBE RESISTORS CHANGED TO 120 OHM U3LITE - ADDED NEW LAMINATE PART AS ALTERNATE
EVT3A RELEASE (REV 22) 06/24/04 "PROPERLY" TERMINATED UNUSED OPAMP IN U2100 BOM RELEASE (REV I)
CHECKIN 22001 - FIXING DIMM SYMBOL R5010 REMOVED TO DECREASE DROOP ON 1.5V RAIL
CHECKIN 22002 - FIXING DIMM SYMBOL AGAIN ADDED CONNECTOR J1701 TO SUPPORT REMOTE HD TEMP SENSOR
CHECKIN 26001
04/21/04 MASTER PAGE SYNC - NOW IN SYNC ON ALL SHAREABLE PAGES
MAIN MEMORY - DQ SERIES TERM CHANGED TO 22 OHM 06/28/04 MASTER PAGE SYNC - PICKED UP AUDIO CHANGES RELATED TO BITCLK
MAIN MEMORY - DQ PARALLEL TERM CHANGED TO 82 OHM CHECKIN 26002
FIREWIRE POWER - NEW CURRENT LIMITING RESISTOR
06/28/04 SUPPORT FOR 2GB DIMMS - SWAPPED PINS 103 & 167 ON DIMM CONNECTOR
NOSTUFFING FIREWIRE PORT POWER "CHOICE A" CIRCUIT
CHECKIN 26003
INPUT VOLTAGE SENSE - CHANGED DIVIDER VALUES
INPUT CURRENT SENSE - CHANGED R3343 TO 0.025 OHM 1% RESISTOR 07/01/04 ADDED SECOND SOURCE VTT REGULATOR (PAGE 46)
CHECKIN 22003 NO STUFF POWER SUPPLY TEMP SENSOR
CHANGED HD TEMP SENSOR CONN J1701 TO 4 PIN
04/21/04 SMU_SUSPENDREQ - STUFFED LEVEL SHIFTER
MASTER PAGE SYNC - AUDIO CHANGES
CPU POWER SUPPLY - NOSTUFFED R3305
CHECKIN 26004
CHANGED R3304 TO 116S1000
CHANGED C3304-7 TO 132S4733 07/02/04 UPDATED LINE AND NECK WIDTH CONSTRAINTS THROUGHOUT SCHEMATIC
EVT3A BOM RELEASE REV 23 NOSTUFFED ON BOARD HD TEMP SENSOR
CHANGED U3LITE CORE TO 1.53V
04/26/04 USB POWER CAPS - NOSTUFFED C9211, C9221, C9231
B PULSAR_POWER_DOWN CONNECTED TO SMU_PWRSEQ_P1_4
FEEDBACK RESISTORS CHANGED TO 603
CHECKIN 26005
B
SW703 CHANGED TO 516S0221
MASTER PAGE SYNC 07/06/04 REMOVED ON BOARD HARD DRIVE TEMP SENSOR
CHECKIN 23001 AUDIO DETECT PULLUPS - CHANGED FROM 47K TO 4.7K
CHANGED AUDIO I2S_BITCLK SERIES RESISTER TO 0 OHM
04/27/04 MASTER PAGE SYNC - AUDIO AND SMU CHANGES
U3LITE FEEDBACK RESISTORS CHANGED TO 0.5% TOLERANCE
SUSPENDACK LEVEL SHIFTER - REPLACED Q2407 AND Q2408 WITH Q2420 SN7002DW
CHECKIN 26006
I2C_CPU_A - ADDED Q1801 TO LEVEL SHIFTER
ADDED POWER SUPPLY TEMP SENSOR 07/08/04 REPLACED MAXIM ANALOG SWITCH U2850 WITH TI ANALOG SWITCH
Q3000 ADDED TO LEVEL SHIFT / INVERT CPU_BYPASS AND CPU_HRESET PERICOM ADDED AS AN ALTERNATE
CURRENT SENSE - CHANGED R3345 FROM 121K TO 73.2K ALL I/O CONNECTORS CHANGED
CHECKIN 23002 POWER CONNECTOR CHANGED
POWER SWITCH CHANGED
04/29/04 QREQ CIRCUITS MOVED TO PWRON RAIL
SMU DOWNLOAD CONNECTOR - PRODUCTION P/N
I2C UPDATE
CPU PART NUMBERS - UPDATED WITH ACTUAL PART NUMBERS
NB_SUSPENDACK_L NOW USED U700 TO LEVEL SHIFT - OLD CIRCUIT REMOVED
CHECKIN 26007
DIMMS - UPDATED TO 25/28 DEGREE CONNECTORS
BOM RELEASE REV 27
MASTER PAGE SYNC
CHECKIN 23003 07/12/04 CPU VREG DROOP - R3327 CHANGED TO 1.5K; R3326 CHANGED TO 301
PULSAR_POWER_DOWN - R2750 CHANGED TO 47 OHM FOR ICT
04/30/04 SOFT MODEM - ADDED DECOUPLING CAPS TO POWER RAIL
AUDIO DETECT PULLUPS - CHANGED BACK TO 47K FROM 4.7K
REMOVED OLD OVERTEMP CIRCUIT
AUDIO MUTE PULLDOWNS R9815 & RA012 - CHANGED FROM 47K TO 4.7K
ADDED DIAG LED
MIC BIAS - NOSTUFFED CA210 TO HELP NOISE FLOOR
MASTER PAGE SYNC
1.5V_RUN FET - ADDED (N/S) C5060 FOR POSSIBLE SOFT-START
CHECKIN 23004
05/03/04 CPU POWER SUPPLY - ON SEMI FETS ONLY

2.5V VREG SOFT START - CHANGED C915 TO 1UF FOR U3L POWER SEQUENCING
MLB CARCODE - CHANGED TO 825-6447 REVISION HISTORY
A ADDED 1.6GHZ CPU PART NUMBER
UPDATED PLATING FOR ZH702
I/O CONNECTOR SYMBOL UPDATES
CHECKIN 27001
NOTICE OF PROPRIETARY PROPERTY
A
CHECKIN 23005
07/13/04 POWER_FAIL_L R DIVIDE - ADJUSTED FOR 2K PULLUP THAT WILL BE IN PVT POWER SUPPLIES
05/05/04 CPU AVDD - ADDED 2.7V BOM OPTION ORIGIN HOLE ZH702 - CHANGED TO 4.15MM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
POWER_FAIL - RESISTOR DIVIDED TO 3.3V CHECKIN 27002
ADDED BOMS OPTIONS FOR ON_SEMI AND VISHAY FETS FOR 3PHASE AND 4PHASE
07/14/04 FIREWIRE CRYSTAL - ADDED R9060 & R9061 II NOT TO REPRODUCE OR COPY IT
CPU PS AVP CHANGES
CHECKIN 27003 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
CPU VREG - ADDED BOM OPTION ’EXTRA_C’ FOR CAPS WE WOULD LIKE TO NOSTUFF
FIREWIRE CRYSTAL R - FIXED REF DES
CHECKIN 23006 SIZE DRAWING NUMBER REV.
ANALOG SWITCH U2850 - ADDED PERICOM & AND MAXIM AS ALTERNATES TO TI
CPU VREG AVP - C3304, C3305, C3306, C3307 CHANGED TO 8.2NF
STUFFED P/S TEMP SENSOR D 051-6482 I
TMDS TERM - STUFFING CHANGES APPLE COMPUTER INC.
NAMED SOME UNNAMED NETS
CHECKIN 23007 SCALE SHT OF
CHECKIN 27004
NONE 4 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSORS ASICS
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM
343S0284 1 IC,U3LITE,V1.1,300MM,PBGA U3
QUALIFIED TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_11_HEAD PART NUMBER
PART # QTY DEVICE PACKAGE DESCRIPTION VALUE VOLT. WATT. TOL. REFERENCE DESIGNATOR(S) BOM OPTION TABLE_ALT_ITEM
TABLE_11_HEAD 343S0282 343S0284 U3 U3L,V1.1,200MM,PBGA
D WAVE3 337S2968
337S2969
1
1
PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD3,1.6G,85C,ARA
PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD3,1.8G,85C,BPA

1.6GHZ
1.8GHZ
1.25V
1.20V
42W
42W
?
?
U2900
U2900
CPU_DD30_1_6GHZ
CPU_DD30_1_8GHZ
TABLE_11_HEAD 343S0321 343S0284 U3 U3L,NEW LAM,200MM
TABLE_ALT_ITEM
D
WAVE3 TABLE_ALT_ITEM
343S0320 343S0284 U3 U3L,NEW LAM,300MM

TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: VOLTAGE
PART NUMBER
TABLE_ALT_ITEM
WAVE3 337S2994 337S2968 CPU_DD30_1_6GHZ U2900 IC,GPUL,DD3,1.6G,APA 1.20V TABLE_5_HEAD
TABLE_ALT_ITEM

WAVE5 337S2995 337S2968 CPU_DD30_1_6GHZ U2900 IC,GPUL,DD3,1.6G,APL 1.20V TABLE_5_ITEM
TABLE_ALT_ITEM
343S0283 1 IC,ASIC,SHASTA,V1.1,PBGA U2300

WAVE5 337S2980 337S2968 CPU_DD30_1_6GHZ U2900 IC,GPUL,DD3,1.6G,ARL 1.25V
TABLE_ALT_ITEM
WAVE5 HP 337S2997 337S2968 CPU_DD30_1_6GHZ U2900 IC,GPUL,DD3,1.6G,ANA 1.20V

TABLE_ALT_ITEM
WAVE3 337S2970 337S2969 CPU_DD30_1_8GHZ U2900 IC,GPUL,DD3,1.8G,BRA 1.25V

TABLE_ALT_ITEM
WAVE5 337S2981 337S2969 CPU_DD30_1_8GHZ U2900 IC,GPUL,DD3,1.8G,BPL 1.20V
WAVE5 337S2982 337S2969 CPU_DD30_1_8GHZ U2900

TABLE_ALT_ITEM
IC,GPUL,DD3,1.8G,BRL
TABLE_ALT_ITEM
1.25V MISC PARTS TABLE_5_HEAD
WAVE5 HP 337S2998 337S2969 CPU_DD30_1_8GHZ U2900 IC,GPUL,DD3,1.8G,BNA 1.20V PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM
062-2082 1 SPEC,VENDOR PACKAGING PROCEDURE VPP1

TABLE_5_ITEM
820-1540 1 PCB,FAB,MLB MLB1

TABLE_5_ITEM
825-6447 1 BARCODE LABEL, MLB, Q45 LBL1

TABLE_5_ITEM
051-6482 1 PCB,SCHEM,MLB SCH1

TABLE_5_ITEM
341T1366 1 IC,FLASH,1MX8,3.3V,90NS U7500

TABLE_5_ITEM
341T1395 1 PURCH ASSY, SMU BIG U1300
C
TABLE_5_ITEM
C NOT QUALIFIED
CRITICAL 603-6015
CRITICAL 603-6016
1
1
HEAT SINK ASSEMBLY 17 IN
HEAT SINK ASSEMBLY 20 IN

MECH17
MECH20
17_INCH_LCD
20_INCH_LCD
TABLE_5_ITEM
TABLE_11_HEAD
PART # QTY DEVICE PACKAGE DESCRIPTION VALUE VOLT. WATT. TOL. REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_11_HEAD
337S2865 1 PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD2.11,1.8GHZ,85C 1.8GHZ 1.45V 45W ? U2900 CPU_DD211_1_8GHZ

TABLE_11_HEAD
337S2866 1 PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD2.11,2.0GHZ,85C 2.0GHZ 1.45V 45W ? U2900 CPU_DD211_2_0GHZ

TABLE_11_HEAD
337S2787 1 PROCESSOR CBGA-576-1MM IC,GPUL,10S,REV3,2.0G,85C,CJA 2.0GHZ 1.25V 45W ? U2900 CPU_DD30_2_0GHZ ALTERNATES
TABLE_ALT_HEAD

PART NUMBER
LED700,LED702,LED5900 TABLE_ALT_ITEM
378S0119 378S0114 KINGBRIGHT LED
B B
TABLE ITEMS
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 5 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP12V_RUN PP5V_RUN PP24V_RUN
NO_TEST=YES TP_BUF_RST 57 I434 NO_TEST=YES TP_RAM_CKE_R<3> 8 90 IN FW_VP_PORT1 FUNC_TEST=YES PP12V_RUN 10 TEST POINTS
FUNC_TEST=YES
PP5V_ALL PP3V3_RUN
IN
NO_TEST=YES TP_DFPCLK 58 I433 NO_TEST=YES TP_RAM_CKE_R<6> 8 90 IN FW_TPO1P FUNC_TEST=YES
5 TEST POINTS
I3 NO_TEST=YES TP_DFPCLK_L 58 I436 NO_TEST=YES TP_RAM_CKE_R<7> 8 90 IN FW_TPO1N FUNC_TEST=YES 11 7 IN PP5V_ALL FUNC_TEST=YES
I4 NO_TEST=YES TP_DFPD0 58 I435 NO_TEST=YES TP_RAM_CS_L_R<10> 8 90 IN FW_TPI1P FUNC_TEST=YES 18 11 PP5V_RUN 5 TEST POINTS
FUNC_TEST=YES
IN
I5 NO_TEST=YES TP_DFPD1 58 I437 NO_TEST=YES TP_RAM_CS_L_R<11> 8 90 IN FW_TPI1N FUNC_TEST=YES
5 TEST POINTS
I6 NO_TEST=YES TP_DFPD2 58 I439 NO_TEST=YES TP_RAM_CS_L_R<2> 8 90 IN FW_VP_PORT2 FUNC_TEST=YES 18 11 IN PP3V3_RUN FUNC_TEST=YES
I7 NO_TEST=YES TP_DFPD3 58 I438 NO_TEST=YES TP_RAM_CS_L_R<3> 8 90 IN FW_TPO2P FUNC_TEST=YES PP24V_RUN 5 TEST POINTS
FUNC_TEST=YES
IN
I8 NO_TEST=YES TP_DFPD5 58 I440 NO_TEST=YES TP_RAM_MUXEN0 8 90 IN FW_TPO2N FUNC_TEST=YES
I9 NO_TEST=YES TP_DFPD6 58 I441 NO_TEST=YES TP_RAM_MUXEN4 8 90 IN FW_TPI2P FUNC_TEST=YES 83 7 =PP5V_DISK 5 TEST POINTS
FUNC_TEST=YES
IN
I10 NO_TEST=YES TP_EXT_TMDS_CKM 58 I442 NO_TEST=YES TP_NB_PM_SLEEP0 24 90 IN FW_TPI2N FUNC_TEST=YES
5 TEST POINTS
NO_TEST=YES TP_EXT_TMDS_CKP NO_TEST=YES TP_J4000_SJRESET_L FW_VGND FUNC_TEST=YES =PP12V_DISK FUNC_TEST=YES
D
I295
I296 NO_TEST=YES TP_EXT_TMDS_D0M
58
58
I444
I443 NO_TEST=YES TP_J4001_SJRESET_L
40
40
90 IN 83 7 IN
12 TEST POINTS
D
I297 NO_TEST=YES TP_EXT_TMDS_D0P 58 I445 NO_TEST=YES TP_CMP_SPARE 77 76 75 74 73 IN PCI_AD<31..0> FUNC_TEST=TRUE IN GND FUNC_TEST=YES
I298 NO_TEST=YES TP_EXT_TMDS_D1M 58 I446 NO_TEST=YES TP_ENET_TXD<6> 87 77 76 74 73 IN PCI_CBE_L<3..0> FUNC_TEST=TRUE
I300 NO_TEST=YES TP_EXT_TMDS_D1P 58 I781 NO_TEST=YES U2100_UNUSED 21 8 IN PCI_CLK33M_AIRPORT FUNC_TEST=YES
I299 NO_TEST=YES TP_EXT_TMDS_D2M 58 I809 NO_TEST=YES PLS_CLK_66M_0_R 27 76 74 IN PCI_SLOTA_REQ_L FUNC_TEST=YES
I302 NO_TEST=YES TP_EXT_TMDS_D2P 58 I810 NO_TEST=YES PLS_CLK_66M_1_R 27 76 74 IN PCI_SLOTA_GNT_L FUNC_TEST=YES
76 25 IN PCI_SLOTA_INT_L FUNC_TEST=YES PP2V5_RUN PP5V_PWRON PP1V2_PWRON
I307 NO_TEST=YES TP_FBBCS1_L 52 74 58 51 8 IN PCI_RESET_L FUNC_TEST=YES
I311 NO_TEST=YES TP_GPU_INTB_L 49 77 76 74 73 IN PCI_FRAME_L FUNC_TEST=YES PP1V5_RUN PP3V3_PWRON
I314 NO_TEST=YES TP_GPU_THERMA 58 77 76 74 73 IN PCI_TRDY_L FUNC_TEST=YES IN PP2V5_RUN FUNC_TEST=YES
I315 NO_TEST=YES TP_GPU_THERMC 58 77 76 74 73 IN PCI_IRDY_L FUNC_TEST=YES IN PP1V5_RUN FUNC_TEST=YES
I316 NO_TEST=YES TP_IFP1VREF 58 77 76 74 73 IN PCI_STOP_L FUNC_TEST=YES 18 11 IN PP5V_PWRON FUNC_TEST=YES
I317 NO_TEST=YES TP_NVAGP_TDO 49 77 76 74 73 IN PCI_DEVSEL_L FUNC_TEST=YES 27 18 11 IN PP3V3_PWRON FUNC_TEST=YES
GENZ SHOULD USE J1400 FOR THE FOLLOWING NETS:
77 76 74 73 IN PCI_PAR FUNC_TEST=YES IN PP1V2_PWRON FUNC_TEST=YES
I320 NO_TEST=YES TP_TMDS_TXD3M 58
NO_TEST=TRUE EI_CPU_TO_NB_AD<0..43> 14 28 29
76 IN PCI_SLOTA_IDSEL FUNC_TEST=YES 10 3 IN PPVCORE_PWRON_SB FUNC_TEST=YES
I319 NO_TEST=YES TP_TMDS_TXD3P 58
I782
EI_CPU_TO_NB_CLK_N
76 75 74 IN ROM_CS_L FUNC_TEST=YES 13 8 7 IN =PP3V3_ALL_SMU FUNC_TEST=TRUE
NO_TEST=YES 14 28 29
I322 NO_TEST=YES TP_TMDS_TXD7M 58
I784
NO_TEST=YES EI_CPU_TO_NB_CLK_P 14 28 29
76 75 74 IN ROM_OE_L FUNC_TEST=YES 31 8 7 3 IN =PP5V_RUN_CPU FUNC_TEST=YES
I323 NO_TEST=YES TP_TMDS_TXD7P 58
I785
NO_TEST=TRUE EI_CPU_TO_NB_SR_N<0..1> 14 28 29
76 75 74 IN ROM_WE_L FUNC_TEST=YES 22 7 IN PPVCORE_NB FUNC_TEST=YES
I321 NO_TEST=YES TP_VIPHCLK 57
I786
NO_TEST=TRUE EI_CPU_TO_NB_SR_P<0..1> 14 28 29
76 75 IN ROM_ONBOARD_CS_L FUNC_TEST=YES 35 34 33 7 IN PPVCORE_CPU FUNC_TEST=YES
I336 NO_TEST=YES TP_FRWRLPS 58
I787
NO_TEST=TRUE EI_NB_TO_CPU_AD<0..43> 14 28 29
76 IN AIRPORT_CLKRUN_L_PD FUNC_TEST=YES 34 33 IN PP12V_CPU FUNC_TEST=YES
I337 NO_TEST=YES TP_AGP_MB_AGP8X_DET_L 48
I789
EI_NB_TO_CPU_CLK_N
33 IN VCORE_SENSE_GND FUNC_TEST=YES
I338 NO_TEST=YES TP_ATTENTION 29
I788
NO_TEST=YES EI_NB_TO_CPU_CLK_P 14 28 29
92 IN USB_BT_N FUNC_TEST=YES 33 IN VCORE_SENSE_VOUT FUNC_TEST=YES
I340 NO_TEST=YES TP_ENET_CLK125M_GTX 87
I790
NO_TEST=TRUE EI_NB_TO_CPU_SR_N<0..1> 14 28 29
92 IN USB_BT_P FUNC_TEST=YES 8 7 IN SMU_MANUAL_RESET_L 2 TEST POINTS FUNC_TEST=YES
I339 NO_TEST=YES TP_ENET_TXD<7> 87
I792
EI_NB_TO_CPU_SR_P<0..1>
13 7 IN SYS_POWER_BUTTON_L 2 TEST POINTS FUNC_TEST=YES
NO_TEST=TRUE 14 28 29
I791
NO_TEST=YES CHKSTOP_L 8 14 29
92 IN USB2_PORT1_N_F FUNC_TEST=YES 7 IN POWER_BUTTON_L FUNC_TEST=YES
I793
NO_TEST=YES CPU_HRESET_L 14 29 30
92 IN USB2_PORT1_P_F FUNC_TEST=YES 7 IN RESET_BUTTON_L FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES
C
I794
C I341
I344
NO_TEST=YES
NO_TEST=YES
TP_FW_CLK98M_LCLK
TP_AFN
90
29
I795 NO_TEST=YES
NO_TEST=YES
CPU_INT_L
CPU1_HTBEN
14 25 29 30
14
92
92
IN
IN
USB2_PORT2_N_F
USB2_PORT2_P_F FUNC_TEST=YES
13 8
33 13 11 10 7
IN
IN
SMU_RESET_L
SYS_POWERUP_L FUNC_TEST=YES
I345 NO_TEST=YES TP_PSRO1 29
I796
NO_TEST=YES EI_CPU1_CLK_N 14 27
92 IN USB2_PORT3_N_F FUNC_TEST=YES 50 46 11 10 9 8 IN SYS_SLEEP FUNC_TEST=YES
I346 NO_TEST=YES TP_PSRO2 29
I797
NO_TEST=YES EI_CPU1_CLK_P 14 27
92 IN USB2_PORT3_P_F FUNC_TEST=YES 13 8 IN SYS_POWERFAIL_L FUNC_TEST=YES
I347 NO_TEST=YES TP_PSYNCOUT 29
I798
NO_TEST=YES EI_QACK_L 14 28 29
92 IN PP5V_USB2_PORT1_F FUNC_TEST=YES IN EXT_POWER_BUTTON_L FUNC_TEST=TRUE
I348 NO_TEST=YES TP_USB2_PWREN<2> 92
I799
EI_QREQ_L
92 IN PP5V_USB2_PORT2_F FUNC_TEST=YES 9 IN U900_FEEDBACK FUNC_TEST=YES
NO_TEST=YES 14 28 29 30
I800
NO_TEST=YES EI_SE 14 28 29 30
92 IN PP5V_USB2_PORT3_F FUNC_TEST=YES 22 IN U2200_FEEDBACK FUNC_TEST=YES
I801
NO_TEST=YES I2C_SMU_A_SCL_OUT_L 13 14 18
59 57 IN ANALOG_RED FUNC_TEST=YES
I802
I2C_SMU_A_SDA_OUT_L
94 76 25 IN I2S1_DEV_TO_SB_DTI 2 TEST POINTS FUNC_TEST=YES 59 57 IN ANALOG_GRN FUNC_TEST=YES
I354 NO_TEST=YES TP_NEC_AMC 77
I803
NO_TEST=YES MCP_L 14 29
94 25 IN I2S1_SYNC 2 TEST POINTS FUNC_TEST=YES 59 57 IN ANALOG_BLU FUNC_TEST=YES
I355 NO_TEST=YES TP_NEC_NANDTEST 77
I804
NO_TEST=YES RI_L 14 29 30
94 25 IN I2S1_BITCLK 2 TEST POINTS FUNC_TEST=YES IN AUDIO_LI_DETECT_L FUNC_TEST=TRUE
I356 NO_TEST=YES TP_NEC_NTEST1 77
I805
SYNCENABLE
94 76 25 IN I2S1_MCLK 2 TEST POINTS FUNC_TEST=YES 101 25 IN AUDIO_LO_DET_L FUNC_TEST=YES
I357 NO_TEST=YES TP_NEC_SMC 77
I806
NO_TEST=YES TP_PROC_TRIGGER_OUT 14 29
94 76 25 IN I2S1_SB_TO_DEV_DTO 2 TEST POINTS FUNC_TEST=YES 75 IN ROM_WP_L FUNC_TEST=YES
I358 NO_TEST=YES TP_NEC_SMI_L 77
I807
NO_TEST=YES EI_CPU1_SYNC 14 27
94 25 IN I2S1_RESET_L 2 TEST POINTS FUNC_TEST=YES
I360 NO_TEST=YES TP_NEC_SRCLK 77
I808
94 25 IN MODEM_RING2SYS_L 2 TEST POINTS FUNC_TEST=YES 83 80 IN UATA_DD<15..0> FUNC_TEST=TRUE
I359 NO_TEST=YES TP_NEC_SRDATA 77 94 18 IN I2C_UDASH_SDA FUNC_TEST=YES 83 80 IN UATA_DA<2..0> FUNC_TEST=TRUE
I362 NO_TEST=YES TP_NEC_SRMOD 77 94 18 IN I2C_UDASH_SCL FUNC_TEST=YES 83 80 IN UATA_CS0_L FUNC_TEST=YES
I363 NO_TEST=YES TP_NEC_TEB 77 94 IN USB_UDASH_N FUNC_TEST=YES 83 80 IN UATA_CS1_L FUNC_TEST=YES
I361 NO_TEST=YES TP_NEC_TEST 77 94 IN USB_UDASH_P FUNC_TEST=YES 83 80 IN UATA_RESET_L FUNC_TEST=YES
I364 NO_TEST=YES TP_PLS_CLK_66M_0 27 94 25 IN UDASH_SDOWN FUNC_TEST=YES 83 IN UATA_DSTROBE_R FUNC_TEST=YES
I365 NO_TEST=YES TP_PLS_CLK_66M_1 27 94 25 IN UDASH_RESET_L FUNC_TEST=YES 83 80 IN UATA_HSTROBE FUNC_TEST=YES
I372 NO_TEST=YES TP_PLS_REF_CML 27 94 IN UDASH_I2C_A1_PU FUNC_TEST=YES 83 806 6
83 80 IN UATA_STOP FUNC_TEST=YES
I373 NO_TEST=YES TP_PLS_TEST1 27 83 IN UATA_DMARQ_R FUNC_TEST=YES
I371 NO_TEST=YES TP_PLS_TEST2 27 59 IN PPVCC_TMDS FUNC_TEST=YES 83 80 IN UATA_DMACK_L FUNC_TEST=YES
I374 NO_TEST=YES TP_PLS_TEST3 27 59 IN PP3V3_DDC FUNC_TEST=YES 83 IN UATA_INTRQ_R FUNC_TEST=YES
I375 NO_TEST=YES TP_SB_FSTEST 25 59 IN TD0M FUNC_TEST=YES 83 IN UATA_IOCS16_PU FUNC_TEST=YES
NO_TEST=YES TP_SB_PLLTEST TD0P FUNC_TEST=YES UATA_CSEL_PD FUNC_TEST=YES
B I376
I377 NO_TEST=YES TP_VREF_CG
25
48
59
59
IN
IN TD1M FUNC_TEST=YES
83 IN
B
I378 NO_TEST=YES TP_SB_NC_P7 91 59 IN TD1P FUNC_TEST=YES 36 31 IN TDIODE_NEG FUNC_TEST=YES
I380 NO_TEST=YES TP_SB_NC_P8 91 59 IN TD2M FUNC_TEST=YES 76 IN TP_AIRPORT_PME_L FUNC_TEST=YES
I379 NO_TEST=YES TP_SB_NC_R3 91 59 IN TD2P FUNC_TEST=YES 76 IN TP_AIRPORT_RF_DISABLE FUNC_TEST=YES
I382 NO_TEST=YES TP_SB_NC_R4 91 59 IN TCKM FUNC_TEST=YES
I383 NO_TEST=YES TP_SB_NC_R5 91 59 IN TCKP FUNC_TEST=YES
I381 NO_TEST=YES TP_SB_NC_R6 91 59 IN TMDS_DDC_DAT FUNC_TEST=YES
I384 NO_TEST=YES TP_SB_NC_R7 91 59 IN TMDS_DDC_CLK FUNC_TEST=YES
I385 NO_TEST=YES TP_SB_NC_R8 91 59 7 IN GND_CHASSIS_TMDS FUNC_TEST=YES
I386 NO_TEST=YES TP_SB_NC_T1 91
I388 NO_TEST=YES TP_SB_NC_T2 91 59 IN FILT_ANALOG_RED FUNC_TEST=YES

I387 NO_TEST=YES TP_SB_NC_T3 91 59 IN FILT_ANALOG_GRN FUNC_TEST=YES
I390 NO_TEST=YES TP_SB_NC_T4 91 59 IN FILT_ANALOG_BLU FUNC_TEST=YES
I389 NO_TEST=YES TP_SB_NC_T5 91 59 57 56 IN ANALOG_HSYNC_L FUNC_TEST=YES
I391 NO_TEST=YES TP_SB_NC_T6 91 59 57 56 IN ANALOG_VSYNC_L FUNC_TEST=YES
I393 NO_TEST=YES TP_SB_NC_T7 91 59 IN VGA_IIC_CLK FUNC_TEST=YES
I392 NO_TEST=YES TP_SB_NC_T8 91 59 IN VGA_IIC_DAT FUNC_TEST=YES
I395 NO_TEST=YES TP_SB_NC_U1 91 59 58 IN MON_DETECT FUNC_TEST=YES
I394 NO_TEST=YES TP_SB_NC_U2 91 59 IN DDC_VCC_5 FUNC_TEST=YES
I396 NO_TEST=YES TP_SB_NC_U3 91
I398 NO_TEST=YES TP_SB_NC_U4 91 59 IN PP24V_INV FUNC_TEST=YES

I397 NO_TEST=YES TP_SB_NC_U5 91 59 IN GND_20_INV FUNC_TEST=YES
I399 NO_TEST=YES TP_SB_NC_U6 91 59 IN INV_20_LCD_PWM_ FUNC_TEST=YES
I401
I400
NO_TEST=YES
NO_TEST=YES
TP_SB_NC_V1
TP_SB_NC_V2
91
91
59
59
IN
IN
INV_20_CUR_HI_F
PP12V_INV
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC TEST
A I403
I402
NO_TEST=YES
NO_TEST=YES
TP_SB_NC_V3
TP_SB_NC_V4
91
91
59
59
IN
IN
GND_17_INV
PP5V_AGP_RL FUNC_TEST=YES NOTICE OF PROPRIETARY PROPERTY
A
I404 NO_TEST=YES TP_SB_NC_W1 91 59 IN INV_17_LCD_PWM_F FUNC_TEST=YES
I405 NO_TEST=YES TP_SB_NC_W3 91 59 IN LAMP_STS_F FUNC_TEST=YES THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I406 NO_TEST=YES TP_SB_NC_Y1 91 59 IN INV_17_CUR_HI_F FUNC_TEST=YES AGREES TO THE FOLLOWING
I408 NO_TEST=YES TP_SB_NC_Y3 91 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
I407 NO_TEST=YES TP_SATA_CLK25M 27 33 8 IN CPU_VID_R<5..0> FUNC_TEST=TRUE II NOT TO REPRODUCE OR COPY IT
I426 NO_TEST=YES TP_ENET_TCK 87 36 IN KPVDD2_FMAX FUNC_TEST=YES III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I429 NO_TEST=YES TP_USB2_PWREN<0> 92 36 IN KPGND2_FMAX FUNC_TEST=YES
NO_TEST=YES TP_USB2_PWREN<1> TDIODE_POS_FMAX FUNC_TEST=YES
I428
I431 NO_TEST=YES TP_DUMMY_A
92
24
36
36
IN
IN TDIODE_NEG_FMAX FUNC_TEST=YES D 051-6482 I
I430 NO_TEST=YES TP_DUMMY_B 24 36 33 IN CORE_ISNS_M FUNC_TEST=YES APPLE COMPUTER INC.
I432 NO_TEST=YES TP_RAM_CKE_R<2> 8 36 33 IN CORE_ISNS_P FUNC_TEST=YES SCALE
NONE 6SHT
103 OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP12V_RUN PP5V_RUN PP24V_RUN
PP5V_ALL PP3V3_RUN PP12V_RUN PP5V_RUN
PP24V_RUN RUN RAILS
CRITICAL
ONLY ON IN RUN PWRON RAILS ALL RAILS
J700 VOLTAGE=24V =PP24V_GRAPHICS 59 ON IN RUN AND SLEEP ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
HM96110-P2 MIN_LINE_WIDTH=25MIL
F-RT-TH MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE PP5V_PWRON
1 12
2 13 PP12V_RUN
_PP5V_PWRON_USB 92 90 59 11 7 PP3V3_ALL =PP3V3_ALL_SMU 6 8 13
3 14 VOLTAGE=5V MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL _PP5V_PWRON_UDASH 94 VOLTAGE=3.3V
4 15 VOLTAGE=12V MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL =PP3V3_ALL_EI
5 16
=PP12V_AGP 50 59 MAKE_BASE=TRUE =PP5V_PWRON_CPU 36 MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
D 6
7
17
18
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
=PP12V_RUN_CPU
=PP12V_DISK
33
6 83
=PP5V_PWRON_AIRPORT 76 =PP3V3_ALL_CPU 36
D
8 POWER_GOOD 8 19
XW700
SM
PP3V3_PWRON PP5V_ALL
9 20 1 2 PP12V_AUDIO_CODEC 102 =PP3V3_PWRON_SB 23 25 74

10 21 VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL =PPPCI64_PWRON_SB
11 22
XW704
SM
MAKE_BASE=TRUE =PPPCI32_PWRON_SB
23
23
11 6 PP5V_ALL
VOLTAGE=5V
=PP5V_ALL_CPU 36
1 2
ALIAS _PP3V3_PWRON_MODEM 94 MIN_NECK_WIDTH=10MIL
VOLTAGE=0V MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL =PP3V3_PWRON_USB
MIN_NECK_WIDTH=10MIL XW701
SM PP3V3_PWRON_ENET
91
87
P/N 518-0159 1 2 PP12V_AUDIO_SPKRAMP 100 _PP3V3_PWRON_BT 92
PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .
_PP3V3_PWRON_UDASH
XW705
SM =PP3V3_PWRON_CPU
94
36
GND RAILS
PP3V3_ALL 1 2 =PP3V3_PWRON_EI
90 59 11 7 28
XW702
SM
PP5V_RUN PP2V5_PWRON GND_AUDIO 1 2
1 C700 102
CRITICAL 20%
0.1UF VOLTAGE=5V =PP5V_PATA 83 =PP2V5_PWRON_SB 23 25 74 88 XW706
U700 2 10V
CERM
MAKE_BASE=TRUE
=PP5V_DISK 6 83
VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL =PP2V5_PWRON_RAM 26 37 40
1
SM
2
74LCX125 402 MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
14 MIN_NECK_WIDTH=10MIL =PP5V_AGP 49 50 59 MAKE_BASE=TRUE =PP2V5_HT 60 64
33 13 11 10 6 SYS_POWERUP_L 2 3 SYS_POWERUP_L_BUF =PP5V_RUN_CPU 3 6 8 31 =PP2V5_PWRON_HT 62
7
125
1 TSSOP
ALIAS PP5V_AUDIO 101 XW703
SM
=PP5V_RUN_RAM 46
102 100 GND_AUDIO_SPKRAMP 1 2
PP1V5_PWRON
PP3V3_RUN XW707
SM
=PP1V5_PWRON_NB_AVDD 28 37 48 60
VOLTAGE=3.3V MAKE_BASE=TRUE 1 2
=PP3V3_AGP 48 49 50 51 52 56 57 58 59 =PPVCORE_PWRON_PULSAR 26
PP5V_ALL PP3V3_PWRON PP3V3_RUN MIN_LINE_WIDTH=12MIL VOLTAGE=1.5V
MIN_NECK_WIDTH=8MIL PP3V3_AUDIO 95 100 101 102 103 MIN_NECK_WIDTH=10MIL
C
ALIAS
C R710 R700
DEVELOPMENT
MAKE_BASE=TRUE
=PP3V3_RUN_CPU 33
R707
330 330 R701 =PP3V3_PATA 83
2
0 1 PPVCORE_NB CHASSIS GND
1 2 ITS_PLUGGED_IN 1 2 ITS_ALIVE
1
330 2 ITS_RUNNING
=PP3V3_SB_PCI 74
6 22
5%
1/16W
5%
1/16W 5%
=PP3V3_PCI 25 74 75 76 77
5%
1W ZH700
MF 1 MF 1 1/16W DEVELOPMENT =PPVIO_PCI_USB2 77
FF
2512 315R138
603 LED702 603 LED700 MF 1
102 101 GND_CHASSIS_AUDIO_EXTERNAL 1
GREEN GREEN
603 LED701 =PP3V3_DISK 83 MIN_NECK_WIDTH=15MIL
2.0X1.25A 2.0X1.25A GREEN MAKE_BASE=TRUE
2.0X1.25A PP1V2_PWRON
VOLTAGE=0
2 2 MIN_LINE_WIDTH=25MIL
2
PP2V5_RUN
SILKSCREEN:1 SILKSCREEN:2 SILKSCREEN:RUN MAKE_BASE=TRUE
=PP1V2_PWRON_HT 62
VOLTAGE=2.5V MIN_LINE_WIDTH=25MIL 59 GND_CHASSIS_VGA
ALIAS PP2V5_GPU 50 52 54 55 MIN_NECK_WIDTH=10MIL =PP1V2_PWRON_DISK_SB 80
MAKE_BASE=TRUE VOLTAGE=1.2V 92 GND_CHASSIS_USB ALIAS
=PP1V2_PWRON_SB
L700 MIN_LINE_WIDTH=25MIL =PP2V5_RUN_CPU 31
25
90 GND_CHASSIS_FIREWIRE
FERR-EMI-100-OHM MIN_NECK_WIDTH=10MIL
=PP2V5_RUN_RAM
SYS_POWER_BUTTON_L 1 2 SYS_PWR_BTN_FILT CRITICAL
44 45 46
ZH701
13 7 6 315R138
SM SW703 59 6 GND_CHASSIS_TMDS 1
PWR-BUTT PP1V5_RUN MIN_NECK_WIDTH=15MIL
ST-SM3 MIN_LINE_WIDTH=25MIL
VOLTAGE=0
1 C703 1 SILKSCREEN:POWER
=PP1V5_AGP
ZH702
0.1UF 3 VOLTAGE=1.5V
48 49 7R4.15
20% MAKE_BASE=TRUE =PPVCORE_PULSAR 26 87 GND_CHASSIS_RJ45 1
10V 2
2 CERM 516S0248 MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=15MIL
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL
402 FOXCONN VOLTAGE=0 SH700
L701 4 5 GND_CHASSIS_AUDIO_INTERNAL
FERR-EMI-100-OHM 101
MAKE_BASE=TRUE
ALIAS 1 4
1 2 SHLD-IO-CONN
GND_SYS_PWR_BTN_FILT 21 GND_CHASSIS_LED Q45-TH1
2 3
SM
35 34 33 6 PPVCORE_CPU =PPVCORE_CPU 7 29 31 32 36
MAKE_BASE=TRUE
B PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD
ZH703 805-5664
B
PART NUMBER 6.00MM-PTH
59 GND_CHASSIS_17_INCH_INVERTER 1
516S0249 516S0248 SW703 POWER SWITCH - SUYIN MIN_NECK_WIDTH=10MIL
VOLTAGE=0 NOSTUFF
SUYIN WILL NOT BE USED FOR INITIAL RAMP
SDF700
HSK-NUT-6.5MM
TH
R713 GND_CHASSIS_20_INCH_INVERTER 1
SYS_POWER_BUTTON_L 1
1K 2 POWER_BUTTON_L
59
13 7 6 6 MIN_LINE_WIDTH=25MIL
VOLTAGE=0
5% SDF700 IS USED FOR CPU HEATSINK MOUNTING
DEVELOPMENT 1/16W
MF
R712 402
PP1V2_RUN
SYS_RESET_BUTTON_L 1
1K 2 RESET_BUTTON_L
RTC BATTERY
13
5%
DEVELOPMENT
6
EI OVDD POWER OPTIONS VOLTAGE=1.2V ALWAYS ON (TRICKLE)
1/16W
MF
SW701 SW702 MAKE_BASE=TRUE
SPST SPST MIN_LINE_WIDTH=25MIL
402 SM SM MIN_NECK_WIDTH=10MIL CRITICAL
1 2 1 2
1 C705 1 C704
PP1V5_RUN
=PP1V2_HT 24 60 DS700 R702 J702
0.1UF 0.1UF SM BB10209-A5
1K 2
20%
10V
20%
10V
=PP1V2_PULSAR 26 13 =PP3V3_ALL_RTC PP3V3_ALL_RTC 2 1PP3V3_ALL_BATT_SAFETY 1 PP3V3_ALL_BATT 1 2
2 CERM 2 CERM VOLTAGE=3.3V VOLTAGE=3.3V VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL MIN_LINE_WIDTH=25MIL 5% MIN_LINE_WIDTH=25MIL
402 402 NOSTUFF MIN_NECK_WIDTH=10MIL MBR0530 MIN_NECK_WIDTH=10MIL 1/16W MIN_NECK_WIDTH=10MIL TH
3 4 3 4
R7191 R718 R7151
1
R711
1
R716 MAKE_BASE=TRUE MF
402
0 0 0 0 1
0 2 PP1V25_RAM_VTT
5% 5% 5% 5% 44 45 46
RESET POWER =PPVCORE_CPU

1/10W
FF
805 2
1/10W
FF
1/10W
FF
1/10W
FF 5%
1/10W
36 32 31 29 7
2 805 805 2 2 805 FF
POWER CONN / ALIAS

805
NOSTUFF
NOSTUFF NOSTUFF NOSTUFF NOSTUFF R717
R7051 R706 R7081 R709 0
A
1 1
8 6 SMU_MANUAL_RESET_L
0
5% 5%
0 0
5% 5%
0
1
5%
2
A
SW700 1/10W 1/10W 1/10W 1/10W 1/10W
FF
SPST FF
805 2
FF FF FF
805
SM 2 805 805 2 2 805 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 2 R703 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1
0 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% II NOT TO REPRODUCE OR COPY IT
1/10W
FF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
3 4 35 31 30 29 18 14 =PP1V2_EI_CPU PP1V2_EI_CPU 805 PP1V2_EI_NB =PP1V2_EI_NB 14 18 28
VOLTAGE=1.2V VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL MIN_LINE_WIDTH=25MIL SIZE DRAWING NUMBER REV.
MIN_NECK_WIDTH=10MIL R704 MIN_NECK_WIDTH=10MIL
051-6482 I
MAKE_BASE=TRUE
1
0 2
MAKE_BASE=TRUE
APPLE COMPUTER INC.
D
SMU RESET 5% SCALE SHT OF
1/10W
FF
805
NONE 7 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI CLOCKS
TP_NB_THMI ALIAS
NB_THMI 24 PCI_CLK33M_USB2 PCI_CLK_GP0 27
MAKE_BASE=TRUE MAKE_BASE=TRUE
TP_THMO ALIAS NB_THMO 24 =PCI_CLK33M_USB2 77 ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
MAKE_BASE=TRUE
6 TP_RAM_CKE_R<2> ALIAS RAM_CKE_R<2> 37 I246 SMU_RESET 10 MIL SPACING SYS_COLD_RESET_L 13 24
MAKE_BASE=TRUE TP_PCI_CLK_GP1 ALIAS
PCI_CLK_GP1 27
MAKE_BASE=TRUE I247 SMU_RESET 10 MIL SPACING SYS_WARM_RESET_L 8 25 74 77 87
6 TP_RAM_CKE_R<3> ALIAS RAM_CKE_R<3> 37
MAKE_BASE=TRUE 6 PCI_CLK33M_AIRPORT PCI_CLK_P3 27
MAKE_BASE=TRUE
6 TP_RAM_CKE_R<6> ALIAS RAM_CKE_R<6> 37 _PCI_CLK33M_AIRPORT 76
MAKE_BASE=TRUE
6 TP_RAM_CKE_R<7> ALIAS RAM_CKE_R<7> 37 TP_PCI_CLK_P4 ALIAS PCI_CLK_P4 27
6 TP_RAM_MUXEN0 ALIAS RAM_MUXEN0 37 74 27 PCI_CLK33M_SB_EXT ALIAS PCI_CLK_P1 27
MAKE_BASE=TRUE MAKE_BASE=TRUE PP2V5_PWRON
D 6 TP_RAM_MUXEN4 ALIAS RAM_MUXEN4 37 D

6
MAKE_BASE=TRUE
TP_RAM_CS_L_R<2> ALIAS RAM_CS_L_R<2> 37
SMU
MAKE_BASE=TRUE
TP_ALS0_OUT ALS0_OUT 13
1
R870
6 TP_RAM_CS_L_R<3> ALIAS RAM_CS_L_R<3> 37 MAKE_BASE=TRUE
ALIAS
4.7K DEVELOPMENT
MAKE_BASE=TRUE 5%
6 TP_RAM_CS_L_R<10>
MAKE_BASE=TRUE
ALIAS RAM_CS_L_R<10> 37 TP_ALS1_OUT
MAKE_BASE=TRUE
ALIAS ALS1_OUT 13
1/16W
MF U700 J800
2 402 14 74LCX125 U.FL-R_SMT
6 TP_RAM_CS_L_R<11> ALIAS RAM_CS_L_R<11> 37 TP_ALS_GAIN_BOOST ALIAS ALS_GAIN_BOOST 13
9 8 F-ST-SM
MAKE_BASE=TRUE MAKE_BASE=TRUE 13 8 SMU_WARM_RESET_L SYS_WARM_RESET_L 8 25 74 77 87
3
TP_SMU_ONEWIRE SMU_ONEWIRE 13
125
ALIAS
PP5V_ALL MAKE_BASE=TRUE 7 10 TSSOP
24 NB_PMR_OBSV 1
TP_SYS_SLOT_PWR SYS_SLOT_PWR
DIAG LED MAKE_BASE=TRUE ALIAS 13
U700
R850
1 TP_SMU_PWRSEQ_P1_3 ALIAS SMU_PWRSEQ_P1_3 13 14 74LCX125 2
MAKE_BASE=TRUE
180 13 SMU_SLEEP 5 6 SYS_SLEEP 6 9 10 11 46 50
5% TP_SYS_DOOR_AJAR_L ALIAS SYS_DOOR_AJAR_L 13
125 518S0104
1/16W MAKE_BASE=TRUE
MF 7 4 TSSOP
2 402
TP_FAN_PWM8 ALIAS FAN_PWM8 13
MAKE_BASE=TRUE
LED850P1
TP_SYS_DRIVE_BAY_INT_L ALIAS
MAKE_BASE=TRUE
SYS_DRIVE_BAY_INT_L 13 U700
1 14 74LCX125
LED850 13 8 SMU_WARM_RESET_L
MAKE_BASE=TRUE
ALIAS NB_WARM_RESET_L 24
NB_SUSPEND_ACK_L 12 11 NB_SUSPENDACK_L
RED 24 13
SM 125
2 7 13 TSSOP
74 58 51 6 PCI_RESET_L PCI_AIRPORT_RESET_L 76
LED850P2 MAKE_BASE=TRUE
R851 3
GPU_RESET_L
=PCI_ROM_RESET_L
49
75
SMU ANALOG VREF POWER_FAIL_L
13 DIAG_LED 1
1K 2 DIAG_LED_R 1 Q850 =PCI_USB2_RESET_L 77 CONNECTION
MAKE_BASE=TRUE PP3V3_ALL_SMU_AVCC
5% 2N3904 13
PP3V3_ALL
1/16W SM
MF
402
2 PP3V3_RUN DOWNLOAD 7 POWER_GOOD
NOSTUFF
C CONNECTOR NOSTUFF 1
R813 1R812
430 10K
C
R818
1
5% 5%
CPU VID<0:5> PP3V3_ALL
1%
200
1/16W
1/16W
MF
2 402
1/16W
MF
2 402
1
R814 1
R816 1
R817 1
R808 R809
1 1
R804 J802
HC17051
MF
2 402
VID CONTROLLED BY SMU 10K 10K 10K 10K 10K 10K M-ST-TH R826 SYS_POWERFAIL_L 6 13
5% 5% 5% 5% 5% 5% PPVREF_SMU =PPVREF_SMU 13
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 100 MAKE_BASE=TRUE
MF
2 402
MF
2 402
MF
2 402
MF
2 402
MF
2 402
MF
2 402
1 2 J802_2 2 1 SMU_BOOT_BUSY 13 NOSTUFF 1
R860
R819 13 SMU_BOOT_SCLK 3 4 5%
1/16W
SMU_BOOT_RXD 13 C801 1
R802 5%
4.7K POWER_GOOD IS A 5V DRIVEN
0 13 SMU_BOOT_CE 5 6 J802_6 MF (SMU_BOOT_EPM) 2.2UF 0 1/16W SIGNAL FROM POWER SUPPLY
13 CPU_VID<0> 1 2 CPU_VID_R<0> 6 33 402 20% 1 2 PPVREF_SMU_ADC_REF 36 MF
7 8 SMU_MANUAL_RESET_L 10V NOSTUFF
6 7 8
CERM 2 2 402
5%
R820 5%
1
SMU_BOOT_CNVSS 9 10 SMU_BOOT_TXD 805
VR801
1/16W 13 13 1/16W 2K PULLUP INSIDE P/S
MF 0 MF
SSOT-23
2.5V
13 CPU_VID<1> 402 1 2 CPU_VID_R<1> 6 33 402
NOSTUFF NOSTUFF
R821 5%
1/16W R8061 1NOSTUFF
R807
518-0158
R805 1 1
R803 1 C802 AIRPORT CARDGUIDE
0 MF
0.47UF
13 CPU_VID<2> 1 2 402 CPU_VID_R<2> 6 33 10K 10K 0 10K 20% SMT NUTS
5% 5% 5% 5%
2
3
10V
5%
1/16W R822 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
2 CERM
603
MF 0 402 2 2 402 402 2 2 402
13 CPU_VID<3> 402 1 2 CPU_VID_R<3> 6 33
R823 5%
1/16W
GND_SMU_AVSS 13 33 36 SDF890
0 MF STDOFF-6MMOD1MMH-TH SDF891
CPU_VID<4> 1 2 402 CPU_VID_R<4> NOSTUFF
13 6 33
R828 1 STDOFF-6MMOD1MMH-TH
5%
1/16W R824 J802 & R826 CAN MOVE TO DEVELOPMENT BOM POST RAMP
0 1
MF 0 1 2 GND_SMU_AVSS_DAGND 36
13 CPU_VID<5> 402 1 2 CPU_VID_R<5> 6 33
5%
5% 1/16W
1/16W
MF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
PLL LOCK LED CHKSTOP LED MF
402 CPU HEATSINK SMT NUTS
402
R832
1
R831
1
R830
1
R829
1
R827
1 1
R811
BM12B-SRSS-TB
NOSTUFF NOSTUFF NOSTUFF

1K 1K 1K 1K 1K 20K 31 8 7 6 3 =PP5V_RUN_CPU
=PP5V_RUN_CPU
SDF800 SDF801 SDF802
B
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
31 8 7 6 3
B
NOSTUFF
HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM

14
10
11
12
13
J803
MF MF MF MF MF MF
F-ST-SM
1
2
3
4
5
6
7
8
9
2 402 2 402 2 402 2 402 2 402 2 402 TH TH TH

DEVELOPMENT
1
DEVELOPMENT
R837DEVELOPMENT R833
1 HS_SDF800 1 HS_SDF801 1 HS_SDF802 1
180
180 5%
NOTE:PULL UP CPU_VID<5>TO 5%
1/16W Q802 1/16W
MF
2.2V FOR CPU VRM10. MF 2N3906
SM
2
2 402
1 C880 1 C881 1 C882
2 402 0.01UF 0.01UF 0.01UF
Q802_B 1 LED801_1 20% 20% 20%
16V 16V 16V
DEVELOPMENT 2 CERM 2 CERM 2 CERM
1 402 402 402
3 LED801
Q802_E DEVELOPMENT RED NOSTUFF
BACKUP SMU RESET CIRCUIT PULSAR ERROR_L LED DEVELOPMENT R834
1 SM
R838
1 DEVELOPMENT 180
2 SDF803 OMIT
PP3V3_RUN 1K
1
R835 5%
1/16W
Q800_D HSK-NUT-6.5MM
TH
ZH804
5% 180 MF 3 6P15R5P4
13 7 6 =PP3V3_ALL_SMU 1/16W 5% 2 402
MF 1/16W DEVELOPMENT HS_SDF803 1 HS_SDF804 1
NOSTUFF 2 402 MF
2 402
D
Q800 SDF700 IS ALSO
2N7002
C800 1 NOSTUFF DEVELOPMENT Q803_C
LED802_1 Q800_G 1 G S
SM 1 C883 1 C884
USED FOR HEATSINK
0.1uF
20%
1
R890 DEVELOPMENT DEVELOPMENT
0.01UF 0.01UF
MOUNTING
10V
CERM 2
2 1K R8011 R800
1
R839 3
DEVELOPMENT 1
DEVELOPMENT
2 20%
16V
20%
16V
5% 4.7K 330 180 LED802 DEVELOPMENT 2 CERM 2 CERM
402
VCC 1/16W
MF
5%
1/16W
5%
1/16W
29 PLLLOCK 1 2 Q803_B 1 Q803 GREEN R836 3
402 402
2 402 MF MF 5% 2N3904 2.0X1.25A 180 DEVELOPMENT
U890 402 2 2 402
1/16W
MF 2
SM 2 29 14 6 CHKSTOP_L 1 2 1 Q801
SM 402 5% Q801_B 2N3904
ERROR_LED 1/16W SM
8 7 6 SMU_MANUAL_RESET_L 5 DELAY NOSTUFF RESET 1 SMU_RESET_L 6 13 MF 2
402
NOSTUFF
C890 1
0.01UF
VOLTAGE DETECTOR
MC33465N_30ATR
1
NOSTUFF
C891
1uF
1 DEVELOPMENT
D810
RED
SIGNAL ALIAS
A 10%
16V
CERM 2
GND
10%
6.3V
2 CERM 2
SM

A
402 402 CLOCK_ERROR_L
3 27
SHASTA JTAG PULL DOWN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R810 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0
1 2 25 JTAG_SB_TRST_L I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W THESE PINS HAVE INTERNAL PULLUPS
MF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
402 TP_JTAG_SB_TCK
MAKE_BASE=TRUE
ALIAS JTAG_SB_TCK 25 1
R825
TP_JTAG_SB_TDI ALIAS JTAG_SB_TDI 25 10K SIZE DRAWING NUMBER REV.
MAKE_BASE=TRUE 5%
TP_JTAG_SB_TDO
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
ALIAS JTAG_SB_TDO
JTAG_SB_TMS
25 1/16W
MF D 051-6482 I
2 402
25
MAKE_BASE=TRUE ALIAS APPLE COMPUTER INC.
SCALE SHT OF
NONE 8 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
2.5V VOLTAGE REGULATOR
PP5V_PWRON
PP5V_PWRON NOTE:
SET OUTPUT=2.62V FOR FRAMEBUFFER.
D900 IRU3037CS VREF=1.25VDC
2 1 VOUT=VREF*(R903+R905)/R905=2.62VDC
1 CRITICAL
MBR0520L D902 C901 PEAK CURRENT OF TOTAL RAILS
R900
1 SM
MBR0520L
1 1
C902 1
C903
4.7 SM 10UF 390UF 390UF 12.68A WITH DIMM TERMINATION
5% 2 20% 20% 20%
1/10W
FF
D901 2 6.3V
CERM 2 6.3V
ELEC
2 6.3V
ELEC
9.24A WITHOUT DIMM TERMINATION
U900_VC_R 2 1 U900_VC_D 1206 8X11.5-TH 8X11.5-TH
2 805
U900_VC
MBR0520L
SM
4
1 C904 1 C916
1UF
C 20%
25V
2 CERM 2 6
1UF
20%
2 25V
R902
0
D
Q901 1 C917 PP2V5_PWRON PP2V5_RUN
C
805 VCC VC CERM 1 2 Q901_GATE 1 G NTD70N03R 1UF
805 20%
U900 5% S
CASE369
10V
2 CERM
IRU3037CS 1/10W
FF 603 CRITICAL Q903
SOI
HD 5 U900_GATE_H
805 3 L901 IRF7410
SO-8
1.6UH VOLTAGE=2.5V
U900_SS 8 8
SS MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL Q902_DRAIN 1 2 MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL 3
LD 3 U900_GATE_L 7
NOSTUFF TH 2 S D 6
U900_COMP 7 COMP
FB 1 U900_FEEDBACK 4
R904
1 NOSTUFF 1
R903
1
5
6
1.1K 1 C907 11K G
R901
1 5%
1/8W 3300PF 1%
27.4K GND D FF 10%
50V 1/16W 4
1% 4 Q902 2 1206 2 CERM MF LOW TO ENABLE
1/16W 603 2 402
MF G NTD70N03R
1 C915 2 402 1 C913 1 C906
1
CASE369
R904_P2 1
C908 1
C909
0.47UF 56PF 220PF NOSTUFF S NOSTUFF 1800UF 1800UF
R901_P2 20% 20%
20%
2 10V
5%
2 50V
5%
2 25V
1 C905 3
1 C912 2 6.3V
ELEC
2 6.3V
ELEC
CERM C914 CERM CERM 0.022UF 1UF
603
1
3900PF
402 402 10%
50V
20%
25V
1
R905 TH-KZJ TH-KZJ
5% 2 CERM 2 CERM 10K

50V 603 1206 1%
2 CERM 1/16W
603 MF
2 402 SYS_SLEEP 6 8 10 11 46 50
U900_FEEDBACK
B B
2.5V VREG
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 9 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SHASTA CORE VOLTAGE REGULATOR

D D
PP5V_ALL
PP5V_ALL
D1000 NOTE:
2 1
SET OUTPUT=1.2V
1 IRU3037ACS VREF=0.8VDC
MBR0520L D1002 C1001 1 C1002 VOUT=VREF*(R1003+R1005)/R1005=1.206VDC
R1002
1 SM
MBR0520L
1
10UF
1
C1003
4.7 SM 390UF 390UF
5%
1/10W D1001 2 20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
PEAK CURRENT OF TOTAL RAILS
FF
U1000_VC_R 2 1 U1000_VC_D
CERM
1206
ELEC
8X11.5-TH
ELEC
8X11.5-TH
5.96A
2 805
MBR0520L
U1000_VC SM
1 C1004 1 C1000
1UF
20% 1UF D 4
25V
2 CERM 2 6 20%
25V
R1000 Q1001 1 C1017
805 VCC VC 2 CERM 0 NTD60N02R 1UF
805
1 2 Q1001_GATE 1
CASE369 20%
U1000 5%
G 10V
2 CERM
PP3V3_ALL IRU3037ACS 1/10W
FF
S 3
603 PPVCORE_PWRON_SB
SOI
HD 5 U1000_GATE_H
805 L1001 3 6 10
1.6UH MAKE_BASE=TRUE
VOLTAGE=1.2V
U1000_SS 8 SS MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL =PPVCORE_PWRON_SB 23
MIN_LINE_WIDTH=25MIL Q1002_DRAIN 1 2 MIN_NECK_WIDTH=15MIL
LD 3 U1000_GATE_L
TH
NOSTUFF
U1000_COMP 7 COMP
R10071 R1004
1 NOSTUFF
C1007 R1003
FB 1 U1000_FEEDBACK 4 1
100K 1.1K 1
5% R1001
1 5% 3300PF 5.11K
1/16W 1/8W 1%
MF 27.4K GND D FF 10% 1/16W
402 2 1% 2 1206 2 50V MF
3 1/16W
4 Q1002 CERM
603 2 402
MF NTD70N03R
C R1010
D Q1000
2N7002
1 C1015
0.1UF
2 402
R1001_P2
1 C1013
68PF
1 C1006
220PF NOSTUFF
1 G
S
CASE369
R1004_P2
NOSTUFF
1
C1008
20%
1800UF
1
C1009
1800UF
20%
C
TURN_ON_SHASTA_CORE_L 1
0 2 Q1000_G 1 G S
SM 20%
16V
2 CERM
5%
50V
2 CERM
5%
25V
2 CERM
1 C1005 3
1 C1012 2 6.3V
ELEC
2 6.3V
ELEC
3
1 C1014 0.022UF 1UF R1005
1 TH-KZJ TH-KZJ
5% 603 603 402 10% 20%
1/16W 2 3900PF 50V
2 CERM
25V
2 CERM 10K
MF 5% 1%
NOSTUFF 402 2 50V
CERM
603 1206 1/16W
603 MF
R1011 2 402
SYS_POWERUP_L 1
0 2
33 13 11 10 7 6
5%
1/16W
MF
402-1 U1000_FEEDBACK
PP1V2_PWRON FET SWITCH PP1V2_RUN FET SWITCH

PEAK CURRENT 0.6A PEAK CURRENT 4.43A
10 6 3 PPVCORE_PWRON_SB PP1V2_PWRON 10 6 3 PPVCORE_PWRON_SB Q1003 PP1V2_RUN

SI9426DY
B
SOI
B
1
2
5
6
7 8
3
1 2
I70
Q1006
5 6
PP3V3_ALL PP5V_ALL SI3446DV PP5V_ALL
RDSON=0.06 OHM RDSON=0.016 OHM
TSOP @ VGS=2.5 V @ VGS=2.5 V
4
R1008
100K 1 Q1003_G
4
2
R1009 5%
2
100K 1 Q1006_G
1/16W
MF
R10141 5%
402
100K 1/16W
MF 3 Q1004 3 6
Q1004
5%
1/16W 402 2N7002DW D D 2N7002DW
MF
402 2 R1012
D Q1005 SOT-363 SOT-363
2N7002
0 SM 5 G S S G 2 SYS_SLEEP 6 8 9 11 46 50
3 TURN_ON_PP1V2_L 1 2 Q1005_G 1 G S
5% 4 1
1/16W 2
MF
NOSTUFF 402
R1013
SYS_POWERUP_L 1
0 2
33 13 11 10 7 6
5%
1/16W
MF
402-1
1.2V VREG
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 10 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
11 7 6 PP5V_ALL
D D
CRITICAL
Q1100
SI4467DY
SM-1 PP5V_PWRON 6 18
18 6 PP5V_RUN 8 VOLTAGE=5V
3 PP5V_PWRON MIN_LINE_WIDTH=25MIL
7 MIN_NECK_WIDTH=10MIL
D S 2
6
1
5
G
1
R1107 1R1101 18 6 PP3V3_RUN
R1100 FET ON IN RUN 1K 1K Q1102
90 59 11 7 PP3V3_ALL
1
100K 2 4 1% 1% SI4467DY
1/16W 1/16W
MF MF SM-1 PP3V3_PWRON 6 18 27
R1104 5%
1/16W
3 CRITICAL
LM339A
2 402 2 402 8 VOLTAGE=3.3V
SYS_POWERUP_L 1
100K 2 MF
402
10
7
SOI
33 13 10 7 6
V+
13 6
D S 2
5%
1/16W R1103 U1100 RAIL_RUN_FET
MIN_LINE_WIDTH=20MIL 1
SYS_SLEEP
MF
402 1
100K 2 11 GND MIN_NECK_WIDTH=10MIL 5
50 46 10 9 8 6
RUN -> LOW G
5% 12 SLEEP -> FLOAT FET ON IN RUN
1/16W SHUTDOWN -> FLOAT
MF 4
402
RAIL_CTL_POS
3 Q1103
4 LM339A FET ON IN SLEEP
4 SI4467DY
SOI SM-1
V+
2 G 5
3 RAIL_CTL_NEG U1100 RAIL_SLEEP_FET
6
5 GND MIN_NECK_WIDTH=10MIL 2 S D
RUN -> FLOAT 7
12 SLEEP -> LOW 3
R11021 SHUTDOWN -> FLOAT
CRITICAL
8
C 47.0K
1%
1/16W
MF FET ON IN SLEEP
4
Q1101
SI4467DY
P-CHANNEL
Ron=11mOhm
C
603 2 SM-1
1
G 5
6
2 S D 7
11 7 6 PP5V_ALL 3
8
PP3V3_ALL 7 11 59 90
VOLTAGE=3.3V
P-CHANNEL MIN_LINE_WIDTH=25MIL
Ron=11mOhm MIN_NECK_WIDTH=10MIL
PROCESS SWING
CRITICAL 1 3.30V - 3.45V
SENSE
VR1100
CS5253
Vpwr >= Vout+0.35V 5 SM 3 Vout=Vref(1+R2/R1)+Iadj(R2)
VPWR VOUT Vref=1.250V typ
Vctrl >= Vout+1.25V 4 VCTRL VOUT 6 R1105
1 Iadj=50uA typ
TAB 124
ADJ R1 1%
1/16W
1
C1100
MF 150UF
20%
2 2 603 2 10V
3_3V_ALL_ADJ ELEC
MIN_LINE_WIDTH=20MIL SM
1
C1102 1 C1101 R1106
1
100UF 0.1UF 210

N20P80% R2 1%
20% 1/16W
16V
2 6.3V 2 CERM MF
ELEC
SM 603 2 603
B B
5V & 3.3V VREGS

A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 11 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
SMU_CLK10M_XTAL 15 MIL SPACING SMU_CLK10M_XIN 13

Real Time Clock
15 MIL SPACING SMU_CLK10M_XOUT 13
15 MIL SPACING SMU_CLK10M_XOUT_R 13 7 =PP3V3_ALL_RTC

13 8 7 6 =PP3V3_ALL_SMU
RTC_CLK32K_XTAL 15 MIL SPACING RTC_CLK32K_X1 13
RTC_CLK32K_X2
15 MIL SPACING 13
System Management Unit C1308 1 8
Page Notes 13 8 7 6 =PP3V3_ALL_SMU R1315

1
4.7 2
PP3V3_ALL_SMU_AVCC 8
VOLTAGE=3.3V
MIN_LINE_WIDTH=15 mil
0.1uF
20%
10V
CERM 2
402
U1301
DS1338
VCC RTC_CLK32K_X1
CRITICAL
13
D Power aliases required by this page:

- _PP3V3_ALL_SMU
5%
1/16W
MIN_NECK_WIDTH=10 mil
18 I2C_RTC_SDA 5 SDA X1
MSOP 1
1
Y1301
32.768K
D
- _PP3V3_ALL_RTC
C1300 1 C1301 1 C1302 1 MF
402
1 C1303 I2C_RTC_SCL 6 SCL
X2 2
SM-1
10uF 0.1uF 0.1uF 1uF 18
4
- _PP3V3_PWRON_SMU 20% 20% 20% 10% 3
6.3V
CERM 2
10V
CERM 2
10V
CERM 2
6.3V
2 CERM NC 7 SQW/ VBAT
- _PPVREF_SMU (SMU AVCC or 2.5V reference) 805 402 402 402 OUT GND RTC_CLK32K_X2 13
GND_SMU_AVSS 8 13 33 36 4
Signal aliases required by this page: 1 C1309
Entry Desktop
Entry Desktop
(NONE) 0.1uF
20%
BOM options provided by this page: SMU_BOOT_BUSY 8
10V
2 CERM
Portable
Consumer
Portable
Consumer
Y = Primary function 13 78
Desktop
Desktop
(NONE) SMU_BOOT_SCLK 8
402
Server
Server
N = Alternate function VCC AVCC
(see aliases below) SMU_BOOT_CE 8
NOTE: CPU current/voltage monitoring
S = Spare U1300
(CPU_SENSE_I/CPU_SENSE_V) requires M30280F8
QFP-80 RTS0*/
100K/10uF RC filter at SMU pins. 33 CPU_SENSE_I Y Y Y S S 67 P0[0] AN00 CTS0* P6[0] 43 Y Y Y N N CPU_VID<0> 8 13
Caps should connect to GND_SMU_AVSS. 33 CPU_SENSE_V Y Y Y S S 66 P0[1] AN01 OMIT CLK0 P6[1] 42 Y Y Y N N CPU_VID<1> 8 13
SMU_VREF should be same signal or 36 CPU_TEMP Y Y Y S S 65 P0[2] AN02 RXD0 P6[2] 41 Y Y Y N N CPU_VID<2> 8 13
reference used by monitoring 30 CPU_BYPASS Y Y Y S S 64 P0[3] AN03 TXD0 P6[3] 40 Y Y Y S S CPU_VID<3> 8

63 RTS1*
circuit, but be aware that this will 13 FAN_RPM3 N S Y Y Y P0[4] AN04 (BUSY) P6[4] 31 Y Y Y S S CPU_VID<4> 8
affect other analog inputs such as 13 FAN_RPM4 N S Y Y Y 62 P0[5] AN05 CLK1 P6[5] 30 Y Y Y S S CPU_VID<5> 8
AC adapter ID. 13 FAN_RPM5 N S Y Y Y 61 P0[6] AN06 RXD1 P6[6] 29 Y Y Y Y Y SMU_BOOT_RXD 8
8 SMU_ONEWIRE Y Y Y Y Y 60 P0[7] AN07 TXD1 P6[7] 28 Y Y Y Y Y SMU_BOOT_TXD 8

NOTE: All analog inputs to SMU should have
a 100pF capacitor to the SMU AVSS Y Y Y Y Y 59 Y Y Y Y Y
3 SMU_PWRSEQ_P1_0 P1[0] AN20 SDA P7[0] 27 I2C_SMU_B_SDA 18
signal (GND_SMU_AVSS). None of 58
3 SMU_PWRSEQ_P1_1 Y Y Y Y Y P1[1] AN21 SCL P7[1] 26 Y Y Y Y Y I2C_SMU_B_SCL 18
those capacitors are provided on Y Y Y Y Y 57 Y Y Y N N
3 SMU_PWRSEQ_P1_2 P1[2] AN22 TA1out P7[2] 25 I2C_SMU_CPU_SDA_IN 13 18
this page.
NOTE: Some primary and alternate functions
8
3
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
56
55
P1[3]
P1[4]
AN23 TA1in
TA2out
P7[3] 24
P7[4] 23
Y
Y
Y
Y
Y
Y
Y
N
Y
N
FAN_RPM0
I2C_SMU_CPU_SCL_IN
16
13 18
SMU Pull-ups / pull-down
C reuire pull-ups that are not.
provided on this page. Please.
13 8 6
13 8
SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
N
N
Y
S
Y
S
Y
S
Y
Y
54
53
P1[5]
P1[6]
INT3*
INT4*
TA2in
TA3out
P7[5] 22
P7[6] 21
Y
N
Y
S
Y
S
Y
Y
Y
Y
FAN_RPM1
FAN_PWM8
16
8 13
=PP3V3_ALL_SMU 6 7 8 13 C
N S Y Y Y 52 P7[7] 20 Y Y Y Y Y
review the latest SMU specification 13 8 SYS_DOOR_AJAR_L P1[7] INT5* TA3in FAN_RPM2 17
R1300
to ensure missing pull-ups are 10K
1 2 SYS_POWERUP_L 6 7 10 11 13 33
provided on another page. 18 I2C_SMU_E_SDA Y Y Y Y Y 51 P2[0] SDAmm TA4out P8[0] 19 Y Y Y Y Y SYS_LED 21
5%
Y Y Y Y Y 50 P8[1] 18 Y Y Y Y Y
NOTE: Pinout matches SMU pinout v1.51.
18 I2C_SMU_E_SCL
Y Y Y Y Y 49
P2[1] SCLmm TA4in
Y Y Y Y Y
SYS_COLD_RESET_L 8 13 24
R1302 1/16W
MF
16 FAN_TACH0 P2[2] IOC2 INT0* P8[2] 17 SYS_PME_L 13 25 77 10K 402
1 2 SYS_POWER_BUTTON_L 6 7 13
16 FAN_TACH1 Y Y Y Y Y 48 P2[3] IOC3 INT1* P8[3] 16 S S S S S SMU_QREQ 28
5%
17 FAN_TACH2 Y Y Y Y Y 47 P2[4] IOC4 INT2* P8[4] 15 Y Y Y Y Y SYS_SLEWING_L 13 25 27 33 1/16W
13 FAN_TACH3 S N Y Y Y 46 P2[5] IOC5 NMI* P8[5] 14 Y Y Y S S I2C_SMU_CPU_SDA_OUT_L 18
MF
402 R1303
S N Y Y Y 45 Y Y Y Y Y 10K
13 FAN_TACH4 P2[6] IOC6 CE* P8[6] 8 SYS_POWERUP_L
MAKE_BASE=TRUE
6 7 10 11 13 33 1 2 SYS_RESET_BUTTON_L 7 13
13 FAN_TACH5 S N Y Y Y 44 P2[7] IOC7 P8[7] 7 Y Y Y Y Y SMU_SLEEP 8 13 5%

1/16W
MF
402
18 I2C_SMU_A_SDA_IN Y Y Y Y Y 39 P3[0] CLK3 TB0in P9[0] 5 Y Y Y Y Y CLOCK_RESET_L 27
18 14 6 I2C_SMU_A_SDA_OUT_L Y Y Y Y Y 38 P3[1] Sin3 TB1in P9[1] 4 Y Y Y S S CPU_HRESET 30

NO_SMU_I2C_D 37
18 I2C_SMU_A_SCL_IN Y Y Y Y Y P3[2] Sout3 TB2in P9[2] 3 Y Y Y Y Y SB_TO_SMU_INT_L 25
PP3V3_PWRON
R1399 18 14 6 I2C_SMU_A_SCL_OUT_L Y Y Y Y Y 36 P3[3] AN24 P9[3] 2 Y Y Y Y Y SB_STOPXTALS_L 25
R1304
0 Y Y Y Y Y 35 Y Y Y Y Y
25 SMU_TO_SB_INT_L 1 2 18 I2C_SMU_D_SDA P3[4] AN25 P9[5] 1 SMU_PWRSEQ_P9_5 3
2
10K 1 SYS_PME_L 13 25 77
5% 18 I2C_SMU_D_SCL Y Y Y Y Y 34 P3[5] AN26 P9[6] 80 Y Y Y Y Y SMU_PWRSEQ_P9_6 3
13 8 7 6 =PP3V3_ALL_SMU 1/16W 5%
MF 13 SMU_CHARGE_BATT Y S S S S 33 P3[6] AN27 P9[7] 79 S S Y Y S SYS_SLOT_PWR 8 1/16W
402 MF
27 25 16 SYS_OVERTEMP_L Y S S S S 32 P3[7] 402
PP3V3_RUN
3 R1322
1
AN0 P10[0] 76 S S S S S TP_SMU_SPARE_P10_0 R1312
150K 2K
D1310
1N914
5%
1/16W 8 =PPVREF_SMU
AN1 P10[1] 74 Y Y Y Y Y SMU_WARM_RESET_L 8 1 2 SYS_SLEWING_L 13 25 27 33
SOT23 MF AN2 P10[2] 73 Y Y Y Y Y NB_SUSPENDACK_L 8 5%

1 1/16W
2 402 8 SMU_BOOT_CNVSS 6 PCNVSS AN3 P10[3] 72 Y Y Y Y Y SB_SUSPENDACK_L 25 MF
402
SMU_RESET_L 9 RESET* KI0* P10[4] 71 Y Y Y Y Y SMU_SUSPENDREQ_L NO STUFF
B B
8 6 13 24 25 28
PP2V5_PWRON
10 70 Y Y Y Y Y
13 SMU_CLK10M_XOUT_R XOUT KI1* P10[5] SYS_POWER_BUTTON_L 6 7 13
R1311
C1310 1 13 SMU_CLK10M_XIN 12 XIN KI2* P10[6] 69 Y Y Y Y Y SYS_RESET_BUTTON_L 7 13
1
2K 2 SMU_SUSPENDREQ_L
0.22uF 77 VREF KI3* P10[7] 68 Y Y Y S S I2C_SMU_CPU_SCL_OUT_L 18
13 24 25 28
20% 5%
6.3V 2
CERM
402
NO STUFF R1313 1/16W
MF
R1316 R13251 R1327
1 100K 2 402
10M 10K
1 C1325 VSS
11
AVSS
75 10K
1 SYS_COLD_RESET_L 8 13 24
1 2 5% 1uF 5% 5%
1/16W 10% 1/16W 1/16W
5% 6.3V MF
1/16W
MF
402 2
2 CERM
402 XW1300 MF
2 402
402
R13171 MF
402
SM
0 1 2
R1310
5%
1/16W CRITICAL 100K 2
1 SMU_SLEEP
MF
402 2 Y1300 GND_SMU_AVSS 8 13 33 36
VOLTAGE=0V 5%
8 13
10.0000M
1 2 MIN_LINE_WIDTH=15 mil 1/16W
MIN_NECK_WIDTH=10 mil MF
Keep crystal subcircuit close to SMU. 402
13 SMU_CLK10M_XOUT 8X4.5MM-SM
Y1300’s load capacitance is 12pF
C1304 1 C1305 1
18pF 18pF
5% 5%
50V 50V
CERM 2 CERM 2
402 402
Master: Link
System Management Unit

A Alternate Functions A
Portable Consumer Tower & Server THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Port Port Port PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
13 FAN_RPM3 0.4 ALS0_OUT 8 13 FAN_TACH3 2.5 SYS_LED_RED 21 13 8 CPU_VID<0> 6.0 FAN_TACH6
13 FAN_RPM4 0.5 ALS1_OUT 8 13 FAN_TACH4 2.6 SYS_LED_GREEN 21 13 8 CPU_VID<1> 6.1 FAN_TACH7
13 FAN_RPM5 0.6 ALS_GAIN_BOOST 8 13 FAN_TACH5 2.7 SYS_LED_BLUE 21 13 8 CPU_VID<2> 6.2 FAN_TACH8
13 8 6 SYS_POWERFAIL_L 1.5 SMU_ACIN 13 SMU_CHARGE_BATT 3.6 DIAG_LED 8 18 13 I2C_SMU_CPU_SDA_IN 7.2 FAN_PWM6
13 8 SYS_DRIVE_BAY_INT_L 1.6 SMU_BATT_DET_L 18 13 I2C_SMU_CPU_SCL_IN 7.4 FAN_PWM7 SIZE DRAWING NUMBER REV.
13 8
13 8
SYS_DOOR_AJAR_L
FAN_PWM8
1.7
7.6
SYS_LID_OPEN
SYS_KBDLED APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
NONE 13 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEVELOPMENT
R1400
0
27 EI_CPU1_CLK_P_R 1 2 EI_CPU1_CLK_P 6 14 27
5% 1/16W
MF 402
DEVELOPMENT
R1401
0
27 EI_CPU1_CLK_N_R 1 2 EI_CPU1_CLK_N 6 14 27
5% 1/16W
MF 402
D DEVELOPMENT
D
0 R1402
27 CPU1_HTBEN_R 1 2 CPU1_HTBEN 6 14
5% 402
DEVELOPMENT
0 R1403
27 EI_CPU1_SYNC_R 1 2 EI_CPU1_SYNC 6 14 27
5% 402
=PP1V2_EI_CPU 7 18 29 30 31 35
28 18 14 7 =PP1V2_EI_NB
NOSTUFF
=PP1V2_EI_NB 7 14 18 28
J1400
YFS-30-03-H-08-SB
F-ST-BGA
27 14 6 EI_CPU1_SYNC H1 H1 G1 G1 EI_CPU1_CLK_P 6 14 27 14 6
27
EI_CPU1_CLK_N F1 F1 E1 E1 30 29 25 6 CPU_INT_L D1 D1 C1 C1 B1 B1 A1 A1 CPU_HRESET_L 6 29 30
29 8 6 CHKSTOP_L H2 H2 G2 G2 F2 F2 E2 E2 D2 D2 C2 C2 B2 B2 A2 A2 CPU1_HTBEN 6 14
H3 H3 G3 G3 NC F3 F3 E3 E3 D3 D3 C3 C3 B3 B3 A3 A3 EI_CPU_TO_NB_AD<0> 6 28 29
H4 H4 G4 G4 EI_CPU_TO_NB_AD<3> 6 28 29 F4 F4 E4 E4 D4 D4 C4 C4 B4 B4 A4 A4 EI_CPU_TO_NB_AD<2> 6 28 29
H5 H5 G5 G5 EI_CPU_TO_NB_AD<4> 6 28 29 F5 F5 E5 E5 D5 D5 C5 C5 B5 B5 A5 A5
H6 H6 G6 G6 EI_CPU_TO_NB_AD<7> 6 28 29 F6 F6 E6 E6 EI_CPU_TO_NB_AD<8> 6 28 29 D6 D6 C6 C6 EI_CPU_TO_NB_AD<6> 6 28 29 B6 B6 A6 A6 EI_CPU_TO_NB_AD<1> 6 28 29
H8 H8 G8 G8 EI_CPU_TO_NB_CLK_N 6 28 29 F8 F8 E8 E8 NC D8 D8 C8 C8 EI_CPU_TO_NB_AD<20> 6 28 29 B8 B8 A8 A8 EI_CPU_TO_NB_AD<10> 6 28 29
H9 H9 G9 G9 EI_CPU_TO_NB_CLK_P 6 28 29 F9 F9 E9 E9 EI_CPU_TO_NB_AD<12> 6 28 29 D9 D9 C9 C9 EI_CPU_TO_NB_AD<25> 6 28 29 B9 B9 A9 A9 EI_CPU_TO_NB_AD<22> 6 28 29
H10 H10 G10 G10 EI_CPU_TO_NB_SR_N<1> 6 28 29 F10 F10 E10 E10 EI_CPU_TO_NB_AD<5> 6 28 29 D10 D10 C10 C10 EI_CPU_TO_NB_AD<26> 6 28 29 B10 B10 A10 A10 EI_CPU_TO_NB_AD<31> 6 28 29
H11 H11 G11 G11 EI_CPU_TO_NB_SR_P<1> 6 28 29 F11 F11 E11 E11 EI_CPU_TO_NB_AD<36> 6 28 29 D11 D11 C11 C11 EI_CPU_TO_NB_SR_P<0> 6 28 29 B11 B11 A11 A11 EI_CPU_TO_NB_AD<37> 6 28 29
C H12
H13
H12
H13
G12 G12 NC
G13 G13 EI_CPU_TO_NB_AD<17> 6 28 29
F12
F13
F12
F13
E12 E12
E13 E13
EI_CPU_TO_NB_AD<35> 6 28 29
D12
D13
D12
D13
C12 C12
C13 C13
EI_CPU_TO_NB_SR_N<0> 6 28 29
B12
B13
B12
B13
A12 A12
A13 A13
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<34>
6 28 29
6 28 29
C
29 28 6 EI_NB_TO_CPU_AD<13> H17 H17 G17 G17 EI_NB_TO_CPU_AD<14> 6 28 29 28 6

29
EI_NB_TO_CPU_AD<5> F17 F17 E17 E17 EI_CPU_TO_NB_AD<40> 6 28 29 28 6
29
EI_CPU_TO_NB_AD<15> D17 D17 C17 C17 EI_CPU_TO_NB_AD<19> 6 28 29 28 6
29
EI_NB_TO_CPU_AD<4> B17 B17 A17 A17 EI_CPU_TO_NB_AD<29> 6 28 29
29 28 6 EI_NB_TO_CPU_AD<15> H18 H18 G18 G18 EI_NB_TO_CPU_AD<12> 6 28 29 F18 F18 E18 E18 EI_NB_TO_CPU_AD<9> 6 28 29 D18 D18 C18 C18 29 28 6 EI_NB_TO_CPU_AD<3> B18 B18 A18 A18
29 28 6 EI_NB_TO_CPU_AD<21> H20 H20 G20 G20 EI_NB_TO_CPU_AD<19> 6 28 29 F20 F20 E20 E20 EI_NB_TO_CPU_AD<0> 6 28 29 D20 D20 C20 C20 B20 B20 A20 A20
29 28 6 EI_NB_TO_CPU_AD<25> H22 H22 G22 G22 EI_NB_TO_CPU_AD<26> 6 28 29 F22 F22 E22 E22 D22 D22 C22 C22 B22 B22 A22 A22
29 28 6 EI_NB_TO_CPU_AD<10> H26 H26 G26 G26 F26 F26 E26 E26 EI_NB_TO_CPU_AD<2> 6 28 29
29
28 6 EI_NB_TO_CPU_AD<8> D26 D26 C26 C26 29 28 6 EI_NB_TO_CPU_AD<23> B26 B26 A26 A26
29 28 6 EI_NB_TO_CPU_AD<39> H27 H27 G27 G27 F27 F27 E27 E27 EI_NB_TO_CPU_AD<38> 6 28 29
29
28 6 EI_NB_TO_CPU_AD<24> D27 D27 C27 C27 29 28 6 EI_NB_TO_CPU_CLK_N B27 B27 A27 A27
29 28 6 EI_NB_TO_CPU_AD<36> H28 H28 G28 G28 EI_NB_TO_CPU_SR_N<0> 6 28 29
29
28 6 EI_NB_TO_CPU_AD<37> F28 F28 E28 E28 SYNCENABLE 6 29 30 28 6 EI_NB_TO_CPU_AD<7>
29
D28 D28 C28 C28 29 28 6 EI_NB_TO_CPU_CLK_P B28 B28 A28 A28
30 29 6 RI_L H29 H29 G29 G29 EI_NB_TO_CPU_SR_P<0> 6 28 29
29
28 6 EI_NB_TO_CPU_SR_N<1> F29 F29 E29 E29 TP_PROC_TRIGGER_OUT 6 29 29 28 6 EI_NB_TO_CPU_AD<6> D29 D29 C29 C29 EI_SE 6 28 29
30
29 6 MCP_L B29 B29 A29 A29
30 29 28 6 EI_QREQ_L H30 H30 G30 G30 I2C_SMU_A_SCL_OUT_L 6 13 18 28 6
29
EI_NB_TO_CPU_SR_P<1> F30 F30 E30 E30 29 28 6 EI_QACK_L D30 D30 C30 C30 18 13 6 I2C_SMU_A_SDA_OUT_L B30 B30 A30 A30
B B
CPU LOGIC ANALYZER

A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 14 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OPTICAL TEMP SENSOR
FAN 1 - Q37 STYLE CPU FAN CONTROL CIRCUIT
PP3V3_PWRON
CPU FAN 2 PP12V_RUN
R1645
4.7 8 NOSTUFF
PP12V_FAN_0_ANALOG 1 2
VOLTAGE=12V VS+
MIN_LINE_WIDTH=20MIL 5%
1/16W
I2C ADDR:90(1001000) U1602
R1640
C1614 1 1 C1601 MF R16441 SOP
D 10K
1%
10UF
20%
0.47UF
20%
402
4.7K
5% C1619 1 1
NOSTUFF
C1600 7 A0
LM75
D
1/16W 16V 2
ELEC
2 16V
CERM 1/16W
47UF 10UF 6 A1 NOSTUFF
MF 805 MF
2 402 FAN_0_DRV_F SM 402 2 20% 10% 5 A2 R1621
16V 2 2 16V
CERM CRITICAL
ELEC 0
R1641 R1642 C1615 SM 1210
18 I2C_OPTICAL_SDA 1 SDA OS 3 TEMP_SENSOR_OS 1 2 SYS_OVERTEMP_L 13 16 25 27
100K 2 100K 2 100PF 5%

FAN_0_DRV 1 1 FAN_0_OPM 1 2
FAN_0_GATE 18 I2C_OPTICAL_SCL 2 SCL 1/16W
MF
402
1% 1% GND
1/16W 1/16W 5%
3 50V 4
MF MF CRITICAL CERM 3
D
Q1600 R1639
402 402
8 U1700 402
D1604
R1605 2N7002
1
1 C1613
6
LM358-SOI1 1N914 Q1601
13 FAN_RPM0 1
0 2 FAN_0_CNTL 1 G S
SM 10K
1% 0.1UF 7 FAN_0_GT 3 1
1/16W 20% 1
G S IRF5505
5% MF 2 16V
CERM 5 SM
1/16W 2 2 402 603 SOT23
MF
402 4
D CRITICAL
NOSTUFF MAX FAN CURRENT=0.5A J1600
4 HF28040-B
R1600 R1643 M-ST-TH
1
0 2 FAN_0_OPP 1
10K 2
FAN_0_PWR 1 MOTOR CONTROL
5% NOSTUFF 1% MIN_NECK_WIDTH=10MIL TACH
1/16W
MF R1603
1
R1601 1 1/16W
MF C1616 2 CRITICAL 3
402
0 10K
402 4700PF C1617 1 1 C1618 D1605 4
GND
12V DC
5% 1% 1 2 10UF 10UF SM
1/16W 1/16W 10%
16V
10% MBR0530
MF MF CERM 2 2 16V
PP3V3_RUN 2 402 402 2 10%
50V
CERM
603
1210
CERM
1210
1
POWER SUPPLY TEMP SENSOR
17" SYSTEM FAN 603-5518
C
1
R1604 PP3V3_PWRON
C
10K 20" SYSTEM FAN 603-5521
1%
1/16W
R1606 MF
2 402 NOSTUFF
FAN_TACH0 1
0 2 FAN_0_TACH
8
13 VS+
5%
1/16W
I2C ADDR:94(1001010) U1650
MF SOP
402 LM75
7 A0
6 A1 NOSTUFF
5 A2 R1650
CRITICAL
0
18 I2C_PS_TEMP_SDA 1 SDA OS 3 PS_SENSOR_OS 1 2 SYS_OVERTEMP_L 13 16 25 27
5%
18 I2C_PS_TEMP_SCL 2 SCL 1/16W
MF
402
GND
4
FAN 2 - Q37 STYLE CPU FAN CONTROL CIRCUIT

PP12V_RUN
SYSTEM FAN 1 L1602 L1603
R1611 FERR-EMI-100-OHM FERR-EMI-100-OHM
4.7 1 2 1 2
U1601_UNUSED PP12V_FAN_1_ANALOG 1 2 PP12V_RUN_FAN_1_LC
VOLTAGE=12V SM VOLTAGE=12V SM
MIN_LINE_WIDTH=20MIL 5% MIN_LINE_WIDTH=20MIL
1/16W
PP3V3_RUN 6 8 U1601 R1616
C1610 1 1 C1609 MF
402 R1610 1
NOSTUFF
C1602 1 MIN_NECK_WIDTH=10MIL
B LM358-SOI1
7
10K
1%
1/16W
10UF
20%
16V 2
0.47UF
20%
2 16V
CERM
4.7K
5%
1/16W
C1604 1 1 C1603
10UF
0.01UF
20%
16V
CERM 2
B
MF ELEC
805 MF 47UF 10% 402
5 2 402 FAN_1_DRV_F SM 402 2 20%
16V 2
ELEC
2 16V
CERM
1210
4
R1615 R1614 C1605 SM
100PF
1
100K 2 1
100K 2 1 2
FAN_1_GATE
FAN_1_DRV FAN_1_OPM
1% 1%
1/16W 1/16W 5%
3 MF MF CRITICAL 50V
402 402 CERM 3
D Q1602 R1620
8 U1601 402
D1602
R1635 2N7002
1
1 C1611
2
LM358-SOI1 1N914 Q1603
13 FAN_RPM1 1
SM 10K
1% 0.1UF 1 FAN_1_GT 3 1
1/16W 20% 1
G S IRF5505
5% MF 2 16V
CERM 3 SM
1/16W 2 2 402 603 SOT23
MF CRITICAL
402 4
NOSTUFF
D J1601
MAX FAN CURRENT=0.5A 10-89-7062
R1619 4 L1600 M-ST-TH
0 R1613 FERR-EMI-100-OHM MOTOR CONTROL 1 PP12V_RUN_FAN_1_LCL

1 2 10K 1 2 VOLTAGE=12V
FAN_1_OPP 1 2 FAN_1_PWR FAN_1_PWR_FILT 4 MIN_LINE_WIDTH=20MIL
5% MIN_LINE_WIDTH=20MIL MIN_NECK_WIDTH=10MIL
1/16W NOSTUFF 1% MIN_NECK_WIDTH=10MIL SM TACH 6 5
MF
402 R1618
1
R16171
1/16W
MF C1608 2 CRITICAL
L1601
0 10K
402 4700PF C1607 1 1 C1606 D1601 FERR-EMI-100-OHM
GND
5% 1% 1 2 10UF 10UF SM
1/16W 1/16W 10%
16V
10% MBR0530 1 2 FAN_1_TACH_FILT
MF MF 10% CERM 2 2 16V
CERM 1 SM
PP3V3_RUN 2 402 402 2 50V 1210 1210
CERM
603 L1604
FERR-EMI-100-OHM FAN 1, 2 & SYSTEM TEMP
A
1 2 FAN_1_GND_FILT
1
R1623
10K
SM VOLTAGE=0V
MIN_NECK_WIDTH=10MIL NOTICE OF PROPRIETARY PROPERTY
A
1%
1/16W
R1636 MF
402
17" CPU FAN 603-5519 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
0 2
2 AGREES TO THE FOLLOWING
13 FAN_TACH1 FAN_1_TACH 20" HD FAN 603-5487
5%
1/16W II NOT TO REPRODUCE OR COPY IT
MF
402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 16 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FAN 3 - Q37 STYLE SYSTEM FAN CONTROL CIRCUIT

PP12V_RUN
R1745
4.7
PP12V_FAN_2_ANALOG 1 2
VOLTAGE=12V
1/16W
R1740
C1714 1 1 C1701 MF R17441
D 10K
1%
10UF
20%
0.47UF
20%
16V
402
4.7K
5% C1719 1 1
NOSTUFF
C1700 D
1/16W 16V 2 2 CERM 1/16W
MF ELEC MF 47UF 10UF
FAN_2_DRV_F SM 805 20% 10%
2 402 402 2
16V 2 2 16V
ELEC CERM
R1741 R1742 C1715 SM 1210
100K 2 100K 2 100PF FAN_2_GATE

FAN_2_DRV 1 1 FAN_2_OPM 1 2
1% 1%
1/16W 1/16W 5%
3 MF MF CRITICAL 50V
CERM 3
D
Q1700 R1739
402 402
8 U1700 402
D1704
R1705 2N7002
1
1 C1713
2
LM358-SOI1 1N914 Q1701
13 FAN_RPM2 1
SM 10K
1% 0.1UF 1 FAN_2_GT 3 1
1/16W 20% 1
G S IRF5505
5% MF 2 16V
CERM 3 SM
1/16W 2 2 402 603 SOT23
MF CRITICAL
402 4
D J1700
NOSTUFF MAX FAN CURRENT=0.5A 10-89-7062
4 M-ST-TH
R1700 R1743 MOTOR CONTROL 1 +12V DC
1
0 2 FAN_2_OPP 1
10K 2
FAN_2_PWR 4
MIN_LINE_WIDTH=20MIL 6 5
5% NOSTUFF 1% MIN_NECK_WIDTH=10MIL
1/16W
MF R1703
1
R17011
1/16W
MF C1716 2 GND
402
0 10K
402 4700PF C1717 1 1 C1718 D1705 TACH
5% 1% 1 2 10UF 10UF SM
1/16W 1/16W 10%
16V
10% MBR0530
MF MF 10% CERM 2 2 16V
CERM 1 CRITICAL
PP3V3_RUN 2 402 402 2 50V 1210 1210
CERM
603
C
1
R1704 C
10K
1% 17" HD FAN 603-5520
1/16W
R1706 MF
2 402
1
0 2
13 FAN_TACH2 FAN_2_TACH 20" CPU FAN 603-5459
5%
1/16W
MF
402
REMOTE HARD DRIVE TEMP SENSOR
REMOTE HD TEMP SENSOR
B CRITICAL B
J1701
53261-0498
PP3V3_PWRON M-RT-SM
5
18 I2C_HD_TEMP_SDA 2
18 I2C_HD_TEMP_SCL 3
4
I2C ADDR:92(1001001)
6
518S0193
FAN 3 & HD TEMP

A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 17 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
11 6 PP5V_PWRON R1832
1
0 2 PP5V_U1800
PP3V3_PWRON
603 MIN_LINE_WIDTH=12MIL
NOSTUFF MIN_NECK_WIDTH=8MIL
R1833
I2C A BUS 11 6 PP5V_RUN
1
0 2
=PP1V2_EI_NB 7 14 28
I2C B BUS
603 NOSTUFF
11 6 PP3V3_RUN 27 18 11 6 PP3V3_PWRON C1800 1
C1802 R1808
1 1
R1810 R18031 R1802
1
0.1UF R18091 1
R1828 1
0.1UF 200 200 2K 2K
NOSTUFF NOSTUFF 20% 4.7K 4.7K 5% 5% 5% 5%
10V
CERM 2 5% 5% 20%
10V 1/16W 1/16W SMU 1/16W 1/16W
R1830 1 1
R1831 R1800 1
R1801
1
402 1/16W
MF
1/16W
MF
2 CERM
402
MF
402 2
MF
2 402 MASTER
MF
402 2
MF
2 402
2K 2K 2K 2K 402 2 2 402
SMU 5% 5% 5% 5% U1300
D MASTER
U1300
1/16W
MF
402 2
1/16W
MF
2 402
1/16W
MF
402 2
1/16W
MF
2 402
LM339A
SOI
3
V+
8
13 I2C_SMU_B_SDA
NET_SPACING_TYPE=I2C D
MAKE_BASE=TRUE
13 I2C_SMU_A_SDA_IN
MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C 14
U1800 U3LITE 13 I2C_SMU_B_SCL
NET_SPACING_TYPE=I2C
GND 6 U3 MAKE_BASE=TRUE
14 13 6 I2C_SMU_A_SDA_OUT_L NET_SPACING_TYPE=I2C 9
MAKE_BASE=TRUE
12
D
Q1800 PINS 26, 27
13 I2C_SMU_A_SCL_IN NET_SPACING_TYPE=I2C 2N7002DW I2C_NB_A_SDA 24
MAKE_BASE=TRUE 2
SOT-363
G S I2C_NB_A_SCL 24
14 13 6 I2C_SMU_A_SCL_OUT_L NET_SPACING_TYPE=I2C
MAKE_BASE=TRUE
1
PINS 36-39 PULSAR
3 PINS A20, B20 U2600
LM339A 6
SOI V+
1
U1800 3 NOSTUFF NOSTUFF 27 I2C_CLOCK_SDA ALIAS
GND 7 D Q1800 R18201 1
R1821 27 I2C_CLOCK_SCL ALIAS
12 2N7002DW 0 0
SOT-363 5% 5%
5 G S 1/16W 1/16W PINS C1, B1
MF MF
402 2 2 402
27 18 11 6 PP3V3_PWRON 4
=PP1V2_EI_CPU 7 14 29 30 31 35
R18191 R1818
1
2K 2K OPTICAL TEMP SENSOR
5% 5%
1/16W 1/16W 3 U1602
MF
402 2
MF
2 402
LM339A 10 R18161 1
R1817
SOI 200 200
SMU 13
V+ 5% 5% 16 I2C_OPTICAL_SDA ALIAS
MASTER U1800 1/16W
MF
1/16W
MF 16 I2C_OPTICAL_SCL ALIAS
GND
U1300 RP1800 11 402 2 2 402 CPU PINS 1, 2
13 I2C_SMU_CPU_SCL_IN I2C 0K 12 U2900
MAKE_BASE=TRUE 5% I2C ADDR:90
C 13 I2C_SMU_CPU_SCL_OUT_L
MAKE_BASE=TRUE
I2C 1
2
8
7
SMU_CPU_JTAG_OR_I2C
I2C_CPU_A_SCL
I2C_CPU_A_SCL 29
C
13 I2C_SMU_CPU_SDA_IN I2C NET_SPACING_TYPE=I2C
MAKE_BASE=TRUE 3 6 I2C_CPU_A_SDA_TO_SMU I2C_CPU_A_SDA 29
13 I2C_SMU_CPU_SDA_OUT_L I2C 4 5 I2C_CPU_A_SDA_TO_CPU 3 PS TEMP SENSOR

MAKE_BASE=TRUE LM339A 4
1/16W U1650
PINS 14,25,23,68 SM1 SOI V+ PINS AA20, Y21
2
6 U1800 16 I2C_PS_TEMP_SDA ALIAS
GND
D
Q1801 5
16 I2C_PS_TEMP_SCL ALIAS
2N7002DW 12
2 SOT-363 3 PINS 1, 2
G S
I2C ADDR:94
1
D
Q1801
2N7002DW
SOT-363
5 G S
I2C_CPU_SCL_LS
I2C_0V6_REF 4 HD TEMP SENSOR
NOSTUFF U1702
RP1801 C1801 1 R18111
0K CPU JTAG 0.1UF 4.7K 17 I2C_HD_TEMP_SDA ALIAS
20% 5%
5% 10V
1 8 CERM 2 1/16W 17 I2C_HD_TEMP_SCL ALIAS
JTAG_CPU_TDO 29 30 402 MF USE 576 OHM FOR R1811 IF 5V RAIL IS USED FOR REFERENCE
2 7 402 2
JTAG_CPU_TDI 29 30 PINS 1, 2
3 6 JTAG_CPU_TMS 29 30 I2C ADDR:92
4 5 JTAG_CPU_TCK 29 30
PP2V5_PWRON
I2C D & E BUS
1/16W
SM1
I2C C BUS PP2V5_PWRON

I2C SB BUS PP3V3_RUN
B PP3V3_ALL
B
R1805 1
R1804
1
U3LITE SHASTA R18151 1
R1814
2K 2K R18121 1
R1813 1K 1K
5% 5% MASTER 5% 5%
1/16W
MF
1/16W
MF
MASTER
5%
2K 2K
5%
R18071 R1806
1
U2300
1/16W
MF
1/16W
MF
402 2 2 402 U3 1/16W 1/16W 2K 2K 402 2 2 402
NET_SPACING_TYPE=I2C MF MF 5% 5%
I2C_NB_C_SDA
MAKE_BASE=TRUE
24
U3LITE ’B’ 402 2 2 402 1/16W
MF
1/16W
MF
RTC 25 I2C_SB_SDA
402 2 2 402 MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C U3 U1301 NET_SPACING_TYPE=I2C
I2C_NB_C_SCL 24 25 I2C_SB_SCL
PINS C21, E21 PINS Y9, AB7
24 I2C_NB_B_SDA I2C I2C I2C_RTC_SDA 13
24 I2C_NB_B_SCL I2C I2C I2C_RTC_SCL 13
DIMMS PINS C20, B21

PINS 5, 6
MICRODASH
J4000 = A0
J4001 = A2
J9400
NOSTUFF NOSTUFF
ALIAS I2C_DIMM_SDA 40
I2C_DIMM_SCL 40
R18221 1
R1823 94 6 I2C_UDASH_SDA ALIAS
ALIAS
0 0 94 6 I2C_UDASH_SCL ALIAS
PINS 91, 92 5% 5%
1/16W 1/16W
OF EACH DIMM MF MF PINS 21, 24
402 2 2 402 NOSTUFF
R1824 R1826
2
0 1 2
0 1
SMU ’E’ SMU ’D’
MASTER
5%
1/16W
MF
5%
1/16W
MF
MASTER
AUDIO I2C CONNECTIONS
A U1300 402 402
NOSTUFF
U1300 U9500 / AU300

A
13 I2C_SMU_E_SDA I2C R1825 R1827 I2C I2C_SMU_D_SDA 13
103 95 I2C_AUDIO_SDA ALIAS
0 0 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
13 I2C_SMU_E_SCL I2C 2 1 2 1 I2C I2C_SMU_D_SCL 13 103 95 I2C_AUDIO_SCL ALIAS PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5% 5%
PINS 50, 51 1/16W 1/16W PINS 34, 35 PINS 18, 19 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF MF
402 402 II NOT TO REPRODUCE OR COPY IT

STANDARD CONFIGURATION: SMU IS MASTER OF BUS E WITH RTC AS SLAVE; U3LITE ’B’ AND SMU ’D’ ARE NOT USED
D 051-6482 I
TO IMPROVE LATENCY WITH RGB LED - U3LITE ’B’ AND SMU ’E’ CAN MAKE AN I2C ’E’ BUS APPLE COMPUTER INC.
SMU ’D’ AND RTC CAN MAKE AN I2C ’D’ BUS SCALE SHT OF
NONE 18 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TOTAL CURRENT EXCLUDING LEDS CURRENT < 170 MICRO AMPS
PP3V3_PWRON
RGB_LED
C2105 RGB_LED
220PF PP5V_PWRON
1 2 GND_CHASSIS_LED 7 21
LED2100
LATBG66B PP5V_PWRON
AMB-GRN-BLUE RGB_LED RGB_LED RGB_LED
PLACE THESE PARTS CLOSE TO SMU IC 5% PLCC
PP5V_PWRON 25V
CERM
L2104 C2103 1 U2100
402 400-OHM-EMI 0.1UF 4
LP324
20% 10 +
G_DRV_K 1 6 RGB_LED_A 1 2 10V 8
MIN_LINE_WIDTH=25MIL MIN_LINE_WIDTH=25MIL CERM 2 9
RGB_LED MIN_NECK_WIDTH=10MIL
AMB
MIN_NECK_WIDTH=10MIL SM-1 402 -
11TSSOP
D R21091
953K
1
3 2
D
RGB_LED 1% RGB_LED GRN
R2101 1/16W
MF L2100
0 402 2 RGB_LED 400-OHM-EMI
SYS_LED_GREEN 2 1 G_PWM_IN_H RGB_LED
13
MAKE_BASE=TRUE
5%
U2100 SM-1 4 5
1 C2107 6 U2100_UNUSED
4 BLUE
PWM INPUT FROM SMU 1/16W RGB_LED 1 LP324 220PF
MF
402 R2104 12 + 14 G_BASE_DRV 2 5%
G_PWM_DC
953K 13 25V
- 2 CERM
1% G_DRV 402
1/16W 11TSSOP MIN_LINE_WIDTH=25MIL
MF MIN_NECK_WIDTH=10MIL
402 2 RGB_LED 3 RGB_LED
C2104 RGB_LED C2108 GND_CHASSIS_LED 7 21
220PF
0.022UF 1 Q2102 2 1
2 1 2N3904
SM
RGB_LED 2 5%
RGB_LED 1 20% 25V
C2106 1 R2105 16V
CERM RGB_LED G_DRV_FB
CERM
402
0.47UF 200K 402
20%
10V 1% R2112 MIN_LINE_WIDTH=25MIL
CERM 2 1/16W 1K RGB_LED
603 MF
402 2
G_IN_OFFSET 2 1 RGB_LED C2109
5MV INPUT OFFSET 1%
1/16W R2100
1
<-- 17 INCH
220PF
MF 25.5 2 1
402 1%
1/16W 5%
MF 25V
2 402 CERM
402
CHANGE R2100 VALUE
100% DUTY CYCLE OF 3V-PP PWM = 0.5V TO SET LED CURRENT
MAX LED CURRENT = 0.5 / R
C PLACE THESE PARTS CLOSE TO SMU IC SYS_DRV_A

C
PP5V_PWRON MIN_LINE_WIDTH=25MIL
R_DRV_K MIN_NECK_WIDTH=10MIL
LED2101
1
2 1
RGB_LED RGB_LED PP5V_PWRON
L2101
R21021 WHITE WHITE_LED
953K 400-OHM-EMI
SM-1
SM6
L2105
1%
1/16W
400-OHM-EMI
RGB_LED MF 1 2
402 2
R2115 RGB_LED
2 SM-1
SYS_DRV_K
0
13 SYS_LED_RED
MAKE_BASE=TRUE
2 1 R_PWM_IN_H U2100 R_DRV WHITE_LED
5% RGB_LED 4
LP324 MIN_LINE_WIDTH=25MIL
C2111
PWM INPUT FROM SMU 1/16W
MF R21101 5 + 7 R_BASE_DRV
220PF
R_PWM_DC
402 953K 6
-
3
5%
1% RGB_LED WHITE_LED 25V
1/16W 11TSSOP C2110 2 CERM
MF
402 2
RGB_LED 1 Q2108 220PF 402
C2101 2N3904
SM 2 1 GND_CHASSIS_LED 7 21
0.022UF 2
2 1 PLACE THESE PARTS CLOSE TO SMU IC 5%
RGB_LED 1 R_DRV_FB 25V
RGB_LED R2111 20% MIN_LINE_WIDTH=25MIL
CERM
402
C2112 1 200K 16V
CERM RGB_LED
0.47UF 1%
1/16W 402 R2114 NOSTUFF WHITE_LED
20% MF 1K RGB_LED Q2100
10V
CERM 2 402 2 R_IN_OFFSET 2 1 L2103
603 1% R2113
1
FDV302P 400-OHM-EMI
1/16W 25.5 <-- 17 INCH PP3V3_PWRON SOT-23 WHITE_LED SM-1
MF
402
1%
1/16W R2106
MF 1K 2
D
SYS_LED_H SYS_GATE
3
2 1
B 2 402
R2119
NOSTUFF 5%
1/16W
SYS_LED_DRV_K
B
WHITE_LED MF MIN_NECK_WIDTH=10MIL
G
953K 1 402
2
R2129 1
117_INCH_LCD
1% 4.7K R2103
1
1/16W 5%
MF
402
1/16W 56.2
PLACE THESE PARTS CLOSE TO SMU IC MF 1%
402 2 1/16W
MF
PP5V_PWRON NOSTUFF 2 402
B_DRV_K
MIN_LINE_WIDTH=25MIL R2132
MIN_NECK_WIDTH=10MIL 1K SYS_LED_DRV_C
13 SYS_LED 2 1 SYS_LED_IN MIN_LINE_WIDTH=25MIL
PWM INPUT FROM SMU 5%
1/16W 3
RGB_LED RGB_LED MF WHITE_LED WHITE_LED
R21181 L2102 402
R2107 Q2101
953K 400-OHM-EMI 2
0 1
FDV301N
1% 1 SM
RGB_LED 1/16W SM-1
R2130 MF
402 2 RGB_LED
5%
1/16W
0 MF 2
13 SYS_LED_BLUE
MAKE_BASE=TRUE
2 1 B_PWM_IN_H U2100 2 402
(STUFF WHEN SYS_LED_L = ACTIVE HIGH)
PWM INPUT FROM SMU 5% RGB_LED 4
LP324 (AND NO STUFF R2132, R2119 & Q2100)
1/16W
MF R21161 3 + 1 B_BASE_DRV
B_DRV
B_PWM_DC
402 953K 2
- MIN_NECK_WIDTH=10MIL
1%
1/16W 11TSSOP 3
MF
402 2 RGB_LED
RGB_LED
C2102 1 Q2114
0.022UF 2N3904 TABLE_5_HEAD
SM PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

1 2 2 TABLE_5_ITEM
RGB_LED RGB_LED 114S3921 1 RES, 39.2 OHM, 1%, 402 R2103 20_INCH_LCD
C2118 R21171 20% B_DRV_FB
0.47UF
1
200K
16V
CERM MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL 20 INCH --> 114S1821 3 RES, 18.2 OHM, 1%, 402 R2100,R2113,R2126 NOSTUFF
TABLE_5_ITEM
INDICATOR LED
A
402
20%
10V
CERM 2
603
1%
1/16W
MF
402 2
RGB_LED
R2127
RGB_LED
R2126
1 NOTICE OF PROPRIETARY PROPERTY
A
1K 25.5 <-- 17 INCH
B_IN_OFFSET 2 1 1% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1% MF AGREES TO THE FOLLOWING
1/16W
MF 2 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 21 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE:
SET OUTPUT=1.5VDC FOR U3LITE CORE
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R2203+R2205)/R2205=1.53VDC
D 7.73A OF PEAK CURRENT DRAW ON PCORE_NB
D
PP5V_PWRON PP5V_PWRON
PPVCORE_NB 6 7
PP5V_PWRON VOLTAGE=1.2V
MAKE_BASE=TRUE
D2200
2 1
22 =PPVCORE_NB
MBR0520L
R2200
1 1
W14
W17
V12
V15
U10
U13
U18
T11
T16
R14
R17
P12
P15
N13
N18
M11
M16
L14
L17
K12
K15
SM
4.7
D2202
5% MBR0520L VDD
1/10W SM AG7 R18
FF
D2201 2 1 C2201 1
C2202 1
C2203 AG13 P11
2 805 10UF 390UF 390UF OMIT
U2200_VC_R 2 1 U2200_VC_D 20% 20% 20% AG16 P16
U2200_VC
6.3V
2 CERM 2 6.3V
ELEC
2 6.3V
ELEC AG22 U3 P19
MBR0520L 1206 8X11.5-TH 8X11.5-TH
AE4
U3LITE N4
SM V1.0-300MM
1 C2204 1 C2216 AE10 PBGA N8
1UF 1UF D (SYM 6 OF 7)
20% 20% AE19 N9
2 25V
CERM
2
VCC
6
VC 2 25V
CERM
R2202 Q2201 1 C2217 AE25 N14
805 805 0 NTD60N02R 1UF
U2200 1 2 Q2201_GATE
G
CASE369 20% AC7 N17
IRU3037CS 5% 2 25V
CERM AC13 N23
1/10W S
SOI
HD 5 U2200_GATE_H
FF
805
805 L2201 AC16 N27
1.6UH
U2200_SS 8 SS AC22 M12
MIN_LINE_WIDTH=25MIL Q2202_DRAIN 1 2
LD 3 U2200_GATE_L MIN_NECK_WIDTH=10MIL AB2 M15
TH
U2200_COMP 7 COMP NOSTUFF AB6 M20
NOSTUFF AB23 L10
FB 1 6 U2200_FEEDBACK R2204
1
C2207 R2203
1
C 1
R2201
27.4K GND
D 4
Q2202
1.1K
1%
1/16W
1
1UF
20%
2.21K
0.5%
1/16W
AB27
AA10
L13
L18
C
10V
1% 4 NTD60N02R MF 2 CERM MF-LF AA19 K2
1/16W 1
2 402 2 603
MF G
CASE369 603 1
C2208 1
C2209 Y12 K6
1 C2214 2 402 1 C2213 1 C2206 S3 R2204_P2 1800UF 1800UF
NOSTUFF 20% 20% Y15 K11
0.1UF R2201_P2 68PF 220PF NOSTUFF 2 6.3V 2 6.3V
20%
16V
5%
50V
5%
25V
1 C2205 1 C2212
ELEC
TH-KZJ
ELEC
TH-KZJ
Y20 GND K16
2 CERM
C2215 2 CERM 2 CERM
0.022UF W4 GND K21
603
1
3900PF
603 402 10%
50V
1UF R2205
1
W8 K25
2 CERM 20% 10K
5%
50V 603 2 25V
CERM 0.5% W13 J9
2 CERM 1206 1/16W
603 MF-LF W18 J14
2 603
W21 H10
W25 H19
V11 G4
V16 G23
U2200_FEEDBACK V19 G27
U9 F13
U14 F16
U17 F22
CHECK FETS T2 D2
T6 D7
T12 D10
T15 D19
T20 D25
T23 B4
T27 B13
R10 B16
B R13 B22
B
22 =PPVCORE_NB
1 C2222 1 C2223 1 C2225 1 C2227 1 C2228 1 C2229 1 C2230 1 C2231 1 C2232 1 C2233 1 C2234 1 C2235 1 C2236 1 C2237 1 C2238 1 C2239 1 C2240 1 C2242 1 C2243 1 C2244 1 C2245 1 C2246 1 C2247
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
U3LITE CORE POWER

A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 22 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PPVCORE_PWRON_SB (1.2V)
NOTE: PCI pads use the VIO supply to meet
different drive timing
characteristics required by the PCI
D spec for 5V vs. 3.3V operation.

Connect _PPPCI32_PWRON_SB to
D
appropriate PCI bus voltage and
_PPPCI64_PWRON_SB to same if 64-bit
PCI, otherwise 3.3V.
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
Power Sequencing:
Must power Shasta VCore rail before any
other Shasta supplies. =PP2V5_PWRON_SB 7 23 25 74 88
10 =PPVCORE_PWRON_SB
1 C2350 1 C2351
0.1uF 0.1uF
20% 20%
H15
J12
J15
L15
M15
P15
R10
R12
T10
T15
1 C2300 1 C2301 1 C2302 1 C2303 1 C2304 10V 10V
H8
K8
L8
N8
R9
2 CERM 2 CERM
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 402 402
20% 20% 20% 20% 20% VDDC
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM AA1 D19
402 402 402 402 402
AA2 VDDO25 G15
AA3 U2300
AB10
SHASTA =PPPCI64_PWRON_SB 7
V1.0 H18
1 C2305 1 C2306 1 C2307 1 C2308 1 C2309 AB2 BGA
H17
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AB6 (1 OF 8) VIO1
20% 20% 20% 20% 20% K21 1 C2355 1 C2356 1 C2357
C 2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
10V
2 CERM
402
B1
B2
POWER
0.1uF
20%
10V
2 CERM
0.1uF
20%
2 10V
0.1uF
20%
10V
2 CERM
C
B5 L21 CERM
VDDO33
402 402 402
D1 OMIT W22
VIO2
F4 Y19 For PCI_AD<63..32>
1 C2310 1 C2311 1 C2312 1 C2313 1 C2314 F8
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% 20% H1
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM L7 VDDP_KL V8 =PPPCI32_PWRON_SB 7
402 402 402 402 402
M1
R2
U12
1 C2360 1 C2361 1 C2362
Shasta max (est 06/30/03) current: 0.1uF 0.1uF 0.1uF
U9 20% 20% 20%
10V 10V 10V
V7 2 CERM 2 CERM 2 CERM
74 25 7 =PP3V3_PWRON_SB DIGITAL - 1.2V - 950 mA (1175 mW) 402 402 402
W4 ANALOG12 - 1.2V - 600 mA ( 760 mW)
VDDPs - 2.5V - 100 mA ( 250 mW) For PCI_AD<31..0>
1 C2320 1 C2321 1 C2322 1 C2323 1 C2324 A1 I/O 2.5 - 2.5V - 20 mA ( 60 mW) W5
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A2 I/O 3.3 - 3.3V - 220 mA ( 770 mW) W19
20% 20% 20% 20% 20% =PP2V5_PWRON_SB 7 23 25 74 88
10V 10V 10V 10V 10V A22 U22
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 A5 Total: 3015 mW U13
AA10 U10
AA6 T12
1 C2365
0.1uF
AB1 R19 20%
1 C2325 1 C2326 1 C2327 1 C2328 1 C2329 AB22 P9
10V
2 CERM
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 402
20% 20% 20% 20% 20% C19 P4
2 10V 2 10V 2 10V 2 10V 10V
2 CERM D2 GND
CERM
402
CERM
402
CERM
402
CERM
402 402 GND P14
E22 P13
F3 P12
B F7 P10 B
1 C2330 1 C2331 1 C2332 1 C2333 1 C2334 H2 N9
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF H9 N22
20% 20% 20% 20% 20%
2 10V 2 10V 2 10V 2 10V 10V
2 CERM J10 N13
CERM CERM CERM CERM
402 402 402 402 402 J11 N12
J13 N11
J14 N10
J16 M2
1 C2335 1 C2336 1 C2337 1 C2338 1 C2339 GND
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
J22
K10
K11
K12
K13
K7
K9
L10
L11
L12
L13
L14
L16
L9
M10
M11
M12
M13
M14
20% 20% 20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM
402 402 402 402 402
Master: Link
Shasta Core Power

A
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
LAST_MODIFIED=Mon Dec 13 20:01:04 2004 NONE 23 103

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
60 7 =PP1V2_HT
PP3V3_PWRON PP2V5_PWRON
PP2V5_PWRON
R2400
1
100
1%
U3LITE REQUIRES ALL JTAG SIGNALS 1/16W
HIGH FOR NORMAL OPERATION
NOSTUFF MF
2 402
R2420
1
R2419
1
1 C2401 NB_VSP_CLK_VREF
330
5%
330
5%
1000PF VOLTAGE=0.6V MIN_LINE_WIDTH=25MIL 1/16W 1/16W
5% MIN_NECK_WIDTH=10MIL MF MF
25V
2 CERM
C2400 R2402 R2401 2 402 2 402
R2424 R2426 R2429 R2431 R2433 R2436
1 1 1 1 1 1
603 R2403
1 1
0.1UF
1 1
PMU_SUSPEND_REQ NB_SUSPEND_REQ_L 24
10K 10K 10K 10K 10K 10K 100 20%
121 121
5% 5% 5% 5% 5% 5% 1% 1% 1% 6 3
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 1/16W 1/16W
MF MF MF MF MF MF MF MF MF
2 402 2 402 2 402 2 402 2 402 2 402 2 402
402
2 402 2 402
D
Q2404 D
Q2404
2N7002DW 2N7002DW
U3 28 25 13 SMU_SUSPENDREQ_L 2 G S
SOT-363 5 G S
SOT-363
U3LITE
V1.0-300MM 1 4
PBGA
(SYM 7 OF 7)
27 VSP_NB_CLK_P P4 VSP_CLKP HRESET* A21 NB_WARM_RESET_L 8

R4 VSP_CLKN OMIT E20 NOSTUFF
27 VSP_NB_CLK_N PURESET* NB_COLD_RESET_L 24
R2408
R25 CE1_LT_TCK SUSPENDACK* D20 NB_SUSPEND_ACK_L 8 0
JTAG_NB_TCK JTAG_NB_TCK D21
1 2
SUSPENDREQ* NB_SUSPEND_REQ_L 24
JTAG_NB_TDI JTAG_NB_TDI V25 CE1_A_TDI 5%
1/16W
JTAG_NB_TDO JTAG_NB_TDO AA25 CE1_B_TDO API0_ISCL A20 I2C_NB_A_SCL 18 MF
402
JTAG_NB_TMS JTAG_NB_TMS M26 CE1_DI1_TMS API_ISCA B20 I2C_NB_A_SDA 18
C JTAG_NB_TRST_L JTAG_NB_TRST_L
NB_RI_PU
F20 CE1_DI2_TRST
AC2 CE1_RI
SYS_ISCL0 C20
SYS_ISCA0 B21
I2C_NB_B_SCL
I2C_NB_B_SDA
18
18
C
AH3 CEO_TEST SYS_ISCL1 C21 I2C_NB_C_SCL 18
NB_TEST_PD
AD5 CE0_MC SYS_ISCA1 E21 I2C_NB_C_SDA 18
NB_MC_PD
NB_RE_PD AD3 CE0_RE DUMMY_A AC28 TP_DUMMY_A 6
D15 PM_SLEEP0 DUMMY_B AB28 TP_DUMMY_B 6

6 TP_NB_PM_SLEEP0
R2444 R2443 R2442
1 1 1
IRQ0 E9 NB_INT_L 25
10K 10K 10K
5% 5% 5%
1/16W 1/16W 1/16W PMR_OBSV Y9 NB_PMR_OBSV 8
MF MF MF
2 402 2 402 2 402 THMI J17 NB_THMI 8
THMO J18 NB_THMO 8
PP3V3_PWRON
PP2V5_PWRON
NOSTUFF NOSTUFF
B R2405 R2438
1
4.7K
1
10K
R2435
1
4.7K B
5% 5% 5%
1/16W 1/16W 1/16W
MF MF MF
2 402 2 402 2 402
NB_PU_RESET NB_COLD_RESET_L 24
6 NOSTUFF 3 NOSTUFF
D
Q2412
2N7002DW
D
Q2412
2N7002DW
2 SOT-363 5 SOT-363
13 8 SYS_COLD_RESET_L G S G S
1 4
R2406
1
0 2
5%
1/16W
MF
402
MASTER: GILA
LAST MODIFIED: JUNE 10, 04
U3LITE MISC
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 24 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I2S0_TO_SB I2S0_DEV_TO_SB_DTI 25 95 74 25 23 7 =PP3V3_PWRON_SB

I2S0_TO_DEV I2S0_SB_TO_DEV_DTO 25 95 103
I2S0_TO_DEV AUDIO I2S0_MCLK 25 102

R2554
1K
I2S0_BIDIR I2S0_BITCLK 25 102 103 25 13 SB_TO_SMU_INT_L 1 2
NO STUFF
I2S0_BIDIR I2S0_SYNC 25 95 103 5%
1/16W
MF R2555
I2S1_TO_SB I2S1_DEV_TO_SB_DTI 6 25 76 94 402 10K
30 29 25 CPU_SRESET_L 1 2
I2S1_TO_DEV I2S1_SB_TO_DEV_DTO 6 25 76 94
5%
I2S1_TO_DEV 10 MIL SPACING I2S1_MCLK 6 25 76 94
R2560 1/16W
MF
I2S1_BIDIR I2S1_BITCLK 6 25 94 1K 402
SYS_OVERTEMP_L 1 2
D I2S1_BIDIR I2S1_SYNC 6 25 94 PP1V2_PWRON_SB_PLL45VDD

VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil R2520 =PP1V2_PWRON_SB 7
27 25 16 13
5%
1/16W
R2561
D
I2S2_TO_SB I2S2_DEV_TO_SB_DTI 25 102 MIN_NECK_WIDTH=15 mil 3.3 MF
1 2 402 10K
I2S2_TO_DEV I2S2_SB_TO_DEV_DTO 25 102 94 25 6 UDASH_RESET_L 1 2
5% NO STUFF
I2S2_TO_DEV 10 MIL SPACING I2S2_MCLK 1/10W 5%
I2S2_BIDIR I2S2_BITCLK
25 102
C2521 1 C2520 1 FF
805 R2562 1/16W
MF
25 102
1uF 10uF 1K 402
I2S2_BIDIR I2S2_SYNC 25 102
10% 20% 33 27 25 13 SYS_SLEWING_L 1 2
6.3V 2 6.3V 2
CERM CERM 5%
402 1206 REDUNDANT - NEED TO ADDRESS THIS
SB_CLK18M_XTAL 15 MIL SPACING SB_CLK18M_XTALI 25 1/16W
MF R2563
15 MIL SPACING SB_CLK18M_XTALO 25 402 10K
94 25 6 MODEM_RING2SYS_L 1 2
15 MIL SPACING SB_CLK18M_XTALO_R 25 PP2V5_PWRON_SB_XTAL18VDD
SB_CLK25M_ATA 15 MIL SPACING SB_CLK25M_ATA 25 27 88 74 23 7 =PP2V5_PWRON_SB R2505 VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil R2564
5%
1/16W
3.3 MIN_NECK_WIDTH=15 mil MF
1 2 PP1V2_PWRON_SB_PLL49VDD 10K 402
5%
VOLTAGE=1.2V R2530 94 25 6 I2S1_RESET_L 1 2
Page Notes
1/10W MIN_NECK_WIDTH=15 mil 3.3 5%
FF
805
1 C2500 1 C2501 1 2 1/16W
MF
10uF 1uF 5% 402
20% 10% 1/10W
Power aliases required by this page: 6.3V
2 CERM
6.3V
2 CERM C2531 1 C2530 1 FF
- _PP3V3_PCI 1206 402 1uF 10uF 805
R2565
10%
6.3V 2
20%
6.3V 2 10K
- _PP3V3_PWRON_SB CERM CERM 25 SB_SATABR_RESET_L 1 2
402 1206
- _PP2V5_PWRON_SB REDUNDANT - NEED TO ADDRESS THIS 5%
- _PP1V2_PWRON_SB R2566 1/16W
MF
10K 402
PP2V5_PWRON_SB_XTALVDD 90 25 FW_LOWPWR 1 2
Signal aliases required by this page: R2510 VOLTAGE=2.5V
5%
(NONE) 3.3 MIN_NECK_WIDTH=15 mil 1/16W
R2567
1 2 =PP3V3_PWRON_SB 7 23 25 74 MF
402 10K
BOM options provided by this page: 5%
1/10W
87 25 ENETFW_RESET 1 2
- PCI_64BIT 1 C2510 1 C2511
AA13
FF 5%
R2568
W14
Y13
Y12
W17
805 1/16W
Configures Shasta for 64-bit PCI 10uF 1uF 1 C2540 MF
20%
6.3V
10%
6.3V 0.1uF 10K 402
NOTE: XGC required for Shasta GPIOs Re-pin within each RPAK as necessary 2 CERM 2 CERM 87 25 ENET_ENERGYDET 1 2
C - MPIC_NB/MPIC_SB
Selects whether NorthBridge or
DO NOT swap between RPAKs
R2511
0
1206 402
XTAL
VDD
XTAL_18 PLL_45 PLL_49
VDD VDD VDD
VIO
PME
20%
10V
2 CERM
402
5%
1/16W
C
SouthBridge MPIC will be used for
1 2 U2300 OMIT
MF
402
5% SHASTA
I2S0: Audio DAC

interrupt controller. 1/16W
MF V1.0 GPIO 74 25 23 7 =PP3V3_PWRON_SB
"Slot E" - AD21
402 BGA
95 25 I2S0_DEV_TO_SB_DTI (I2S0_DEV_TO_SB_DTI) W7 I2S0DTI_H
(2 OF 8) 6 PCI1REQ_3_L U17 PCI_SLOTE_REQ_L 25 RP2550
103 95 25 I2S0_SB_TO_DEV_DTO 4 5 I2S0_SB_TO_DEV_DTO_R Y5 I2S0DTO_H 7 PCI1GNT_3_L AA19 PCI_SLOTE_GNT_L 25
4
10K 5
RP2510 "Slot F" - AD22 SB_GPIO12
I2S0
25
I2S0_MCLK 3 33 6 I2S0_MCLK_R U8 I2S0MCLK_H
102 25
I2S0_BITCLK 1 5%
1/16W 8 I2S0_BITCLK_R AA4 I2S0BITCLK_H 8 PCI1REQ_4_L AB21 PCI_SLOTF_REQ_L 25 5%
1/16W
RP2550
103 102 25
SM1 9 PCI1GNT_4_L AA20 PCI_SLOTF_GNT_L 25 SM1 10K
I2S0_SYNC 2 7 I2S0_SYNC_R Y6 I2S0SYNC_H PCI_SLOTB_INT_L 2 7
NorthBridge / SouthBridge MPIC Routing
I2S1: Soft Modem

103 95 25 25
I2S1_DEV_TO_SB_DTI (I2S1_DEV_TO_SB_DTI) V10 I2S1DTI_H 10 PCI1REQ_5_L U16 SB_TO_SMU_INT_L 13 25 RP2550 5%

1/16W
94 76 25 6
2 7 AB5 I2S1DTO_H 11 PCI1GNT_5_L Y20 CPU_SRESET_L 25 29 30
1
10K 8 SM1
PP3V3_RUN 94 76 25 6 I2S1_SB_TO_DEV_DTO I2S1_SB_TO_DEV_DTO_R 25 PCI_SLOTC_INT_L
RP2520
RP2551
(SCCA)
I2S1
94 76 25 6 I2S1_MCLK 1 33 8 I2S1_MCLK_R V9 I2S1MCLK_H 12 PCI1AD_32_H D18 SB_GPIO12 25 5%
5% AA8 I2S1BITCLK_H 1/16W 10K
94 25 6 I2S1_BITCLK 4 1/16W 5 I2S1_BITCLK_R 13 PCI1AD_33_H A20 SYS_OVERTEMP_L 13 16 25 27 SM1 1 8
SM1 AA7 I2S1SYNC_H 25 PCI_SLOTF_INT_L
R2576
1 94 25 6 I2S1_SYNC 3 6 I2S1_SYNC_R 14 PCI1AD_34_H F18 UDASH_SDOWN 6 94
10K I2S1_RESET_L (I2S1_RESET_L) V5 GPIO_H_0 15 PCI1AD_35_H F17 UDASH_RESET_L RP2551 5%

1/16W
5%
94 25 6 6 25 94
10K SM1
1/16W AA5 I2S2DTI_H 16 PCI1AD_36_H G16 AGP_INT_L 49 25 SB_GPIO23 3 6
I2S2_DEV_TO_SB_DTI (I2S2_DEV_TO_SB_DTI)
I2S2: S/P-DIF
MF
2 402 To SouthBridge ->
102 25
25 I2S2_SB_TO_DEV_DTO
4 5 I2S2_SB_TO_DEV_DTO_R Y8 I2S2DTO_H 17 PCI1AD_37_H F16 PCI_SLOTA_INT_L 6 25 76 5%
1/16W
RP2551
102
RP2530 18 PCI1AD_38_H A21 PCI_SLOTB_INT_L 25 SM1 10K
I2S2
Y7 I2S2MCLK_H
(SCCB)
NB_TO_SB_INT 25 102 25 I2S2_MCLK
3 33 6 I2S2_MCLK_R 25 SB_GPIO24 2 7
5% 19 PCI1AD_39_H B21 PCI_SLOTC_INT_L
MPIC_SB 102 25 I2S2_BITCLK
2 1/16W
SM1
7 I2S2_BITCLK_R AB4 I2S2BITCLK_H
20 PCI1AD_40_H C20 PCI_SLOTD_INT_L
25
RP2550 5%
1/16W
3 1 8 W9 I2S2SYNC_H 25
10K
-> From NorthBridge R2575 MPIC_SB
102 25 I2S2_SYNC I2S2_SYNC_R
Y2 GPIO_H_1 21 PCI1AD_41_H G17 PCI_SLOTE_INT_L 25 25 SB_GPIO25 3 6 SM1
10K 102 I2S2_RESET_L (I2S2_RESET_L)
24 NB_INT_L 1 2 NB_INT_L_R 1 Q2576 AUDIO GPIO - see note on right 22 PCI1AD_42_H G18 PCI_SLOTF_INT_L 25 5%
1/16W
RP2551
MPIC_NB 5% 2N3904 25 SB_INT_L AB3 GPIO_H_2 23 PCI1AD_43_H E19 SB_GPIO23 25 SM1 10K
GPIO
1/16W SM 25 SB_GPIO30 4 5
W8 GPIO_H_3 PCI1AD_44_H F19
R25791 MF
402
2 94 25 6 MODEM_RING2SYS_L
W6 PCI_SEL32BIT_H
24 SB_GPIO24 25
RP2552 5%
0 74 25 23 7 =PP3V3_PWRON_SB SB_PCI_SEL32BIT 25 PCI1AD_45_H D20 SB_GPIO25 25
10K 1/16W
B
5%
PCI1AD_46_H E20
SM1
B
PCI
1/16W MPIC_SB 26 SB_SATABR_RESET_L 25 25 SB_GPIO45 1 8
I2C_SB_SCL Y9 I2CCLK_H
I2C
MF 18
<- To CPU
402 2 R2578 From SouthBridge <- R25001 I2C_SB_SDA AB7 I2CDATA_H 27 PCI1AD_47_H C21 PCI_SLOTG_INT_L 25 77 5%
1/16W
RP2552
47 10K 18
28 PCI1AD_48_H F20 FW_LOWPWR 25 90 SM1 2
10K 7
30 29 14 6 CPU_INT_L 1 2 SB_INT_L 25 5% E9 25 SB_GPIO46
1/16W SYS_WARM_RESET_L RESET_L 29 PCI1AD_49_H G19 ENETFW_RESET
5% MF
87 77 74 8
W10 PCI1AD_50_H C22
25 87
RP2552 5%
PWR_MGT
1/16W 402 2 SB_STOPXTALS_L STOPXTALS_L 30 SB_GPIO30 1/16W
MF
13 25
10K SM1
NOTE: It is the responsibility of

the audio circuit to provide the
necessary pull-ups & pull-downs.
402 28 24 13 SMU_SUSPENDREQ_L U11 SUSPENDREQ_L 31 PCI1AD_51_H D21 ENET_ENERGYDET 25 87 25 SB_GPIO47 3 6
13 SB_SUSPENDACK_L V11 SUSPENDACK_L 32 PCI1AD_52_H G20 AUDIO_LO_DET_L 6 101 5% RP2552
AUDIO GPIOS
PCI_64BIT W18 1/16W
10K
PCI 32-bit select 77 13 SYS_PME_L PCI1PME_L 33 PCI1AD_53_H D22 AUDIO_LO_OPTICAL_PLUG_L 101 SM1
=PP3V3_PCI 7 74 75 76 77
R25011 TP_SB_WATCHDOG V12 INTRWD_H 34 PCI1AD_54_H K18 AUDIO_LI_DET_L
25 SB_GPIO49 4 5
1 = 32-bit PCI & GPIOs 1K

PCI1AD_55_H H19
101
RP2553 5%
R2550 0 = 64-bit PCI & XGC
5%
1/16W 8 JTAG_SB_TDI AA11 TDI 35 AUDIO_LI_OPTICAL_PLUG_L 102
10K 1/16W
SM1
10K MF W11 TDO 36 PCI1AD_56_H J17 AUDIO_HP_DET_L 102 25 SB_GPIO50 4 5
1 2 PCI_SLOTE_REQ_L 402 2 JTAG_SB_TDO
5%
25 8
JTAG_SB_TCK AB11 TCK 37 PCI1AD_57_H F21 AUDIO_SPKR_DET_L 102 5%

1/16W
RP2553
R2551 1/16W
8
38 PCI1AD_58_H G21 AUDIO_LO_MUTE_L 98 SM1 10K
TEST
MF 8 JTAG_SB_TMS Y11 TMS 25 SB_GPIO51 2 7
10K 402 39 PCI1AD_59_H H20 AUDIO_HP_MUTE_L 102
1 2 PCI_SLOTE_GNT_L 25 8 JTAG_SB_TRST_L W12 TRST_L
40 PCI1AD_60_H J19 AUDIO_SPKR_MUTE_L RP2553 5%
1/16W
5%
A3 TEST_MODE_H
100
10K SM1
1/16W
R2552 SB_TEST_MODE_PD 41 PCI1AD_61_H F22 AUDIO_EXT_MCLK_SEL 102 25 SB_GPIO52 3 6
MF
402
1
10K 2 PCI_SLOTF_REQ_L
6 TP_SB_PLLTEST U14 PLLTEST 42 PCI1AD_62_H G22 AUDIO_GPIO_11 102 103 5%
1/16W
RP2553
25
R2580 1 6 TP_SB_FSTEST V14 FSTEST 43 PCI1AD_63_H H21 AUDIO_GPIO_12 101 SM1 1
10K 8
5% 25 13 SMU_TO_SB_INT_L
R2553 1/16W 4.7K W13 XTAL_18_I J20
MF 5% 25 SB_CLK18M_XTALI 44 PCI1C_BE_4_L I2S0_RESET_L 95 5%
10K 402 1/16W V13 XTAL_18_O H22 1/16W
PCI_SLOTF_GNT_L SB_CLK18M_XTALO_R SB_GPIO45
XTALS
1 2 25 MF 25 45 PCI1C_BE_5_L 25 SM1
402 2 K22
5%
U15 XTALI 46 PCI1C_BE_6_L SB_GPIO46 25
1/16W
MF R2556 27 25 SB_CLK25M_ATA
47 PCI1C_BE_7_L K20 SB_GPIO47 25 Master: Link
402 10K NC V15 XTALO
1 2 PCI_SLOTA_INT_L 6 25 76
1
R2590 48 PCI1REQ64_L K17 SYS_SLEWING_L 13 25 27 33
5% 200
R2557
10K
1/16W
MF
402
1%
1/16W
MF
49
50
PCI1ACK64_L
PCI1PAR64_H
L17
E18
SB_GPIO49
SB_GPIO50
25
25
Shasta Serial / Misc
A 1
5%
2 PCI_SLOTD_INT_L 25 CRITICAL
Y2590
2 402
51 XGI_CLK_H Y4 SB_GPIO51 25 A
1/16W
MF R2558 18.432M SB_CLK18M_XTALO 25
52 XGI_DTO0_H U7 SB_GPIO52
XGI
25
402 10K 1 2
1 2 PCI_SLOTE_INT_L 25 53 XGI_DTO1_H T9 NB_TO_SB_INT 25 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5% 8X4.5MM-SM 54 XGI_DTI_H W2 SMU_TO_SB_INT_L AGREES TO THE FOLLOWING
R2559 1/16W
MF
C2590 1 1 C2591 13 25

10K 402 22pF 22pF XTAL_18 PLL_45 PLL_49
1 2 PCI_SLOTG_INT_L 25 77
5% 5% GND GND GND II NOT TO REPRODUCE OR COPY IT
50V 50V
AB12
AB13
AA12
5% CERM 2 2 CERM
402 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W
MF
402 SIZE DRAWING NUMBER REV.
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L2601
180-OHM-1.5A
26 7 =PPVCORE_PWRON_PULSAR SYM 2 OF 2
OMIT
26 7 =PPVCORE_PWRON_PULSAR F1 C1_VDD C1_VSS G1
1 2 L3 C2_VDD U2600 C2_VSS M4
0603 E12 C3_VDD PULSAR C3_VSS E10
FSBGA
R2601 B9 C4_VDD C4_VSS C9
4.7 2 D10 VDD_PLL1
1 PP1V5_PSL_PLL1 VSS_PLL1 D12
VOLTAGE=1.5V D2 VDD_PLL2
5% VSS_PLL2 D1
1/16W
MF
1 C2645 1 C2609 MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL L8 VDD_PLL3 VSS_PLL3 K8
402 2.2UF 0.1UF
20% M3 VDD_PLL4
20% VSS_PLL4 M2
1 C2611 2 6.3V 2 10V
D
D 0.1UF
20%
10V
CERM1
603
CERM
402
PP3V3_PWRON
B2 VDD_I2C
VSS_CML A6
2 CERM VSS_I2C C2
402 26 7 =PP1V2_PULSAR G12 VDD_NBSYNC VSS_NBSYNC F11
PLACE NEAR PIN D10 D12 M12 VDD_PCLK VSS_PCLK L12
L2603 =PP2V5_PWRON_RAM
180-OHM-1.5A 40 37 26 7
H3 VDD25 VSS25 L2
1 2 PP3V3_PWRON K1 VDD25 VSS25 H2
0603 PP3V3_RUN
R2609 E1 VDD33 VSS33 E2
1
4.7 2 PP1V5_PSL_PLL2
L5 VDD33_BC VSS33_BC L7
VOLTAGE=1.5V M9 VDD33_BC1 VSS33_BC1 M5
5% =PPVCORE_PULSAR
1/16W
MF
26 7
A11 VDD_HCLK0 VSS_HCLK0 C10
402 2.2UF 0.1UF
20% A9 VDD_HCLK0
20% VSS_HCLK0 B11
1 C2613 6.3V
2 CERM1 2 10V
CERM A8 VDD_HCLK1 VSS_HCLK1 B7
0.1UF 603 402
20% C5 VDD_HCLK2 VSS_HCLK2 A4
10V
2 CERM B4 VDD_HCLK2 VSS_HCLK2 A7
402 26 7 =PP1V2_PULSAR
PLACE NEAR PIN D2 D1 K10 VDD_HSYNC VSS_HSYNC H10
L2605 H12 VDD_HSYNC VSS_HSYNC K12
180-OHM-1.5A 26 7 =PPVCORE_PULSAR
1 2 J11 VDD15_HSYNC
0603 M11 VDD15_PCLK
R2603 A1 VDD_VCLK VSS_VCLK A3

4.7 2 A12 VDD_XTAL
1 PP1V5_PSL_PLL3 VSS_XTAL C12
VOLTAGE=1.5V
5%
1/16W
MF
402 2.2UF 0.1UF
C 1 C2615
0.1UF
20%
6.3V
2 CERM1
603
20%
2 10V
CERM
402 PINS G12, M12, H3, K1, L5, M9, A11, A9
C
20%
10V
2 CERM A8, C5, B4, K10, H12 J11, M11, A1
402 CAN BE TURNED OFF IN SLEEP
L2607 PLACE NEAR PIN L8 K8
180-OHM-1.5A
1 2 PP3V3_PWRON PP3V3_RUN
0603
R2605
4.7 2
1 PP1V5_PSL_PLL4 1 C2665 1 C2667 1 C2651 1 C2671
5%
VOLTAGE=1.5V 0.1UF 0.1UF 0.1UF 0.1UF
1/16W
MF
MIN_NECK_WIDTH=10MIL 20%
2 10V
20%
2 10V
20%
2 10V
20%
2 10V
402 2.2UF
20%
0.1UF
20%
CERM
402
CERM
402
CERM
402
CERM
402
1 C2619 6.3V
2 CERM1 2 10V
CERM
0.1UF 603 402 40 37 26 7 =PP2V5_PWRON_RAM
20%
10V
2 CERM
402
PLACE NEAR PIN M3 M2 1 C2639 1 C2640
PP3V3_PWRON L2609 0.1UF
20%
0.1UF
20%
180-OHM-1.5A 2 10V 2 10V
CERM CERM
1 2 402 402
0603
R2607
1
4.7 2 PP3V3_PSL_XTAL
VOLTAGE=3.3V 26 7 =PPVCORE_PULSAR
5%
1/16W
MF
402 2.2UF
20%
0.1UF
20%
1 C2631 1 C2632 1 C2633 1 C2634 1 C2635 1 C2636 1 C2637 1 C2638
B 1 C2620 2 6.3V
CERM1 2 10V
CERM
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20% B
0.1UF
20%
603 402 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 402 402 402 402 402 402 402 402
402
402 CAPS NOT NEEDED

26 7 =PPVCORE_PWRON_PULSAR
IF 603 CAN BE PLACED CLOSE TO PULSAR
1 C2627 1 C2628 1 C2629 1 C2630
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402
26 7 =PP1V2_PULSAR
1 C2623 1 C2624 1 C2625 1 C2626

0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402
MASTER: GILA
LAST MODIFIED: APR 09, 04
TABLE_5_HEAD
359S0076 1 PULSAR, PBGA U2600

TABLE_5_ITEM
PULSAR POWER
A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 26 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
29 27 EI_CPU_CLK_P
EI_CPU_CLK_N
EI_CPU_CLK CLOCKS EI_CPU_CLK I86 R2701
0 5%
29 27 EI_CPU_CLK CLOCKS EI_CPU_CLK I87 1 2 PCI_CLK_GP0 8
14 6 EI_CPU1_CLK_P EI_CPU1_CLK CLOCKS EI_CPU1_CLK I116 3.3V 33MHZ
14 6 EI_CPU1_CLK_N EI_CPU1_CLK CLOCKS EI_CPU1_CLK I117
R2761
28 27 EI_NB_CLK_P EI_NB_CLK CLOCKS EI_NB_CLK I96 0
1 2 PCI_CLK_GP1 8
28 27 EI_NB_CLK_N EI_NB_CLK CLOCKS EI_NB_CLK I97 3.3V 33MHZ
5% 402
29 27 EI_CPU_SYNC EI_SYNC CLOCKS I98
28 27 EI_NB_SYNC CLOCKS I99
C2708
D 14 6 EI_CPU1_SYNC EI_CPU1_SYNC CLOCKS I118
0.001UF
50V 1 2 CERM
D
27 24 VSP_NB_CLK_P VSP_NB_CLK CLOCKS VSP_NB_CLK I94
27 24 VSP_NB_CLK_N VSP_NB_CLK CLOCKS VSP_NB_CLK 10% 402
I95
VSP_NB_CLK_P 24 27
C2710 VSP_NB_CLK_N 24 27
48 27 AGP_CLK66M_NB AGP_NB_CLK CLOCKS I100 0.001UF
49 27 AGP_CLK66M_GPU AGP_GPU_CLK CLOCKS 50V 1 2 CERM
I101
10% 402
60 27 HT_CLK66M_NB HT_NB_CLK CLOCKS I102

62 27 HT_CLK66M_SB HT_SB_CLK CLOCKS I103
C2713
0.001UF
50V 1 2 CERM
74 27 PCI_CLK66M_SB_INT CLOCKS_PCI CLOCKS I90 10% 402
74 8 PCI_CLK33M_SB_EXT CLOCKS_PCI CLOCKS I91
EI_CPU_CLK_P 27 29
C2715 EI_CPU_CLK_N 27 29
27 PLS_EXTCLK PLS_XTAL CLOCKS I119 0.001UF
50V 1 2 CERM
10% 402
DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHER

ALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP
NET
SPACING
EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY TYPE
SYM 1 OF 2
GPCLK33_0 L4 PCI_CLK_GP0_R CLOCKS

GPCLK33_1 K4 PCI_CLK_GP1_R CLOCKS
OMIT
VCLKN A2 VSP_NB_CLK_N_C CLOCKS
U2600
C PULSAR
VCLKP B3
HCLKN_0 B10
VSP_NB_CLK_P_C
EI_CPU_CLK_N_C
CLOCKS
CLOCKS
C2700
0.001UF C
50V 1 2 CERM
FSBGA HCLKN_1 C8 EI_CPU1_CLK_N_R CLOCKS 14
10% 402
18 I2C_CLOCK_SCL C1 SCLK HCLKN_2 C4 EI_NB_CLK_N_C CLOCKS EI_NB_CLK_P 27 28
B1 SDATA HCLKP_0 A10 EI_CPU_CLK_P_C CLOCKS C2702 EI_NB_CLK_N 27 28

18 I2C_CLOCK_SDA 0.001UF
R2704 HCLKP_1 B8 EI_CPU1_CLK_P_R CLOCKS 14
50V 1 2 CERM
0 D3
13 CLOCK_RESET_L 1 2 PLS_RESET_L RESET* HCLKP_2 B5 EI_NB_CLK_P_C CLOCKS
NOSTUFF 10% 402
5% 402 0 R2775
C11 XIN GPCLK25_0 J3 6 PLS_CLK_66M_0_R CLOCKS 1 2 NOSTUFF 2.5V 66MHZ TP_PLS_CLK_66M_0 6
PLS_X_IN 0 R2776
GPCLK25_1 J1 6 PLS_CLK_66M_1_R CLOCKS 5% 402 1 2 2.5V 66MHZ TP_PLS_CLK_66M_1 6
PLS_X_OUT B12 XOUT 5% 402 20 R2703

NOSTUFF PCLK25_0 K2 HT_CLK66M_NB_R CLOCKS 1 2 2.5V 66MHZ HT_CLK66M_NB 27 60
R2738 20 R2709
0=IIC ADDR D2/D3 1K E3 ADDRSEL PCLK25_1 L1 RAM_CLK66M_NB_R CLOCKS 1 2 5% 402 2.5V 66MHZ RAM_CLK66M_NB 37
1 2 PLS_X_ADDRSEL
5% 402 0 R2705
1=IIC ADDR D4/D5 5% 402 PCLK33_0 K5 PCI_CLK66M_SB_INT_R CLOCKS 1 2 3.3V 66MHZ PCI_CLK66M_SB_INT 27 74
K3 TEST1 0 R2711
6 TP_PLS_TEST1 PCLK33_1 L6 PCI_CLK_P1_R CLOCKS 5% 402 1 2 3.3V 33MHZ PCI_CLK_P1 8
E11 TEST2 0 R2707
6 TP_PLS_TEST2 PCLK33_2 M7 AGP_CLK66M_GPU_R CLOCKS 1 2 5% 402 3.3V 66MHZ AGP_CLK66M_GPU 27 49
D11 TEST3 0 R2702
6 TP_PLS_TEST3 PCLK33_3 L9 PCI_CLK_P3_R CLOCKS 5% 402 1 2 3.3V 33MHZ PCI_CLK_P3 8
0 R2779
PCLK33_4 M10 PCI_CLK_P4_R CLOCKS 5% 402 1 2 PCI_CLK_P4 8
R2706 249 1 2 402 1% PLS_SCAN_MODE M1 SCAN_MODE 0 R2715 5% 402
HTBEN_0 K11 CPU_HTBEN_R CLOCKS 1 2 1.2V 33MHZ CPU_HTBEN 29 30
18 11 6 PP3V3_PWRON R2744 681 1 2 402 1% PLS_REF15 G11 REF15 HTBEN_1 J12 CPU1_HTBEN_R CLOCKS 14 5% 402
R2740 1K 1 2 402 1% PLS_REF25 J2 REF25 0 R2768
M6 REF33 NBSYNC F12 EI_NB_SYNC_R CLOCKS 1 2 1.2V EI_NB_SYNC 27 28
R2722
1 R2746 1K 1 2 402 1% PLS_REF33
0 R2772 5% 402
1K A5 REF_CML HSYNC_0 J10 EI_CPU_SYNC_R CLOCKS 1 2 1.2V EI_CPU_SYNC 27 29
5% 6 TP_PLS_REF_CML
1/16W HSYNC_1 H11 EI_CPU1_SYNC_R CLOCKS 14 5% 402
MF B6 PRES_CML
NOSTUFF 2 402
R2742 806 1 2 402 1% PLS_PRES_CML 20 R2770
R2748 REFCLK_0 G2 SB_CLK25M_ATA_R CLOCKS NOSTUFF 1 2 2.5V 25MHZ SB_CLK25M_ATA 25
22 R2700
0 REFCLK_1 H1 SATA_CLK25M_R CLOCKS 1 2 5% 402 2.5V 25MHZ TP_SATA_CLK25M
B 25 16 13 SYS_OVERTEMP_L 1
5%
2 PLS_FORCE_P0_L_R F2
C3 PD
FORCESPO*
SLEWING* K9 SLEWING_L_R CLOCKS 1
0 R2720
2 SYS_SLEWING_L 13 25 33
5% 402
6
B
1/16W
MF ERROR* M8 CLOCK_ERROR_L 8 5% 402
402
0 R2717
PCLK12 L11 HT_CLK66M_SB_R CLOCKS 1 2 1.2V 66MHZ HT_CLK66M_SB 27 62
0 R2719
PCLK15 L10 AGP_CLK66M_NB_R CLOCKS 5% 402 1 2 1.5V 66MHZ AGP_CLK66M_NB 27 48
5% 402
3 =PULSAR_POWER_DOWN R2750 47 1 2 402 5% PULSAR_POWER_DOWN_R
NO STUFF
R2752
0 R2724 1K 1
NOSTUFF
2 402 5%
NOSTUFF 27 PLS_EXTCLK 1 2
NOSTUFF
J2700 R2762
1 5%
1/16W R2754
U.FL-R_SMT 24
MF
402 1
0 2
F-ST-SM 5%
3 1/16W NO STUFF 5%
MF
2 402
R2758 1/16W
MF
1 PLS_INTERM 1
330K2 402
NOSTUFF 5%
1/16W R2756
2
R2764
1 MF
402 1
0 2
24 5%
5%
1/16W 1/16W
MF CRITICAL MF
2 402 402
Y2701 MASTER: GILA
25.0000M
1 2 LAST MODIFIED: JULY 12, 04
PLS_X_OUT_B
PLS_X_IN_B 8X4.5MM-SM
A
PULSAR CLOCKS
C2707 1 1 C2705 NOTICE OF PROPRIETARY PROPERTY
A
33PF
5%
33PF
5%
50V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
CERM 2 2 50V
CERM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 402 AGREES TO THE FOLLOWING
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 27 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V2_EI_NB 7 14 18 28
29 28 14 6 EI_CPU_TO_NB_CLK_P EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK I212

1 C2800 1 C2801 1 C2802 1 C2803 1 C2804 1 C2805 1 C2806 1 C2807 1 C2808 1 C2809 1 C2810 1 C2811 1 C2812 1 C2813 1 C2814 1 C2815 1 C2816 1 C2817 29 28 14 6 EI_CPU_TO_NB_CLK_N EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK I213
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 29 28 14 6 EI_NB_TO_CPU_CLK_P EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK I214
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V EI_NB_TO_CPU_CLK_N
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 29 28 14 6 EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK I215
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
29 28 14 6 EI_CPU_TO_NB_AD<0..43> EI_CPU_TO_NB_CAD EI_CPU_TO_NB_AD I216
29 28 14 6 EI_NB_TO_CPU_AD<0..43> EI_NB_TO_CPU_CAD EI_NB_TO_CPU_AD I217
29 28 14 6 EI_CPU_TO_NB_SR_P<0> EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR0 I218

29 28 14 6 EI_CPU_TO_NB_SR_N<0> EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR0
=PP1V5_PWRON_NB_AVDD R2800 I219
D
60 48 37 7
1
2.2 2 PP1V5_PWRON_EI_NB_AVDD MIN_LINE_WIDTH=25MIL
29 28 14 6
29 28 14 6
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_SR1
EI_CPU_TO_NB_SR1
I220
I221
D
VOLTAGE=1.5V MIN_NECK_WIDTH=10MIL
5%
1/16W EI_NB_TO_CPU_SR_P<0> EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR0
MF
603
1 C2818 1 C2819 =PP1V2_EI_NB 7 14 18 28
29 28 14 6
EI_NB_TO_CPU_SR_N<0> EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR0

I222
1UF 0.1UF 29 28 14 6 I223

10% 20% 29 28 14 6 EI_NB_TO_CPU_SR_P<1> EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR1
6.3V 10V I224
2 CERM 2 CERM
EI_NB_TO_CPU_SR_N<1>
F21
J13
H13
H16
F10
D13
D16
B10
B19
402 402 29 28 14 6 EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR1 I225
K4
K8
G2
F7
D4
B7
API VDD_API
APCLK_AVDD
U3 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
U3LITE ZT2847 ZT2857 ZT2867 ZT2807 ZT2817 ZT2827 ZT2837
F15 API0_BCLKIP
V1.0-300MM HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
29 28 14 6 EI_NB_TO_CPU_CLK_P PBGA API0_BCLKOP D6 EI_CPU_TO_NB_CLK_P 6 14 28 29 1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_CLK_N E15 API0_BCLKIN (SYM 1 OF 7)
API0_BCLKON E6 EI_CPU_TO_NB_CLK_N 6 14 28 29
OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<0> F11 API0_ADI0 OMIT
API0_ADO0 J2 EI_CPU_TO_NB_AD<0> 6 14 28 29 ZT2848 ZT2858 ZT2868 ZT2808 ZT2818 ZT2828 ZT2838
29 28 14 6 EI_NB_TO_CPU_AD<1> F12 API0_ADI1 API0_ADO1 H1 EI_CPU_TO_NB_AD<1> 6 14 28 29
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<2> G11 API0_ADI2 API0_ADO2 J1 EI_CPU_TO_NB_AD<2> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<3> H11 API0_ADI3 API0_ADO3 K1 EI_CPU_TO_NB_AD<3> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<4> G12 API0_ADI4 API0_ADO4 E1 EI_CPU_TO_NB_AD<4> 6 14 28 29 ZT2849 ZT2859 ZT2869 ZT2809 ZT2819 ZT2829 ZT2839
29 28 14 6 EI_NB_TO_CPU_AD<5> H12 API0_ADI5 APPLE PI API0_ADO5 F2 EI_CPU_TO_NB_AD<5> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<6> H14 API0_ADI6 INTERFACE API0_ADO6 J4 EI_CPU_TO_NB_AD<6> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<7> G14 API0_ADI7 API0_ADO7 H4 EI_CPU_TO_NB_AD<7> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<8> D9 API0_ADI8 API0_ADO8 G1 EI_CPU_TO_NB_AD<8> 6 14 28 29 ZT2850 ZT2860 ZT2800 ZT2810 ZT2820 ZT2830 ZT2840
29 28 14 6 EI_NB_TO_CPU_AD<9> C9 API0_ADI9 API0_ADO9 H2 EI_CPU_TO_NB_AD<9> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<10> D11 API0_ADI10 API0_ADO10 F1 EI_CPU_TO_NB_AD<10> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<11> E11 API0_ADI11 API0_ADO11 H5 EI_CPU_TO_NB_AD<11> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<12> A10 API0_ADI12 API0_ADO12 H3 EI_CPU_TO_NB_AD<12> 6 14 28 29 ZT2851 ZT2861 ZT2801 ZT2811 ZT2821 ZT2831 ZT2841
C 29 28 14 6
29 28 14 6
EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<14>
A9 API0_ADI13
A8 API0_ADI14
API0_ADO13 J3
API0_ADO14 J5
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
6 14 28 29
6 14 28 29
1 1 1 1 1 1 1 C
29 28 14 6 EI_NB_TO_CPU_AD<15> B9 API0_ADI15 API0_ADO15 J6 EI_CPU_TO_NB_AD<15> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<16> C11 API0_ADI16 API0_ADO16 E3 EI_CPU_TO_NB_AD<16> 6 14 28 29 ZT2852 ZT2862 ZT2802 ZT2812 ZT2822 ZT2832 ZT2842
29 28 14 6 EI_NB_TO_CPU_AD<17> B11 API0_ADI17 API0_ADO17 F4 EI_CPU_TO_NB_AD<17> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<18> A11 API0_ADI18 API0_ADO18 E2 EI_CPU_TO_NB_AD<18> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<19> A12 API0_ADI19 API0_ADO19 F5 EI_CPU_TO_NB_AD<19> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<20> B12 API0_ADI20 API0_ADO20 H6 EI_CPU_TO_NB_AD<20> 6 14 28 29 ZT2853 ZT2863 ZT2803 ZT2813 ZT2823 ZT2833 ZT2843
29 28 14 6 EI_NB_TO_CPU_AD<21> C12 API0_ADI21 API0_ADO21 J7 EI_CPU_TO_NB_AD<21> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<22> D12 API0_ADI22 API0_ADO22 F3 EI_CPU_TO_NB_AD<22> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<23> E12 API0_ADI23 API0_ADO23 J8 EI_CPU_TO_NB_AD<23> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<24> A13 API0_ADI24 API0_ADO24 F6 EI_CPU_TO_NB_AD<24> 6 14 28 29 ZT2854 ZT2864 ZT2804 ZT2814 ZT2824 ZT2834 ZT2844
29 28 14 6 EI_NB_TO_CPU_AD<25> A14 API0_ADI25 API0_ADO25 E5 EI_CPU_TO_NB_AD<25> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<26> B14 API0_ADI26 API0_ADO26 D5 EI_CPU_TO_NB_AD<26> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<27> C14 API0_ADI27 API0_ADO27 E4 EI_CPU_TO_NB_AD<27> 6 14 28 29 OMIT OMIT OMIT OMIT OMIT OMIT OMIT
29 28 14 6 EI_NB_TO_CPU_AD<28> A16 API0_ADI28 API0_ADO28 D8 EI_CPU_TO_NB_AD<28> 6 14 28 29 ZT2855 ZT2865 ZT2805 ZT2815 ZT2825 ZT2835 ZT2845
29 28 14 6 EI_NB_TO_CPU_AD<29> A15 API0_ADI29 API0_ADO29 A5 EI_CPU_TO_NB_AD<29> 6 14 28 29
1 1 1 1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<30> B15 API0_ADI30 API0_ADO30 C2 EI_CPU_TO_NB_AD<30> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<31> C15 API0_ADI31 API0_ADO31 C3 EI_CPU_TO_NB_AD<31> 6 14 28 29 OMIT OMIT OMIT OMIT

29 28 14 6 EI_NB_TO_CPU_AD<32> H15 API0_ADI32 API0_ADO32 C5 EI_CPU_TO_NB_AD<32> 6 14 28 29 ZT2806 ZT2816 ZT2826 ZT2836
29 28 14 6 EI_NB_TO_CPU_AD<33> G15 API0_ADI33 API0_ADO33 C6 EI_CPU_TO_NB_AD<33> 6 14 28 29
HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10 HOLE-VIA-20R10
1 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<34> F17 API0_ADI34 API0_ADO34 B2 EI_CPU_TO_NB_AD<34> 6 14 28 29
29 28 14 6 EI_NB_TO_CPU_AD<35> G17 API0_ADI35 API0_ADO35 D1 EI_CPU_TO_NB_AD<35> 6 14 28 29 OMIT OMIT OMIT

29 28 14 6 EI_NB_TO_CPU_AD<36> G18 API0_ADI36
H18 API0_ADI37
API0_ADO36 B1 EI_CPU_TO_NB_AD<36> 6 14 28 29
=PP1V2_EI_NB 7 14 18 28
ZT2846
HOLE-VIA-20R10
ZT2856
HOLE-VIA-20R10
ZT2866
HOLE-VIA-20R10
29 28 14 6 EI_NB_TO_CPU_AD<37> API0_ADO37 C1 EI_CPU_TO_NB_AD<37> 6 14 28 29
NOSTUFF 1 1 1
29 28 14 6 EI_NB_TO_CPU_AD<38> F18 API0_ADI38 API0_ADO38 A6 EI_CPU_TO_NB_AD<38> 6 14 28 29
EI_NB_TO_CPU_AD<39> E18 API0_ADI39 API0_ADO39 C8 EI_CPU_TO_NB_AD<39> R2802

1
B
29 28 14 6
29 28 14 6 EI_NB_TO_CPU_AD<40> A17 API0_ADI40

A18 API0_ADI41
API0_ADO40 A2 EI_CPU_TO_NB_AD<40>
6 14 28 29
6 14 28 29 1%
100
1/16W
B
29 28 14 6 EI_NB_TO_CPU_AD<41> API0_ADO41 B3 EI_CPU_TO_NB_AD<41> 6 14 28 29 NOSTUFF MF
29 28 14 6 EI_NB_TO_CPU_AD<42> B17 API0_ADI42 API0_ADO42 A7 EI_CPU_TO_NB_AD<42> 6 14 28 29
1 C2821 2 402 MIN_LINE_WIDTH=25MIL
C17 API0_ADI43 0.001UF EI_APCLK_VREF MIN_NECK_WIDTH=10MIL
29 28 14 6 EI_NB_TO_CPU_AD<43> API0_ADO43 B8 EI_CPU_TO_NB_AD<43> 6 14 28 29
10% VOLTAGE=0.6V
50V NOSTUFF NOSTUFF NOSTUFF
D17 API0_SRIP0 2 CERM NOSTUFF
EI_NB_TO_CPU_SR_P<0> API0_SROP0 A3 EI_CPU_TO_NB_SR_P<0> R2801
1 1
R2803 R28041
29 28 14 6
EI_NB_TO_CPU_SR_N<0> A19 API0_SRIN0 API0_SRON0 A4 EI_CPU_TO_NB_SR_N<0>

6 14 28 29 402
100
1 C2820 121 121
29 28 14 6 6 14 28 29
1% 0.1UF 1% 1%
29 28 14 6 EI_NB_TO_CPU_SR_P<1> E17 API0_SRIP1 API0_SROP1 B5 EI_CPU_TO_NB_SR_P<1> 6 14 28 29 1/16W 20% 1/16W 1/16W
10V
PLACE R2805 AND R2806 B18 API0_SRIN1 MF 2 CERM MF MF
29 28 14 6 EI_NB_TO_CPU_SR_N<1> API0_SRON1 B6 EI_CPU_TO_NB_SR_N<1> 6 14 28 29
2 402 402 2 402 2 402
NEAR U3LITE
29 14 6 EI_QACK_L D14 API_QACK0 API_QREQ0 E14
R2805 E8 API0_APSYNC API_APCLKP D18
EI_NB_CLK_P
EI_NB_CLK_P 27
0 H17 API0_SE EI_NB_CLK_N
27 EI_NB_SYNC 1 2 NB_APSYNC API_APCLKN C18 EI_NB_CLK_N 27
402
API_CSTP F14 CPU_CHKSTOP_L 29
NOSTUFF
R2806
0 API_APCLK_AVSS
29 EI_SYNC_FROM_NB 1 2
G20
402
30 29 14 6 EI_SE
QREQ_L HACK QREQ TO SMU MASTER: GILA

28 7 =PP3V3_PWRON_EI LAST MODIFIED: JULY 14, 04
28 7 =PP3V3_PWRON_EI
CRITICAL NOSTUFF
C2850 1
0.1UF
U2850
74LVC1G66
R2898
1
10K
U3LITE APPLE PI
A
20%
10V
CERM 2
402 VCC
5 SOT23-5
TI
5%
1/16W
MF
2 402 NOTICE OF PROPRIETARY PROPERTY
A
30 29 14 6 EI_QREQ_L 1 2 EI_NB_QREQ_L THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SMU_QREQ 13 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
4 NOSTUFF 3
POST-RAMP QUAL
25 24 13 SMU_SUSPENDREQ_L R2899 NOSTUFF
180 II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_HEAD
GND
1 2 EI_NB_QREQ_L_R 1 Q2899 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
PART NUMBER 3 5% 2N3904
TABLE_ALT_ITEM
NOSTUFF R28511 1/16W
MF 2
SM
353S0920 353S0867 U2850 PERICOM ANALOG SWITCH CRITICAL R2850 10K 402
353S0924 353S0867 U2850 MAXIM ANALOG SWITCH

TABLE_ALT_ITEM
1
0 2
5%
1/16W
MF
D 051-6482 I
402 2 APPLE COMPUTER INC.
5% SCALE SHT OF
1/16W
MF
402
NONE 28 103
PLACE QREQ CIRCUITS BETWEEN CPU AND U3LITE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE NEAR PROCESSOR.
PLACE AT PROCESSOR PINS. 35 31 30 29 18 14 7 =PP1V2_EI_CPU

NOSTUFF
NOSTUFF
R2903 R2909
1
100 MORE PROCESSOR DECOUPLING ON PAGES 31 & 32

D 27 EI_CPU_CLK_P 1
46.4 2 1%
1/16W
MF
36 32 31 7 =PPVCORE_CPU
D
1%
1/16W 2 402
MF
402 SYSCLK_TERM
NOSTUFF
1 C2953 1 C2947 1 C2945 1 C2939 1 C2937 1 C2928 1 C2924 1 C2920 1 C2914 1 C2912
NOSTUFF NOSTUFF VOLTAGE=0.6V 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
R2901 1 C2901 R2907
1 10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
10%
6.3V
2 CERM
1
46.4 2 0.22UF 100 402 402 402 402 402 402 402 402 402 402
27 EI_CPU_CLK_N 1%
20% 1/16W
1% 6.3V
2 X5R MF
1/16W
MF 402 2 402
402 1 C2954 1 C2948 1 C2946 1 C2940 1 C2938 1 C2929 1 C2925 1 C2921 1 C2915 1 C2913
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
T22
R22 402 402 402 402 402 402 402 402 402 402
SYSCLK* SYSCLK
28 14 6 EI_NB_TO_CPU_CLK_P EI_CPU_TO_NB_CLK_P
E24 EI_CLKI
C2955 C2951 C2949 C2943 C2941 C2930 C2926 C2922 C2918 C2916
D3
EI_CLKO 6 14 28
28 14 6 EI_NB_TO_CPU_CLK_N D24 OMIT EI_CLKO* E3 EI_CPU_TO_NB_CLK_N 6 14 28
1 1 1 1 1 1 1 1 1 1
EI_CLKI*
28 14 6 EI_NB_TO_CPU_AD<0> H21
EI_ADI0 CRITICAL EI_ADO0 N3 EI_CPU_TO_NB_AD<0> 6 14 28
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
28
28
28
14
14
14
6 EI_NB_TO_CPU_AD<1>
J21
H22
J22
EI_ADI1
EI_ADI2
EI_ADI3
U2900 EI_ADO1
EI_ADO2
EI_ADO3
H2
K3
L1
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
6
6
6
14
14
14
28
28
28
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
6.3V
2 CERM
402
CBGA EI_ADO4
C13 M3
28 14 EI_ADI4 6 14 28
28 14 6 EI_NB_TO_CPU_AD<5> A13
EI_ADI5 EI_ADO5 K4 EI_CPU_TO_NB_AD<5> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<6> K22
EI_ADI6 EI_ADO6 K2 EI_CPU_TO_NB_AD<6> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<7> H23 (1 OF 3) EI_ADO7 H3 EI_CPU_TO_NB_AD<7> 6 14 28
EI_ADI7
NEO-10S-REV2
1.8GHZ-76C
6 EI_NB_TO_CPU_AD<8> EI_CPU_TO_NB_AD<8>
28 14 EI_ADO8
C2956 C2952 C2950 C2944 C2942 C2931 C2927 C2923 C2919 C2917
J24 H1 6 14 28
EI_ADI8 1 1 1 1 1 1 1 1 1 1
28 14 6 EI_NB_TO_CPU_AD<9> G20
EI_ADI9 EI_ADO9 G4 EI_CPU_TO_NB_AD<9> 6 14 28
28
28
14
14 6 EI_NB_TO_CPU_AD<11>
F23
G21
EI_ADI10
EI_ADI11
EI_ADO10
EI_ADO11
F2
F4 EI_CPU_TO_NB_AD<11>
6
6
14
14
28
28
28 14 6 EI_NB_TO_CPU_AD<12> D22
EI_ADI12 EI_ADO12 E2 EI_CPU_TO_NB_AD<12> 6 14 28
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
28 14 6 EI_NB_TO_CPU_AD<13> G24
EI_ADI13 EI_ADO13 G3 EI_CPU_TO_NB_AD<13> 6 14 28 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
28 14 6 EI_NB_TO_CPU_AD<14> G19
EI_ADI14 EI_ADO14 B8 EI_CPU_TO_NB_AD<14> 6 14 28 402 402 402 402 402 402 402 402 402 402
28 14 6 EI_NB_TO_CPU_AD<15> B15
EI_ADI15 EI_ADO15 D11 EI_CPU_TO_NB_AD<15> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<16> A14
EI_ADI16 EI_ADO16 E12 EI_CPU_TO_NB_AD<16> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<17> C15
EI_ADI17 EI_ADO17 A11 EI_CPU_TO_NB_AD<17> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<18> D15
EI_ADI18 EI_ADO18 B10 EI_CPU_TO_NB_AD<18> 6 14 28
C2900 C2960 C2959 C2958 C2957 C2936 C2935 C2934 C2933 C2932
28 14 A16 EI_ADO19 C11
EI_ADI19 6 14 28
28 14 6 EI_NB_TO_CPU_AD<20> C22 EI_ADO20 C1 EI_CPU_TO_NB_AD<20> 6 14 28
1 1 1 1 1 1 1 1 1 1
EI_ADI20
28
28
14
E20
E21
EI_ADI21 EI_ADO21
EI_ADO22
C5
B2 EI_CPU_TO_NB_AD<22>
6
6
14
14
28
28
C
EI_ADI22
C 28 14 6 EI_NB_TO_CPU_AD<23> B23 EI_ADO23 D6 EI_CPU_TO_NB_AD<23> 6 14 28

10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
EI_ADI23 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
28 14 6 EI_NB_TO_CPU_AD<24> B24
EI_ADI24 EI_ADO24 A5 EI_CPU_TO_NB_AD<24> 6 14 28 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
28 14 6 EI_NB_TO_CPU_AD<25> F21
28 14 6 EI_NB_TO_CPU_AD<26> B17
EI_ADO26 D2 EI_CPU_TO_NB_AD<26> 6 14 28
402 402 402 402 402 402 402 402 402 402
EI_ADI26
28 14 6 EI_NB_TO_CPU_AD<27> B19
EI_ADI27 EI_ADO27 D8 EI_CPU_TO_NB_AD<27> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<28> C14
EI_ADI28 EI_ADO28 C12 EI_CPU_TO_NB_AD<28> 6 14 28
28 14 6 EI_NB_TO_CPU_AD<29> C17
28 14 EI_ADO30
C2911 C2910 C2909 C2908 C2907 C2906 C2905 C2904 C2903 1C2902
D18 B6 6 14 28
EI_ADI30 1 1 1 1 1 1 1 1 1
28 14 6 EI_NB_TO_CPU_AD<31> B21
EI_ADI31 EI_ADO31 B4 EI_CPU_TO_NB_AD<31> 6 14 28
28
28
14
D20
A22
EI_ADI32
EI_ADI33
EI_ADO32
EI_ADO33
C4
C7 EI_CPU_TO_NB_AD<33>
6
6
14
14
28
28
28 14 6 EI_NB_TO_CPU_AD<34> C19
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
28 14 6 EI_NB_TO_CPU_AD<35> C18
EI_ADI35 EI_ADO35 C8 EI_CPU_TO_NB_AD<35> 6 14 28 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
28 14 6 EI_NB_TO_CPU_AD<36> A21
EI_ADI36 EI_ADO36 C6 EI_CPU_TO_NB_AD<36> 6 14 28 402 402 402 402 402 402 402 402 402 402
28 14 6 EI_NB_TO_CPU_AD<37> A23
28 14 6 EI_NB_TO_CPU_AD<38> A20
28 14 6 EI_NB_TO_CPU_AD<39> A18
28 14 6 EI_NB_TO_CPU_AD<40> A15
28 14 6 EI_NB_TO_CPU_AD<41> A17
28
28
14
C16
A19
EI_ADI42
EI_ADI43
EI_ADO42
EI_ADO43
A8
A6 EI_CPU_TO_NB_AD<43>
6
6
14
14
28
28
R2910
0
28 14 6 EI_NB_TO_CPU_SR_P<0> L24
EI_SRI0 EI_SRO0 L3 EI_CPU_TO_NB_SR_P<0> 6 14 28 1 2 EI_CPU_SYNC 27
28 14 6 EI_NB_TO_CPU_SR_N<0> K24
EI_SRI0* EI_SRO0* L2 EI_CPU_TO_NB_SR_N<0> 6 14 28
28 14 6 EI_NB_TO_CPU_SR_P<1> L21
EI_SRI1 EI_SRO1 G1 EI_CPU_TO_NB_SR_P<1> 6 14 28 5%
28 14 6 EI_NB_TO_CPU_SR_N<1> L22
EI_SRI1* EI_SRO1* F1 EI_CPU_TO_NB_SR_N<1> 6 14 28 1/16W
MF
28 14 6 EI_QACK_L V21
QACK* QREQ* AB12 EI_QREQ_L 6 14 28 30 402
29 14 8 6 CHKSTOP_L R20
CHKSTOP* INT* AB19 CPU_INT_L 6 14 25 30 NOSTUFF
30 29 27 CPU_HTBEN AD17
TBEN
R2911
MATCH TO SYSCLK 0
6 TP_PSYNCOUT AD14
APSYNCOUT APSYNCIN AA10 CPU_APSYNC 1 2 EI_SYNC_FROM_NB 28
5%
30 14 6 CPU_HRESET_L V20
HRESET* IIC_SCL AA20 I2C_CPU_A_SCL 18 1/16W
IIC_SDA Y21 I2C_CPU_A_SDA 18 MF
30 25 CPU_SRESET_L AB4
SRESET* 402
I2CGO N22 I2CGO 30
30 PROC_THERM_INT_L V22
THERM_INT*
CKTERMDIS AA14 CKTERMDIS_L 30
30 PROCID0 L19
PROCID0
30 PROCID1 M19
PROCID1 EI_DISABLE P20 EI_DISABLE 30
30 PROCID2 M18
PROCID2
BUSCFG0 AA19 BUSCFG0 30
30 28 14 6 EI_SE N21
TRIGGER_IN BUSCFG1 AC19 BUSCFG1 30
14 6 TP_PROC_TRIGGER_OUT N19
TRIGGER_OUT BUSCFG2 AB16 BUSCFG2 30
6 TP_AFN AA12
AFN ATTENTION AD12 TP_ATTENTION 6
30 AVPRESET_L W23
AVPRESET* GPUL_DBG AA22 GPUL_DBG 30
30 BIMODE_L AC24
BIMODE* JTAGMODE W4 JTAGMODE_SPARE2 30
C1UNDGLOBAL
B B
AC16
30 C1UNDGLOBAL
30 C2UNDGLOBAL AC15
C2UNDGLOBAL TCK AD21 JTAG_CPU_TCK 18 30
30 DI2_L U24
DI2* TDI AB21 JTAG_CPU_TDI 18 30
TDO AD13 JTAG_CPU_TDO 18 30
30 LSSDMODE AB5
LSSDMODE TMS AD22 JTAG_CPU_TMS 18 30
30 LSSDSCANENABLE U19
LSSDSCANENABLE TRST* W20 JTAG_CPU_TRST_L 30
30 LSSDSTOPC2ENABLE AD8
LSSDSTOPC2ENABLE
30 LSSDSTOPC2STARENABLE AD7
LSSDSTOPC2STARENABLE BYPASS* V24 CPU_BYPASS_L 30
30 LSSDSTOPENABLE AD11
LSSDSTOPENABLE PLLLOCK T20 PLLLOCK 8
29 14 6 MCP_L AD18
PLLMULT AA8 PLLMULT 30
PROCESSOR IIC ADDRESS:
MCP*
PLLRANGE0 AB7 PLLRANGE0 30
6 TP_PSRO1 V23 PLLRANGE1 AA9 PLLRANGE1 30
80,84
PSRO1
6 TP_PSRO2 V5
PSRO2 PLLTEST W22 PLLTEST 30
30 PULSESEL0 AC9
PULSESEL0 PLLTESTOUT T19 PLLTESTOUT 30
30 PULSESEL1 AB11
PULSESEL1
30 PULSESEL2 AC10
PULSESEL2 SPARE AA13 CPU_SPARE 30
30 RAMSTOPENABLE AB6
RAMSTOPENABLE
30 14 6 RI_L AA5
RI*
30 14 6 SYNCENABLE AB24
SYNCENABLE*
35 31 30 29 18 14 7 =PP1V2_EI_CPU
NOSTUFF 1 1
R2906 R2908
1K 1K MASTER: GILA
R2905 5% 5%
1
49.9 2 1/16W
MF
1/16W
MF
30 29 27 CPU_HTBEN
1%
R2902 2 402 2 402
1/16W
MF
402
1
0
2 CHKSTOP_L 6 8 14 29
NEO APPLE PI
A PLACE BY PROCESSOR PIN. 28 CPU_CHKSTOP_L
5%
1/16W
MF
A
NOSTUFF
R2904 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0
1 2 MCP_L 6 14 29 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W
402
D 051-6482 I
PROCESSOR LOGIC I/O APPLE COMPUTER INC.
SCALE SHT OF
NONE 29 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.
TABLE_5_HEAD
*
TABLE_5_ITEM
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3034 EI_3TO1 SYSCLK * 12

TABLE_5_ITEM
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3018 EI_2TO1 SYSCLK * 8
=PP1V2_EI_CPU 7 14 18 29 30 31 35 SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.
R3039 TABLE_5_HEAD
1
0 2
35 31 30 29 18 14 7 =PP1V2_EI_CPU PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
29 JTAGMODE_SPARE2
TABLE_5_ITEM
5% NOSTUFF 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3026,R3028 EI_2TO1 PROC / 2

1/16W
R3009 MF
402
R3000 R3001 *
TABLE_5_ITEM
PROC / 3
C1UNDGLOBAL 0 0 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3026,R3012 EI_3TO1
D
29
NOSTUFF
R3077 R3043
29 JTAG_CPU_TRST_L 2
1K
5%
1 R3045
1K
1
5%
1/16W
2 1
5%
1/16W
2
114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3010,R3028 NOSTUFF
TABLE_5_ITEM
PROC / 4 D
LSSDMODE 1 2
JTAG_SEL
29
TABLE_5_ITEM
1K 1K 1/16W MF MF
1 2 1 2 MF 402 402 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3024,R3010,R3012 NOSTUFF PROC / 6
402 5%
1/16W TABLE_5_ITEM
5% 5% MF 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3026,R3028 NOSTUFF PROC / 8

1/16W 1/16W 402
MF MF R3093 R3095 TABLE_5_ITEM
29 C2UNDGLOBAL
402 402
JTAG_CPU_TDO 1
1K 2
R3041 29 18 JTAG_CPU_TCK 1
10K 2
114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3026,R3012 NOSTUFF PROC / 12
29 18
LSSDSCANENABLE 1
1K 2
TABLE_5_ITEM
NOSTUFF 5% 29 5% 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3010,R3028 NOSTUFF PROC / 16

R3079 R3069 1/16W
MF 5% 1/16W
MF
TABLE_5_ITEM
1
1K 2 1
1K 2 402 1/16W 402 114S1103 3 RES,1K OHM,1/16W,5%,0402 R3008,R3010,R3012 NOSTUFF
MF
402
5% 5%
R3031 R3097
1/16W
MF
1/16W
MF 1K R3047 29 18 JTAG_CPU_TDI 1
10K 2 SELECT ELASTIC MODE OR BYPASS.
402 402 29 BIMODE_L 1 2
1
1K 2
29 LSSDSTOPC2ENABLE 5%
TABLE_5_HEAD
29 PLLTEST 5% 1/16W PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

1/16W 5% MF
MF 1/16W
NOSTUFF
*
TABLE_5_ITEM
402
R3063 R3061 402 MF
402
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3036
1K 1K R3033 R3099 TABLE_5_ITEM
1 2 1 2
1K R3049 29 18 JTAG_CPU_TMS 1
10K 2
114S1103 1 RES,1K OHM,1/16W,5%,0402 R3020 NOSTUFF BYPASS MODE
5% 5% 29 DI2_L 1 2 1K
1/16W
MF
1/16W
MF 5%
29 LSSDSTOPC2STARENABLE 1 2 5% SELECT PLL FREQUENCY RANGE.
402 402 1/16W 5% 1/16W TABLE_5_HEAD
CKTERMDIS_L MF 1/16W MF
29 402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
402 MF
NOSTUFF 402 TABLE_5_ITEM
R3075 R3073 R3035 R3051

114S1103 2 RES,1K OHM,1/16W,5%,0402 R3030,R3032 CPU_PLL_LOW
1K 1K 1K TABLE_5_ITEM
1 2 1 2 29 14 6 RI_L 1 2
29 LSSDSTOPENABLE 1
1K 2
NOSTUFF >= 1.8 GHZ * 114S1103 2 RES,1K OHM,1/16W,5%,0402 R3030,R3016 CPU_PLL_HIGH
5%
1/16W
5%
1/16W
5%
1/16W 5% R3071 <= 1.6 GHZ * 114S1103 2 RES,1K OHM,1/16W,5%,0402 R3014,R3032 CPU_PLL_MEDIUM
TABLE_5_ITEM
MF
402
MF
402
MF
402
1/16W
MF PLLTESTOUT 1
1K 2
29
TABLE_5_ITEM
29 GPUL_DBG 402 114S1103 2 RES,1K OHM,1/16W,5%,0402 R3014,R3016 NOSTUFF RESERVED

NOSTUFF R3091 R3053
5%
1/16W
R3040 R3042 1K MF
29 25 14 6 CPU_INT_L 1 2 10K 402
C 1
5%
1K 2 1
1K
5%
2 5%
1/16W
MF
29 28 14 6 EI_QREQ_L 1
5%
1/16W
2
TABLE_5_HEAD
TABLE_5_ITEM
C
1/16W 1/16W 402 MF 114S1103 1 RES,1K OHM,1/16W,5%,0402 R3022 AVPRESET OFF
MF MF 402
402 402
R3065
TABLE_5_ITEM
1K
R3037 114S1103 1 RES,1K OHM,1/16W,5%,0402 R3038 NOSTUFF AVPRESET ON
29 PROC_THERM_INT_L 1 2 1
1K 2
29 14 6 SYNCENABLE
5% 5%
1/16W
MF 1/16W
MF
* STUFF THESE ON Q45.
402 402
R3085 R3055
CPU_SRESET_L 1
1K 2 29 RAMSTOPENABLE 1
1K 2
SYSTEM CONFIGURATION
29 25
5% 5%
1/16W 1/16W =PP1V2_EI_CPU 7 14 18 29 30 31 35
MF MF
402 402 35 31 30 29 18 14 7 =PP1V2_EI_CPU
NOSTUFF
R3067
1
R3068
R3087 10K
1K 5%
1K 29 CPU_SPARE 1 2 1/16W
I2CGO 1 2 MF
29
5% 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT
5% 1/16W 2 402 R3008 R3010 R3012 R3014 R3016 R3018 R3020 R3022
1/16W MF 1K 1K 1K 1K 1K 1K 1K 1K
MF 402 5% 5% 5% 5% 5% 5% 5% 5%
402 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
R3081 MF MF MF MF MF MF MF MF
R3089 EI_SE 1
1K 2 BUSCFG0
2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
1
1K 2
29 28 14 6 29
29 27 CPU_HTBEN 5% BUSCFG1
29
5% 1/16W
1/16W MF 29 BUSCFG2
MF 402
402 29 PLLRANGE0
R3003 29 PLLRANGE1
PULSESEL0 1
1K 2 29 PLLMULT
29
EI_DISABLE
B =PP1V2_EI_CPU
2
7 14 18 29 30 31 35
5%
1/16W
MF
402
29
29 AVPRESET_L B
R3083
1K 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT
5%
1/16W R3005 R3024
1K
R3026
1K
R3028
1K
R3030
1K
R3032
1K
R3034
1K
R3036
1K
R3038
1K
MF 1K
1 402 29 PULSESEL1 1 2 5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
5% MF MF MF MF MF MF MF MF
CPU_HRESET_L 6 14 29
1/16W 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
MF
402
6
D
Q3000 R3007
2N7002DW 1
1K 2
29 PULSESEL2
2 SOT-363
13 CPU_HRESET G S 5%
1/16W
MF
1 402
R3002
1
1K 2
29 PROCID0
5%
1/16W
MF
402
=PP1V2_EI_CPU 7 14 18 29 30 31 35
R3004 MASTER: GILA
1
1K 2
29 PROCID1
1
R3059 5%
1K 1/16W
5%
1/16W
MF
MF
402
CPU STRAPS
A 2 402
CPU_BYPASS_L
R3006 NOTICE OF PROPRIETARY PROPERTY
A
29
1
1K 2
29 PROCID2
3 5% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

NOSTUFF 1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D
Q3000
2N7002DW
1
R3057 MF
402
1K
5 SOT-363 5% II NOT TO REPRODUCE OR COPY IT
13 CPU_BYPASS G S 1/16W
4 2 402
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 30 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
36 32 31 29 7 =PPVCORE_CPU =PP1V2_EI_CPU 7 14 18 29 30 35
VOLTAGE=1.2V
MIN_NECK_WIDTH=8MIL
7 =PP2V5_RUN_CPU
NOSTUFF
L3101 NET_SPACING_TYPE=PROC_DIFF 1 C3117 1 C3116 1 C3115 1 C3114 1 C3111 1 C3106 1 C3105 1 C3103
R3132 60-OHM-EMI DIFFERENTIAL_PAIR=P_TDD
10UF 10UF 10UF 10UF 1UF 1UF 1UF 1UF
1
2.2 2 1 2
20% 20% 20% 20% 10% 10% 10% 10%
35 PP2V5_RUN_CPU_AVDD_R PP2V5_RUN_CPU_AVDD_R_L TDIODE_POS 36 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VOLTAGE=2.5V SM VOLTAGE=2.5V MIN_NECK_WIDTH=8MIL 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
5% MIN_LINE_WIDTH=25MIL MIN_LINE_WIDTH=25MIL
1/16W MIN_NECK_WIDTH=10MIL 0805 MIN_NECK_WIDTH=10MIL 805 805 805 805 402 402 402 402
MF
OMIT 603 P24 R2
D
Y1
=PP5V_RUN_CPU
D 8 7 6 3
VR3100
MM1572JN
R3101
2.2
1 C3199
1UF A1
AVDD KPVDD1 KPVDD2
A3 OMIT
1 C3112
1UF
1 C3109
1UF
1 C3107
1UF
1 C3104
1UF
SOT-25A PP2V5_RUN_CPU_AVDD 1 2 A24 OMIT B1 CRITICAL
10% 10% 10% 10% 10%
U2900
B11 B12
1 5 MIN_NECK_WIDTH=10MIL
VOLTAGE=2.5V
5%
1/16W
1 C3100 2 6.3V
CERM
B13
B16
CRITICAL B14
B18
P1
P11
P18
P2 GND_Z_OUT
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
VIN VOUT
C3102 0.22UF 402 31 402 402 402 402
3 CPU_AVDD_EN 3 CONT NOISE 4 CPU_AVDD_NOISE

MF
603
1
10UF
20%
20%
6.3V
2 X5R
B20
B3
B7
U2900 B22
B5
B9
P13
P15
P17
CBGA
(3 OF 3)
P22
P4
P6
2 6.3V 402
C2
C20 CBGA C21
C23
P19
P21
P8
GND_Z_SENSE
1.8GHZ-76C
R1
C3113 C3110 C3108
NEO-10S-REV2
CERM 31
GND C24 C3 P23 R11 1 1 1
805 D13 (2 OF 3) D1 P3 R13
2
C3150 1UF 1UF 1UF
1.8GHZ-76C
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8 1
NEO-10S-REV2
D17 D10 P5 R15
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8 D19 D12 P7 R17 10% 10% 10%
1 C3148 10UF 6.3V 6.3V 6.3V
1 C3149 20%
D21
D23
D14
D16
P9
R10
R19
R21
2 CERM 2 CERM 2 CERM
1UF 0.01UF 2 6.3V
CERM
D5 D4 R12 R23 402 402 402
20%
20% D7 E11 R14 R3
16V 805 D9 E13 R16 R5
2 10V
CERM CERM 2 E1 E15 R18 R7
603 402 E10 E17 R4 R9
E14 E19 R6 T10 1 C3126 1 C3120 1 C3118
E16
E18
E23
E5
R8
T1
T12
T14 1UF 1UF 1UF
E22 E7 T11 T16 10% 10% 10%
E4 E9 T13 T18 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
E6 F10 T15 T24
E8 F12 T17 T4 402 402 402
F11 F14 T21 T6
TABLE_5_HEAD
F13 F16 T23 T8

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION F15 F18 T3 U1
F17 F20 T5 U11
CRITICAL 353S0806 1 VREG MM1572 2.6V VR3100 CPU_AVDD_2V6

TABLE_5_ITEM
F19
F3
F22
F24
T7
T9
U13
U15
1 C3127 1 C3121 1 C3119
F5 F6 U10 U17 1UF 1UF 1UF
TABLE_5_ITEM
F7 F8 U12 U21 10% 10% 10%
6.3V 6.3V 6.3V
CRITICAL 353S0886 1 VREG MM1572 2.7V VR3100 CPU_AVDD_2V7 F9 G11 U14 U23 2 CERM 2 CERM 2 CERM
G10 G13 U16 U3
TABLE_5_ITEM
G12 G15 U18 U5 402 402 402
CRITICAL 353S0807 1 VREG MM1572 2.8V VR3100 CPU_AVDD_2V8 G14 G17 U2 U7
G16 G2 U20 U9
G18 G23 U22 V10
G22 G5 U4 V12
G6 G7 U6 V14 1 C3128 1 C3124 1 C3122
G8
H11
G9
H10
U8
V1
V16
V18 1UF 1UF 1UF
H13 H12 V11 V2 10% 10% 10%
H15 H14 V13 V4 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM
H17 H16 V15 V6
H19 H18 V17 V8 402 402 402
C H24
H5
H7
H9 VCORE GND
H20
H4
H6
H8
V19
V3
V7
V9
VCORE
X100
GND
X99
W1
W11
W13
W15
C
J1
J10
X105 X105 J11
J13
W10
W12
W17
W19
1 C3129 1 C3125 1 C3123
J12 J15 W14 W21 1UF 1UF 1UF
J14 J17 W16 W3 10% 10% 10%
J16 J19 W18 W5 6.3V 6.3V 6.3V
J18 J23 W2 W7
J2 J3 W24 W9 402 402 402
J20 J5 W6 Y10
J4 J7 W8 Y12
J6 J9 Y11 Y14
J8 K1 Y13 Y16
K11 K10 Y15 Y18 1 C3136 1 C3131 1 C3130
K13
K15
K12
K14
Y17
Y19
Y2
Y20 1UF 1UF 1UF
K17 K16 Y22 Y24 10% 10% 10%
K19 K18 Y23 Y4 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM
K21 K20 Y3 Y6
K23 K6 Y5 Y8 402 402 402
K5 K8 Y7 AA11
K7 L11 Y9 AA15
K9 L13 AA16 AA17
L10 L15 AA18 AA21
L12
L14
L17
L23
AA2
AA24
AA23
AA3
1 C3137 1 C3134 1 C3132
L16 L5 AA4 AA7 1UF 1UF 1UF
L18 L7 AA6 AB10 10% 10% 10%
L20 L9 AB1 AB14 6.3V 6.3V 6.3V
L4 M10 AB13 AB18
L6 M12 AB15 AB2 402 402 402
L8 M14 AB17 AB20
M1 M16 AB23 AB22
M11 M2 AB3 AB8
M13 M20 AB9 AC1
M15 M22 AC12 AC11 1 C3138 1 C3135 1 C3133
M17
M21
M24
M4
AC14
AC18
AC13
AC17 1UF 1UF 1UF
M23 M6 AC2 AC21 10% 10% 10%
M5 M8 AC20 AC23 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
M7 N1 GND_SPARE_GND 31 AC22 AC3
402 402 402
M9 N11 AC4 AC5
N10 N13 AC6 AC7
N12 N15 AC8 AD10
N14 N17 AD1 AD16
N16 N23 AD15 AD2
N18
N2
N5
N7
AD19
AD23
AD20
AD24
1 C3145 1 C3141 1 C3139
N20 N9 AD3 AD4 1UF 1UF 1UF
N24 P10 AD5 AD6 10% 10% 10%
6.3V 6.3V 6.3V
B
N4 P12 AD9
B
N6 P14
N8 P16 402 402 402
AGND KPGND1 KPGND2

R24 AA1 T2
1 C3146 1 C3142 1 C3140
1UF 1UF 1UF
10% 10% 10%
GND_CPU_AVDD 2 6.3V 2 6.3V 2 6.3V
R3127 CERM
402
CERM
402
CERM
402
TDIODE_NEG 6 36 1
0 2
31 GND_Z_OUT
2 OMIT DIFFERENTIAL_PAIR=P_TDD
XW3100
SM
MIN_NECK_WIDTH=8MIL 1/16W
MF R3129 1 C3147 1 C3144 1 C3143
NET_SPACING_TYPE=PROC_DIFF 402 0 1UF 1UF 1UF
31 GND_Z_SENSE 1 2 10% 10% 10%
1 6.3V 6.3V 6.3V
5% 2 CERM 2 CERM 2 CERM
R3131 1/16W
MF
402 402 402
0 402
31 GND_SPARE_GND1 2
5%
1/16W
MF
402
MASTER: GILA
LAST MODIFIED: JULY 9, 04
NOSTUFF CPU POWER AND BYPASS

A 36 32 31 29 7 =PPVCORE_CPU
R3103
1
0 2 KPVDD2 33 36 NOTICE OF PROPRIETARY PROPERTY
A
NOSTUFF MIN_LINE_WIDTH=10MIL
5% MIN_NECK_WIDTH=8MIL
1/16W
MF
1 C3101 DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF
402 0.22UF AGREES TO THE FOLLOWING
NOSTUFF 20%
6.3V
R3105 2 X5R
402
1
0 2
KPGND2 33 36
MIN_LINE_WIDTH=10MIL III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W DIFFERENTIAL_PAIR=P_KP2
MF NET_SPACING_TYPE=PROC_DIFF SIZE DRAWING NUMBER REV.
402
PLACE ALL THESE PARTS VERY CLOSE TO U2900
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
NONE 31 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
1 C3222 1 C3221 1 C3220 1 C3219 1 C3218 1 C3217 1 C3216 1 C3215 1 C3212 1 C3200
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402 402 402
1 C3293 1 C3268 1 C3261 1 C3259 1 C3235 1 C3232 1 C3226 1 C3224 1 C3245 1 C3223
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C3294 1 C3269 1 C3264 1 C3260 1 C3236 1 C3233 1 C3227 1 C3225 1 C3256 1 C3234
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402 402 402
1 C3295 1 C3271 1 C3265 1 C3262 1 C3239 1 C3237 1 C3230 1 C3228 1 C3289 1 C3267
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
C 2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402
2 6.3V
CERM
402 C
1 C3296 1 C3270 1 C3266 1 C3263 1 C3240 1 C3238 1 C3231 1 C3229 1 C3201 1 C3278
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402 402 402
1 C3297 1 C3282 1 C3276 1 C3272 1 C3252 1 C3250 1 C3243 1 C3241 1 C3206 1 C3204
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C3298 1 C3281 1 C3277 1 C3273 1 C3253 1 C3251 1 C3244 1 C3242 1 C3207 1 C3205
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402 402 402
1 C3299 1 C3284 1 C3279 1 C3274 1 C3257 1 C3254 1 C3248 1 C3246 1 C3210 1 C3208
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
1 C3202 1 C3283 1 C3280 1 C3275 1 C3258 1 C3255 1 C3249 1 C3247 1 C3211 1 C3209
B 1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
1UF
10%
6.3V
2 CERM
B
402 402 402 402 402 402 402 402 402 402
1 C3203 1 C3292 1 C3291 1 C3290 1 C3288 1 C3287 1 C3286 1 C3285 1 C3214 1 C3213
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402 402 402 402 402 402 402 402 402 402
MASTER: GILA
A
PROC DECOUPLING
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 32 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
33 7 =PP12V_RUN_CPU
C3310 34 33 6 PP12V_CPU
R3329
1 1UF
10 SC2643_VCC 33 U3310_BST_R 1 2
5% CRITICAL CRITICAL
1/16W
MF 20%
16V
1
C3311 1 C3312
2 402 CERM 1000UF 10UF
1206
R3330 U3310_DRN 2
20%
16V 2 CERM
10%
16V
0 ELEC
3PHASE 1 2 SYS_SLEWING_L 13 25 27 TH-KZJ 1210
1 C3319 R3390
1 5%
1/16W
34 33 6 PP12V_CPU U3310
1UF
9
0 MF
6 VIN
SC1211
20%
16V 5% 402 SOIC BG 8
CRITICAL
D 33 SC2643_AGND
2 CERM
1206
U3300
VCC 1/16W
MF
2 402 33 OUT1 4 CO VREG 7
D 4 VISHAY
Q3310
D
14 VID0 OUT1 19 OUT1 1 DRN TG 2 U3310_TG V30284
C3329 R3307
8 6 CPU_VID_R<0> TSSOP 33 1
1 G TO-252
8 6 CPU_VID_R<1> 13 VID1 OUT2 20 OUT2 33
1UF 2.2 1 2 U3310_BST 3 BST VPN 5 S 3 CRITICAL
SC2643VX
CPU_VID_R<2> 12 VID2 OUT3 21 OUT3 20% 1
8 6
11 VID3 OUT4 22 OUT4
34
2 16V
CERM
5% THMPAD R3350 L3310
8 6 CPU_VID_R<3> 34
R3300 1206 1/16W
MF 9
10K
5%
0.6UH-24A
8 6 CPU_VID_R<4> 10 VID4
U3300_BGOUT
1.5K 2 VRM_EN
603 1/16W
PN1 1 2 PPVCORE_CPU
15 VID5 BGOUT 4 1 3
R3310 MF 33 6 7 33 34 35
CPU_VID_R<5> MIN_NECK_WIDTH=10MIL
8 6
PGOOD 16 SC2643_PGOOD
5%
1/16W 3 Q3312 D3310
BAS16 1
1 2
2 402 MIN_LINE_WIDTH=25MIL TH1 CRITICAL
SC2643_OS1 3 OS1 MF 2N7002 SOT23 1
C3318 1
C3317 1
C3332
402 D SM 1 5%
SC2643_OS2 2 OS2 ERROUT 5 1/16W 1800UF 1800UF 1800UF
1 OS3
U3310_VREG MF 20% 20% 20%
SC2643_OS3 402 2 6.3V 2 6.3V 2 6.3V
24 OS4 DACSTEP 8 SC2643_DACSTEP S G 1 SYS_POWERUP_L 6 7 10 11 13 VPN1 CRITICAL ELEC
TH-KZJ
ELEC
TH-KZJ
ELEC
TH-KZJ
D 4 VISHAY
1 C3301
23 OUTSEN FB 7 1UF 2 1
R3312 Q3311 1
R3311
3PHASE
GSENSE 6
1 C3300 10%
2 6.3V 100
U3310_BG 1 V30289 1
SC2643_OSCREF
0.1UF CERM G TO-252 5%
1
R3391 17 OSCREF
20% 402 5%
1/16W S 3 1/10W
FF
0 2 10V MF 2 805
5%
1/16W AGND
CERM
402 SC2643_AGND
1 C3313 2 402 NOSTUFF
MF OMIT
33
1UF C3316_1
2 402
18 NOSTUFF 20%
16V AUX1
1 C3315
R3328
1
R3303
2 CERM
1206
33
0.0022UF 1 C3316
232K 10%
50V 0.0047UF
1% 2.7M 2 2 CERM
1/16W SC2643_ERROUT 1 SC2643_VCC 10%
MF
5%
33
1 C3314 402 2 25V
CERM
2 402 0.001UF 402
1
R3301 1/16W
MF 20%
50V VOLTAGE SENSE
30K 603 2 CERM
SC2643_AGND 33 5% 402 PLACE NEXT TO SMU
1/16W
MF NOSTUFF 34 33 6 PP12V_CPU
2 402 33 PN1
AUX1 33 AUX2 33 AUX3 34 AUX4 34 R3302
1
R3360
1
4PHASE C3302_1 0
C 1
R3313
20.5K
1
R3316
20.5K
1
R3317
20.5K
R3323
1
20.5K
1 C3302
330PF
5%
1/16W
MF NOSTUFF
10K
1%
1/16W
C
10% 2 402 MF
1%
1/16W
1%
1/16W
1%
1/16W
1%
1/16W
50V
2 CERM 35 34 33 7 6 PPVCORE_CPU R3308 2 402
MF MF MF MF 402 100K 2
2 402 2 402 2 402 2 402
1 CPU_SENSE_V 13
SC2643_OS4 5%
NOSTUFF NOSTUFF NOSTUFF 4PHASE NOSTUFF C3320 PP12V_CPU
1/16W
MF
1
R3361 1 C3303
1UF
34 33 6
402 2K 10UF
1 C3304 R3314
1
1 C3305 R3315
1
1 C3306 R3318
1 1 C3307 1R3319 SC2643_AGND 33
U3320_BST_R 1 2 1%
1/16W
20%
6.3V
2 CERM
0.0082UF 20.5K 20.5K 20.5K 0.0082UF 20.5K MF
10%
1% 0.0082UF 1% 0.0082UF 1% 10% 1% 805
25V 10% 10% 25V 20% 1 1 C3322 2 402
2 X7R 1/16W
MF
25V
2 X7R
1/16W
MF
25V
2 X7R
1/16W
MF
2 X7R 1/16W
MF 16V C3321 GND_SMU_AVSS 8 13 33 36
402 402 CERM 1000UF 10UF
2 402 402 2 402 402 2 402 2 402 1206 20% 10%
U3320_DRN 2 16V 16V
2 CERM
VCORE_SENSE_GND 6 33 ELEC
1210
TH-KZJ
R3305 R3304 DIFFERENTIAL PAIR

PP12V_CPU U3320 SCALE COUNT
SC2643_VCC
4.99K2
SC2643_OS_HUB
261 34 33 6
6 VIN
SC1211 6 V/V .01464 V/COUNT
33 1 1 2 FOR REMOTE SENSE SOIC BG 8
CRITICAL
1% 1% D 4 VISHAY
1/16W 1/16W 33 OUT2 4 CO VREG 7 ADC IS 10BIT 0 TO 1023
MF
C3308 MF VCORE_SENSE_VOUT 6 33
Q3320
402 402 0 TO 2.5V
0.068UF R3306 1 DRN TG 2 U3320_TG 1 V30284
G TO-252
1 2 2.2 U3320_BST 3 BST S 3
1 2 VPN 5 1
10% 1 C3330 THMPAD R3351 L3320
10V R3326 1UF
5%
1/16W 10K 0.6UH-24A
OMIT CERM
402 1
301 2 20%
MF 9 5%
603
XW3300
SM 1%
NOSTUFF 16V
2 CERM 3
R3320
1/16W
MF
33 PN2 1 2 PPVCORE_CPU
NOSTUFF
6 7 33 34 35
1/16W 1206
D3320 1 2 402 MIN_NECK_WIDTH=10MIL TH1
33 SC2643_AGND 1 2 MF
402 R3324
1
BAS16
SOT23
1 2 1
C3328 1
C3327 1
C3333
330 1 5% 1800UF 1800UF 1800UF
NOSTUFF 5% 1/16W 20% 20% 20%
1/16W U3320_VREG MF 2 6.3V 2 6.3V 2 6.3V
R3325 MF
VPN2
402
CRITICAL
ELEC
TH-KZJ
ELEC
TH-KZJ
ELEC
TH-KZJ
B 1
1K 2 R3325_2
2 402 D 4 VISHAY
Q3321 1
R3321
B
5%
1/16W R3322
1
U3320_BG 1 V30289 1
MF 100 G TO-252 5%
402 5% 1/10W
PLACE R3325 CLOSE TO INDUCTOR OUTPUT LEAD. 1/16W S 3 FF
NOSTUFF MF 2 805
1 C3323 2 402 NOSTUFF
C3309 1UF
20%
1 C3325 C3326_1
0.015UF AUX2 0.0022UF
2 16V
SC2643_OUTSEN 1 2
OMIT
CERM
1206
33
10%
50V
2 CERM
1 C3326
0.0047UF
R3327 10% 16V
X7R 402
XW3302
SM 1 C3324
402 10%
25V
2 CERM
1.5K 2 0.001UF
1 SC2643_OUTSEN_R 1 2 PPVCORE_CPU 6 7 33 34 35
20%
402
1% CONNECT BETWEEN THE INDUCTOR & BULK CAPS. 50V
2 CERM
1/16W 402
MF
402
33 PN2
PLACE REGULATOR SENSE POINTS AT DESIGNATED LOCATIONS.
R3335 CRITICAL TABLE_5_HEAD
0
35 34 33 7 6 PPVCORE_CPU MIN_LINE_WIDTH=10MIL 1 2 VCORE_SENSE_VOUT 6 33 L3300 PP12V_CPU 6 33 34
MIN_NECK_WIDTH=8MIL
R3336 5%
DIFFERENTIAL_PAIR=P_SENSE_CORE
33 7 =PP12V_RUN_CPU 1UH-20A-4.5MOHM R3343 VOLTAGE=12V
MIN_LINE_WIDTH=25MIL 376S0130 2 ON SEMI FET Q3310,Q3320 ON_SEMI
TABLE_5_ITEM
1/16W MIN_NECK_WIDTH=8MIL 0.0252 MIN_NECK_WIDTH=10MIL

UNDER PROCESSOR
1
0 2
MF
402
NET_SPACING_TYPE=PROC_DIFF 1 2 PP12V_CPU_R 1 CURRENT SENSE 376S0146 2 ON SEMI FET Q3311,Q3321 ON_SEMI
TABLE_5_ITEM
TH-VERT 1%
5% NOSTUFF 1W KEEP SHORTS NEXT TO U3301 TABLE_5_ITEM
1/16W
R3337 VCORE_SENSE_GND 6 33 MF 114S2325 1 RES,232K,1%,402 R3328 4PHASE
MF 2512 PLACE R3344 AND C3331 BY SMU
402
1
0 2
DIFFERENTIAL_PAIR=P_SENSE_CORE
TABLE_5_ITEM
114S3325 1 RES,332K,1%,402 R3328 3PHASE

NOSTUFF MIN_NECK_WIDTH=8MIL OMIT
5% NET_SPACING_TYPE=PROC_DIFF =PP3V3_RUN_CPU
NEAR SIDE R3338 1/16W
MF
XW3304 7
CPU VREG
3 4 SM
0 402
1 2 INA138_OUT 1 2 CORE_ISNS_P 3 NOSTUFF
VIN+ VIN- 6 36
SCALE COUNT
5% NOSTUFF OMIT D3300
A 1/16W
R3339 U3301 BAS16 2.73224 A/V .00675 A/COUNT
MF
402
1
0 2
5
INA138
SOT23-5 1
XW3303
SM R3344
100K 2
1
SOT23
A
NOSTUFF 5%
V+ OUT 1 2 CPU_SENSE_I_R 1 CPU_SENSE_I 13 ADC IS 10BIT 0 TO 1023
FAR SIDE R3340 1/16W
MF
5%
1/16W
0 TO 2.5V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
0 402 MF AGREES TO THE FOLLOWING
1 2
R3345
1 402 1 C3331 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% NOSTUFF GND 73.2K 10UF
20%
1/16W
MF R3341 2 1%
1/16W 2 6.3V
CERM
402
1
0 2
MF 805 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
KPVDD2
36 31
2 402
NOSTUFF 5% OMIT SIZE DRAWING NUMBER REV.
CPU SENSE SIDE R3342 1/16W
XW3301 GND_SMU_AVSS 8 13 33 36
051-6482 I
36 31 KPGND2 1
0 2
MF
402 SM
APPLE COMPUTER INC.
D
1 2 CORE_ISNS_M 6 36
5% SCALE SHT OF
1/16W
MF
402
NONE 33 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP12V_CPU 6 33 34
C3410 1
C3411 1
C3412 1 C3468
1UF 1000UF 1000UF 10UF
U3410_BST_R 1 2 20% 20% 10%
16V 35 34 33 7 6 PPVCORE_CPU
2 16V 2 16V 2 CERM
ELEC ELEC
20% TH-KZJ TH-KZJ 1210
16V
CERM EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1206
U3410_DRN 1 C3433 1 C3431 1 C3429 1 C3461 1 C3459
10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20%
U3410 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
D 34 33 6 PP12V_CPU 6 VIN
SC1211
SOIC BG 8
CRITICAL
1206 1206 1206 1206 1206
D
D 4 VISHAY EXTRA_C EXTRA_C EXTRA_C
OUT3 4 CO VREG 7
33
Q3410 1 C3434 1 C3432 1 C3430 1 C3462 1 C3460
1 DRN TG 2 U3410_TG V30284 10UF 10UF 10UF 10UF 10UF
R3423 1
G TO-252 20% 20% 20% 20% 20%
2.2 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
1 2 U3410_BST 3 BST VPN 5 1
S 3 CERM
1206
CERM
1206
CERM
1206
CERM
1206
CERM
1206
1 C3470 5%
1/16W
THMPAD R3450
10K
L3410
1UF MF 9 5%
0.6UH-24A EXTRA_C EXTRA_C EXTRA_C
20% 603
2 16V
CERM 3
R3410
1/16W
MF 34 PN3
1 2 PPVCORE_CPU 6 7 33 34 35
1 C3443 1 C3437 1 C3435 1 C3465 1 C3463
1206 D3410 1 2 402 MIN_NECK_WIDTH=10MIL TH1 10UF 10UF 10UF 10UF 10UF
BAS16
SOT23
1 2 1
C3417 1
C3418 1
C3472 1
C3473 20%
6.3V
2 CERM
20%
6.3V
2 CERM
20%
6.3V
2 CERM
20%
6.3V
2 CERM
20%
6.3V
2 CERM
1 5% 1800UF 1800UF 1800UF 1800UF 1206 1206 1206 1206 1206
1/16W 20% 20% 20% 20%
U3410_VREG MF 2 6.3V 2 6.3V 2 6.3V 2 6.3V
402 ELEC ELEC ELEC ELEC
VPN3 CRITICAL TH-KZJ TH-KZJ TH-KZJ TH-KZJ EXTRA_C EXTRA_C EXTRA_C
D 4 VISHAY 1 C3444 1 C3438 1 C3436 1 C3466 1 C3464
1
R3412 Q3411 R3411
1
U3410_BG 1 V30289 1 20% 20% 20% 20% 20%
100 G TO-252 5% 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
5% S 3 1/10W 1206 1206 1206 1206 1206
1/16W FF
MF NOSTUFF 2 805
1 C3413 2 402 1 C3415 EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1UF C3416_1
20% 0.0022UF 1 C3445 1 C3441 1 C3439 1 C3401 1 C3467
16V AUX3 10%
2 CERM 10UF 10UF 10UF 10UF 10UF
1206
33
2 50V
CERM
1 C3416 20% 20% 20% 20% 20%
402 0.0047UF 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
10%
1 C3414 2 25V
CERM
1206 1206 1206 1206 1206
0.001UF 402
20% EXTRA_C EXTRA_C EXTRA_C
50V
2 CERM
402
1 C3446 1 C3442 1 C3440 1 C3402 1 C3400
34 PN3 20% 20% 20% 20% 20%
C 2 6.3V
CERM
1206
2 6.3V
CERM
1206
2 6.3V
CERM
1206
2 6.3V
CERM
1206
2 6.3V
CERM
1206 C
EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1 C3455 1 C3449 1 C3447 1 C3405 1 C3403
PP12V_CPU 6 33 34
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
4PHASE 1206 1206 1206 1206 1206
C3420 1
NOSTUFF
C3421 1
C3422
4PHASE
EXTRA_C EXTRA_C EXTRA_C
1UF 1000UF 1000UF
1 C3469 1 C3456 1 C3450 1 C3448 1 C3406 1 C3404
U3420_BST_R 1 2 20% 20% 10UF
2 16V 2 16V 10% 10UF 10UF 10UF 10UF 10UF
ELEC ELEC 2
16V 20% 20% 20% 20% 20%
20%
16V
TH-KZJ TH-KZJ CERM
1210 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
CERM 1206 1206 1206 1206 1206
1206
U3420_DRN
U3420
1 C3457 1 C3453 1 C3451 1 C3409 1 C3407
SC1211 20% 20% 20% 20% 20%
34 33 6 PP12V_CPU 6 VIN SOIC BG 8 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
CRITICAL 1206 1206 1206 1206 1206
D 4 OMIT
33 OUT4 4 CO 4PHASE VREG 7
4PHASE Q3420 EXTRA_C
R3424 1 DRN TG 2 U3420_TG 1 V30284
2.2 G TO-252 1 C3458 1 C3454 1 C3452 1 C3419 1 C3408
1 2 U3420_BST 3 BST VPN 5 S 3 10UF 10UF 10UF 10UF 10UF
4PHASE 14PHASE 4PHASE 20% 20% 20% 20% 20%
1 C3471
5%
1/16W
THMPAD R3451
10K
L3420 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
MF 9 0.6UH-24A 1206 1206 1206 1206 1206
1UF 603 4PHASE
5%
1/16W
20%
16V 3 4PHASE MF 34 PN4 1 2 PPVCORE_CPU 6 7 33 34 35
2 CERM
D3420 R3420 2 402 MIN_LINE_WIDTH=25MIL TH1 NOSTUFF
1206
BAS16 1
1 2
C3427 1
C3428 1
C3474 1
C3475
B 1
SOT23
U3420_VREG
5%
1/16W
1800UF
20%
2 6.3V
1800UF
20%
2 6.3V
1800UF
20%
2 6.3V
1800UF
20%
2 6.3V
B
MF ELEC ELEC ELEC ELEC
VPN4 402 CRITICAL TH-KZJ TH-KZJ TH-KZJ TH-KZJ
D 4 OMIT 4PHASE
4PHASE
1
R3422 Q3421 R3421
1
U3420_BG 1 V30289 1
100 G TO-252 5%
5% S 3 1/10W
4PHASE 1/16W FF
MF 2 805
1 C3423 2 402 NOSTUFF
1UF 1 C3425 C3426_1
20% 4PHASE
16V
2 CERM AUX4 0.0022UF
1206
33
10%
2 50V
1 C3426
0.0047UF
TABLE_5_HEAD
CERM
4PHASE 402 10% PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
1 C3424 2 25V
CERM
376S0130 1 ON SEMI FET Q3410 ON_SEMI
TABLE_5_ITEM
0.001UF 402
20% TABLE_5_ITEM
50V
2 CERM 376S0146 1 ON SEMI FET Q3411 ON_SEMI
402 TABLE_5_ITEM
376S0130 1 ON SEMI FET Q3420 4PHASE_ON

34 PN4 TABLE_5_ITEM
376S0146 1 ON SEMI FET Q3421 4PHASE_ON

TABLE_5_ITEM
376S0204 1 VISHAY FET Q3420 4PHASE_VISH

TABLE_5_ITEM
376S0207 1 VISHAY FET Q3421 4PHASE_VISH
CPU VREG
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 34 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
35 34 33 7 6 PPVCORE_CPU
CRITICAL
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1 C3500 1 C3512 1 C3523 1 C3534 1 C3545 1 C3501 1 C3589 1 C3578 1 C3567 1 C3556
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
PPVCORE_CPU 6 7 33 34 35
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C
31 30 29 18 14 7 =PP1V2_EI_CPU 1 C3513 1 C3511 1 C3510 1 C3509 1 C3508 1 C3507 1 C3506 1 C3505 1 C3504 1 C3503
PP2V5_RUN_CPU_AVDD_R 31
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
NOSTUFF 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
DS3500
SM
DS3502
SM
1 2 1 2 EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1 C3524 1 C3522 1 C3521 1 C3520 1 C3519 1 C3518 1 C3517 1 C3516 1 C3515 1 C3514
10BQ040 10BQ040
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
NOSTUFF 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
DS3501
SM
2 1 EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C
1 C3535 1 C3533 1 C3532 1 C3531 1 C3530 1 C3529 1 C3528 1 C3527 1 C3526 1 C3525
10BQ040
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

C 1 C3546
10UF
1 C3544
10UF
1 C3543
10UF
1 C3542
10UF
1 C3541
10UF
1 C3540
10UF
1 C3539
10UF
1 C3538
10UF
1 C3537
10UF
1 C3536
10UF
C
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3557 1 C3555 1 C3554 1 C3553 1 C3552 1 C3551 1 C3550 1 C3549 1 C3548 1 C3547
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206

1 C3568 1 C3566 1 C3565 1 C3564 1 C3563 1 C3562 1 C3561 1 C3560 1 C3559 1 C3558
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3579 1 C3577 1 C3576 1 C3575 1 C3574 1 C3573 1 C3572 1 C3571 1 C3570 1 C3569
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C

1 C3590 1 C3588 1 C3587 1 C3586 1 C3585 1 C3584 1 C3583 1 C3582 1 C3581 1 C3580
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
B EXTRA_C EXTRA_C EXTRA_C EXTRA_C EXTRA_C B

1 C3502 1 C3599 1 C3598 1 C3597 1 C3596 1 C3595 1 C3594 1 C3593 1 C3592 1 C3591
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
CPU VREG OUTPUT CAPS

A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 35 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF
7 =PP5V_PWRON_CPU
DS3602
SM
1 2
MBR0530
7 =PP5V_ALL_CPU
D R3602
1
2 2 MIN_LINE_WIDTH=15MIL DAVDD 36
D
1/16W
MF
1 C3603 1 C3604 1 C3605 1 C3600
603 2.2UF 2.2UF 2.2UF 2.2UF
XW3601
SM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
20%
10V
2 CERM
805 805 805 805
1 2 DAGND 36
OMIT MIN_NECK_WIDTH=10MIL
XW3600, R3602, AND DS3602 MUST BE PLACED CLOSE TO SMU
100UA CURRENT SOURCE
R3606 R3603
DAGND 1
10K 2 TD11
10K2 TD_CURRENT
36
0.1% 10MIL 0.1%

1/16W 8MIL 1/16W
FF FF
THESE SIGNALS HAVE A MIN_LINE_WIDTH=10MIL 603 603
AND MIN_NECK_WIDTH=8MIL 36 DAVDD
U3601
5 LMV2011
4 BUFFER
SOT23-5
1
R3604
20K
36 ADC_REF 1 2 TD23 36 DAVDD
0.1%
1/16W
2
DAGND
1
R3608 U3602
FF
36 12.7K 4 5 LMV2011
C 603 1%
1/16W
MF
2 603
SOT23-5
1 C
3
R3607 R3605 DAGND

2
36
20K 10K
36 DAGND 1 2 1
10MIL
2 TD_BUFFERED
POWER MONITOR
0.1%
1/16W
8MIL 0.1%
1/16W
MIN_NECK_WIDTH=8MIL C3607
FF FF 10UF
603 603 1 2
20%
6.3V
R3609 R3611 CERM
10K 100K 2 805
1 2 TD3 1
10MIL
0.1% 0.1%
1/16W 8MIL 1/16W
FF MF
603 603
R3612
DAGND 1
40.2K2 36 DAVDD =PP3V3_ALL_CPU 7 =PP3V3_PWRON_CPU 7
36 31 TDIODE_POS 36
0.1%
U3603
5 LMV2011
1NOSTUFF 4
R3628 R3650
1
1 NOSTUFF
1 C3610 1 C3606 R3616 1/16W
FF
SOT23-5
100K 2 0 DS3650
0.0022UF 0.0022UF 1K 603 1 CPU_TEMP_R 1 CPU_TEMP 13 36 5% SM
10% 10% 1% 1/16W
2 50V 2 50V
1/16W 5% MIN_LINE_WIDTH=10MIL
MF MBR0530
CERM CERM MF
2 402
R3610 3 1/16W MIN_NECK_WIDTH=8MIL 2 603 2
TDIODE_NEG
402 402
1
10K 2 2
MF
402
1 C3613
36 31 6 DAGND 36 10UF NEED TO CONNECT TO P65 OF 80PIN SMU OR PIN 49 OF 64PIN SMU
PP3V3_CPU_DIODE
0.1% 20%
R3615
1 1/16W 2 6.3V
CERM
FF
0 603 805 MIN_NECK_WIDTH=10MIL
5% GND_SMU_AVSS 8 13 33
R3601
1
1/16W
R3613 R3614 200
B MF
2 402
36 ADC_REF 1
40.2K2
TD4 1
100K 2
ADC_REF 36
1%
1/16W
MF
1 C3601
2.2UF
20%
B
0.1% 10MIL 0.1% 2 603 2 10V
1/16W
FF
8MIL 1/16W
MF
C3608 36 ADC_REF
CERM
805
603 603 10UF MIN_LINE_WIDTH=10MIL
1 2 MIN_NECK_WIDTH=8MIL
R3690
0
1
20%
PPVREF_SMU_ADC_REF 1 2
6.3V
CERM
8
D3600
805 5%
1/16W 2.5V 1 C3602
MF
402
SSOT-23 0.47UF
20%
10V
NOSTUFF 2 CERM
R3691
2
3
603
PLACE CLOSE 0
8 GND_SMU_AVSS_DAGND 1 2 DAGND 36
TO U2900
5%
OMIT 1/16W NEEDED FOR FMAX
MF
XW3611
SM
402
NOSTUFF KPVDD2_FMAX 1 2 KPVDD2 NOSTUFF

J3600
6
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=10MIL OMIT
31 33
R3620
51
BM12B-SRSS-TB MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF XW3612 36 13 CPU_TEMP 1 2 FMAXT_P
F-ST-SM
14 SM 5% DIFFERENTIAL_PAIR=P_FMAXT NOSTUFF
6 KPGND2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
1 2 KPGND2 31 33
1/16W
MF NET_SPACING_TYPE=PROC_DIFF
1
R3619
MIN_LINE_WIDTH=10MIL OMIT 402 0
1 MIN_NECK_WIDTH=8MIL 5%
2 NET_SPACING_TYPE=PROC_DIFF XW3613
SM
NOSTUFF
R3621
1/10W
FF
3 51 2 805
6 TDIODE_POS_FMAX 1 2 TDIODE_POS 31 36
36 DAGND 1 2 FMAXT_M
4 DIFFERENTIAL_PAIR=TDIODE DIFFERENTIAL_PAIR=P_FMAXT
MIN_LINE_WIDTH=10MIL OMIT 5%
MIN_NECK_WIDTH=8MIL NET_SPACING_TYPE=PROC_DIFF
5 NET_SPACING_TYPE=PROC_DIFF XW3614
SM
1/16W
MF
CPU DIODE CONDITIONER
402
A
6
7
8
6 TDIODE_NEG_FMAX
DIFFERENTIAL_PAIR=TDIODE
1 2 TDIODE_NEG 6 31 36
PLACE AT BOARD EDGE
A
MIN_NECK_WIDTH=8MIL
9 NET_SPACING_TYPE=PROC_DIFF
10 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
CORE_ISNS_M 6 33 AGREES TO THE FOLLOWING
11 DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NET_SPACING_TYPE=PROC_DIFF II NOT TO REPRODUCE OR COPY IT
13
CORE_ISNS_P 6 33
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL SIZE DRAWING NUMBER REV.
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
NONE 36 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U3TWINS DO NOT HAVE MASKS
40 37 26 7 =PP2V5_PWRON_RAM
60 48 28 7 =PP1V5_PWRON_NB_AVDD R3702
2.2
1 2 PP1V5_PWRON_RAM_NB_AVDD
AG19
AG25
AE13
AE16
AE22
AE27
AC19
AB25
AA13
AA16
Y16
Y19
W23
W27
V20
VOLTAGE=1.5V MIN_LINE_WIDTH=25MIL
5% MIN_NECK_WIDTH=10MIL =PP2V5_PWRON_RAM 7 26 37 40
1/16W
VDD_DDR
MF
603
1 C3745 1 C3744
1UF 0.1UF
U3 10% 20%
2 6.3V 2 10V
AB21
U3LITE CERM CERM
T19
T21
T25
P20
N21
N25
M19
K19
K23
K27
G25
F19
D22
D27
B25
V1.0-300MM 402 402
D 38 RAM_DQ_R<0> AF20 DDR_DQ0

AH22 DDR_DQ1
PBGA
(SYM 2 OF 7) DDR_DQ64 AG27 RAM_DQ_R<64> 38 DDR VDD_DDR
D
38 RAM_DQ_R<1> DDR_DQ65 AF24 RAM_DQ_R<65> 38 CLK_AVDD
38 RAM_DQ_R<2> AH21 DDR_DQ2 OMIT
DDR_DQ66 AE24 RAM_DQ_R<66> 38
U3
AG21 DDR_DQ3 U3LITE
38 RAM_DQ_R<3> DDR_DQ67 AG26 RAM_DQ_R<67> 38 27 RAM_CLK66M_NB AC20 DDR_CLKP
V1.0-300MM DDR_RAS AE21 RAM_RAS_L_R 38
38 RAM_DQ_R<4> AB20 DDR_DQ4 DDR_DQ68 AF26 RAM_DQ_R<68> 38 PBGA

38 RAM_CLK_A_P_R AA12 DDR_CK_A (SYM 3 OF 7) DDR_CAS AD20 RAM_CAS_L_R 38
38 RAM_DQ_R<5> AC21 DDR_DQ5 DDR_DQ69 AD24 RAM_DQ_R<69> 38
38 RAM_CLK_A_N_R AB12 DDR_CK_AN OMIT
RAM_DQ_R<6> AD23 DDR_DQ6 DDR_DQ70 AD25 RAM_DQ_R<70> DDR_WE AC23 RAM_WE_L_R
38
MEMORY 38
38 RAM_CLK_B_P_R AB14 DDR_CK_B 38
RAM_DQ_R<7> AD21 DDR_DQ7 DDR_DQ71 AG28 RAM_DQ_R<71>

38
DATA 38
38 RAM_CLK_B_N_R AA14 DDR_CK_BN
RAM_DQ_R<8> AH26 DDR_DQ8 DDR_DQ72 AF28 RAM_DQ_R<72> DDR_BA0 AF21 RAM_BA_R<0>
38
INTERFACE 38
38 RAM_CLK_C_P_R AE15 DDR_CK_C 38
38 RAM_DQ_R<9> AH25 DDR_DQ9 DDR_DQ73 AE28 RAM_DQ_R<73> 38 DDR_BA1 AE20 RAM_BA_R<1> 38

38 RAM_CLK_C_N_R AE14 DDR_CK_CN
38 RAM_DQ_R<10> AH24 DDR_DQ10 DDR_DQ74 AD26 RAM_DQ_R<74> 38
38 RAM_CLK_D_P_R AC14 DDR_CK_D
38 RAM_DQ_R<11> AH23 DDR_DQ11 DDR_DQ75 AF27 RAM_DQ_R<75> 38 DDR_MUXEN0 AH16 RAM_MUXEN0 8
38 RAM_CLK_D_N_R AD14 DDR_CK_DN
38 RAM_DQ_R<12> AH27 DDR_DQ12 DDR_DQ76 AC26 RAM_DQ_R<76> 38 DDR_MUXEN4 AH18 RAM_MUXEN4 8
38 RAM_CLK_E_P_R AD15 DDR_CK_E
38 RAM_DQ_R<13> AG24 DDR_DQ13 DDR_DQ77 AC25 RAM_DQ_R<77> 38
38 RAM_CLK_E_N_R AC15 DDR_CK_EN
38 RAM_DQ_R<14> AF23 DDR_DQ14 DDR_DQ78 AC27 RAM_DQ_R<78> 38 MEMORY DDR_MAD0 AG12 RAM_A_R<0> 38
38 RAM_CLK_F_P_R AA15 DDR_CK_F
38 RAM_DQ_R<15> AH28 DDR_DQ15 DDR_DQ79 AD27 RAM_DQ_R<79> 38 CONTROL DDR_MAD1 AH13 RAM_A_R<1> 38
38 RAM_CLK_F_N_R AB15 DDR_CK_FN
38 RAM_DQ_R<16> U25 DDR_DQ16 DDR_DQ80 AA27 RAM_DQ_R<80> 38 INTERFACE DDR_MAD2 AH14 RAM_A_R<2> 38
38 RAM_DQ_R<17> AA23 DDR_DQ17 DDR_DQ81 AA26 RAM_DQ_R<81> 38 DDR_MAD3 AH15 RAM_A_R<3> 38

38 RAM_CKE_R<0> AC17 DDR_CKE0
38 RAM_DQ_R<18> Y22 DDR_DQ18 DDR_DQ82 AA24 RAM_DQ_R<82> 38 DDR_MAD4 AF12 RAM_A_R<4> 38
38 RAM_CKE_R<1> AD17 DDR_CKE1
38 RAM_DQ_R<19> AA22 DDR_DQ19 DDR_DQ83 AA28 RAM_DQ_R<83> 38 DDR_MAD5 AE12 RAM_A_R<5> 38
8 RAM_CKE_R<2> AE17 DDR_CKE2
38 RAM_DQ_R<20> U24 DDR_DQ20 DDR_DQ84 Y26 RAM_DQ_R<84> 38 DDR_MAD6 AD12 RAM_A_R<6> 38
8 RAM_CKE_R<3> AF17 DDR_CKE3
38 RAM_DQ_R<21> V23 DDR_DQ21 DDR_DQ85 Y25 RAM_DQ_R<85> 38 DDR_MAD7 AC12 RAM_A_R<7> 38
38 RAM_CKE_R<4> AB17 DDR_CKE4
38 RAM_DQ_R<22> V22 DDR_DQ22 DDR_DQ86 Y28 RAM_DQ_R<86> 38 DDR_MAD8 AG15 RAM_A_R<8> 38
38 RAM_CKE_R<5> AA17 DDR_CKE5
38 RAM_DQ_R<23> U22 DDR_DQ23 DDR_DQ87 Y24 RAM_DQ_R<87> 38 DDR_MAD9 AF15 RAM_A_R<9> 38
8 RAM_CKE_R<6> AB18 DDR_CKE6
38 RAM_DQ_R<24> P25 DDR_DQ24 DDR_DQ88 V26 RAM_DQ_R<88> 38 DDR_MAD10 AF14 RAM_A_R<10> 38
8 RAM_CKE_R<7> AA18 DDR_CKE7
38 RAM_DQ_R<25> R22 DDR_DQ25 DDR_DQ89 V27 RAM_DQ_R<89> 38 DDR_MAD11 AG14 RAM_A_R<11> 38
C 38
38
RAM_DQ_R<26>
RAM_DQ_R<27>
R21 DDR_DQ26
U23 DDR_DQ27
DDR_DQ90 V24
DDR_DQ91 W28
RAM_DQ_R<90>
RAM_DQ_R<91>
38
38
Y21 DDR_VREF0
U21 DDR_VREF1
DDR_MAD12 AH17
DDR_MAD13 AG17
RAM_A_R<12>
RAM_A_R<13>
38
38
C
38 RAM_DQ_R<28> P26 DDR_DQ28 DDR_DQ92 U27 RAM_DQ_R<92> 38
R24 DDR_DQ29
=PP2V5_PWRON_RAM 7 26 37 40
L21 DDR_VREF2
38 RAM_DQ_R<29> DDR_DQ93 V28 RAM_DQ_R<93> 38
H20 DDR_VREF3 DDR_CS0 AF18 RAM_CS_L_R<0> 38
38 RAM_DQ_R<30> P24 DDR_DQ30 DDR_DQ94 T28 RAM_DQ_R<94> 38 DDR_CS1 AE18 RAM_CS_L_R<1> 38

AA21 DDR_VREF4
38 RAM_DQ_R<31> P23 DDR_DQ31 DDR_DQ95 U26 RAM_DQ_R<95> 38
R37001 DDR_CS2 AG20 RAM_CS_L_R<2> 8
M25 DDR_DQ32 1K M21 DDR_VREF5
38 RAM_DQ_R<32> DDR_DQ96 R27 RAM_DQ_R<96> 38 1% V21 DDR_VREF6 DDR_CS3 AH20 RAM_CS_L_R<3> 8
M23 DDR_DQ33 1/16W MIN_LINE_WIDTH=25MIL
38 RAM_DQ_R<33> DDR_DQ97 R26 RAM_DQ_R<97> 38 MF MIN_NECK_WIDTH=10MIL J20 DDR_VREF7 DDR_CS8 AC18 RAM_CS_L_R<8> 38
P21 DDR_DQ34 402 2
38 RAM_DQ_R<34> DDR_DQ98 R28 RAM_DQ_R<98> 38 DDR_CS9 AD18 RAM_CS_L_R<9> 38
P22 DDR_DQ35
PP1V25_PWRON_RAM_VREF_NB
38 RAM_DQ_R<35> DDR_DQ99 P27 RAM_DQ_R<99> 38 VOLTAGE=1.25V DDR_CS10 AG18 RAM_CS_L_R<10> 8
M24 DDR_DQ36 DDR_DQ100 M28 DDR_CS11 AH19
38 RAM_DQ_R<36>
L22 DDR_DQ37
RAM_DQ_R<100> 38 R37011 1 C3730 1 C3746 1 C3747 1 C3748 RAM_CS_L_R<11> 8
38 RAM_DQ_R<37> DDR_DQ101 N28 RAM_DQ_R<101> 38 1K 0.1UF 0.1UF 0.1UF 0.1UF

L23 DDR_DQ38 1%
38 RAM_DQ_R<38> DDR_DQ102 L28 RAM_DQ_R<102> 38 1/16W 20% 20% 20% 20% DDR_DQSP0 AC24 RAM_DQS_R<0> 38
J23 DDR_DQ39 MF 2 10V 2 10V 2 10V 2 10V
38 RAM_DQ_R<39> DDR_DQ103 P28 RAM_DQ_R<103> 38 402 2
CERM
402
CERM
402
CERM
402
CERM
402 DDR_DQSP1 AG23 RAM_DQS_R<1> 38
38 RAM_DQ_R<40> D23 DDR_DQ40 DDR_DQ104 L25 RAM_DQ_R<104> 38 DDR_DQSP2 Y23 RAM_DQS_R<2> 38
38 RAM_DQ_R<41> D24 DDR_DQ41 DDR_DQ105 L26 RAM_DQ_R<105> 38 DDR_DQSP3 R23 RAM_DQS_R<3> 38
38 RAM_DQ_R<42> C26 DDR_DQ42 DDR_DQ106 L27 RAM_DQ_R<106> 38 DDR_DQSP4 M22 RAM_DQS_R<4> 38
38 RAM_DQ_R<43> C27 DDR_DQ43 DDR_DQ107 K28 RAM_DQ_R<107> 38 DDR_DQSP5 B26 RAM_DQS_R<5> 38
38 RAM_DQ_R<44> A22 DDR_DQ44 DDR_DQ108 H27 RAM_DQ_R<108> 38 DDR_DQSP6 B27 RAM_DQS_R<6> 38
38 RAM_DQ_R<45> A25 DDR_DQ45 DDR_DQ109 H28 RAM_DQ_R<109> 38 DDR_DQSP7 F23 RAM_DQS_R<7> 38
38 RAM_DQ_R<46> C24 DDR_DQ46 DDR_DQ110 J27 RAM_DQ_R<110> 38 DDR_DQSP8 AE23 RAM_DQS_R<8> 38
38 RAM_DQ_R<47> C23 DDR_DQ47 DDR_DQ111 L24 RAM_DQ_R<111> 38 DDR_DQSP9 AD28 RAM_DQS_R<9> 38
38 RAM_DQ_R<48> B24 DDR_DQ48 DDR_DQ112 J25 RAM_DQ_R<112> 38 DDR_DQSP10 Y27 RAM_DQS_R<10> 38
38 RAM_DQ_R<49> B23 DDR_DQ49 DDR_DQ113 J24 RAM_DQ_R<113> 38 DDR_DQSP11 U28 RAM_DQS_R<11> 38
38 RAM_DQ_R<50> A23 DDR_DQ50 DDR_DQ114 J26 RAM_DQ_R<114> 38 DDR_DQSP12 M27 RAM_DQS_R<12> 38
38 RAM_DQ_R<51> A24 DDR_DQ51 DDR_DQ115 G28 RAM_DQ_R<115> 38 DDR_DQSP13 J28 RAM_DQS_R<13> 38
RAM_DQ_R<52> A27 DDR_DQ52 DDR_DQ116 H25 RAM_DQ_R<116> DDR_DQSP14 F28 RAM_DQS_R<14>

B
38
38 RAM_DQ_R<53> A28 DDR_DQ53

B28 DDR_DQ54
DDR_DQ117 H24 RAM_DQ_R<117>
38
38 DDR_DQSP15 F25 RAM_DQS_R<15>

38
38 B
38 RAM_DQ_R<54> DDR_DQ118 F27 RAM_DQ_R<118> 38
DDR_CLK_AVSS
RAM_DQ_R<55> A26 DDR_DQ55 DDR_DQ119 H26 RAM_DQ_R<119>
AA20
38 38
38 RAM_DQ_R<56> F24 DDR_DQ56 DDR_DQ120 E28 RAM_DQ_R<120> 38
38 RAM_DQ_R<57> J22 DDR_DQ57 DDR_DQ121 E27 RAM_DQ_R<121> 38
38 RAM_DQ_R<58> E23 DDR_DQ58 DDR_DQ122 F26 RAM_DQ_R<122> 38
38 RAM_DQ_R<59> H23 DDR_DQ59 DDR_DQ123 E26 RAM_DQ_R<123> 38
38 RAM_DQ_R<60> J21 DDR_DQ60 DDR_DQ124 D28 RAM_DQ_R<124> 38
38 RAM_DQ_R<61> H21 DDR_DQ61 DDR_DQ125 C28 RAM_DQ_R<125> 38
38 RAM_DQ_R<62> G21 DDR_DQ62 DDR_DQ126 E25 RAM_DQ_R<126> 38
38 RAM_DQ_R<63> H22 DDR_DQ63 DDR_DQ127 E24 RAM_DQ_R<127> 38
=PP2V5_PWRON_RAM 7 26 37 40
MASTER: GILA
1 C3700 1 C3701 1 C3702 1 C3703 1 C3704 1 C3705 1 C3706 1 C3707 1 C3708 1 C3709 1 C3710 1 C3711 1 C3712 1 C3713 1 C3714 1 C3731 1 C3732 1 C3733 1 C3734 1 C3735 1 C3736 1 C3737 LAST MODIFIED: APR 12, 04
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
10V
2 CERM
402
U3LITE MEMORY
A
1 C3715 1 C3716 1 C3717 1 C3718 1 C3719 1 C3720 1 C3721 1 C3722 1 C3724 1 C3725 1 C3726 1 C3727 1 C3728 1 C3729 1 C3743 1 C3742 1 C3740 1 C3739 1 C3738 II NOT TO REPRODUCE OR COPY IT
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 SIZE DRAWING NUMBER REV.
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 37 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ALL R PACKS ARE 1/16W 5% ELECTRICAL_CONSTRAINT_SET NET_PHYSICAL_TYPE NET_SPACING_TYPE DIFFERENTIAL_PAIR
RP3836 RP3818 RAM_CLK_A_P_R RAM_CLK RAM_CLK_A_R

38 37 RAM_DQ_R<7> 4 5 22 RAM_DQ<7> 38 40 44 38 37 RAM_DQ_R<68> 2 7 22 RAM_DQ<68> 38 40 45
38 37 I206
RP3836 RP3805 RAM_CLK_A_N_R RAM_CLK RAM_CLK_A_R

38 37 I207
RP3836 RP3818 RAM_CLK_B_P_R RAM_CLK RAM_CLK_B_R
38 37 I208
RP3836 RP3805 RAM_CLK_B_N_R RAM_CLK RAM_CLK_B_R
38 37 I209
RP3816 RP3818 RAM_CLK_C_P_R RAM_CLK RAM_CLK_C_R
38 37 I210
RP3816 RP3805 RAM_CLK_C_N_R RAM_CLK RAM_CLK_C_R
38 37 I211
RP3816 RP3805 RAM_CLK_D_P_R RAM_CLK RAM_CLK_D_R
38 37 I212
RP3816 RP3818 RAM_CLK_D_N_R RAM_CLK RAM_CLK_D_R
38 37 I213
RP3835 RP3817 RAM_CLK_E_P_R RAM_CLK RAM_CLK_E_R
38 37 I214
RP3801 RP3802 RAM_CLK_E_N_R RAM_CLK RAM_CLK_E_R
RAM_DQ_R<10> 1 8 22 RAM_DQ<10> RAM_DQ_R<73> 4 5 22 RAM_DQ<73>
38 37 I215
D
38 37
38 37 RAM_DQ_R<11> RP3801
RP3801
3
4
6
5
22
22
RAM_DQ<11>
38 40 44
38 40 44
38 37
38 37 RAM_DQ_R<72> RP3817
RP3817
2
4
7
5
22
22
RAM_DQ<72>
38 40 45
38 40 45
38 37
38 37
RAM_CLK_F_P_R
RAM_CLK_F_N_R
RAM_CLK
RAM_CLK
RAM_CLK_F_R
RAM_CLK_F_R
I216
I217
D
38 37 RAM_DQ_R<14> RAM_DQ<14> 38 40 44 38 37 RAM_DQ_R<75> RAM_DQ<75> 38 40 45
RP3835 RP3802 RAM_CLK_A_P RAM_CLK0 RAM_CLK RAM_CLK_A
40 38 I218
RP3801 RP3817 RAM_CLK_A_N RAM_CLK0 RAM_CLK RAM_CLK_A
40 38 I219
RP3835 RP3802 RAM_CLK_B_P RAM_CLK0 RAM_CLK RAM_CLK_B
40 38 I220
RP3835 RP3802 RAM_CLK_B_N RAM_CLK0 RAM_CLK RAM_CLK_B
40 38 I221
RP3822 RP3806 RAM_CLK_C_P RAM_CLK0 RAM_CLK RAM_CLK_C
40 38 I222
RP3822 RP3821 RAM_CLK_C_N RAM_CLK0 RAM_CLK RAM_CLK_C

40 38 I223
RP3822 RP3821 RAM_CLK_D_P RAM_CLK1 RAM_CLK RAM_CLK_D
40 38 I224
RP3822 RP3821 RAM_CLK_D_N RAM_CLK1 RAM_CLK RAM_CLK_D
40 38 I225
RP3823 RP3806 RAM_CLK_E_P RAM_CLK1 RAM_CLK RAM_CLK_E
40 38 I226
RP3823 RP3806 RAM_CLK_E_N RAM_CLK1 RAM_CLK RAM_CLK_E
40 38 I227
RP3823 RP3821 RAM_CLK_F_P RAM_CLK1 RAM_CLK RAM_CLK_F
40 38 I228
RP3823 RP3806 RAM_CLK_F_N RAM_CLK1 RAM_CLK RAM_CLK_F
40 38 I229
RAM_DQ_R<30> RP3808 3 6 22 RAM_DQ<30> RAM_DQ_R<91> RP3819 3 6 22 RAM_DQ<91>

38 37 38 40 44 38 37 38 40 45
RP3824 RP3819 RAM_CKE_R<1..0> RAM_CAD
38 37 I230
RP3808 RP3803 RAM_CKE_R<5..4> RAM_CAD
38 37 I232
RP3824 RP3819 RAM_CKE<0> RAM_CKECS0 RAM_CAD
44 40 38 I234

44 40 38 I236
45 40 38 I235
45 40 38 I237
RP3824 RP3803 RAM_CS_L_R<1..0> RAM_CAD
38 37 I238
RP3826 RP3820 RAM_CS_L_R<9..8> RAM_CAD
38 37 I241
RP3807 RP3820 RAM_CS_L<0> RAM_CKECS0 RAM_CAD
44 40 38 I243

44 40 38 I242
45 40 38 I245
22 22 45 40 38
C
I244
C 38 37 RAM_DQ_R<39> 3 6 RAM_DQ<39> 38 40 44 38 37 RAM_DQ_R<100> 2 7 RAM_DQ<100> 38 40 45
RAM_DQ_R<33> RP3807 3 6 22 RAM_DQ<33> RAM_DQ_R<99> RP3825 3 6 22 RAM_DQ<99> RAM_DQS_R<15..0>

38 37 38 40 44 38 37 38 40 45 38 37 RAM_CAD I305
RAM_DQ_R<34> RP3807 1 8 22 RAM_DQ<34> RAM_DQ_R<102> RP3825 1 8 22 RAM_DQ<102> RAM_DQ_R<127..0>
38 37 38 40 44 38 37 38 40 45 38 37 RAM_CAD I294
38 37 RAM_DQ_R<36> RP3826 1 8 22 RAM_DQ<36> 38 40 44 38 37 RAM_DQ_R<101> RP3825 4 5 22 RAM_DQ<101> 38 40 45 45 44 40 38 RAM_DQ<127..0> RAM_CAD I293
RAM_DQ_R<47> RP3811 2 7 22 RAM_DQ<47> RAM_DQ_R<111> RP3809 1 8 22 RAM_DQ<111> RAM_DQS<0>
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS0 RAM_CAD I246
RAM_DQ_R<46> RP3811 1 8 22 RAM_DQ<46> RAM_DQ_R<106> RP3809 3 6 22 RAM_DQ<106> RAM_DQ<7..0>
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS0 RAM_CAD I248
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS1 RAM_CAD I251
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS1 RAM_CAD I252
38 37 RAM_DQ_R<45> RP3811 4 5 22 RAM_DQ<45> 38 40 44 38 37 RAM_DQ_R<107> RP3829 4 5 22 RAM_DQ<107> 38 40 45 44 40 38 RAM_DQS<2> RAM_DQS2 RAM_CAD I253
38 37 RAM_DQ_R<42> RP3814 3 6 22 RAM_DQ<42> 38 40 44 38 37 RAM_DQ_R<110> RP3829 3 6 22 RAM_DQ<110> 38 40 45 44 40 38 RAM_DQ<23..16> RAM_DQS2 RAM_CAD I254
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS3 RAM_CAD I255
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS4 RAM_CAD I257
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS4 RAM_CAD I258
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS5 RAM_CAD I260
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS6 RAM_CAD I262
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS7 RAM_CAD I263
38 37 38 40 44 38 37 38 40 45 44 40 38 RAM_DQS7 RAM_CAD I264
38 37 38 40 44 38 37 38 40 45 45 40 38 RAM_DQS8 RAM_CAD I267
38 37 38 40 44 38 37 38 40 45 45 40 38 RAM_DQS9 RAM_CAD I268
38 37 38 40 44 38 37 38 40 45 45 40 38 RAM_DQS10 RAM_CAD I270
RAM_DQ_R<58> RP3813 3 6 22 RAM_DQ<58> RAM_DQ_R<126> RP3810 1 8 22 RAM_DQ<126> RAM_DQS<11> RAM_DQS11 RAM_CAD
B
38 37
38 37 RAM_DQ_R<62> RP3813 4 5 22 RAM_DQ<62>

38 40 44
38 40 44
38 37
38 37 RAM_DQ_R<127> RP3810 3 6 22 RAM_DQ<127>

38 40 45
38 40 45
45 40 38
45 40 38 RAM_DQ<95..88> RAM_DQS11 RAM_CAD

I272
I271
B
45 40 38 RAM_DQS<12> RAM_DQS12 RAM_CAD I273
THE FOLLOWING IS A SWAPPABLE GROUP
RP3841 3 RAM_DQ<103..96> RAM_DQS12 RAM_CAD
38 37 RAM_CKE_R<4> 6 15 RAM_CKE<4> 38 40 45
45 40 38 I275
RP3841 4 THE FOLLOWING ARE 0402 5% RESISTORS RAM_DQS<13> RAM_DQS13 RAM_CAD
38 37 RAM_CKE_R<5> 5 15 RAM_CKE<5> 38 40 45
45 40 38 I274
RP3841 RAM_DQ<111..104> RAM_DQS13 RAM_CAD
38 37 RAM_CKE_R<0> 2 7 15 RAM_CKE<0> 38 40 44
R3816
45 40 38 I277
RP3841 1 8 15 38 37 RAM_CLK_A_P_R 1 2 15 RAM_CLK_A_P 38 40 45 40 38 RAM_DQS<14> RAM_DQS14 RAM_CAD I276
38 37 RAM_CKE_R<1> RAM_CKE<1> 38 40 44
R3817
38 37 RAM_CLK_A_N_R 1 2 15 RAM_CLK_A_N 38 40 45 40 38 RAM_DQ<119..112> RAM_DQS14 RAM_CAD I278
RAM_CS_L_R<8> RP3842 1 8 15 RAM_CS_L<8> RAM_CLK_B_P_R R3818 1 2 15 RAM_CLK_B_P RAM_DQS<15>
38 37 38 40 45 38 37 38 40 45 40 38 RAM_DQS15 RAM_CAD I280
38 37 RAM_CS_L_R<9> RP3842 2 7 15 RAM_CS_L<9> 38 40 45 38 37 RAM_CLK_B_N_R R3819 1 2 15 RAM_CLK_B_N 38 40 45 40 38 RAM_DQ<127..120> RAM_DQS15 RAM_CAD I279
38 37 RAM_CS_L_R<1> RP3842 3 6 15 RAM_CS_L<1> 38 40 44 38 37 RAM_CLK_C_P_R R3820 1 2 15 RAM_CLK_C_P 38 40
RAM_CS_L_R<0> RP3842 4 5 15 RAM_CS_L<0> RAM_CLK_C_N_R R3821 1 2 15 RAM_CLK_C_N RAM_A_R<13..0>

38 37 38 40 44 38 37 38 40 38 37 RAM_CAD I295
38 37 RAM_CLK_D_P_R R3822 1 2 15 RAM_CLK_D_P 38 40 38 37 RAM_BA_R<1..0> RAM_CAD I296
THE FOLLOWING IS A SWAPPABLE GROUP 38 37 RAM_CLK_D_N_R R3823 1 2 15 RAM_CLK_D_N 38 40 38 37 RAM_RAS_L_R RAM_CAD I297
RAM_A_R<11> RP3832 3 6 15 RAM_A<11> RAM_CLK_E_P_R R3824 1 2 15 RAM_CLK_E_P RAM_CAS_L_R
38 37 38 40 44 38 37 38 40 38 37 RAM_CAD I298
38 37 RAM_A_R<1> RP3832 4 5 15 RAM_A<1> 38 40 44 38 37 RAM_CLK_E_N_R R3825 1 2 15 RAM_CLK_E_N 38 40 38 37 RAM_WE_L_R RAM_CAD I299
38 37 RAM_A_R<10> RP3832 2 7 15 RAM_A<10> 38 40 45 38 37 RAM_CLK_F_P_R R3826 1 2 15 RAM_CLK_F_P 38 40 45 44 40 38 RAM_A<13..0> RAM_A_CTL RAM_CAD I300
38 37 RAM_WE_L_R RP3800 4 5 15 RAM_WE_L 38 40 45 38 37 RAM_CLK_F_N_R R3827 1 2 15 RAM_CLK_F_N 38 40 45 40 38 RAM_BA<1..0> RAM_A_CTL RAM_CAD I304
38 37 RAM_A_R<4> RP3833 3 6 15 RAM_A<4> 38 40 44 45 40 38 RAM_RAS_L RAM_A_CTL RAM_CAD I303
RAM_A_R<6> RP3833 2 7 15 RAM_A<6> RAM_CAS_L
38 37 38 40 44 45 40 38 RAM_A_CTL RAM_CAD I302
38 37 RAM_A_R<7> RP3833 1 8 15 RAM_A<7> 38 40 44 38 37 RAM_DQS_R<0> R3800 1 2 15 RAM_DQS<0> 38 40 44 45 40 38 RAM_WE_L RAM_A_CTL RAM_CAD I301
RP3834 1 8 15 38 37 RAM_DQS_R<1> R3801 1 2 15 RAM_DQS<1> 38 40 44
RAM_A_R<12> RP3800 3 6 15 RAM_A<12> RAM_DQS_R<2> R3802 1 2 15 RAM_DQS<2>

38 37 38 40 44 38 37 38 40 44
38 37 RAM_A_R<2> RP3834 2 7 15 RAM_A<2> 38 40 44 38 37 RAM_DQS_R<3> R3803 1 2 15 RAM_DQS<3> 38 40 44

R3804
SERIES TERM
38 37 RAM_A_R<0> RP3833 4 5 15 RAM_A<0> 38 40 44 38 37 RAM_DQS_R<4> 1 2 15 RAM_DQS<4> 38 40 44 RAM_CLK PRIMARY SPACING SET BASED ON DIFF IMPEDANCE
38 37 38 40 44 38 37 38 40 44 RAM_CLK LINE-LINE SPACING SET TO 15MIL
RP3800 15 R3806 15
A RAM_A_R<13> 2 7 RAM_A<13> RAM_DQS_R<6> 1 2 RAM_DQS<6> TOTAL LENGTH TOLERENCE = 20PS = 2.82MM
38 37
38 37 RAM_A_R<3> RP3800 1 8 15 RAM_A<3>

38 40 44
38 40 44
38 37
38 37 RAM_DQS_R<7> R3807
R3808
1 2 15 RAM_DQS<7>
38 40 44
38 40 44
RAM_CAD SPACING IS 10MIL NOTICE OF PROPRIETARY PROPERTY
A
38 37 RAM_DQS_R<8> 1 2 15 RAM_DQS<8> 38 40 45
38 37 RAM_CAS_L_R RP3804 1 8 15 RAM_CAS_L 38 40 45 38 37 RAM_DQS_R<9> R3809 1 2 15 RAM_DQS<9> 38 40 45 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
RAM_BA_R<0> RP3804 4 5 15 RAM_BA<0> RAM_DQS_R<10> R3810 1 2 15 RAM_DQS<10>
38 37 38 40 45 38 37 38 40 45 AGREES TO THE FOLLOWING
38 37 RAM_DQS_R<11> R3811 1 2 15 RAM_DQS<11> 38 40 45 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
38 37 RAM_BA_R<1> RP3804 2 7 15 RAM_BA<1> 38 40 45 38 37 RAM_DQS_R<12> R3812 1 2 15 RAM_DQS<12> 38 40 45 II NOT TO REPRODUCE OR COPY IT
RAM_RAS_L_R RP3804 3 6 15 RAM_RAS_L RAM_DQS_R<13> R3813 1 2 15 RAM_DQS<13>
38 37 38 40 45 38 37 38 40 45 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
38 37 RAM_A_R<9> RP3834 3 6 15 RAM_A<9> 38 40 44 38 37 RAM_DQS_R<14> R3814 1 2 15 RAM_DQS<14> 38 40 45

051-6482 I
38 37 38 40 44 38 37 38 40 45
APPLE COMPUTER INC.

D
SCALE SHT OF
NONE 38 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PIN 82:
40 37 26 7 =PP2V5_PWRON_RAM J4001 =PP2V5_PWRON_RAM 7 26 37 40
40 37 26 7 =PP2V5_PWRON_RAM J4000 =PP2V5_PWRON_RAM 7 26 37 40 NC: VDD & VDDQ ARE THE SAME =PP2V5_PWRON_RAM 7 26 37 40
DDR-DIMM-STD GND: VDD & VDDQ ARE DIFFERENT

DDR-DIMM-STD
516-0086 F-28DEG-TH
F-28DEG-TH 1
BOT SIDE TOP SIDE 40 PP1V25_RAM_VREF_DIMM 1 BOT SIDE TOP SIDE
93 R4008
PP1V25_RAM_VREF_DIMM 1 93 VREF OMIT VSS 150
40 VREF OMIT VSS 45 38 RAM_DQ<75> 2 94 RAM_DQ<74> 38 45 1%
44 38 RAM_DQ<14> 2 94 RAM_DQ<11> 38 44
DQ0 DQ4 1/16W
DQ0 DQ4 3 95 RAM_DQ<72> MF
3 95 RAM_DQ<13> VSS DQ5 38 45
VSS DQ5 38 44
45 38 RAM_DQ<79> 4 96 2 402
RAM_DQ<10> 4 96 DQ1 VDDQ PP1V25_RAM_VREF_DIMM
44 38 DQ1 VDDQ 45 38 RAM_DQS<9> 5 97 MIN_LINE_WIDTH=25MIL
40
44 38 RAM_DQS<1> 5 97 DQS0 DM0/DQS9 MIN_NECK_WIDTH=10MIL

DQS0 DM0/DQS9 45 38 RAM_DQ<73> 6 98 RAM_DQ<76> 38 45
44 38 RAM_DQ<9> 6 98 RAM_DQ<8> 38 44
DQ2 DQ6 1 C4035 R40101
DQ2 DQ6 7 99 RAM_DQ<78>
7 99 RAM_DQ<12> 38 44
VDD DQ7 38 45
1UF 150
VDD DQ7 RAM_DQ<77> 8 100 10% 1%
RAM_DQ<15> 8 100 45 38 DQ3 VSS 6.3V
D
44 38
NC 9
10
DQ3
NC
VSS
NC
101 NC
102 NC 6 TP_J4001_SJRESET_L
NC 9
10
NC
NC
NC
NC
101 NC
102 NC
2 CERM
603
1/16W
MF
2 402
D
6 TP_J4000_SJRESET_L NC NC 11 103 NC FETEN
11 103 NC FETEN VSS A13
VSS A13 45 38 RAM_DQ<66> 12 104
RAM_DQ<2> 12 104 DQ8 VDDQ
44 38 DQ8 VDDQ 45 38 RAM_DQ<67> 13 105 RAM_DQ<65> 38 45
44 38 RAM_DQ<0> 13 105 RAM_DQ<3> 38 44
DQ9 DQ12
DQ9 DQ12 RAM_DQS<8> 14 106 RAM_DQ<64>
44 38 RAM_DQS<0> 14 106 RAM_DQ<7> 38 44
45 38 DQS1 DQ13 38 45
DQS1 DQ13 15 107
15 107 VDDQ DM1/DQS10
VDDQ DM1/DQS10 38 RAM_CLK_F_P 16 108
38 RAM_CLK_A_P 16 108 CK1 VDD
CK1 VDD 38 RAM_CLK_F_N 17 109 RAM_DQ<69> 38 45
38 RAM_CLK_A_N 17 109 RAM_DQ<1> 38 44
CK1* DQ14
CK1* DQ14 18 110 RAM_DQ<68> 38 45
18 110 RAM_DQ<4> 38 44
VSS DQ15
VSS DQ15 RAM_DQ<71> 19 111 RAM_CKE<5>
44 38 RAM_DQ<6> 19 111 RAM_CKE<1> 38 44
45 38 DQ10 CKE1 38 45
DQ10 CKE1 45 38 RAM_DQ<70> 20 112
RAM_DQ<5> 20 112 =PP2V5_PWRON_RAM DQ11 VDDQ =PP2V5_PWRON_RAM
44 38 DQ11 VDDQ 7 26 37 40
45 38 RAM_CKE<4> 21 113 NC 7 26 37 40
44 38 RAM_CKE<0> 21 113 NC CKE0 BA2

CKE0 BA2 22 114 RAM_DQ<81>
22 114 RAM_DQ<17> VDDQ DQ20 38 45
RAM_DQ<19> 23
VDDQ DQ20
115 RAM_A<12>
38 44
1 C4036 1 C4006 45 38 RAM_DQ<83> 23
DQ16 A12
115 RAM_A<12> 38 40 44
1 C4008 1 C4007
44 38 DQ16 A12 38 40 44
10UF 10UF 45 38 RAM_DQ<80> 24 116 10UF 10UF
44 38 RAM_DQ<18> 24 116 20% 20% DQ17 VSS 20% 20%
DQ17 VSS 6.3V
2 CERM
6.3V
2 CERM RAM_DQS<10> 25 117 RAM_DQ<86> 6.3V
2 CERM
6.3V
2 CERM
44 38 RAM_DQS<2> 25 117 RAM_DQ<22> 38 44
45 38 DQS2 DQ21 38 45
DQS2 DQ21 1206 1206 26 118 RAM_A<11> 38 40 44
1206 1206
26 118 RAM_A<11> VSS A11
VSS A11 38 40 44
44 40 38 RAM_A<9> 27 119
RAM_A<9> 27 119 A9 DM2/DQS11
44 40 38
RAM_DQ<23> 28
A9 DM2/DQS11
120
1 C4039 1 C4037 1 C4023 45 38 RAM_DQ<82> 28
DQ18 VDD
120 1 C4011 1 C4010 1 C4009
44 38
DQ18 VDD 0.1UF 0.1UF 0.1UF 44 40 38 RAM_A<7> 29 121 RAM_DQ<85> 38 45
0.1UF 0.1UF 0.1UF
44 40 38 RAM_A<7> 29 121 RAM_DQ<21> 38 44
20% 20% 20% A7 DQ22 20% 20% 20%
30
A7 DQ22
122 2 10V
CERM 2 10V
CERM 2 10V
CERM
30
VDDQ A8
122 RAM_A<8> 38 40 44
10V
2 CERM
10V
2 CERM
10V
2 CERM
VDDQ A8 RAM_A<8> 38 40 44
402 402 402 31 123 402 402 402
45 38 RAM_DQ<87> DQ19 DQ23 RAM_DQ<84> 38 45
RAM_DQ<16> 31 123 RAM_DQ<20>
44 38 DQ19 DQ23 38 44
44 40 38 RAM_A<5> 32 124
RAM_A<5> 32 124 A5 VSS
44 40 38
RAM_DQ<27> 33
A5 VSS
125 RAM_A<6>
1 C4040 1 C4038 1 C4024 45 38 RAM_DQ<90> 33
DQ24 A6
125 RAM_A<6> 38 40 44
1 C4014 1 C4012 1 C4033
44 38
DQ24 A6 38 40 44
0.1UF 0.1UF 0.1UF 34 126 RAM_DQ<91> 38 45
0.1UF 0.1UF 0.1UF
34 126 RAM_DQ<26> 20% 20% 20% VSS DQ28 20% 20% 20%
VSS DQ28 2 10V 2 10V 2 10V 10V 10V 10V
38 44
RAM_DQ<89> 35 127 RAM_DQ<93> 2 CERM 2 CERM 2 CERM
CERM CERM CERM 45 38 38 45
C 44 38
44 38
RAM_DQ<29>
RAM_DQS<3>
35
36
DQ25
DQS3
DQ29
VDDQ
127
128
RAM_DQ<25> 38 44 402 402 402 45 38
44 40 38
RAM_DQS<11>
RAM_A<4>
36
37
DQ25
DQS3
DQ29
VDDQ
128
129
402 402 402
C
RAM_A<4> 37 129 A4 DM3/DQS12
44 40 38
38
A4 DM3/DQS12
130 RAM_A<3>
1 C4044 1 C4041 1 C4025 38
VDD A3
130 RAM_A<3> 38 40 44
1 C4000 1 C4013 1 C4042
VDD A3 38 40 44
0.1UF 0.1UF 0.1UF 45 38 RAM_DQ<88> 39 131 RAM_DQ<92> 38 45
0.1UF 0.1UF 0.1UF
44 38 RAM_DQ<31> 39 131 RAM_DQ<24> 38 44
20% 20% 20% DQ26 DQ30 20% 20% 20%
40
DQ26 DQ30
132 2 10V
CERM 2 10V
CERM 2 10V
CERM 45 38 RAM_DQ<94> 40
DQ27 VSS
132 2 10V
CERM 2 10V
CERM 2 10V
CERM
44 38 RAM_DQ<28> DQ27 VSS 402 402 402 41 133 402 402 402
41 133 44 40 38 RAM_A<2> A2 DQ31 RAM_DQ<95> 38 45
44 40 38 RAM_A<2> A2 DQ31 RAM_DQ<30> 38 44
42 134 NC
42 134 NC VSS NC
RAM_A<1> 43
VSS NC
135 NC
1 C4045 1 C4043 1 C4026 44 40 38 RAM_A<1> 43
A1 NC
135 NC 1 C4020 1 C4015 1 C4001
44 40 38
A1 NC 0.1UF 0.1UF 0.1UF NC 44 136 0.1UF 0.1UF 0.1UF
NC 44 136 20% 20% 20% NC VDDQ 20% 20% 20%
NC VDDQ 10V
2 CERM 10V
2 CERM 10V
2 CERM NC 45 137 RAM_CLK_D_P 38 2 10V 10V
2 CERM 10V
2 CERM
NC 45 137 RAM_CLK_C_P NC CK0 CERM
NC CK0 38 402 402 402 46 138 RAM_CLK_D_N 38
402 402 402
46 138 RAM_CLK_C_N 38
VDD CKO*
VDD CKO* NC 47 139
NC 47 139 NC VSS
RAM_A<0> 48
NC VSS
140 NC
1 C4048 1 C4046 1 C4029 44 40 38 RAM_A<0> 48
A0 NC
140 NC 1 C4017 1 C4016 1 C4027
44 40 38 A0 NC 0.1UF 0.1UF 0.1UF NC 49 141 RAM_A<10> 38 40 45
0.1UF 0.1UF 0.1UF
NC 49 141 RAM_A<10> 38 40 45
20% 20% 20% NC A10 20% 20% 20%
50
NC A10
142 NC 2 10V
CERM 2 10V
CERM 2 10V
CERM
50
VSS NC
142 NC 2 10V
CERM 2 10V
CERM 2 10V
CERM
VSS NC 402 402 402 NC 51 143 402 402 402
NC 51 143 NC VDDQ
NC VDDQ RAM_BA<1> 52 144 NC
RAM_BA<1> 52 144 NC 45 40 38 BA1 NC
45 40 38 BA1 NC 1 C4031 1 C4047 1 C4030 RAM_DQ<98> 53 145
1 C4019 1 C4051 1 C4004
44 38 RAM_DQ<34> 53 145 0.1UF 0.1UF 0.1UF 45 38 DQ32 VSS 0.1UF 0.1UF 0.1UF
DQ32 VSS 20% 20% 20% 54 146 RAM_DQ<96> 20% 20% 20%
54 146 RAM_DQ<35> 2 CERM
10V 10V
2 CERM
10V
2 CERM
VDDQ DQ36 38 45
10V
2 CERM
10V
2 CERM
10V
2 CERM
VDDQ DQ36 38 44
RAM_DQ<103> 55 147 RAM_DQ<97>
44 38 RAM_DQ<37> 55 147 RAM_DQ<33> 38 44
402 402 402 45 38 DQ33 DQ37 38 45
402 402 402
DQ33 DQ37 RAM_DQS<12> 56 148
44 38 RAM_DQS<4> 56 148 45 38 DQS4 VDD
DQS4 VDD RAM_DQ<101> 57 149
44 38 RAM_DQ<38> 57
DQ34 DM4/DQS13
149 1 C4050 1 C4049 1 C4032 45 38
58
DQ34 DM4/DQS13
150 RAM_DQ<99>
1 C4021 1 C4018 1 C4005
58 150 RAM_DQ<36> 38 44
0.1UF 0.1UF 0.1UF VSS DQ38 38 45
0.1UF 0.1UF 0.1UF
VSS DQ38 20% 20% 20% RAM_BA<0> 59 151 RAM_DQ<100> 20% 20% 20%
2 10V 10V 10V BA0 DQ39 10V 10V 10V
45 40 38 38 45
45 40 38 RAM_BA<0> 59 151 RAM_DQ<39> 38 44 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
BA0 DQ39 CERM RAM_DQ<102> 60 152
44 38 RAM_DQ<32> 60 152 402 402 402 45 38 DQ35 VSS 402 402 402
DQ35 VSS RAM_DQ<106> 61 153 RAM_DQ<104>
B 44 38 RAM_DQ<61> 61
62
DQ40
VDDQ
DQ44
RAS*
153
154
RAM_DQ<60>
RAM_RAS_L
38 44
38 40 45
1 C4028 1 C4022
45 38
62
63
DQ40
VDDQ
DQ44
RAS*
154
155
RAM_RAS_L
38 45
38 40 45
1 C4052 1 C4002 1 C4003
B
63 155 0.1UF 0.1UF 45 40 38 RAM_WE_L WE* DQ45 RAM_DQ<105> 38 45
0.1UF 0.1UF 0.1UF
45 40 38 RAM_WE_L WE* DQ45 RAM_DQ<63> 38 44
20% 20% 64 156 20% 20% 20%
RAM_DQ<111>
2 10V 2 10V DQ41 VDDQ 10V 10V 10V
45 38
44 38 RAM_DQ<57> 64 156 2 CERM 2 CERM 2 CERM
DQ41 VDDQ CERM CERM RAM_CAS_L 65 157 RAM_CS_L<8>
RAM_CAS_L 65 157 RAM_CS_L<0> 402 402 45 40 38 CAS* S0* 38 45
402 402 402
45 40 38 CAS* S0* 38 44
66 158 RAM_CS_L<9> 38 45
66 158 RAM_CS_L<1> 38 44
VSS S1*
VSS S1* RAM_DQS<13> 67 159
44 38 RAM_DQS<7> 67 159 45 38 DQS5 DM5/DQS14
DQS5 DM5/DQS14 45 38 RAM_DQ<107> 68 160
RAM_DQ<59> 68 160 DQ42 VSS
44 38 DQ42 VSS 45 38 RAM_DQ<110> 69 161 RAM_DQ<108> 38 45
44 38 RAM_DQ<56> 69 161 RAM_DQ<62> 38 44
DQ43 DQ46
DQ43 DQ46 70 162 RAM_DQ<109>
70 162 RAM_DQ<58> 38 44
VDD DQ47 38 45
VDD DQ47 NC 71 163 NC
NC 71 163 NC NC,S2* NC,S3*
NC,S2* NC,S3* 45 38 RAM_DQ<114> 72 164
44 38 RAM_DQ<43> 72 164 DQ48 VDDQ
DQ48 VDDQ 45 38 RAM_DQ<113> 73 165 RAM_DQ<112> 38 45
RAM_DQ<41> 73 165 RAM_DQ<40> DQ49 DQ52
44 38 DQ49 DQ52 38 44
74 166 RAM_DQ<117> 38 45
74 166 RAM_DQ<42> 38 44
VSS DQ53
VSS DQ53 RAM_CLK_E_N 75 167 RAM_A<13>
38 RAM_CLK_B_N 75 167 RAM_A<13> 38 40 44
38 CK2* NC,FETEN 38 40 44
CK2* NC,FETEN 38 RAM_CLK_E_P 76 168
RAM_CLK_B_P 76 168 CK2 VDD
38 CK2 VDD 77 169
77 169 VDDQ DM6/DQS15
VDDQ DM6/DQS15 RAM_DQS<14> 78 170 RAM_DQ<119>
44 38 RAM_DQS<5> 78 170 RAM_DQ<46> 38 44
45 38 DQS6 DQ54 38 45
DQS6 DQ54 45 38 RAM_DQ<115> 79 171 RAM_DQ<116> 38 45
RAM_DQ<47> 79 171 RAM_DQ<45> DQ50 DQ55
44 38 DQ50 DQ55 38 44
45 38 RAM_DQ<118> 80 172
44 38 RAM_DQ<44> 80 172 DQ51 VDDQ
DQ51 VDDQ 81 173 NC
81 173 NC VSS NC
VSS NC NC 82 174 RAM_DQ<120> 38 45
NC 82 174 RAM_DQ<49> 38 44
VDDID DQ60
VDDID DQ60 45 38 RAM_DQ<124> 83 175 RAM_DQ<121> 38 45
44 38 RAM_DQ<50> 83 175 RAM_DQ<48> 38 44
DQ56 DQ61
DQ56 DQ61 45 38 RAM_DQ<125> 84 176
RAM_DQ<51> 84 176 DQ57 VSS
DQ57 VSS
DIMMS
44 38
85 177
85 177 VDD DM7/DQS16
VDD DM7/DQS16 RAM_DQS<15> 86 178 RAM_DQ<122>
44 38 RAM_DQS<6> 86 178 RAM_DQ<54> 38 44
45 38 DQS7 DQ62 38 45
DQS7 DQ62 87 179
A 44 38
44 38
RAM_DQ<53>
RAM_DQ<52>
87
88
DQ58 DQ63
179
180
RAM_DQ<55> 38 44
45 38
45 38
RAM_DQ<127>
RAM_DQ<126> 88
DQ58
DQ59
DQ63
VDDQ
180
RAM_DQ<123> 38 45

A
DQ59 VDDQ 89 181 SA0
89 181 SD_A_SA0 VSS SA0
VSS SA0 NC 90 182 SA1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NC 90 182 SA1 WP SA1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
WP SA1 40 18 I2C_DIMM_SDA 91 183 SA2 SD_B_SA2 AGREES TO THE FOLLOWING
I2C_DIMM_SDA 91 183 SDA SA2
40 18
92
SDA SA2
184
SA2 R4014 40 18 I2C_DIMM_SCL 92
SCL VVDDSPD
184 R4006 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
40 18 I2C_DIMM_SCL SCL VVDDSPD 1
10K 2 1
10K 2
5% 5% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W TABLE_5_HEAD
1/16W
MF PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION MF
ADDR=0(A0/A1) 402 402 SIZE DRAWING NUMBER REV.
ADDR=1(A2/A3)
051-6482 I
TABLE_5_ITEM
516-0086 2 CONN,DDR DIMM 30 DEG J4000,J4001 17_INCH_LCD

TABLE_5_ITEM
CRITICAL
V
V R’S ADJACENT TO V’S OR G’S APPLE COMPUTER INC.
D
516-0087 2 CONN,DDR DIMM REVERSE 30 DEG J4000,J4001 20_INCH_LCD CRITICAL R V’S ADJACENT TO G’S FORBIDDEN
R SCALE SHT OF
V
NONE 40 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
46 45 44 7 PP1V25_RAM_VTT
46 45 44 7 PP1V25_RAM_VTT 46 45 44 7 PP1V25_RAM_VTT
8 RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT
RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5 RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RP4400 RP4400 RP4400 RP4400 RP4401 RP4401 RP4401 RP4401 1 C4400 1 C4412 RP4416 RP4416 RP4416 RP4416 RP4417 RP4417 RP4417 RP4417 1 C4407 1 C4414
1
R4400 1R4401 1R4402 1R4403 1R4404 1R4405 1R4406 1R4407 1 C4408 1 C4420
120 120 120 120 120 120 120 120 0.1UF 0.1UF
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM MF MF MF MF MF MF MF MF
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 402 402
1 2 3 4 1 2 3 4 402 402 1 2 3 4 1 2 3 4 402 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
40 38 RAM_DQS<0>
40 38 RAM_DQ<7> 40 38 RAM_DQ<33>
40 38 RAM_DQS<1>
40 38 RAM_DQ<0> 40 38 RAM_DQ<37>
40 38 RAM_DQS<2>
RAM_DQ<3> RAM_DQ<35>
D
40 38
40 38 RAM_DQ<2>
40 38
40 38 RAM_DQ<34>
40 38
40 38
RAM_DQS<3>
RAM_DQS<4>
D
40 38 RAM_DQ<5> 40 38 RAM_DQ<32>
40 38 RAM_DQS<5>
40 38 RAM_DQ<4> 40 38 RAM_DQ<39>
40 38 RAM_DQS<6>
40 38 RAM_DQ<1> 40 38 RAM_DQ<36>
40 38 RAM_DQS<7>
40 38 RAM_DQ<6> 40 38 RAM_DQ<38>
PP1V25_RAM_VTT 46 45 44 7 =PP2V5_RUN_RAM
46 45 44 7 PP1V25_RAM_VTT 46 45 44 7
8 7 6 5 8 7 6 5
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6
RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RP4404 RP4404 RP4404 RP4404 RP4405 RP4405 RP4405 RP4405 1 C4401 1 C4413 RP4420 RP4420 RP4420 RP4420 RP4421 RP4421 RP4421 RP4421 1 C4406 1 C4415 RP4437 RP4437 RP4437 RP4437 RP4436 RP4436 RP4436 RP4436 1 C4409 1 C4421
150 150 150 150 150 150 150 150 0.1UF 0.1UF
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V 2 10V
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 CERM
402
CERM
402
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 1 2 3 4 1 2 3 4
402 402 402 402
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
40 38 RAM_A<0>
40 38 RAM_DQ<10> 40 38 RAM_DQ<43>
40 38 RAM_A<1>
40 38 RAM_DQ<13> 40 38 RAM_DQ<42>
40 38 RAM_A<2>
40 38 RAM_DQ<11> 40 38 RAM_DQ<40>
40 38 RAM_A<3>
40 38 RAM_DQ<14> 40 38 RAM_DQ<41>
40 38 RAM_A<4>
C 40 38
40 38
RAM_DQ<15>
RAM_DQ<12>
40 38
40 38
RAM_DQ<44>
RAM_DQ<45>
40 38
40 38
RAM_A<6>
RAM_A<5>
C
40 38 RAM_DQ<8> 40 38 RAM_DQ<47>
40 38 RAM_A<7>
40 38 RAM_DQ<9> 40 38 RAM_DQ<46>
8 7 6 5 8 7 6 5
RP4438 RP4438 RP4438 RP4438 RP4439 RP4439 RP4439 RP4439

150 150 150 150 150 150 150 150
5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1
1 2 3 4 1 2 3 4
46 45 44 7 =PP2V5_RUN_RAM
8 7 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5

RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RAM_VTT RAM_VTT 8 7 6 5
RP4408 RP4408 RP4408 RP4408 RP4409 RP4409 RP4409 RP4409 1 C4402 1 C4416 RP4424 RP4424 RP4424 RP4424 RP4425 RP4425 RP4425 RP4425 1 C4405 1 C4419 RP4441 RP4441 RP4441 RP4441 R4416
1 1
R4417 1 C4410 1 C4422
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 150 150
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 150 150 150 150 5% 5%
0.1UF 0.1UF
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
5% 5% 5% 5% 1/16W 1/16W
20%
10V
20%
10V
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 1/16W 1/16W 1/16W 1/16W MF MF 2 CERM 2 CERM
402 402 402 402 SM1 SM1 SM1 SM1
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2 402 2 402 402 402
1 2 3 4
40 38 RAM_DQ<22> 40 38 RAM_DQ<51>
RP4441_NC
40 38 RAM_DQ<18> 40 38 RAM_DQ<48>
40 38 RAM_A<8>
40 38 RAM_DQ<19> 40 38 RAM_DQ<50>
40 38 RAM_A<9>
40 38 RAM_DQ<17> 40 38 RAM_DQ<49>
40 38 RAM_A<11>
40 38 RAM_DQ<20> 40 38 RAM_DQ<52>
40 38 RAM_A<12>
RAM_DQ<16> RAM_DQ<55>
B
40 38
40 38 RAM_DQ<21>
40 38
40 38 RAM_DQ<53>
40 38 RAM_A<13>
B
40 38 RAM_DQ<23> 40 38 RAM_DQ<54>
8 7 6 5 1 1
R4420 R4421
RP4442 RP4442 RP4442 RP4442 150 150
150 150 150 150 5% 5%
1/16W 1/16W
5% 5% 5% 5% MF MF
1/16W 1/16W 1/16W 1/16W
SM1 SM1 SM1 SM1 2 402 2 402
1 2 3 4
46 45 44 7 PP1V25_RAM_VTT 46 45 44 7 PP1V25_RAM_VTT 46 45 44 7 PP1V25_RAM_VTT

=PP2V5_RUN_RAM 7 44 45 46
8RAM_VTT 7RAM_VTT 6RAM_VTT RAM_VTT

5RAM_VTT 8 7RAM_VTT 6
RAM_VTT 5 RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 1 1 1 1
RP4412 RP4412 RP4412 RP4412 RP4413 RP4413 RP4413 RP4413 1 C4403 1 C4417 RP4428 RP4428 RP4428 RP4428 RP4429 RP4429 RP4429 RP4429 1 C4404 1 C4418 R4408
120
R4409
120
R4410
150
R4411
150
1 C4411
82 82 82 82 82 82 82 82 0.1UF 0.1UF 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 1/16W 1/16W 1/16W 1/16W
20%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM MF MF MF MF 2 CERM
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1
1 2 3 4 1 2 3 4
402 402
1 2 3 4 1 2 3 4
402 402 2 402 2 402 2 402 2 402 402
40 38 RAM_DQ<30> 40 38 RAM_DQ<58> 40 38 RAM_CKE<0>

40 38 RAM_DQ<28> 40 38 RAM_DQ<62> 40 38 RAM_CKE<1>
40 38 RAM_DQ<31> 40 38 RAM_DQ<56> 40 38 RAM_CS_L<0>
40 38
40 38
RAM_DQ<24>
RAM_DQ<29>
40 38
40 38
RAM_DQ<59>
RAM_DQ<57>
40 38 RAM_CS_L<1>
PARALLEL TERM
A 40 38
40 38
RAM_DQ<25>
RAM_DQ<26>
40 38
40 38
RAM_DQ<63>
RAM_DQ<60>
1
R4412
4.7K
1
R4413
4.7K
1
R4414
150
1
R4415
A
40 38 RAM_DQ<27> 40 38 RAM_DQ<61> 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF MF MF MF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2 402 2 402 2 402 2 402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 44 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
46 45 44 7 PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
1
R4500 1R4501 1R4502 1R4503 1R4504 1R4505 1R4506 1R4507 1 C4508 1 C4518
82 82 82 82 82 82 82 82 0.1UF 0.1UF 120 120 120 120 120 120 120 120 0.1UF 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 10V 10V
2 CERM 2 CERM 10V 10V 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM MF MF MF MF MF MF MF MF
1 2 3 4 1 2 3 4 402 402 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 402 402
1 2 3 4 1 2 3 4 402 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402
40 38 RAM_DQ<64> 40 38 RAM_DQS<8>
40 38 RAM_DQ<97>
RAM_DQ<67> RAM_DQS<9>
40 38 RAM_DQ<103>
RAM_DQ<65> RAM_DQS<10>
D
40 38
40 38 RAM_DQ<66>
40 38
40 38
RAM_DQ<96>
RAM_DQ<98>
40 38
40 38 RAM_DQS<11> D
40 38 RAM_DQ<70> 40 38 RAM_DQS<12>
40 38 RAM_DQ<102>
40 38 RAM_DQ<71> 40 38 RAM_DQS<13>
40 38 RAM_DQ<100>
40 38 RAM_DQ<68> 40 38 RAM_DQS<14>
40 38 RAM_DQ<99>
40 38 RAM_DQ<69> 40 38 RAM_DQS<15>
40 38 RAM_DQ<101>
40 38
40 38
46 45 44 7 PP1V25_RAM_VTT
46 45 44 7 PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
82 82 82 82 82 82 82 82 0.1UF 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 CERM 2 CERM
402 402 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1
1 2 3 4 1 2 3 4 402 402
1 2 3 4 1 2 3 4
40 38 RAM_DQ<79>
40 38 RAM_DQ<111>
40 38 RAM_DQ<72>
40 38 RAM_DQ<105>
40 38 RAM_DQ<74>
40 38 RAM_DQ<106>
40 38 RAM_DQ<75>
40 38 RAM_DQ<104>
C 40 38
40 38
RAM_DQ<77>
RAM_DQ<78>
40 38
40 38
RAM_DQ<109>
RAM_DQ<108>
C
40 38 RAM_DQ<76>
40 38 RAM_DQ<110>
40 38 RAM_DQ<73>
40 38 RAM_DQ<107>
1 C4509 1 C4519
0.1UF 0.1UF
20% 20%
10V 10V
2 CERM 2 CERM
402 402
46 45 44 7 PP1V25_RAM_VTT
46 45 44 7 PP1V25_RAM_VTT
46 45 44 7 PP1V25_RAM_VTT
46 44 7 =PP2V5_RUN_RAM
8 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
RP4508 RP4508 RP4508 RP4508 RP4509 RP4509 RP4509 RP4509 1 C4502 1 C4514 RP4524 RP4524 RP4524 RP4524 RP4525 RP4525 RP4525 RP4525 1 C4505 1 C4516 RAM_VTT RAM_VTT
82 82 82 82 82 82 82 82 0.1UF 0.1UF 7 6 7 6 7 6 7 6
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF 1
R4508 1
R4509
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
5% 5% 5% 5% 5% 5% 5% 5% 20%
10V
20%
10V RP4530 RP4530 RP4531 RP4531 RP4532 RP4532 RP4533 RP4533
402 402
1/16W
SM1
1/16W
SM1
1/16W
SM1
1/16W
SM1
1/16W
SM1
1/16W
SM1
1/16W
SM1
1/16W
SM1
2 CERM 2 CERM 150 150 150 150 150 150 150 150 120 120
1 2 3 4 1 2 3 4 402 402 5% 5%
1 2 3 4 1 2 3 4 5% 5% 5% 5% 5% 5% 5% 5% 1/16W 1/16W
40 38 RAM_DQ<84> 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF MF
RAM_DQ<117> SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1
40 38 RAM_DQ<87>
40 38
2 3 2 3 2 3 2 3 2 402 2 402
40 38 RAM_DQ<112>
40 38 RAM_DQ<85>
40 38 RAM_DQ<113> 40 38 RAM_RAS_L
40 38 RAM_DQ<82>
40 38 RAM_DQ<114> 40 38 RAM_BA<0>
40 38 RAM_DQ<86>
40 38 RAM_DQ<118> 40 38 RAM_CAS_L
RAM_DQ<80>
B
40 38
40 38 RAM_DQ<83>
40 38
40 38
RAM_DQ<116>
RAM_DQ<115>
40 38
40 38
RAM_WE_L
RAM_CS_L<9>
B
40 38 RAM_DQ<81>
40 38 RAM_DQ<119> 40 38 RAM_CS_L<8>
40 38 RAM_BA<1>
40 38 RAM_A<10>
40 38 RAM_CKE<4>
40 38 RAM_CKE<5>
1 4 1 4 1 4 1 4
RP4530
150
RP4530
150
RP4531
150
RP4531
150
RP4532
150
RP4532
150
RP4533
150
RP4533
150
1
R4510 1R4511
5% 5% 5% 5% 5% 5% 5% 5% 4.7K 4.7K
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 5% 5%
SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1 1/16W 1/16W
MF MF
8 5 8 5 8 5 8 5 2 402 2 402
46 45 44 7 PP1V25_RAM_VTT
46 45 44 7 PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT RAM_VTT RAM_VTT
82 82 82 82 82 82 82 82 0.1UF 0.1UF
5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 82 82 82 82 82 82 82 82 0.1UF 0.1UF
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 10V 10V 5% 5% 5% 5% 5% 5% 5% 5% 20% 20%
2 CERM 2 CERM
402 402
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2 10V
CERM 2 10V
CERM
1 2 3 4 1 2 3 4 SM1 SM1 SM1 SM1 SM1 SM1 SM1 SM1
402 402
1 2 3 4 1 2 3 4
40 38 RAM_DQ<95>
40 38 RAM_DQ<126>
40 38 RAM_DQ<94>
40 38 RAM_DQ<123>
40 38 RAM_DQ<92>
RAM_DQ<127>
PARALLEL TERM
40 38
40 38 RAM_DQ<88>
40 38 RAM_DQ<122>
40 38 RAM_DQ<93>
40 38 RAM_DQ<125>
A 40 38
40 38
RAM_DQ<89>
RAM_DQ<91>
40 38
40 38
RAM_DQ<124>
RAM_DQ<121> NOTICE OF PROPRIETARY PROPERTY
A
40 38 RAM_DQ<90>
40 38 RAM_DQ<120>
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 45 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ONLY STUFF ONE VTT VREG
46 45 44 7 =PP2V5_RUN_RAM
NOSTUFF NOSTUFF RAM_VTT

1
R4603
1
C4610
1
C4601 10UF
PHILIPS 10K
D 353S0603
0.1UF
10%
5%
1/16W 2
20%
6.3V D
2
16V CERM
2 X7R MF 805
402
VDD 603 2
U4700_REFOUT 5 REFOUT VTT 1

RAM_VTT
1
C4606 SHTDWN 4 VR4700_SHTDWN
0.1UF
10%
16V
2 X7R
603
VSS VSS
3
U4600
NE57811
SPAK-5
RAM_VTT
NOTE: U4700 PIN 4 IS LOW ACTIVE.
NOSTUFF
R4610 PP1V25_RAM_VTT 7 44 45
TURN_ON_VTT 1
0 2
3 VOLTAGE=1.25V
5%
1/16W
MF
402
3 NOSTUFF
D
Q4600 1
C4609 1
C4608 1
C4600 1
C4602
2N7002 220UF 10UF
20%
10UF
20%
10UF
20%
SM 20%
50 11 10 9 8 6 SYS_SLEEP 1 G S 2 2V 2
6.3V
2
6.3V
2
6.3V
TANT CERM CERM CERM
7343 1206 1206 1206
2
C PLACE 10UF CAPS NEAR DIMMS

C
7 =PP5V_RUN_RAM
VTT_ALT
C4651 1
0.1UF
20% VTT_ALT
10V
CERM 2
402 Q4651 NTD70N03R
CASE369
46 45 44 7 =PP2V5_RUN_RAM
S
4
3
VTT_ALT
1 C4655 VTT_ALT
G
22uF
R4671
2
20% SEMTECH
2 6.3V
1
CERM
1206
1K .5% 353S0880
1/16W VTT_ALT
603 FF 1
VCC 4
1
U4650_3
U4650 U4650_6 D VTT_ALT
3 REF DRVH 6
SC1116 MIN_NECK_WIDTH=10MIL Q4652
5 FB DRVL 4
U4650_4 MIN_LINE_WIDTH=25MIL 1 G NTD70N03R
CASE369
SOT23-6L VTT_ALT S
B VTT_ALT VTT_ALT
B
2
2
VTT_ALT R4672 GND R4673 R4674 3
C4650
2
1 2 1K 5% 1K 5%
402 402
0.1UF 1K .5% MF MF
1
1
20% 1/16W 1/16W 1/16W
10V 603 FF
2 CERM
R4673_1
1
402 R4674_1
VTT_ALT
1 C4652 VTT_ALT
0.0047UF
10%
25V
2 CERM
1 C4653
0.0047UF
402 10%
2 25V
CERM
402
MEM TERM VREGS

A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 46 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AGP_CBE<1..0> AGP_AD_0 AGP_DATA

60 37 28 7 =PP1V5_PWRON_NB_AVDD R4800
49 48
AGP_CBE<3..2>
I46
AGP_AD_1 AGP_DATA
1
2.2 2 PP1V5_PWRON_AGP_NB_AVDD
=PP1V5_AGP 7 48 49
49 48 I48
5% MIN_NECK_WIDTH=10MIL 49 48 AGP_SB_STBF AGP_SB_STBS AGP_STROBE AGP_SB_STB I49
1/16W
MF 1C4811 C4816 1 49 48 AGP_SB_STBS AGP_SB_STBS AGP_STROBE AGP_SB_STB
AG10
AC10
603 I50
1UF 0.1UF
AE6
AG4
AE2
AE7
AB4
Y11
W10
10% 20% 49 48 AGP_AD_STBF<0> AGP_AD_STB_0 AGP_STROBE AGP_AD_STB0 I51
W2
W6
V9
2 6.3V
CERM 2 10V
CERM 49 48 AGP_AD_STBS<0> AGP_AD_STB_0 AGP_STROBE AGP_AD_STB0 I52
402 402 AGP VDD_AGP 49 48 AGP_AD_STBF<1> AGP_AD_STB_1 AGP_STROBE AGP_AD_STB1
REFCLK_AVDD I53
OMIT
49 48 AGP_AD_STBS<1> AGP_AD_STB_1 AGP_STROBE AGP_AD_STB1 I54
U3 D
D 49 48 AGP_CBE<0> AG8 AGP_CBE0
AF8 AGP_CBE1
U3LITE
V1.0-300MM
AGP_AD0 AB11
AGP_AD1 AA11
AGP_AD<0>
AGP_AD<1>
48 49
48 49
49 48 AGP_DBI_LO AGP_AD_1 AGP_DATA I55
AGP_CBE<1> PBGA AGP_DBI_HI AGP_AD_1 AGP_DATA
AGP_AD2 AG11
49 48 49 48 I56
(SYM 4 OF 7)
AGP_AD<2> 48 49
49 48 AGP_DBI_LO AA6 AGP_DBI_LO AGP_AD3 AH12 AGP_AD<3> 48 49

AGP_AD<15..0> AGP_AD_0 AGP_DATA
AGP_AD4 AC11
49 48 I57
AGP_AD<4>
AGP_AD_STBF<0> AE8 AGP_AD_STBF0 48 49
AGP_AD<31..16> AGP_AD_1 AGP_DATA
49 48
AGP_AD5 AD11 AGP_AD<5>
49 48 I58
AGP_AD_STBS<0> AD8 AGP_AD_STBS0 48 49
49 48
AGP_AD6 AE11 AGP_AD<6> 48 49
AF11 49 48 AGP_SBA_L<7..0> AGP_SBA AGP_DATA I59
AGP_AD7 AGP_AD<7> 48 49
AGP_AD8 AH8 AGP_AD<8> 48 49
AGP_AD9 AH9 AGP_AD<9> 48 49
DBIHI AND DBILO AGP AGP_AD10 AH10 AGP_AD<10> 48 49 DBI_HI IS NOT A STROBE BUT SHARES THE SAME TOPOLOGY AS A STROBE
GROUPS WITH STROBE1 INTERFACE AGP_AD11 AH11 AGP_AD<11> 48 49
FOR CONSTRAINTS AGP_AD12 AG9 AGP_AD<12> 48 49
AGP_AD13 AF9 AGP_AD<13> 48 49
AGP_AD14 AE9 AGP_AD<14> 48 49
AGP_AD15 AD9 AGP_AD<15> 48 49
Y8 AGP_CBE2 AGP_AD16 Y4 AGP_AD<16> 48 49

AGP_CBE<2>
49 48
AGP_CBE<3> AA5 AGP_CBE3 AGP_AD17 Y3 AGP_AD<17> 48 49 LEVEL SHIFTER FOR U3LITE

AGP_AD18 Y6
49 48
AGP_AD<18> 48 49
AA4 AGP_DBI_HI Y5 AGP BUSY AND STOP ARE NOT USED IN ALL DESIGNS
49 48 AGP_DBI_HI AGP_AD19 AGP_AD<19> 48 49
AGP_AD20 AA1 AGP_AD<20>

AGP_AD_STBF<1> AA3 AGP_AD_STBF1 48 49
49 48
AGP_AD21 Y2 AGP_AD<21> 48 49 59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP
AGP_AD_STBS<1> AA2 AGP_AD_STBS1
49 48
AGP_AD22 Y1 AGP_AD<22> 48 49 49 48 7 =PP1V5_AGP
AGP_AD23 Y7 AGP_AD<23> 48 49
AGP_AD24 V5 AGP_AD<24> 48 49
AGP_AD25 V6 AGP_AD<25> 48 49 AGP_BUSYSTOP

C AGP_AD26
AGP_AD27
V4
V3
AGP_AD<26>
AGP_AD<27>
48 49
48 49
R4811
1
10K
1
R4807
10K
C
AGP_AD28 V8 AGP_AD<28> 48 49
1
R4812 5%
1/16W
5%
1/16W
V7 10K MF MF
AGP_AD29 AGP_AD<29> 48 49 5% 2 402 2 402
W1 1/16W
AGP_AD30 AGP_AD<30> 48 49 MF NB_AGP_BUSY_L 48
AA7 2 402
AGP_BUSY_L_F
AGP_AD31 AGP_AD<31> 48 49
6 3
AGP_BUSYSTOP AGP_BUSYSTOP
AD1 AGP_SB_STBF AGP_SBA0 AG2 AGP_SBA_L<0> 48 49 D
Q4801 D
Q4801
AGP_SB_STBF
AGP_SBA1 AF3
49 48
AE1 AGP_SB_STBS AGP_SBA_L<1> 48 49 2N7002DW 2N7002DW
AGP_SB_STBS SOT-363 SOT-363
AGP_SBA2 AH1
49 48
AGP_SBA_L<2> 48 49 49 AGP_BUSY_L 2 G S 5 G S
AGP_SBA3 AG3 AGP_SBA_L<3> 48 49
AD2 1 4
AGP_SBA4 AGP_SBA_L<4> 48 49
AGP_SBA5 AF2 AGP_SBA_L<5> 48 49
AGP_SBA6 AG1 AGP_SBA_L<6> 48 49
AGP_SBA7 AF1 AGP_SBA_L<7> 48 49
49 AGP_PAR AH7 AGP_PAR

AC4 AGP_ST0 AGP_REFCLK AH2 AGP_CLK66M_NB 27
49 AGP_ST<0> 59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP
49 AGP_ST<1> AC1 AGP_ST1
49 AGP_ST<2> AB1 AGP_ST2 AGP_BUSY* AC8 NB_AGP_BUSY_L 48 59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP
AGP_STP_AGP* AD4 NB_STOP_AGP_L
49 AGP_RBF AC6 AGP_RBF
48
49 AGP_WBF AD6 AGP_WBF

49 48 7 =PP1V5_AGP AGP_BUSYSTOP R4810
1
AGP_TRDY AH5
1
R4808 10K
49 AGP_TRDY 5%
AG6 PVTREF RESISTOR 1
R4809 10K 1/16W
AGP_IRDY AGP_IRDY 5% MF
R4801
49
AGP_GNT AC3 10K 1/16W 2 402

AGP_GNT 5% MF
49
AGP_FRAME AH6 1
182 2 1/16W 2 402 STOP_AGP_L
AGP_FRAME
B
49
49 AGP_DEVSEL AF6 AGP_DEVSEL 1%

1/16W
MF
2 402
STOP_AGP_L_F
3 AGP_BUSYSTOP
49
B
AGP_PVTREF1 AG5 AGP_PVTREF1 MF AGP_BUSYSTOP
AGP_PVTREF2 AF5 AGP_PVTREF2
402 R4813 3
AGP_BUSYSTOP
D Q4803
1K 2N7002
49 AGP_REQ AB9 AGP_REQ 48 NB_STOP_AGP_L 1 2 STOP_AGP_L_R 1 Q4802 1 G S
SM
49 AGP_STOP AH4 AGP_STOP AGP_VREFCG AC5 TP_VREF_CG 6 5% 2N3904
1/16W SM
AGP_VREFGC AA9 AGP_VREF_GC 49 MF 2 2
402
AGP_TYPEDET_L AC9 AGP_TYPEDET
AGP_MB_AGP8X_DET AA8
49
AB8 AGP_GC_AGP8X_DET TP_AGP_MB_AGP8X_DET_L 6
49 NB_AGP_GCDET_L
AGP_REFCLK_AVSS
C4817
AE5
1
0.01UF
20%
2 16V
CERM
402
MASTER: GILA
=PP1V5_AGP 7 48 49
U3LITE AGP
A 1 C4800 1 C4801 1 C4802 1 C4803 1 C4804 1 C4805 1 C4806 1 C4807 1 C4808 1 C4810 1 C4812 1 C4813 1 C4814 1 C4815 NOTICE OF PROPRIETARY PROPERTY
A
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 10V
2 CERM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 402 402 402 402 402 402 402 402 402 402 402 402 402 AGREES TO THE FOLLOWING
D 051-6482 I
APPLE COMPUTER INC.
SCALE
NONE 48 103
SHT OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD
NVIDIA RECOMMENDS A WIDER RANGE OF CAP VALUES, EMC LIKES ONE VALUE
=PP1V5_AGP
338S0176 1 IC,NV18B,GRAPHIC CTRL,C1 U4900 NV18B
TABLE_5_ITEM
49 48 7
OUTPUT DRIVER BYPASS
TABLE_5_ITEM
338S0175 1 IC,NV34,GRAPHIC CTRL,B1 U4900 NV34

U4900 C4912 C4911 C4904 C4905 C4906 C4913 C4907 C4908 C4909 C4910
NV18B 1 0.01UF 1 0.01UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF
U3LITE AGP I/O REFERENCE BGA
(1 OF 5)
10%
16V
10%
16V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
(PLACE CLOSE TO GPU AGP BALL) AGP_AD<0> AJ28 PCIAD0
AE14 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
48
OMIT AE11 402 402 402 402 402 402 402 402 402 402
AGP_AD<1> AK28 PCIAD1
48
AE17
AGP_AD<2> AH27 PCIAD2
D 49 48 7 =PP1V5_AGP
48
48 AGP_AD<3> AK27
AJ27
PCIAD3
AE20
AGPVDDQ AE23
D
AGP_AD<4> PCIAD4
48
AD11
R4914
1 48 AGP_AD<5> AH26 PCIAD5 AD14 58 50 PPVCORE_GPU CORE BYPASS
3.32K AGP_AD<6> AJ26 PCIAD6
1%
48
AD23
1/16W AGP_AD<7> AH25 PCIAD7
MF
48
AD20
AGP_AD<8> AH23 PCIAD8 C4914 C4915 C4916 C4917 C4918 C4919 C4920 C4921 C4922 C4923 C4924
2 402 48
AD17
48 AGP_AD<9> AJ23 PCIAD9 1 0.01UF 1 0.01UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF
AGP_VREF_GC 48
48 AGP_AD<10> AH22 PCIAD10 10% 10% 20% 20% 20% 20% 20% 20% 20% 20% 20%
16V 16V 10V 10V 10V 10V 10V 10V 10V 10V 10V
AGP_AD<11> AJ22 PCIAD11 2 2 2 2 2 2 2 2 2 2 2
48
AA17 CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
R4940 1 C4940
1 AGP_AD<12> AJ21 PCIAD12 402 402 402 402 402 402 402 402 402 402 402
48
AA18
1.02K 0.01UF AGP_AD<13> AK21 PCIAD13
1%
48
L20
1/16W 20% AGP_AD<14> AH20 PCIAD14
MF 16V
2 CERM
48
Y20
2 402
AGP_AD<15> AJ20 PCIAD15
402 48
L13
AGP_AD<16> AG26 PCIAD16
48
Y13
AGP_AD<17> AE24 PCIAD17
48
N20
48
P20
AGP_AD<19> AG24 PCIAD19 C4925 C4926 C4927 C4928 C4929 C4930 C4931 C4932
48
U20 1 0.01UF 1 0.01UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF
AGP_AD<20> AF24 PCIAD20
48
V20
AGP_AD<21> AG23 PCIAD21 10% 10% 20% 20% 20% 20% 20% 20%
VDD L11
48
16V 16V 10V 10V 10V 10V 10V 10V
AGP_AD<22> AE22 PCIAD22 2 2 2 2 2 2 2 2
48
N11 CERM CERM CERM CERM CERM CERM CERM CERM
AGP_AD<23> AF22 PCIAD23 402 402 402 402 402 402 402 402
48
P11
48
U11
48
V11
48
Y11
AGP_AD<27> AF19 PCIAD27
48
L14 =PP3V3_AGP
59 58 57 56 52 51 50 49 48 7
48
Y14
AF18
C 48
48
AGP_AD<29>
AGP_AD<30> AG18
PCIAD29
PCIAD30
L17
Y17 1 C4961 1 C4960
2
C4902
10UF
2
C4900
10UF
2
C4903
10UF
2
C4901
10UF
C4933
1 0.1UF
C4934
1 0.1UF
C4935
1 0.1UF L4901
NV34 C
48
L18 10UF 10UF 20% 20% 20% 20% 20% 20% 20%
1000-OHM-EMI
20% 20% 10V 10V 10V
AGP 2X,4X : AGP 8X Y18 2
6.3V
CERM 2
6.3V
CERM
1 6.3V 1 6.3V 1 6.3V 1 6.3V
CERM CERM CERM CERM 1 2
48 AGP_CBE<0> AJ24 PCIC0/BE0* : C0*/BE0 805 805
805 805 805 805 402 402 402
SM
48 AGP_CBE<1> AH19 PCIC1/BE1* : C1*/BE1
48 AGP_CBE<2> AF25 PCIC2/BE2* : C2*/BE2
48 AGP_CBE<3> AG22 PCIC3/BE3* : C3*/BE3 AGP_PLLVDD VOLTAGE=3.3V
R4912 27 AGP_CLK66M_GPU AG12 PCICLK : CLK
NV34 NV34
1 C4956
NV34
1 C4955
GPU_RESET_L
0
NV_PCIRST_L AF15 PCIRST* =PP3V3_AGP 7
1
C4959
8 1 2 : RST* 48 49 50 51 52 56 57 58 59
4.7UF 0.1UF 0.001UF
5% H6 20% 20% 10%
1/16W
AGP_GNT AE15 PCIGNT* AC6
6.3V
2 CERM 2 10V
CERM 2 50V
CERM
MF
402
48 : GNT 805 402 402
48 AGP_REQ AF13 PCIREQ* : REQ U7
G14
48 AGP_FRAME AK16 PCIFRAME* : FRAME U6
AGP_IRDY AG16 PCIIRDY* : IRDY AD15
48
AJ17 I/O BYPASS
=PP3V3_AGP 7 48 49 50 51 52 56 57 58 59 48 AGP_TRDY PCITRDY* : TRDY VDD33 H7
48 AGP_DEVSEL AJ16 PCIDEVSEL* : DEVSEL AD16
AGP_STOP AH17 PCISTOP* : STOP AD19
R4908
48
AGP_PAR AK18 AD22 C4936 C4942 C4938 C4939 C4941 C4937

4.99K 48 PCIPAR : PAR 1 0.01UF 1 0.01UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF
1 2 AGP_INT_L 25 49 AC7
10% 10% 20% 20% 20% 20%
1% 49 25 AGP_INT_L AG15 PCIINTA* : INTA AD12 16V 16V 10V 10V 10V 10V
1/16W
MF TP_GPU_INTB_L AE10 P24 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402
6 NC_PCIINTB*: INTB 402 402 402 402 402 402
48 AGP_RBF AG14 AGPRBF* : RBF
48 AGP_WBF AG17 AGPWBF* : WBF
B 48
48
AGP_DBI_HI
AGP_DBI_LO
AJ18
AJ19
AGPPIPE*
<RESRVD>
:
:
DBI_HI
DBI_LO =PP5V_AGP 7 50 59
B
48 AGP_ST<0> AG13 AGPST0 : ST0
48 NB_AGP_GCDET_L 48 AGP_ST<1> AE16 AGPST1 : ST1 VD50CLAMP0 N4
48 AGP_ST<2> AE13 AGPST2 : ST2 VD50CLAMP1 AE9 C4943 C4944 C4945 C4946 C4947 C4949 C4950 C4951 C4952
48 AGP_TYPEDET_L 2 1 0.01UF 1 0.01UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF 1 0.1UF
C4953 C4954 10UF
AGP_AD_STBF<0> AK24 AGP_PLLVDD AE12 1 0.1UF 1 0.1UF 20% 10% 10% 20% 20% 20% 20% 20% 20%
AGPADSTBF0 : ADSTBF0
R4913 1R4909
48
1 16V 16V 10V 10V 10V 10V 10V 10V
AGP_AD_STBS<0> AJ25 AGPADSTBS0* : ADSTBS0 50 OHM
20% 20% 1 6.3V
2 2 2 2 2 2 2 2
0 10K 48
AG21 TO VDDQ 10V 10V CERM CERM CERM CERM CERM CERM CERM CERM CERM
5% 5% AGP_AD_STBF<1> AGPADSTBF1 : ADSTBF1 2 2 805 402 402 402 402 402 402 402 402
AGPCALPD AA13
48 CERM CERM
1/16W 1/16W AF21
MF MF 48 AGP_AD_STBS<1> AGPADSTBS1* : ADSTBS1 402 402
2 402 2 402
48 AGP_SB_STBF AK13 AGPSBSTBF : SBSTBF 50 OHM GPU_50PULLUP
TO GND
48 AGP_SB_STBS AJ13 AGPSBSTBS* : SBSTBS AGPCALPU AA14 GPU_50PULLDWN
48 AGP_SBA_L<0> AJ11 AGPSBA0 : SBA0*

48 AGP_SBA_L<1> AH11 AGPSBA1 : SBA1* 10K OHM
AGP_SBA_L<2> AJ12 AGPSBA2 : SBA2* TO GND =PP1V5_AGP 7
TESTMODE AE5
48 48 49
GPU_TMODE
48 AGP_SBA_L<3> AH12 AGPSBA3 : SBA3* 1 R4902
AGP_SBA_L<4> AJ14 AGPSBA4 : SBA4* 1 R4901
48
1 R4900 49.9
DOES HOOP UP AGP_BUSY_L & 48 AGP_SBA_L<5> AH14 AGPSBA5 : SBA5* 10K
AGP_SBA_L<6> AJ15 AGPSBA6 49.9 1%
: SBA6* 5%
STOP_AGP_L TO 3.3V OR 1.5V? AGP_SBA_L<7> AH15 AGPSBA7 1/16W
1% 1/16W
2 MF
48 : SBA7* 2 MF 1/16W
2 MF 402 =PP1V5_AGP FROM Q27 PAGE 24
GPU_MBDET_L AF16 <RESRVD> : MBDET* 402 49 48 7
402
48 AGP_BUSY_L AF12 AGPBUSY* : BUSY*
STOP_AGP_L AG11 AGPSTOP* : STOP* 1
R4906
NVIDIA AGP
48
=PP3V3_AGP 7 48 49 50 51 52 56 57 58
3.32K
D2 TRST*
59
AK29 AGPVREF
C2 TCLK
49 GPU_AGP_VREF : AGPVREF 1%
A
C1 TMS
D1 TDI
E2 TDO
1/16W
NC
1
NV34
R4910 1
NV34
R4911
MF
2 402
GPU AGP I/O REFERENCE
(PLACE CLOSE TO U3LITE AGP BALLS) NOTICE OF PROPRIETARY PROPERTY
A
10K 10K
A1
TP_GPU<1>AK30
G6
R7
T7
R4903
1 56 52 51 50 49 48 7
59 58 57
=PP3V3_AGP
R4905 5% 5% GPU_AGP_VREF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
AGP VERSION SELECT 0 NVAGP_TRST_L 1 2 1/16W 1/16W VOLTAGE=0.35V
49
5% NOSTUFF NOSTUFF MIN_LINE_WIDTH=25MIL AGREES TO THE FOLLOWING
TP_GPU<0>
TP_GPU<2>
(LOW = AGP V3.X) 1/16W 2 MF 2 MF

1K MIN_NECK_WIDTH=10MIL
(HIGH = AGP V2.X)

MF
2 402
R49501 1
R4951 402 402 1
R4907 1 C4957
10K 10K TP_NVAGP_TDO II NOT TO REPRODUCE OR COPY IT
5% 5%
6
1.02K 0.01UF
1/16W 1/16W TP_NVAGP_TDI 1% 20% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF MF 1/16W
402 2 2 402 TP_NVAGP_TMS MF 2 16V
CERM
2 402 402 SIZE DRAWING NUMBER REV.
NO_TEST
NO_TEST
NO_TEST
R4904
NVAGP_TCLK 1 2
APPLE COMPUTER INC.
D 051-6482 I
GPU_BALLR7 1K SCALE SHT OF
GPU_BALLT7
BOUNDRY SCAN AVAILABLE ONLY ON NV3X SERIES NONE 49 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU VCORE VREG

TABLE_5_HEAD
PPVCORE_GPU PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_ITEM
1.60VDC 114S2803 1 RES,2.8K OHM,1/16W,1%,0402 R5003 NV18B

TABLE_5_ITEM
1.40VDC 114S1213 1 RES,1.21K OHM,1/16W,1%,0402 R5003 NV34
=PP12V_AGP =PP3V3_AGP NOTE:

D
59 7 7 48 49 51 52 56
57 58 59
SET OUTPUT=1.60V FOR NV18B D
=PP5V_AGP
SET OUTPUT=1.40V FOR NV34
59 49 7
R5000
1 1 C5016 IRU3037CS VREF=1.25VDC
4.7 1UF 1 C5001 1
C5002 1
C5003 VOUT=VREF*(R5004+R5005)/R5005=1.60(OR 1.40) VDC
5% 20%
1/10W 2 25V 10UF 390UF 390UF
C5004 1 FF
CERM
805
20%
6.3V 20%
2 6.3V
20%
2 6.3V PEAK CURRENT OF TOTAL RAILS
1UF 2 805 4 2 CERM
ELEC ELEC
20%
25V U5000_VC
1206 8X11.5-TH 8X11.5-TH 7.2A WITH NV34
CERM 2 D
805
R5002 Q5001
2 6 0 1 G NTD70N03R
1 2 Q5001_GATE
VCC VC S
CASE369
U5000 5%
1/10W
IRU3037CS
SOI
FF
805 3 L5001
HD 5 U5000_GATE_H 1.6UH
U5000_SS 8 SS Q5002_DRAIN 1 2 PPVCORE_GPU 49 50 58
VOLTAGE=1.65V
LD 3 U5000_GATE_L TH OMIT MIN_LINE_WIDTH=25MIL
NOSTUFF MIN_NECK_WIDTH=10MIL
U5000_COMP 7 COMP
4
R5004
1
1 C5007 R5003
1
FB 1 U5000_FEEDBACK 0.51 3300PF2.8K

5% 1%
1
R5001 GND
D 1/4W
FF
10%
2 50V
CERM
1/16W
MF
27.4K
1% 4 Q5002 2 1206 603 2 402
1/16W 1 G NTD70N03R R5004_P2
1
C5008 1
C5009
GPU VTT VREG
MF
1 C5014 2 402
1 C5013 1 C5006 S
CASE369 1800UF
20%
1800UF
20%
0.1UF R5001_2 68PF 220PF NOSTUFF 2 6.3V 2 6.3V
20%
16V
2 CERM
5%
50V
2 CERM
5%
25V
2 CERM 1 C5005 3
1 C5012 1
R5005 ELEC
TH-KZJ
ELEC
TH-KZJ
0.1UF 10K
603 1 C5023 603 402 0.022UF 20% 1%
10% 50V
3900PF 50V 2 CERM 1/16W
2 CERM 1206 MF
5%
50V 603 2 402 55 54 52 7 PP2V5_GPU
2 CERM
C 603
NOSTUFF NOSTUFF
1 1
NOSTUFF
C5052
C
1
C5051 R5050
0.1UF 10K 10UF
20%
PP1V25_GPU_VTT 52
U5000_FEEDBACK 10%
5% 6.3V MIN_LINE_WIDTH=25MIL
1/16W 2 MIN_NECK_WIDTH=10MIL
2
16V CERM
2 X7R MF 805 VOLTAGE=1.25V
402
VDD 603 2
U5050_REFOUT 5 REFOUT VTT 1

1
C5050 SHTDWN 4 U5050_SHTDWN 1
C5053 1
C5054
0.1UF
10%
330UF 10UF
20%
20%
16V 6.3V
2 X7R VSS VSS 2 6.3V 2 CERM
ELEC
603 SM-1 1206
3
U5050
NE57811
SPAK-5
NOSTUFF
AGP 1.5V VREG PLACE 10UF CAP NEAR GPU
PP2V5_PWRON PP1V5_PWRON
58 50 49 PPVCORE_GPU NOTE:
NOSTUFF
PP1V5_RUN SET OUTPUT=1.5V
D5001
SC4215 VREF=0.8VDC
VOUT=VREF*(R5015+R5017)/R5017=1.5 VDC
2
10BQ040
NOSTUFF
PEAK CURRENT OF TOTAL RAILS
B 3 VIN
VR5001
VO 6
SM
0.95A B
1
2
SC4215 1
NOSTUFF
Q5006
EN SOIC ADJ 7 VR5001_ADJ R5015 SI4410DY
NOSTUFF 174 SOI
1 1%
C5000 1 NC 1/10W NOSTUFF NOSTUFF NOSTUFF
7 8
10UF FF 1 1 1
4 C5020
3
20% NC NC 2 805 C5022 R5007
6.3V
THM 5 10UF 330UF
1 2
2 NC 0
PP5V_PWRON
6
CERM 20% 20%

1206 GND PAD 6.3V 5% RDSON=0.012 OHM
NOSTUFF 2 CERM 2 6.3V 1/10W @ VGS=3.5 V
5
ELEC
8
FF
1 1206 SM-2
R5017 2 805
NOSTUFF
200
1% C5060
4
1/10W
FF R5021 0.1UF
2 805 100K 1 2
2 1 Q5006G
5%
1/16W 20%
MF 10V
402 3 CERM
402
NOTE:CONNECT VR5001 PIN 9 TO GND PLANE. Q5007 D
2N7002
SM
S G 1 SYS_SLEEP 6 8 9 10 11 46
GRAPHICS VREGS
A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 50 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP TMDS_XMIT_SI TMDS_XMIT_SI

=PP3V3_AGP 7 48 49 50 51 52 56 57 58 59
L5102 L5101
FERR-EMI-100-OHM PP3V3_SI_VCC 51 FERR-EMI-100-OHM
VOLTAGE=3.3V VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL MIN_LINE_WIDTH=25MIL
1 2 PP3V3_SI_AVCC 1 2
MIN_NECK_WIDTH=10MIL MIN_NECK_WIDTH=10MIL
SM SM
C5107 1
C5106 1
C5104 1
10UF
1
C5103 1
C5102 1
C5101
20% 100PF 100PF 100PF 100PF 10UF
5% 5%
D
6.3V
CERM
805
2 50V
CERM
402
2
50V
CERM
402
2
2
5%
50V
CERM
402
2
5%
50V
CERM
402
2
20%
6.3V
CERM
805
D
TMDS_XMIT_SI TMDS_XMIT_SI TMDS_XMIT_SI
TMDS_XMIT_SI TMDS_XMIT_SI TMDS_XMIT_SI
L5100
FERR-EMI-100-OHM
VOLTAGE=3.3V
TMDS_XMIT_SI MIN_LINE_WIDTH=25MIL
1 2 3V_SI_PLLVCC MIN_NECK_WIDTH=10MIL
NOTE:
SM
C5109 1
C5108 1
C5105 1 330OHM HI SWING
C5100 1
10UF 100PF 100PF RESISTOR MAY NEED TO BE
10UF 20% 5% 5% HIGHER
20% 6.3V 50V 50V
6.3V CERM 2 CERM 2 CERM 2
CERM 2 805 402 402
805 TMDS_XMIT_SI TMDS_XMIT_SI TMDS_XMIT_SI
TMDS_XMIT_SI
TMDS_XMIT_SI
PLL NOISE SHOULD BE LESS THAN 100MV PEAK-TO-PEAK 1
R5127
330
5%
1/16W
TMDS_XMIT_SI NOSTUFF NOSTUFF NOSTUFF MF
1 1 1 402
R5100 R5128 R5113
1
R5129 2
4.7K 4.7K 4.7K 4.7K
28
PVCC1 46
PVCC2 40
AVCC 34
22
5% 5% 5%
3
5%
1/16W 1/16W 1/16W
AVCC
VCC
VCC
1/16W
MF MF MF MF
402 2 402 2 402 2 2
402
58 SI_SCL 27 SCL/DK1 MSEN 48 NC

SI_SDA
IPD
58 26 SDA/DK0
TMDS_XMIT_SI
NC 24 CTL3/A2 IPD
R5130 SI_I2C_OFF 25 ISEL/RST* IPD
PCI_RESET_L
0 2 SI_PCI_RESET_L SI_PCI_RESET_L
74 58 8 6 1 51 51 47 PD* TMDS_XMIT_SI
R5112
C 5%
1/16W
MF
402 57 51
SI_EDGE
DVOD0
44
18
EDGE/HTPLG
D0 U5100
TXC+ 33
TXC- 32
SI_TMDS_CKP
SI_TMDS_CKM
TMDS_XMIT_SI
22 1 2 R5111
22 1 2 TMDS_CKP
TMDS_CKM
58 59
58 59
C
57 51 DVOD1 17 D1 SIL1162 TX0+ 36 SI_TMDS_D0P 22
TMDS_XMIT_SI
1 2 R5110 TMDS_D0P 58 59
TMDS_XMIT_SI
57 56 DVOD2 16 D2 TSSOP TX0- 35 SI_TMDS_D0M 22 1 2 R5109 TMDS_D0M 58 59
57 56 DVOD3 15 D3 SI_TMDS_D1P 22
TMDS_XMIT_SI
R5108
TMDS_XMIT_SI TX1+ 39 1 2 TMDS_D1P 58 59
DVOD4 14 D4 TMDS_XMIT_SI
57 51
TX1- 38 SI_TMDS_D1M 22 1 2 R5107 TMDS_D1M 58 59
57 51 DVOD5 13 D5 CRITICAL
TMDS_XMIT_SI
57 51 DVOD6 10 D6 TX2+ 42 SI_TMDS_D2P 22 1 2 R5106 TMDS_D2P 58 59
TMDS_XMIT_SI
57 51 DVOD7 9 D7 TX2- 41 SI_TMDS_D2M 22 1 2 R5105 TMDS_D2M 58 59
57 56 DVOD8 8 D8 5%
1/16W
57 51 DVOD9 7 D9 MF
402
57 51 DVOD10 6 D10
57 51 DVOD11 5 D11
57 DVODE 19 DE PLACE TMDS RESISTORS ON OPPOSITE SIDE TO TMDS
57 56 DVOHSYNC 20 HSYNC RESISTORS ON PAGE 25
EXT_SWING 30 SI_EXT_SWING_SET
57 DVOVSYNC 21 VSYNC
57 DVOCLKOUT 12 IDCK+ VREF 2
11 IDCK- PP3V3_SI_VCC
THRML
51
PGND
PGND
AGND
AGND
AGND
PAD
GND
GND
GND
TMDS_XMIT_SI
1
R5116
29
45
31
43
37
23
49
0
5%
1/16W
MF
2 402
SI_VREF
B NOSTUFF
R5104 1
TMDS_XMIT_SI
R5103 1
NOSTUFF
R5102 1
TMDS_XMIT_SI
R5101 1
VOLTAGE=1.5V
NOSTUFF
B
1
4.7K 4.7K 4.7K 4.7K R5117
5% 5% 5% 5% 1K
1/16W 1/16W 1/16W 1/16W
MF MF MF MF 1%
=PP3V3_AGP 1/16W
59 58 57 56 52 51 50 49 48 7 402 2 402 2 402 2 402 2 MF
402
2
SILICON IMAGE 1162 TMDS

R5120
1
R5124
1 1
R5121 1
R5126
10K 10K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF MF MF MF
R5119
1
2 402
1
R5118 2 402 R5123 2 402 2 402 1
R5125
10K 10K 1 1
R5122
5% 5% 10K 10K
1/16W 1/16W 5% 10K 5%
MF MF 1/16W 5% 1/16W
2 402 2 402 MF
402
1/16W
MF
MF
2 402
2 2 402
57 51 DVOD11
57 51 DVOD10
57 51 DVOD9
57 51 DVOD7
57 51 DVOD6
57 51 DVOD5
DVOD4
57 51
EXTERNAL TMDS TRANSMITTER
A 57 51
57 51
DVOD1
DVOD0
A
LAST_MODIFIED=Mon Dec 13 20:02:16 2004
UNDEFINED RESET CONFIGURATION STRAPS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 51 103
8 7 6 5 4 3 2 1 DRAWING
8 7 6 5 4 3 2 1
H H
55 54 52 50 7 PP2V5_GPU
NVIDIA RECOMMENDS WIDER RANGE OF CAP VALUES, EMC LIKE ONE VALUE EVENLY DISTRIBUTE 0.01UF & 0.1 UF CAPS AMONGST FBVDDQ PINS ON NV ASIC
1
C5215 C5216 C5217 C5218 C5221 C5219 C5220 C5213 C5212 C5211 C5210 C5222 C5224 C5225 C5226 C5227 C5228 C5229 C5200 C5223 C5214 C5209
C5208 2 2 2 2 2 2 2 2 2 2 2 1 C5201 2 2 2 2 2 2 2 2 2 2 2 1 C5202
0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.1UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.1UF
10% 10% 20% 20% 20% 10% 20% 10% 20% 20% 20% 20% 10UF 20% 20% 20% 10% 20% 20% 10% 20% 10% 20% 20% 10UF
16V 20% 20%
2
CERM 1 16V 1 10V 1 10V 1 10V 1 16V 1 10V 1 16V 1 10V 1 10V 1 10V 1 10V 2 6.3V 1 10V 1 10V 1 10V 1 16V 1 10V 1 10V 1 16V 1 10V 1 16V 1 10V 1 10V 2 6.3V
402 CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
805 805
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
G F17
PP2V5_GPU 7 50 52 54 55
G
U4900
G11
NV18B
53 FBD<0> N25 FBAD0 G8
BGA U4900
53 FBD<1> N27 FBAD1 (3 OF 5) F8
NV18B
53 FBD<2> N26 FBAD2 L25
M25 OMIT
Y25 53 FBD<64> F13 FBCD0 (4 BGA
OF 5)
N13
53 FBD<3> FBAD3 D13 P13
K26 F11 53 FBD<65> FBCD1
53 FBD<4> FBAD4 E13 U13
K27 F14
53 FBD<66> FBCD2 OMIT
53 FBD<5> FBAD5 F12 V13
J27 F20 53 FBD<67> FBCD3
53 FBD<6> FBAD6 E10 M14
H27
53 FBD<68> FBCD4
53 FBD<7> FBAD7 FBVDDQ F23 53 FBD<69> D10 FBCD5 N14
53 FBD<8> N29 FBAD8 Y24
53 FBD<70> D9 FBCD6 P14
53 FBD<9> M29 FBAD9 L24
53 FBD<71> D8 FBCD7 R14
53 FBD<10> M28 FBAD10 G20
53 FBD<72> B13 FBCD8 T14
53 FBD<11> L29 FBAD11 G23
53 FBD<73> B12 FBCD9 U14
53 FBD<12> J29 FBAD12 H24
53 FBD<74> C12 FBCD10 V14
53 FBD<13> J28 FBAD13 AC24
53 FBD<75> B11 FBCD11 W14
53 FBD<14> H29 FBAD14 H25
53 FBD<76> B9 FBCD12 M15
53 FBD<15> G30 FBAD15 P25
53 FBD<77> C9 FBCD13 N15
53 FBD<16> K25 FBAD16 U25
53 FBD<78> B8 FBCD14 P15
53 FBD<17> J26 FBAD17 AC25 PP1V25_GPU_VTT 50
FBD<79> A7 FBCD15 R15
F
53
F 53 FBD<18> J25 FBAD18

53 FBD<80> F10 FBCD16 T15
53 FBD<19> G26 FBAD19 G9
G12 53 FBD<81> E9 FBCD17 U15
53 FBD<20> F28 FBAD20 G15 NV36 NV36 NV36 NV36 NV36 NV36 NV36 NV36 NV36 NV36 NV36 NV36
G16 FBD<82> F9 FBCD18 V15
53 FBD<21> F26 FBAD21 G19
G22
1 C5250 1 C5251 1 C5252 1 C5253 1 C5254 1 C5255 1 C5256 1 C5257 1 C5258 1 C5259 1 C5260 1 C5261 53
FBD<83> F7 FBCD19 W15

53 FBD<22> E27 FBAD22 NC_VTT J24 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 53
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% C6 M16
D27
M24
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 53 FBD<84> FBCD20
53 FBD<23> FBAD23 R24 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
E6 N16
H28
T24
402 402 402 402 402 402 402 402 402 402 402 402 53 FBD<85> FBCD21
53 FBD<24> FBAD24 W24
D5 P16
G29
AB24 53 FBD<86> FBCD22
53 FBD<25> FBAD25 C4 R16
F29 A25
53 FBD<87> FBCD23
53 FBD<26> FBAD26 AK25 C8 T16
E29 AA5 53 FBD<88> FBCD24
53 FBD<27> FBAD27 B7 U16
C30
AF20
AH16
53 FBD<89> FBCD25
53 FBD<28> FBAD28 AK15 B6 THERMAL GND V16
C29 53 FBD<90> FBCD26
53 FBD<29> FBAD29 AF11
B5 W16
B30
AH21
U26
53 FBD<91> FBCD27
53 FBD<30> FBAD30 AD28 A3 M17
A30 53 FBD<92> FBCD28
53 FBD<31> FBAD31 AH18
F25 B3 N17
AJ29 C18
53 FBD<93> FBCD29
53 FBD<32> FBAD32 E14 A2 P17
AJ30
53 FBD<94> FBCD30
53 FBD<33> FBAD33 AF8
Y8 B2 R17
AH29 K3
53 FBD<95> FBCD31
53 FBD<34> FBAD34 G3 B29 T17
AH30
53 FBD<96> FBCD32
53 FBD<35> FBAD35 F6
AF17 A29 U17
AF29 AF23 53 FBD<97> FBCD33
53 FBD<36> FBAD36 AH24 B28 V17
AE29
53 FBD<98> FBCD34
53 FBD<37> FBAD37 AH28
AG27 A28 W17
AD29 AF26 53 FBD<99> FBCD35
53 FBD<38> FBAD38 B26 M18
AC28
AF14
AH13
DIFFERENTIAL_PAIR NET_SPACING_TYPE 53 FBD<100> FBCD36
FBD<39> FBAD39
E
53
E L8 53 FBD<101> B25 FBCD37 N18

53 FBD<40> AG28 FBAD40 P26 54 53 52 FBACLK0 FBACLK0 FBCLK I373 B24 P18
AF27
G28
K28
53 FBD<102> FBCD38
53 FBD<41> FBAD41 N28
54 53 52 FBACLK0_L FBACLK0 FBCLK I372 C23 R18
AE26 V28
53 FBD<103> FBCD39
53 FBD<42> FBAD42 54 53 52 FBACLK1 FBACLK1 FBCLK I374 E26 T18
AE28
AA28
F30
53 FBD<104> FBCD40
53 FBD<43> FBAD43 J30
54 53 52 FBACLK1_L FBACLK1 FBCLK I375 D26 U18
AD25 M30 53 FBD<105> FBCD41
53 FBD<44> FBAD44 55 53 52 FBBCLK0 FBBCLK0 FBCLK I376 E25 V18
AB25
W30
AB30
53 FBD<106> FBCD42
53 FBD<45> FBAD45 AE30
55 53 52 FBBCLK0_L FBBCLK0 FBCLK I377 C25 W18
AB26 53 FBD<107> FBCD43
53 FBD<46> FBAD46 H26 55 53 52 FBBCLK1 FBBCLK1 FBCLK I378 E24 M19
AA25
L26
Y26
53 FBD<108> FBCD44
53 FBD<47> FBAD47 AC26
55 53 52 FBBCLK1_L FBBCLK1 FBCLK I379 F22 N19
AD30 GND E17 53 FBD<109> FBCD45
53 FBD<48> FBAD48 D28 E22 P19
AC29 C7
53 FBD<110> FBCD46
53 FBD<49> FBAD49 E8 F21 R19
AB28
53 FBD<111> FBCD47
53 FBD<50> FBAD50 A9
C10 A24 T19
AB29 E11
53 FBD<112> FBCD48
53 FBD<51> FBAD51 C13 B23 U19
Y29
53 FBD<113> FBCD49
53 FBD<52> FBAD52 E20
C21 C22 V19
W28 E23 53 FBD<114> FBCD50
53 FBD<53> FBAD53 C24 B22 W19
W29 53 FBD<115> FBCD51
53 FBD<54> FBAD54 A6
A12 B20 P12
V29 AH10
53 FBD<116> FBCD52
53 FBD<55> FBAD55 C19 N12
AC27
AK12
C3
53 FBD<117> FBCD53
53 FBD<56> FBAD56 D4 B19 V12
AB27 E5
53 FBD<118> FBCD54
53 FBD<57> FBAD57 B18 U12
AA27
AG4
AH3
53 FBD<119> FBCD55
53 FBD<58> FBAD58 AK6 D23 M12
AA26 AH7
53 FBD<120> FBCD56
53 FBD<59> FBAD59 D22 R12
W25
AF5 53 FBD<121> FBCD57
D
53
53
FBD<60>
FBD<61> V26
FBAD60
FBAD61
AE6
AK9
N3
H11
53
53
FBD<122>
FBD<123>
D21
E21
FBCD58
FBCD59
T12
W12
D
53 FBD<62> V27 FBAD62 AC11
H20 53 FBD<124> F19 FBCD60 M13
53 FBD<63> V25 FBAD63 AC20 PP2V5_GPU 7 50 52 54 55
L23 53 FBD<125> E18 FBCD61 R13
Y23
F1 53 FBD<126> D18 FBCD62 T13
J1
L27 FBADQM0 M1 1 NV34 F18 W13
54 FBDQM<0>
T1 R5202 53 FBD<127> FBCD63
54 FBDQM<1> K29 FBADQM1 W1 49.9
AB1 1%
54 FBDQM<2> G25 FBADQM2 AE1 1/16W
A19 MF 55 FBDQM<8> D11 FBCDQM0 FBCDQS0 D12 FBDQS<8> 53
54 FBDQM<3> E28 FBADQM3 AK19 402
A22 2 55 FBDQM<9> B10 FBCDQM1 FBCDQS1 A10 FBDQS<9> 53
54 FBDQM<4> AF28 FBADQM4 AK22
K5 55 FBDQM<10> D7 FBCDQM2 FBCDQS2 E7 FBDQS<10> 53
54 FBDQM<5> AD27 FBADQM5 J7
AE25 55 FBDQM<11> C5 FBCDQM3 FBCDQS3 A4 FBDQS<11> 53
54 FBDQM<6> AA30 FBADQM6 55 FBDQM<12> C26 FBCDQM4 FBCDQS4 A27 FBDQS<12> 53
54 FBDQM<7> Y27 FBADQM7
FBCAL_PD_VDDQ F5 FBCAL_PD_VDDQ 55 FBDQM<13> F24 FBCDQM5 FBCDQS5 D24 FBDQS<13> 53
55 FBDQM<14> B21 FBCDQM6 FBCDQS6 A21 FBDQS<14> 53

V30 FBCAL_PU_GND E4 FBCAL_PU_GND
D20 D19
54 FBA<0> FBAA0 55 FBDQM<15> FBCDQM7 FBCDQS7 FBDQS<15> 53
FBA<1> U28 FBAA1 FBCAL_TERM_GND D3 FBCAL_TERM_GND

54
1 NV34 55 FBBA<0> A18 FBCA0 NC_FBCDQS0* E12 NC
U29 R5203
54 FBA<2> FBAA2
T28 FBCAL_CLK_GND E3 FBCAL_CLK_GND 49.9 55 FBBA<1> C17 FBCA1 NC_FBCDQS1* C11 NC
54 FBA<3> FBAA3 1%
B17 D6
T29
1/16W 55 FBBA<2> FBCA2 NC_FBCDQS2* NC
54 FBA<4> FBAA4 FB_DLLVDD C27 FB_DLLVDD NOSTUFF NOSTUFF MF
C16 NC_FBCDQS3* B4
T27 2 402 55 FBBA<3> FBCA3 NC
54 FBA<5> FBAA5 1
R5207
1
R5208
T30 FBACKE N30 54 FBACKE 55 FBBA<4> B16 FBCA4 NC_FBCDQS4* B27 NC
54 FBA<6> FBAA6 549 0 D16 NC_FBCDQS5* D25
FBBA<5> FBCA5
C
1% 5% 55 NC
C 54 FBA<7> T26 FBAA7 FBACLK0 U21 FBACLK1 52 53 54 1 1/16W 1/16W

R5201 A16 NC_FBCDQS6* C20
T25
MF MF 55 FBBA<6> FBCA6 NC
54 FBA<8> FBAA8 FBACLK0* V21 FBACLK1_L 52 53 54 10K 2 402 2 402 E16 NC_FBCDQS7* E19
R27 1% 55 FBBA<7> FBCA7 NC
54 FBA<9> FBAA9 FBACLK1 N21 FBACLK0 52 53 54 1/16W
F16
R25 MF 55 FBBA<8> FBCA8
54 FBA<10> FBAA10 FBACLK1* P21 FBACLK0_L 52 53 54 2 402 D15 FBCRAS* C14 FBBRAS_L 55
R30
55 FBBA<9> FBCA9 FBCCAS* B14
54 FBA<11> FBAA11 M27 F15
FBBCAS_L 55
U24 FBADQS0 FBDQS<0> 53 55 FBBA<10> FBCA10 FBCWE* C15
54 FBA<12> FBAA12 K30 A15
FBBWE_L 55
FBADQS1 FBDQS<1> 53 55 FBBA<11> FBCA11 D17
R26 G27 G17 FBCCS0* FBBCS0_L 55
54 FBABA<0> FBABA0 FBADQS2 FBDQS<2> 53
WEAK PULL-DOWN
55 FBBA<12> FBCA12 FBCCS1* D14 TESTPOINT
TP_FBBCS1_L 6
FBABA<1> R29 FBABA1 D30 FBDQS<3>
54
FBADQS3 53
RECOMMANDED NY NVIDIA. 55 FBBBA<0> E15 FBCBA0 FBCCKE A13 55 FBBCKE
AG30 FBDQS<4>
FBADQS4 53
55 FBBBA<1> B15 FBCBA1
FBARAS_L P28 FBARAS* AD26 FBDQS<5>
54
FBADQS5 53
1
R5200
FBACAS_L P29 FBACAS* AA29 FBDQS<6> FBBCLK1 K18 FBBCLK0
54
FBADQS6 53 55 53 52
10K
FBAWE_L R28 FBAWE* W27 FBDQS<7> FBBCLK1_L K17 FBBCLK0*
54
FBADQS7 53 55 53 52 1%
1/16W
54 FBACS0_L U27 FBACS0* 55 53 52 FBBCLK0 K13 FBBCLK1 MF WEAK PULL-DOWN
M26
TP_FBACS1_L TESTPOINT P27 FBACS1* NC_FBADQS0* NC
55 53 52 FBBCLK0_L K14 FBBCLK1* 2 402
L28
NC_FBADQS1* NC
FBBCLK 0 AND 1 SWAPPED FOR ROUTING REASONS
RECOMMENDED BY NVIDIA
F27
GPU_FB_VREF C28 FBVREF NC_FBADQS2* NC
D29
NC_FBADQS3* NC
56 ROMA14 TESTPOINT R2 ROMA14 NC_FBADQS4*

AG29 NC
NV34
ROMA15 TESTPOINT R1 ROMA15 AE27 =PP3V3_AGP
56
NC_FBADQS5* NC
R5206 7 48 49 50 51 56 57 58 59
TP_ROMCS_L TESTPOINT AF2 ROMCS* NC_FBADQS6*

Y28 NC 52 52 FB_DLLVDD
1
10
2
VOLTAGE=2.5V
W26
B
NC_FBADQS7* NC
B ALTERNATE STUFFING FOR 10 OHM R

1/10W
NV34 NV34 NV34 FF
805 IS FILTER APN 155S0052 PER NVIDIA SPEC
1
C5205 1
C5206 1
C5207
4.7UF 0.1UF 0.001UF
N20P80% 20% 10%
10V 10V 50V
805 402 402
55 54 52 50 7 PP2V5_GPU
1
R5204 1 C5203
1K
1%
1/16W
0.1UF
20%
10V
NVIDIA FRAME BUFFER
2
VOLTAGE=1.25V
MF
2 402
CERM
MIN_LINE_WIDTH=25MIL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
R5205 1 C5204 AGREES TO THE FOLLOWING
1K 0.1UF
A
1%
1/16W
20% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
A
10V
MF 2 CERM II NOT TO REPRODUCE OR COPY IT
2 402 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

E 051-6482 ??
SCALE SHT OF
NONE 52 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE R’S CLOSE TO MEMORY
FBD<31> 15 1 8 RP5320 RFBD<31> FBD<32> 15 3 6 RP5328 RFBD<32>

52 54 52 54

52 54 52 54

52 54 52 54

52 54 52 54
15 1 8 RP5321 15 4 5 RP5316
52 FBD<27> RFBD<27> 54 52 FBD<36> RFBD<36> 54 PLACE R’S CLOSE TO GPU
52 54 52 54

52 54 52 54
D 52
52
FBD<24>
FBD<0>
15
15
4
1
5
8
RP5321
RP5322
RFBD<24>
RFBD<0>
54
54
52
52
FBD<39>
FBD<40>
15
15
1
2
8
7
RP5316
RP5329
RFBD<39>
RFBD<40>
54
54
54 52 FBACLK1
D
52 54 52 54
RP5322 RP5329 1
52 FBD<2> 15 3 6 RFBD<2> 54 52 FBD<42> 15 3 6 RFBD<42> 54
R5316
15 4 5 RP5322 15 4 5 RP5329 100
52 FBD<3> RFBD<3> 54 52 FBD<43> RFBD<43> 54 1% PLACE 100OHM TERM AT RAM
1/16W
52 54 52 54 MF
402
2
52 54 52 54

52 54 52 54
RP5323 RP5330 54 52 FBACLK1_L
52 FBD<19> 15 4 5 RFBD<19> 54 52 FBD<47> 15 3 6 RFBD<47> 54

52 54 52 54

52 54 52 54

52 54 52 54

52 54 52 54

52 54 52 54
FBD<11> 15 2 7 RP5325 RFBD<11> FBD<53> 15 3 6 RP5300 RFBD<53> FBACLK0

52 54 52 54 54 52

52 54 52 54

52 54 52 54
RP5326 RP5301 1
52 FBD<5> 15 1 8 RFBD<5> 54 52 FBD<56> 15 1 8 RFBD<56> 54
R5317
2 7 RP5326 2 7 RP5301 100
52 FBD<6> 15 RFBD<6> 54 52 FBD<57> 15 RFBD<57> 54 1% PLACE 100OHM TERM AT RAM
1/16W
52 54 52 54 MF

402
2
52 54 52 54

52 54 52 54
RP5327 RP5302 54 52 FBACLK0_L
52 FBD<21> 15 2 7 RFBD<21> 54 52 FBD<61> 15 3 6 RFBD<61> 54

52 54 52 54

52 54 52 54
C 52 FBD<64>
GPU128BIT
15 1 8 RP5310 RFBD<64> 55 52 FBD<96>
GPU128BIT
15 4 5 RP5315 RFBD<96> 55
55 52 FBBCLK1 C
FBD<65>
GPU128BIT
15 2 7 RP5310 RFBD<65> FBD<97>
GPU128BIT
15 3 6 RP5315 RFBD<97>
52 55 52 55
FBD<66>
GPU128BIT
15 3 6 RP5310 RFBD<66> FBD<98>
GPU128BIT
15 2 7 RP5315 RFBD<98>
GPU128BIT
1
52 55 52 55
R5318
FBD<67>
GPU128BIT
15 4 5 RP5310 RFBD<67> FBD<99>
GPU128BIT
15 1 8 RP5315 RFBD<99>
52 55 52 55 100
FBD<84>
GPU128BIT
15 1 8 RP5309 RFBD<84> FBD<100>
GPU128BIT
15 4 5 RP5314 RFBD<100>
1% PLACE 100OHM TERM AT RAM
52 55 52 55 1/16W
FBD<85>
GPU128BIT
15 2 7 RP5309 RFBD<85> FBD<101>
GPU128BIT
15 3 6 RP5314 RFBD<101>
MF
52 55 52 55 402
GPU128BIT RP5309 GPU128BIT RP5314 2
52 FBD<86> 15 3 6 RFBD<86> 55 52 FBD<102> 15 2 7 RFBD<102> 55
FBD<87>
GPU128BIT
15 4 5 RP5309 RFBD<87> FBD<103>
GPU128BIT
15 1 8 RP5314 RFBD<103> FBBCLK1_L
52 55 52 55 55 52
FBD<72>
GPU128BIT
15 4 5 RP5319 RFBD<72> FBD<104>
GPU128BIT
15 1 8 RP5312 RFBD<104>
52 55 52 55
FBD<73>
GPU128BIT
15 3 6 RP5319 RFBD<73> FBD<105>
GPU128BIT
15 2 7 RP5312 RFBD<105>
52 55 52 55
FBD<75>
GPU128BIT
15 2 7 RP5319 RFBD<75> FBD<106>
GPU128BIT
15 3 6 RP5312 RFBD<106>
52 55 52 55
FBD<74>
GPU128BIT
15 1 8 RP5319 RFBD<74> FBD<107>
GPU128BIT
15 4 5 RP5312 RFBD<107>
52 55 52 55
FBD<68>
GPU128BIT
15 1 8 RP5308 RFBD<68> FBD<108>
GPU128BIT
15 1 8 RP5313 RFBD<108>
52 55 52 55
FBD<70>
GPU128BIT
15 2 7 RP5308 RFBD<70> FBD<109>
GPU128BIT
15 2 7 RP5313 RFBD<109>
52 55 52 55
GPU128BIT RP5308 GPU128BIT RP5313 55 52 FBBCLK0
52 FBD<69> 15 3 6 RFBD<69> 55 52 FBD<110> 15 3 6 RFBD<110> 55
FBD<71>
GPU128BIT
15 4 5 RP5308 RFBD<71> FBD<111>
GPU128BIT
15 4 5 RP5313 RFBD<111>
52 55 52 55
FBD<80>
GPU128BIT
15 1 8 RP5307 RFBD<80> FBD<112>
GPU128BIT
15 4 5 RP5311 RFBD<112>
GPU128BIT
1
52 55 52 55
R5319
FBD<81>
GPU128BIT
15 2 7 RP5307 RFBD<81> FBD<113>
GPU128BIT
15 3 6 RP5311 RFBD<113> 100
52 55 52 55
FBD<82>
GPU128BIT
15 3 6 RP5307 RFBD<82> FBD<114>
GPU128BIT
15 2 7 RP5311 RFBD<114>
1% PLACE 100OHM TERM AT RAM
52 55 52 55 1/16W
FBD<83>
GPU128BIT
15 4 5 RP5307 RFBD<83> FBD<115>
GPU128BIT
15 1 8 RP5311 RFBD<115>
MF
52 55 52 55 402
GPU128BIT RP5317 GPU128BIT RP5306 2
52 FBD<76> 15 4 5 RFBD<76> 55 52 FBD<116> 15 4 5 RFBD<116> 55
FBD<77>
GPU128BIT
15 3 6 RP5317 RFBD<77> FBD<117>
GPU128BIT
15 3 6 RP5306 RFBD<117> FBBCLK0_L
52 55 52 55 55 52
FBD<78>
GPU128BIT
15 2 7 RP5317 RFBD<78> FBD<118>
GPU128BIT
15 2 7 RP5306 RFBD<118>
52 55 52 55
FBD<79>
GPU128BIT
15 1 8 RP5317 RFBD<79> FBD<119>
GPU128BIT
15 1 8 RP5306 RFBD<119>
52 55 52 55
FBD<91>
GPU128BIT
15 1 8 RP5318 RFBD<91> FBD<120>
GPU128BIT
15 1 8 RP5304 RFBD<120>
52 55 52 55
B 52
52
FBD<90>
FBD<89>
GPU128BIT
GPU128BIT
15
15
2
3
7
6
RP5318
RP5318
RFBD<90>
RFBD<89>
55
55
52
52
FBD<121>
FBD<122>
GPU128BIT
GPU128BIT
15
15
2
4
7
5
RP5304
RP5304
RFBD<121>
RFBD<122>
55
55
B
FBD<88>
GPU128BIT
15 4 5 RP5318 RFBD<88> FBD<123>
GPU128BIT
15 3 6 RP5304 RFBD<123>
52 55 52 55
FBD<95>
GPU128BIT
15 1 8 RP5303 RFBD<95> FBD<124>
GPU128BIT
15 1 8 RP5305 RFBD<124>
52 55 52 55
FBD<94>
GPU128BIT
15 2 7 RP5303 RFBD<94> FBD<125>
GPU128BIT
15 3 6 RP5305 RFBD<125>
52 55 52 55
FBD<93>
GPU128BIT
15 3 6 RP5303 RFBD<93> FBD<126>
GPU128BIT
15 2 7 RP5305 RFBD<126>
52 55 52 55
FBD<92>
GPU128BIT
15 4 5 RP5303 RFBD<92> FBD<127>
GPU128BIT
15 4 5 RP5305 RFBD<127>
52 55 52 55
PLACE THESE R CLOSE TO SGRAM PLACE THESE R CLOSE TO SGRAM

R5301 GPU128BIT
R5308
15 15
52 FBDQS<0> 1 2 RFBDQS<0> 54 52 FBDQS<8> 1 2 RFBDQS<8> 55
1% 1%
R5302 1/16W GPU128BIT
R5314 1/16W
15 MF 15 MF
52 FBDQS<1> 1 2 402 RFBDQS<1> 54 52 FBDQS<9> 1 2 402 RFBDQS<9> 55
1% 1%
1/16W 1/16W
MF R5300 GPU128BIT MF R5309
402 15 402 15
1% 1%
R5303 1/16W GPU128BIT
R5315 1/16W FROM Q27 PAGE 26
15 MF 15 MF
1% 1%
1/16W 1/16W
MF R5307 GPU128BIT MF R5310
15 15
FB TERMINATION
402 402
1% 1%
R5305 R5313
A 52 FBDQS<5> 1
15
2
1/16W
MF
402 RFBDQS<5> 54 52 FBDQS<13>
GPU128BIT
1
15
2
1/16W
MF
402 RFBDQS<13> 55
A
1% 1%
1/16W 1/16W
MF R5306 GPU128BIT MF R5311 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402 15 402 15 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
52 FBDQS<6> 1 2 RFBDQS<6> 54 52 FBDQS<14> 1 2 RFBDQS<14> 55 AGREES TO THE FOLLOWING
1% 1% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
R5304 1/16W GPU128BIT
R5312 1/16W
15 MF 15 MF II NOT TO REPRODUCE OR COPY IT
1% 1%
1/16W 1/16W
MF MF SIZE DRAWING NUMBER REV.
402 402
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 53 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
55 54 52 50 7 PP2V5_GPU 55 54 52 50 7 PP2V5_GPU
55 54 52 50 7 PP2V5_GPU
PLACE NEAR VDD PINS PLACE NEAR VDD PINS
NVIDIA RECOMMENDS WIDER RANGE OF CAP VALUES C5415 C5414 C5401 C5400
1 C5424 1 C5425 1 C5426 1 C5422 1 C5427 1 C5428 1 C5429 1 C5423 1 10UF 1 10UF 1 10UF 1 10UF
0.1UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.1UF 0.001UF 20% 20% 20% 20%
20% 20% 20% 10% 20% 20% 20% 10% 6.3V 6.3V 6.3V 6.3V
10V 10V 10V 50V 10V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402
805 805 805 805
D D
55 54 52 50 7 PP2V5_GPU
55 54 52 50 7 PP2V5_GPU
OMIT
OMIT
U5401
U5400 SDRAM_DDR_4MX32
SDRAM_DDR_4MX32 BGA
BGA D7 (2 OF 2)
E5
(2 OF 2)
D7 E5
D8 E7
D8 E7 OMIT
E4 E8 OMIT
E4 E8 U5400
SDRAM_DDR_4MX32 E11 E10 U5401
E11 E10 SDRAM_DDR_4MX32
FBA<0> N5 A0 BGA
L4 VDD K6
L4 VDD K6 54 52 (1 OF 2)
VSS 54 52 FBA<0> N5 A0
BGA
(1 OF 2)
VSS 54 52 FBA<1> N6 A1 DQ0 B7 RFBD<7> 53 L7 K7
L7 K7 54 52 FBA<1> N6 A1 DQ0 B7 RFBD<48> 53
54 52 FBA<2> M6 A2 DQ1 C6 RFBD<5> 53 L8 K8
L8 K8 54 52 FBA<2> M6 A2 DQ1 C6 RFBD<49> 53
54 52 FBA<3> N7 A3 DQ2 B6 RFBD<6> 53 L11 K9
L11 K9 54 52 FBA<3> N7 A3 DQ2 B6 RFBD<50> 53
L5 54 52 FBA<4> N8 A4 DQ3 B5 RFBD<4> 53
C3
L5
N8 B5
54 52 FBA<4> A4 DQ3 RFBD<51> 53
C3 54 52 FBA<5> M9 A5 DQ4 C2 RFBD<2> 53 L10
C5
L10
N9 D3
C5 54 52 FBA<5> M9 A5 DQ4 C2 RFBD<53> 53
54 52 FBA<6> A6 DQ5 RFBD<3> 53
C7 F6 54 52 FBA<6> N9 A6 DQ5 D3 RFBD<52> 53
C7 F6 54 52 FBA<7> N10 A7 DQ6 D2 RFBD<1> 53
C8 F7 N10 D2
54 52 FBA<7> A7 DQ6 RFBD<54> 53
C8 F7 54 52 FBA<8> N11 A8 DQ7 E2 RFBD<0> 53
C10 F8 M8 K13
C10 F8 54 52 FBA<8> N11 A8 DQ7 E2 RFBD<55> 53
54 52 FBA<9> A9 DQ8 RFBD<31> 53
C12 F9 54 52 FBA<9> M8 A9 DQ8 K13 RFBD<32> 53
C12 F9 54 52 FBA<10> L6 A10 DQ9 K12 RFBD<30> 53
E3 G6 L6 K12
54 52 FBA<10> A10 DQ9 RFBD<33> 53
E3 G6 54 52 FBA<11> M7 A11 DQ10 J13 RFBD<29> 53
E12 G7 J12
E12 G7 54 52 FBA<11> M7 A11 DQ10 J13 RFBD<35> 53
DQ11 RFBD<28> 53 VDDQ
VDDQ 53 RFBDQS<0> B2 DQS0 F4 G8 DQ11 J12 RFBD<34> 53
F4 G8 DQ12 G13 RFBD<27> 53 53 RFBDQS<6> B2 DQS0
53 RFBDQS<3> H13 DQS1 F11 VSS_THERM G9 DQ12 G13 RFBD<37> 53
F11 VSS_THERM G9 DQ13 G12 RFBD<26> 53 53 RFBDQS<4> H13 DQS1
53 RFBDQS<1> H2 DQS2 G4 H6 DQ13 G12 RFBD<36> 53
G4 H6
B13
DQ14 F13 RFBD<25> 53
G11 H7 53 RFBDQS<7> H2 DQS2 F13
53 RFBDQS<2> DQS3 DQ14 RFBD<38> 53
C G11
J4
H7
H8 52 FBDQM<0> B3 DM0
DQ15
DQ16
F12
F3
RFBD<24>
RFBD<15>
53
53
J4
J11
H8
H9
53
52
RFBDQS<5>
FBDQM<6>
B13
B3
DQS3
DM0
DQ15
DQ16
F12
F3
RFBD<39>
RFBD<57>
53
53
C
J11 H9 52 FBDQM<3> H12 DM1 DQ17 F2 RFBD<14> 53
K4 J6 H12 F2
52 FBDQM<4> DM1 DQ17 RFBD<56> 53
K4 J6 52 FBDQM<1> H3 DM2 DQ18 G3 RFBD<13> 53
K11 J7 B12 G2
52 FBDQM<2> DM3 DQ19 RFBD<12> 53
J8 52 FBDQM<5> B12 DM3 DQ19 G2 RFBD<59> 53
N13
J8
N4
DQ20 J3 RFBD<10> 53 54 SGRAVREF N13 VREF J9 J3
54 SGRAVREF VREF 54 52 FBABA<0> BA0 DQ20 RFBD<62> 53
J9 DQ21 J2 RFBD<11> 53 54 52 FBABA<0> N4 BA0
54 52 FBABA<1> M5 BA1 K2 B4 M5
DQ21 J2 RFBD<60> 53
DQ22 RFBD<8> 53 54 52 FBABA<1> BA1
B4 1 C5435 DQ22 K2 RFBD<61> 53
1 C5434 53 52 FBACLK0 M11 CK DQ23 K3 RFBD<9> 53
0.1UF
B11
0.1UF
B11 53 52 FBACLK1 M11 CK DQ23 K3 RFBD<63> 53
53 52 FBACLK0_L M12 CK DQ24 E13 RFBD<23> 53
20% D4
20% D4 2 10V
53 52 FBACLK1_L M12 CK DQ24 E13 RFBD<41> 53
2
10V
D5 54 52 FBACKE N12 CKE DQ25 D13 RFBD<22> 53
CERM D5
N12 D13
CERM 402
54 52 FBACKE CKE DQ25 RFBD<40> 53
402
54 52 FBACS0_L N2 CS DQ26 D12 RFBD<21> 53 D6
D6
M2 C13 D9 54 52 FBACS0_L N2 CS DQ26 D12 RFBD<42> 53
54 52 FBARAS_L RAS DQ27 RFBD<20> 53
D9 54 52 FBARAS_L M2 RAS DQ27 C13 RFBD<43> 53
D10 54 52 FBACAS_L L2 CAS DQ28 B10 RFBD<19> 53 D10
L2 B10
54 52 FBACAS_L CAS DQ28 RFBD<44> 53
54 52 FBAWE_L L3 WE DQ29 B9 RFBD<16> 53 D11
D11
C9 E6 54 52 FBAWE_L L3 WE DQ29 B9 RFBD<47> 53
DQ30 RFBD<18> 53
E6 C4 VSSQ DQ30 C9 RFBD<45> 53
VSSQ E9 C11
DQ31 B8 RFBD<17> 53 E9 C4
B8
F5 C11
DQ31 RFBD<46> 53
F5 H4 MCL M13
F10 H4 M13
F10 H11 MCL
RFU1 L9 FBA<12> 52 54 G5 H11
G5 L12
NC RFU1 L9 FBA<12> 52 54
RFU2 M10 TP_U5400_RFU2 NO_TEST G10 L12
NC
G10 L13
H5 L13
RFU2 M10 TP_U5401_RFU2 NO_TEST
H5 M3
H10 M3
H10 M4
J5 M4
J5 N3
J10 N3
J10
K5
K5
K10
B K10
B
55 54 52 50 7 PP2V5_GPU
55 54 52 50 7 PP2V5_GPU
1 C5418 1 C5408 1 C5409 1 C5419 1 C5410 1 C5411 1 C5420 1 C5412 1 C5413 1 C5421 1 C5433 1 C5402 1 C5403 1 C5430 1 C5404 1 C5405 1 C5431 1 C5406 1 C5407 1 C5432
0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF
10% 20% 20% 10% 20% 20% 10% 20% 20% 10% 10% 20% 20% 10% 20% 20% 10% 20% 20% 10%
50V 10V 10V 50V 10V 10V 50V 10V 10V 50V 50V 10V 10V 50V 10V 10V 50V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
EVENLY PLACE 0.1UF CAP & 0.01UF CAPS
DDR SDRAM A VREF
PP2V5_GPU
55 54 52 50 7
1
R5400
1K
1 C5416
0.1UF GPU DDR SDRAM A
A 1%
1/16W
MF
402
2
20%
10V
CERM
A
2 402
SGRAM0 & SGRAM1 MEMORY SUPPORT SGRAVREF 54
VOLTAGE=1.25V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 MIN_NECK_WIDTH=10MIL PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R5401 1 C5417 MIN_LINE_WIDTH=25MIL AGREES TO THE FOLLOWING
1K 0.1UF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
333S0251 2 SDRAM,4MX32,DDR,300MHZ U5400,U5401 CRITICAL SAMSUNG 1%
20%
1/16W 10V II NOT TO REPRODUCE OR COPY IT
MF 2 CERM
333S0252 2 SDRAM,4MX32,DDR,300MHZ U5400,U5401 CRITICAL HYNIX 2 402 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 54 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
55 54 52 50 7 PP2V5_GPU 55 54 52 50 7 PP2V5_GPU
55 54 52 50 7 PP2V5_GPU
PLACE NEAR VDD PINS PLACE NEAR VDD PINS
GPU128BIT GPU128BIT GPU128BIT GPU128BIT
GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT

C5515 C5514 C5501 C5500
1 C5518 1 C5519 1 C5520 1 C5521 1 C5522 1 C5523 1 C5524 1 C5525 1 10UF 1 10UF 1 10UF 1 10UF
0.1UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.1UF 0.001UF 20% 20% 20% 20%
20% 20% 20% 10% 20% 20% 20% 10% 6.3V 6.3V 6.3V 6.3V
10V 10V 10V 50V 10V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402
805 805 805 805
D 55 54 52 50 7 PP2V5_GPU
D
55 54 52 50 7 PP2V5_GPU
U5501
U5500 SDRAM_DDR_4MX32
SDRAM_DDR_4MX32 BGA
BGA D7 (2 OF 2)
E5
(2 OF 2)
D7 E5
D8 OMIT E7
D8 OMIT E7
E4 E8
E4 E8 U5500
SDRAM_DDR_4MX32 E11 E10 U5501
E11 E10 SDRAM_DDR_4MX32
FBBA<0> N5 A0 BGA
L4 VDD K6
L4 VDD K6 55 52 (1 OF 2)
VSS 55 52 FBBA<0> N5 A0
BGA
(1 OF 2)
VSS 55 52 FBBA<1> N6 A1 DQ0 B7 RFBD<71> 53
L7 K7
L7 K7 OMIT 55 52 FBBA<1> N6 A1 OMIT DQ0 B7 RFBD<113> 53
55 52 FBBA<2> M6 A2 DQ1 C6 RFBD<69> 53 L8 K8
L8 K8 55 52 FBBA<2> M6 A2 DQ1 C6 RFBD<114> 53
55 52 FBBA<3> N7 A3 DQ2 B6 RFBD<70> 53 L11 K9
L11 K9 55 52 FBBA<3> N7 A3 DQ2 B6 RFBD<112> 53
L5 55 52 FBBA<4> N8 A4 DQ3 B5 RFBD<68> 53
C3
L5
N8 B5
55 52 FBBA<4> A4 DQ3 RFBD<115> 53
C3 55 52 FBBA<5> M9 A5 DQ4 C2 RFBD<65> 53 L10
C5
L10
N9 D3
C5 55 52 FBBA<5> M9 A5 DQ4 C2 RFBD<117> 53
55 52 FBBA<6> A6 DQ5 RFBD<67> 53
C7 F6 55 52 FBBA<6> N9 A6 DQ5 D3 RFBD<116> 53
C7 F6 55 52 FBBA<7> N10 A7 DQ6 D2 RFBD<66> 53
C8 F7 N10 D2
55 52 FBBA<7> A7 DQ6 RFBD<118> 53
C8 F7 55 52 FBBA<8> N11 A8 DQ7 E2 RFBD<64> 53
C10 F8 M8 K13
C10 F8 55 52 FBBA<8> N11 A8 DQ7 E2 RFBD<119> 53
55 52 FBBA<9> A9 DQ8 RFBD<95> 53
C12 F9 55 52 FBBA<9> M8 A9 DQ8 K13 RFBD<97> 53
C12 F9 55 52 FBBA<10> L6 A10 DQ9 K12 RFBD<94> 53
E3 G6 L6 K12
55 52 FBBA<10> A10 DQ9 RFBD<96> 53
E3 G6 55 52 FBBA<11> M7 A11 DQ10 J13 RFBD<93> 53
E12 G7 J12
E12 G7 55 52 FBBA<11> M7 A11 DQ10 J13 RFBD<99> 53
DQ11 RFBD<92> 53 VDDQ
VDDQ 53 RFBDQS<8> B2 DQS0 F4 G8 DQ11 J12 RFBD<98> 53
F4 G8 DQ12 G13 RFBD<91> 53 53 RFBDQS<14> B2 DQS0
53 RFBDQS<11> H13 DQS1 F11 VSS_THERM G9 DQ12 G13 RFBD<100> 53
F11 VSS_THERM G9 DQ13 G12 RFBD<90> 53 53 RFBDQS<12> H13 DQS1
53 RFBDQS<9> H2 DQS2 G4 H6 DQ13 G12 RFBD<101> 53
G4 H6
B13
DQ14 F13 RFBD<89> 53
G11 H7 53 RFBDQS<15> H2 DQS2 F13
53 RFBDQS<10> DQS3 DQ14 RFBD<102> 53
C G11
J4
H7
H8 52 FBDQM<8> B3 DM0
DQ15
DQ16
F12
F3
RFBD<88>
RFBD<79>
53
53
J4
J11
H8
H9
53
52
RFBDQS<13>
FBDQM<14>
B13
B3
DQS3
DM0
DQ15
DQ16
F12
F3
RFBD<103>
RFBD<121>
53
53
C
J11 H9 52 FBDQM<11> H12 DM1 DQ17 F2 RFBD<78> 53
K4 J6 H12 F2
52 FBDQM<12> DM1 DQ17 RFBD<120> 53
K11 J7 B12 G2
K11 J7 52 FBDQM<15> H3 DM2 DQ18 G3 NO_TEST RFBD<122> 53
52 FBDQM<10> DM3 DQ19 RFBD<76> 53
J8 52 FBDQM<13> B12 DM3 DQ19 G2 RFBD<123> 53
N13
J8
N4
DQ20 J3 RFBD<74> 53 55 SGRBVREF N13 VREF J9 J3
55 SGRBVREF VREF 55 52 FBBBA<0> BA0 DQ20 RFBD<126> 53
J9 DQ21 J2 RFBD<75> 53 55 52 FBBBA<0> N4 BA0
55 52 FBBBA<1> M5 BA1 K2 B4 M5
DQ21 J2 RFBD<124> 53
DQ22 RFBD<72> 53 GPU128BIT 55 52 FBBBA<1> BA1
GPU128BIT B4 DQ22 K2 RFBD<125> 53
53 52 FBBCLK0 M11 CK DQ23 K3 RFBD<73> 53
1 C5535 B11
1 C5534 B11
0.1UF 53 52 FBBCLK1 M11 CK DQ23 K3 RFBD<127> 53
0.1UF 53 52 FBBCLK0_L M12 CK DQ24 E13 RFBD<87> 53 D4
D4 20%
53 52 FBBCLK1_L M12 CK DQ24 E13 RFBD<104> 53
20%
D5 55 52 FBBCKE N12 CKE DQ25 D13 RFBD<86> 53 2
10V D5
N12 D13
2
10V CERM
55 52 FBBCKE CKE DQ25 RFBD<105> 53
CERM
55 52 FBBCS0_L N2 CS DQ26 D12 RFBD<85> 53
402 D6
402 D6
M2 C13 D9 55 52 FBBCS0_L N2 CS DQ26 D12 RFBD<106> 53
55 52 FBBRAS_L RAS DQ27 RFBD<84> 53
D9 55 52 FBBRAS_L M2 RAS DQ27 C13 RFBD<107> 53
D10 55 52 FBBCAS_L L2 CAS DQ28 B10 RFBD<83> 53
D10
L2 B10
55 52 FBBCAS_L CAS DQ28 RFBD<108> 53
55 52 FBBWE_L L3 WE DQ29 B9 RFBD<81> 53 D11
D11
C9 E6 55 52 FBBWE_L L3 WE DQ29 B9 RFBD<110> 53
DQ30 RFBD<82> 53
E6 C4 VSSQ DQ30 C9 RFBD<109> 53
VSSQ E9 C11
DQ31 B8 RFBD<80> 53 E9 C4
B8
F5 C11
DQ31 RFBD<111> 53
F5 H4 MCL M13
F10 H4 M13
F10 H11 MCL
RFU1 L9 FBBA<12> 52 55 G5 H11
G5 L12
NC RFU1 L9 FBBA<12> 52 55
RFU2 M10 TP_U5500_RFU2 NO_TEST G10 L12
NC
G10 L13
H5 L13
RFU2 M10 TP_U5501_RFU2 NO_TEST
H5 M3
H10 M3
H10 M4
J5 M4
J5 N3
J10 N3
J10
K5
K5
K10
B K10
B
55 54 52 50 7 PP2V5_GPU
55 54 52 50 7 PP2V5_GPU
GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT GPU128BIT
1 C5526 1 C5508 1 C5509 1 C5527 1 C5510 1 C5511 1 C5528 1 C5512 1 C5513 1 C5529 1 C5530 1 C5502 1 C5503 1 C5531 1 C5504 1 C5505 1 C5532 1 C5506 1 C5507 1 C5533
0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF 0.1UF 0.1UF 0.001UF
10% 20% 20% 10% 20% 20% 10% 20% 20% 10% 10% 20% 20% 10% 20% 20% 10% 20% 20% 10%
50V 10V 10V 50V 10V 10V 50V 10V 10V 50V 50V 10V 10V 50V 10V 10V 50V 10V 10V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
DDR SDRAM B VREF EVENLY PLACE 0.1UF CAP & 0.01 UF CAPS
55 54 52 50 7 PP2V5_GPU
1GPU128BIT GPU128BIT
R5500 1 C5516
1K 0.1UF
1%
GPU DDR SDRAM B

20%
1/16W 10V
MF 2 CERM
2 402
A
402
GPU128BIT
1 GPU128BIT
SGRBVREF
VOLTAGE=1.25V
55

A
R5501 1 C5517 MIN_NECK_WIDTH=10MIL
1K 0.1UF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1%
20%
1/16W 10V AGREES TO THE FOLLOWING
MF 2
SGRAM0 & SGRAM1 MEMORY SUPPORT 2 402
CERM
402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
333S0251 2 SDRAM,4MX32,DDR,300MHZ U5500,U5501 CRITICAL GPU128BIT_SAMSUNG
333S0252 2 SDRAM,4MX32,DDR,300MHZ U5500,U5501 CRITICAL GPU128BIT_HYNIX
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
NONE 55 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(8) FRAME BUFFER MEMORY SPEED

=PP3V3_AGP
=PP3V3_AGP [5..0] = [NV11_HSYNC,NV11_VSYNC,GPU_STRAP<3>,GPU_STRAP<2>,DVOD3,DVOD2]
=PP3V3_AGP
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
2 NOSTUFF 2 OMIT
R5616 1 2 OMIT 2 2 OMIT 2 OMIT 2
R5638 R5625 R5626 R5624 R5623 R5644 R5643
10K
5% 10K 10K 10K 10K 10K 10K 10K
110111 = 270MHZ SAMSUNG (NV18B)
1/16W 1% 5% 5% 5% 5% 5% 5%
MF 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 116S1104 2 RES,10K-OHM,1/16W,5% R5625,R5623 270MHZ_SAM_18
D
1 402
2
MF
402
57 NV_HSYNC
1
MF
402
1
MF
402
1
MF
402
1
MF
402
MF
1 402
1
MF
402
116S1104 1 RES,10K-OHM,1/16W,5% R5644 270MHZ_SAM_18 D
57 VIPHCTL
57 VIPD7 57 NV_VSYNC 116S1103 1 RES,1K-OHM,1/16W,5% R5628 270MHZ_SAM_18
NOSTUFF 57 GPU_STRAP<3>
2 57 GPU_STRAP<2> 110011 = 270MHZ HYNIX (NV18B)
R5617 2
1K R5618 57 51 DVOD3
5% 1K 116S1104 2 RES,10K-OHM,1/16W,5% R5625,R5644 270MHZ_HYN_18
1/16W 5% 57 51 DVOD2
MF 1/16W
402 MF 116S1103 2 RES,1K-OHM,1/16W,5% R5628,R5627 270MHZ_HYN_18
1 402
1
2
2 OMIT 2 NOSTUFF 2 OMIT 2 OMIT OMIT 2 NOSTUFF 111101 = 270MHZ SAMSUNG (NV34)
R5630 R5629 R5628 R5627 R5647 R5648
1K 1K 1K 1K 1K 1K
5% 5% 5% 5% 5% 5% 116S1104 2 RES,10K-OHM,1/16W,5% R5625,R5624 270MHZ_SAM_34
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
(5) HOST MODE MF MF MF MF MF
1 402 MF
(6) AGP SIDEBAND 1 402
1 402
1 402
1 402
1 402 116S1104 1 RES,10K-OHM,1/16W,5% R5623 270MHZ_SAM_34
[0] = [VIPHCTL]
[0] = [VIPD7]
0 = PCI MODE 116S1103 1 RES,1K-OHM,1/16W,5% R5647 270MHZ_SAM_34
* 0 = ENABLE AGP SIDEBAND
* 1 = AGP MODE
1 = DISABLE AGP SIDEBAND
111100 = 270MHZ HYNIX (NV34)
116S1104 2 RES,10K-OHM,1/16W,5% R5624,R5623 270MHZ_HYN_34
116S1103 2 RES,1K-OHM,1/16W,5% R5630,R5647 270MHZ_HYN_34
C =PP3V3_AGP C
=PP3V3_AGP
=PP3V3_AGP
=PP3V3_AGP 7 48 49 50 51 52 56 57 58 59
2 NOSTUFF NOSTUFF
R5663 2 2 2 2
10K R5664 R5653 R5631 R5633
1% 10K 10K 10K 10K
1/16W 1% 5% 1% 5%
MF 1/16W 1/16W 1/16W 1/16W
1 402 MF MF MF MF
1402 1402 1 402 1 402
52 ROMA15
57 GPU_STRAP<1> 57 GPU_STRAP<0>
52 ROMA14 57 51 DVOD8
NOSTUFF
2 2
NOSTUFF NOSTUFF R5632 R5634
2 1K 1K
2 2 R5658 5% 5%
R5665 R5666 1K 1/16W 1/16W
1K 1K 5% MF MF
5% 5% 1/16W
1/16W 1/16W MF
1 402 1 402
MF MF 402
402 402
1
1 1
FAST WRITE SUPPORT (9) SUB-VENDOR (10) PCI ADDRESS BUS

0=ENABLE [0] = [GPU_STRAP<1>] [0] = [GPU_STRAP<0>]
(1) ROM TYPE (OVERRIDDEN IF STRAP1 = 0) 1=DISABLE * 0 = SYSTEM BIOS (VENDOR & SUBSYSTEM ID=0X0000) 0 = REVERSED
[1..0] = [ROMA15,ROMA14] 1 = ADAPTER CARD VGA BIOS (VENDOR & SUBSYSTEM ID=0X54-0X57) * 1 = NORMAL
00 = PARALLEL
01 = SERIAL AT25F
B *
10 = SERIAL SST45VF
11 = SERIAL FUTURE B
=PP3V3_AGP
=PP3V3_AGP
=PP3V3_AGP =PP3V3_AGP
NOSTUFF NOSTUFF
2 2
NOSTUFF NOSTUFF NOSTUFF TMDS_XMIT_SI NOSTUFF R5619 R5620
NOSTUFF 2 2 2 2 2 1 NOSTUFF 2 10K 10K
R5636 5% 5%
2 1 R5612 R5613 R5608 R5609 R5602 1 R5605 1/16W 1/16W
R5667 R5635 10K 10K 10K 10K 10K 10K R5637 10K MF MF
10K 10K 1% 5% 5% 5% 5% 1% 10K 5%
1 402 1402
5% 1% 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1% 1/16W
1/16W 1/16W MF MF MF MF MF MF 1/16W MF
MF MF 402 402 402 402 402 402 MF 402
1 1 1 1 1 2 1
1 402 2 402 2 402
59 57 6 ANALOG_HSYNC_L
57 VIPHAD1
57 51 DVOHSYNC 59 57 6 ANALOG_VSYNC_L
57 VIPHAD0
57 VIPD6 57 VIPD3
57 VIPD1
57 VIPD2 57 VIPD5 NOSTUFF NOSTUFF
57 VIPD0 2 2
57 VIPD4
R5622 R5621
NOSTUFF 2 2 TMDS_XMIT_GPU 1K 1K
2 2 2 2 NOSTUFF 5% 5%
R5600 R5615 NOSTUFF 1/16W 1/16W
R5601 1K 1K R5614 R5611 R5610 2 2 2 MF MF
1K 5% 5% 1K 1K 1K 2 R5603 R5607 R5606
5% 1/16W 1/16W 5% 5% 5% R5604 1K 1K 1K 1 402 1 402
1/16W MF MF 1/16W 1/16W 1/16W 1K 5% 5% 5%
MF 402 402 MF MF MF 5% 1/16W 1/16W 1/16W
1 1
1 402 1 402 1 402 1 402 1/16W
MF
MF MF MF
1 402 1 402 1 402
1 402
(7) TV MODE
[1..0] = [ANALOG_HSYNC*,ANALOG_VSYNC*] NVIDIA STRAPS
A (2) CRYSTAL FREQUENCY SELECT
[1..0] = [VIPD6,VIPD2]
(4) USER DEFINED STRAPS
[3..0] = [VIPHAD1,VIPHAD0,VIPD1,VIPD0]
(3) PCI DEVICE ID
00 = SECAM
01 = NTSC NOTICE OF PROPRIETARY PROPERTY
A
00 = 13.5MHZ [3..0] = [DVOHSYNC,VIPD3,VIPD5,VIPD4]
10 = PAL
01 = 14.38MHZ 0010 = 0X112 GEFORCE2 GO THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
11 = DISABLED PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
* 10 = 27MHZ THESE BITS ARE UNDEFINED BUT THEY 0011 = 0X113 QUADRO2 GO AGREES TO THE FOLLOWING
11 = {UNDEFINED} MUST BE KEPT LOW DURING RESET 0100 = 0X114 NV17M (THESE RESISTORS ARE ALL NOSTUFF) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0000 = 0X110 GEFORCE2GO MX (NV11B) II NOT TO REPRODUCE OR COPY IT
* 1001 = 0X111 NV18B,NV31,NV34 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 56 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U4900
NV18B
59 GRAPH_DDC_SCL AG6 I2CC_SCL VIPPCLK L4 VIPCLK
BGA
GRAPH_DDC_SDA AG7 I2CC_SDA
59 (2 OF 5) 1
R5735
OMIT 10K
MON_I2C_SCL AG5 I2CA_SCL VIPD0 J3 VIPD0
D
TESTPOINT
59 56 5%
L5702
D 59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP 1000-OHM-EMI
1 2
59 MON_I2C_SDA AF7 I2CA_SDA TESTPOINT
VIPD1
VIPD2
J2
K2
VIPD1
VIPD2
56
56
1/16W
MF
2 402
6 TP_VIPHCLK M5 VIPHCLK TESTPOINT
VIPD3 K1 VIPD3 56
SM
56 VIPHCTL M4 VIPHCTL TESTPOINT
VIPD4 L3 VIPD4 56 =PP3V3_AGP 7 48 49 50 51 52 56 57 58 59
1
C5710 1 C5704 1 C5705 VIPD5 L2 VIPD5 56
4.7UF 0.1UF 0.001UF 56 VIPHAD0 P3 VIPHAD0 TESTPOINT
VIPD6 N2 VIPD6 56
20% 20% 10%
2
6.3V
2 10V
2 50V
56 VIPHAD1 P2 VIPHAD1 TESTPOINT
VIPD7 N1 VIPD7 56
1C5706
CERM CERM CERM
805 402 402 0.1UF
VIPVDDQ0 L6 20%
10V
L7 2
VIPVDDQ1 CERM
402
NOSTUFF
R5709 VIPVDDQ2 M7
10 PP3V3_NV_PLL AK7 PLLVDD R5723
59 56 6 ANALOG_VSYNC_L 1 2 MIN_LINE_WIDTH=25MIL 49.9
MIN_NECK_WIDTH=10MIL VIPCAL_PD_VDDQ P6 VIPCAL_PD_VDDQ 1 2 1
C5716
MF 5% 402 VOLTAGE=3.3V
1/16W VIPCAL_PU_GND P7 VIPCAL_PU_GND 1 2 1% 0.1UF
1/16W 20%
10V NV34
R5710 10 NOSTUFF 1% MF 2
59 56 6 ANALOG_HSYNC_L 1 2 1/16W 402 CERM
R5724 MF 402
MF 1/16W 5% 402 49.9 402
L5700 R5727 =PP3V3_AGP 7 48 49 50 51 52 56 57 58 59
=PP3V3_AGP 1000-OHM-EMI 0
59 58 57 56 52 51 50 49 48 7
1 2
1 2 NOSTUFF NOSTUFF NOSTUFF
VSYNC_L AE3 DACB_VSYNC TESTPOINT
DACA_VSYNC AJ8 NV_VSYNC 56 5%
SM 1
C5712 1 C5720 1 C5721 1/16W
1
C5711 1C5702 1 C5701 HSYNC_L AF3 DACB_HSYNC TESTPOINT
DACA_HSYNC AH9 NV_HSYNC 56 MF
4.7UF 0.1UF 0.001UF 402
4.7UF 0.1UF 0.001UF 20% 20% 10%
20% 20% 10% 6.3V 10V 50V
AB4 AG9 MIN_LINE_WIDTH=25MIL 2 2 2
2
6.3V
CERM 2 10V
CERM 2 50V
CERM MIN_LINE_WIDTH=25MIL PP3V3_NV_DACB DACB_VDD DACA_VDD PP3V3_NV_DACA MIN_NECK_WIDTH=10MIL
CERM
805
CERM
402
CERM
402
ROUTE THE RGB LINES MIN_NECK_WIDTH=10MIL
AC4 AG10
805 402 402 (GND) DACB_IDUMP DACA_IDUMP (GND)
AS 37.5 OHM TRACES.
59 6 ANALOG_BLU AD1 DACB_BLUE DACA_BLUE AJ9 DACA_BLUE

59 6 ANALOG_GRN AD2 DACB_GREEN DACA_GREEN AJ10 DACA_GREEN
59 6 ANALOG_RED AE2 DACB_RED DACA_RED AK10 DACA_RED
C AD3
C
NOSTUFF 1 1 DAC2RSET DACB_RSET DACA_RSET AG8 DACRSET1
R5702 NOSTUFF R5704
C5707 1 NOSTUFF NOSTUFF NOSTUFF DAC2VREF AB5 DACB_VREF DACA_VREF AH8 DACVREF1
27PF 75 C5709 1 75 NOSTUFF NOSTUFF NOSTUFF
1% 1%
5% 27PF 1 1 1 1 1 1
50V
2
1/16W
MF
5%
1/16W
MF
R5730 R5729 R5728 NC_DACC_BLUE W7 NC
1 R5733 R5732 R5731
CERM
402
50V
2 402 75 75 75 DVOVREF AF4 DVOVREF 1
C5717 R5725 75 75 75
402 2 CERM 2 1% 1% 1%
1 C5703 NC_DACC_GREEN Y7 NC 121 1% 1% 1%
402
1/16W 1/16W 1/16W 51 DVODE AE4 DVODE TESTPOINT 0.1UF 1% 1/16W 1/16W 1/16W
NOSTUFF MF MF MF
0.01UF NC_DACC_RED AA6 NC
20%
1/16W MF MF MF
1 10% DVOCLKOUT AJ2 DVOCLKOUT TESTPOINT 10V
C5708 1 R5703 2
402
2
402
2
402
2 50V 51 2 CERM MF
402
2
402
2
402
2
402
75 X7R TP_DVOCLKOUT_L AK2 DVOCLKOUT* TESTPOINT 402 2

27PF 1%
603
NC_DACC_RSET AC5 NC
5%
1/16W DVOCLKIN AG1 DVOCLKIN
50V
CERM 2 MF
AD5
402 2 402 56 51 DVOHSYNC DVOHSYNC
PLACE CLOSE TO GPU 51 DVOVSYNC AD6 DVOVSYNC TESTPOINT
1
PLACE CLOSE TO VGA CONNECTOR
R5711
10K
5% 51 DVOD0 AG2 DVOD0 STRAPS
NV34 1/16W
AH1
1 1 NV18B MF 51 DVOD1 DVOD1
R5740 R5708 NV34 2 402
AG3
130 95.3
NV18B1 1 56 51 DVOD2 DVOD2
1% 1%
R5700 R5741 56 51 DVOD3 AJ1 DVOD3
1/16W 1/16W 121 124 AH2
MF MF 1% 1% 51 DVOD4 DVOD4
2 402 2 402 1/16W 1/16W
DVOD5 AK1 XTALSSIN AJ7 GPU_XTALSSIN
MF MF 51 DVOD5
402
2 2 402 DVOD6 AJ3
CVBS_D 51 50 49 48 7 =PP3V3_AGP
51 DVOD6
59 58 57 56 52 DVOD7 AK3 DVOD7 1
D 3 CRITICAL
51 R5726
56 51 DVOD8 AH4 DVOD8 10K
XTALIN AJ6 GPU_CLK27M_XIN 5%
Q5700 51 DVOD9 AK4 DVOD9 PROPAGATION_DELAY=L:S::16 MM 1/16W
56
58 CVBS_CNT 1 IRLML2502 48 7 =PP3V3_AGP NOSTUFF MF
G 52 51 50 49 1 DVOD10 AJ4 DVOD10
SOT23 59 58 57 R5721 51 402
2
S 2 1 49.9 DVOD11 AH5 DVOD11 XTALOUT AH6 GPU_CLK27M_XOUT
1 R5707 1%
51
PROPAGATION_DELAY=L:S::16 MM
R5720 10K
B 1K
5%
1/16W
5%
1/16W
MF
2
1/16W
MF
402
AE8
AD8
DVOVDD AJ5
B
MF 402
2 AD9 XTALOUTBUFF TP_GPU_XTALOUTBUFF
402
2
VOLTAGE=3.3V STRAP0 G1 GPU_STRAP<0> 56
MIN_LINE_WIDTH=25MIL DVOCAL_PD_VDDQ AB6 DVOCAL_PD_VDDQ
MIN_NECK_WIDTH=10MIL STRAP1 G2 GPU_STRAP<1> 56
DVOCAL_PU_GND AB7 DVOCAL_PU_GND
1
C5718 NC_STRAP2 F2 GPU_STRAP<2> 56
0.1UF 6 TP_BUF_RST B1 BUFRST* NC_STRAP3 F3 GPU_STRAP<3> 56
20% TESTPOINT
10V
2 CERM
402
NOSTUFF R5706
1 5.1M
R5722 1 2
49.9
1% 5%
1/16W 1/16W
MF MF
402 603
1 1 R5734 2
NOTE: KEEP STUB SHORT ->
C5713 1 R5701 10K
10K
0.01UF
20%
5%
1/16W
5%
1/16W
MF
Y5700
SM-3
16V
CERM 2 MF 402
402 1 3
402 2 2
27.000M
CRITICAL
1 C5719 1 C5700
27PF 27PF
5% 5%
50V 50V
2 CERM 2 CERM
402 402
DAC & CLOCKS

A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 57 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP
59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP
1 1
R5805 R5804
59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP 10K 10K
1% 1% 1
1/16W 1/16W R5818 1
MF MF 2K R5819
1 C5850 2 402
2 402 5% 2K
D
0.1UF
20%
10V
2 CERM U4900
2
1/16W
MF
402
5%
1/16W
MF
2 402
NOSTUFF
R5831
D
402 0 MF 5%
NV18B I2CB_SDA AF6 GRAPH_IIC_SDA2 1 2 SI_SDA 51
0 MF 5%
59 LAMP_STS [IN] 47 1 2 R5802 NV_GPIOD0 G5 GPIOD0 BGA I2CB_SCL AE7 GRAPH_IIC_SCL2 1/16W 402 1 2 R5832 SI_SCL 51
5
R5803 1 PCI_RESET_L 6 8 51 74
47
402
R5820 (5 OF 5) 1/16W 402 NOSTUFF
47 4 59 6 MON_DETECT [IN] 1 2 MON_DETECT_R F4 GPIOD1
59 LCD_PWM
[OUT]
1 2 LCD_PWM_U5850
U5850 2 402
G4 OMIT IFPATXC W2 58 GPU_TMDS_CKP
TMDS_XMIT_GPU
R5833 1
0 MF 5%
2 TMDS_XMIT_GPU TMDS_CKP 51 59
5%
1/16W
NV_GPIOD2 GPIOD2 IFPATXC* V1 58 GPU_TMDS_CKM 1/16W 402 R5834 1
0 MF 5%
2 TMDS_CKM 51 59
MF 1 MC74VHC1G08 3
402 R5806 SOT23-5 NV_GPIOD3 H5 GPIOD3 TMDS_XMIT_GPU
0 MF 5% 402
10K IFPATXD0 U4 58 GPU_TMDS_D0P R5835 1 2 TMDS_XMIT_GPU 1/16W TMDS_D0P 51 59
1% 47 1 R5809 R5836 0 MF 5%
1/16W 57 CVBS_CNT 2 NV_GPIOD4 H4 GPIOD4 IFPATXD0* T4 58 GPU_TMDS_D0M 1/16W 402 1 2 TMDS_D0M 51 59
MF
2 402
1
R5860 R5861 1
59 INV_CUR_HI
[OUT] 47 1
402
2 R5830 NV_GPIOD5 J4 GPIOD5 IFPATXD1 Y2 58 GPU_TMDS_D1P
TMDS_XMIT_GPU
R5837 1
0 MF 5%
2 TMDS_XMIT_GPU
402
1/16W TMDS_D1P 51 59
59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP 100K 100K 402 AA1 R5840 0 MF 5%
5% 5%
TMDS_EN
[IN] 47 1 2 R5808 NV_GPIOD6 J5 IFPATXD1* 58 GPU_TMDS_D1M 1/16W 402 1 2 TMDS_D1M 51 59
1/16W
MF
1/16W
MF
59 GPIOD6 TMDS_XMIT_GPU 0 MF 5% 402
1 C5851 2 402 2 402 402 10K 1
402
2 R5817 NV_GPIOD7 J6 GPIOD7
IFPATXD2 V3 58 GPU_TMDS_D2P R5838 1 2 TMDS_XMIT_GPU
0 MF
1/16W
5%
TMDS_D2P 51 59
0.1UF IFPATXD2* W3 58 GPU_TMDS_D2M 1/16W 402 R5839 1 2 TMDS_D2M 51 59
20%
2 10V
402 10K 1 2 R5816 NV_GPIOD8 K4 GPIOD8 1/16W 402
CERM U5
402 IFPATXD3 TP_TMDS_TXD3P 6
10K 1 R5815 WHAT IS THE FREQUENCY OF THE Q27 PIXEL CLOCK?
402 2 NV_GPIOD9 K6 GPIOD9 IFPATXD3* V4 TP_TMDS_TXD3M 6 BETH: 96.21MHZ
5 IFPBTXC AA2 TP_EXT_TMDS_CKP 6 58 IFP0AVCC

1 6 TP_GPU_THERMC H3 THERMD-
IFPBTXC* Y3 TP_EXT_TMDS_CKM 6
FPD_PWR_ON 4
59
[OUT]
U5851 2 6 TP_GPU_THERMA H2 THERMD+ W4 NOSTUFF
IFPBTXD4 TP_EXT_TMDS_D0P
MC74VHC1G08 3 TP_GPU_FPBCLKOUT M3 FPBCLKOUT IFPBTXD4* V5 TP_EXT_TMDS_D0M
6
Q5800
SOT23-5 59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP
6
TP0610 2
TP_GPU_FPBCLKOUT_L M2 SM
FPBCLKOUT* IFPBTXD5 AB3 TP_EXT_TMDS_D1P 6 59 FPD_PWR_SW_G 1
NV34
R5845 IFPBTXD5* AB2 TP_EXT_TMDS_D1M G S
402 10K 1 2 GPU_SWAP_A AF9 SWAPRDY_A
6
402 10K 1 R5846 NV34 GPU_SWAP_B AD4 IFPBTXD6 Y6 TP_EXT_TMDS_D2P

2 SWAPRDY_B 6 D
C TP_GPU_STEREO Y5 STEREO
IFPBTXD6* W6 TP_EXT_TMDS_D2M 6 3 C
402 10K 1 2 R5812 GPU_TESTMECLK G24 TESTMEMCLK IFPBTXD7 AC3 TP_TMDS_TXD7P 6 PP3V3_TMDSTERM
50 49 PPVCORE_GPU VOLTAGE=3.3V
IFPBTXD7* AC2 TP_TMDS_TXD7M 6 MIN_LINE_WIDTH=12MIL
AF10 MIN_NECK_WIDTH=8MIL
TP_FRWR_PME_L NC_FRWR_PME* P5
N6 IFPCTXC TP_DFPCLK 6 NOSTUFF
59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP NC_FRWR_VAUXC P4 R5847
M6 IFPCTXC* TP_DFPCLK_L 6
NC_FRWR_VAUXP 58 GPU_TMDS_CKP 1
49.9
2
TP_FRWRLNKON L5 NC_FRWRLNKON IFPCTXD0 R3 TP_DFPD0 6
1%
6 TP_FRWRLPS N5 NC_FRWRLPS IFPCTXD0* T2 TP_DFPD1 6 R5869 1 1/16W
MF 402
1
C5810 U2
100
0.1UF IFPCTXD1 TP_DFPD2 6 1%
T3 1/16W NOSTUFF
20%
10V IFPCTXD1* TP_DFPD3 6 MF R5848
2 CERM 402 2
49.9
402
IFPCTXD2 U3 TP_DFPD5 6 58 GPU_TMDS_CKM 1 2
IFPCTXD2* V2 TP_DFPD6 6 1%
1/16W
MF 402
59 58 57 56 52 51 50 49 48 7 =PP3V3_AGP MAKE TP AS SHORT AS POSSIBLE NOSTUFF
IFP0VREF AA4 IFPABVPROVE IFPCVPROBE AA3 TP_IFP1VREF 6
R5849
49.9
58 GPU_TMDS_D0P 1 2
L5800 IFP0RSET V6 IFPABRSET IFPCRSET R4 IFP1RSET
1%
1000-OHM-EMI
R5870 1 1/16W
MF 402
1 2
VOLTAGE=3.3V IFP0PLLVDD U10 IFPABPLLVDD IFPCPLLVDD P10 GPU_IFB1IOVDD 100
SM
V10 N10 1/16W NOSTUFF
IFPABPLLGND IFPCPLLGND MF R5850
402 2
49.9
58 GPU_TMDS_D0M 1 2
IFP0AVCC T5 IFPAIOVDD IFPCIOVDD R5 GPU_IFP1PLLVDD
1%
1/16W
T6 IFPAIOGND IFPCIOGND R6 MF 402
1 1 1 NOSTUFF
R5800 R5801 R5821
Y4 IFPBIOVDD 10K 10K 1K R5851
B W5 IFPBIOGND
1%
1/16W
MF
1%
1/16W
MF
5%
1/16W
MF
58 GPU_TMDS_D1P 1
49.9
2 B
402 402 402 1%
2 2 2
R5871 1 1/16W
MF 402
OMIT 100
NOSTUFF 1 1 C5803 1 C5802 1 C5804 1%
1 C5800 R5807 1 1 C5801 1 C5805 1/16W NOSTUFF
C5811 4.7UF 0.1UF 0.1UF MF R5852
0.1UF 1K 4.7UF 0.1UF 0.001UF 20% 20% 20%
402 2
1% 10% 6.3V 10V 10V
49.9
20%
10V 1/16W
20%
6.3V
20%
10V 2 50V 2 CERM CERM 2 CERM 58 GPU_TMDS_D1M 1 2
2 CERM MF 2 CERM 2 CERM
CERM
805 2 402 402
402 402 1%
402 2 805 402 1/16W
MF 402
NOSTUFF
R5853
49.9
58 GPU_TMDS_D2P 1 2
1%
R5872 1 1/16W
MF 402
100
1%
1/16W NOSTUFF
MF R5854
402 2
49.9
58 GPU_TMDS_D2M 1 2
1%
1/16W
MF
402
L5801
FERR-EMI-100-OHM DVI AND STRAPS
A IFP0AVCC
1 2
SM
VOLTAGE=3.3V
58

A
GPU TMDS SWING AGREES TO THE FOLLOWING
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION II NOT TO REPRODUCE OR COPY IT
TABLE_5_ITEM

114S1003 1 RES,1K OHM,1%,1/16W,0402 R5807 17_INCH_LCD
TABLE_5_ITEM

114S1503 1 RES,1.5K OHM,1%,1/16W,0402 R5807 20_INCH_LCD
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 58 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF
EXTERNAL VGA CONNECTOR D5900 =PP5V_AGP 7 49 50 59 INTERNAL TMDS CONNECTOR R5926 0
BAV99DW 58 51 TMDS_D2M 1 2
SOT-363 5% MF
2
SDF5900 1/16W 402
STDOFF-118OD-181H-TH L5902 SYM_VER-1
1 90-OHM 1 4
57 56 6 ANALOG_HSYNC_L 6
NOSTUFF 1
R5904 TD2M 6 59
SM
CRITICAL 301
1 C5907
1
(516S0241) 1%
1/16W
J5902 MF 2 3 TD2P 6 59
22PF D5900 402 NOSTUFF
5% 53307-3072 2
2 50V BAV99DW F-ST-SM R5927 0 5% MF
CERM
402
SOT-363
2
58 51 TMDS_D2P 1 2 1/16W 402
1
5
3 4
NOSTUFF
57 56 6 ANALOG_VSYNC_L 3
NOSTUFF 5 6 59 6 PPVCC_TMDS VOLTAGE=3.3V R5928 0
D 1 C5908
4
59 6 TD0M
7
9
8
10
VOLTAGE=3.3V PP3V3_DDC
6 59
58 51 TMDS_D1M
1
1 2
5% MF
1/16W 402
D
22PF GND_CHASSIS_VGA 7 59 MIN_LINE_WIDTH=25MIL R5903 L5908
5%
CRITICAL 59 6 TD0P 11 12
SYM_VER-1
90-OHM
301 4 1 SM
2 50V
CERM (514-0201) 13 14 TCKM 6 59 1% TD1M 6 59
402 1/16W
59 6 TD2M 15 16 TCKP 6 59 MF
59 6 TD2P 17 18 2 402
3 2 TD1P
FL1702 J5903 19 20 TD1M 6 59 NOSTUFF
6 59
LCFILTER DV01793 21 22 TD1P R5929 0 5% MF

SM-100MHZ F-ST-TH 6 59
58 51 TMDS_D1P 1 2 1/16W 402
15
59 6 TMDS_DDC_DAT 23 24 TMDS_DDC_CLK 6 59 NOSTUFF
57 6 ANALOG_RED 1 2
R5930
16 25 26 0
58 51 TMDS_D0M 1 2
3 4 L5903 27 28 5% MF
CHECK RGB RETURN PINS FERR-220-OHM 1/16W 402
1 29 30 1 C5916 1 C5900
2
1 2 10UF 0.01UF L5909 SYM_VER-1
3 PP5V_USB2 92 10% 1 90-OHM 1 4
4 (RED_RTN)
16V
10%
16V R5902 TD0M 6 59
FILT_ANALOG_RED 5
6
0805 2 CERM 2 CERM SM
(GRN_RTN)
1210 301
FILT_ANALOG_GRN 7
7 6 GND_CHASSIS_TMDS 402
1%
FL1701
8 6 DDC_VCC_5 VOLTAGE=5V 1/16W
FILT_ANALOG_BLU 9
MIN_LINE_WIDTH=25MIL MF 2 3 TD0P 6 59
LCFILTER 11
10 6 VGA_IIC_DAT MIN_NECK_WIDTH=10MIL SDF5901 2 402 NOSTUFF
0 5%
SM-100MHZ 12 (BLU_RTN) STDOFF-118OD-181H-TH R5931 MF
13
58 51 TMDS_D0P 1 2 1/16W 402
57 6 ANALOG_GRN 1 2 14 1 C5902 1 NOSTUFF
0.01UF R5932 0
3 4 1 C5905 1 C5904 10%
58 51 TMDS_CKM 1 2
17 16V 5% MF
0.01UF 0.01UF 1 C5903 2 CERM 1/16W 402
18 10% 10% 402 L5910
2 16V
2 16V 0.01UF 90-OHM
SYM_VER-1
CERM CERM 10% 1
402 402
2 16V R5901 SM 1 4 TCKM 6 59
CERM R5906 301
402
33 1%
GND_CHASSIS_VGA GRAPH_DDC_SDA 1 2 TMDS_DDC_DAT 1/16W
FL1700 7 59 57 6 59
MF
LCFILTER 5% 402 2 3 TCKP 6 59
2 1/16W 2 NOSTUFF
SM-100MHZ
6 VGA_IIC_CLK GND_CHASSIS_VGA 7 59 R5907 MF
R5933 0
2K 402 5% MF
C 57 6 ANALOG_BLU 1
3 4
2
D5902
BAV99DW
SOT-363 =PP5V_AGP =PP3V3_AGP
5%
1/16W
MF
L5901
FERR-220-OHM PP3V3_DDC
58 51 TMDS_CKP 1 2 1/16W 402
C
7 49 50 59 58 57 56 52 51 50 49 48 7
1 402 6 59
=PP5V_AGP 7 49 50 59
2 1 2
0805
6
NOSTUFF 1
58 6 MON_DETECT R5905 1 C5901
1 1 2K 0.01UF
R5911 R5910 1
5%
10%
16V
2K 2K 1/16W 2 CERM
ROUTE THE ANALOG RGB TRACES AT 37.5 OHMS. 5% 5% MF
1/16W 1/16W 402
R5900 402
MF MF D5902 2 33
402 402 57 GRAPH_DDC_SCL 1 2 TMDS_DDC_CLK 6 59
2 2 R5908
33 BAV99DW 5%
57 MON_I2C_SDA 1 2 SOT-363 1/16W
MF
5% 5 402
1/16W
MF
402 3
NOSTUFF
INVERTER INTERFACE
R5909 20" LCD INVERTER NEED +24V.
17_INCH_LCD 17" LCD INVERTER NEED +12V.
33 4
MON_I2C_SCL 1 2
57
GND_CHASSIS_VGA 7 59 Q5903 17_INCH_LCD
CRITICAL
5%
1/16W
MF
C5909 1 1 C5906 SI3433DV
TSOP L5904 17_INCH_LCD
J5900
402 47PF 47PF 1
FERR-220-OHM
42375
5% 5% M-ST-TH
50V
2 2 50V 2 59 50 7 =PP12V_AGP
CERM CERM 1 2
VOLTAGE=12V 6 PP12V_INV 1
402 402 5 0805 MIN_LINE_WIDTH=100MIL
59 50 49 7 =PP5V_AGP MIN_NECK_WIDTH=10MIL VOLTAGE=0V 6 GND_17_INV 2
PP3V3_RUN PP12V_RUN
Q5903_GATE 3 6 L5905 17_INCH_LCD MIN_LINE_WIDTH=100MIL
6 PP5V_AGP_RL 3
FERR-220-OHM VOLTAGE=5V MIN_NECK_WIDTH=10MIL
90 11 7 PP3V3_ALL 4 MIN_NECK_WIDTH=10MIL 6 INV_17_LCD_PWM_F 4
1 2
17_INCH_LCD 5
17_INCH_LCD NOSTUFF 20_INCH_LCD
PPVCC_FPD R5920 0805
6 LAMP_STS_F
1
R5950
1
R5923
1
R5922 100K 2 6 INV_17_CUR_HI_F 6
1 L5906 17_INCH_LCD
0 0 0 17_INCH_LCD FERR-220-OHM
5% 5% 5% 5 6 7 8 5% 518-0135
1/8W
FF
1/8W
FF
1/8W
FF
1/16W
MF
1
R5921 PP5V_AGP_P_SEQ 1 2
402 10K 0805
B 2 1206
2 1206
2 1206
D 17_INCH_LCD
Q5900
PP3V3_RUN PP12V_RUN
59 50 7 =PP12V_AGP
5%
1/16W
MF
L5907
FERR-220-OHM
17_INCH_LCD B
IRF7410 17_INCH_LCD 2 402
58 FPD_PWR_SW_G 4
SO-8
1
R5919 3 NOSTUFF Q5902_DRAIN 59 58 LCD_PWM 1
0805
2
G
S NOSTUFF 1
NOSTUFF
200K D5901 3
L5911
376S0082 1 R5935 5% 1N914 D
17_INCH_LCD 17_INCH_LCD
R5934 0
20_INCH_LCD 1/16W
MF 1
SOT23 Q5902 FERR-220-OHM
1 2 3 0 L5900 2N7002
5%
2 402 SM LAMP_STS 1 2
FPD_PWR_SW_S
5%
1/8W
1/8W
FF
FERR-220-OHM Q5902_GATE 1 G S
58
0805
VOLTAGE=3.3V FF 1206
1 2 17_INCH_LCD 17_INCH_LCD
C5918 2 1206
2 PPVCC_TMDS 6 59 17_INCH_LCD L5912
C5919 0.022UF 0805
1
R5916 1 C5920 2 FERR-220-OHM
0.01UF VOLTAGE=3.3V 100K 0.1UF
2 1 2 1
MIN_LINE_WIDTH=25MIL 5% 20% 59 58 INV_CUR_HI 1 2
MIN_NECK_WIDTH=10MIL 1/16W 10V
0805
MF 2 CERM 17_INCH_LCD 17_INCH_LCD 17_INCH_LCD 17_INCH_LCD 17_INCH_LCD 17_INCH_LCD
OMIT 2 402 402 17_INCH_LCD 17_INCH_LCD
C5917 R5960
20% 1 20% 1 OMIT 1
C5910 1
C5913 1
C5911 1
C5912 1
C5914 1
C5915
16V R5913 16V 1 1 1 1
R5925 D5914 10K C5921 C5922 0.01UF 0.01UF 0.01UF 220PF 0.01UF 0.01UF
100K
CERM
402
10K
5%
CERM
402
1N914
10UF 5%
1
R5912 10UF 10UF 20% 20% 20% 5% 20% 20%
1 2 1/16W
SOT23
10%
16V 1/16W 330 20% 20% 2
50V
CERM 2
50V
CERM 2
50V
CERM 2
25V
CERM 2
50V
CERM 2
50V
CERM
MF 2 CERM MF 5% 2 16V 2 16V
603 603 603 603 603 603
5% 3 ELEC ELEC
1/16W 2 402 1210 2 402 1/16W
MF SM SM
MF FPD_PWR_ON_D 2 603
402
3
TMDS_EN_R LED5900_P1 GND_CHASSIS_17_INCH_INVERTER
7
1
20_INCH_LCD
D Q5901 CRITICAL
1
LED5900
2N7002 R5914
10K GREEN
L5913
J5901
58 FPD_PWR_ON 1 G S
SM
5%
2.0X1.25A
FERR-220-OHM
20_INCH_LCD
53048
1/16W 2 7 =PP24V_GRAPHICS RT-S-TH
MF
1 2 402 SILKSCREEN: 3 1 2 VOLTAGE=24V 6 PP24V_INV 1
R5915 2 0805
100K 58 TMDS_EN MIN_NECK_WIDTH=10MIL 2
L5914
5%
1/16W
MF
3
20_INCH_LCD
DZ5900 FERR-220-OHM
20_INCH_LCD
VOLTAGE=0V
6 GND_20_INV 3
4
EXT VGA / TMDS
1N5227B
402
2 1 2 MIN_NECK_WIDTH=10MIL
AND INVERTER
A INV_20_LCD_PWM_ 5
A
SOT23 0805 6
1
L5915 20_INCH_LCD 6 INV_20_CUR_HI_F 6
FERR-220-OHM NOTICE OF PROPRIETARY PROPERTY
1 2 518-0141
TABLE_5_HEAD
59 58 LCD_PWM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 0805 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NOTE:REMOVED 2 PINS:LAMP_STATUS & AGREES TO THE FOLLOWING
TABLE_5_ITEM
L5916 20_INCH_LCD ON/OFF FOR 20" LCD INVETER.

116S1104 1 RES,10K OHM,1/16W,5%,0402 R5913 17_INCH_LCD FERR-220-OHM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TABLE_5_ITEM

116S1105 1 RES,100K OHM,1/16W,5%,0402 R5913 20_INCH_LCD 59 58 INV_CUR_HI
NOSTUFF 20_INCH_LCD 20_INCH_LCD 20_INCH_LCD 20_INCH_LCD 20_INCH_LCD
TABLE_5_ITEM
113S1332 1 RES,330 OHM,1/16W,5%,0603 R5912 17_INCH_LCD

C5947 1 1 C5942 1 C5943 1 C5944 1 C5945 1 C5946 SIZE DRAWING NUMBER REV.
1UF 1UF
TABLE_5_ITEM
0.01UF 0.01UF 220PF 0.01UF

113S1123 1 RES,1.2K OHM,1/16W,5%,0603 R5912 20_INCH_LCD
TABLE_5_ITEM
20%
50V
CERM 2
20%
50V
2 CERM 2
20%
50V
CERM 2
20%
50V
CERM 2
5%
25V
CERM 2
20%
50V
CERM APPLE COMPUTER INC.
D 051-6482 I
376S0225 1 XSTR,MOSFET,P-CH,0.02OHM Q5900 20_INCH_LCD 1210 1210 603 603 603 603
TABLE_5_ITEM
SCALE SHT OF
101S1000 1 RES,0 OHM,1/10W,5%,0805 L5900 17_INCH_LCD GND_CHASSIS_20_INCH_INVERTER NONE 59 103
7
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
48 37 28 7 =PP1V5_PWRON_NB_AVDD R6000 64 62 60 HT_NB_TO_SB_CLK_P HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CLK I46

2.2 =PP2V5_HT 64 62 60 HT_NB_TO_SB_CLK_N HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CLK I47
1 2 PP1V5_PWRON_HT_NB_AVDD 7 60 64
VOLTAGE=1.5V MIN_LINE_WIDTH=25MIL 64 62 60 HT_NB_TO_SB_CTL_P HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CTL I83
1/16W HT_NB_TO_SB_CTL_N HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CTL
MF
603
1 C6013 1 C6012 =PP1V2_HT 7 24 60
64 62 60
HT_NB_TO_SB_CAD_P<0> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD0

I82
1UF 0.1UF 64 62 60 I51

10% 20% 64 62 60 HT_NB_TO_SB_CAD_N<0> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD0
2 6.3V 2 10V
I50
CERM CERM HT_NB_TO_SB_CAD_P<1>
J10
N10
402 402 64 62 60 HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD1 I52
F8
G6
T4
T8
R9
N2
N6
L9
D HT_CLK
AVDD
VDD_HT
2_5
VDD_HT
1_2
64 62 60
64 62 60
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD2
I53
I54
D
HT_NB_TO_SB_CAD_N<2> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD2
HT_CLK66M_NB H9 HT_CLK
U3 64 62 60
HT_NB_TO_SB_CAD_P<3>
I55
27 U3LITE 64 62 60 HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD3 I56
V1.0-300MM 64 62 60 HT_NB_TO_SB_CAD_N<3> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD3 I57
N1 HT_CLK_RXP0 PBGA
64 62 60 HT_SB_TO_NB_CLK_P (SYM 5 OF 7) HT_CLK_TXP0 R7 HT_NB_TO_SB_CLK_P 60 62 64 64 62 60 HT_NB_TO_SB_CAD_P<4> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD4 I58
HT_SB_TO_NB_CLK_N P1 HT_CLK_RXN0 HT_CLK_TXN0 R8 HT_NB_TO_SB_CLK_N HT_NB_TO_SB_CAD_N<4> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD4
64 62 60 HT 60 62 64 64 62 60 I59
INTERFACE 64 62 60 HT_NB_TO_SB_CAD_P<5> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD5 I60
64 62 60 HT_SB_TO_NB_CAD_P<0> L1 HT_CAD_RXP0 HT_CAD_TXP0 U8 HT_NB_TO_SB_CAD_P<0> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_N<5> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD5 I61
L2 HT_CAD_RXN0 OMIT
64 62 60 HT_SB_TO_NB_CAD_N<0> HT_CAD_TXN0 U7 HT_NB_TO_SB_CAD_N<0> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_P<6> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD6 I62
64 62 60 HT_SB_TO_NB_CAD_P<1> L3 HT_CAD_RXP1 HT_CAD_TXP1 U6 HT_NB_TO_SB_CAD_P<1> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_N<6> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD6 I63
64 62 60 HT_SB_TO_NB_CAD_N<1> L4 HT_CAD_RXN1 HT_CAD_TXN1 U5 HT_NB_TO_SB_CAD_N<1> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_P<7> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD7 I64
64 62 60 HT_SB_TO_NB_CAD_P<2> M4 HT_CAD_RXP2 HT_CAD_TXP2 U4 HT_NB_TO_SB_CAD_P<2> 60 62 64 64 62 60 HT_NB_TO_SB_CAD_N<7> HT_NB_TO_SB HT_NB_TO_SB HT_NB_TO_SB_CAD7 I65
64 62 60 HT_SB_TO_NB_CAD_N<2> M3 HT_CAD_RXN2 HT_CAD_TXN2 U3 HT_NB_TO_SB_CAD_N<2> 60 62 64
64 62 60 HT_SB_TO_NB_CAD_P<3> M2 HT_CAD_RXP3 HT_CAD_TXP3 R5 HT_NB_TO_SB_CAD_P<3> 60 62 64 64 62 60 HT_SB_TO_NB_CLK_P HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CLK I48

64 62 60 HT_SB_TO_NB_CAD_N<3> M1 HT_CAD_RXN3 HT_CAD_TXN3 R6 HT_NB_TO_SB_CAD_N<3> 60 62 64 64 62 60 HT_SB_TO_NB_CLK_N HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CLK I49
64 62 60 HT_SB_TO_NB_CAD_P<4> P2 HT_CAD_RXP4 HT_CAD_TXP4 P8 HT_NB_TO_SB_CAD_P<4> 60 62 64 64 62 60 HT_SB_TO_NB_CTL_P HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CTL I84
64 62 60 HT_SB_TO_NB_CAD_N<4> P3 HT_CAD_RXN4 HT_CAD_TXN4 P7 HT_NB_TO_SB_CAD_N<4> 60 62 64 64 62 60 HT_SB_TO_NB_CTL_N HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CTL I85
64 62 60 HT_SB_TO_NB_CAD_P<5> R3 HT_CAD_RXP5 HT_CAD_TXP5 P6 HT_NB_TO_SB_CAD_P<5> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<0> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD0 I66
64 62 60 HT_SB_TO_NB_CAD_N<5> R2 HT_CAD_RXN5 HT_CAD_TXN5 P5 HT_NB_TO_SB_CAD_N<5> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<0> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD0
64 60 7 =PP2V5_HT R1 HT_CAD_RXP6
I67
64 62 60 HT_SB_TO_NB_CAD_P<6> HT_CAD_TXP6 M5 HT_NB_TO_SB_CAD_P<6> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<1> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD1 I68
64 62 60 HT_SB_TO_NB_CAD_N<6> T1 HT_CAD_RXN6 HT_CAD_TXN6 M6 HT_NB_TO_SB_CAD_N<6> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<1> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD1 I69
64 62 60 HT_SB_TO_NB_CAD_P<7> U1 HT_CAD_RXP7 HT_CAD_TXP7 M7 HT_NB_TO_SB_CAD_P<7> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<2> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD2
1
R6005 R6004 R6003 R6002
1 1 1
64 62 60 HT_SB_TO_NB_CAD_N<7> U2 HT_CAD_RXN7 HT_CAD_TXN7 M8 HT_NB_TO_SB_CAD_N<7> 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<2> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD2
I70
1K 1K 1K 1K I71
5% 5% 5% 5% 64 62 60 HT_SB_TO_NB_CAD_P<3> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD3 I72
1/16W 1/16W 1/16W 1/16W V2 HT_CTL_RXP0
MF MF MF MF 64 62 60 HT_SB_TO_NB_CTL_P HT_CTL_TXP0 L6 HT_NB_TO_SB_CTL_P 60 62 64 64 62 60 HT_SB_TO_NB_CAD_N<3> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD3 I73
2 402 2 402 2 402 2 402 64 62 60 HT_SB_TO_NB_CTL_N V1 HT_CTL_RXN0 HT_CTL_TXN0 L5 HT_NB_TO_SB_CTL_N 60 62 64 64 62 60 HT_SB_TO_NB_CAD_P<4> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD4
C
I74
C 64 62 60 HT_PWROK F9 HT_PWROK
64 62 60
64 62 60
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD5
I75
I76
64 62 60 HT_RESET_L G9 HT_RESET* 64 62 60 HT_SB_TO_NB_CAD_N<5> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD5 I77
64 62 60 HT_LDTSTOP_L H8 HT_LDTSTOP* HT_PVTREF0 L7 HT_NB_PVTREF0 64 62 60 HT_SB_TO_NB_CAD_P<6> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD6 I78
64 62 60 HT_LDTREQ_L H7 HT_LDTREQ* HT_PVTREF1 L8 HT_NB_PVTREF1 64 62 60 HT_SB_TO_NB_CAD_N<6> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD6 I79
HT_CLK_AVSS
1
R6001 64 62 60 HT_SB_TO_NB_CAD_P<7> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD7 I80
200 64 62 60 HT_SB_TO_NB_CAD_N<7> HT_SB_TO_NB HT_SB_TO_NB HT_SB_TO_NB_CAD7
G8
I81
1%
1/16W
MF
HT_PWROK HT_PWROK HT_2V5
2 402 64 62 60 I86
64 62 60 HT_RESET_L HT_CTL HT_2V5 I87
64 62 60 HT_LDTSTOP_L HT_CTL HT_2V5 I88
64 62 60 HT_LDTREQ_L HT_CTL HT_2V5 I89
HT_NB_TO_SB HT_SB_TO_NB HT_2V5

5 MIL SPACING FOR DIFF PAIR 4 MIL SPACING IN GROUP
10 MIL SPACING TO ANYTHING ELSE 8 MIL SPACING TO ANYTHING ELSE
64 60 7 =PP2V5_HT 60 24 7 =PP1V2_HT
1 C6010 1 C6011 1 C6000 1 C6001 1 C6002 1 C6004 1 C6005 1 C6006 1 C6007 1 C6008 LENGTH TOLERENCE CAN BE LOOSE
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF MATCHED GROUP CONSTRAINT IS TIGHT ENOUGH
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
B 10V
2 CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
10V
2 CERM
402
2 10V
CERM
402 B
MASTER: GILA
U3LITE HT
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 60 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
15 MIL SPACING HT_CLK66M_SB_C 62
Page Notes
- _PP2V5_PWRON_HT
- _PP1V2_PWRON_HT
D (NONE) D
BOM options provided by this page: =PP2V5_PWRON_HT 7
- SB_HT_200M
Stuffs resistor to select 200MHz HT I/F.
1 C6220
PP1V2_PWRON_HT_PLLDVDD 0.1uF
20%
62 7 =PP1V2_PWRON_HT R6200 VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil 10V
2 CERM
1
3.3 2
MIN_NECK_WIDTH=15 mil 402
5%
1/10W
FF
805
1 C6200 1 C6201
10uF 1uF =PP1V2_PWRON_HT 7 62
20% 10%
6.3V 6.3V
2 CERM 2 CERM
1206 402
1 C6230 1 C6231 1 C6232
0.1uF 0.1uF 0.1uF
20% 20% 20%
2 10V
CERM
10V
2 CERM 2 10V
CERM
PP1V2_PWRON_HT_PLLAVDD 402 402 402
R6210 VOLTAGE=1.2V
1
3.3 2
MIN_NECK_WIDTH=15 mil
5%
1/10W
FF
805
1 C6210 1 C6211 =PP1V2_PWRON_HT 7 62
10uF 1uF
20% 10%
6.3V 6.3V
2 CERM 2 CERM
B19
B15
B17
G13
B12
G11
1206 402 1 C6240 1 C6241 1 C6242
C7
B6
B9
0.1uF 0.1uF 0.1uF
AVDD DVDD VDDP HT_RXVDD HT_TXVDD 20% 20% 20%
10V 10V 10V
HT_PLL HT OMIT 2 CERM 2 CERM 2 CERM
C U2300
SHASTA
402 402 402
C
V1.0
BGA
HT_NB_TO_SB_CLK_P D15 HT_CLKIN_P B10 HT_SB_TO_NB_CLK_P
64 60 (3 OF 8) HT_CLKOUT_P 60 64
HT_NB_TO_SB_CLK_N C15 HT_CLKIN_N HT_CLKOUT_N A10 HT_SB_TO_NB_CLK_N
HYPERTRANSPORT
64 60 60 64
64 60 HT_NB_TO_SB_CAD_P<0> D17 HT_CADIN_0_P HT_CADOUT_0_P D10 HT_SB_TO_NB_CAD_P<0> 60 64
64 60 HT_NB_TO_SB_CAD_N<0> C17 HT_CADIN_0_N HT_CADOUT_0_N C10 HT_SB_TO_NB_CAD_N<0> 60 64
64 60 HT_NB_TO_SB_CAD_P<1> B18 HT_CADIN_1_P HT_CADOUT_1_P B8 HT_SB_TO_NB_CAD_P<1> 60 64
64 60 HT_NB_TO_SB_CAD_N<1> A18 HT_CADIN_1_N HT_CADOUT_1_N A8 HT_SB_TO_NB_CAD_N<1> 60 64
64 60 HT_NB_TO_SB_CAD_P<2> F15 HT_CADIN_2_P HT_CADOUT_2_P E11 HT_SB_TO_NB_CAD_P<2> 60 64
64 60 HT_NB_TO_SB_CAD_N<2> E15 HT_CADIN_2_N HT_CADOUT_2_N F11 HT_SB_TO_NB_CAD_N<2> 60 64
64 60 HT_NB_TO_SB_CAD_P<3> D16 HT_CADIN_3_P HT_CADOUT_3_P D11 HT_SB_TO_NB_CAD_P<3> 60 64
64 60 HT_NB_TO_SB_CAD_N<3> C16 HT_CADIN_3_N HT_CADOUT_3_N C11 HT_SB_TO_NB_CAD_N<3> 60 64
64 60 HT_NB_TO_SB_CAD_P<4> B16 HT_CADIN_4_P HT_CADOUT_4_P A11 HT_SB_TO_NB_CAD_P<4> 60 64
64 60 HT_NB_TO_SB_CAD_N<4> A16 HT_CADIN_4_N HT_CADOUT_4_N B11 HT_SB_TO_NB_CAD_N<4> 60 64
64 60 HT_NB_TO_SB_CAD_P<5> D14 HT_CADIN_5_P HT_CADOUT_5_P C12 HT_SB_TO_NB_CAD_P<5> 60 64
64 60 HT_NB_TO_SB_CAD_N<5> C14 HT_CADIN_5_N HT_CADOUT_5_N D12 HT_SB_TO_NB_CAD_N<5> 60 64
64 60 HT_NB_TO_SB_CAD_P<6> E14 HT_CADIN_6_P HT_CADOUT_6_P E12 HT_SB_TO_NB_CAD_P<6> 60 64
64 60 HT_NB_TO_SB_CAD_N<6> F14 HT_CADIN_6_N HT_CADOUT_6_N F12 HT_SB_TO_NB_CAD_N<6> 60 64
64 60 HT_NB_TO_SB_CAD_P<7> B14 HT_CADIN_7_P HT_CADOUT_7_P A13 HT_SB_TO_NB_CAD_P<7> 60 64
64 60 HT_NB_TO_SB_CAD_N<7> A14 HT_CADIN_7_N HT_CADOUT_7_N B13 HT_SB_TO_NB_CAD_N<7> 60 64
64 60 HT_NB_TO_SB_CTL_P F13 HT_CTLIN_P HT_CTLOUT_P C13 HT_SB_TO_NB_CTL_P 60 64
64 60 HT_NB_TO_SB_CTL_N E13 HT_CTLIN_N HT_CTLOUT_N D13 HT_SB_TO_NB_CTL_N 60 64
64 60 HT_PWROK E16 HT_PWROK_H

HT_RESET_L C18 HT_RESET_L
B C6255
0.1uF
64 60
64 60 HT_LDTSTOP_L E17 HT_LDTSTOP_L HT_LDTREQ_L A19 HT_LDTREQ_L 60 64 B

27 HT_CLK66M_SB 1 2 62 HT_CLK66M_SB_C C8 HT_REFCLK HT_R100P E10 SB_HT_R100_P
D8 HT_S100M66M HT_R100N F10
20%
SB_HT_S100M66M
V6 SEL_HT00_H
SB_HT_R100_N R6250
R62551 10V
CERM
SB_SELHT100
1
82.5 2
332 402
1% AC coupled HT_PLL 1%
1/16W 1/16W
MF 1.0V pk-pk AGND DGND HT_RXGND HT_TXGND C6250 1 MF
402
1 C6251
C6
A6
A15
A17
G12
A12
A9
G10
402 2 47pF 47pF
5% 5%
50V 50V
CERM 2 2 CERM
402 402
62 7 =PP1V2_PWRON_HT
NO STUFF
R62521 R62541
4.7K 10K
5% 5%
1/16W 1/16W
MF MF
402 2 402 2
SB_HT_200M
R62531 R62511 Master: Link
4.7K 1K
5% 5%
1/16W 1/16W
MF
402 2
MF
402 2 Shasta HyperTransport
A
HT RefClk HT I/F Speed PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 = 100MHz 1 = 100MHz I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 = 66MHz 0 = 200MHz II NOT TO REPRODUCE OR COPY IT
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SAME CONNECTORS & PINOUT AS D

D
Q37 HYPERTRANSPORT BETWEEN GOLEM AND K2
NOSTUFF
NOSTUFF NOSTUFF
J6400 J6401 J6402
P6860
ST-SM-DF P6860 P6860
SYM_VER1 ST-SM-DF ST-SM-DF
SYM_VER1 SYM_VER1
NOSTUFF
R6400
62 60 HT_NB_TO_SB_CLK_N A15
A15 A15
0
A14 CLK- 62 60 HT_SB_TO_NB_CAD_P<0> 62 60 HT_SB_TO_NB_CLK_N 1 2
CLK- CLK-
GND
B12 HT_NB_TO_SB_CAD_N<7> 60 62
A14 A14 5%
62 60 HT_NB_TO_SB_CLK_P A13 D15 GND
B12 HT_SB_TO_NB_CAD_P<1> 60 62 GND
B12 TEK_HT_B12 1/10W
CLK+
B11 62 60 HT_SB_TO_NB_CAD_N<0> A13 D15 62 60 HT_SB_TO_NB_CLK_P A13 D15 MF
GND CLK+
B11 CLK+
B11 603
B10 HT_NB_TO_SB_CAD_P<7> 60 62 GND NOSTUFF GND
A12 B10 B10
62 60 HT_NB_TO_SB_CAD_P<6> D14
62 60 HT_SB_TO_NB_CAD_N<2> A12
HT_SB_TO_NB_CAD_N<1> 60 62
R6403 TEK_HT_A12 A12
TEK_HT_B10
A11 D13
B9 HT_NB_TO_SB_CAD_N<5> A11 D13

D14
1
0 2 A11 D13
D14
GND 60 62
62 60 HT_NB_TO_SB_CAD_N<6> A10 D11 GND
B9 HT_SB_TO_NB_CAD_P<3> 60 62 GND
B9 HT_RESET_L 60 62
B8 62 60 HT_SB_TO_NB_CAD_P<2> A10 5% TEK_HT_A10 A10
C
D12 D11 D11
C GND D12
B8 1/10W D12
B8
B7 HT_NB_TO_SB_CAD_P<5> 60 62 GND 603 GND
62 60 HT_NB_TO_SB_CAD_N<4> A9 D10
B7 HT_SB_TO_NB_CAD_N<3> 60 62
B7
D9 62 60 HT_SB_TO_NB_CAD_P<4> A9 D10 TEK_HT_A9 A9 D10
A8 D9 NOSTUFF D9
B6 A8 A8
62 60 HT_NB_TO_SB_CAD_P<4> A7 GND HT_NB_TO_SB_CAD_P<3> 60 62
B6 HT_SB_TO_NB_CAD_N<5> 60 62
R6404 B6 HT_LDTREQ_L 60 62
D8
D7
B5 62 60 HT_SB_TO_NB_CAD_N<4> A7 GND
D7
B5 1
0 2
TEK_HT_A7 A7 GND
D7
B5
GND D8 D8
B4 HT_NB_TO_SB_CAD_N<3> 60 62 GND GND
B4 HT_SB_TO_NB_CAD_P<5> 60 62 5% B4
D5 62 60 HT_SB_TO_NB_CAD_P<6> A6 D6 1/10W A6 D6
A5 D5 MF D5
GND
B3 HT_NB_TO_SB_CAD_P<1> 60 62
A5 603 A5
62 60 HT_NB_TO_SB_CAD_P<2> A4 D3 GND
B3 HT_SB_TO_NB_CAD_N<7> 60 62 GND
B3 HT_NB_TO_SB_CTL_N 60 62
D4
B2 62 60 HT_SB_TO_NB_CAD_N<6> A4 D3 62 60 HT_LDTSTOP_L A4 D3
GND D4
B2 D4
B2
B1 HT_NB_TO_SB_CAD_N<1> 60 62 GND GND
B1 HT_SB_TO_NB_CAD_P<7> 60 62
B1 HT_NB_TO_SB_CTL_P 60 62
D1 62 60 HT_SB_TO_NB_CTL_P A3 D2
A3 D2
A2 D1 D1
GND
A2 A2
62 60 HT_NB_TO_SB_CAD_P<0> A1 GND GND
D0 62 60 HT_SB_TO_NB_CTL_N A1 62 60 HT_PWROK A1
D0 D0
=PP2V5_HT 7 60
DEVELOPMENT
R6401
1
10K
5%
1/16W
MF
2 402
HT_VREF_DEBUG
VOLTAGE=1.25V DEVELOPMENT
MIN_LINE_WIDTH=25MIL R6402
1
10K
5%
1/16W
MF
2 402
B B
MASTER: GILA
HT DEBUG CONN
A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 64 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ALL RESISTOR PACKS ARE 47 OHM 1/16W 5%

D D
R PAKS ARE PIN SWAPPABLE ACROSS ALL SIGNALS (EXCEPT IDSELS)
PCI_SB_AD<0> RP7300 2 7 47 PCI_AD<0>

74 6 74 75 76 77
PCI_SB_AD<1> RP7303 1 8 47 PCI_AD<1>

74 6 74 75 76 77
PCI_SB_AD<2> RP7303 2 7 47 PCI_AD<2>

74 6 74 75 76 77
PCI_SB_AD<3> RP7303 4 5 47 PCI_AD<3>

74 6 74 75 76 77
74 PCI_SB_AD<4> RP7309 2 7 47 PCI_AD<4> 6 74 75 76 77
74 PCI_SB_AD<5> RP7300 1 8 47 PCI_AD<5> 6 74 75 76 77
PCI_SB_AD<6> RP7300 3 6 47 PCI_AD<6>

74 6 74 75 76 77
74 PCI_SB_AD<7> RP7309 4 5 47 PCI_AD<7> 6 74 75 76 77
PCI_SB_AD<8> RP7300 4 5 47 PCI_AD<8>

74 6 74 75 76 77
PCI_SB_AD<9> RP7301 2 7 47 PCI_AD<9>

74 6 74 75 76 77
74 PCI_SB_AD<10> RP7301 1 8 47 PCI_AD<10> 6 74 75 76 77
PCI_SB_AD<11> RP7301 4 5 47 PCI_AD<11>

74 6 74 75 76 77
PCI_SB_AD<12> RP7309 1 8 47 PCI_AD<12>

74 6 74 75 76 77
PCI_SB_AD<13> RP7309 3 6 47 PCI_AD<13>

74 6 74 75 76 77
PCI_SB_AD<14> RP7301 3 6 47 PCI_AD<14>

74 6 74 75 76 77
PCI_SB_AD<15> RP7307 1 8 47 PCI_AD<15>

74 6 74 75 76 77
74 PCI_SB_AD<16> RP7308 1 8 47 PCI_AD<16> 6 74 75 76 77
R7300
47
76 74 PCI_SB_AD<17> 1 2 PCI_AD<17> 6 74 75 76 77
5%
1/16W
MF
C 74 PCI_SB_AD<18> RP7307 2
402
7 47 PCI_AD<18> 6 74 75 76 77
C
PCI_SB_AD<19> RP7306 3 6 47 PCI_AD<19>
74 6 74 75 76 77
74 PCI_SB_AD<20> RP7305 1 8 47 PCI_AD<20> 6 74 75 76 77
PCI_SB_AD<21> RP7305 2 7 47 PCI_AD<21>

74 6 74 76 77
74 PCI_SB_AD<22> RP7302 1 8 47 PCI_AD<22> 6 74 76 77
PCI_SB_AD<23> RP7302 3 6 47 PCI_AD<23>

74 6 74 76 77
PCI_SB_AD<24> RP7304 1 8 47 PCI_AD<24>

74 6 74 75 76 77
PCI_SB_AD<25> RP7306 4 5 47 PCI_AD<25>

74 6 74 75 76 77
74 PCI_SB_AD<26> RP7305 3 6 47 PCI_AD<26> 6 74 75 76 77
R7301
PCI_SB_AD<27> 1
47 2 PCI_AD<27>
77 74 6 74 75 76 77
5%
1/16W
MF
402
74 PCI_SB_AD<28> RP7302 2 7 47 PCI_AD<28> 6 74 75 76 77
PCI_SB_AD<29> RP7304 4 5 47 PCI_AD<29>

74 6 74 75 76 77
74 PCI_SB_AD<30> RP7302 4 5 47 PCI_AD<30> 6 74 75 76 77
74 PCI_SB_AD<31> RP7304 2 7 47 PCI_AD<31> 6 74 75 76 77
74 PCI_SB_CBE_L<0> RP7303 3 6 47 PCI_CBE_L<0> 6 74 76 77
PCI_SB_CBE_L<1> RP7306 2 7 47 PCI_CBE_L<1>

74 6 74 76 77
74 PCI_SB_CBE_L<2> RP7305 4 5 47 PCI_CBE_L<2> 6 74 76 77
PCI_SB_CBE_L<3> RP7304 3 6 47 PCI_CBE_L<3>

74 6 74 76 77
PCI_SB_DEVSEL_L RP7306 1 8 47 PCI_DEVSEL_L

74 6 74 76 77
PCI_SB_FRAME_L RP7307 4 5 47 PCI_FRAME_L

74 6 74 76 77
B 74
74
PCI_SB_IRDY_L
PCI_SB_TRDY_L
RP7307
RP7308
3
3
6
6
47
47
PCI_IRDY_L
PCI_TRDY_L
6 74 76 77
6 74 76 77
B
74 PCI_SB_STOP_L RP7308 4 5 47 PCI_STOP_L 6 74 76 77
74 PCI_SB_PAR RP7308 2 7 47 PCI_PAR 6 74 76 77
PLACE CLOSE TO SHASTA
AD<17> IS IDSEL FOR AIRPORT

AD<27> IS IDSEL FOR USB
PCI SERIES TERMINATION

A
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 73 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI_AD PCI_AD<31..28> 6 73 75 76 77
PCI_AD27 PCI_AD<27> 6 73 75 76 77
PCI_AD PCI_AD<26..24> 6 73 75 76 77
PCI_AD23 PCI_AD<23> 6 73 76 77
PCI_AD22 PCI_AD<22> 6 73 76 77
PCI_AD21 PCI_AD<21> 6 73 76 77
PCI_AD20 PCI_AD<20> 6 73 75 76 77
PCI_AD PCI_AD<19..18> 6 73 75 76 77
PCI_AD17 PCI_AD<17> 6 73 75 76 77
PCI_AD PCI_AD<16..0>
D PCI PCI_CBE_L<3..0>
6 73 75 76 77
6 73 76 77
D
PCI PCI_PAR 6 73 76 77
PCI_CTL PCI_DEVSEL_L 6 73 74 76 77
PCI_CTL PCI_FRAME_L 6 73 74 76 77
PCI_CTL PCI_IRDY_L 6 73 74 76 77
PCI_CTL PCI_TRDY_L 6 73 74 76 77
PCI_CTL PCI_STOP_L 6 73 74 76 77
Page Notes
- _PP3V3_PCI
- _PP3V3_SB_PCI (can be _PP3V3_PCI)
- _PP3V3_PWRON_SB =PP3V3_SB_PCI
7
- _PP2V5_PWRON_SB
Signal aliases required by this page: NO STUFF
(NONE) 1 C7410 1 C7400 1 C7401 1 C7402 1 C7403 1 C7404
10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
BOM options provided by this page: 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM
(NONE) 805 402 402 402 402 402
=PP2V5_PWRON_SB 7 23 25 88
PCI Devices implemented on this page:
AD11 - PCI0 (0x106B/0x0053)
NO STUFF
AD11 - PCI1 (0x106B/0x0054)
AD11 - PCI2 (0x106B/0x0055)
1 C7411 1 C7405 1 C7406 1 C7407 1 C7408 1 C7409 C7420 1 C7421 1 C7422 1 C7423 1
10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C AD23
AD28
-
-
KeyLargo
SATA 150
(0x106B/0x004F,
(0x1166/0x0240,
PCI1)
PCI0 or 2)
20%
6.3V
2 CERM
805
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
2 CERM
402
20%
10V
CERM 2
402
20%
10V
CERM 2
402
20%
10V
CERM 2
402
20%
10V
CERM 2
402
C
AD29 - UATA 133 (0x106B/0x0050, PCI0 or 2)
AA22
AD30 - FireWire (0x106B/0x0052, PCI0 or 2)
B22
E21
H16
J21
M16
N21
R20
U21
V19
B20
J18
N20
U20
AD31 - Ethernet (0x106B/0x0051, PCI0)
VDDOPC PCIVDDP
U2300 OMIT
SHASTA
V1.0
BGA
PCI_CLK66M_SB_INT AB9 PCIBR_CLK_H PCI1AD_0_H L18 PCI_SB_AD<0>
27 (4 OF 8) 73
PCI1AD_1_H K19 PCI_SB_AD<1> 73
27 8 PCI_CLK33M_SB_EXT U19 PCI1CLK_H PCI1AD_2_H L22 PCI_SB_AD<2> 73
PCI1AD_3_H M22 PCI_SB_AD<3> 73

PCI PCI1AD_4_H M18 PCI_SB_AD<4> 73
PCI1AD_5_H L20 PCI_SB_AD<5> 73
PCI1AD_7_H N16 PCI_SB_AD<7> 73
PCI1AD_9_H P22 PCI_SB_AD<9> 73

"Slot A" - AD17
AB18 PCI1AD_10_H M17 PCI_SB_AD<10> 73
=PP3V3_PCI 7 25 74 75 76 77 76 74 6 PCI_SLOTA_REQ_L PCI1REQ_0_L
AA18 PCI1AD_11_H N18 PCI_SB_AD<11> 73
PCI_SLOTA_GNT_L PCI1GNT_0_L
RP7400 76 74 6
2
4.7K 7 PCI1AD_13_H N19 PCI_SB_AD<13> 73
PCI_SLOTA_REQ_L 6 74 76 "Slot G" - AD27
AB20 PCI1AD_14_H P21 PCI_SB_AD<14> 73
5% PCI_SLOTG_REQ_L PCI1REQ_1_L
1/16W
SM1
RP7400 77 74
PCI_SLOTG_GNT_L AB19 PCI1GNT_1_L

PCI1AD_15_H R22 PCI_SB_AD<15> 73
4.7K 77 74
PCI1AD_16_H P20 PCI_SB_AD<16>
B 1
5%
8 PCI_SLOTA_GNT_L 6 74 76
"Slot D" - AD20

PCI1AD_17_H V21 PCI_SB_AD<17>
73
73 76
=PP3V3_PCI
B
RP7400 1/16W
SM1 PCI_SLOTD_REQ_L V17 PCI1REQ_2_L
PCI1AD_18_H P18 PCI_SB_AD<18> 73
77 76 75 74 25 7
4.7K 74
PCI1AD_19_H T20 PCI_SB_AD<19> 73 RP7402
4 5 PCI_SLOTG_REQ_L PCI_SLOTD_GNT_L V18 PCI1GNT_2_L
74 77 74
3
4.7K 6
5% PCI_DEVSEL_L
1/16W
SM1
RP7400 PCI1AD_21_H R17 PCI_SB_AD<21> 73
77 76 74 73 6
5%
4.7K PCI1AD_22_H W21 PCI_SB_AD<22> 73 RP7402 1/16W
3 6 PCI_SLOTG_GNT_L SM1
74 77
PCI1AD_23_H Y22 PCI_SB_AD<23> 73
4
4.7K 5
5% PCI_FRAME_L
RP7401 1/16W
SM1
77 76 74 73 6
5%
4.7K PCI1AD_25_H T19 PCI_SB_AD<25> 73 1/16W RP7402
3 6 PCI_SLOTD_REQ_L SM1
74
PCI1AD_26_H T18 PCI_SB_AD<26> 73
2
4.7K 7
5% 77 76 74 73 6 PCI_IRDY_L
1/16W
SM1
RP7401 PCI1AD_27_H Y21 PCI_SB_AD<27> 73 77
5%
4.7K PCI1AD_28_H W20 PCI_SB_AD<28> 73 RP7402 1/16W
4 5 PCI_SLOTD_GNT_L SM1
74
PCI1AD_29_H T16 PCI_SB_AD<29> 73
4.7K
5% 77 76 74 73 6 PCI_TRDY_L 1 8
1/16W PCI1AD_30_H AA21 PCI_SB_AD<30> 73
SM1 5%
PCI1AD_31_H T17 PCI_SB_AD<31> 73 1/16W
SM1
RP7401
4.7K
PCI1C_BE_0_L L19 PCI_SB_CBE_L<0> 73 77 76 74 73 6 PCI_STOP_L 7 2
PCI1C_BE_1_L P16 PCI_SB_CBE_L<1> 73 5%

V22 1/16W
PCI1C_BE_2_L PCI_SB_CBE_L<2> 73 SM1
PCI1C_BE_3_L V20 PCI_SB_CBE_L<3> 73
=PP3V3_PWRON_SB 7 23 25
PCI1DEVSEL_L T22 PCI_SB_DEVSEL_L 73
PCI1FRAME_L T21 PCI_SB_FRAME_L 73 Master: Link

PCI1IRDY_L R21 PCI_SB_IRDY_L 73
1
R7455 1 C7450 1R7450
PCI1TRDY_L P19 PCI_SB_TRDY_L 73 4.7K 0.1uF 4.7K
76 75 6 ROM_CS_L AB8 ROMCS_L
PCI1STOP_L P17
N17
PCI_SB_STOP_L 73
5%
1/16W
MF
20%
10V
2 CERM
402
5%
1/16W
MF
Shasta PCI Interface
A 76 75 6
76 75 6
ROM_OE_L
ROM_WE_L
AA9
Y10
ROMOE_L
ROMRW_L
PCI1PAR_H
PCI1RST_L U18
PCI_SB_PAR
SB_PCI_RESET_L
73
2 402
1
5
2 402

A
SYS_WARM_RESET_L 2
U7450 4 PCI_RESET_L 6 8 51 58
87 77 25 8 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
Shasta drives PCI RESET, but its output 3MC74VHC1G08
SOT23-5 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
may not be valid during power-up, so
it is ANDed with a reset from the SMU.
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- _PP3V3_PCI
(NONE)
(NONE)
NOTE: This page does not specify a BootROM
part number. Must use a TABLE_x_ITEM
D symbol to declare U7500 part number. D
77 76 75 74 25 7 =PP3V3_PCI
C7500 1 C7501 1 C7502 1

2.2uF 0.1uF 0.1uF
20% 20% 20%
10V 10V 10V
CERM 2 CERM 2 CERM 2
805 402 402
11 30 31
C VPP
U7500
VCC C
FEPR-1MX8
PCI_AD<0> 21
90.0ns 25 PCI_AD<24> 6
77 76 74 73 6
A0 TSOP DQ0 73 74 76 77
PCI_AD<1> 20 26 PCI_AD<25> 6
77 76 74 73 6
A1 OMIT DQ1 73 74 76 77
PCI_AD<2> 19 27 PCI_AD<26> 6
77 76 74 73 6
A2 DQ2 73 74 76 77
PCI_AD<3> 18 28 PCI_AD<27> 6
77 76 74 73 6
A3 DQ3 73 74 76 77
PCI_AD<4> 17 32 PCI_AD<28> 6
77 76 74 73 6
A4 DQ4 73 74 76 77
PCI_AD<5> 16 33 PCI_AD<29> 6
77 76 74 73 6
A5 DQ5 73 74 76 77
PCI_AD<6> 15 34 PCI_AD<30> 6
77 76 74 73 6
A6 DQ6 73 74 76 77
PCI_AD<7> 14 35 PCI_AD<31> 6
77 76 74 73 6
A7 DQ7 73 74 76 77
PCI_AD<8> 8
77 76 74 73 6
A8
PCI_AD<9> 7
77 76 74 73 6
A9
PCI_AD<10> 36
77 76 74 73 6
A10
PCI_AD<11> 6
77 76 74 73 6
A11
PCI_AD<12> 5
77 76 74 73 6
A12
PCI_AD<13> 4
77 76 74 73 6
A13
PCI_AD<14> 3
77 76 75 74 25 7 =PP3V3_PCI
77 76 74 73 6
A14
PCI_AD<15> 2
77 76 74 73 6
A15
PCI_AD<16> 1
77 76 74 73 6
A16
PCI_AD<17> 40
R75001 R7501
1 77 76 74 73 6
A17
PCI_AD<18> 13
10K 10K 77 76 74 73 6
A18
5% 5% PCI_AD<19> 37
1/16W 1/16W
77 76 74 73 6
A19
MF MF PCI_AD<20> 38
402 2 R7502 2 402
77 76 74 73 6
A20
ROM_CS_L 1
1K 2 76 6 ROM_ONBOARD_CS_L 22
76 74 6
CE
Allows ROM override module 5% ROM_OE_L 24
B to intercept ROM chip select
1/16W
MF
402
76 74 6
76 74 6 ROM_WE_L 9
OE
WE B
6 ROM_WP_L 12
WP
=PCI_ROM_RESET_L 10
8
PWD
GND
23 39
Master: Link
BootROM
A
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI_CLK_AIRPORT CLOCKS _PCI_CLK33M_AIRPORT 8 76
Page Notes
- _PP3V3_PCI
- _PCI_CLK33M_AIRPORT (33MHz PCI clock)
D BOM options provided by this page: D

(NONE)
AD17 (Slot "A") - AirPort (0x????/0x????)
NOTE: This AirPort implementation does
not support PME#. =PP3V3_PCI
77 75 74 25 7
NO STUFF NO STUFF
1 C7600 1 C7601 1 C7602 1 C7603
10UF 10UF 0.1UF 0.1UF
20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 10V
CERM 2 10V
CERM
1206 1206 402 402
CRITICAL
J7600
RCPT-CARD-EDGE
F-ST-TH1
SIDE-A SIDE-B
8 PCI_AIRPORT_RESET_L 1 2
6 TP_AIRPORT_RF_DISABLE 3 4 _PCI_CLK33M_AIRPORT 8 76
74 6 PCI_SLOTA_REQ_L 5 6
7 8 PCI_SLOTA_GNT_L 6 74
77 75 74 73 6 PCI_AD<31> 9 10 TP_AIRPORT_PME_L 6
11 12 PCI_SLOTA_INT_L 6 25
77 75 74 73 6 PCI_AD<29> 13 14 PCI_AD<30> 6 73 74 75 77
C 77 75 74 73 6
77 75 74 73 6
PCI_AD<27>
PCI_AD<25>
15
17
16
18 PCI_AD<28> 6 73 74 75 77
C
19 20 PCI_AD<26> 6 73 74 75 77
77 74 73 6 PCI_CBE_L<3> 21 22 PCI_AD<24> 6 73 74 75 77
R7600
23 24
22
6 PCI_SLOTA_IDSEL 1 2 PCI_SB_AD<17> 73 74
77 74 73 6 PCI_AD<23> 25 26 5%
1/16W
77 74 73 6 PCI_AD<21> 27 28 PCI_AD<22> 6 73 74 77 MF
402
77 75 74 73 6 PCI_AD<19> 29 30 PCI_AD<20> 6 73 74 75 77
31 32 PCI_PAR 6 73 74 77
77 75 74 73 6 PCI_AD<17> 33 34 PCI_AD<18> 6 73 74 75 77
35 36 PCI_AD<16> 6 73 74 75 77
77 74 73 6 PCI_CBE_L<2> 37 38
77 74 73 6 PCI_IRDY_L 39 40 PCI_FRAME_L 6 73 74 77
41 42 PCI_TRDY_L 6 73 74 77
6 AIRPORT_CLKRUN_L_PD 43 44 PCI_STOP_L 6 73 74 77
45 46 PCI_DEVSEL_L 6 73 74 77
77 74 73 6 PCI_CBE_L<1> 47 48
77 75 74 73 6 PCI_AD<14> 49 50 PCI_AD<15> 6 73 74 75 77
51 KEY 52 PCI_AD<13> 6 73 74 75 77
77 75 74 73 6 PCI_AD<12> 53 54 PCI_AD<11> 6 73 74 75 77
77 75 74 73 6 PCI_AD<10> 55 56
75 74 6 ROM_WE_L 57 58 PCI_AD<9> 6 73 74 75 77
77 75 74 73 6 PCI_AD<8> 59 60 PCI_CBE_L<0> 6 73 74 77
77 75 74 73 6 PCI_AD<7> 61 62 ROM_OE_L 6 74 75
63 64 PCI_AD<6> 6 73 74 75 77
77 75 74 73 6 PCI_AD<5> 65 66
B 75 6
77 75 74 73 6
ROM_ONBOARD_CS_L
PCI_AD<3>
67
69
68
70
PCI_AD<4>
PCI_AD<2>
6 73 74 75 77
6 73 74 75 77
B
71 72 PCI_AD<0> 6 73 74 75 77
77 75 74 73 6 PCI_AD<1> 73 74
75 74 6 ROM_CS_L 75 76 NC
77 78 NC
RESERVED FOR USB_DP AND USB_DN
NC
NC 79 80
R7612 NC 81 82 NC
0 83 84 NC
94 25 6 I2S1_MCLK 1 2 I2S1_MCLK_MARTY
SCC_RTS_L 85 86 NC
5% I2S1_DEV_TO_SB_DTI_MARTY
1/16W
MF NC 87 88 NC
402
I2S1_SB_TO_DEV_DTO_MARTY 89 90 NC RESERVED FOR RADIO_IO
NC 91 92 NC
R7610 NC 93 94 NC
0 95 96 NC
94 25 6 I2S1_DEV_TO_SB_DTI 1 2 NC
SCC_RXDA 97 98 NC
5% PP5V_PWRON_AIRPORT_MARTY
1/16W MIN_LINE_WIDTH=25MIL
MF MIN_NECK_WIDTH=10MIL NC 99 100 NC
402
516-0069
R7611
I2S1_SB_TO_DEV_DTO 1
0 2
94 25 6
SCC_TXDA
5%
1/16W
MF R76011
402 10K
5%
1/16W
7 =PP5V_PWRON_AIRPORT R7613
0
MF
402 2 AirPort Extreme
A 1
5%
1/16W
2

A
MF
402
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 76 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI_CLK_USB2 CLOCKS =PCI_CLK33M_USB2 8 77
Page Notes
- _PPVIO_PCI (to 3.3V or 5V)
- _PCI_CLK33M_USB2 (33MHz PCI clock)
D BOM options provided by this page: D

(NONE) =PPVIO_PCI_USB2
7

AD27 (Slot "G") - USB2 (0x1033/0x0035)
NOTE: This USB2 implementation supports
C7703 1
0.1uF
D3cold. 20%
10V
CERM 2
402
H3
M4
C8
PCI_AD<0> M5
76 75 74 73 6 AD0
VDD_PCI
PCI_AD<1> P5
76 75 74 73 6 AD1
PCI_AD<2> N5
76 75 74 73 6 AD2
PCI_AD<3> P4
76 75 74 73 6 AD3
PCI_AD<4> N4
76 75 74 73 6 AD4
PCI_AD<5> M3
76 75 74 73 6 AD5
PCI_AD<6> N3 CRITICAL
76 75 74 73 6 AD6
76 75 74 73 6 PCI_AD<7>
PCI_AD<8>
M1
L2
AD7
AD8
U7700
76 75 74 73 6
76 75 74 73 6 PCI_AD<9> L1
AD9
NEC_uPD720101_USB2
FBGA
76 75 74 73 6 PCI_AD<10> K2 AD10
PCI_AD<11> L3
76 75 74 73 6 AD11
PCI_AD<12> K1
76 75 74 73 6 AD12
PCI_AD<13> K3
76 75 74 73 6 AD13
PCI_AD<14> J2
76 75 74 73 6 AD14
PCI_AD<15> J1
76 75 74 73 6 AD15
C 76 75 74 73 6 PCI_AD<16>
PCI_AD<17>
F2
E3
AD16 C
76 75 74 73 6 AD17
PCI_AD<18> E1
76 75 74 73 6 AD18
PCI_AD<19> D3
76 75 74 73 6 AD19
PCI_AD<20> D1
76 75 74 73 6 AD20
76 74 73 6 PCI_AD<21> D2 AD21
PCI_AD<22> C2
76 74 73 6 AD22
PCI_AD<23> C1
76 74 73 6 AD23
PCI_AD<24> B4
76 75 74 73 6 AD24
PCI_AD<25> A4
76 75 74 73 6 AD25
PCI_AD<26> B5
76 75 74 73 6 AD26
PCI_AD<27> (PCI_AD<27>) C4
76 75 74 73 6 AD27
6 PCI_AD<28>
A5
76 75 74 73 AD28
6 PCI_AD<29>
C5
76 75 74 73 AD29
PCI_SB_AD<27> 6 PCI_AD<30>
B6
74 73 76 75 74 73 AD30
6 PCI_AD<31>
A6
76 75 74 73 AD31
PCI_CBE_L<0> M2
76 74 73 6 CBE0
R77141 76 74 73 6 PCI_CBE_L<1> J3
CBE1
22 76 74 73 6 PCI_CBE_L<2> F1
CBE2
5% C3
1/16W 76 74 73 6 PCI_CBE_L<3> CBE3
MF
402 2
PCI_PAR J4
76 74 73 6 PAR
PCI_FRAME_L F3
=PP3V3_PCI
76 74 73 6 FRAME
76 75 74 25 7
PCI_IRDY_L F4
76 74 73 6 IRDY
PCI_TRDY_L G1
76 74 73 6 TRDY
B R77161 R77131
76 74 73 6 PCI_STOP_L
PCI_SLOTG_IDSEL
G3
STOP
B3 IDSEL
B
10K 10K G2
5% 5% 76 74 73 6 PCI_DEVSEL_L DEVSEL
1/16W 1/16W C6
MF MF PCI_SLOTG_REQ_L REQ
RP7703 402 2 402 2
74
PCI_SLOTG_GNT_L D6
GNT
4
47 5
74
H2
25 PCI_SLOTG_INT_L NEC_PERR_L_PU PERR IPD NTEST1 M8 TP_NEC_NTEST1 6
NEC_SERR_L_PU H1
5% SERR OD
1/16W
SM1
RP7703 NEC_INTA_L C7
INTA OD IPD SMC M7 TP_NEC_SMC
47 6
2 7 NEC_INTB_L B7
INTB OD
NEC_INTC_L A7
5% INTC OD
RP7703 1/16W
SM1 =PCI_CLK33M_USB2 A8
PCLK IPD TEB N7 TP_NEC_TEB
47 77 8 6
3 6 IPD AMC P7 TP_NEC_AMC 6
5% NEC_VBBRST_L B8 VBBRST (CHIP RESET)

1/16W
SM1
RP7702 NEC_CRUN_L_PD N6
CRUN IPD TEST L8 TP_NEC_TEST
47 6
SYS_WARM_RESET_L 3 6 NEC_PME_L D9
87 74 25 8 PME OD
NEC_VCCRST_L C9
5% VCCRST (PCI RESET)
RP7702 1/16W
SM1 TP_NEC_SMI_L L6
SMI OD NANDTEST M10 TP_NEC_NANDTEST
47 6 6
25 13 SYS_PME_L 4 5 SRCLK M9 TP_NEC_SRCLK 6
5% SRDTA N9 TP_NEC_SRDATA
1/16W
SM1
RP7702 NEC_LEGC_PD L7
LEGC IPD SRMOD P9 TP_NEC_SRMOD
6
47 6
8 =PCI_USB2_RESET_L 2 7
8
5%
1/16W
SM1
R77151 RP7703 Master: Link
4.7K 47
RP7702 & RP7703 required to 5%
1/16W 5%
facilitate NAND-tree testing MF
402 2
1
1/16W
SM1 USB 2.0 PCI Interface
A
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SATA_RXD1
SATA_RXD1
SATA
SATA
SATA_RXD1_C
SATA_RXD1_C
SATA_RXD_P1_C
SATA_RXD_N1_C
80 83
80 83
UATA Termination
SATA_TXD1 SATA SATA_TXD1 SATA_TXD_P1 80 83
SATA_TXD1 SATA SATA_TXD1 SATA_TXD_N1 80 83 RP8000

33
SATA_RXD2 SATA SATA_RXD2_C SATA_RXD_P2_C 80 83 80 UATA_DD_R<0> 4 5 UATA_DD<0> 6 80 83
SATA_RXD2 SATA SATA_RXD2_C SATA_RXD_N2_C 5%

80 83
RP8000 1/16W
SM1
SATA_TXD2 SATA SATA_TXD2 SATA_TXD_P2 80 83 33
80 UATA_DD_R<1> 3 6 UATA_DD<1> 6 80 83
SATA_TXD2 SATA SATA_TXD2 SATA_TXD_N2 80 83
D UATA_DD UATA_DD<15..8> 6 80 83
5%
1/16W
SM1
RP8000
2
33 7
D
UATA_DD7 UATA_DD<7> 6 80 83 80 UATA_DD_R<2> UATA_DD<2> 6 80 83
UATA_DD UATA_DD<6..0> 5%
UATA_HOST UATA_DA<2..0>
6 80 83
RP8003 1/16W
SM1
6 80 83
33
UATA_HOST UATA_CS0_L 6 80 83 80 UATA_DD_R<3> 4 5 UATA_DD<3> 6 80 83
UATA_HOST UATA_CS1_L 5%
UATA_HOST UATA_HSTROBE
6 80 83
1/16W
SM1
RP8001
6 80 83
1
33 8
UATA_HOST UATA_STOP 6 80 83 80 UATA_DD_R<4> UATA_DD<4> 6 80 83
UATA_HOST_R UATA_DMACK_L 5%
UATA_HOST_R UATA_RESET_L
6 80 83
RP8001 1/16W
SM1
6 80 83
2
33 7
UATA_DEV_R_C UATA_DSTROBE 80 83 80 UATA_DD_R<5> UATA_DD<5> 6 80 83
UATA_DEV_R UATA_DMARQ 5%
UATA_DEV_R UATA_INTRQ
80 83
1/16W
SM1
RP8003
80 83
33
80 UATA_DD_R<6> 3 6 UATA_DD<6> 6 80 83
Page Notes
5%
RP8002 1/16W
SM1
33
80 UATA_DD_R<7> 1 8 UATA_DD<7> 6 80 83
Power aliases required by this page: 5%

- _PP1V2_PWRON_DISK R80051
1/16W
SM1
RP8002
33
10K UATA_DD_R<8> 2 7 UATA_DD<8>
Signal aliases required by this page: 7 =PP1V2_PWRON_DISK_SB SATA_VDD x 5 5%
1/16W
80
5%
6 80 83
(NONE) MF
402 2
RP8003 1/16W
SM1
2
33 7
BOM options provided by this page: UATA_DD_R<9> UATA_DD<9>
(NONE)
1 C8000 1 C8001 1 C8002 1 C8003 1 C8004 80
5%
6 80 83
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1/16W RP8000

20% 20% 20% 20% 20% SM1
2 10V 2 10V 2 10V 10V
2 CERM 2 10V 33
Net Spacing Type: SATA CERM
402
CERM
402
CERM
402 402
CERM
402 80 UATA_DD_R<10> 1 8 UATA_DD<10> 6 80 83
C Line To Line: 15 mils RP8002 5%

1/16W C
AB14
AB17
33 SM1
Length Tolerance: 50 mils
T14
W15
Y18
80 UATA_DD_R<11> 4 5 UATA_DD<11> 6 80 83
Primary Max Sep: 10 mils outer
5%
Primary Max Sep: 9 mils inner SATA_VDD 1/16W
SM1
RP8001
33
Secondary Max Sep: 100 mils U2300 OMIT
80 UATA_DD_R<12> 3 6 UATA_DD<12> 6 80 83
Secondary Length: 500 mils SHASTA 5%
NOTE: Target differential impedance for V1.0 RP8002 1/16W
SM1
BGA 33
SATA data pairs is 100 ohms. 80 UATA_DD_R<13> 3 6 UATA_DD<13> 6 80 83
(5 OF 8)
UD_IDEDD_0_H J6 UATA_DD_R<0> 5%
UD_IDEDD_1_H H7 UATA_DD_R<1>
80
1/16W
SM1
RP8004
80
33
UD_IDEDD_2_H H6 UATA_DD_R<2> 80 80 UATA_DD_R<14> 1 8 UATA_DD<14> 6 80 83
UD_IDEDD_3_H E2 UATA_DD_R<3> 5%
UD_IDEDD_4_H C1 UATA_DD_R<4>
80
RP8003 1/16W
SM1
80
33
UD_IDEDD_5_H C2 UATA_DD_R<5> 80 80 UATA_DD_R<15> 1 8 UATA_DD<15> 6 80 83
UD_IDEDD_6_H E3 UATA_DD_R<6> 5%
UD_IDEDD_7_H G6 UATA_DD_R<7>
80
1/16W
SM1
RP8004
80
33
UD_IDEDD_8_H G5 2 7
UATA
UATA_DD_R<8> 80 80 UATA_DA_R<0> UATA_DA<0> 6 80 83
UD_IDEDD_9_H D4 UATA_DD_R<9> 5%
UD_IDEDD_10_H G7 UATA_DD_R<10>
80
RP8001 1/16W
SM1
80
33
UD_IDEDD_11_H F6 UATA_DD_R<11> 80 80 UATA_DA_R<1> 4 5 UATA_DA<1> 6 80 83
UD_IDEDD_12_H C3 UATA_DD_R<12> 5%
DSTROBE aka: UD_IDEDD_13_H F5 UATA_DD_R<13>
80
1/16W
SM1
RP8004
80
33
IORDY/HDMARDY* UD_IDEDD_14_H E5 UATA_DD_R<14> 80 80 UATA_DA_R<2> 4 5 UATA_DA<2> 6 80 83
UD_IDEDD_15_H D5 UATA_DD_R<15> 5%
HSTROBE aka:
80
RP8004 1/16W
SM1
DIOR* UD_IDEDA0_H E6 UATA_DA_R<0> 80 33
UATA_RESET_L_R 3 6 UATA_RESET_L
B STOP aka:
UD_IDEDA1_H C4
UD_IDEDA2_H D6
UATA_DA_R<1>
UATA_DA_R<2>
80
80
80
5%
1/16W R8000
6 80 83
B
DIOW* SM1
B3 33
UD_IDECS1FX_L UATA_CS0_L_R 80 80 UATA_CS0_L_R 1 2 UATA_CS0_L 6 80 83
83 80 UATA_DSTROBE F9 UD_IDECHRDY_H UD_IDECS3FX_L B4 UATA_CS1_L_R 80 5%
D7 UD_IDEDMARQ_H E8
R8001 1/16W
MF
83 80 UATA_DMARQ UD_IDEDMACK_L UATA_DMACK_L_R 80 33 402
E4 80 UATA_CS1_L_R 1 2 UATA_CS1_L 6 80 83
C5 UD_IDEINTRQ_H UD_IDERD_L UATA_HSTROBE_R 80
83 80 UATA_INTRQ D3
5%
UD_IDEWR_L
E7
UATA_STOP_R 80 1/16W
MF R8002
UD_IDERST_L UATA_RESET_L_R 80 402 22
80 UATA_HSTROBE_R 1 2 UATA_HSTROBE 6 80 83
83 80 SATA_RXD_P1_C Y17 RXDP1 TXDP1 AA16 SATA_TXD_P1 80 83 5%

83 80 SATA_RXD_N1_C Y16 RXDN1 SATA 0 TXDN1 AB16 SATA_TXD_N1 80 83
R8003 1/16W
MF
22 402
80 UATA_STOP_R 1 2 UATA_STOP 6 80 83
83 80 SATA_RXD_P2_C AB15 RXDP2 TXDP2 Y15 SATA_TXD_P2 80 83
AA15 RXDN2 SATA 1 5%
83 80 SATA_RXD_N2_C TXDN2 Y14 SATA_TXD_N2 80 83 1/16W
R8004
MF
AC coupling required for any SATA pair used. SATA_GND UATA_DMACK_L_R
402
1
22 2 UATA_DMACK_L
80 6 80 83
Recommend 0.1uF cap placed close to Shasta.
AA14
AA17
T13
W16
5%
(Caps provided by device page) 1/16W
MF
402
Master: Link
Shasta Disk
A
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
83 80 6 UATA_DD<15..8> UATA_DD
83 80 6 UATA_DD<7> UATA_DD7
83 80 6 UATA_DD<6..0> UATA_DD
83 80 6 UATA_DA<2..0> UATA_HOST
83 80 6 UATA_CS0_L UATA_HOST
83 80 6 UATA_CS1_L UATA_HOST
83 80 6 UATA_HSTROBE UATA_HOST
83 80 6 UATA_STOP UATA_HOST
83 80 6 UATA_DMACK_L UATA_HOST_R
UATA_RESET_L UATA_HOST_R
D
83 80 6
83 80 UATA_DSTROBE UATA_DEV_R_C D
83 80 UATA_DMARQ UATA_DEV_R
83 80 UATA_INTRQ UATA_DEV_R
SATA CONNECTORS
PATA CONNECTOR
C8304
0.1UF
SATA_TXD_P1_C 1 2 SATA_TXD_P1 80 83 7 =PP5V_PATA
J8300 C8305 20%

10V =PP3V3_PATA
LD18077-S04 0.1UF CERM
7
ATA-6 spec does not call out R8180 or R8182
M-ST-TH SATA_TXD_N1_C 1 2 402 SATA_TXD_N1 80
1 NO STUFF
C8307
2
20%
10V
0.1UF R8313
NO STUFF
1 R83111
CERM 10K
3 SATA_RXD_N1 402 1 2 SATA_RXD_N1_C 80 10K 5%
4 5% 1/16W
C8308 20%
1/16W CRITICAL MF
MF 402 2
5 0.1UF 10V
CERM
402 2 J8301
6 SATA_RXD_P1 1 2 402 SATA_RXD_P1_C 80 804RVS
7
R8314
1 F-ST-SM
1
R8312
20% 51 1K
10V
CERM
4.7K 5%
402
5% 1/16W
518-0157 1/16W MF
C MF
2 402 Per ATA Spec
NC 1
3
2
4
NC
NC
2 402
Obsolete
C
83 80 6 UATA_RESET_L 5 6 UATA_DD<8> 6 80 83
83 80 6 UATA_DD<7> 7 8 UATA_DD<9> 6 80 83
83 80 6 UATA_DD<6> 9 10 UATA_DD<10> 6 80 83
83 80 6 UATA_DD<5> 11 12 UATA_DD<11> 6 80 83
DEVELOPMENT
UATA_DD<4> 13 14 UATA_DD<12>
C8302 Sourced by drive
83 80 6 6 80 83
0.1UF 83 80 6 UATA_DD<3> 15 16 UATA_DD<13> 6 80 83

1 2 Terminate near connector
NOSTUFF SATA_TXD_P2_C SATA_TXD_P2 80 83 80 6 UATA_DD<2> 17 18 UATA_DD<14> 6 80 83
DEVELOPMENT
UATA_DD<1> 19 20 UATA_DD<15>
J8302 C8303 20%
10V
83 80 6
UATA_DD<0> 21 22
6 80 83
LD18077-S04 0.1UF CERM

83 80 6
M-ST-TH SATA_TXD_N2_C 1 2 402 SATA_TXD_N2 80 23 24 UATA_HSTROBE 6 80 83
1 DEVELOPMENT
20% C8300 83 80 6 UATA_STOP 25 26
2 10V
0.1UF 6 UATA_DSTROBE_R 27 28 UATA_DMACK_L 6 80 83
3 SATA_RXD_N2
CERM
402 1 2 SATA_RXD_N2_C 80
R8315 6 UATA_INTRQ_R 29 30 UATA_IOCS16_PU 6
4 DEVELOPMENT
UATA_DSTROBE
82
C8306 20%
83 80 1 2 83 80 6 UATA_DA<1> 31 32 NC
5 0.1UF 10V 5% 83 80 6 UATA_DA<0> 33 34 UATA_DA<2> 6 80 83
CERM 1/16W
6 SATA_RXD_P2 1 2 402 SATA_RXD_P2_C 80 MF 83 80 6 UATA_CS0_L 35 36 UATA_CS1_L 6 80 83
402
7 UATA_DASP_L 37 38
20%
10V R8316 39 40
CERM
402 UATA_INTRQ 1
82 2 41 42
518-0157 83 80
NO STUFF 5% 43 44
1/16W
C8301 1 MF
402
45 46
10pF 6 UATA_CSEL_PD 47 48
5%
50V 49 50
CERM 2 NC NC
402
52
B HD POWER R8320
82
B
83 80 UATA_DMARQ 1 2 6 UATA_DMARQ_R
5% 516S0264
1/16W
MF
402
ATA-6 spec does not call out C8177

=PP5V_DISK 6 7
CRITICAL
=PP5V_PATA R83191 1
R8318 1R8317
J8303 =PP12V_DISK
83 7
5.6K 0 6.2K
S05B-XA 6 7
DEVELOPMENT
5%
1/16W
5%
1/16W
5%
1/16W
M-RT-TH MF MF MF
1 =PP3V3_DISK 7
R8321 1 402 2 2 402 2 402
PER ATA7 SPEC
2
499 Per ATA Spec
1%
3 1/16W Per ATA Spec
MF DEVELOPMENT
4 402 2
5
LED8301
UATA_DASP_L_DS 1 2
518-0144
GREEN
2.0X1.25A
"UATA ACTIVE"
DISK CONNECTORS
A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 83 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ENET_RX_CLK ENET 10 MIL ENET_CLK25M_TX 84 87
ENET_RX_CLK ENET 10 MIL ENET_CLK125M_RX 84 87
ENET_GBE_REF ENET 15 MIL SPACING ENET_CLK125M_GBE_REF 84 87
ENET_TX_CLK ENET 15 MIL SPACING ENET_CLK125M_GTX 84 87
ENET 15 MIL SPACING ENET_CLK125M_GTX_R 84
ENET_RX ENET ENET_RXD<7..0> 84 87
ENET_RX_CTL ENET ENET_RX_DV 84 87
ENET_RX_CTL ENET ENET_RX_ER 84 87
ENET_TX ENET ENET_TXD<7..0>
D ENET_TX_CTL ENET ENET_TX_EN

84 87
84 87 D
ENET_TX_CTL ENET ENET_TX_ER 84 87
ENET_RX_CTL ENET ENET_CRS 84 87
ENET_RX_CTL ENET ENET_COL 84 87
ENET_MDC ENET ENET_MDC 84 87
ENET_MDIO ENET ENET_MDIO 84 87
Page Notes
(NONE)
(NONE)
(NONE)
RP8400
0K
2 7 ENET_TXD<0> 84 87
C OMIT RP8400 5%
1/16W
C
0K SM1
U2300 4 5 ENET_TXD<1> 84 87
SHASTA 5%
1/16W RP8400
V1.0 SM1 0K
BGA 1 8 ENET_TXD<2> 84 87
(6 OF 8)
5%
87 84 ENET_CLK25M_TX H5 ETH_TX_CLK_H
RP8400 1/16W
ETHERNET
J3 ETH_RX_CLK_H 0K SM1
87 84 ENET_CLK125M_RX 3 6 ENET_TXD<3> 84 87
ENET_RXD<0> K1 ETH_RXD_0_H ETH_TXD_0_H G4 ENET_TXD_R<0> 5%

87 84
ENET_RXD<1> L3 ETH_RXD_1_H ETH_TXD_1_H E1 ENET_TXD_R<1>

1/16W
SM1
RP8401
87 84
K2 ETH_RXD_2_H
0K
87 84 ENET_RXD<2> ETH_TXD_2_H H4 ENET_TXD_R<2> 2 7 ENET_TXD<4> 84 87
ENET_RXD<3> J1 ETH_RXD_3_H ETH_TXD_3_H J5 ENET_TXD_R<3> 5%

87 84
ENET_RXD<4> L4 ETH_RXD_4_H ETH_TXD_4_H G3 ENET_TXD_R<4> RP8401 1/16W

SM1
87 84
0K
87 84 ENET_RXD<5> K3 ETH_RXD_5_H ETH_TXD_5_H F2 ENET_TXD_R<5> 4 5 ENET_TXD<5> 84 87
ENET_RXD<6> J2 ETH_RXD_6_H ETH_TXD_6_H J4 ENET_TXD_R<6> 5%

87 84
ENET_RXD<7> G1 ETH_RXD_7_H ETH_TXD_7_H K6 ENET_TXD_R<7>

1/16W
SM1
RP8401
87 84
1
0K 8 ENET_TXD<6> 84 87
87 84 ENET_RX_DV K4 ETH_RX_DV_H ETH_TX_EN_H H3 ENET_TX_EN_R
5%
87 84 ENET_RX_ER G2 ETH_RX_ER_H ETH_TX_ER_H F1 ENET_TX_ER_R RP8401 1/16W
SM1
M5 ETH_REFCLK_H
0K
87 84 ENET_CLK125M_GBE_REF ETH_GTX_CLK_H K5 84 ENET_CLK125M_GTX_R 3 6 ENET_TXD<7> 84 87
L6 ETH_CRS_H 5%
87 84 ENET_CRS ETH_MDC_H M4 ENET_MDC 84 87 1/16W R8400
SM1
L5 ETH_COL_H 0
87 84 ENET_COL ETH_MDIO_H M6 ENET_MDIO 84 87 1 2 ENET_TX_EN 84 87
5%
R8401 1/16W
MF
0 402
B 1
5%
2 ENET_TX_ER 84 87
B
1/16W
MF R8402
402 0
1 2 ENET_CLK125M_GTX 84 87
5%
1/16W
MF
402
Master: Link
Shasta Ethernet
A
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR ETHERNET ROUTING PRIORITY:

1. DECOUPLING CAPS
ENET_MDI_TX ENET ENET_MDI_TD ENET_TDP 87
2. TX TERMINATION - LOCATE NEAR PHY
ENET_MDI_TX ENET ENET_MDI_TD ENET_TDN 87
3. RX TERMINATION - LOCATE NEAR PHY
ENET_MDI_RX ENET ENET_MDI_RD ENET_RDP 87
ENET_MDI_RX ENET ENET_MDI_RD ENET_RDN 87 ROUTE TD OVER 2.5V PLANE (BOTTOM LAYER) ONLY
ROUTE RD OVER GROUND PLANE (TOP LAYER) ONLY
ENET_XTAL 15 MIL SPACING ENET_CLK25M_XIN 87
15 MIL SPACING ENET_CLK25M_XOUT 87 ALL DIFFERENTIAL SIGNALS SHOULD BE CLOSE,

PP2V5_ENET
D
MIN_NECK_WIDTH=10MIL PARALLEL, MATCHED LENGTHS, WITH MINIMUM
VIA COUNT, AND SHORT IF POSSIBLE D
1
C8703 1
C8704 1
C8702 1
C8705 1
C8712 CLEAR OUT ALL PLANES BETWEEN MIDDLE
0.1UF 0.01UF 0.1UF 0.01UF 10UF
20% 20% 20% 20% 20%
OF TRANSFORMER AND CONNECTOR
10V 16V 10V 16V 6.3V
87 7 PP3V3_PWRON_ENET 402 402 402 402 805
ENET_DVDD VOLTAGE=2.5V
1
C8711 1
C8716 1
C8708 1
C8715 1
C8709
10UF 0.1UF 0.01UF 0.1UF 0.01UF
20% 20% 20% 20% 20%
6.3V 10V 16V 10V 16V NC
20
55
27
28
46
22
805 402 402 402 402
8
1
C8722 (514-0200)
REGDVDD
REGAVDD
DVDD1
DVDD2
AVDD1
AVDD2
OVDD1
OVDD2
REFCLK
BIASVDD
OVDD/NC
0.1UF
20%
CRITICAL
1
C8710 1 1
2
10V
CERM
(PLACE R3126, R3127
R3117, R3118
0.1UF R8701 R8700 402
J8700
20% 49.9 49.9
CLOSE TO PHY) 10V
NOTE: PLACE R3128, R3100, RP 3101 CLOSE TO PHY 2 CERM 1% 1% RJ45
402 1/16W 1/16W
MF MF JFM24V10
402 402
2 2 F-ST-TH
R8706 PRIMARY
I237 33
ENET_CLK25M_TX CLK_ENET_LINK_TX 1 2 CLKENET_PHY_TX 53 TXC TD+ 31 9
U8700
84
MAKE_BASE=TRUE NET_SPACING_TYPE=10 MIL
5%
1/16W
NET_SPACING_TYPE=10 MIL
84 ENET_TXD<0> 57 TXD0 TD- 30 10
MF
402 84 ENET_TXD<1> 58 TXD1 BCM5231 RD+ 26 SYM_VER-3 SECONDARY
84 ENET_TXD<2> 59 TXD2 TQFP RD- 25 ENET_TDP 1 1CT:1CT J1
ENET_TXD<3> 60 TXD3 2 J2
87
84
NC 21
C
(SYM_VER2)
NC 19
1 1
ENET_TDN 3 J3
C
7
PP3V3_PWRON_ENET R8703 R8702
ENET_CLK125M_RX
I238
CLK_ENET_LINK_RX
84 ENET_TX_EN 56 TXEN CRITICAL
NC
49.9 49.9 ENET_RDP 4 J4
84
MAKE_BASE=TRUE NET_SPACING_TYPE=10 MIL 84 ENET_TX_ER 52 TXER 1 1
1%
1/16W
1%
1/16W
5 J5
R8712 R8713 MF MF
ENET_RDN 6 TX-SIDE J6
RP8700 R8707 10K 10K
402
2 2
402
7 1CT:1CT J7
33 1
MF
33
2
402
CLKENET_PHY_RX 50
RXC FDX 39 ENET_5221_FDX 87
5%
1/16W
5%
1/16W
8 J8
5%
1/16W 5%
48 F100/JTAG_TCK 37 TP_ENET_TCK 6
MF
402
MF
402
84 ENET_RXD<0> 1 8 ENET_PHY_RXD<0>
47
RXD0 ANEN/JTAG_TRST 38 ANEN
2 2
RJ45
CABLE SIDE
44
RXD1 TESTEN 15 ENET_5221_TESTEN 87 11
43
RXD2 OVDD/NC 18 MII_EN 12
RX-SIDE
84 ENET_RXD<3>
R8709
4 5 ENET_PHY_RXD<3> RXD3 LOW_PWR 16 ENET_5221_LOW_PWR 87
RJ45
1/16W
49
84 ENET_RX_DV 1
33
2
SM1 ENET_PHY_RX_DV
51
RXDV GND_CHASSIS_RJ45
CHIP SIDE 75
OHM
75
OHM
75
OHM
75
OHM
ENET_PHY_RX_ER RXER 1
C8721
7
5%
1/16W
1
C8706 1
C8707 1
C8714 0.1UF
ENET_PHY_CRS 62
MF
402 RP8701
61
CRS ENERGY_DET 17 ENET_ENERGYDET 25
0.1UF
20%
0.1UF
20%
0.1UF
20%
2
20%
10V
ENET_PHY_COL 10V 10V 10V CERM
ENET_RX_ER 8
33
1 COL 2 CERM 2 CERM 2 CERM 402 SHIELD 1000PF, 2000V
84
RP8701 33 1/16W 5%
9 RDAC 23 402 402 402
84 ENET_CRS
1/16W
5 4
5%
RP8701 33
ETHPHYRESET_L
RESET*
84 ENET_COL 6 3
42
ENET_MDC
1/16W 5% 84
41
MDC
87 7 PP3V3_PWRON_ENET MDIO
87
87
87
1 C8750 6 LNKLED/JTAG_TDI* 35 ENET_TDI 87 TWO OF THESE CAPS SHOULD BE NEAR
XTALI
7
SPDLED/JTAG_TMS*
7
36 ENET_TMS J8700 PINS 2&5 PP3V3_PWRON_ENET PP3V3_PWRON_ENET PP3V3_PWRON_ENET
0.1uF 5 87
20% XTALO XMTLED* 34 XMIT_LED 87
2 10V
5
CERM
402 NC
10
PHYAD0 RCVLED/JTAG_TDO* 33 TP_ENET_TDO DEVELOPMENT DEVELOPMENT
1 R8711 11 DEVELOPMENT
77 74 25 8 SYS_WARM_RESET_L
0
NC
PHYAD1 1
R8717 1
R8716 1
R8715 1
R8714
87 7 PP3V3_PWRON_ENET
2
U8750 4 ETHPHYRESET_L_R 1 2 NC
12
13
PHYAD2 1
R8704 1
R8718 330 330 330 4.7K
5% NC
PHYAD3 10K 4.7K 5% 5% 5% 5%
ENET_RDAC_PD
B B
1/16W 5% 5% 1/16W 1/16W 1/16W 1/16W
R87191 3MC74VHC1G08
SOT23-5
MF
402
NC
14
PHYAD4 1/16W
MF
1/16W
MF
MF
603
MF
603
MF
603
MF
603
1K 2 2 2 2
JTAG_EN
XTALGND
BIASGND
PHY ADDRESS 00000 402 603
2 2
5%
OGND3/
1/16W 87 7 PP3V3_PWRON_ENET DS3P1 DS1P1 DS2P1

OGND1
OGND2
DGND1
DGND2
AGND1
AGND2
MF
402 2 DEVELOPMENT DEVELOPMENT DEVELOPMENT
R87081 1
LED8702
1
LED8701
1
LED8700
ENETFW_RESET_L
1.5K GREEN GREEN GREEN
90 1% R8704 PULLDOWN ENABLES 2.0X1.25A 2.0X1.25A 2.0X1.25A
1/16W
3 MF AUTO-MDI/MDIX 2 10/100 2 XMIT 2 LINK
603 2
Q8700 NOSTUFF
40
45
64
54
63
29
32
24
D 84 ENET_MDIO
2N7002 1 C8723
SM
1UF
1 (PLACE Y8700 CRYSTAL CLOSE TO PHY)
25 ENETFW_RESET G S 20%
10V 87 ENET_TMS
2 CERM
87 ENET_CLK25M_XIN
CRITICAL
2 603
R8705 1 RP8702
SHASTA SIGNAL IS ACTIVE HIGH Y8700 1.27K 10K 87 XMIT_LED
25.0000M 1% 5%
1 2 87 ENET_CLK25M_XOUT 1/16W
MF 87 ENET_5221_FDX 2 7
87 ENET_TDI
402
8X4.5MM-SM 2
87 ENET_5221_TESTEN 3 6
C8701 1 1
C8700 87 ENET_5221_LOW_PWR 4 5
27PF
5%
27PF
5%
87 OGND3_JTAG_EN 1 8
50V 50V 1/16W

CERM 2 2 CERM
603 603 SM1
87 OGND3_JTAG_EN
NOTE: LINK SUPPORT FOR GIGABIT ETHERNET PULLED DOWN OR ALIASED TO TEST POINTS HERE.
I228 I232
84 ENET_RXD<4> ENET_RXD_PD 84 ENET_CLK125M_GBE_REF 84 ENET_TXD<4> TP_ENET_TXD<4> 6
87
I229 I233
ENET_RXD<5> 84 ENET_TXD<5> TP_ENET_TXD<5>
ETHERNET PHY
7
84 6
PP3V3_PWRON_ENET MAKE_BASE=TRUE
I230 I234
A ENET_RXD<6> 1 84 ENET_TXD<6> TP_ENET_TXD<6>
84
84 ENET_RXD<7>
I231
R8798
10K
1% 84 ENET_TXD<7>
I235
MAKE_BASE=TRUE
TP_ENET_TXD<7>
6

A
1/16W MAKE_BASE=TRUE
1
C8720 1
C8719 1
C8718 1
C8717 1
C8713 MF I236 LAST_MODIFIED=Mon Dec 13 20:02:41 2004
402 84 ENET_CLK125M_GTX TP_ENET_CLK125M_GTX 6 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
4.7UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
10UF
20% R87991 2 MAKE_BASE=TRUE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
10V 10V 10V 10V 6.3V
2 2 2 2 2 10K
CERM CERM CERM CERM CERM
1206 402 402 402 1206 1% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W
MF II NOT TO REPRODUCE OR COPY IT
402

KEEP ALL CAPS CLOSE TO TRANSCEIVER ON THIS PAGE
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 87 103
8 7 6 5 4 3 2 1 DRAWING
8 7 6 5 4 3 2 1
FW FW FW_DATA<7..0> 88 90
FW FW FW_CTL<1..0> 88 90
FW_LPS FW FW_LPS 88 90
FW_LREQ FW FW_LREQ 88 90
FW_PINT FW FW_PINT 88 90
FW_LCLK FW 15 MIL SPACING FW_CLK98M_LCLK 88 90
FW_PCLK FW 15 MIL SPACING FW_CLK98M_PCLK 88 90
15 MIL SPACING FW_CLK98M_LCLK_R 88
D Page Notes D
- _PP2V5_PWRON_SB
(NONE)
(NONE)
74 25 23 7 =PP2V5_PWRON_SB
1 C8800 1 C8801 1 C8802

0.1uF 0.1uF 0.1uF
20% 20% 20%
2 10V
CERM
10V
2 CERM 2 10V
CERM
402 402 402
C C
N5
J7
A4
FWVDDP
OMIT
U2300
SHASTA
V1.0
BGA
(7 OF 8)
PHY_DATA_0_H N4 FW_DATA<0> 88 90
PHY_DATA_1_H P5 FW_DATA<1> 88 90
FIREWIRE
PHY_DATA_3_H M7 FW_DATA<3> 88 90
PHY_DATA_5_H L1 FW_DATA<5> 88 90
PHY_DATA_6_H M3 FW_DATA<6> 88 90
PHY_DATA_7_H L2 FW_DATA<7> 88 90
PHY_CTL_0_H N2 FW_CTL<0> 88 90
PHY_CTL_1_H N3 FW_CTL<1> 88 90
PHY_LPS_H P6 FW_LPS 88 90
PHY_LREQ_H P1 FW_LREQ 88 90
R8800
P2 PHY_SCLK_H 22
90 88 FW_CLK98M_PCLK PHY_LCLK_H R1 88 FW_CLK98M_LCLK_R 1 2 FW_CLK98M_LCLK 88 90
5%
90 88 FW_PINT P3 PHY_PINT_L PHY_LINKON_L N7 FW_LINKON 90 1/16W
MF
402
B B
Master: Link
Shasta FireWire
A
DRAWING
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP24V_RUN VERTICAL
R9056 FW_VP CONNECTORS
PP3V3_FW 1
1.3 2
90 VOLTAGE=24V
1W
FF
PORT 1
CRITICAL
2512
L9001 514-0202
D9000 CRITICAL
R9002 FERR-160-OHM
J9000
D9001 3 4
MURS320T3
1.3 FL9000
PP24V_FW 1 2 FW_CPS 1 2 FW_CPS_R 1 2 165-OHM FWS22
BAV99DW
D
SM
S
MIN_LINE_WIDTH=35MIL MIN_LINE_WIDTH=35MIL MIN_LINE_WIDTH=35MIL F-ST-TH
SOT-363 NOSTUFF NOSTUFF MIN_NECK_WIDTH=10MIL MIN_NECK_WIDTH=10MIL 20% MIN_NECK_WIDTH=10MIL 1206 SYM_VER-1
5 R90501 Q9050 VOLTAGE=24V SM VOLTAGE=24V 1W

FF
VOLTAGE=24V
1 4
90 6 FW_TPO1P 6
TPO
3.3K C9009
G
D9001 5%
IRF5505 1 2512
90 6 FW_TPO1N
FW_TPA1P 3 BAV99DW 0.1UF 5
1/8W SM R9007
90
SOT-363 FF 1
20%
50V
TPO#
PP3V3_ALL 7 0 2 3
FW_TPI1P
D D9002
4 2
1206 2 11 59
CERM
805
2
1
5%
2 6 FW_VGND
90 6
FW_TPI1N
4
TPI D
FW_TPA1N 6 Q9050_GATE NOSTUFF 1/8W FL9001 90 6
3
90
BAV99DW FF 165-OHM TPI#
SOT-363
1
PP24V_RUN 1
R9055 1206 SM
SYM_VER-1
1
6 FW_VP_PORT1 1
VP
5
NOSTUFF 1K NOSTUFF
NOSTUFF NOSTUFF 5%
Q9053 1
R9021 1 4
F9002
90 FW_TPB1P 3 D9002 DZ9050 3 1
R9051 R9053
1 1/16W
MF NTR4101P 2 390K 0.5AMP
2
VGND
BAV99DW 1N5248B
SOT-363 2K 18K 2 402 SOT-23 5%
1/16W
SM
VOLTAGE=24V
4
2
SOT23
1
5%
1/8W
5%
1/16W Q9053_BASE 1 S
1
R9057 2
MF
402
2 3
7 8 9 10
FF MF G 0 2 MIN_NECK_WIDTH=10MIL
FW_TPB1N D9003 6 2 1206 2 402 5%

1/8W PORT POWER PHY
90
BAV99DW 3 FF C9018 1
SOT-363 NOSTUFF D 2 1206
1
SLEEP OFF ON 0.01UF GND_CHASSIS_FIREWIRE
5 Q9052_BASE 1 Q9052 10%
90 7
PP3V3_PWRON Q9051_COLLECTOR
2N3904 3 RAMP 16V
CERM 2
90 FW_TPA2P 3 D9003 NOSTUFF SM

OFF OFF ON 1
C9024 402
BAV99DW 2 0.01UF
4
SOT-363 NOSTUFF
R9052 3
1
R9054 SLEEP ON ON
10%
50V
2
NOSTUFF 100K 2 CERM
4.7K 2 5% CHOICE A
FW_TPA2N D9004 6
1 Q9051_BASE 1 Q9051 1/16W
MF PP3V3_FW
OFF OFF ON
805
90
BAV99DW 5% 2N3904 90
NEW PS C9010 PORT 2
SOT-363 1/16W SM 2 402 MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL FL9002 100PF
1 MF 2 VOLTAGE=3.3V SLEEP ON ON 165-OHM GND_CHASSIS_FIREWIRE
5 402 CHOICE B * SM
SYM_VER-1
1 2
514-0202
90 7
OFF ON ON CRITICAL
90 FW_TPB2P 3
D9004 1 4 5%
50V
4
BAV99DW
SOT-363
CERM
402 J9001
FWS22
2 2 3
F-ST-TH
VOLTAGE=3.3V
FW_TPB2N 6
MIN_LINE_WIDTH=20MIL 90 6 FW_TPO2P 6
PP3V3_FW 90 FL9003 TPO
165-OHM
1 SM
90 6 FW_TPO2N 5
SYM_VER-1 TPO#
1 4 90 6 FW_TPI2P 4
TPI
C NO STUFF
1 1
C9004
PP1V8_FW_BIAS1
VOLTAGE=1.8V
MIN_LINE_WIDTH=10MIL 90 6 FW_TPI2N 3
TPI#
C
R9098 U9000 PP1V8_FW_BIAS2
MIN_NECK_WIDTH=8MIL
2 3
4.7K 1000pF
FW803 VOLTAGE=1.8V F9000 6 FW_VP_PORT2 1
5%
5%
25V C9027 FLAS MIN_LINE_WIDTH=10MIL 1.5AMP-33V MIN_LINE_WIDTH=35MIL VP
1/16W 2 CERM
30
AVDD0 OMIT DVDD0
1 2
MF 603 27PF
31
AVDD1 17 VGND
402
2 1 2 FW_CLK25M_XIN DVDD1
NOSTUFF 43 26
AVDD2 DVDD2 1
C9015 1
C9016
SM
7 8 9 10
5%
50V
1
CRITICAL
R90601 50
AVDD3 DVDD3
27
0.47UF 0.47UF
8 WATTS MAX
CERM
603
Y9000 0 51
AVDD4 DVDD4
62 20%
10V 1 1
20%
10V 1 1
5% 2 R9015 R9014 2 R9010 R9009
R9022 1
24.576M
SM
1/16W
MF CPS 24 37
CERM
603
CERM
603 24 VOLTS GND_CHASSIS_FIREWIRE
C9028 CPS TPBIAS0 56.2 56.2 56.2 56.2
C9000 C9005
10K
R9061 402 2 1 1
90 7
2 1% 1% 1% 1%
59 42
5%
1/16W
27PF
470 XI TPBIAS1 1/16W
MF
1/16W
MF
1/16W
MF
1/16W
MF
0.01UF 0.01UF
1 2 FW_CLK25M_XOUT_R 1 2 FW_CLK25M_XOUT 60 48 10% 10%
MF
402 XO TPBIAS2 NC
2
402
2
402
2
402
2
402
2
50V
CERM 2
16V
CERM
25 FW_LOWPWR
2 5% 19
5% 1/16W PD 36 90 FW_TPA1P 805 402
NO STUFF 50V MF 28 TPA0+
SE
R9099 CERM
603
402
29
SM
TPA0-
35 90 FW_TPA1N
1
0 2 FW_PHY_RST_L 61 TPB0+
34 90 FW_TPB1P
87 ENETFW_RESET_L RESET 33 90 FW_TPB1N GND_CHASSIS_FIREWIRE
FW_PHY_ISO_L TPB0-
90 7
23
FW_LPS ISO 41 90 FW_TPA2P
90 88
16 TPA1+
RP9000 LPS 40 FW_TPA2N
FW_LREQ 22 1 8 FW_LREQ_R 1 TPA1- 90
C9011
88
LREQ 39 90 FW_TPB2P 100PF
NOTE: 49M, NOT 98M CLK FOR 1394-A 57 TPB1+
PLLVDD 38 90 FW_TPB2N 1 2
NAMING KEPT FROM NEOBORG 88 FW_CLK98M_PCLK 22 1 2 R9001 FW_CLK98M_PCLK_R 63 TPB1-
RP9000 SYSCLK 47
88 FW_CTL<0> 22 2 7 FW_CTL_R<0> 3 TPA2+ NC
5%
RP9000 CTL0 46 50V
88 FW_CTL<1> 22 3 6 FW_CTL_R<1> 4 TPA2- NC
CERM
CTL1 45 402
TPB2+ NC
44
TPB2- NC
FW_DATA<0> 22 4 5 RP9000 FW_DATA_R<0> 5 54 FW_R0

88
RP9001 D0 R0 ELECTRICAL_CONSTRAINT_SET NET_SPACING_TYPE DIFFERENTIAL_PAIR
FW_DATA<1> 22 1 8 FW_DATA_R<1> 6 55 FW_R1
B
88
88 FW_DATA<2> 22
22
2 7 RP9001
RP9001
FW_DATA_R<2> 8
D1
D2
R1
PC2
22
1
R9019
2.49K
FW_TPA1 FW FW_TPA1 FW_TPA1P 90 B
FW_DATA<3> 3 6 FW_DATA_R<3> 9 21 FW_TPA1 FW FW_TPA1 FW_TPA1N
88
RP9001 D3 PC1 1%
1/16W
1
R9018
1
R9016
1
R9013
1
R9011
90
FW_DATA<4> 22 4 5 FW_DATA_R<4> 10 20 FW_TPB1 FW FW_TPB1 FW_TPB1P

88
RP9002 D4 PC0 MF
402 56.2 56.2 56.2 56.2
90
FW_DATA<5> 22 1 8 FW_DATA_R<5> 11 2
FW_TPB1 FW FW_TPB1 FW_TPB1N
88
RP9002 D5 58
1% 1% 1% 1% 90
FW_DATA<6> 22 2 7 FW_DATA_R<6> 12 PLLVSS 1/16W 1/16W 1/16W 1/16W

FW_TPA1 FW FW_TPO1 FW_TPO1P
88
RP9002 D6 MF
402
MF
402
MF
402
MF
402
6 90
FW_DATA<7> 22 3 6 FW_DATA_R<7> 13 18 FW_LINKON 88 2 2 2 2

FW_TPA1 FW FW_TPO1 FW_TPO1N
88
D7 C/LKON 6 90
FW_TPB1 FW FW_TPI1 FW_TPI1P 6 90

15 FW_TPB2 FW_TPB1
NC
CNA FW_TPB1 FW FW_TPI1 FW_TPI1N 6 90
1
2 32 R9020
FW_LPS 88 90 DGND0 AGND0 4.7K
1
1
R9017 1 1
FW_TPA2 FW FW_TPA2 FW_TPA2P 90
14
DGND1 AGND1
49 5% C9021 C9019 R9012
1/16W
220PF
4.99K
220PF
FW_TPA2 FW FW_TPA2 FW_TPA2N 90
NOT USED WITH 1394-A PHY NOSTUFF 25 52 4.99K
R9025 1 C9034 1
R9024 1 R9023 1 DGND2 AGND2 2
MF
402
5%
25V
1%
1/16W
5%
25V 1% FW_TPB2 FW FW_TPB2 FW_TPB2P 90
56 53
1
R9000 510K 0.1UF 1K 10K DGND3 AGND3 2 CERM
402
MF
402
2 CERM
402
1/16W
MF FW_TPB2 FW FW_TPB2 FW_TPB2N 90
FW_CLK98M_LCLK TP_FW_CLK98M_LCLK 20% 64 2
2K
88
MAKE_BASE=TRUE
6 5%
1/16W
10V
CERM 2
5%
1/16W
5%
1/16W DGND4 2
402
FW_TPA2 FW FW_TPO2 FW_TPO2P 6 90
5% MF 402 MF MF
1/16W 402
2
402
2
402
2
FW_TPA2 FW FW_TPO2 FW_TPO2N 6 90
MF
402 FW_TPB2 FW FW_TPI2 FW_TPI2P 6 90
2
88 FW_PINT
FW_TPB2 FW FW_TPI2 FW_TPI2N 6 90
PW_LOWPWR SHOULD BE
1
R9026 LREQ PULL-DOWN
ENSURES SIGNAL
PULLED DOWN ON SB
FW_XTAL 15 MIL SPACING X_TAL_IN
10K LOW WHEN LUCENT
5% PHY POWERS UP 15 MIL SPACING X_TAL_OUT
1/16W
MF
2 402
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM
338S0088 1 FIREWIRE PHY 802A U9000 CRITICAL

FIREWIRE PHY
A PP3V3_FW 90 NOTICE OF PROPRIETARY PROPERTY
A
DVDD BYPASS
AVDD BYPASS
1
C9006 1
C9035 1
C9033 1
C9032 1
C9031 1
C9030 1
C9029 1
C9007 1
C9008 1
C9026 1
C9025 1
C9023 1
C9022 1
C9002 1
C9001 II NOT TO REPRODUCE OR COPY IT
10UF 0.1UF 0.1UF 0.1UF 0.001UF 0.001UF 0.001UF 10UF 10UF 0.1UF 0.1UF 0.1UF 0.001UF 0.001UF 0.001UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 10V 10V 10V 50V 50V 50V 6.3V 6.3V 10V 10V 10V 50V 50V 50V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
1206 402 402 402 402 402 402 1206 1206 402 402 402 402 402 402 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 90 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB2_0 USB2 USB2 USB2_0 USB2_P<0> 91 92
USB2_0 USB2 USB2 USB2_0 USB2_N<0> 91 92
D USB2_4 USB2 USB2 USB2_4 USB2_P<4> 91 92 D

USB2_NEC_XTAL 15 MIL SPACING NEC_CLK30M_XT1

NEC_CLK30M_XT2
91
L9135 PP3V3_PWRON_NEC_AVDD
15 MIL SPACING 91
91 7 =PP3V3_PWRON_USB FERR-EMI-100-OHM VOLTAGE=3.3V
15 MIL SPACING NEC_CLK30M_XT2_R 91
1 2 MIN_NECK_WIDTH=10 mil
SM
Page Notes R9135

1
4.7 2
C9135
10uF
20%
6.3V
CERM
C9136
0.1uF
20%
10V
CERM 2
1 C9137
0.1uF
20%
10V
CERM 2
1
Power aliases required by this page: 5% 805 402 402

- _PP3V3_PWRON_USB 1/16W
MF
603
(NONE)
P12
A13
A12
L13
J13
H13
F13
D13
G12
N10
N12
BOM options provided by this page: C9120 1 C9121 1 C9122 1 C9123 1 C9124 1 C9125 1
P2
P3
A3
E2
N8
H4
D7
(NONE) 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VDD
R9100
20%
6.3V 2
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V 1
36 2
CERM CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
AVDD
Net Spacing Type: USB2 805 402 402 402 402 402 1%
1/16W
RSDM1 M14 USB_NEC_N<0> MF
Line To Line: 19.5 mils 402
DM1 M13 (USB2_N<0>) USB2_N<0> 91 92
Length Tolerance: 50 mils
DP1 L14 (USB2_P<0>) USB2_P<0>
Primary Max Sep: 7.5 mils C9126 1 C9127 1 C9128 1 C9129 1 C9130 1
RSDP1 K13 USB_NEC_P<0>
91 92
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Secondary Max Sep: 100 mils 20%
10V
20%
10V
20%
10V
20%
10V
20%
10V CRITICAL R9101
Secondary Length: 500 mils CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 36
NOTE: Target differential impedance for
402 402 402 402 402 U7700 1
1%
2
USB2 data pairs is 90 ohms.

NEC_uPD720101_USB2 1/16W
MF
C FBGA 402
C
R9102
1
36 2
91 7 =PP3V3_PWRON_USB
1%
1/16W
RSDM2 K14 USB_NEC_N<1> MF
402
DM2 K12 (USB2_N<1>) USB2_N<1> 91 92
8 7 6 5 J14
DP2 (USB2_P<1>) USB2_P<1> 91 92
U2300 R91102 RP9110 RSDP2 J12 USB_NEC_P<1>
SHASTA 10K 10K R9103
5%
V1.0 1/16W 5%
1/16W 1
36 2
MF SM1
BGA 402 1
1%
(8 OF 8) 1 2 3 4 1/16W
OMIT NC0 P7 TP_SB_NC_P7 6 MF
402
NC1 P8 TP_SB_NC_P8 6 92 USB2_OC<0> (USB2_OC<0>) B12 OCI1
NC2 R3 TP_SB_NC_R3 6 92 USB2_OC<1> (USB2_OC<1>) B11 OCI2

R9104
1
36 2
NC4 R5 TP_SB_NC_R5 6 94 USB2_OC<3> (USB2_OC<3>) A10 OCI4
1%
H11
1/16W
RSDM3 USB_NEC_N<2> MF
NC6 R7 TP_SB_NC_R7 6 402
DM3 G11 (USB2_N<2>) USB2_N<2> 91 92
NC7 R8 TP_SB_NC_R8 6 92 USB2_PWREN<0> C12 PPON1
DP3 G13 (USB2_P<2>) USB2_P<2> 91 92
NC8 T1 TP_SB_NC_T1 6 92 USB2_PWREN<1> A11 PPON2
RSDP3 G14 USB_NEC_P<2>
NC9 T2 TP_SB_NC_T2 6 92 USB2_PWREN<2> C11 PPON3
R9105
NC10 T3 TP_SB_NC_T3 6 92 USB2_PWREN<3> C10 PPON4 36
1 2
NC11 T4 TP_SB_NC_T4 6 92 USB2_PWREN<4> A9 PPON5
1%
NC12 T5 TP_SB_NC_T5 6 1/16W
MF
NC13 T6 TP_SB_NC_T6 6 402
NC14 T7 TP_SB_NC_T7
B NC15 T8 TP_SB_NC_T8
6
6
R9106
36
B
NC16 U1 TP_SB_NC_U1 6 1 2
NC17 U2 TP_SB_NC_U2 6 1%
1/16W
NC18 U3 TP_SB_NC_U3 6 RSDM4 F12 USB_NEC_N<3> MF
402
NC19 U4 TP_SB_NC_U4 6 91 7 =PP3V3_PWRON_USB DM4 F14 (USB2_N<3>) USB2_N<3> 91 94
NC20 U5 TP_SB_NC_U5 6 DP4 E12 (USB2_P<3>) USB2_P<3> 91 94
NC21 U6 TP_SB_NC_U6 6 RSDP4 E14 USB_NEC_P<3>

NC22 V1 TP_SB_NC_V1 6 R91401 R9141
1 R9107
36
NC23 V2 TP_SB_NC_V2 6 1.5K 1.5K 1 2
5% 5%
NC24 V3 TP_SB_NC_V3 6 1/16W 1/16W 1%
MF MF 1/16W
NC25 V4 TP_SB_NC_V4 6 402 2 2 402
MF
402
NC26 W1 TP_SB_NC_W1 6
P6 NC1
NEC_NC1_PU
NC27 W3 TP_SB_NC_W3 6
M6 NC2 R9108
NEC_NC2_PU
NC28 Y1 TP_SB_NC_Y1 6
1
36 2
NC29 Y3 TP_SB_NC_Y3 6
1%
1/16W
RSDM5 E13 USB_NEC_N<4> MF
402
DM5 D14 (USB2_N<4>) USB2_N<4> 91 92
DP5 C13 (USB2_P<4>) USB2_P<4> 91 92
L9 XT1/SCLK RSDP5 C14 USB_NEC_P<4>

91 NEC_CLK30M_XT1 R9109
91 NEC_CLK30M_XT2_R P8 XT2
1
36 2
1%
Master: Fizzy
R9145
2 1/16W
MF
100 402
5%
1/16W
MF RREF P11 NEC_RREF_PD
USB Host Interfaces
A CRITICAL 1 402
A
AVSS(R)
Y9145
30.0000M NEC_CLK30M_XT2 91 R91381 NOTICE OF PROPRIETARY PROPERTY
1 2 9.09K
VSS AVSS 1% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
P10
N14
H14
B14
N13
B13
M11
L12
H12
D12
J11
F11
P13
M12
N11
8X4.5MM-SM
B1
N1
A2
B2
N2
G4
D8
MF AGREES TO THE FOLLOWING
C9145 1 1 C9146 R9139 402 2
22pF 22pF 0 Tie to GND at ball N11
5% 5% 2 1 II NOT TO REPRODUCE OR COPY IT
50V 2 50V
CERM 2 CERM 5% GND_NEC_AVSS_R
402 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W VOLTAGE=0V
MF MIN_LINE_WIDTH=20 mil
603 MIN_NECK_WIDTH=10 mil SIZE DRAWING NUMBER REV.
DRAWING
Y9145 LOAD CAPACITANCE IS 16pF
APPLE COMPUTER INC.
D 051-6482 I
SCALE SHT OF

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROVIDED USB2 USB2_PORT1_F USB2_PORT1_P_F 6 92
BY USB2 USB2_PORT1_F USB2_PORT1_N_F 6 92
USB USB2 USB2_PORT2_F USB2_PORT2_P_F 6 92
CONTROLLER USB2 USB2_PORT2_F USB2_PORT2_N_F 6 92
I526 USB2 USB2_PORT3_F USB2_PORT3_P_F 6 92
I527 USB2 USB2_PORT3_F USB2_PORT3_N_F 6 92
External USB Ports

D D
Page Notes L9210
FERR-250-OHM
Power aliases required by this page: PP5V_USB2 1 2 6 PP5V_USB2_PORT1_F
59
- _PP5V_PWRON_USB VOLTAGE=5V SM VOLTAGE=5V
MIN_LINE_WIDTH=25MIL NOSTUFF NOSTUFF MIN_LINE_WIDTH=25MIL
- _PP5V_PWRON_UDASH MIN_NECK_WIDTH=10MIL
- _PP3V3_PWRON_UDASH
1
C9210 1 C9211MIN_NECK_WIDTH=10MIL
150uF 10uF
- _PP3V3_PWRON_BT L9211 20%
2 6.3V
10%
2 16V
FERR-250-OHM POLY X5R
1210
Signal aliases required by this page: 1 2
SMD
(NONE) SM
NOTE: This page is expected to contain the
necessary aliases to map the
GND_USB2_PORT1
VOLTAGE=0V
C9212 1 C9213 1 CRITICAL
MIN_LINE_WIDTH=25MIL 0.01uF 0.01uF
USB pairs to their appropriate MIN_NECK_WIDTH=20MIL 20%
16V
20%
16V J9210
destinations and/or to properly CERM 2 CERM 2 USB-UAS25
402 402 F-ST-TH
terminate unused signals. L9212 5
PORT 1
165-OHM
SM 6
BOM options provided by this page: SYM_VER-1
(NONE) 91 USB2_N<0> USB2_PORT1_N 1 4

ALIAS 1
MAKE_BASE=TRUE VDD
NOTE: USB pairs are NOT constrained on 92 6 USB2_PORT1_N_F D- 2
this page. It is assumed that the 91 USB2_P<0> USB2_PORT1_P 2 3 92 6 USB2_PORT1_P_F D+ 3

ALIAS
MAKE_BASE=TRUE 4
USB Host Controller page will GND
provide the appropriate constraints R9210 1
R9211
1 NO STUFF NO STUFF
to apply to entire USB D+/D- XNets. 15K
5% 5%
15K C9214 1 1 C9215 7
1/16W 1/16W 33pF 33pF

MF MF 5% 5%
50V 50V
514-0199
neoBorg Implementation 402 2 2 402 CERM 2 2 CERM
C
C NOTE: This design does not provide power
402 402
GND_CHASSIS_USB 7 92
control on USB ports 2-4. Rename
USB controller outputs to indicate
single-pin connections. MIN_LINE_WIDTH=25MIL
L9220
91 USB2_PWREN<0> TP_USB2_PWREN<0> 6
FERR-250-OHM VOLTAGE=0
ALIAS
MAKE_BASE=TRUE 1 2 6 PP5V_USB2_PORT2_F
91 USB2_PWREN<1> ALIAS TP_USB2_PWREN<1> 6 VOLTAGE=5V
MAKE_BASE=TRUE SM NOSTUFF NOSTUFF MIN_LINE_WIDTH=25MIL
91 USB2_PWREN<2> ALIAS TP_USB2_PWREN<2>
MAKE_BASE=TRUE
6 1
C9220 1 C9221MIN_NECK_WIDTH=10MIL
150uF 10uF
91 USB2_PWREN<3> ALIAS TP_USB2_PWREN<3>
MAKE_BASE=TRUE
6 L9221 20%
2 6.3V
10%
2 16V
FERR-250-OHM POLY X5R
USB2_PWREN<4> TP_USB2_PWREN<4> 6 SMD 1210
91 ALIAS
MAKE_BASE=TRUE 1 2
SM
GND_USB2_PORT2
VOLTAGE=0V
C9222 1 C9223 1 CRITICAL
MIN_LINE_WIDTH=25MIL 0.01uF 0.01uF
16V
20%
16V J9220
CERM 2 CERM 2 USB-UAS25
402 402 F-ST-TH
L9222 5
PORT 2
165-OHM
SM 6
SYM_VER-1
91 USB2_N<1> USB2_PORT2_N 1 4
ALIAS
MAKE_BASE=TRUE
92 6 USB2_PORT2_N_F
VDD
D-
1
2 Q37 BlueTooth Connector
USB2_P<1> USB2_PORT2_P 2 3 USB2_PORT2_P_F D+ 3 SDF9200
91 ALIAS
MAKE_BASE=TRUE
92 6
4
STDOFF-197OD-283H-TH
GND
1
R92201 R9221
1 NO STUFF NO STUFF
_PP3V3_PWRON_BT
15K 15K C9224 1 1 C9225 7 7
B 5%
1/16W
MF
5%
1/16W
MF
33pF
5%
50V
5%
33pF
50V
91 USB2_OC<4> ALIAS
CRITICAL
J9240
B
402 2 2 402 CERM 2 2 CERM 514-0199
402 402 C9240 1 C9241 1 53353
M-ST-SM
10uF 0.1uF
20% 20% 1 2 NC
GND_CHASSIS_USB 6.3V 10V
7 92 CERM 2 CERM 2 3 4
805 402 NC
USB2_N<4> USB_BT_N 5 6 NC
F9200 L9230 91
USB2_P<4>
ALIAS 6
MAKE_BASE=TRUE
USB_BT_P 7 8 NC
2AMP-6V FERR-250-OHM 91 ALIAS
6
MAKE_BASE=TRUE 9 10 NC
7 _PP5V_PWRON_USB 1 2 1 2 PP5V_USB2_PORT3_F
6
SM NOSTUFF
VOLTAGE=5V
NOSTUFF MIN_LINE_WIDTH=25MIL R9240 1 1
R9241
SM-1 MIN_NECK_WIDTH=10MIL 15K 15K 516S0097
1
C9230 1 C9231 5%
1/16W
5%
1/16W
150uF 10uF
1
R9200 L9231 20%
2 6.3V
10%
16V
MF
402 2
MF
2 402 SDF9201
160 FERR-250-OHM POLY
2 X5R STDOFF-197OD-283H-TH
5% SMD 1210
1/16W 1 2 1
MF
SM
2 603
USB2_OC<0> USB_OC
GND_USB2_PORT3
VOLTAGE=0V
C9232 1 C9233 1
CRITICAL
91 ALIAS
MAKE_BASE=TRUE MIN_LINE_WIDTH=25MIL 0.01uF 0.01uF
USB2_OC<1>
16V
20%
16V J9230
91
CERM 2 CERM 2 USB-UAS25
ALIAS 1
R9201 402 402 F-ST-TH
91 USB2_OC<2> ALIAS 300 L9232 5
PORT 3
5% 6
1/16W 165-OHM
MF SM
2 603
SYM_VER-1
91 USB2_P<2> USB2_PORT3_P 1 4 92 6 USB2_PORT3_P_F VDD 1

ALIAS
MAKE_BASE=TRUE 2
92 6 USB2_PORT3_N_F D-
91 USB2_N<2> ALIAS USB2_PORT3_N

MAKE_BASE=TRUE
2 3 D+
GND
3
4 USB Device Interfaces
A R9230
15K
1
R9231
1
15K
NO STUFF
C9234 1 1
NO STUFF
C9235 7 NOTICE OF PROPRIETARY PROPERTY
A
5% 5% 33pF 33pF
1/16W 1/16W 5% 5%
MF MF 50V 50V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402 2 2 402 CERM 2 2 CERM 514-0199 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 402 AGREES TO THE FOLLOWING
GND_CHASSIS_USB 7 92 II NOT TO REPRODUCE OR COPY IT
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 92 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- _PP3V3_PWRON_MODEM
Spec Load: 0.5 A active, 3 mA auxiliary
(NONE)
(NONE)
D D
SOFT MODEM IS PLAN OF RECORD
MICRODASH MODEM CONNECTOR LEFT ON FOR DEVELOPMENT PURPOSES ONLY
Q52 Modem Connector MicroDash Modem Connector NOSTUFF

SDF9400 SDF9402
STDOFF-4MM-9MMH-TH STDOFF-4MM-9MMH-TH
1 1
CRITICAL
USB2_OC<3>
J9401 91 ALIAS
C104A-H9.0 7 _PP3V3_PWRON_UDASH
NC 35 F-ST-SM
DEVELOPMENT
NC 31 32 NC DEVELOPMENT DEVELOPMENT NOSTUFF DEVELOPMENT
C9400 1 C9401 1 R94002 R9401
1
DEVELOPMENT R9402
1
4.7uF 0.1uF 10K 10K 10K
_PP3V3_PWRON_MODEM NC 1 2 NC 20% 20% 5% 5% 5%
94 7
3 4 NC
_PP3V3_PWRON_MODEM 7 94
10V
CERM 2
10V
CERM 2 1/16W
MF
1/16W
MF
J9400 1/16W
MF
1206 402
402 1 5047
2 402 2 402
1 C9450 1 C9451 NC 5 6 MODEM_RING2SYS_L 6 25 94
1
R9451 F-ST-SM
10UF 0.1UF NC 7 8 10K (+3.3V) 1 2 (+3.3V)

20% 20% 5% 4
NC 9 10 NC 1/16W (GND) 3 (RST*) UDASH_RESET_L 6 25
6.3V 10V
2 CERM 2 CERM 11 12 NC MF 5 6
NC 25 6 UDASH_SDOWN (SDOWN) (RTS*) I2S1_MCLK
805 402 2 402 Default to Modem On
6 25 76 94
NC 13 14 MODEM_FC_RGDT (GND) 7 8 (DTR*) I2S1_RESET_L 6 25 94

15 16 NC 94 76 25 6 I2S1_DEV_TO_SB_DTI (RXD) 9 10 (GND)
17 18 NC 94 25 6 I2S1_SYNC (GPIO*) 11 12 (TXD*) I2S1_SB_TO_DEV_DTO 6 25 76 94
C NC 21
19 20
22 I2S1_SYNC 6 25 94 94 25 6 MODEM_RING2SYS_L
(GND)
(RING*)
13
15
14
16
(TRXC)
(GND)
I2S1_BITCLK 6 25 94 C
23 24 MODEM_RING2SYS_L SHOULD BE PULLED UP ON SB 18
94 76 25 6 I2S1_SB_TO_DEV_DTO I2S1_DEV_TO_SB_DTI 6 25 76 94 (HOOK) NC 17 (D-) 6 USB_UDASH_N ALIAS USB2_N<3> 91
94 25 6 I2S1_RESET_L (GND) (D+) 6 USB_UDASH_P ALIAS USB2_P<3> 91
18 6 I2C_UDASH_SCL (SCL) (GND)
94 76 25 6 I2S1_MCLK 29 30 I2S1_BITCLK 6 25 94 (GND) 23 24 (SDA) I2C_UDASH_SDA 6 18
(A0) 25 26 (A1) UDASH_I2C_A1_PU 6 R94041 1

R9403
(SNDIN) NC 27 28 (+5V)
_PP5V_PWRON_UDASH
15K 15K
NC 33 34 NC
30 7 5% 5%
(SNDOUT) NC 29 (+5V) 1/16W 1/16W
NC 36 MF MF
402 2 2 402
516S0116 516S0121
DEVELOPMENT DEVELOPMENT
1 C9402 1 C9403
0.1uF 10uF
20% 20%
SDF9401 2 10V
CERM 2 6.3V
CERM
STDOFF-4MM-9MMH-TH 402 1206
GND_CHASSIS_MODEM 1
RJ11 CONNECTOR
STUFFED AT FATP
SYMBOL USED FOR PLACEMENT
B OMIT
B
J9402
RJ11-HGT27.5
ST-TH
1
2
514-0205
From Intel Mobile Audio/Modem

Daughter Card Specification
Rev 1.0, February 22, 1999
1 - MONO_OUT/PC_BEEP 2 - AUDIO_PWRON
3 - GND 4 - MONO_PHONE
5 - AUXA_RIGHT 6 - RESERVED
7 - AUXA_LEFT 8 - GND
9 - CD_GND 10 - 5Vmain
11 - CD_RIGHT 12 - RESERVED
13 - CD_LEFT 14 - RESERVED
15 - GND 16 - PRIMARY_DN
17 - 3.3Vaux 18 - 5Vd
19 - GND 20 - GND
21 - 3.3Vmain 22 - AC97_SYNC
23 - AC97_SDATA_OUT 24 - AC97_SDATA_INB
25 - AC97_RESET# 26 - AC97_SDATA_INA Modem Interface
A 27
29
-
-
GND
AC97_MSTRCLK
28
30
-
-
GND
AC97_BITCLK
A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 94 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
AUDIO CODEC
APPLE P/N 353S0655
L9500 MIN_NECK_WIDTH=8MIL
VOLTAGE=3.3V
1000-OHM-200MA
103 102 101 100 7 PP3V3_AUDIO 1 2 PPV_3V3_AUDIO_CODEC PP4V5_AUDIO_ANALOG 96 102
0603
PLACE AT U9500
C9500 1
1 C9501 1 C9502 1 C9503
1UF 1UF 1UF
10UF 10% 10% 10%
R9503
1 20% 2 10V 2 10V 2 10V
1K
6.3V
CERM 2
805
U9500 CERM
805
CERM
805
CERM
805 GND_AUDIO_CODEC 95 96 98 102
16
23
31
1% CRITICAL
7
1/16W
MF VCC
VDD
2 402
PCM3052
I2S0_BITCLK_DELAYED 11 VQFN 2
102 NET_SPACING_TYPE=AUDIO BCK VINL AUD_CODEC_IN_L 96
103 25 I2S0_SYNC 10 LRCK VINR 6 AUD_CODEC_IN_R 96
C AUDI2S0OUT
AUDSPDIFOUT
13
14
DOUT
DOUTS
VOUTL
VOUTR
25
24
AUD_CODEC_OUT_L
AUD_CODEC_OUT_R
98 100
98 100
C
103 25 I2S0_SB_TO_DEV_DTO NET_SPACING_TYPE=AUDIO 12 DIN
VCOM 26 AUD_PCM_VCOM 100
21 I2CEN VREF1 4 AUD_PCM_REF1

NC 20 ADR VREF2 5 AUD_PCM_REF2
103 18 I2C_AUDIO_SCL 19 SCL VREFS 3 AUD_CODEC_LI_SHDN_L 96
103 18 I2C_AUDIO_SDA 18 SDA REFO 32 AUD_PSEUDO_VREF 96
25 I2S0_RESET_L 9 PDWN* MBIAS 27 AUD_PCM_MBIAS 102

MINM 28 AUD_MICIN_N 102
103 102 AUD_CODEC_MCLK NET_SPACING_TYPE=AUDIO 17 SCKI
MINP 29 AUD_MICIN_P 102
R9500 NC 1 ATEST
33
25 I2S0_DEV_TO_SB_DTI NET_SPACING_TYPE=AUDIO 1 2
DGND AGND
1 C9504 1
C9506 1
C9508 1
C9510 1
C9512
5% 0.1UF 10UF 10UF 10UF 10UF
15
8
22
30
NOSTUFF 1/16W 10% 20% 20% 20% 20%
R9501
1 MF 2 16V 2 16V 2 16V 2 16V 2 16V
C9513 1
47K
402 X7R
603
ELEC
SM
ELEC
SM
ELEC
SM
ELEC
SM
4.7PF 5%
+/-0.25PF 1/16W
50V
C0G 2 MF
402 2 402 R9502 C9505 1 C9507 1 C9509 1 C9511 1
AUD_SPDIF_OUT 1
33 2 0.1UF 0.1UF 0.1UF 0.1UF
103 101 NET_SPACING_TYPE=AUDIO 10% 10% 10% 10%
5% 16V 16V 16V 16V
1/16W X7R 2 X7R 2 X7R 2 X7R 2
MF 603 603 603 603
402
102 98 96 95 GND_AUDIO_CODEC
B B
AUDIO: CODEC
A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 95 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LINE IN PSEUDO-DIFFERENTIAL AMP

AV= 0.49
D D
NOSTUFF
C9603
47PF
102 96 95 PP4V5_AUDIO_ANALOG 1 2
5%
50V
CERM
402
C9600 R9604 R9607
10UF
2 1
20.5K2 10K
101 AUD_LI_L AUD_LI_L1 1 AUD_LI_L2 1 2
1% 1%
20% 1/16W 1/16W
16V MF MF
ELEC 402 CRITICAL 402
SM
D9600 10
U9600
1
R9603 C9602 1 BAV99DW
SOT-363
2
V+
MAX4253
100K 0.47UF UMAX
R9602 1
1% 20%
10V
2 1 AUD_CODEC_IN_L 95
47K 1/16W CERM 2
5% MF 603 6 3 5
1/16W 2 402 V-
MF
402 2 1
4 APPLE P/N 353S0642
C9601 R9605
10UF
2 1
20.5K2
101 96 AUD_LI_GND AUD_LI_GNDL1 1 AUD_LI_VREFL
1%
20% 1/16W
R9600
1 16V
ELEC
MF
402
165 SM
1%
C 1/16W
MF
2 402 R9606
C
10K
96 95 AUD_PSEUDO_VREF 1 2
1%
1/16W
MF
402
NOSTUFF
R9601
AUD_CODEC_LI_SHDN_L 1
0 2 AUD_CODEC_LI_SHDN_L1
95
5%
1/16W
MF
402
NOSTUFF
C9606
47PF
102 96 95 PP4V5_AUDIO_ANALOG 1 2
5%
50V
CERM
402
C9604 R9609 R9612
10UF
2 1 20.5K2 10K
101 AUD_LI_R AUD_LI_R1 1 AUD_LI_R2 1 2
1% 1%
20% 1/16W 1/16W
16V MF MF
ELEC 402 CRITICAL 402
SM
D9600 10
U9600
R9608
1 BAV99DW 8 MAX4253
B 1%
100K 5
SOT-363 V+ UMAX
9 AUD_CODEC_IN_R 95
B
1/16W
MF 3 7 6
2 402 V-
4
4 APPLE P/N 353S0642
C9605 R9610
10UF 20.5K2
101 96 AUD_LI_GND 2 1 AUD_LI_GNDR1 1 AUD_LI_VREFR
1%
20% 1/16W
16V MF
ELEC 402
SM
R9611
AUD_PSEUDO_VREF 1
10K 2
96 95
1%
1/16W
MF
402
AUDIO: LINE INPUT AMP

A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 96 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LINE OUT LOW-PASS FILTER

FC = 37 KHZ, HO = -1.4
R9801
1
14K 2
1%
1/16W
MF
402
D C9800 R9800 R9802 C9801 D

10UF 270PF
1 2
10K 3.92K2 1 2
100 95 AUD_CODEC_OUT_L AUDCODECOUTL 1 2 AUDCODECOUTL1 1 AUD_LOAMP_OUT_L 98
1% 1%
20% 1/16W 1/16W 5%
16V MF MF 50V
ELEC 402 402 CERM
SM-1 603
AUD_LOAMP_IN_L_M 98
CRITICAL
1 C9802
1.5NF
5%
25V
2 CERM
0603
R9803
AUD_LO_GND_PRB 1
14K 2 AUD_LOAMP_IN_L_P
101 98
1%
1/16W
MF R9804
1
402 10K
1%
1/16W
MF
2 402 LINE OUT
GROUND NOISE
CANCELLATION
R9805
1
10K
1%
1/16W
MF
102 98 96 95 GND_AUDIO_CODEC R9806 2 402
1
14K 2 AUD_LOAMP_IN_R_P 98
CRITICAL 1%
C 1 C9804
1.5NF
1/16W
MF
402
C
5% AUD_LOAMP_IN_R_M 98
25V
2 CERM
0603
C9803 R9807 R9808 C9805

10UF 270PF
1 2 10K 3.92K2 1 2
100 95 AUD_CODEC_OUT_R AUDCODECOUTR 1 2 AUDCODECOUTR1 1 AUD_LOAMP_OUT_R 98
1% 1%
20% 1/16W 1/16W 5%
16V MF MF 50V
ELEC 402 402 CERM
SM-1 603
R9809
1
14K 2
1%
1/16W
MF
402
LINE OUT AMP

APPLE P/N 353S0687
R9810 VOLTAGE=5V
PP5V_AUDIO_ANALOG 1
4.7 2
PP5V_AUDIO_LOAMP
102
5%
1/10W
MF
603
1
C9806
10UF
B 20%
2 16V
ELEC
B
SM
C9807 1 GND_AUD_LOAMP_CHGPMP 98 102
10UF
20% CRITICAL
6.3V AUD_LOAMP_OUT_L
CERM 2 98
805 U9800 R9811
13
GND_AUD_LOAMP_CHGPMP 14
1
102 98 9
1 2 AUD_LO_L
PVDD
VDDR
VDDL
101
MIN_LINE_WIDTH=20MIL 1% MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL 1/10W MIN_NECK_WIDTH=10MIL
FF
805
98 AUD_LOAMP_IN_L_M 14 LIN- LOUT 12
98 AUD_LOAMP_IN_L_P LIN+ MIN_NECK_WIDTH=10MIL
MAX9722 MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL R9812
8 QFN 14
98 AUD_LOAMP_IN_R_M RIN- ROUT 10 1 2 AUD_LO_R 101
98 AUD_LOAMP_IN_R_P 7 RIN+ 1%
AUD_MAX9722_C1P 1/10W
C1P 2 FF
805
TO SHASTA GPIO R9816 16 SHDN* C1N 4 1 C9808 1 C9809 AUD_LOAMP_OUT_R 98
1K AUDIO_LO_MUTE_L_F
PGND
SGND
PVSS
AUDIO_LO_MUTE_L 1 2 NC 17 1UF 1UF

VSS
25
10% 10%
5% 10V 10V
2 CERM 2 CERM
1/16W
805 805
R98151 MF
3
11
4.7K C9812 1 402 C9813 1

AUD_MAX9722_C1N MIN_LINE_WIDTH=20MIL
5% 100PF 100PF R9817
1
R9818
1/16W 5% 5%
50V 50V 1K 1K
MF
402 2 CERM 2
402
CERM 2
402 1% 1% R9813
1/16W 1/16W
1
0 2 AUD_LO_GND 101
MF MF
2 402 2 402 5%
1/10W
AUDIO: LINE OUT AMP
MIN_LINE_WIDTH=12MIL FF
A 102 98 96 95 GND_AUDIO_CODEC MIN_NECK_WIDTH=8MIL

AUD_MAX9722_PVSS
805

A
C9810 1 2
C9811 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1UF 20%
10UF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
10%
10V 1 16V
CERM 2 ELEC I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND_AUD_LOAMP_CHGPMP 805 SM
R9814 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
0
102 GND_AUD_LOAMP 1 2
5%
1/10W
FF
805
D 051-6482 I
APPLE COMPUTER INC.
SCALE SHT OF
NONE 98 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
NET_SPACING_TYPE=AUDIO
SPEAKER AMP
FA000 MIN_NECK_WIDTH=10MIL
VOLTAGE=12V
VOLTAGE=12V LA000 MIN_NECK_WIDTH=10MIL
VOLTAGE=12V APPLE P/N 353S0680
VOLTAGE=12V 1.5A-24V XWA000
SM OMIT
FERR-250-OHM
SM
PP12V_AUDIO_SPKRAMP_F PP12V_AUDIO_SPKRAMP_F2 PP12V_AUD_SPKRAMP_PLANE
D 7 PP12V_AUDIO_SPKRAMP 1 2 1 2 1
SM-1
2
D
XWA003
SM OMIT CA017 1
CA000 1 CA001 1 CA018 1 1 CA002 1 CA019 1 CA003 1 CA023
1 2 220UF 10UF 0.1UF 1UF 0.1UF 10UF 10UF
20% 220UF 10% 20% 20% 20% 10% 10%
16V 2 20%
ELEC 16V 2 16V 16V 16V 16V 16V 16V
SM-2 ELEC CERM 2 CERM 2 2 CERM 2 CERM 2 CERM 2 CERM
SM-2 1210 603 1206 603 1210 1210
GND_AUDIO_SPKRAMP_PLANE
MIN_NECK_WIDTH=8MIL
102 100
GND_AUDIO_SPKRAMP_PLANE
AUD_MAX9714_CHOLD
100 102
LA005 CA004 PP3V3_AUDIO_SPKR 100

1000-OHM-200MA 0.47UF
98 95 AUD_CODEC_OUT_L 1 2 AUDSAMPINLN 1 2
0603
1
RA014
10%
16V 10K NOSTUFF NET_SPACING_TYPE=AUDIO
1 CA015 X7R
805
1%
1/16W NET_SPACING_TYPE=AUDIO
LA001 MIN_NECK_WIDTH=10MIL
100PF MF 180-OHM-1.5A
21
22
5% 2 402 MIN_NECK_WIDTH=10MIL
3
4
LA006 2 50V
CERM CA005 AUDSAMPOUTLP 1 2 AUD_SPKR_OUTL_P 101
1000-OHM-200MA 402
0.47UF VDD CHOLD 7 0603
AUD_SAMP_INL_N 9 INL-
1 2 AUDSAMPINLP 1 2 NOSTUFF NET_SPACING_TYPE=AUDIO
OUTL+ 31 MIN_LINE_WIDTH=20MIL
0603
10% AUD_SAMP_INL_P 10 INL+ OUTL+ 32
16V MIN_NECK_WIDTH=10MIL
180-OHM-1.5A
X7R
95 AUD_PCM_VCOM 805 OUTL- 29 AUDSAMPOUTLN 1 2 AUD_SPKR_OUTL_N 101
AUD_SAMP_INR_P 16 INR+
LA007 CA006 OUTL- 30 MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
0603
1000-OHM-200MA 0.47UF
1 2 AUDSAMPINRP 1 2
AUD_SAMP_INR_N 15 INR- U9700 C1+ 6 AUDSAMPCPP LA011
800-OHM
0603 AUD_SAMP_G1 17 G1 MAX9714 MIN_LINE_WIDTH=8MIL
1 CA008 ACM4532
SYM_VER-1
10% 100
QFN MIN_NECK_WIDTH=6MIL 0.1UF
16V 100 AUD_SAMP_G2 18 G2 10% 1 4
50V
X7R C1- 5 AUDSAMPCPN 2 X7R
CA016 C
C
1 805 NOSTUFF NET_SPACING_TYPE=AUDIO
AUD_SAMP_FS1 19 FS1 603
5%
100PF 100
100 AUD_SAMP_FS2 20 FS2 OUTR+ 27 NET_SPACING_TYPE=AUDIO LA003 2 3 MIN_NECK_WIDTH=10MIL

50V
OUTR+ 28
180-OHM-1.5A
LA008 2 CERM
402 CA007 AUD_SAMP_SHDN_L 11 AUDSAMPOURTP 1 2 AUD_SPKR_OUTR_P
1000-OHM-200MA 0.47UF
SHDN*
OUTR- 25
101
0603
98 95 AUD_CODEC_OUT_R 1 2 AUDSAMPINRN 1 2 NC 8 NC OUTR- 26
0603
NOSTUFF
RA015 10%
16V
AUD_MAX9714_VREG 14 REG
SS 12
LA004 MIN_LINE_WIDTH=20MIL
10K X7R MIN_LINE_WIDTH=8MIL THM PGND MIN_NECK_WIDTH=10MIL
180-OHM-1.5A
100 PP3V3_AUDIO_SPKR 1 2 AUDIO_SPKR_MUTE_L_INV 805 MIN_NECK_WIDTH=6MIL AGND PAD
AUDSAMPOUTRN 1 2 AUD_SPKR_OUTR_N
13
33
23
24
101
1%
1/16W 0603
MF
6 3 MIN_NECK_WIDTH=6MIL LA012
TIE TO SHASTA GPIO RA013
D QA000 D QA000 AUDSAMPCSS 800-OHM
ACM4532 1 CA010 1 CA011 1 CA012 1 CA013
2N7002DW 2N7002DW SYM_VER-1
1000PF 1000PF 1000PF 1000PF
47K AUDIO_SPKR_MUTE_L_F 2
SOT-363
5
SOT-363
1 4 5% 5% 5% 5%
25 AUDIO_SPKR_MUTE_L 1 2 G S G S
2 25V
CERM 2 25V
CERM 2 25V
CERM
25V
2 CERM
5% 603 603 603 603
1/16W 1 4
MF
402 1 CA009 2 3
CA014 0.47UF
RA0121 CA020 1 CA021 1
1
0.47UF
10%
16V APPLE P/N 155S0194
4.7K 100PF 100PF 10% 2 X7R
5%
1/16W 5%
50V
5%
50V 2 16V
X7R
805
MF CERM 2 CERM 2 805
402 2 402 402
XCA000
50R28
DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
1
MIN_NECK_WIDTH=10MIL XWA001 MIN_NECK_WIDTH=10MIL

B 102 7 GND_AUDIO_SPKRAMP 1
OMITSM
2
B
XWA002
OMITSM
1 2
GAIN SETTINGS: +19DB

MODULATION SETTING: LOW EMI
102 100 GND_AUDIO_SPKRAMP_PLANE
GAIN AND SWITCHING FREQUENCY STUFF OPTIONS
LA009 MIN_NECK_WIDTH=4MIL LA010 MIN_NECK_WIDTH=4MIL
1000-OHM-EMI 1000-OHM-EMI
1 2
PP3V3_AUDIO_SPKR_EMI 1 2
103 102 101 95 7 PP3V3_AUDIO PP3V3_AUDIO_SPKR 100
SM SM
8 7 6 5
CA022 1 RPA000
100PF
5% 47K
50V 5%
CERM 2 1/16W
402 SM1
1 2 3 4
AUDIO: SPEAKER AMP

A 100 AUD_SAMP_G1
100 AUD_SAMP_G2 NOTICE OF PROPRIETARY PROPERTY
A
100 AUD_SAMP_FS1
100 AUD_SAMP_FS2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
RA008
1
RA009
1 1
RA010 1
RA011 II NOT TO REPRODUCE OR COPY IT
0 0 0 0
5% 5% 5% 5% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W 1/16W 1/16W 1/16W
MF MF MF MF
2 402 2 402 2 402 2 402 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6482 I
102 100 GND_AUDIO_SPKRAMP_PLANE
SCALE SHT OF
NONE 100 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LINE IN JACK SPEAKER CABLE CONNECTOR
APPLE P/N 514-0203 APPLE P/N 518-0138
JA100 LA100 LA104

AJR23
MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL FERR-EMI-100-OHM MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL FERR-EMI-100-OHM MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
MIN_LINE_WIDTH=20MIL NET_SPACING_TYPE=AUDIO
F-ST-TH AUD_LI_L_JACK 1 2 AUD_LI_L_EMI 1 2 AUD_LI_L 96
LA130 MIN_NECK_WIDTH=12MIL MIN_LINE_WIDTH=20MIL LA133
5 180-OHM-1.5A MIN_NECK_WIDTH=12MIL 180-OHM-1.5A
SM SM
6 100 AUD_SPKR_OUTR_P 1 2 AUD_SPKR_OUTR_P_CONN JA101 AUD_SPKR_OUTR_N_CONN 1 2 AUD_SPKR_OUTR_N 100
LA101 LA105 0603 10-89-7082 0603

M-ST-TH
MIN_NECK_WIDTH=6MIL
FERR-EMI-100-OHM MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
MIN_NECK_WIDTH=6MIL 2 1
3 AUD_LI_DET_JACK 1 2 AUD_LI_DET_EMI 1 2 AUD_LI_DET_H 101 NET_SPACING_TYPE=AUDIO NET_SPACING_TYPE=AUDIO
LA131 MIN_LINE_WIDTH=20MIL 4 3 MIN_LINE_WIDTH=20MIL LA134
D
4
2
SM
MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
SM
180-OHM-1.5A MIN_NECK_WIDTH=12MIL 5
MIN_NECK_WIDTH=12MIL 180-OHM-1.5A D
LA102 LA106 100 AUD_SPKR_OUTL_N 1 2 AUD_SPKR_OUTL_N_CONN 8 7 AUD_SPKR_OUTL_P_CONN 1 2 AUD_SPKR_OUTL_P 100
MIN_NECK_WIDTH=6MIL FERR-EMI-100-OHM FERR-EMI-100-OHM MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL 0603 0603
AUDIO_GPIO_12_CONN
8
AUD_LI_R_EMI 103 102 101 100 95 7 PP3V3_AUDIO
AUD_LI_R_JACK 1 2 1 2 AUD_LI_R 96
SM SM
1
RA113
47K
LA103 LA107 5%
1/16W
FERR-EMI-100-OHM FERR-EMI-100-OHM MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
MF
AUD_LI_GND_JACK 1 2 1 2 AUD_LI_GND 96
2 402 LA132
1000-OHM-200MA 1 CA126 1 CA127
MIN_LINE_WIDTH=8MIL SM SM
102 101 7 MIN_NECK_WIDTH=6MIL 25 AUDIO_GPIO_12 1 2 1000PF 1000PF
5% 5%
GND_CHASSIS_AUDIO_EXTERNAL 1 CA100 1 CA101 1 CA102 1 CA103 1 3 NOSTUFF SPEAKER TYPE DETECT 0603 25V
2 CERM
25V
2 CERM
MIN_LINE_WIDTH=8MIL 100PF 100PF 100PF 100PF DZA100 TO SHASTA GPIO 603 603
2 50V
5%
2 50V
5%
50V
2 CERM
5%
2 50V 14V-15A
1 CA119 1 CA125 NOSTUFF NOSTUFF NOSTUFF NOSTUFF
101 AUD_LI_GND_EMI CERM
402
CERM
402 402
CERM
402 0405 1000PF 1000PF 1 CA104 1 CA105 1 CA106 1 CA107
5% 5%
2 4 2 25V
CERM
25V
2 CERM 1000PF 1000PF 1000PF 1000PF
5% 5% 5% 5%
603 603 25V 25V 25V 25V
2 CERM 2 CERM 2 CERM 2 CERM
GND_CHASSIS_AUDIO_EXTERNAL 603 603 603 603
102 101 7
101 7 GND_CHASSIS_AUDIO_INTERNAL
LINE IN PLUG DETECT

AUDIO_IN_DET0_L = LOW: PLUG INSERTED LA108 LA111
AUDIO_IN_DET0_L = HIGH: PLUG NOT INSERTED FERR-EMI-100-OHM FERR-EMI-100-OHM
102 GND_AUDIO_MIC 1 2 GND_AUDIO_MIC_EMI 1 2
103 102 101 100 95 7 PP3V3_AUDIO
SM SM
JA102
RA101
1
HF28
47K LA109 LA112 M-ST-TH
RA100
1 5% FERR-EMI-100-OHM FERR-EMI-100-OHM
C 100K
5%
1/16W
1/16W
MF
2 402
TO SHASTA GPIO 102 AUD_MIC_IN_P 1 2 AUD_MIC_IN_P_EMI 1 2
GND_AUDIO_MIC_CONN
AUD_MIC_IN_P_CONN
1
2 C
MF AUDIO_LI_DET_L 25 SM SM AUD_MIC_IN_N_CONN 3
2 402
3
LA110 LA113 APPLE P/N 518-0034 LINE OUT PLUG DETECTS
RA102
D
QA100 FERR-EMI-100-OHM FERR-EMI-100-OHM
101 AUD_LI_DET_H 1
47K 2 AUDLINDETH 1 G S
2N7002
SM 102 AUD_MIC_IN_N 1
SM
2 AUD_MIC_IN_N_EMI 1
SM
2 MIC CABLE CONNECTOR AUDIO_LO_DET_L = LOW: PLUG INSERTED
5%
AUDIO_LO_DET_L = HIGH: PLUG NOT INSERTED
1/16W 2
MF
402
1 CA108 1 CA120 1 CA121 1 CA122 AUDIO_LO_OPTICAL_PLUG_L = LOW: OPTICAL DIGITAL AUDIO PLUG INSERTED
0.1UF AUDIO_LO_OPTICAL_PLUG_L = HIGH: ANALOG AUDIO PLUG INSERTED
20%
10V
1000PF 1000PF 1000PF
2 CERM 10% 10% 10%
402 2 25V
X7R 2 25V
X7R 2 25V
X7R
402 402 402 103 102 101 100 95 7 PP3V3_AUDIO
101 7 GND_CHASSIS_AUDIO_INTERNAL 1
RA104
47K
LA114 LA122 1
RA103 5%
FERR-EMI-100-OHM FERR-EMI-100-OHM 100K 1/16W
MF TO SHASTA GPIO
1 2 1 2 5% 2 402
103 95 AUD_SPDIF_OUT AUD_SPDIF_OUT_EMI AUD_SPDIF_OUT_JACK 1/16W
MF AUDIO_LO_DET_L 6 25
SM SM
2 402
3 QA101
2N7002DW
LA115 LA123 MIN_LINE_WIDTH=12MIL D SOT-363
MIN_NECK_WIDTH=8MIL
FERR-EMI-100-OHM MIN_NECK_WIDTH=8MIL RA105
1 2 1 2
PP5V_AUDIO_SPDIF_JACK 47K 5
7 PP5V_AUDIO PP5V_AUDIO_SPDIF_EMI 101 AUD_LO_DET1 1 2 AUD_LO_DET1_1 G S
SM SM
LINE OUT JACK 5%
1/16W
MF 1 CA109 4
LA116 LA124 1 CA117 1 CA118 APPLE P/N 514-0204
402
0.1UF
FERR-EMI-100-OHM FERR-EMI-100-OHM 20%
0.1UF 1UF 10V
2 CERM
AUD_LO_DET1 1 2 AUD_LO_DET1_EMI 1 2 20% 10%
B
101
SM SM
10V
2 CERM
402
2 10V
CERM
805
JA103 402
B
JFJ8210
LA117 LA125 F-ST-TH
MIN_NECK_WIDTH=8MIL FERR-EMI-100-OHM 9 103 102 101 100 95 7 PP3V3_AUDIO
98 AUD_LO_R 1 2 AUD_LO_R_EMI 1 2 10
SM SM
MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL AUD_LO_GND_JACK 1 RA107
1
TO SHASTA GPIO
47K
LA118 LA126 AUD_LO_DET1_JACK 3 1
RA106 5%
MIN_NECK_WIDTH=8MIL
FERR-EMI-100-OHM MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL AUD_LO_R_JACK 4 100K 1/16W
MF
1 2 1 2 2 5% 2 402
98 AUD_LO_L AUD_LO_L_EMI MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL AUD_LO_L_JACK 1/16W
MF AUDIO_LO_OPTICAL_PLUG_L 25
SM SM
5 2 402
AUD_LO_DET2_JACK 6 QA101
LA119 LA127 6 D
2N7002DW
FERR-EMI-100-OHM FERR-EMI-100-OHM VIN SOT-363
7 RA108
LED
VDD
101 AUD_LO_DET2 1 2 AUD_LO_DET2_EMI 1 2
8 47K 2
GND 101 AUD_LO_DET2 1 2 AUD_LO_DET2_1 G S
SM SM
5%
11 NOSTUFF 1/16W 1
LA120 LA128 12
MF 1 CA110
FERR-EMI-100-OHM MIN_LINE_WIDTH=12MIL FERR-EMI-100-OHM RA109
1 402
0.1UF
MIN_NECK_WIDTH=8MIL 100K 20%
10V
1 2 1 2 5% 2 CERM
98 AUD_LO_GND AUD_LO_GND_EMI MIN_LINE_WIDTH=12MIL 1/16W 402
SM SM MIN_NECK_WIDTH=8MIL MF
AUD_SPDIF_GND 2 402
RA1121
0
LA121 LA129 5% PLACE NEAR PLACE NEAR
FERR-EMI-100-OHM FERR-EMI-100-OHM 1/16W
98 AUD_LO_GND_PRB 1 2 AUD_LO_GND_PRB_EMI 1 2
MF
402 2
J9801
XCA100
J700
XCA101
AUDIO: Q45 CONNECTORS
A SM SM 50R28 50R28
A
1 CA123
1 CA111 1 CA113 1 CA115
1
100PF 100PF 100PF AUD_LI_GND_EMI THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
100PF 5% 5% 5% 101
5% 50V 50V 50V
50V 2 CERM 2 CERM 2 CERM AGREES TO THE FOLLOWING
2 CERM GND_CHASSIS_AUDIO_INTERNAL
402
402 402 402
DZA101 101 7
1 CA124 1 CA112 MMBZ15DLT1
2

100PF 100PF
1 CA114 1 CA116 15V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5% 5% 100PF
2 50V
CERM 2 50V
CERM
5%
50V
0.01UF SOT23
2 CERM 10% SIZE DRAWING NUMBER REV.
402 402 16V
2 CERM
402
D 051-6482 I
3
402
102 101 7 GND_CHASSIS_AUDIO_EXTERNAL APPLE COMPUTER INC.

SCALE SHT OF
NONE 101 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RA226 RA227
UNUSED GPIO TERMINATIONS
0 0
1 2 I2S0_BITCLK_8NS_DELAY 1 2
ELECTRICAL_CONSTRAINT_SET=8NS
5% 5%
5V POWER SUPPLY FOR THE HEADPHONES/LINE OUT AMP 1/16W
MF
402 NOSTUFF
1/16W
MF
MIN_NECK_WIDTH=8MIL
RA225 103 102 101 100 95 7 PP3V3_AUDIO
0
103 25 I2S0_BITCLK 1 2 I2S0_BITCLK_DELAYED 95
DIFFERENTIAL_PAIR=AUD_CODEC_PWR
APPLE P/N 353S0539 NET_SPACING_TYPE=AUDIO 5%
1/16W NOSTUFF
D NET_SPACING_TYPE=AUDIO
CRITICAL
VRA200 MIN_LINE_WIDTH=25MIL
MF
402 1
RA228 RA206 D
VOLTAGE=12V VOLTAGE=12V VOLTAGE=12V VOLTAGE=5V 0 47K
AUDIO_LI_OPTICAL_PLUG_L 1 2
LA200 5%
1/16W
25
FERR-250-OHM RA200 LM1117 MF

2 402
5%
1/16W
1 2
10 SOT223-4 MF
7 PP12V_AUDIO_CODEC AUD_12V_CODEC 1 2 AUD_12V_CODEC2 3 IN VOUT 4 PP5V_AUDIO_ANALOG 98 102 402
SM-1 5% OUT 2
1W
FF ADJ/GND RA207
2512 1 RA2011 47K
PLACE ACROSS GROUND SPLIT 25 AUDIO_HP_DET_L 1 2
205
1% AT RIGHT SIDE OF CA007 5%
1/16W
1/16W
1 CA200 1
CA201 1
CA209 MF NOSTUFF MF
1UF 220UF 220UF 402 2 1
CA203 RA216
402
20%
16V 20% 20% AUD_V5_REF 100UF
2 CERM 2 16V 2 16V FC=7HZ 20% 0 RA208
1206
ELEC ELEC 2 16V 100 GND_AUDIO_SPKRAMP_PLANE 1 2 GND_AUDIO_CODEC 95 96 98 102
SM-2 SM-2 ELEC 47K
SM 5% 25 AUDIO_SPKR_DET_L 1 2
CA202 1 RA202 1 1/10W

FF 5%
100UF 634 805 1/16W
1% MF
20% 1/16W 402
16V 2
ELEC
MF PLACE NEAR ENTRY TO SPEAKER
402 2
SM AMP GROUND PLANE RA209
NOSTUFF 47K
25 I2S2_DEV_TO_SB_DTI 1 2
RA217 5%
0 1/16W
100 7 GND_AUDIO_SPKRAMP 1 2 MF
402
5%
1/10W
FF
RA210
4.5V POWER SUPPLY FOR CODEC AND LINE IN AMP 805
103 25 AUDIO_GPIO_11 1
47K 2
APPLE P/N 353S0733 5%
1/16W
MF
C CRITICAL
402
C
VRA201
PLACE ACROSS GROUND SPLIT RA211
MAX8510-4.5V MIN_NECK_WIDTH=10MIL AT CODEC U9500 47K
SC70-5 VOLTAGE=4.5V 25 I2S2_BITCLK 1 2
102 98 PP5V_AUDIO_ANALOG 1 IN OUT 5 PP4V5_AUDIO_ANALOG 95 96 5%
1/16W
RA205 MF
402
RA2031 3 SHDN* BP 4 1 CA206 GND_AUDIO_CODEC 1
0 2
100K 0.01UF 102 98 96 95
NOSTUFF 1% 10%
16V 5% RA212
1/16W GND 2 CERM 1/10W 47K
RA204 MF
402 2 2
402
MF
603
25 I2S2_SYNC 1 2
100K 2 AUD_4V5_FB 5%
103 102 101 100 95 7 PP3V3_AUDIO 1 1/16W
MF
1% AUD_4V5_SHDN* 402
1/16W
MF
1 CA207 1
CA208
1UF 10UF
402
10% 20% RA213
1 CA204 1 CA205 2 10V
CERM 2 16V
ELEC PLACE AT J5903 AUDIO_HP_MUTE_L 1
47K 2
10UF 0.1UF NOT USED: C9906 805 SM-1
25
20% 10% 5%
6.3V 16V 1/16W
2 CERM 2 X7R
MF
805 603 402
RA229
102 98 96 95 GND_AUDIO_CODEC 0 RA214
101 7 GND_CHASSIS_AUDIO_EXTERNAL 1 2
5% AUDIO_EXT_MCLK_SEL 1
47K 2
25
1/10W
FF 5%
805 1/16W
MF
402
RA215
47K
I2S2_RESET_L 1 2
B
25
5%
1/16W
B
MF
402
MICROPHONE IMPEDANCE MATCHING CIRCUIT MAKE_BASE=TRUE

TP_I2S2_SB_TO_DEV_DTO
I88
I2S2_SB_TO_DEV_DTO 25
MAKE_BASE=TRUE I89
AUDIO GROUND RETURNS AUD_PCM_MBIAS 95 TP_I2S2_MCLK I2S2_MCLK 25
MAKE_BASE=TRUE I116
DIFFERENTIAL_PAIR=AUD_CODEC_PWR NOSTUFF
NET_SPACING_TYPE=AUDIO 25 I2S0_MCLK AUD_CODEC_MCLK 95 103
XWA200
VOLTAGE=4.5V
1 CA210 1
CA211
SM OMIT
10UF 10UF
20% 20%
7 GND_AUDIO 1 2 GND_AUDIO_CODEC 95 96 98 102
6.3V
2 CERM 2 16V
ELEC
805 SM-1
NOSTUFF
1
RA218 1
RA223
1K 1K GND_AUDIO_CODEC 95 96 98 102
MIN_LINE_WIDTH=10MIL 1% 1%
MIN_NECK_WIDTH=6MIL 1/16W 1/16W
XWA201 VOLTAGE=4.5V MF MF
SM OMIT
2 402 2 402
1 2 GND_AUDIO_MIC 101 102 DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO RA219
DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO CA213 DIFFERENTIAL_PAIR=AUDIO_MIC_2
0.1UF NET_SPACING_TYPE=AUDIO
165 1 2
MIN_LINE_WIDTH=25MIL 101 AUD_MIC_IN_P 1 2 AUD_MIC_P1 AUD_MICIN_P 95
XWA202
SM OMIT
VOLTAGE=4.5V 1%
1/16W 10%
1 2 GND_AUD_LOAMP 98 CA212 1
MF
402 RA2221 16V
X7R AUDIO: Q45 POWER SUPPLIES
100K
A
603
DIFFERENTIAL_PAIR=AUDIO_MIC
1000PF
10%
25V 2
X7R
1%
1/16W
MF CA214 NOTICE OF PROPRIETARY PROPERTY
A
NET_SPACING_TYPE=AUDIO 402 RA220 402 2
0.1UF
DIFFERENTIAL_PAIR=AUDIO_MIC_2
XCA201 XWA203
SM OMIT
VOLTAGE=4.5V
101 AUD_MIC_IN_N 1
165 2 AUD_MIC_M1 1 2 AUD_MICIN_N 95
50R28 AGREES TO THE FOLLOWING
1 1 2 GND_AUD_LOAMP_CHGPMP 98 1%
10%
NOSTUFF 1/16W DIFFERENTIAL_PAIR=AUDIO_MIC_1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF NET_SPACING_TYPE=AUDIO 16V
1
RA221 402 1
RA224 X7R
603 II NOT TO REPRODUCE OR COPY IT
1K 1K III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1% 1%
1/16W 1/16W
MF MF SIZE DRAWING NUMBER REV.
2 402 2 402
102 101 GND_AUDIO_MIC APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 102 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
S/PDIF TRANSMITTER
I2C ADDRESS = 0010 000X
APPLE P/N 353S0597
NOSTUFF
1000-OHM-200MA
PP3V3_AUDIO_CS8406
102 101 100 95 7 PP3V3_AUDIO 1 2
NOSTUFF 0603
CA300 1 NOSTUFF NOSTUFF
10UF
CA301 CA302 C
C
20% 1 1
6.3V
CERM 2 1UF 1UF
805 10% 10%
10V 10V
2 CERM 2 CERM
805 805
NOSTUFF
UA300
6 23
VD VL
102 95 AUD_CODEC_MCLK 21 OMCK
USER 18
TEST18
I2S0_SYNC 12 NOSTUFF
95 25 ILRCLK TEST20 20
13
102 25 I2S0_BITCLK ISCLK
USER
NET_SPACING_TYPE=AUDIO RA301 NET_SPACING_TYPE=AUDIO
CS8406 26
33
14 TXP
AUD_CS8406_TXP 1 2 AUD_SPDIF_OUT 95 101
95 25 I2S0_SB_TO_DEV_DTO SDIN TSSOP
25 NC 5%
TXN 1/16W
MF
95 18 I2C_AUDIO_SCL 28 ORIG 402
SCL/CCLK C EN 16
95 18 I2C_AUDIO_SDA 1 COPY/C TEST16 AUD_CS8406_USERBIT
SDA/CDOUT
VALIDITY 17
TEST17
2 TEST2
I87 MAKE_BASE=TRUE
AD0/CS AUDIO* 19 AUD_CS8406_INT TP_AUD_CS8406_INT
27 TEST27 INT
AD1/CDIN
3 EMPH* APMS 10
AD2 TEST10
TCBLD 11
102 25 AUDIO_GPIO_11 9 TEST11
RST*
24 15 AUD_CS8406_TCBL
H_S* TCBL
4 SFMT0 NOSTUFF NOSTUFF

RXP 7
5 SFMT1
TEST7
8 RA300
1
RA302
1
DGND TEST8 47K 47K
B DGND
22
5%
1/16W
MF
2 402
5%
1/16W
MF
2 402
B
AUDIO: S/PDIF XMITTER

A
APPLE COMPUTER INC.

D 051-6482 I
SCALE SHT OF
NONE 103 103
8 7 6 5 4 3 2 1

820-1540 (Project Q45A)

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820-1540 (Project Q45A)

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8 7 6 5 4 3 2 1

SCHEMATIC,MLB,Q45A ("Rous") I 355571 PRODUCTION RELEASED 12/13/04 ?

A 48 39 U3LITE AGP X.XX

* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC RELEASE SCALE SCH,MLB,IMG5

SIZE DRAWING NUMBER

POWER CLOCKS BUFFER B I2C J6400

AIRPORT USB 2.0

EDUCATION: NOT USED

D PP24V_RUN PP12V_RUN PP5V_RUN PP5V_ALL PP3V3_RUN SMU_PWRSEQ_P9_5 13 (PWR_GOOD_SB_CORE) D

PP5V_RUN_AUDIO CPU CORE PP2V5_RUN_CPU_AVDD PP5V_PWRON PP3V3_PWRON PP1V2_SHASTA_CORE

LINEAR U3LITE CORE PP2V5_PWRON IN

PP1V25_RAM_VTT PP1V5_RUN V+ SOI

POWER BLOCK DIAGRAM

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

05/03/04 CPU POWER SUPPLY - ON SEMI FETS ONLY

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_11_HEAD 343S0282 343S0284 U3 U3L,V1.1,200MM,PBGA

PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD3,1.8G,85C,BPA

343S0320 343S0284 U3 U3L,NEW LAM,300MM

WAVE3 337S2994 337S2968 CPU_DD30_1_6GHZ U2900 IC,GPUL,DD3,1.6G,APA 1.20V TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

343S0283 1 IC,ASIC,SHASTA,V1.1,PBGA U2300

WAVE5 HP 337S2997 337S2968 CPU_DD30_1_6GHZ U2900 IC,GPUL,DD3,1.6G,ANA 1.20V

WAVE3 337S2970 337S2969 CPU_DD30_1_8GHZ U2900 IC,GPUL,DD3,1.8G,BRA 1.25V

WAVE5 337S2981 337S2969 CPU_DD30_1_8GHZ U2900 IC,GPUL,DD3,1.8G,BPL 1.20V

WAVE5 337S2982 337S2969 CPU_DD30_1_8GHZ U2900

062-2082 1 SPEC,VENDOR PACKAGING PROCEDURE VPP1

820-1540 1 PCB,FAB,MLB MLB1

825-6447 1 BARCODE LABEL, MLB, Q45 LBL1

051-6482 1 PCB,SCHEM,MLB SCH1

341T1366 1 IC,FLASH,1MX8,3.3V,90NS U7500

341T1395 1 PURCH ASSY, SMU BIG U1300

HEAT SINK ASSEMBLY 20 IN

337S2865 1 PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD2.11,1.8GHZ,85C 1.8GHZ 1.45V 45W ? U2900 CPU_DD211_1_8GHZ

337S2866 1 PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD2.11,2.0GHZ,85C 2.0GHZ 1.45V 45W ? U2900 CPU_DD211_2_0GHZ

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

378S0119 378S0114 KINGBRIGHT LED

SIZE DRAWING NUMBER REV.

I388 NO_TEST=YES TP_SB_NC_T2 91 59 IN FILT_ANALOG_RED FUNC_TEST=YES

I398 NO_TEST=YES TP_SB_NC_U4 91 59 IN PP24V_INV FUNC_TEST=YES

9 20 1 2 PP12V_AUDIO_CODEC 102 =PP3V3_PWRON_SB 23 25 74

33 13 11 10 6 SYS_POWERUP_L 2 3 SYS_POWERUP_L_BUF =PP5V_RUN_CPU 3 6 8 31 =PP2V5_PWRON_HT 62

B PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

RESET POWER =PPVCORE_CPU

POWER CONN / ALIAS

D 6 TP_RAM_MUXEN4 ALIAS RAM_MUXEN4 37 D

NOSTUFF NOSTUFF NOSTUFF

HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM

2 402 2 402 2 402 2 402 2 402 2 402 TH TH TH

NOTICE OF PROPRIETARY PROPERTY

2.5V VOLTAGE REGULATOR

5% 2 CERM 2 CERM 10K

SIZE DRAWING NUMBER REV.

SHASTA CORE VOLTAGE REGULATOR

PP1V2_PWRON FET SWITCH PP1V2_RUN FET SWITCH

10 6 3 PPVCORE_PWRON_SB PP1V2_PWRON 10 6 3 PPVCORE_PWRON_SB Q1003 PP1V2_RUN

SIZE DRAWING NUMBER REV.

100UF 0.1UF 210

5V & 3.3V VREGS

SIZE DRAWING NUMBER REV.

SMU_CLK10M_XTAL 15 MIL SPACING SMU_CLK10M_XIN 13