Compal La-8711p r0.1 Schematics

A B C D E
1 1
2
Compal Confidential 2
PAGANI M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point
Date : 2011/11/22
Version 0.1
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8711
Date: Sunday, November 27, 2011 Sheet 1 of 57
A B C D E
A B C D E
Compal Confidential
Model Name : Zonda
1
File Name : LA8711P Intel DDR3 1333/1600MHz 1.5V 1
DDR3L 1333MHz 1.35V DDR3-SO-DIMM X 2

64Mx16 AMD IVY Bridge BANK 0, 1, 2, 3
2011/11/22 128Mx16 128Bit
PEG 2.0 x16 page11 ~ 12
SV Processor Dual Channel
VRAMx8pcs Chelsea Pro
DDRIII 25W rPGA 988B
page27 ~ 29 31mm*24mm
page21 ~ 26 Daughter board
page4 ~ 10
FDI x8 DMI x4 HDD LED & PWR LED

100MHz 100MHz
Accelerometer HDMI Conn. LVDS Conn. USB2.0 x1 port9
2.7GT/s 5GT/s
USB3.0 x2 USB3.0 x1
page42 HP3DC2 page29 page32 3.0 port1,2 page35 3.0 port3 USB charger
X2 X1 X1
FAN conn. LVDS(1Ch) USB 3.0 x3

Intel
page37 HDMI
2
Panther Point USB 2.0 x4
2
PCI-Express x 2 (PCIE2.0 5GT/s) 100MHz X1

PCH X1
SATAx3 100MHz HD Audio port8 port3
989pin BGA
X1 X1 X1 X1 X1 25mm*25mm HD webcam Finger print
GEN1 1.5Gb/S GEN3 6Gb/S GEN3 6Gb/S SPI Module Module
page13 ~ 20 D-MIC(daul)
HDA Codec
port1 port2 port2 port1 port0 IDT 92HD91
BIOS SPI ROM, page38
Card Reader WLAN&BT SATA ODD m-SATA SATA HDD LPC BUS 8MB
page33
/LAN controller (mini card) (mini card) 33MHz
RTL8411 page34 port 10 JMINI1 page33 page33 JMINI2 page33

page31 SPK conn Sub Woofer Amp HP Amp page39
X1 page41 HPA2011 page40 HPA00929
USB 2.0 x1
3
RJ45 SD socket 3
page34 page34
Sub Woofer HP&MIC page41
conn page35 Combo jack
ENE KB932
page36
CRT page30 SM bus PS2 SPI
LED page37 EC ROM,

Lid switch Touch Pad Int.KBD FAN/LED
page37 page37 256kB page36 page37
RTC CKT. page14
Power On/Off CKT. TP BTN on daughter board
DC/DC interface CKT.
4 page43 & PWR BTN LED 4
ODD connector board Daughter board

Daughter board Block Diagrams
Custom 0.1
LA-8711
A B C D E
A B C D E
Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply (19V) N/A N/A N/A
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1 +CPU_CORE Core voltage for CPU ON OFF OFF 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS_VCCP +V1.05SP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+VCCP +VCCP (1.05V ) power for PCH ON OFF OFF
+1.5V +1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V) ON ON OFF
+1.5VS +1.5VS switched power rail ON OFF OFF
+1.8VS (+5VALW ) to 1.8V switched power rail to PCH ON OFF OFF

+3VALW +3VALW always on power rail ON ON ON*
+3VALW_EC +3VALW always to KBC ON ON ON*
+LAN_VDD_3V3 +3VALW to +LAN_VDD_3V3 power rail for LAN ON ON ON*
+3V_PCH +3VALW to +3V_PCH power rail for PCH (Short Jumper) ON ON ON*
EC SM Bus1 address
+3VS +3VALW to +3VS power rail ON OFF OFF
+5VALW +5VALWP to +5VALW power rail ON ON ON* Device Address EC SM Bus2 address
+5V_PCH +5VALW to +5V_PCH power rail for PCH (Short resister) ON ON ON* Smart Battery 0001 011X b
Device Address
+5VS +5VALW to +5VS switched power rail ON OFF OFF G-sensor 0101001b
PCH (Reserve) 1010 0110b
2 +VSB B+ to +VSB always on power rail for sequence control ON ON ON* 2
PCH SM Bus address
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Device Address
DDR DIMM0 1010 0000b
DDR DIMM1
Mini Card1
Mini Card2
TP module
SMBUS Control Table
WLAN BATT EC_SMB_CK2 PCH_SML1CLK

BATT MIINI1 Charger TP SODIMM G-Sensor GPU HP AMP
SOURCE EC_SMB_DA2 PCH_SML1DATA
EC_SMB_CK1 KB930
EC_SMB_DA1 V V V
EC_SMB_CK2 KB930
EC_SMB_DA2 V V USB Port Table
PCH_SMBCLK
PCH_SMBDATA
PCH V V V 1 External
USB 2.0 USB 1.1 Port USB Port
PCH_SML0CLK PCH
3
PCH_SML0DATA SATA DESTINATION 0 USB3.0 3
UHCI0
1 USB3.0
PCH_SML1CLK
PCH_SML1DATA
PCH V SATA0 HDD,JHDD1 2 USB3.0
UHCI1
3 USB2.0 FRP
SATA1 m-SATA,JMINI2 EHCI1
4 X
UHCI2
5 m-SATA
SATA2 ODD, JODD1 6 X
UHCI3
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION 7 X
SATA3 None 8 Camera
UHCI4
CLKOUT_PCIE0 CR+ Giga LAN CLKOUTFLEX0 None 9 USB2.0 and sleep charger
SATA4 None 10 minPCIE-WLAN/BT
EHCI2 UHCI5
CLKOUT_PCIE1 WLAN CLKOUTFLEX1 None 11 X
SATA5 None 12 X
UHCI6
CLKOUT_PCIE2 None CLKOUTFLEX2 None 13 X
CLKOUT_PCIE3 None CLKOUTFLEX3 None 3 External

CLK USB 3.0 Port USB Port
CLKOUT_PCIE4 None Option @ CONN@ PX@ 0 USB3.0
Symbol Note : UMA X X X 1 USB3.0
4
CLKOUT_PCIE5 None : means Digital Ground DIS X X V 2 USB3.0(SB) 4
CLKOUT_PCIE6 None
: means Analog Ground
CLKOUT_PCIE7 None
2011/11/02 2011/11/02 Title
CLKOUT_PEG_B None Issued Date Deciphered Date
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8711
A B C D E
5 4 3 2 1
+1.05VS
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
D D
with - max length = 500 mils - typical
1
RC1 impedance = 43 mohms
24.9_0402_1%
PEG_ICOMPO signals should be routed with -
JCPUA max length = 500 mils
2
J22 PEG_COMP
PEG_ICOMPI
J21
- typical impedance = 14.5 mohms
PEG_ICOMPO
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
15 DMI_CRX_PTX_N1 B25
DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25 DMI_RX#[2]
B24 K33 PEG_GTX_C_HRX_N15
15 DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0]
M35 PEG_GTX_C_HRX_N14
PEG_RX#[1] PEG_GTX_C_HRX_N13
15 DMI_CRX_PTX_P0 B28 DMI_RX[0] PEG_RX#[2]
L34
15 DMI_CRX_PTX_P1 B26 J35 PEG_GTX_C_HRX_N12
DMI_RX[1] PEG_RX#[3] PEG_GTX_C_HRX_N11
15 DMI_CRX_PTX_P2 A24 J32
DMI
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10
15 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_GTX_C_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N[0..15]
15 DMI_CTX_PRX_N0 G21 G33 PEG_GTX_C_HRX_N[0..15] 21
DMI_TX#[0] PEG_RX#[7] PEG_GTX_C_HRX_N7
15 DMI_CTX_PRX_N1 E22 G30
DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_P[0..15]
15 DMI_CTX_PRX_N2 F21
DMI_TX#[2] PEG_RX#[9] F35
PEG_GTX_C_HRX_N5
<PEG> PEG_GTX_C_HRX_P[0..15] 21
15 DMI_CTX_PRX_N3 D21 E34
DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4
PEG_RX#[11] E32
G22 D33 PEG_GTX_C_HRX_N3
15 DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] PEG_HTX_C_GRX_N[0..15]
D22 D31 PEG_GTX_C_HRX_N2
15 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PEG_HTX_C_GRX_N[0..15] 21
F20 B33 PEG_GTX_C_HRX_N1
15 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
PCI EXPRESS* - GRAPHICS

C21 C32 PEG_GTX_C_HRX_N0 PEG_HTX_C_GRX_P[0..15]
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] PEG_HTX_C_GRX_P[0..15] 21
J33 PEG_GTX_C_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14
PEG_RX[1] L35
K34 PEG_GTX_C_HRX_P13
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3]
H35
C PEG_GTX_C_HRX_P11 C
15 FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32
E19 G34 PEG_GTX_C_HRX_P10
15 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_GTX_C_HRX_P9
Intel(R) FDI
B21 F33 PEG_GTX_C_HRX_P8
15 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7] PEG_GTX_C_HRX_P7
15 FDI_CTX_PRX_N5 C20 F30
FDI1_TX#[1] PEG_RX[8] PEG_GTX_C_HRX_P6
15 FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9]
E35
E17 E33 PEG_GTX_C_HRX_P5
F32 PEG_GTX_C_HRX_P4
PEG_RX[12] D34
A22 E31 PEG_GTX_C_HRX_P2
15 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P1
15 FDI_CTX_PRX_P1 G19 FDI0_TX[1] PEG_RX[14] C33
E20 B32 PEG_GTX_C_HRX_P0
15 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 CU33 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14
C19 M32 CU34 2 1 PX@ 0.1U_0402_10V6K
15 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13
D19 M31 CU35 2 1 PX@ 0.1U_0402_10V6K
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 CU36 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_HTX_GRX_N11 CU37 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N11
+1.05VS PEG_TX#[4] PEG_HTX_GRX_N10 CU38 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 K31 2 1
FDI0_FSYNC PEG_TX#[5] PEG_HTX_GRX_N9 CU39 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N9
15 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6]
K28 2 1
J30 PEG_HTX_GRX_N8 CU40 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N8
PEG_TX#[7] PEG_HTX_GRX_N7 CU41 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N7
15 FDI_INT H20 FDI_INT PEG_TX#[8]
J28 2 1
H29 PEG_HTX_GRX_N6 CU42 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N6
PEG_TX#[9]
1
15 FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 CU43 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N5

RC2 FDI0_LSYNC PEG_TX#[10] PEG_HTX_GRX_N4 CU44 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N4
15 FDI_LSYNC1 H17 E29 2 1
FDI1_LSYNC PEG_TX#[11] PEG_HTX_GRX_N3 CU45 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N3
24.9_0402_1% F27 2 1
PEG_TX#[12] PEG_HTX_GRX_N2 CU46 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N2
PEG_TX#[13] D28 2 1
F26 PEG_HTX_GRX_N1 CU47 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N1
2
PEG_TX#[14] PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

eDP_COMPIO and ICOMPO signals PEG_TX#[15] E25 CU48 2 1 PX@ 0.1U_0402_10V6K <PEG>
EDP_COMP A18
should be shorted near balls A17
eDP_COMPIO
M28 PEG_HTX_GRX_P15 CU49 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_P15
eDP_ICOMPO PEG_TX[0]
B
and routed with typical T20 PAD B16
eDP_HPD# PEG_TX[1]
B
impedance <25 mohms PEG_TX[2]
L31 PEG_HTX_GRX_P12 CU52 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_P12
PEG_TX[3] PEG_HTX_GRX_P11 CU53 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_P11
C15 eDP_AUX L28 2 1
D15 eDP_AUX# K30 2 1
K27 2 1
eDP

J29 2 1
PEG_TX[7] PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7
NOTE:eDP_COMPIO and eDP_ICOMPO C17 J27 CU57 2 1 PX@ 0.1U_0402_10V6K
eDP_TX[0] PEG_TX[8] PEG_HTX_GRX_P6 CU58 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_P6
should not be left floating even if Internal F16 H28 2 1
Graphic is disabled since they are shared C16 G28 2 1
with other interfaces G15 eDP_TX[3] E28 2 1
PEG_TX[12] F28 2 1
C18 D27 PEG_HTX_GRX_P2 CU62 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_P2
eDP_TX#[0] PEG_TX[13] PEG_HTX_GRX_P1 CU63 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_P1
E16 eDP_TX#[1] E26 2 1
D16 D25 2 1
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]
10/05 Change to 0.22uF.
TYCO_2013620-2_IVY BRIDGE
@
Typ- suggest 220nF. The change in AC capacitor value from
180nF to 265nF is to enable compatibility with future platforms
having PCIE Gen3 (8GT/s)
11/23 AC-coupling capacitor is 0.1u.Chelsea only support GEN2.
A A

PROCESSOR(1/7) DMI,FDI,PEG
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8551P
5 4 3 2 1
5 4 3 2 1
+3VS Buffered reset to CPU Reset# signal is driven by the PCH to multiple agents on the platform.
PCH Reset# output DC levels are 0-V and 3.3 V,
processor Reset input DC levels are 0V and 1.0 V.
Processor high-voltage level is lower than PCH high voltage level,
+1.05VS therefore a voltage level shifter is required on the Reset# signal.
1
@ CC1 In order for Reset# to meet the signal quality requirement at the input to
0.1U_0402_16V4Z
Check circuit!!! the processor OD buffer must be placed on the motherboard between
1
@ the PCH and the processor.
2 RC3
75_0402_5%
11/21 follow QAZ60 cost down CPU_RST#
5
@ UC1
2
1 RC4
P
NC BUFO_CPU_RST#
4 2 1 BUF_CPU_RST#
D
PLT_RST# 2 Y 1.5K_0402_1%
D
16,21,31,34,36 PLT_RST# A
1
G
SN74LVC1G07DCKR_SC70-5
RC6
3
750_0402_1%
Requires a series resistor of 43±5% between processor and PCH.
2
R956 It also a needs an Rtt of 75±5% to VCCP after the OD
0_0402_5% buffer and before the series resistor.
1 2
JCPUB
This pin is for compability with future
platforms. A pull up resistor to VCCIO is 100MHz
required if connected to the DF_TVS strap +3VS
on the PCH. A28
BCLK CLK_CPU_DMI 14
C26 A27 XDP_DBRESET# RC5 2 1 1K_0402_5%
MISC
CLOCKS
17 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 14 +1.05VS
circuit check 10k
PROC_DETECT (Processor Detect): pulled to 1 @ 2 AN34
ground on the processor package. There is no RC7 10K_0402_5% SKTOCC# RC84
A16 2 1 1K_0402_5%
connection to the processor silicon for this DPLL_REF_CLK RC85
A15 2 1 1K_0402_5%
signal. System board designers may use this DPLL_REF_CLK#
signal to determine if the processor is present ITP CLK change to part E.
PAD T5 @ AL33
+1.05VS CATERR#
Processor Pullups
THERMAL
RC8 2 1 62_0402_5% H_PROCHOT# 1 2 H_PECI_ISO AN33 R8 H_DRAMRST#
17,36 H_PECI PECI SM_DRAMRST# H_DRAMRST# 6
RC9 0_0402_5%
DDR3
MISC
36,47 H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0
RC10 56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP1
A5
SM_RCOMP[1] SM_RCOMP2
A4
SM_RCOMP[2]
RC11 2 1 10K_0402_5% H_CPUPWRGD_R
17 H_THEMTRIP# H_THEMTRIP# 1 2 H_THEMTRIP#_R AN32
THERMTRIP#
C C
RC12 0_0402_5%
PAD
T35
PAD @
T39
AP29 @
PRDY#
AP27
H_PROCHOT# PREQ#
AR26 XDP_TCK
TCK
AR27 XDP_TMS 6/27 Add ESD solution
PWR MANAGEMENT
TMS
1
JTAG & BPM

1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST#
47P_0402_50V8J
15 H_PM_SYNC PM_SYNC TRST#

RC13 0_0402_5%
C4680
RC16 AR28 XDP_TDI SI# 8/16 Reserve RC81~RC85 by ESD request

2
0_0402_5% TDI
AP26 XDP_TDO
TDO
17 H_CPUPWRGD 1 2 H_CPUPWRGD_R AP33
UNCOREPWRGOOD
UNCOREPWRGOOD: 非CORE外外外OK AL35 XDP_DBRESET#_R 1 RC17 2 0_0402_5% XDP_DBRESET#
DBR# XDP_DBRESET# 15
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8
RC18 130_0402_5% SM_DRAMPWROK
AT28
BPM#[0]
SM_DRAMPWROK:DRAM power ok BPM#[1]
AR29
AR30
BUF_CPU_RST# BPM#[2]
AR33 AT30
RESET# BPM#[3] XDP_BPM#4_R T60 @ PAD
AP32
BPM#[4] XDP_BPM#5_R T61 @ PAD
AR31
AT31
AR32
BPM#[7]
2011.10.18 delete all reserved XDP conponent.

SI# 10/02 Change to Pull High +3VS
Just reserve test point for XDP.
+3VS @
+3VALW
DDR3 Compensation Signals
2
B +1.5V_CPU_VDDQ B
RC81 1 SM_RCOMP0 RC23 2 1 140_0402_1% XDP_DBRESET#_R CC4 2 1 0.1U_0402_16V7K
10K_0402_5% CC2 <BOM Structure>
0.1U_0402_16V4Z SM_RCOMP1 RC24 2 1 25.5_0402_1%
1
H_CPUPWRGD_R C118 1 2 220P_0402_50V7K

1
2 RC25 SM_RCOMP2 RC26 2 1 200_0402_1% C263 0.1U_0402_16V7K

UC2 200_0402_5% XDP_TRST# 1 2
@ RC27 74AHC1G09GW_TSSOP5 C264 220P_0402_50V7K
5
0_0402_5% PLT_RST# 1 2
2
1 2 1 PU/PD for JTAG signals C265 @ 100P_0402_50V8J

P
15 SYS_PWROK B
4 PM_SYS_PWRGD_BUF PM_SYS_PWRGD_BUF 1 2
O C266 220P_0402_50V7K
15 PM_DRAM_PWRGD 2
A
G
BUF_CPU_RST# 1 2
RC28 6/27 Add ESD solution
@ XDP_TMS T40 @ PAD
3
+3VS 1 2
XDP_TDI T41 @ PAD
200_0402_5%
Part Number = SA00003Y000 XDP_TDO T42 @ PAD SI# 8/19 BOM
C118 220P
XDP_TCK T43 @ PAD
C266 220P
XDP_TRST# T46 @ PAD C264 220P
C263 0.1u
+3V_PCH CC4 0.1u ok
RC30
1 2
200_0402_5%
2011.10.18 delete all reserved XDP conponent.
Just reserve test point for XDP.
Remove mos for layout
Sharing add for module desige
A A

PROCESSOR(2/7) PM,XDP,CLK
C 0.1
LA-8041P
5 4 3 2 1
5 4 3 2 1
JCPUC
JCPUD
11 DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 11

SA_CLK#[0] AA6 M_CLK_DDR#0 11 12 DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 12
DDR_A_D0 C5 V9 AD2
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA 11 SB_CLK#[0] M_CLK_DDR#2 12
DDR_A_D1 D5 DDR_B_D0 C9 R9
DDR_A_D2 SA_DQ[1] DDR_B_D1 SB_DQ[0] SB_CKE[0] DDR_CKE0_DIMMB 12
D3 A7
DDR_A_D3 SA_DQ[2] DDR_B_D2 SB_DQ[1]
D2 SA_DQ[3]
D10 SB_DQ[2]
DDR_A_D4 D6 AA5 DDR_B_D3 C8
SA_DQ[4] SA_CLK[1] M_CLK_DDR1 11 SB_DQ[3]
DDR_A_D5 C6 AB5 DDR_B_D4 A9 AE1
D SA_DQ[5] SA_CLK#[1] M_CLK_DDR#1 11 SB_DQ[4] SB_CLK[1] M_CLK_DDR3 12 D
DDR_A_D6 C2 V10 DDR_B_D5 A8 AD1
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA 11 DDR_B_D6 SB_DQ[5] SB_CLK#[1] M_CLK_DDR#3 12
C3 SA_DQ[7]
D9 SB_DQ[6] SB_CKE[1] R10 DDR_CKE1_DIMMB 12
DDR_A_D8 F10 DDR_B_D7 D8
F8 G4
G10 AB4 F4
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D10 SB_DQ[9]
G9 SA_DQ[11] RSVD_TP[2] AA4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D12 F9 W9 DDR_B_D11 G1 AA2
DDR_A_D13 SA_DQ[12] RSVD_TP[3] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F7 SA_DQ[13]
G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D14 G8 DDR_B_D13 F5
DDR_A_D15 SA_DQ[14] DDR_B_D14 SB_DQ[13] 10/05 change net name.
G7 F2
K4 AB3 G2
DDR_A_D17 SA_DQ[16] RSVD_TP[4] DDR_B_D16 SB_DQ[15]
K5 SA_DQ[17] RSVD_TP[5] AA3 J7
SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D18 K1 W10 DDR_B_D17 J8 AB1
J1 SA_DQ[19]
K10
SB_DQ[18] RSVD_TP[16] T10
DDR_A_D20 J5 DDR_B_D19 K9
J4 J9
J2 AK3 DDR_CS0_DIMMA# 11 J10
DDR_A_D23 SA_DQ[22] SA_CS#[0] DDR_B_D22 SB_DQ[21]
K2 AL3 DDR_CS1_DIMMA# 11 K8 AD3 DDR_CS0_DIMMB# 12
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_B_D23 SB_DQ[22] SB_CS#[0]
M8 SA_DQ[24] RSVD_TP[7]
AG1 K7 SB_DQ[23] SB_CS#[1] AE3 DDR_CS1_DIMMB# 12
DDR_A_D25 N10 AH1 DDR_B_D24 M5 AD6
N8 SA_DQ[26]
N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D27 N7 DDR_B_D26 N2
M10 SA_DQ[28]
N1 SB_DQ[27]
DDR_A_D29 M9 AH3 DDR_B_D28 M4
SA_DQ[29] SA_ODT[0] M_ODT0 11 SB_DQ[28]
DDR_A_D30 N9 AG3 DDR_B_D29 N5 AE4
SA_DQ[30] SA_ODT[1] M_ODT1 11 SB_DQ[29] SB_ODT[0] M_ODT2 12
DDR_A_D31 DDR_B_D30
M7
DDR SYSTEM MEMORY A AG2 M2 AD4 M_ODT3 12
DDR SYSTEM MEMORY B

DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D31 SB_DQ[30] SB_ODT[1]
AG6 AH2 M1 AD5
AG5 SA_DQ[33]
AM5
SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D34 AK6 DDR_B_D33 AM6
AK5 SA_DQ[35]
AR3
SB_DQ[34]
DDR_A_D36 AH5 DDR_B_D35 AP3
DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_A_DQS#[0..7] 11 DDR_B_D36 SB_DQ[35]
AH6 SA_DQ[37] C4 AN3 DDR_B_DQS#[0..7] 12
C DDR_A_D38 SA_DQS#[0] DDR_A_DQS#1 DDR_B_D37 SB_DQ[36] DDR_B_DQS#0 C
AJ5 SA_DQ[38] G6 AN2 D7
DDR_A_D39 SA_DQS#[1] DDR_A_DQS#2 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ6 J3 AN1 F3
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ8 SA_DQ[40] M6 AP2 K6
AK8 SA_DQ[41] AL6 AP5 N3
AJ9 SA_DQ[42] AM8 AN9 AN5
AK9 AR12 AT5 AP9
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AH8 SA_DQ[44] AM15 AT6 AK12
DDR_A_D45 SA_DQS#[7] DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AH9 AP6 AP15
DDR_A_D46 SA_DQ[45] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AL9 SA_DQ[46]
AN8 SB_DQ[45]
DDR_A_D47 AL8 DDR_B_D46 AR6
AP11 SA_DQ[48] DDR_A_DQS[0..7] 11 AR5 SB_DQ[47]
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D48 AR9
SA_DQ[49] SA_DQS[0] SB_DQ[48] DDR_B_DQS[0..7] 12
DDR_A_D50 AL12 F6 DDR_A_DQS1 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AM12 K3 AT8 G3
AM11 SA_DQ[52] N6 AT9 J6
DDR_A_D53 SA_DQS[3] DDR_A_DQS4 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AL11 AL5 AH11 M3
AP12 SA_DQ[54] AM9 AR8 AN6
AN12 SA_DQ[55] AR11 AJ12 AP8
AJ14 AM14 AH12 AK11
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AH14 SA_DQ[57]
AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D58 AL15 DDR_B_D57 AN14
AK15 AR14
AL14 DDR_A_MA[0..15] 11 AT14
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D60 SB_DQ[59]
AK14 SA_DQ[61] AD10 AT12 DDR_B_MA[0..15] 12
DDR_A_D62 SA_MA[0] DDR_A_MA1 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AJ15 W1 AN15 AA8
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AH15 W2 AR15 T7
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
SA_MA[3] W7 AT15 SB_DQ[63] SB_MA[2] R7
V3 DDR_A_MA4 T6 DDR_B_MA3
SA_MA[4] DDR_A_MA5 SB_MA[3] DDR_B_MA4
V2 T2
W3 T4
11 DDR_A_BS0 AE10 W6 T3
SA_BS[0] SA_MA[7] DDR_A_MA8 SB_MA[6] DDR_B_MA7
11 DDR_A_BS1 AF10 V1 12 DDR_B_BS0 AA9 R2
B SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[0] SB_MA[7] DDR_B_MA8 B
11 DDR_A_BS2 V6 SA_BS[2] SA_MA[9] W5 12 DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
AD8 DDR_A_MA10 R6 R3 DDR_B_MA9
SA_MA[10] DDR_A_MA11 12 DDR_B_BS2 SB_BS[2] SB_MA[9] DDR_B_MA10
SA_MA[11] V4 SB_MA[10] AB7
W4 DDR_A_MA12 R1 DDR_B_MA11
11 DDR_A_CAS# AE8 AF8 T1
SA_CAS# SA_MA[13] DDR_A_MA14 SB_MA[12] DDR_B_MA13
11 DDR_A_RAS# AD9 V5 12 DDR_B_CAS# AA10 AB10
SA_RAS# SA_MA[14] DDR_A_MA15 SB_CAS# SB_MA[13] DDR_B_MA14
11 DDR_A_WE# AF9 V7 12 DDR_B_RAS# AB8 R5
SA_WE# SA_MA[15] SB_RAS# SB_MA[14] DDR_B_MA15
12 DDR_B_WE# AB9 R4
SB_WE# SB_MA[15]
@
+1.5V @
通通DIMM做reset @ RC35
1
CPU 0_0402_5%
1 2 RC36
1K_0402_5%
RC37
2
1K_0402_5%
S
H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
5 H_DRAMRST# DDR3_DRAMRST# 11,12
QC2
2
BSS138_NL_SOT23-3
RC38 S0
G
2
4.99K_0402_1% DRAMRST_CNTRL_PCH hgih ,MOS ON

9/7 Folllow PAJ80 BOM by Light H_DRAMRST# HIGH,DDR3_DRAMRST# HIGH
del: SB501380020
1
A RC39 Dimm not reset A

add: SB00000QO00
0_0402_5% S3
9,14 DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL DRAMRST_CNTRL_PCH Low ,MOS OFF
H_DRAMRST# lo,DDR3_DRAMRST# HIGH
Dimm not reset
S4,5
1
CC3
DRAMRST_CNTRL_PCH Low ,MOS OFF
H_DRAMRST# lo,DDR3_DRAMRST# low Issued Date 2011/11/02 Deciphered Date 2011/11/02 Title
0.047U_0402_16V4Z
2 Dimm reset
PROCESSOR(3/7) DDRIII
Custom 0.1
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
RC40
1K_0402_1%
change to install
2
D D
Change to part G.
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

CFG2 * socket pin map definition
0:Lane Reversed
CFG4
1
RC41
JCPUE 1K_0402_1%
change to install
2
AH27 PAD T3
CFG0 VCC_DIE_SENSE
T9 AK28 AH26
CFG1 CFG[0] VSS_DIE_SENSE
T6 AK29
CFG2 CFG[1]
T10 AL26 CFG[2]
T11 CFG3 AL27 Display Port Presence Strap
CFG4 CFG[3]
AK26 CFG[4] RSVD28 L7
CFG5 AL29 AG7
C T12 CFG[5] RSVD29 C
CFG6 AL30 AE7 1 : Disabled; No Physical Display Port
T13
T7
T8
CFG7
CFG8
AM31
AM32
CFG[6]
CFG[7]
CFG[8]
RSVD30
RSVD31
AK2 CFG4 * attached to Embedded Display Port
CFG9 AM30 W8
CFG
T14 CFG[9] RSVD32
CFG10 AM28 0 : Enabled; An external Display Port device is
T15 CFG[10]
CFG11 AM26
T16
CFG12 AN28
CFG[11]
AT26
connected to the Embedded Display Port
T47 CFG[12] RSVD33
2011.10.18 delete XDP resistor T48 CFG13 AN31 AM33
CFG14 CFG[13] RSVD34
T58 AN26 AJ27
just reserve test point for XDP. CFG15 AM27
CFG[14] RSVD35
T59 CFG[15]
CFG16 AK31 CFG6
T17 CFG[16]
T18 CFG17 AN29
CFG[17] CFG5
1
RSVD37 T8
J16 RC48 UMA@ RC49
RSVD38
+VGFX_CORE RC42 1 249.9_0402_1% VCC_VAL_SENSE AJ31 H16 1K_0402_1% 1K_0402_1%
VAXG_VAL_SENSE RSVD39
2 149.9_0402_1% VSS_VAL_SENSE AH31 VSSAXG_VAL_SENSE RSVD40 G16 @
+CPU_CORE RC44 1 RC43 2 49.9_0402_1% VAXG_VAL_SENSE AJ33
2
VSSAXG_VAL_SENSE VCC_VAL_SENSE
2 1 AH33 VSS_VAL_SENSE
RC45 49.9_0402_1%
Just modify PWR to correct ,
AJ26 AR35
didn't change net-name to save layout time;must modify on SI phase RSVD5 RSVD_NCTF1
AT34
RSVD_NCTF2
RESERVED
AT33
RSVD_NCTF3
AP35
RSVD_NCTF4
RSVD_NCTF5 AR34
PCIE Port Bifurcation Straps
F25
RSVD8
F24
RSVD9 11: (Default) x16 - Device 1 functions 1 and 2 disabled
F23
B RSVD10 B
D24 RSVD11 B34 CPU_RSVD6 T21 CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
RSVD_NCTF6
G25 RSVD12 RSVD_NCTF7 A33 CPU_RSVD7 T22 disabled
G24 RSVD13 A34
RSVD_NCTF8
E23 B35 01: Reserved - (Device 1 function 1 disabled ; function
D23
C30
RSVD14
RSVD15
RSVD16
RSVD_NCTF9
RSVD_NCTF10
C35
* 2 enabled)
A31
RSVD17 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
B30
RSVD18
B29
RSVD19
D30 RSVD20 AJ32
RSVD51
B31 RSVD21 AK32
RSVD52 CFG7
A30
RSVD22
C29 RSVD23
1
AN35 CLK_RES_ITP 14 @ RC50
BCLK_ITP 1K_0402_1%
J20 AM35 CLK_RES_ITP# 14
RSVD24 BCLK_ITP#
B18
RSVD25
2
ITP CLK change from part C.
J15 AT2
RSVD27 RSVD_NCTF11
RSVD_NCTF12 AT1
AR1
RSVD_NCTF13
PEG DEFER TRAINING
B1 PAD T64
KEY
CFG7 * 1: (Default) PEG Train immediately following
xxRESETB de assertion
A
0: PEG Wait for BIOS for training A

PROCESSOR(4/7) RSVD,CFG
Custom 0.1
5 4 3 2 1
5 4 3 2 1
JCPUF POWER
+1.05VS
+CPU_CORE
AG35
VCC1
AG34 VCC2 VCCIO1 AH13
AG33 AH10
VCC3 VCCIO2
AG32 VCC4 VCCIO3 AG10
AG31 VCC5 VCCIO4
AC10
AG30 VCC6 VCCIO5 Y10
D D
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 VCC12 VCCIO11
J12
AF33 J11
VCC13 VCCIO12
AF32 VCC14 VCCIO13 H14
AF31 H12
VCC15 VCCIO14
AF30 H11
VCC16 VCCIO15
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12
PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 F13
VCC21 VCCIO20
AD34 F12
VCC22 VCCIO21
AD33 VCC23 VCCIO22 F11
AD32 E14
VCC24 VCCIO23
AD31 VCC25 VCCIO24 E12
AD30
VCC26
AD29 VCC27 VCCIO25 E11
AD28 D14
VCC28 VCCIO26
AD27 VCC29 VCCIO27
D13
AD26 D12
VCC30 VCCIO28
AC35 D11
VCC31 VCCIO29
AC34 C14
VCC32 VCCIO30
AC33 C13
VCC33 VCCIO31
AC32 C12
VCC34 VCCIO32
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 A14
C VCC38 VCCIO36 C
AC27 VCC39 VCCIO37
A13
AC26 A12
VCC40 VCCIO38
AA35 VCC41 VCCIO39
A11
AA34 VCC42
AA33 VCC43 VCCIO40
J23
AA32 VCC44
AA31
VCC45
AA30
VCC46
AA29 VCC47
AA28 VCC48
AA27 VCC49
AA26
VCC50 +1.05VS +1.05VS
Y35
CORE SUPPLY
VCC51
Y34
VCC52
Y33 VCC53
Y32
VCC54
1
Y31
VCC55
75_0402_5%
Y30 RC55 RC56
VCC56 130_0402_5%
Y29 VCC57
Y28 VCC58
Y27
2
VCC59
Y26
VCC60
V35
VCC61 H_CPU_SVIDALRT# RC57 1 43_0402_1%
V34 AJ29 2
SVID
VCC62 VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# 55
V33 AJ30 RC58 1 2 0_0402_5%
VCC63 VIDSCLK H_CPU_SVIDDAT VR_SVID_CLK 55
V32 AJ28 RC59 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT 55
V31 VCC65
V30
VCC66
V29 VCC67
V28
VCC68
V27
VCC69
V26
B VCC70 B
U35 VCC71
U34 VCC72
U33 VCC73
U32 VCC74
U31 VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27 VCC79
U26 VCC80
R35 VCC81
R34 VCC82
R33 VCC83
R32 1 RC121 2 +CPU_CORE
VCC84
R31 VCC85
100_0402_1%~D Place the PU
R30 @ 1 2
R29
VCC86 RC60 100_0402_1% resistors close to CPU
VCC87
R28
SENSE LINES
VCC88
R27
VCC89 AJ35 VCCSENSE_R RC61 1 2 0_0402_5%
VCCSENSE 55
VCC_SENSE
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R RC62 1 2 0_0402_5%
VSSSENSE 55
P35
VCC91
1
P34 RC63 1 2 +1.05VS
VCC92 10_0402_1% RC64
P33
VCC93 VCCIO_SENSE_R RC65 1 0_0402_5%
P32 VCC94 VCCIO_SENSE B10 2 VCCIO_SENSE 50 100_0402_1%
P31 A10 VSS_SENSE_VCCIO
VCC95 VSS_SENSE_VCCIO VSS_SENSE_VCCIO 50
1
P30
2
VCC96
P29 VCC97
RC66 Place the PU
P28 10_0402_1%
VCC98 resistors close to VR
P27
P26
VCC99 10/05 mount.
2
VCC100
(follow check list)
A A
@
PROCESSOR(5/7) PWR,BYPASS
Custom 0.1
5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ +1.5V
‧ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
CC74 1 0.1U_0402_10V7K
‧
2 stuffed in a common motherboard design,
VAXG can be left floating in a common
CC75 2 1 0.1U_0402_10V7K motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
+VGFX_CORE JCPUG
POWER 100±5% pull-up to VCC;
D RC157 1 @ 2 100_0402_1%~D 100±5% pull-down to GND. +1.5V_CPU_VDDQ D
AT24 AK35
SENSE
LINES
VAXG1 VAXG_SENSE VCC_AXG_SENSE 55
1
AT23
VAXG2 VSSAXG_SENSE
AK34 VSS_AXG_SENSE 55 +V_SM_VREF should
AT21 RC68
AT20
VAXG3 have 20 mil trace width 1K_0402_1%
VAXG4
AT18
VAXG5
AT17
2
VAXG6 +V_SM_VREF_CNT
AR24 VAXG7
AR23
VAXG8
1
AR21 1
VAXG9 CC79 RC69
AR20 VAXG10
QC7 AR18 AL1 0.1U_0402_16V4Z 1K_0402_1%
VAXG11 SM_VREF
AR17 VAXG12
SB000002X00 AP24 2
VREF
2
VAXG13
1
D BSS138W-7-F_SOT323-3 +1.5V_CPU_VDDQ
AP23
VAXG14
2 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 6,14 AP21
G VAXG15 +V_DDR_REFA_R
AP20 B4
+V_DDR_REFA VAXG16 SA_DIMM_VREFDQ +V_DDR_REFB_R
S AP18 D1
3
RC15 VAXG17 SB_DIMM_VREFDQ

AP17
+V_DDR_REFA_R VAXG18
1 2 AN24 VAXG19 11/21 follow PBL22 design remove 10u*2, 1U*8; 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@ 0_0402_5% AN23 1 1 1 1 1
VAXG20 keep 10U*5 +
1 RC14 2 AN21 VAXG21
CC100
CC95
CC96
CC97
CC98
CC99
QC8 @ 1K_0402_1% AN20 330U_D2_2V_Y
VAXG22
AN18
VAXG23
DDR3 -1.5V RAILS

SB000002X00 2 2 2 2 2 2
AN17
VAXG24
1
D BSS138W-7-F_SOT323-3 AM24 AF7
GRAPHICS
VAXG25 VDDQ1
2 DRAMRST_CNTRL_PCH AM23 AF4
G VAXG26 VDDQ2
AM21 VAXG27 VDDQ3 AF1
+V_DDR_REFB S AM20 AC7
QC4 Change to SA0000JA00 for small package +1.5V_CPU_VDDQ Source
3
RC82 VAXG28 VDDQ4

AM18 VAXG29 VDDQ5 AC4
+V_DDR_REFB_R
C
1 2
@ 0_0402_5%
AM17
AL24
VAXG30 VDDQ6 AC1
Y7
1016 +VCCSA C
VAXG31 VDDQ7 +VCCSA
1 RC83 2 AL23 Y4
@ 1K_0402_1% VAXG32 VDDQ8
AL21 Y1
VAXG33 VDDQ9
AL20 VAXG34 VDDQ10 U7
AL18 U4
VAXG35 VDDQ11 Delete CC25 330U cap 10.19
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AL17 U1 1 1 1
VAXG36 VDDQ12
AK24 VAXG37 VDDQ13 P7 (after check with power)
CC22
CC21
CC24
AK23 P4
VAXG38 VDDQ14
AK21 VAXG39 VDDQ15 P1
AK20 2 2 2
VAXG40
For Chief River only AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
M3 Circuit (Processor Generated SO-DIMM VREF_DQ) AJ23
VAXG44
AJ21 VAXG45
AJ20
VAXG46 11/21 follow PBL22 design remove 10u*2, 1U*5
AJ18
VAXG47
AJ17 VAXG48 VCCSA1 M27
SA RAIL
10/03 add +V_DDR_REFB AH24
AH23
VAXG49
VAXG50
VCCSA2
VCCSA3
M26
L26
AH21 J26
VAXG51 VCCSA4
AH20 J25
VAXG52 VCCSA5
AH18 J24
VAXG53 VCCSA6
AH17 VAXG54 VCCSA7
H26
H25
VCCSA8
VCCSA_SENSE 52
1.8V RAIL
H23VCCSA_SENSE 1 2
+1.8VS RC77 VCCSA_SENSE @ RC78 0_0402_5% +1.05VS
B 0_0805_5% B
1 2 +1.8VS_VCCPLL B6 0_0402_5%
VCCPLL1
1
330U_D2_2VM_R6M
10U_0603_6.3V6M
A6 C22 1 RC79 2 VCCSA_VID0

MISC
VCCPLL2 VCCSA_VID[0] VCCSA_VID0 52
1U_0402_6.3V6K
CC121
1U_0402_6.3V6K
CC122
1 1 1 1 A2 VCCPLL3 VCCSA_VID[1] C24 1 2 VCCSA_VID1 VCCSA_VID1 52

RC52 @
CC120
RC80 0_0402_5% 75_0402_5%

CC26
2
2 @ 2 2 A19 VCCP_PWRCTRL_R 110K_0402_5%
2
2 VCCIO_SEL
@ RC53
SI# 7/29 Add CC26 10uF and reserve 330U on 1.8V power Rail
@ CPU EDS descript as follow:
For Chief River platforms this pin
should not be used.
+1.5V QC4 +1.5V_CPU_VDDQ
+VSB AON6718L_DFN8-5
1
2
1
+3VALW 5 3
2
RC70 RC71
1
20K_0402_5%
100K_0402_5% 470_0603_5%
4
R78
2
1
RC72 RUN_ON_CPU1.5VS3 @
3
100K_0402_5%
2
6
1
RC74 1
2
0_0402_5% RUN_ON_CPU1.5VS3# 2N7002DWH_SOT363-6 VID[0] VID[1] 2011 2012

5
A
1 2 QC5B 2 RUN_ON_CPU1.5VS3# 0 0 0.90 V Yes Yes A
36 CPU1.5V_S3_GATE
6
RC73 CC118 0 1 0.80 V Yes Yes

4
@ RC75 330K_0402_5% 2 0.1U_0402_25V6 Q10A 1 0 0.725 V No Yes

2
0_0402_5% 2N7002DWH_SOT363-6 1 1 0.675 V No Yes

2N7002DWH_SOT363-6
36,43,50,51,52,53 SUSP# 1 2 2
QC5A
1
SI# BOM Change CC118 0.1u 25V form 0.1u 16V Security Classification Compal Secret Data Compal Electronics, Inc.
PROCESSOR(6/7) PWR
Custom 0.1
Follow DG 0.71 page 6 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8041P
5 4 3 2 1
5 4 3 2 1
JCPUH
AT35 VSS1 VSS81 AJ22

AT25 AJ10
VSS5 VSS85
AT22 AJ7
VSS6 VSS86
AT19 AJ4
VSS7 VSS87
AT16 VSS8 VSS88 AJ3
AT13 AJ2 JCPUI
VSS9 VSS89
D D
AT7 VSS11 VSS91 AH35
AT4 VSS12 VSS92 AH34
AT3 VSS13 VSS93 AH32 T35 VSS161 VSS234
F22
AR25 AH30 T34 F19
VSS14 VSS94 VSS162 VSS235
AR22 AH29 T33 E30
AR19 VSS16 VSS96
AH28 T32 VSS164 VSS237
E27
AR16 AH25 T31 E24
AR13 VSS18 VSS99 AH22 T30 VSS166 VSS239
E21
AR10 AH19 T29 E18
AR7 VSS20 VSS101 AH16 T28
VSS168 VSS241
E15
AR4 VSS21 VSS102 AH7 T27
VSS169 VSS242
E13
AR2 VSS22 VSS103
AH4 T26
VSS170 VSS243 E10
AP34 VSS23 VSS104 AG9 P9 VSS171 VSS244
E9
AP31 VSS24 VSS105
AG8 P8 VSS172 VSS245 E8
AP28 VSS25 VSS106 AG4 P6 VSS173 VSS246
E7
AP25 AF6 P5 E6
AP22 VSS27 VSS108 AF5 P3 VSS175 VSS248 E5
AP19 AF3 P2 E4
AP16 VSS29 VSS110 AF2 N35
VSS177 VSS250 E3
AP13 AE35 N34 E2
AP10 VSS31 VSS112 AE34 N33 VSS179 VSS252
E1
AP7 AE33 N32 D35
AP4 VSS33 VSS114 AE32 N31 VSS181 VSS254 D32
AP1 VSS34 VSS115 AE31 N30 VSS182 VSS255 D29
AN30 AE30 N29 D26
AN27 AE29 N28 D20
AN25 AE28 N27 D17
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
N26
M34
VSS185
VSS186
VSS187
VSS258
VSS259
VSS260
C34
C31
AN16 VSS40 VSS121 AE9 L33 VSS188 VSS261 C28
AN13 AD7 L30 C27
AN10 VSS42 VSS123 AC9 L27 VSS190 VSS263 C25
C C
AN7 AC8 L9 C23
AN4 AC6 L8 C10
AM29 AC5 L6 C1
AM25 VSS46 VSS127 AC3 L5 VSS194 VSS267 B22
AM22 AC2 L4 B19
AM19
AM16
VSS47
VSS48
VSS49
VSS128
VSS129
VSS130
AB35
AB34
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AM13 AB33 L1 B13
AM10 VSS51 VSS132 AB32 K35 VSS199 VSS272 B11
AM7 VSS52 VSS133
AB31 K32 VSS200 VSS273
B9
AM4 VSS53 VSS134 AB30 K29 VSS201 VSS274 B8
AM3 AB29 K26 B7
AM2 VSS55 VSS136
AB28 J34 VSS203 VSS276 B5
AM1 AB27 J31 B3
AL34 VSS57 VSS138 AB26 H33 VSS205 VSS278 B2
AL31 Y9 H30 A35
AL28 Y8 H27 A32
AL25 VSS60 VSS141 Y6 H24 VSS208 VSS281 A29
AL22 Y5 H21 A26
AL19 VSS62 VSS143 Y3 H18 VSS210 VSS283 A23
AL16 VSS63 VSS144
Y2 H15
VSS211 VSS284
A20
AL13 W35 H13 A3
AL10 W34 H10
VSS65 VSS146 VSS213
AL7 W33 H9
VSS66 VSS147 VSS214
AL4 VSS67 VSS148 W32 H8
VSS215
AL2 W31 H7
VSS68 VSS149 VSS216
AK33 VSS69 VSS150 W30 H6 VSS217
AK30 W29 H5
VSS70 VSS151 VSS218
AK27 W28 H4
VSS71 VSS152 VSS219
AK25 W27 H3
VSS72 VSS153 VSS220
AK22 W26 H2
VSS73 VSS154 VSS221
AK19 U9 H1
B VSS74 VSS155 VSS222 B
AK16 VSS75 VSS156 U8 G35 VSS223
AK10 VSS77 VSS158
U5 G29 VSS225
AJ25 G20
VSS80 VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31 VSS232
TYCO_2013620-2_IVY BRIDGE F29
VSS233
A A

PROCESSOR(7/7) VSS
Custom 0.1
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM A
+V_DDR_REFA +1.5V +1.5V
3.56A@+1.5V
JDDRL1
All VREF traces should +V_DDR_REFA 1 2
D VREF_DQ VSS1 DDR_A_D4 D
have 20 mil trace width 3 4
VSS2 DQ4
0.1U_0402_16V7K
2.2U_0603_6.3V6K
CD2
DDR_A_D0 5 6 DDR_A_D5
6 DDR_A_D[0..63] DQ0 DQ5
CD1
1 1 DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
6 DDR_A_DQS[0..7] 9 10
VSS4 DQS#0 DDR_A_DQS0
11 12
DM0 DQS0
6 DDR_A_DQS#[0..7] 13 14
2 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
15 16
DDR_A_D3 DQ2 DQ6 DDR_A_D7
6 DDR_A_MA[0..15] 17 18
DQ3 DQ7
19 20
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 22
23 24
DQ9 DQ13
Delete DDR_A_DM[0..7] 25
VSS9 VSS10
26
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# 6,12
DQS1 RESET#
31 32
33 34
35 36
DQ11 DQ15
37 38
39 40
41 42
+1.5V DQ17 DQ21
43 44
DDR_A_DQS#2 VSS15 VSS16
45 46
DDR_A_DQS2 DQS#2 DM2
47 48
DQS2 VSS17
1
49 50 DDR_A_D22
RD1 DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 52
1K_0402_1% DDR_A_D19 DQ18 DQ23
53 54
+V_DDR_REFA DQ19 VSS19 DDR_A_D28
55 56
DDR_A_D24 VSS20 DQ28 DDR_A_D29
57 58
2
DDR_A_D25 DQ24 DQ29

59 60
61 62
63 64
DM3 DQS3
1
65 66
RD2 DDR_A_D26 VSS23 VSS24 DDR_A_D30
67 68
1K_0402_1% DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 70
DQ27 DQ31
71 72
VSS25 VSS26
2
C C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 6
6 DDR_CKE0_DIMMA CKE0 CKE1
75 76
VDD1 VDD2 DDR_A_MA15
77 78
DDR_A_BS2 NC1 A15 DDR_A_MA14
6 DDR_A_BS2 79 80
BA2 A14
81 82
DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
83 84
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 86
A9 A7
87 88
89 90
DDR_A_MA5 A8 A6 DDR_A_MA4
91 92
A5 A4
93 94
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
Layout Note: 97
A1 A0
98
99 100
Place near JDIMM1.203 & JDIMM1.204 M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
6 M_CLK_DDR0 101 102 M_CLK_DDR1 6
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
6 M_CLK_DDR#0 103 104 M_CLK_DDR#1 6
CK0# CK1# +1.5V
105 106
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 6
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
+0.75VS
11/18 for layout spacing: remove CD5/CD6/CD9 6 DDR_A_BS0 109
BA0 RAS#
110 DDR_A_RAS# 6
111 112
VDD13 VDD14
1
11/21 1U*4 only 6 DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA# DDR_CS0_DIMMA# 6
DDR_A_CAS# WE# S0# M_ODT0 RD3
6 DDR_A_CAS# 115 116 M_ODT0 6
CAS# ODT0 1K_0402_1%
117 118
DDR_A_MA13 VDD15 VDD16 M_ODT1 +VREF_CA
119 120 M_ODT1 6
A13 ODT1
CD3
1U_0402_6.3V6K
CD4
1U_0402_6.3V6K
CD5
1U_0402_6.3V6K
CD6
1U_0402_6.3V6K
DDR_CS1_DIMMA# 121 122

6 DDR_CS1_DIMMA#
2
S1# NC2
1 1 1 1 123 124
VDD17 VDD18 +VREF_CA
125 126
NCTEST VREF_CA
127 128
VSS27 VSS28
0.1U_0402_16V7K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36
1
2 2 2 2
2.2U_0603_6.3V6K
CD11
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37
CD10
133 134 1 1 RD4
DDR_A_DQS#4 VSS29 VSS30 1K_0402_1%
135 136
137 138
DQS4 VSS31 DDR_A_D38
139 140
2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_A_D44
145 146
B
DDR_A_D40 VSS34 DQ44 DDR_A_D45 B
147 148
DDR_A_D41 DQ40 DQ45
149 150
151 152
153 154
DM5 DQS5
155 156
157 158
Layout Note: 159
DQ43 DQ47
160
161 162
Place near JDIMM1 DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
Layout Note: Place these 4 Caps near Command 165
DQ49 DQ53
166
167 168
and Control signals of DIMMA DDR_A_DQS#6 169
VSS41 VSS42
170
171 172
DQS6 VSS43 DDR_A_D54
173 174
+1.5V DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DQ56 DQ61
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 DDR_A_D57 183 184

DQ57 VSS47
CD12
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
1 1 1 1 1 1 1 1 1 1 185 186 DDR_A_DQS#7

+ CD22 VSS48 DQS#7 DDR_A_DQS7
187 188
330U_B2_2.5VM_R15M DM7 DQS7
189 190
191 192
2 2 2 2 2 2 2 2 2 2 2 DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
RD5 1 VSS51 VSS52
2 10K_0402_5% 197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 200 PCH_SMBDATA 12,14,37,40
VDDSPD SDA
2.2U_0603_6.3V6K
0.1U_0402_16V7K
201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK 12,14,37,40
CD24
SGA00004400 1 1 203 204 +0.75VS

VTT1 VTT2
1
CD23
10K_0402_5%
RD6
205
G1 G2
206 0.6A@+0.75VS
DDR3 SO-DIMM A 2 2 LCN_DAN06-K4806-0102
CONN@
2
+1.5V
A A
Standard
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CD26
CD27
CD28
CD25
1 1 1 1
<Address(SA1,SA0):00>
@ @ @ @
2 2 2 2
LA-8711
Security Classification Compal Secret Data
DDRIII DIMM
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue C 0.1
LA-8041P
5 4 3 2 1
5 4 3 2 1
DDR3 SO-DIMM B
10/03 change to +V_DDR_REFB
+V_DDR_REFB +1.5V +1.5V
3.56A@+1.5V
JDDRL2
All VREF traces should +V_DDR_REFB 1 2
VREF_DQ VSS1 DDR_B_D4
have 20 mil trace width 3 4
VSS2 DQ4
0.1U_0402_16V7K
2.2U_0603_6.3V6K
CD29
DDR_B_D0 5 6 DDR_B_D5
6 DDR_B_D[0..63] DQ0 DQ5
CD50
1 1 DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
6 DDR_B_DQS[0..7] 9 10
VSS4 DQS#0 DDR_B_DQS0
11 12
D DM0 DQS0 D
6 DDR_B_DQS#[0..7] 13 14
2 2 DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 16
DDR_B_D3 DQ2 DQ6 DDR_B_D7
6 DDR_B_MA[0..15] 17 18
DQ3 DQ7
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 22
23 24
DQ9 DQ13
Delete DDR_B_DM[0..7] 25
VSS9 VSS10
26
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# 6,11
DQS1 RESET#
31 32
33 34
35 36
DQ11 DQ15
37 38
39 40
41 42
+1.5V DQ17 DQ21
43 44
DDR_B_DQS#2 VSS15 VSS16
45 46
DDR_B_DQS2 DQS#2 DM2
47 48
DQS2 VSS17
1
49 50 DDR_B_D22
RD12 DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 52
1K_0402_1% DDR_B_D19 DQ18 DQ23
53 54
+V_DDR_REFB DQ19 VSS19 DDR_B_D28
10/03 change to +V_DDR_REFB DDR_B_D24
55
57
VSS20 DQ28
56
58 DDR_B_D29
2
DDR_B_D25 DQ24 DQ29

59 60
61 62
63 64
DM3 DQS3
1
65 66
RD11 DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 68
1K_0402_1% DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 70
DQ27 DQ31
71 72
VSS25 VSS26
2
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB DDR_CKE1_DIMMB 6

6 DDR_CKE0_DIMMB CKE0 CKE1
75 76
VDD1 VDD2 DDR_B_MA15
77 78
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 80
BA2 A14
C 81 82 C
DDR_B_MA12 VDD3 VDD4 DDR_B_MA11
83 84
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 88
89 90
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 94
Layout Note: DDR_B_MA1
95
A3 A2
96
DDR_B_MA0
97 98
Place near JDIMM1.203 & JDIMM1.204 A1 A0
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
6 M_CLK_DDR2 101 102 M_CLK_DDR3 6
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
6 M_CLK_DDR#2 103 104 M_CLK_DDR#3 6
CK0# CK1# +1.5V
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
+0.75VS
11/18 for layout spacing: remove CD51/CD54/CD53 DDR_B_BS0
107
A10/AP BA1
108
DDR_B_RAS#
DDR_B_BS1 6
6 DDR_B_BS0 109 110 DDR_B_RAS# 6
BA0 RAS#
11/21 keep 1u*4 only -Kenny 111
VDD13 VDD14
112
1
6 DDR_B_WE# DDR_B_WE# 113 114 DDR_CS0_DIMMB# DDR_CS0_DIMMB# 6
DDR_B_CAS# WE# S0# M_ODT2 RD8
6 DDR_B_CAS# 115 116 M_ODT2 6
CAS# ODT0 1K_0402_1%
117 118
VDD15 VDD16 +VREF_CB
CD41
1U_0402_6.3V6K
CD51
1U_0402_6.3V6K
CD53
1U_0402_6.3V6K
CD48
1U_0402_6.3V6K
DDR_B_MA13 119 120 M_ODT3 M_ODT3 6

DDR_CS1_DIMMB# A13 ODT1
1 1 1 1 6 DDR_CS1_DIMMB# 121 122
2
S1# NC2
123 124
VDD17 VDD18 +VREF_CB
125
127
NCTEST
VSS27
VREF_CA
VSS28
126
128 10/03 change to +VREF_CB
2 2 2 2
0.1U_0402_16V7K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
1
2.2U_0603_6.3V6K
CD30
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37
CD55
133 134 1 1 RD10
DDR_B_DQS#4 VSS29 VSS30 1K_0402_1%
135 136
137 138
DQS4 VSS31 DDR_B_D38
139 140
2
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_B_D44
145 146
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 148
DDR_B_D41 DQ40 DQ45
149 150
151 152
153 154
DM5 DQS5
155 156
B
DDR_B_D42 VSS37 VSS38 DDR_B_D46 B
157 158
Layout Note: 159
DQ43 DQ47
160
161 162
Place near JDIMM1 DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
Layout Note: Place these 4 Caps near Command 165
DQ49 DQ53
166
167 168
and Control signals of DIMMA DDR_B_DQS#6 169
VSS41 VSS42
170
171 172
DQS6 VSS43 DDR_B_D54
173 174
+1.5V DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DQ56 DQ61
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 DDR_B_D57 183 184

DQ57 VSS47
CD37
CD46
CD45
CD40
CD42
CD56
CD44
CD43
CD47
CD39
1 1 1 1 1 1 1 1 1 1 185 186 DDR_B_DQS#7

+ CD36 VSS48 DQS#7 DDR_B_DQS7
187 188
330U_B2_2.5VM_R15M DM7 DQS7
189 190
191 192
2 2 2 2 2 2 2 2 2 2 2 DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
RD7 1 VSS51 VSS52
2 10K_0402_5% 197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 200 PCH_SMBDATA 11,14,37,40
VDDSPD SDA
2.2U_0603_6.3V6K
0.1U_0402_16V7K
201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK 11,14,37,40
CD38
SGA00004400 1 1 203 204 +0.75VS

VTT1 VTT2
1
CD31
10K_0402_5%
RD9
205
G1 G2
206 0.6A@+0.75VS
DDR3 SO-DIMM B 2 2 +3VS LCN_DAN06-K4406-0102
CONN@
2
+1.5V
10/05 change to PH. Standard

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CD33
CD34
CD35
CD32
A
1 1 1 1
<Address(SA1,SA0):10> A
@ @ @ @
2 2 2 2
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue Security Classification Compal Secret Data Compal Electronics, Inc.
DDRIII-DDRH
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
1 2 PCH_RTCX2
RH115 10M_0402_5%
Y2
1 2
32.768KHZ_12.5PF_CM31532768DZFT HDA_SYNC
18P_0402_50V8J
1 1 This signal has a weak internal pull-down

CH2 CH3 On Die PLL VR is supplied by
18P_0402_50V8J 1.5V when smapled high
2 2 +RTCBATT 1.8V when sampled low
D
Needs to be pulled High for Chief River platfrom D
RH116 1 2 SM_INTRUDER#
1M_0402_5% +3V_PCH
HDA_SYNC RH149 2 1 1K_0402_5%

UH1A
+RTCBATT PCH_RTCX1 A20 C38 LPC_AD0

1 RTCX1 FWH0 / LAD0 LPC_AD0 31,36
1
CMOS A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 31,36 +RTCVCC
LPC
DB# 11/1 Reserve 10pF by RF request CH4 CLRP1 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 31,36
1U_0603_10V4Z SHORT PADS C37 LPC_AD3
LPC_AD3 31,36
2
@ 2 PCH_RTCRST# FWH3 / LAD3
CH82 1 2 D20
RTCRST#
RH117 20K_0402_5% D36 LPC_FRAME# PCH_INTVRMEN RH124 2 1 330K_0402_5%
FWH4 / LFRAME# LPC_FRAME# 31,36
HDA_BIT_CLK1 2 1 2 PCH_SRTCRST# G22
RH118 20K_0402_5% SRTCRST# PCH_INTVRMEN RH126 @
1 LDRQ0# E36 2 1 330K_0402_5%
1
SM_INTRUDER#
RTC
K22 INTRUDER# LDRQ1# / GPIO23 K36
10P_0402_50V8J CH5 CLRP2
1U_0603_10V4Z SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 36
：
INTVRMEN
：
2
2 INTVRMEN SERIRQ
ME CMOS
CLP1 & CLP2 place near DIMM
* H Integrated VRM enable
L Integrated VRM disable
AM3 SATA_PRX_DTX_N0 33
HDA_BIT_CLK HDA_BIT_CLK SATA0RXN
38 HDA_BITCLK_AUDIO 1 2 N34
HDA_BCLK SATA0RXP AM1 SATA_PRX_DTX_P0 33 SATA HDD
RH119 33_0402_5%
SATA 6G
AP7 SATA_PTX_DRX_N0 33
+5VS HDA_SYNC SATA0TXN
L34 AP5 SATA_PTX_DRX_P0 33
HDA_RST# HDA_SYNC SATA0TXP +3VS
38 HDA_RST_AUDIO# 1 2
RH120 33_0402_5% 38 HDA_SPKR HDA_SPKR T10 AM10 SATA_PRX_DTX_N1 33
SPKR SATA1RXN
2
G
SATA1RXP AM8 SATA_PRX_DTX_P1 33

QH1 HDA_RST# K34 AP11 m-SATA SSD SERIRQ RH131 2 1 10K_0402_5%
HDA_RST# SATA1TXN SATA_PTX_DRX_N1 33
38 HDA_SYNC_AUDIO 1 2 HDA_SYNC_R 3 1 HDA_SYNC
SATA1TXP AP10 SATA_PTX_DRX_P1 33
RH121 33_0402_5% HDDHALT_LED# RH136 1 10K_0402_5%
S
2
SB000002X00 38 HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 33
BSS138W-7-F_SOT323-3 HDA_SDIN0 SATA2RXN SATA_LED# RH138
SATA2RXP
AD5 SATA_PRX_DTX_P2 33 2 1 10K_0402_5%
G34
HDA_SDIN1 SATA2TXN
AH5 SATA_PTX_DRX_N2 33 SATA ODD
1 2 RH158 1 2 SATA2TXP
AH4 SATA_PTX_DRX_P2 33
1M_0402_5% RH122 @ 0_0402_5% C34
HDA_SDIN2 +3VS
IHDA
C AB8 C
SATA3RXN
Follow intel ME update requirement A34
HDA_SDIN3 SATA3RXP
AB10
AF3
SATA3TXN HDA_SPKR RH139 @
AF1 2 1 1K_0402_5%
HDA_SDOUT HDA_SDOUT SATA3TXP
36 HDA_SDO 1 2 A36 HDA_SDO
RH123 0_0402_5% LOW=Default
SATA
Y7
SATA4RXN
SATA4RXP Y5 * HIGH=No Reboot
38 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT C36 AD3
RH125 33_0402_5% HDA_DOCK_EN# / GPIO33 SATA4TXN
AD1
SATA4TXP
N32
HDA_DOCK_RST# / GPIO13
Y3
SATA5RXN
Y1
SATA5RXP
AB3
HDA_SDO +3V_PCH
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TCK SATA5TXN
J3 JTAG_TCK SATA5TXP AB1 ME debug mode , this signal has a weak internal PD
PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA L=>security measures defined in the Flash HDA_SDOUT RH140 2 @ 1 1K_0402_5%
JTAG_TMS SATAICOMPO
1
JTAG
PCH_JTAG_TDI SATA_COMP Descriptor will be in effect (default)
@ RH127
200_0402_5%
@ RH128
200_0402_5%
@ RH129
200_0402_5%
K5
JTAG_TDI SATAICOMPI
Y10 1
RH130
2
37.4_0402_1% *Low = Disabled
High = Enabled
PCH_JTAG_TDO H1 H=>Flash Descriptor Security will be overridden
JTAG_TDO +1.05VS_SATA3
AB12
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI SATA3RCOMPO

AB13 SATA3_COMP 1 2
SATA3COMPI
1
RH132 49.9_0402_1%
RH133 RH134 RH135
100_0402_1% 100_0402_1% 100_0402_1% PCH_SPI_CLK T3 SPI_CLK SATA3RBIAS AH1 RBIAS_SATA3 1
RH137
2
750_0402_1%
RTC Battery
11/24 according RTC spec swap RTC to pin1
PCH_SPI_CS0# Y14
2
SPI_CS0#
T1 +RTCBATT
SPI_CS1#
SPI
2 1 PCH_JTAG_TCK P3 SATA_LED# SATA_LED# 35 +RTCVCC

51_0402_5% RH150 SATALED# 1K_0402_5%
+3VS
20mils ACES_50273-0020N-001
PCH_SPI_SI V4 V14 HDDHALT_LED# HDDHALT_LED# 35
SPI_MOSI SATA0GP / GPIO21 RH148
20mils DH1 10mils
PCH_SPI_SO U3 P1 BBS_BIT0_R R60 1 2 10K_0402_5% 2 2 1 1
SPI_MISO SATA1GP / GPIO19 1
W=20mils 1 2
2
1 3 +3VLP 3 G1
B PANTHER-POINT_FCBGA989 CH7 W=20mils 4 G2 B
1U_0603_10V4Z BAV70W 3P C/C_SOT-323
Place CH95 close to PCH.
2 JRTC1 CONN@
SPI ROM FOR ME (8MByte ) 8MByte SPI ROM PN SA000039A00

+3V_PCH &UH2 @ @
Should be ACES_50273-0020N-001_2P,need check
CH1 RH151
+3V_PCH +3V_SPI 2 1 1 2PCH_SPI_CLK
@ 33_0402_5%
RH141 1 2 PCH_SPI_CS0#_R UH2 CONN@ 22P_0402_50V8J
3.3K_0402_5% R213 1 2 0_0402_5% 8 4
PCH_SPI_WP# VCC VSS
RH145 1 2 @ 64M MX25L6405DZNI-12G WSON 8P Reserve for EMI please close to U48
3.3K_0402_5% PCH_SPI_WP# 3
W
RH144 1 2 PCH_SPI_HOLD#
3.3K_0402_5% PCH_SPI_HOLD# 7
+3V_SPI HOLD
+3V_SPI PCH_SPI_CS0# 1 2 PCH_SPI_CS0#_R 1
RH142 0_0402_5% S
20mils PCH_SPI_CLK 1 2 PCH_SPI_CLK_R 6
RH146 0_0402_5% C
1 1
CH6 PCH_SPI_SI 2 1 PCH_SPI_SI_R 5 2 PCH_SPI_SO_R 2 1PCH_SPI_SO
0.1U_0402_16V4Z CH8 RH147 0_0402_5% D Q 0_0402_5% RH143
22P_0402_50V8J 64M MX25L6405DZNI-12G WSON 8P
2 2
@
DB# 11/1 Reserve for RF please close to UH2
A A

PCH (1/8) SATA,HDA,SPI, LPC
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
+3V_PCH SMBDATA 1 2 +3V_PCH

UH1B RH152 2.2K_0402_5%
SMBCLK 1 2
RH153 2.2K_0402_5%
34 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 RH155 10K_0402_5% SML0CLK 1 2
PCIE_PRX_DTX_P1 PERN1
34 PCIE_PRX_DTX_P1 BJ34 E12 SMBALERT# 1 2 RH156 2.2K_0402_5%
CH37 PCIE_PTX_DRX_N1 PERP1 SMBALERT# / GPIO11 SML0DATA
PCIE LAN 34 PCIE_PTX_C_DRX_N1 1 2 0.1U_0402_10V7K AV32
PETN1 1 2
CH9 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 H14 SMBCLK RH157 2.2K_0402_5%
34 PCIE_PTX_C_DRX_P1 PETP1 SMBCLK SML1CLK 1 2
31 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 BE34 C9 SMBDATA RH159 2.2K_0402_5%
PCIE_PRX_DTX_P3 PERN2 SMBDATA SML1DATA
MiniWLAN ---> 31 PCIE_PRX_DTX_P3 BF34 PERP2
1 2
31 PCIE_PTX_C_DRX_N3 CH10 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 BB32 RH160 2.2K_0402_5%
CH11 1 PCIE_PTX_DRX_P3 PETN2
31 PCIE_PTX_C_DRX_P3 2 0.1U_0402_10V7K AY32
PETP2 DRAMRST_CNTRL_PCH GPIO74
SMBUS
A12 DRAMRST_CNTRL_PCH 6,9 1 RH263 2 10K_0402_5%
SML0ALERT# / GPIO60
BG36
PERN3 SML0CLK
D BJ36 C8 D
PERP3 SML0CLK DRAMRST_CNTRL_PCH
AV34 1 2
PETN3
AU34 G12 SML0DATA RH161 1K_0402_5%
PETP3 SML0DATA
BF36 RH176 1 2
PERN4 @ 1M_0402_5%
BE36
PERP4
AY34 C13 GPIO74 DB# 10/14 check to intel
PETN4 SML1ALERT# / PCHHOT# / GPIO74
BB34 PETP4
SML1CLK / GPIO58 E14 SML1CLK
PCI-E*
BG37 PERN5
BH37 M16 SML1DATA
PERP5 SML1DATA / GPIO75
AY36
PETN5
BB36
PETP5
BJ38 PERN6
BG38 PERP6
AU36 M7
Controller
PETN6 CL_CLK1
AV36 PETP6 CLKIN_DMI2# RH162 1 2 10K_0402_5%
Link
BG40 T11 CLKIN_DMI2 RH163 1 2 10K_0402_5%
PERN7 CL_DATA1 +3V_PCH CLKIN_DMI# RH164 10K_0402_5%
BJ40 1 2
PERP7 CLKIN_DMI RH165 10K_0402_5%
AY40 1 2
PETN7 CLKIN_DOT96# RH166 10K_0402_5%
BB40 P10 1 2
PETP7 CL_RST1#
1
CLKIN_DOT96 RH167 1 2 10K_0402_5%
BE38 RH8 CLKIN_SATA# RH168 1 2 10K_0402_5%
PERN8 CLKIN_SATA RH169 10K_0402_5%
BC38 10K_0402_5% 1 2
PERP8 CLK_PCH_14M RH170 10K_0402_5%
AW38 1 2
PETN8
AY38
2
PETP8
M10 PEG_CLKREQ#_R 2 1 If use extenal CLK gen, please place close to CLK gen
PEG_A_CLKRQ# / GPIO47 VGA_CLKREQ# 22
RH4 2 1 0_0402_5% PCIE_CD# Y40 0_0402_5% R286 else, please place close to PCH
34 CLK_PCIE_CD# CLKOUT_PCIE0N
Card Reader+ Giga LAn---> RH5 2 1 0_0402_5% PCIE_CD Y39
34 CLK_PCIE_CD CLKOUT_PCIE0P
RH171 AB37 CLK_VGA# 0_0402_5% 2 1 R275
CLKOUT_PEG_A_N CLK_PCIE_VGA# 21
1 2 10K_0402_5% J2 AB38 CLK_VGA 0_0402_5% 2 1 R276
CLOCKS
+3V_PCH PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA 21
34 LAN_CLKREQ#
CLK_PCIE_MINI1# AB49 AV22 CLK_CPU_DMI#_PCH RH172 1 2 0_0402_5% CLK_CPU_DMI#
31 CLK_PCIE_MINI1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5
C WLAN---> CLK_PCIE_MINI1 AB47 AU22 CLK_CPU_DMI_PCH RH173 1 2 0_0402_5% CLK_CPU_DMI C
31 CLK_PCIE_MINI1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
+3VS 2 RH175 1 10K_0402_5% M1

PCIECLKRQ1# / GPIO18
AM12 @ T1616 PAD~D
MINI1CLK_REQ# CLKOUT_DP_N @ T1628 PAD~D
31 MINI1_CLKREQ# CLKOUT_DP_P AM13
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
CLKIN_DMI_N BF18 CLKIN_DMI#
+3VS RH182 1 2 10K_0402_5% V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 CLKIN_DMI
Y37 BJ30 CLKIN_DMI2#

CLKOUT_PCIE3N CLKIN_GND1_N
Y36 BG30 CLKIN_DMI2
CLKOUT_PCIE3P CLKIN_GND1_P
+3V_PCH RH180 2 1 10K_0402_5% A8
PCIECLKRQ3# / GPIO25
G24 CLKIN_DOT96#
CLKIN_DOT_96N
CLKIN_DOT_96P E24 CLKIN_DOT96
Y43 +3VS +3VS
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
AK7 CLKIN_SATA#
CLKIN_SATA_N
+3V_PCH RH177 2 1 10K_0402_5% L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5 CLKIN_SATA
V45 K45 CLK_PCH_14M

CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P
2
+3V_PCH RH320 1 2 10K_0402_5% L14
PCIECLKRQ5# / GPIO44 H45 CLK_PCI_LPBACK CLK_PCI_LPBACK 16 RH186
CLKIN_PCILOOPBACK RH188
2.2K_0402_5%
2.2K_0402_5%
2
AB42 V47 XTAL25_IN 2N7002DWH_SOT363-6
1
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 V49
1
CLKOUT_PEG_B_P XTAL25_OUT SMBCLK 6 1 PCH_SMBCLK 11,12,37,40
+3V_PCH RH183 1 2 10K_0402_5% E6
PEG_B_CLKRQ# / GPIO56 QH2A
XTAL25_IN Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
XCLK_RCOMP RH184 90.9_0402_1% RH192 @
V40
XTAL25_OUT CLKOUT_PCIE6N
2 1 V42 1 2
CLKOUT_PCIE6P
5
1M_0402_5% RH187 +3VS 0_0402_5%
B B
+3V_PCH RH185 1 2 10K_0402_5% T13
PCIECLKRQ6# / GPIO45 SMBDATA 3 4 PCH_SMBDATA 11,12,37,40
2
V38 K43 @ T1615 PAD~D
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
V37 RH316 2N7002DWH_SOT363-6
CLKOUT_PCIE7P @ T1627 PAD~D UMA@ 10K_0402_5%
F47 QH2B
RH189 1 CLKOUTFLEX1 / GPIO65
+3V_PCH 2 10K_0402_5% K12 PCIECLKRQ7# / GPIO46
RH194
1
YH2 H47 @ T1629 PAD~D 1 2
1
CLKOUTFLEX2 / GPIO66
27P_0402_50V8J
27P_0402_50V8J
1 1 RH190 2 @ 1 0_0402_5% CLK_BCLK_ITP# AK14 0_0402_5%

OSC
OSC
7 CLK_RES_ITP# CLKOUT_ITPXDP_N
CH12 CH13 7 CLK_RES_ITP RH191 2 @ 1 0_0402_5% CLK_BCLK_ITP AK13 K49 DGPU_PRSNT# @
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
2
GND
GND
2 2 PANTHER-POINT_FCBGA989 RH318
PX@ 10K_0402_5%
2
1
+3VS +3VS
25MHZ_20PF_FSX3M-25.M20FDO @ @
RH193 CH14
CLK_PCH_14M 2 1 1 2
33_0402_5% 22P_0402_50V8J
Reserve for EMI please close to UH1
2
RH291
@ @ 2.2K_0402_5% RH311
RH195 CH15 2.2K_0402_5%
2
CLK_PCI_LPBACK 2 1 1 2 2N7002DWH_SOT363-6
1
33_0402_5% 22P_0402_50V8J
1
Reserve for EMI please close to SML1CLK 6 1 EC_SMB_CK2 22,36
UH1
QH6A
5
A A
SML1DATA 3 4 EC_SMB_DA2 22,36
2N7002DWH_SOT363-6
QH6B

PCH (2/8) PCIE, SMBUS, CLK
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
UH1C
4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
4 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 4
4 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 4
4 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 4
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4
BC12 FDI_CTX_PRX_N4 4
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5
4 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 4
DMI_CTX_PRX_P1 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6
4 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 4
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
4 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 4
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7
4 DMI_CTX_PRX_P3 BJ20
DMI3RXP FDI_CTX_PRX_P0
BG14 FDI_CTX_PRX_P0 4
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1
4 DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 4
D DMI_CRX_PTX_N1 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P2 D
4 DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 4
DMI_CRX_PTX_N2 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P3
4 DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 4
DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4
4 DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 4
DMI3TXN FDI_RXP4
DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
4 DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 4
DMI_CRX_PTX_P1 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P7
4 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 4
DMI_CRX_PTX_P2 DMI1TXP FDI_RXP7
4 DMI_CRX_PTX_P2 AY18
DMI_CRX_PTX_P3 DMI2TXP
4 DMI_CRX_PTX_P3 AU18
DMI3TXP FDI_INT
AW16 FDI_INT 4
FDI_INT
+1.05VS BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4
RH196 49.9_0402_1%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 4
RH197 750_0402_1%
4mil width and place FDI_LSYNC1
BB10 FDI_LSYNC1
FDI_LSYNC1 4
within 500mil of the PCH
@
SUSWARN# 1 2 SUSACK#_R A18 DSWODVREN
RH198 0_0402_5% DSWVRMEN
1 RH199 2 0_0402_5% PCH_RSMRST#
System Power Management

36 SUSACK# 1 2 SUSACK#_R C12 E22 PCH_DPWROK PCH_DPWROK 36
RH200 0_0402_5% SUSACK# DPWROK UH1D
5 XDP_DBRESET# XDP_DBRESET# K3 B9 WAKE# 1 2 PCH_PCIE_WAKE# 34 36 ENBKL ENBKL J47 AP43

SYS_RESET# WAKE# RH201 0_0402_5% L_BKLTEN SDVO_TVCLKINN
32 PCH_ENVDD M45 AP45
L_VDD_EN SDVO_TVCLKINP
5 SYS_PWROK SYS_PWROK 1 2 P12 N3 PM_CLKRUN# 32 DPST_PWM P45 AM42
RH202 0_0402_5% SYS_PWROK CLKRUN# / GPIO32 L_BKLTCTL SDVO_STALLN
AM40
PCH_LCD_CLK SDVO_STALLP
32 PCH_LCD_CLK T40
C PCH_PWROK1 PM_PWROK_R SUS_STAT# T38 PAD~D PCH_LCD_DATA L_DDC_CLK C
36 PCH_PWROK 2 L22 G8 32 PCH_LCD_DATA K47 AP39
RH203 0_0402_5% PWROK SUS_STAT# / GPIO61 L_DDC_DATA SDVO_INTN
AP40
CTRL_CLK SDVO_INTP
T45
SUSCLK CTRL_DATA L_CTRL_CLK
1 2 L10 N14 2 1 SUSCLK_R 36 P39
RH204 0_0402_5% APWROK SUSCLK / GPIO62 RH205 0_0402_5% L_CTRL_DATA
LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK PCH_DDPB_CLK 29
5 PM_DRAM_PWRGD PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PM_SLP_S5# 36 PAD~D T37 AF36 M39
DRAMPWROK SLP_S5# / GPIO63 LVD_VBG SDVO_CTRLDATA PCH_DDPB_DAT 29
1 2LVD_VREF AE48
PCH_RSMRST# RH207 0_0402_5% LVD_VREFH
36 PCH_RSMRST# 1 2PCH_RSMRST#_R C21 H4 PM_SLP_S4# PM_SLP_S4# 36 AE47 AT49
RH206 0_0402_5% RSMRST# SLP_S4# LVD_VREFL DDPB_AUXN
AT47
DDPB_AUXP
AT40 PCH_DDPB_HPD 29
DDPB_HPD
36 SUSWARN# 1 2 SUSWARN#_R K16 F4 PM_SLP_S3#
PM_SLP_S3# 36 32 PCH_TXCLK-
PCH_TXCLK- AK39
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# LVDSA_CLK#
LVDS
RH208 0_0402_5% PCH_TXCLK+ AK40 AV42 PCH_DPB_N2 29
32 PCH_TXCLK+ LVDSA_CLK DDPB_0N
AV40 PCH_DPB_P2 29
DDPB_0P
36 PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10 SLP_A# 36 32 PCH_TXOUT0-
PCH_TXOUT0- AN48 AV45 PCH_DPB_N1 29 HDMI
RH209 0_0402_5% PWRBTN# SLP_A# PCH_TXOUT1- LVDSA_DATA#0 DDPB_1N
32 PCH_TXOUT1- AM47 AV46 PCH_DPB_P1 29
LVDSA_DATA#1 DDPB_1P
Digital Display Interface

PCH_TXOUT2- AK47 AU48 PCH_DPB_N0 29
32 PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N
22,36,48 ACIN 1 2 ACIN_R H20 G16 PM_SLP_SUS# PM_SLP_SUS# 36 AJ48 AU47 PCH_DPB_P0 29
DH2 CH751H-40PT_SOD323-2 ACPRESENT / GPIO31 SLP_SUS# LVDSA_DATA#3 DDPB_2P
AV47 PCH_DPB_N3 29
PCH_TXOUT0+ DDPB_3N
32 PCH_TXOUT0+ AN47 AV49 PCH_DPB_P3 29
GPIO72 H_PM_SYNC PCH_TXOUT1+ LVDSA_DATA0 DDPB_3P
E10 AP14 H_PM_SYNC 5 32 PCH_TXOUT1+ AM49
BATLOW# / GPIO72 PMSYNCH PCH_TXOUT2+ LVDSA_DATA1
32 PCH_TXOUT2+ AK49
LVDSA_DATA2
AJ47 P46
RI# PCH_GPIO29 LVDSA_DATA3 DDPC_CTRLCLK
A10 K14 P42
RI# SLP_LAN# / GPIO29 DDPC_CTRLDATA
AF40
+3V_PCH PANTHER-POINT_FCBGA989 LVDSB_CLK#
AF39 AP47
Check EC for S3 S4 LED LVDSB_CLK DDPC_AUXN
AP49
DDPC_AUXP
AH45 AT38
PCH_GPIO29 RH228 1 LVDSB_DATA#0 DDPC_HPD
2 10K_0402_5% AH47
PCH_PWROK PCH_RSMRST# LVDSB_DATA#1
2 1 AF49 AY47
B RH210 1 LVDSB_DATA#2 DDPC_0N B
GPIO72 2 10K_0402_5% D30 CH751H-40PT_SOD323-2 AF45 AY49
+RTCVCC LVDSB_DATA#3 DDPC_0P
AY43
RH211 1 DDPC_1N
RI# 2 10K_0402_5% AH43 AY45
LVDSB_DATA0 DDPC_1P
WAKE# RH212 1 2 10K_0402_5% DSWODVREN RH213 2 1 330K_0402_5%
47,49 SPOK
D29
1 2
CH751H-40PT_SOD323-2
AH49
AF47
LVDSB_DATA1 mDP DDPC_2N
BA47
BA48
LVDSB_DATA2 DDPC_2P
AF43 BB47
ACIN_R RH214 1 LVDSB_DATA3 DDPC_3N
2100K_0402_5% DSWODVREN RH215 2 1 330K_0402_5% BB49
@ DDPC_3P
SUSWARN# RH216 1 2 10K_0402_5%
*：
DSWODVREN - On Die DSW VR Enable PCH_CRT_B N48 M43
：
30 PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
H Enable 30 PCH_CRT_G
PCH_CRT_G P49 M36
PCH_RSMRST# RH217 1 L Disable CRT_GREEN DDPD_CTRLDATA
2 10K_0402_5% 30 PCH_CRT_R
PCH_CRT_R T49
CRT_RED
AT45
DDPD_AUXN
CRT
PCH_CRT_CLK T39 AT43
30 PCH_CRT_CLK CRT_DDC_CLK DDPD_AUXP
PCH_CRT_DATA M40 BH41
30 PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD
C268 @ BB43
PCH_PWROK +3VS PCH_CRT_HSYNC DDPD_0N
1 2 30 PCH_CRT_HSYNC M47 BB45
100P_0402_50V8J PCH_CRT_VSYNC CRT_HSYNC DDPD_0P
30 PCH_CRT_VSYNC M49
CRT_VSYNC DMC DDPD_1N BF44
BE44
DDPD_1P
BF42
CRT_IREF DDPD_2N
T43 BE42
DAC_IREF DDPD_2P
T42 BJ42
+3VS RH218 CRT_IRTN DDPD_3N
1 2 8.2K_0402_5% PM_CLKRUN# PM_CLKRUN# EC Request BG42
DDPD_3P
1
RH219 1 2 2.2K_0402_5% CTRL_CLK on 20110309 PANTHER-POINT_FCBGA989
5
UH3 RH220
1
RH221 1 2 2.2K_0402_5% CTRL_DATA 1K_0402_0.5%

VCC
PCH_PWROK 1 RH308
2
IN1 SYS_PWROK
4 10K_0402_5%
OUT
2
GND
A
55 VGATE IN2 A
@
2
MC74VHC1G08DFT2G_SC70-5
3
1 2 LVDS_IBG
RH222 2.37K_0402_1%
RH223 2 1 10K_0402_5% SYS_PWROK 1 2 PCH_ENVDD
RH224 100K_0402_5%
1 2 ENBKL
RH225 100K_0402_5% 2011/11/02 2011/11/02 Title
Issued Date Deciphered Date
PCH (3/8) DMI,FDI,PM,GFX,DP
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
UH1E
RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25 TP3
BJ16 TP4 RSVD5 AT10
BG16 TP5 RSVD6 BC8
AH38 TP6
AH37 TP7 RSVD7 AU2
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3
C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
H3 TP12 RSVD12 AT5
D AH12 AV3 D
TP13 RSVD13
AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8
RSVD
RSVD21 BD4
RSVD22 BF6
B21 TP21 RSVD23 AV5

M20 TP22 RSVD24 AV10
AY16 TP23
BG46 TP24 RSVD25 AT8
RSVD26 AY5
RSVD27 BA2
35 USB3_RX1_N BE28 USB3Rn1
35 USB3_RX2_N BC30 USB3Rn2 RSVD28 AT12
35 USB3_RX3_N BE32 USB3Rn3 RSVD29 BF3
BJ32 USB3Rn4
35 USB3_RX1_P BC28 USB3Rp1
35 USB3_RX2_P BE30 USB3Rp2
35 USB3_RX3_P BF32 USB3Rp3
USB3.0 x3 BG32 C24 USB20_N0
USB3Rp4 USBP0N USB20_N0 35
AV26 A24 USB20_P0 To USB3.0 connector
35 USB3_TX1_N USB3Tn1 USBP0P USB20_P0 35
BB26 C25 USB20_N1
35 USB3_TX2_N USB3Tn2 USBP1N USB20_N1 35
35 USB3_TX3_N AU28 USB3Tn3 USBP1P B25 USB20_P1
USB20_P1 35
(Port 0 & 1 & 2)
AY30 C26 USB20_N2
USB3Tn4 USBP2N USB20_N2 35
AU26 A26 USB20_P2
35 USB3_TX1_P USB3Tp1 USBP2P USB20_P2 35
AY26 K28 USB20_N3
C 35 USB3_TX2_P USB3Tp2 USBP3N USB20_N3 42 C
AV28 H28 USB20_P3 USB2.0 Finger Print (Port 3)
35 USB3_TX3_P USB3Tp3 USBP3P USB20_P3 42
AW30 USB3Tp4 USBP4N E28
USBP4P D28
USBP5N C28
USBP5P A28
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28
PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 32
PCI_PIRQD# G38 K30 USB20_P8 Camera
PIRQD# USBP8P USB20_P8 32
G30 USB20_N9
USBP9N USB20_N9 35
21 DGPU_HOLD_RST# DGPU_HOLD_RST# C46 E30 USB20_P9 USB2.0 and sleep charger(Port 9)
REQ1# / GPIO50 USBP9P USB20_P9 35
USB
DGPU_SELECT# C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 31
23,53,54,56 PXS_PWREN PXS_PWREN E40 A30 USB20_P10 mPCIE-WLAN/BT
REQ3# / GPIO54 USBP10P USB20_P10 31
USBP11N L32
GPIO51 D47 K32
GPIO53 GNT1# / GPIO51 USBP11P +3V_PCH
E42 GNT2# / GPIO53 USBP12N G32
31 WL_OFF# WL_OFF# F46 E32
GNT3# / GPIO55 USBP12P RPH1
USBP13N C32
A32 USB_OC3# 4 5
ACCEL_INT# USBP13P USB_OC2#
42 ACCEL_INT# G42 PIRQE# / GPIO2 3 6
ODD_DA# G40 Within 500 mils 35 USB_OC0# USB_OC0# 2 7
33 ODD_DA# PIRQF# / GPIO3
DP_CBL_DET C42 C33 USBRBIAS 1 2 USB_OC1# 1 8
PIRQH# PIRQG# / GPIO4 USBRBIAS#
DB# 10/20 move ACCEL_INT# to PCH_GPIO_02. D44 PIRQH# / GPIO5
RH229 22.6_0402_1%
PCH_GPIO_03 is reserved for ODD_DA# 10K_1206_8P4R_5%
B33 RPH2
AOAC_PME# PCH_AOAC_PME# USBRBIAS USB_OC4#
36 AOAC_PME# 1 2 K10 PME# 4 5
RH274 0_0402_5% USB_OC6# 3 6
5,21,31,34,36 PLT_RST# PLT_RST# C6 A14 USB_OC0# USB_OC7# 2 7
PLTRST# OC0# / GPIO59 USB_OC1# USB_OC5#
OC1# / GPIO40 K20 1 8
B17 USB_OC2#
B CLK_PCI_LPBACK RH230 OC2# / GPIO41 B
14 CLK_PCI_LPBACK 2 1 22_0402_5% CLK_PCI0 H49 CLKOUT_PCI0 OC3# / GPIO42 C16 USB_OC3# 10K_1206_8P4R_5%
CLK_PCI_LPC RH231 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#
36 CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
CLK_PCI_DEBUG RH242 1 2 22_0402_5% CLK_PCI2 J48 A16 USB_OC5#
31 CLK_PCI_DEBUG CLKOUT_PCI2 OC5# / GPIO9
K42 D14 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
H40 CLKOUT_PCI4 OC7# / GPIO14 C14
+3VS
PANTHER-POINT_FCBGA989
RPH3
DP_CBL_DET 1 8 DB# 11/1 Reserve 10pF by RF request
PCI_PIRQD# 2 7
PCI_PIRQB# 3 6 @
CH83
PCI_PIRQC# 4 5
CLK_PCI1 1 2
8.2K_0804_8P4R_5%
RPH4 10P_0402_50V8J
PIRQH# 1 8 +3VS 1 2
GPIO53 2 7 RH232 0_0402_5%
ODD_DA# 3 6
2
GPIO51 4 5 @ +3VS
RH233
8.2K_0804_8P4R_5% 10K_0402_5%
5
@UH4
1
RH7 1 PLT_RST#
P
PCI_PIRQA# IN1
1 2 8.2K_0402_5% 31 PLT_RST_BUF# 4 O
IN2 2
G
ACCEL_INT# 1 RH6 2 8.2K_0402_5%

1
SN74AHC1G08DCKR_SC70-5
3
RH234 @
A DGPU_HOLD_RST# @1 RH235 2 10K_0402_5% 100K_0402_5% A
2
DGPU_SELECT# 1 RH236 2 10K_0402_5%
PXS_PWREN 1 RH237 2 10K_0402_5%
WL_OFF# 1 RH302 2 10K_0402_5%

PCH (4/8) PCI, USB, NVRAM
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
+3VS
11/24 Kirk review need pu +3VS; but not in check list.
2
UH1F RH280
10K_0402_5%
GPIO0 T7 C40 ODD_EN#
36 GPIO0 BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 33
1
GPIO1 A42 B41
TACH1 / GPIO1 TACH5 / GPIO69
GPIO6 H36 C41 +3VS
36 EC_SCI# EC_SCI# E38 A40

2
D D
GPIO28 36 EC_SMI# EC_SMI# C10 RH238
GPIO8
10K_0402_5%
On-Die PLL Voltage Regulator DMC_DET# C4 LAN_PHY_PWR_CTRL / GPIO12
1
This signal has a weak internal pull up 2 1 EC_LID_OUT#_R G2 P4
* ：On-Die voltage regulator enable

36 EC_LID_OUT# GPIO15 A20GATE GATEA20 36
RH154 0_0402_5%
H AU16 PCH_PECI_R 1 @ 2
L：On-Die PLL Voltage Regulator disable

PECI H_PECI 5,36
PCH_GPIO16 U2 0_0402_5% RH239
SATA4GP / GPIO16 EC_KBRST# +1.8VS
RCIN# P5 EC_KBRST# 36
GPIO
56 VGA_PWRGD VGA_PWRGD D40 AY11
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5
1
+3V_PCH
CPU/MISC
PCH_GPIO22 T5 AY10 H_THERMTRIP#_C 1 2 H_THEMTRIP# H_THEMTRIP# 5 RH226
SCLOCK / GPIO22 THRMTRIP#
1 2 SLP_ME_CSW_DEV# 390_0402_5% RH240 2.2K_0402_5%
RH267 10K_0402_5% DDR3L_EN E8 T14
51 DDR3L_EN GPIO24 INIT3_3V#
2
PCH_GPIO27 E16 AY1 NV_CLE 2 1 H_SNB_IVB# 5
GPIO27 DF_TVS
1 2 SLP_ME_CSW_DEV# RH227 1K_0402_5%
RH241 1K_0402_5% SLP_ME_CSW_DEV# P8
36 SLP_ME_CSW_DEV# GPIO28 Layout note: CLOSE TO THE BRANCHING POINT
@ TS_VSS1 AH8
31 BT_ON# BT_ON# K1 STP_PCI# / GPIO34
TS_VSS2 AK11
PCH_GPIO35 K4 GPIO35
TS_VSS3 AH10
ODD_DETECT# V8
33 ODD_DETECT# SATA2GP / GPIO36
TS_VSS4 AK10
PCH_GPIO37 M5 SATA3GP / GPIO37
DB# 10/20 Common BT_ON is GPIO 34
PCH_GPIO37 (Rout to GPIO 38 currently), GPIO 38 pull PCH_GPIO38 N2 SLOAD / GPIO38 NC_1 P37
FDI TERMINATION VOLTAGE OVERRIDE high 10K to 3VS only
PCH_GPIO39 M3
C SDATAOUT0 / GPIO39 C
LOW - Tx, Rx terminated
* to same voltage PCH_GPIO48 V13 SDATAOUT1 / GPIO48 VSS_NCTF_15 BG2 +3VS
(DC Coupling Mode)
GPIO49 V3 BG48 ODD_EN# 1 RH310 2 10K_0402_5%
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
+3VS HDD_DETECT# D6 BH3 GPIO6 1 RH243 2 10K_0402_5%
33 HDD_DETECT# GPIO57 VSS_NCTF_17
BH47 GPIO1 1 RH244 2 10K_0402_5%
RH245 @ VSS_NCTF_18
2 1 1K_0402_5% PCH_GPIO37
A4 BJ4 EC_KBRST# 1 RH295 2 10K_0402_5%
VSS_NCTF_1 VSS_NCTF_19
RH246 2 1 PCH_GPIO37 A44 BJ44 PCH_GPIO35 1 RH273 2 10K_0402_5%
100K_0402_5% A45 BJ45 PCH_GPIO16 1 RH247 2 10K_0402_5%
NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

GPIO27
A6 BJ6 +3V_PCH
PCH_GPIO27 (Have internal Pull-High)
B3 C2 DDR3L_EN 1 2 10K_0402_5%
*High: VCCVRM VR Enable
Low: VCCVRM VR Disable
HDD_DETECT#
@ RH248
B47 VSS_NCTF_8 VSS_NCTF_26 C48 1 2 10K_0402_5%
RH249
1 2 PCH_GPIO27 BD1 D1 DMC_DET# 1 2 10K_0402_5%
@ RH250 10K_0402_5% VSS_NCTF_9 VSS_NCTF_27 RH251
BD49 D49 EC_LID_OUT#_R 1 2 1K_0402_5%
VSS_NCTF_10 VSS_NCTF_28 RH252
BE1 E1 EC_SMI# 1 2 10K_0402_5%
VSS_NCTF_11 VSS_NCTF_29 @ RH253
BE49 VSS_NCTF_12 VSS_NCTF_30 E49
B B
DB# 10/20 Reserve GPIO 36 pull up resistor BF1 VSS_NCTF_13 VSS_NCTF_31 F1
and add pull down resistor
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
DB# 11/23 pull up +3VS for ODD_detect#
+3VS
PANTHER-POINT_FCBGA989
+3VS
10K_0402_5% 2 1 ODD_DETECT# GPIO0 RH254 1 2 10K_0402_5%

RH301
10K_0402_5% 2 1 ODD_DETECT# PCH_GPIO38 1 2 10K_0402_5%

@ RH255 RH256
PCH_GPIO48 1 2 10K_0402_5%
RH257
PCH_GPIO22 1 2 10K_0402_5%
RH258
BT_ON# 1 2 10K_0402_5%
RH259
PCH_GPIO39 1 2 10K_0402_5%
RH260
VGA_PWRGD 1 2 10K_0402_5%
RH261
GPIO49 1 2 10K_0402_5%
RH262
A A

PCH (5/8) GPIO, CPU, MISC
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
+1.05VS PCH Power Rail Table

UH1G POWER +3VS S0 Iccmax
Voltage Rail Voltage Current (A)
1300mA LH1
0.01U_0402_16V7K
0.1U_0402_10V7K
AA23 1mA VCCADAC U48 +VCCADAC 2 1
VCCCORE[1]
AC23
VCCCORE[2] 1 1 1 BLM18PG181SN1D_2P V_PROC_IO 1.05 0.001
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 AD21
CRT
VCCCORE[3]
CH20
CH21
AD23 U47 CH22
VCCCORE[4] VSSADAC
CH18
CH19
CH16
CH17 AF21 10U_0603_6.3V6M V5REF 5 0.001
VCC CORE
10U_0603_6.3V6M VCCCORE[5] 2 2 2
AF23 VCCCORE[6]
D 2 2 2 2
AG21 +3VS D
VCCCORE[7]
AG23 VCCCORE[8]
V5REF_Sus 5 0.001
AG24 VCCCORE[9]
1mA VCCALVDS AK36
AG26
VCCCORE[10] +1.8VS
AG27
VCCCORE[11] VSSALVDS
AK37 Vcc3_3 3.3 0.266
AG29 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[12]
22U_0805_6.3V6M
AJ23
VCCCORE[13] Near AP43 LH2
LVDS
AJ26 AM37 +VCCTX_LVDS 2 1 VccADAC 3.3 0.001
VCCCORE[14] VCCTX_LVDS[1] CH23 1
AJ27 VCCCORE[15] 1 1
CH25
AJ29 AM38 0.1uH inductor, 200mA
VCCCORE[16] VCCTX_LVDS[2]
AJ31
VCCCORE[17]
CH24 VccADPLLA 1.05 0.08
60mAVCCTX_LVDS[3] AP36 0.01U_0402_16V7K
0.01U_0402_16V7K2 2 2
VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.08

+1.05VS +1.05VS AN19
VCCIO[28]
VccCore 1.05 1.3
2 1 +VCCAPLLEXP BJ22
RH264 0_0603_5% VCCAPLLEXP RH265
10U_0805_4VAM
@ 1 V33 +3VS_VCC3_3_6 1 2 +3VS VccDMI 1.05 0.042
VCC3_3[6]
Place CH35 Near AP19 pin
HVCMOS
AN16 0_0805_5%
VCCIO[15]
CH27
1
AN17 VCCIO[16]
VccIO 1.05 2.925
2 CH26
VCC3_3[7] V34
@ 0.1U_0402_10V7K
+1.05VS 2 VccASW 1.05 1.01
AN21 VCCIO[17]
AN26 VCCIO[18]
RH297 VccSPI 3.3 0.02
1 2 +1.05VS_VCC_EXP AN27 2925mA AT16 +VCCAFDI_VRM
0_0805_5% VCCIO[19] VCCVRM[3] +VCCP_VCCDMI
+1.05VS
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 AP21 VCCIO[20]
20mA RH266 VccDSW 3.3 0.003
C C
CH28
CH29
CH30
CH31
CH32
AP23 AT20 +VCCP_VCCDMI 1 2

VCCIO[21] VCCDMI[1]
1 VccpNAND 1.8 0.19
2 2 2 2 2
DMI
AP24 0_0805_5%
VCCIO[22] RH314
VCCIO
+3VS CH33
AP26 AB36 +1.05VS_VCC_DMI_CCI 1 2 +1.05VS VccRTC 3.3 6 uA
VCCIO[23] VCCCLKDMI 2 1U_0402_6.3V6K
1
AT24 0_0805_5%
VCCIO[24] CH34 VccSus3_3 3.3 0.119
1U_0402_6.3V6K
1
AN33 2
VCCIO[25]
RH268 VccSusHDA 3.3 / 1.5 0.01
0_0805_5% AN34 VCCIO[26] AG16
VCCDFTERM[1] +VCCPNAND
VccVRM 1.8 / 1.5 0.16
2
+3VS_VCCA3GBG BH29 AG17 1 2

VCC3_3[3] VCCDFTERM[2] +1.8VS
RH269 0_0805_5%
DFT / SPI
1
0.1U_0402_10V7K
+1.05VS CH35 VccCLKDMI 1.05 0.02
AJ16 1
VCCDFTERM[3]
0.1U_0402_10V7K 190mA
2
CH36
+VCCAFDI_VRM AP16 VccSSC 1.05 0.095
VCCVRM[2]
Place CH53 Near AP13,AP15 pin VCCDFTERM[4]
AJ17
2
2 1 +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
RH270 0_0603_5% VccAFDIPLL
@ RH271
+1.05VS 1 2 +1.05VS_VCCDPLL_FDIAP17 VCCIO[27]
RH272 VccALVDS 3.3 0.001
0_0805_5% V1 +3V_VCCPSPI 1 2
FDI
VCCSPI +3V_PCH
20mA 0_0805_5%
+VCCP_VCCDMI AU20
VCCDMI[2] 1 VccTX_LVDS 1.8 0.06
CH38
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2
11/24 change +1.5VS to 1.5VPCIEV +VCCAFDI_VRM
2 RH275
1 +VCCAFDI_VRM
1.5VPCIEV
0_0603_5%
A A

PCH (6/8) PWR
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
VCC3_3 = 266mA detal waiting for newest spec

VCCDMI = 42mA detal waiting for newest spec
+1.05VS
+5VALW +5V_PCH
2 @ 1 +VCCACLK
+3V_PCH RH276 0_0603_5%
UH1J POWER
1 2 2 1@ RH278
RH277 0_0603_5% 1 AD49 N26 +1.05VS_VCCUSBCORE 2 1 0_0603_5%
VCCACLK VCCIO[29] +1.05VS
CH39 RH285 0_0603_5%
D
P26 1 3 1
VCCIO[30]
0.1U_0402_10V7K
+VCCPDSW T16 QH3
D 0.1U_0402_10V7K 2 VCCDSW3_33mA CH40 AO3413_SOT23 D
P28
VCCIO[31]
1
1U_0402_6.3V6K
G
1
2
+1.05VS LH3 +PCH_VCCDSW V12 T27 2 RH279
DCPSUSBYP VCCIO[32]
CH41
10UH_LB2012T100MR_20% 1 20K_0402_5%
1 2 T29 43 PCH_PWR_EN#
@ CH42 +3VS_VCC_CLKF33 VCCIO[33] 2
T38
2
VCC3_3[5]
10U_0805_10V4Z
1 0.1U_0402_10V7K
@ @ 2 T23 +3V_VCCPUSB 2 1
+1.05VS 119mA VCCSUS3_3[7] +3V_PCH
CH43
0.1U_0402_10V7K
+VCCAPLL_CPY_PCH BH23 RH281 0_0603_5%
VCCAPLLDMI2 +3V_VCCAUBG
T24 1 2 1 +3V_PCH
2 VCCSUS3_3[8] +5V_PCH +3V_PCH
0.1U_0402_10V7K
1 2 +VCCDPLL_CPY AL29 RH282 0_0603_5%
VCCIO[14]
CH44
RH283 0_0603_5% V23 1
VCCSUS3_3[9]
USB
2
2
CH47
+VCCSUS1 AL24 V24 +VCCA_USBSUS
DCPSUS[3] VCCSUS3_3[10]
1U_0402_6.3V6K
1 RH284
CH45 2 100_0402_5% DH3
P24 1
@ VCCSUS3_3[6]
CH48
1U_0402_6.3V6K AA19 CH751H-40PT_SOD323-2
1
2 VCCASW[1] +1.05VS_VCCAUPLL @ +PCH_V5REF_SUS
VCCIO[34] T26 2 1 +1.05VS
+1.05VS 1010mA RH286 0_0603_5% 2
AA21 1
VCCASW[2]
22U_0805_6.3V6M
22U_0805_6.3V6M
2 @ 1 +1.05VM_VCCSUS AA24 M26 +PCH_V5REF_SUS CH49
R407 0_0603_5% VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2 1 +3V_PCH 2
0.1U_0402_10V7K
CH50
CH51
1 AA26 RH287 0_0603_5%
Clock and Miscellaneous

VCCASW[4]
AN23 +VCCA_USBSUS 1
@ C262 DCPSUS[4]
AA27 VCCASW[5]
2 2
CH52
1U_0402_6.3V6K AN24 +3V_VCCPSUS_1
2 VCCSUS3_3[1]
AA29 VCCASW[6] 2
AA31 +5VS +3VS
RH307 VCCASW[7]
2 1 +VCCP_VCCASW AC26 P34 +PCH_V5REF_RUN
+1.05VS VCCASW[8] 1mA V5REF
2
C C
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 RH289
0_0805_5% AC27 0_0603_5% RH288
VCCASW[9]
CH53
CH54
CH55
N20 +3V_VCCPSUS 2 1 +3V_PCH 100_0402_5% DH4
VCCSUS3_3[2]
PCI/GPIO/LPC
AC29 VCCASW[10]
1
2 2 2 N22 CH56 CH751H-40PT_SOD323-2
1
VCCSUS3_3[3] 1U_0402_6.3V6K +PCH_V5REF_RUN
AC31 VCCASW[11]
P20 +3VS
1
2
+3VS VCCSUS3_3[4]
AD29 VCCASW[12]
P22 +3VS_VCCPCORE 2 1 CH57
RH313 0_0805_5% VCCSUS3_3[5] RH290 0_0805_5% 1U_0603_10V6K
AD31 1
VCCASW[13] 2
2 1
W21 AA16 CH58
VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K
W23 W16 2 +3VS
LH4 +3VS_VCC_CLKF33 VCCASW[15] VCC3_3[8]
1 2
1U_0402_6.3V6K
1 1 W24 T34 +3VS_VCCPPCI 2 1

10UH_LB2012T100MR_20% VCCASW[16] VCC3_3[4] RH292 0_0603_5%
1
CH61
@ CH59 W26 VCCASW[17] CH60

10U_0603_6.3V6M 2 2 W29 +3VS 0.1U_0402_10V7K
VCCASW[18] RH293 2
W31 AJ2 +VCC3_3_2 2 1
VCCASW[19] VCC3_3[2] +1.05VS_SATA3
1
W33 0_0603_5% RH294
VCCASW[20] CH62
VCCIO[5] AF13 2 1 +1.05VS
0.1U_0402_10V7K 1
+VCCRTCEXT 2 0_0805_5%
N16 DCPRTC
1 AH13 CH63
VCCIO[12] 1U_0402_6.3V6K
CH64 +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
+1.05VS 0.1U_0402_10V7K VCCVRM[4] VCCIO[13]
2
B +VCCDIFFCLK LH5 B
2 1 VCCIO[6] AF14
RH296 0_0603_5% 1 +1.05VS_VCCA_A_DPL BD47 10UH_LB2012T100MR_20%
VCCADPLLA80mA
SATA
CH65 AK1 +VCCSATAPLL 1 2
VCCAPLLSATA +1.05VS
+1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM @
1U_0402_6.3V6K VCCADPLLB80mA
2 1
+1.05VS +1.05VS_VCCDIFFCLKN AF11 +VCCAFDI_VRM CH66
VCCVRM[1] 10U_0805_10V4Z
AF17
+1.05VS_VCCDIFFCLKN VCCIO[7] +1.05VS_VCC_SATA
2 1 AF33
VCCDIFFCLKN[1]
RH299 @ Place CH73 Near AK1 pin
RH298 0_0603_5% 1 AF34 55mA AC16 +1.05VS_VCC_SATA 2 1 2
VCCDIFFCLKN[2] VCCIO[2] +1.05VS
AG34 VCCDIFFCLKN[3]
1U_0402_6.3V6K
CH67 AC17 1 0_0805_5%
1U_0402_6.3V6K VCCIO[3]
+1.05VS 2
CH68
+1.05VS_SSCVCC AG33 AD17
VCCSSC95mA VCCIO[4]
2 1 2
RH300 0_0603_5% 1 1 +VCCSST V16
CH70 DCPSST +1.05VS
CH69 0.1U_0402_10V7K
1U_0402_6.3V6K +1.05VM_VCCSUS T17 T21
2 2 DCPSUS[1] VCCASW[22]
V19 DCPSUS[2]
MISC
+1.05VS V21
VCCASW[23]
0.1U_0402_10V7K
0.1U_0402_10V7K
CPU
1 2 +V_CPU_IO BJ8
RH303 0_0603_5%
1mA
V_PROC_IO
1 1 1 T19
VCCASW[21]
+RTCVCC
CH72
CH73
CH71
4.7U_0603_6.3V6K
2 2 2 A22 P32 +VCCSUSHDA 2 1
RTC
VCCRTC 10mA VCCSUSHDA +3V_PCH

0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
HDA
RH305 0_0603_5%
1 1 1 1
150_0402_1%
LH6 PANTHER-POINT_FCBGA989 CH77
1
A A
CH74
CH75
CH76
10UH_LB2012T100MR_20% 0.1U_0402_16V4Z
+1.05VS 1 2 +1.05VS_VCCA_A_DPL
2 2 2 2
RH306
@
1 2 +1.05VS_VCCA_B_DPL
2
22U_0805_6.3V6M
22U_0805_6.3V6M
LH7
1U_0402_6.3V6K
1U_0402_6.3V6K
10UH_LB2012T100MR_20%
1 1 1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
CH78
CH80
CH79
CH81

2 2 2 2
PCH (7/8) PWR
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
UH1I
AY4 VSS[159] VSS[259] H46

AY42 K18
VSS[160] VSS[260]
AY46 K26
VSS[161] VSS[261]
AY8 K39
VSS[162] VSS[262]
B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264]
K7
B19 VSS[165] VSS[265] L18
D UH1H D
B23 VSS[166] VSS[266] L2
H5 VSS[0]
B27 VSS[167] VSS[267] L20
B31 VSS[168] VSS[268] L26
AA17 VSS[1] VSS[80]
AK38 B35
VSS[169] VSS[269]
L28
AA2 AK4 B39 L36
VSS[2] VSS[81] VSS[170] VSS[270]
AA3 VSS[3] VSS[82] AK42 B7 VSS[171] VSS[271] L48
AA33 AK46 F45 M12
VSS[4] VSS[83] VSS[172] VSS[272]
AA34 VSS[5] VSS[84] AK8 BB12 VSS[173] VSS[273] P16
AB11 VSS[6] VSS[85]
AL16 BB16
VSS[174] VSS[274] M18
AB14 AL17 BB20 M22
VSS[7] VSS[86] VSS[175] VSS[275]
AB39 AL19 BB22 M24
VSS[8] VSS[87] VSS[176] VSS[276]
AB4 VSS[9] VSS[88]
AL2 BB24
VSS[177] VSS[277] M30
AB43 VSS[10] VSS[89] AL21 BB28
VSS[178] VSS[278]
M32
AB5 VSS[11] VSS[90] AL23 BB30 VSS[179] VSS[279] M34
AB7 VSS[12] VSS[91] AL26 BB38 VSS[180] VSS[280] M38
AC19 AL27 BB4 M4
VSS[13] VSS[92] VSS[181] VSS[281]
AC2 AL31 BB46 M42
VSS[14] VSS[93] VSS[182] VSS[282]
AC21 AL33 BC14 M46
VSS[15] VSS[94] VSS[183] VSS[283]
AC24 VSS[16] VSS[95]
AL34 BC18
VSS[184] VSS[284] M8
AC33 AL48 BC2 N18
VSS[17] VSS[96] VSS[185] VSS[285]
AC34 AM11 BC22 P30
VSS[18] VSS[97] VSS[186] VSS[286]
AC48 AM14 BC26 N47
VSS[19] VSS[98] VSS[187] VSS[287]
AD10 AM36 BC32 P11
VSS[20] VSS[99] VSS[188] VSS[288]
AD11 VSS[21] VSS[100]
AM39 BC34 VSS[189] VSS[289] P18
AD12 VSS[22] VSS[101]
AM43 BC36
VSS[190] VSS[290]
T33
AD13 AM45 BC40 P40
VSS[23] VSS[102] VSS[191] VSS[291]
AD19 AM46 BC42 P43
VSS[24] VSS[103] VSS[192] VSS[292]
AD24 AM7 BC48 P47
VSS[25] VSS[104] VSS[193] VSS[293]
AD26 VSS[26] VSS[105] AN2 BD46
VSS[194] VSS[294] P7
AD27 VSS[27] VSS[106] AN29 BD5 VSS[195] VSS[295] R2
AD33 VSS[28] VSS[107]
AN3 BE22
VSS[196] VSS[296] R48
AD34 VSS[29] VSS[108] AN31 BE26 VSS[197] VSS[297] T12
C C
AD36 VSS[30] VSS[109] AP12 BE40
VSS[198] VSS[298] T31
AD37 AP19 BF10 T37
VSS[31] VSS[110] VSS[199] VSS[299]
AD38 AP28 BF12 T4
VSS[32] VSS[111] VSS[200] VSS[300]
AD39 VSS[33] VSS[112] AP30 BF16
VSS[201] VSS[301] W34
AD4 VSS[34] VSS[113] AP32 BF20 VSS[202] VSS[302]
T46
AD40 VSS[35] VSS[114] AP38 BF22 VSS[203] VSS[303] T47
AD42 AP4 BF24 T8
VSS[36] VSS[115] VSS[204] VSS[304]
AD43 AP42 BF26 V11
VSS[37] VSS[116] VSS[205] VSS[305]
AD45 VSS[38] VSS[117] AP46 BF28 VSS[206] VSS[306]
V17
AD46 VSS[39] VSS[118]
AP8 BD3 VSS[207] VSS[307]
V26
AD8 VSS[40] AR2 BF30 V27
VSS[119] VSS[208] VSS[308]
AE2 AR48 BF38 V29
VSS[41] VSS[120] VSS[209] VSS[309]
AE3 VSS[42] AT11 BF40 V31
VSS[121] VSS[210] VSS[310]
AF10 AT13 BF8 V36
VSS[43] VSS[122] VSS[211] VSS[311]
AF12 AT18 BG17 V39
VSS[44] VSS[123] VSS[212] VSS[312]
AD14 AT22 BG21 V43
VSS[45] VSS[124] VSS[213] VSS[313]
AD16 VSS[46] VSS[125]
AT26 BG33
VSS[214] VSS[314]
V7
AF16 VSS[47] VSS[126] AT28 BG44 VSS[215] VSS[315] W17
AF19 AT30 BG8 W19
VSS[48] VSS[127] VSS[216] VSS[316]
AF24 VSS[49] VSS[128] AT32 BH11 VSS[217] VSS[317] W2
AF26 AT34 BH15 W27
VSS[50] VSS[129] VSS[218] VSS[318]
AF27 VSS[51] VSS[130] AT39 BH17
VSS[219] VSS[319] W48
AF29 AT42 BH19 Y12
VSS[52] VSS[131] VSS[220] VSS[320]
AF31 AT46 H10 Y38
VSS[53] VSS[132] VSS[221] VSS[321]
AF38 VSS[54] VSS[133]
AT7 BH27 VSS[222] VSS[322]
Y4
AF4 VSS[55] VSS[134]
AU24 BH31 VSS[223] VSS[323] Y42
AF42 VSS[56] VSS[135] AU30 BH33 VSS[224] VSS[324] Y46
AF46 AV16 BH35 Y8
VSS[57] VSS[136] VSS[225] VSS[325]
AF5 AV20 BH39 BG29
VSS[58] VSS[137] VSS[226] VSS[328]
AV24 BH43
VSS[227] VSS[329]
N24
AV30 BH7
VSS[228] VSS[330]
AJ3
AG19 AV38 D3 AD47
B VSS[61] VSS[140] VSS[229] VSS[331] B
AG2 AV4 D12 B43
VSS[62] VSS[141] VSS[230] VSS[333]
AG31 VSS[63] VSS[142]
AV43 D16 VSS[231] VSS[334] BE10
AG48 VSS[64] VSS[143] AV8 D18 VSS[232] VSS[335]
BG41
AH11 VSS[65] VSS[144] AW14 D22
VSS[233] VSS[337] G14
AH3 AW18 D24 H16
VSS[66] VSS[145] VSS[234] VSS[338]
AH36 VSS[67] VSS[146]
AW2 D26
VSS[235] VSS[340]
T36
AH39 AW22 D30 BG22
VSS[68] VSS[147] VSS[236] VSS[342]
AH40 AW26 D32 BG24
VSS[69] VSS[148] VSS[237] VSS[343]
AH42 VSS[70] VSS[149]
AW28 D34
VSS[238] VSS[344] C22
AH46 VSS[71] VSS[150] AW32 D38 VSS[239] VSS[345] AP13
AH7 VSS[72] VSS[151] AW34 D42 VSS[240] VSS[346] M14
AJ19 AW36 D8 AP3
VSS[73] VSS[152] VSS[241] VSS[347]
AJ21 VSS[74] AW40 E18 AP1
VSS[153] VSS[242] VSS[348]
AJ24 AW48 E26 BE16
VSS[75] VSS[154] VSS[243] VSS[349]
AJ33 VSS[76] VSS[155] AV11 G18 VSS[244] VSS[350] BC16
AJ34 AY12 G20 BG28
VSS[77] VSS[156] VSS[245] VSS[351]
AK12 AY22 G26 BJ28
VSS[78] VSS[157] VSS[246] VSS[352]
AK3 AY28 G28
VSS[79] VSS[158] VSS[247]
G36
PANTHER-POINT_FCBGA989 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22
VSS[252]
H24 VSS[253]
H26 VSS[254]
H30
VSS[255]
H32 VSS[256]
H34
VSS[257]
F3 VSS[258]
A PANTHER-POINT_FCBGA989 A

PCH (8/8) VSS
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
LVDS Interface
UVG1G
PART 7 0F 9
VARY_BL AK27
LVDS CONTROL DIGON AJ27
PEG_HTX_C_GRX_P[15..0] UVG1A PEG_GTX_C_HRX_P[0..15]
4 PEG_HTX_C_GRX_P[15..0] PEG_GTX_C_HRX_P[0..15] 4
PEG_HTX_C_GRX_N[15..0] PART 1 0F 9 PEG_GTX_C_HRX_N[0..15]
4 PEG_HTX_C_GRX_N[15..0] PEG_GTX_C_HRX_N[0..15] 4
D
TXCLK_UP_DPF3P AK35 D
TXCLK_UN_DPF3N AL36
PEG_HTX_C_GRX_P0 AA38 PCIE_RX0P PCIE_TX0P Y33 PEG_GTX_HRX_P0 .1U_0402_16V7K 2 1 CV1 PX@ PEG_GTX_C_HRX_P0 TXOUT_U0P_DPF2P AJ38
PEG_HTX_C_GRX_N0 Y37 PCIE_RX0N PCIE_TX0N Y32 PEG_GTX_HRX_N0 .1U_0402_16V7K 2 1 CV2 PX@ PEG_GTX_C_HRX_N0 TXOUT_U0N_DPF2N AK37
TXOUT_U1P_DPF1P AH35
PEG_HTX_C_GRX_P1 Y35 PCIE_RX1P PCIE_TX1P W33 PEG_GTX_HRX_P1 .1U_0402_16V7K 2 1 CV3 PX@ PEG_GTX_C_HRX_P1 TXOUT_U1N_DPF1N AJ36
PEG_HTX_C_GRX_N1 W36 PCIE_RX1N PCIE_TX1N W32PEG_GTX_HRX_N1 .1U_0402_16V7K 2 1 CV4 PX@ PEG_GTX_C_HRX_N1
TXOUT_U2P_DPF0P AG38
TXOUT_U2N_DPF0N AH37
PEG_HTX_C_GRX_P2 W38 PCIE_RX2P PCIE_TX2P U33 PEG_GTX_HRX_P2 .1U_0402_16V7K 2 1 CV5 PX@ PEG_GTX_C_HRX_P2
PEG_HTX_C_GRX_N2 V37 PCIE_RX2N PCIE_TX2N U32 PEG_GTX_HRX_N2 .1U_0402_16V7K 2 1 CV6 PX@ PEG_GTX_C_HRX_N2 TXOUT_U3P AF35
TXOUT_U3N AG36
LVTMDP
PEG_HTX_C_GRX_P3 V35 PCIE_RX3P PCIE_TX3P U30 PEG_GTX_HRX_P3 .1U_0402_16V7K 2 1 CV7 PX@ PEG_GTX_C_HRX_P3
PEG_HTX_C_GRX_N3 U36 PCIE_RX3N PCIE_TX3N U29 PEG_GTX_HRX_N3 .1U_0402_16V7K 2 1 CV8 PX@ PEG_GTX_C_HRX_N3
TXCLK_LP_DPE3P AP34
PEG_HTX_C_GRX_P4 U38 PCIE_RX4P PCIE_TX4P T33 PEG_GTX_HRX_P4 .1U_0402_16V7K 2 1 CV9 PX@ PEG_GTX_C_HRX_P4 TXCLK_LN_DPE3N AR34
PEG_HTX_C_GRX_N4 T37 PCIE_RX4N PCIE_TX4N T32 PEG_GTX_HRX_N4 .1U_0402_16V7K 2 1 CV10 PX@ PEG_GTX_C_HRX_N4
TXOUT_L0P_DPE2P AW37
TXOUT_L0N_DPE2N AU35
PEG_HTX_C_GRX_P5 T35 PCIE_RX5P PCIE_TX5P T30 PEG_GTX_HRX_P5 .1U_0402_16V7K 2 1 CV11 PX@ PEG_GTX_C_HRX_P5
PEG_HTX_C_GRX_N5 R36 PCIE_RX5N PCIE_TX5N T29 PEG_GTX_HRX_N5 .1U_0402_16V7K 2 1 CV12 PX@ PEG_GTX_C_HRX_N5 TXOUT_L1P_DPE1P AR37
TXOUT_L1N_DPE1N AU39
PEG_HTX_C_GRX_P6 R38 PCIE_RX6P PCIE_TX6P P33 PEG_GTX_HRX_P6 .1U_0402_16V7K 2 1 CV13 PX@ PEG_GTX_C_HRX_P6 TXOUT_L2P_DPE0P AP35
PEG_HTX_C_GRX_N6 P37 PCIE_RX6N PCIE_TX6N P32 PEG_GTX_HRX_N6 .1U_0402_16V7K 2 1 CV14 PX@ PEG_GTX_C_HRX_N6 TXOUT_L2N_DPE0N AR35
TXOUT_L3P AN36
PEG_HTX_C_GRX_P7 P35 PCIE_RX7P PCIE_TX7P P30 PEG_GTX_HRX_P7 .1U_0402_16V7K 2 1 CV15 PX@ PEG_GTX_C_HRX_P7 TXOUT_L3N AP37
PEG_HTX_C_GRX_N7 N36 PCIE_RX7N PCIE_TX7N P29 PEG_GTX_HRX_N7 .1U_0402_16V7K 2 1 CV16 PX@ PEG_GTX_C_HRX_N7
PEG_HTX_C_GRX_P8 N38 PCIE_RX8P PCIE_TX8P N33 PEG_GTX_HRX_P8 .1U_0402_16V7K 2 1 CV17 PX@ PEG_GTX_C_HRX_P8
PEG_HTX_C_GRX_N8 M37 PCIE_RX8N PCIE_TX8N N32 PEG_GTX_HRX_N8 .1U_0402_16V7K 2 1 CV18 PX@ PEG_GTX_C_HRX_N8 +1.8VGS (1.8V @237mA for display use DP_VDDR) 2160834000A10CHELSE_FCBGA962
C RV143 75mA C
PEG_HTX_C_GRX_P9 M35 PCIE_RX9P PCIE_TX9P N30 PEG_GTX_HRX_P9 .1U_0402_16V7K 2 1 CV19 PX@ PEG_GTX_C_HRX_P9 1 2 +DPLL_PVDD
PEG_HTX_C_GRX_N9 L36 PCIE_RX9N PCIE_TX9N N29 PEG_GTX_HRX_N9 .1U_0402_16V7K 2 1 CV20 PX@ PEG_GTX_C_HRX_N9
0_0402_5%
CV40
CV41
CV42
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1 1 1
PEG_HTX_C_GRX_P10 L33PEG_GTX_HRX_P10 .1U_0402_16V7K 1 CV21 PX@ PEG_GTX_C_HRX_P10
PCI EXPRESS INTERFACE
L38 PCIE_RX10P PCIE_TX10P 2

PEG_HTX_C_GRX_N10 K37 PCIE_RX10N PCIE_TX10N L32PEG_GTX_HRX_N10 .1U_0402_16V7K 2 1 CV22 PX@ PEG_GTX_C_HRX_N10
2 2 2 UVG1I
PX@
PX@
PX@
PEG_HTX_C_GRX_P11 K35 PCIE_RX11P PCIE_TX11P L30PEG_GTX_HRX_P11 .1U_0402_16V7K 2 1 CV23 PX@ PEG_GTX_C_HRX_P11
PEG_HTX_C_GRX_N11 J36 PCIE_RX11N PCIE_TX11N L29PEG_GTX_HRX_N11 .1U_0402_16V7K 2 1 CV24 PX@ PEG_GTX_C_HRX_N11
PART 9 0F 9
PEG_HTX_C_GRX_P12 J38 PCIE_RX12P PCIE_TX12P K33PEG_GTX_HRX_P12 .1U_0402_16V7K 2 1 CV25 PX@ PEG_GTX_C_HRX_P12

PEG_HTX_C_GRX_N12 H37 PCIE_RX12N PCIE_TX12N K32PEG_GTX_HRX_N12 .1U_0402_16V7K 2 1 CV26 PX@ PEG_GTX_C_HRX_N12
0.935V (0.935V @222mA DP_VDDC)
+DPLL_PVDD AM32 DPLL_PVDD XTALIN AV33 XTALIN
PEG_HTX_C_GRX_P13 H35 PCIE_RX13P PCIE_TX13P J33PEG_GTX_HRX_P13 .1U_0402_16V7K 2 1 CV27 PX@ PEG_GTX_C_HRX_P13 RV144 125mA
PEG_HTX_C_GRX_N13 G36 PCIE_RX13N PCIE_TX13N J32PEG_GTX_HRX_N13 .1U_0402_16V7K 2 1 CV28 PX@ PEG_GTX_C_HRX_N13 1 2 +DPLL_VDDC +DPLL_VDDC AN31 DPLL_VDDC
0_0402_5%
CV43
CV44
CV45
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
PEG_HTX_C_GRX_P14 G38 PCIE_RX14P PCIE_TX14P K30PEG_GTX_HRX_P14 .1U_0402_16V7K 2 1 CV29 PX@ PEG_GTX_C_HRX_P14 1 1 1 AN32 DPLL_PVSS
PEG_HTX_C_GRX_N14 F37 PCIE_RX14N PCIE_TX14N K29PEG_GTX_HRX_N14 .1U_0402_16V7K 2 1 CV30 PX@ PEG_GTX_C_HRX_N14
XTALOUT AU34 XTALOUT
2 2 2
PX@
PX@
PX@
PEG_HTX_C_GRX_P15 F35 PCIE_RX15P PCIE_TX15P H33PEG_GTX_HRX_P15 .1U_0402_16V7K 2 1 CV31 PX@ PEG_GTX_C_HRX_P15
PEG_HTX_C_GRX_N15 E37 PCIE_RX15N PCIE_TX15N H32PEG_GTX_HRX_N15 .1U_0402_16V7K 2 1 CV32 PX@ PEG_GTX_C_HRX_N15
+MPV18 H7 MPLL_PVDD
H8 MPLL_PVDD
CLOCK XO_IN AW342 RV146 1@ 0_0402_5%

CLK_PCIE_VGA AB35 PCIE_REFCLKP
14 CLK_PCIE_VGA +1.8VGS
CLK_PCIE_VGA# AA36 PCIE_REFCLKN +SPV18 AM10 SPLL_PVDD
14 CLK_PCIE_VGA#
PLLS/XTAL
1.69K_0402_1% 1 PX@ 2 RV29 For Chelsea only (M97, Broadway and Madison:
0.935V
CALIBRATION
PX@ LV9
1.8V@150mA MPV18-MPLL_PVDD)
PCIE_CALR_TX Y30 For Chelsea non staff 1 2 +MPV18 +SPV10 AN9 SPLL_VDDC XO_IN2 AW351 RV147 2@ 0_0402_5%
PX@ BLM15BD121SN1D_0402
B B
RV4 2 1 AH16 TEST_PG PCIE_CALR_RX Y29 1 PX@ 2 0.935V
1K_0402_5% 1K_0402_5% RV5
CV149
CV150
CV151
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
11/20 follwo AMD/ check list 1 1 1 AN10 SPLL_PVSS
GPU_RST# AA30 PERSTB
1
2 2 2
PX@
PX@
PX@
PX@ @ RV141 0_0402_5% CLKTESTA AK10
2160834000A10CHELSE_FCBGA962
RV6 +DPLL_PVDD 2 1 AF30 NC_XTAL_PVDD CLKTESTB AL10
100K_0402_5% 2 1 AF31 NC_XTAL_PVSS
+1.8VGS @ RV148 0_0402_5%
2
(1.8V@75mA
SPV18-SPLL_PVDD)
LV10 PX@ 2160834000A10CHELSE_FCBGA962
1 2 +SPV18
1
BLM15BD121SN1D_0402 @ @
RV1 2 @ 1 0_0402_5% CV171 CV170
0.1U_0402_16V7K 0.1U_0402_16V7K
CV152
CV153
CV154
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
2
1 1 1
+3VGS
RV28
1
2 2 2
PX@
PX@
PX@
XTALOUT PX@ XTALIN @ @
5
UV1 RV70 RV69

2 1M_0402_5% 51.1_0402_1% 51.1_0402_1%
P
5,16,31,34,36 PLT_RST# B
4 GPU_RST# YV2 PX@
2
Y
16 DGPU_HOLD_RST# 1 2 1
A
G
0.935V
PX@ (150mA SPV10-SPLL_VDDC) 27MHZ_16PF_X5H027000FG1H
3
MC74VHC1G08DFT2G SC70 5P LV11 PX@

1 2 +SPV10 PX@ CV49 CV50 PX@
MCK1608471YZF 0603 18P_0402_50V8J 18P_0402_50V8J route 50ohms single-ended/100ohms diff
and keep short
CV166
CV168
CV169
10U_0603_6.3V6M
1U_0402_6.3V6K
Debug only, for clock observation, if not needed, DNI

0.1U_0402_16V7K
1 1 1
A 5mil 5mil A
2 2 2
PX@
PX@
PX@

ATI_SeymourXT_M2_PCIE/LVDS
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
CONFIGURATION STRAPS RECOMMENDED SETTINGS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
UVG1B
STRAPS NA = NOT APPLICABLE
+3VGS
PART 2 0F 9
RECOMMENDED
MUTI GFX 10K_0402_5% 1 @ 2 RV7 GPU_GPIO0 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS <all internal PD> SETTINGS
N72158384 AD29 GENLK_CLK TXCAP_DPA3P AU24 10K_0402_5% 1 PX@ 2 RV8 GPU_GPIO1
T76 N72155053 AC29 GENLK_VSYNC TXCAM_DPA3N AV23 10K_0402_5% 1 @ 2 RV9 GPU_GPIO2 0: 50% swing
T77 R1.0 TX_PWRS_ENB GPIO0 PCIE TRANSMITTER Power Saving Enable 1: Full swing X
RV9 SMT-->@
TX0P_DPA2P AT25
AJ21 SWAPLOCKA TX0M_DPA2N AR24 100K_0402_5% 1 @ 2 RV10 GPU_GPIO5 0: disable
DPA 1: enable
AK21 SWAPLOCKB 10K_0402_5% 1 @ 2 RV31 GPIO21_BBEN TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS X
TX1P_DPA1P AU26 10K_0402_5% 1 @ 2 RV32 GPIO22_ROMCSB
TX1M_DPA1N AV25 10K_0402_5% 1 @ 2 RV11 GPU_GPIO8 0: 2.5GT/s
D D
10K_0402_5% 1 @ 2 RV12 GPU_GPIO9 RSVD GPIO2 Advertises PCIE speed when compliance test 1: 5GT/s 0
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 10K_0402_5% 1 PX@ 2 RV13 GPU_GPIO11
AP8 DVPCNTL_0 10K_0402_5% 1 @ 2 RV15 GPU_VID1 RSVD GPIO8 0
AW8 DVPCNTL_1 TXCBP_DPB3P AR30 10K_0402_5% 1 @ 2 RV16 GPU_GPIO13
AR3 DVPCNTL_2 TXCBM_DPB3N AT29 Internal use only.This Pad has an internal PD and Must be 0V at reset.
+3VGS RSVD H2SYNC The pad may be left unconnected. 0
AR1 DVPCLK Update net name
24 VRAM_ID0 AU1 DVPDATA_0 TX3P_DPB2P AV31
AU3 AU30 10K_0402_5% 1 @ 2 RV18 GPIO24_TRSTB
VRAM ID2424 VRAM_ID1
VRAM_ID2 AW3
DVPDATA_1
DVPDATA_2
DPB
TX3M_DPB2N
10K_0402_5% 1 @ 2 RV19 GPIO25_TDI RSVD GPIO21 0
AP6 DVPDATA_3 TX4P_DPB1P AR32 10K_0402_5% 1 @ 2 RV20 GPIO27_TMS
AW5 DVPDATA_4 TX4M_DPB1N AT31 0: disable
AU5 DVPDATA_5 10K_0402_5% 1 @ 2 RV21 GPIO26_TCK BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1: enable X
AR6 DVPDATA_6 TX5P_DPB0P AT33
AW6 DVPDATA_7 TX5M_DPB0N AU32
AU6 DVPDATA_8 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13 GPIO13,12,11(config 2,1,0): internal PD.
AN7 DVPDATA_11 a)If BIOS_ROM_EN=1,the config[2:0] defines the ROM type. Memory apertures
AV9 DVPDATA_12 TX0P_DPC2P AT15 config[3:0]
b)If BIOS_ROM_EN=0,the config[2:0] defines the primary aperture size.
AT9 DVPDATA_13 TX0M_DPC2N AR14 128MB 000
AR10 DVPDATA_14 256MB 001
DPC
AW10 DVPDATA_15 TX1P_DPC1P AU16 64MB 010
AU10 DVPDATA_16 TX1M_DPC1N AV15
AP10 DVPDATA_17 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16
AR12 DVPDATA_20 BIF_VGA DIS GPIO9 VGA ENABLED 0
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19
AP12 DVPDATA_23 RSVD GENERICC 0
TX3P_DPD2P AT21
TX3M_DPD2N AR20 AUD[1] AUD[0]
AUD[1] HSYNC 0 0 No audio function
DPD
VGA_SMB_CK2 AJ23 SMBCLK TX4P_DPD1P AU22 0 1 Audio for DisplayPort and HDMI if dongle is detected 11
SMBus
VGA_SMB_DA2 AH23 SMBDATA TX4M_DPD1N AV21 1 0 Audio for DisplayPort only
AUD[0] VSYNC 1 1 Audio for both DisplayPort and HDMI
C TX5P_DPD0P AT23 C
11/20 follow AMD/HP
N72158384
TX5M_DPD0N AR22
AMD RESERVED CONFIGURATION STRAPS
AK26 SCL
I2C
T74 N72155053 AJ26 SDA ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
T75
R AD39 ATI_DP_R T69 RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
GENERAL PURPOSE I/O AVSSN#1 AD37 NOT CONFLICT DURING RESET
GPU_GPIO0 AH20 GPIO_0
GPU_GPIO1 AH18 GPIO_1 G AE36 ATI_DP_G T70
GPU_GPIO2 AN16 GPIO_2 AVSSN#2 AD35 GPIO21 H2SYNC GENERICC GPIO2 GPIO8
RB751V_SOD323 B AF37 ATI_DP_B T71

DV1 @ 1 2 GPU_GPIO5 AH17 GPIO_5_AC_BATT AVSSN#3 AE38
15,36,48 ACIN
VDDCI_VID AJ17 GPIO_6 Transmitter Power Saving Enable
54 VDDCI_VID DAC1
AK17 GPIO_7_BLON HSYNC AC36 ATI_DP_H T72 TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode
1 2 @ RV132 GPU_GPIO8 AJ13 GPIO_8_ROMSO VSYNC AC38 ATI_DP_V T73 1: full Tx output swing (Default setting for Desktop)
10K_0402_5% GPU_GPIO9 AH15 GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
+1.8VGS PCI Express Transmitter De-emphasis Enable
GPU_GPIO11 AK16 GPIO_11 RSET AB34 RV14 1 PX@ 2 499_0402_1% TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode
GPU_VID1 AL16 GPIO_12 1: Tx de-emphasis enabled (Defailt setting for desktop)
56 GPU_VID1
GPU_GPIO13 AM16 GPIO_13 AVDD AD34 +AVDD (1.8V@18mA AVDD) 1 2
AM14 GPIO_14_HPD2 AVSSQ AE34 LV1 PX@
GPU_VID3 BLM15BD121SN1D_0402
CV33
CV34
CV35
AM13 GPIO_15_PWRCNTL_0
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
56 GPU_VID3
GPU_VID2 AK14 GPIO_16 VDD1DI AC33 +VDD1DI (1.8V@117mA VDD1DI) 1 2 +1.8VGS 1 1 1
56 GPU_VID2
VGA_THERALERT# AG30 AC34 LV2 PX@
Internal VGA Thermal Sensor
GPIO_17_THERMAL_INT VSS1DI
PX@ RV24 10K_0402_5% BLM15BD121SN1D_0402 +3VGS
CV36
CV37
CV38
AN14 GPIO_18_HPD3
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1 2 GPIO_19_CTF AM17 GPIO_19_CTF 1 1 1 2 2 2
PX@
PX@
PX@
GPU_VID4 AL13 GPIO_20_PWRCNTL_1 NC#1 V13
56 GPU_VID4
GPIO21_BBEN AJ14 GPIO_21 NC#2 U13
T51 GPIO22_ROMCSB AK13 GPIO_22_ROMCSB NC#3 AC31 +3VGS
2
2 2 2
PX@
PX@
PX@
VGA_CLKREQ# AN13 CLKREQB NC#4 AD30 PX@ PX@
14 VGA_CLKREQ#
NC#5 AC32 RV22 RV23
NC#6 AD32 2.2K_0402_5% 2.2K_0402_5%
AG32 GPIO_29 NC#7 AF32
2
AG33 GPIO_30 NC#8 AA29
1
NC#9 AG21
AJ19 GENERICA VGA_SMB_CK2 1 6 EC_SMB_CK2 14,36
AK19 GENERICB
5
B B
AJ20 GENERICC QV1A PX@
AK20 GENERICD @ RV142 DMN66D0LDW-7_SOT363-6
AJ24 GENERICE_HPD4 NC_TSVSSQ AF331 2 VGA_SMB_DA2 4 3 EC_SMB_DA2 14,36
AH26 GENERICF_HPD5
AH24 GENERICG_HPD6 0_0402_5% QV1B PX@
DMN66D0LDW-7_SOT363-6
PS_0 AM34
For Chelsea non staff
AC30 CEC_1
0.60 V level, Please AK24 HPD1

MLPS
PS_1 AD31
+1.8VGS
VREFG Divider ans
PX@ cap close to ASIC
2 RV25 1 499_0402_1% +VREFG_GPU AH13 VREFG PS_2 AG31
PX@
2 RV26 1 249_0402_1%
BACO
2 1 AL21 PX_EN PS_3 AD33
CV39 0.1U_0402_16V7K
PX@
Use Internal Thermal Sensor
+3VGS
DEBUG DDC/AUX
DDC1CLK AM26
External VGA Thermal Sensor: No stuff
@ DDC1DATA AN26
RV66 1 2 TESTEN AD28 TESTEN
5.11K_0402_1% AUX1P AM27
AUX1N AL27
GPIO24_TRSTB AM23 JTAG_TRSTB DDC2CLK AM19

1 2 GPIO25_TDI AN23 JTAG_TDI DDC2DATA AL19 @ +3VGS
RV131 1K_0402_5% GPIO26_TCK AK23 JTAG_TCK UV13
PX@ GPIO27_TMS AL24 JTAG_TMS AUX2P AN20 2 1 1 8 VGA_SMB_CK2
T52 GPIO28_TDO CV271 0.1U_0402_16V4Z VDD SCLK
AM24 JTAG_TDO AUX2N AM20
THERM_D+ 2 7 VGA_SMB_DA2
@ CV272 D+ SDATA
DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30 1 2 3 6 2 @ 1 +3VGS
THERM_D- D- ALERT# RV134 2.2K_0402_5%
A A
THERMAL
DDCCLK_AUX4P AL29 2200P_0402_50V7K 4 5
THERM_D+ THERM# GND
AF29 DPLUS DDCDATA_AUX4N AM29 +3VGS 2 1 1 R123 2 VGA_THERALERT#
THERM_D- AG29 DMINUS @ 0_0402_5%
PX@ (1.8V@20mA TSVDD) +3VGS DDCCLK_AUX5P AN21 RV133 2.2K_0402_5% ADM1032ARMZ-2REEL_MSOP8
LV5 @ RV30 DDCDATA_AUX5N AM21
+1.8VGS 1 2 +TSVDD 1 2 GPIO_28_FDO AK32 GPIO_28_FDO
BLM15BD121SN1D_0402 10K_0402_5% DDCCLK_AUX6P AK30
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V4Z
CV46
CV47
CV48
1 1 1 AL31 TS_A DDCDATA_AUX6N AK29
T53
AJ32 TSVDD
DDCVGACLK
DDCVGADATA
AJ30
AJ31 T54
2 2 2 AJ33 2011/06/30 2013/06/30 Title
TSVSS
Issued Date Deciphered Date
PX@
PX@
PX@
ATI_SeymourXT_M2_Main_MSIC
2160834000A10CHELSE_FCBGA962 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
1.5VPCIEV +1.5VGS
+1.5V TO +1.5VGS
UV148 PX@
+3.3VS TO +3.3VGS +3VS +3VGS 10U_0603_6.3V6M AO4430L_SO8
D D
8 1 10U_0603_6.3V6M
1 7 2 1 1
1
10U_0603_6.3V6M 1U_0603_10V6K CV59 6 3 CV60 CV61 PX@
PX@ 5 PX@ 1U_0603_10V6K RV39 @
1
470_0603_5%
Chelsea Power Up 1
CV56
1
CV57 RV34 @ 2 2 2
4
PX@ PX@ 470_0603_5%
3 2
2 2 +VSB
+3VGS/+VGA_CORE 3 1
2
+5VALW
0,935V(VDDC) PX@
1
QV16 PX@ D RV40 PX@ QV2B 5
AP2301GN-HF_SOT23-3 2 20K_0402_5% DMN66D0LDW-7_SOT363-6
2
VDDCI PX@ PX@ G
4
RV36 RV37 PXS_PWREN_5V# S QV7 @ RV41
3
2N7002K_SOT23-3 1 PX@ 2
2
+1.5VGS(VDDR1/MVDDQ) 20K_0402_5% 20K_0402_5% 200K_0402_1% 1
6
RV43
1 PX@ 0_0402_5% 0_0402_5% CV62 PX@ @
1
D PX@ CV58 PXS_PWREN# PX@ @ 0.1U_0603_25V7K PXS_PWREN#
+1.8VS 1 2 1 RV44 2 0_0402_5%
PXS_PWREN 2 QV9 0.1U_0603_25V7K @ RV38 PXS_PWREN# 2 QV2A 2
1
G 2N7002K_SOT23-3 DMN66D0LDW-7_SOT363-6
S 2
1
C C
+3VALW
1
PX@
RV35
100K_0402_5%
2
PXS_PWREN#
11/20 PXS_PWREN=PCH GPIO54
+1.8VS TO +1.8VGS
1
D
PXS_PWREN 2 QV8
16,53,54,56 PXS_PWREN
G 2N7002K_SOT23-3
S PX@ +1.8VS +1.8VGS
3
PXS_PWREN_R 1 RV138 2 0_0402_5%
PX@
AP2301GN-HF_SOT23-3
3 1
1 1 1
1
B B
PX@ CV275 CV274 CV273 PX@
1U_0402_6.3V6K QV19 PX@ PX@ 1U_0603_10V6K RV136 @
+5VALW 10U_0603_6.3V6M 470_0603_5%
2
2 2 2
6 2
PX@ PX@
RV137 RV53 PXS_PWREN_5V#
PX@
20K_0402_5% 20K_0402_5% QV18A 2
1 PX@
1
3
CV63
0.1U_0603_25V7K
PX@
PXS_PWREN 5 QV18B 2
PXS_PWREN# 1 RV135 @2 0_0402_5%
4
A A

ATI_SeymourXT_M2_BACO POWER
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
MDA[0..63] UVG1D
UVG1C 27 MDA[0..63]
MDB[0..63] PART 4 0F 9
PART 3 0F 9 MAA[12..0] 28 MDB[0..63]
MAA[12..0] 27 GDDR5/DDR3
GDDR5/DDR3 MDB0 C5 DQB0_0 MAB0_0/MAB_0 P8 MAB0
MDA0 C37 DQA0_0 MAA0_0/MAA_0 G24 MAA0 A_BA[2..0] MAB[12..0] MDB1 C3 DQB0_1 MAB0_1/MAB_1 T9 MAB1
A_BA[2..0] 27 MAB[12..0] 28
MDA1 C35 DQA0_1 MAA0_1/MAA_1 J23 MAA1 MDB2 E3 DQB0_2 MAB0_2/MAB_2 P9 MAB2
MDA2 A35 DQA0_2 MAA0_2/MAA_2 H24 MAA2 B_BA[2..0] MDB3 E1 DQB0_3 MAB0_3/MAB_3 N7 MAB3
B_BA[2..0] 28
MDA3 E34 DQA0_3 MAA0_3/MAA_3 J24 MAA3 MDB4 F1 DQB0_4 MAB0_4/MAB_4 N8 MAB4
MDA4 G32 DQA0_4 MAA0_4/MAA_4 H26 MAA4 MDB5 F3 DQB0_5 MAB0_5/MAB_5 N9 MAB5
MDA5 D33 DQA0_5 MAA0_5/MAA_5 J26 MAA5 MDB6 F5 DQB0_6 MAB0_6/MAB_6 U9 MAB6
MDA6 F32 DQA0_6 MAA0_6/MAA_6 H21 MAA6 +1.8VGS MDB7 G4 DQB0_7 MAB0_7/MAB_7 U8 MAB7
MDA7 E32 DQA0_7 MAA0_7/MAA_7 G21 MAA7 MDB8 H5 DQB0_8 MAB1_0/MAB_8 Y9 MAB8
MDA8 D31 DQA0_8 MAA1_0/MAA_8 H19 MAA8 RV56 1 @ 2 10K_0402_5% VRAM_ID0 MDB9 H6 DQB0_9 MAB1_1/MAB_9 W9 MAB9
MEMORY INTERFACE A
VRAM_ID0 22
MDA9 F30 DQA0_9 MAA1_1/MAA_9 H20 MAA9 RV59 1 @ 2 10K_0402_5% MDB10 J4 DQB0_10 MAB1_2/MAB_10 AC8 MAB10
MDA10 C30 DQA0_10 MAA1_2/MAA_10 L13 MAA10 RV57 1 @ 2 10K_0402_5% VRAM_ID1 MDB11 K6 DQB0_11 MAB1_3/MAB_11 AC9 MAB11
VRAM_ID1 22
MDA11 A30 DQA0_11 MAA1_3/MAA_11 G16 MAA11 RV58 1 @ 2 10K_0402_5% MDB12 K5 DQB0_12 MAB1_4/MAB_12 AA7 MAB12
D D
MDA12 F28 DQA0_12 MAA1_4/MAA_12 J16 MAA12 RV60 1 @ 2 10K_0402_5% VRAM_ID2 MDB13 L4 DQB0_13 MAB1_5/BA2 AA8 B_BA2
VRAM_ID2 22
MDA13 C28 DQA0_13 MAA1_5/MAA_BA2 H16 A_BA2 RV61 1 @ 2 10K_0402_5% MDB14 M6 DQB0_14 MAB1_6/BA0 Y8 B_BA0
MDA14 A28 DQA0_14 MAA1_6/MAA_BA0 J17 A_BA0 MDB15 M1 DQB0_15 MAB1_7/BA1 AA9 B_BA1
MDA15 E28 DQA0_15 MAA1_7/MAA_BA1 H17 A_BA1 MDB16 M3 DQB0_16
DQMB#[7..0] 28
MDA16 MDB17 DQMB#0
MEMORY INTERFACE B
D27 DQA0_16
DQMA#[7..0] 27 M5 DQB0_17 WCKB0_0/DQMB_0 H3
MDA17 F26 DQA0_17 WCKA0_0/DQMA_0 A32 DQMA#0 MDB18 N4 DQB0_18 WCKB0B_0/DQMB_1 H1 DQMB#1
MDA18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 DQMA#1 MDB19 P6 DQB0_19 WCKB0_1/DQMB_2 T3 DQMB#2
MDA19 A26 DQA0_19 WCKA0_1/DQMA_2 D23 DQMA#2 MDB20 P5 DQB0_20 WCKB0B_1/DQMB_3 T5 DQMB#3
MDA20 F24 DQA0_20 WCKA0B_1/DQMA_3 E22 DQMA#3 MDB21 R4 DQB0_21 WCKB1_0/DQMB_4 AE4 DQMB#4
MDA21 C24 DQA0_21 WCKA1_0/DQMA_4 C14 DQMA#4 MDB22 T6 DQB0_22 WCKB1B_0/DQMB_5 AF5 DQMB#5
MDA22 A24 DQA0_22 WCKA1B_0/DQMA_5 A14 DQMA#5 MDB23 T1 DQB0_23 WCKB1_1/DQMB_6 AK6 DQMB#6
MDA23 E24 DQA0_23 WCKA1_1/DQMA_6 E10 DQMA#6 MDB24 U4 DQB0_24 WCKB1B_1/DQMB_7 AK5 DQMB#7
MDA24 C22 DQA0_24 WCKA1B_1/DQMA_7 D9 DQMA#7 MDB25 V6 DQB0_25
QSB[7..0] 28
MDA25 A22 DQA0_25 MDB26 V1 DQB0_26 EDCB0_0/QSB_0 F6 QSB0
QSA[7..0] 27
MDA26 F22 DQA0_26 EDCA0_0/QSA_0 C34 QSA0 MDB27 V3 DQB0_27 EDCB0_1/QSB_1 K3 QSB1
MDA27 D21 DQA0_27 EDCA0_1/QSA_1 D29 QSA1 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2 MDB28 Y6 DQB0_28 EDCB0_2/QSB_2 P3 QSB2
MDA28 A20 DQA0_28 EDCA0_2/QSA_2 D25 QSA2 MDB29 Y1 DQB0_29 EDCB0_3/QSB_3 V5 QSB3
MDA29 F20 DQA0_29 EDCA0_3/QSA_3 E20 QSA3 MDB30 Y3 DQB0_30 EDCB1_0/QSB_4 AB5 QSB4
MDA30 D19 DQA0_30 EDCA1_0/QSA_4 E16 QSA4 128M16 (2G) H5TQ2G63BFR-11C MDB31 Y5 DQB0_31 EDCB1_1/QSB_5 AH1 QSB5
MDA31 E18 DQA0_31 EDCA1_1/QSA_5 E12 QSA5 Hynix 2GB RV57 RV58 RV59 MDB32 AA4 DQB1_0 EDCB1_2/QSB_6 AJ9 QSB6
MDA32 C18 DQA1_0 EDCA1_2/QSA_6 J10 QSA6 MDB33 AB6 DQB1_1 EDCB1_3/QSB_7 AM5 QSB7
PN:SA00003YO00 QSB#[7..0] 28
MDA33 A18 DQA1_1 EDCA1_3/QSA_7 D7 QSA7 1 0 0 MDB34 AB1 DQB1_2
QSA#[7..0] 27
MDA34 F18 DQA1_2 MDB35 AB3 DQB1_3 DDBIB0_0/QSB_0B G7 QSB#0
MDA35 D17 DQA1_3 DDBIA0_0/QSA_0B A34 QSA#0 RV54 RV55 RV59 MDB36 AD6 DQB1_4 DDBIB0_1/QSB_1B K1 QSB#1
MDA36 A16 DQA1_4 DDBIA0_1/QSA_1B E30 QSA#1 MDB37 AD1 DQB1_5 DDBIB0_2/QSB_2B P1 QSB#2
MDA37 F16 DQA1_5 DDBIA0_2/QSA_2B E26 QSA#2 0 1 0 MDB38 AD3 DQB1_6 DDBIB0_3/QSB_3B W4 QSB#3
MDA38 D15 DQA1_6 DDBIA0_3/QSA_3B C20 QSA#3 MDB39 AD5 DQB1_7 DDBIB1_0/QSB_4B AC4 QSB#4
MDA39 E14 DQA1_7 DDBIA1_0/QSA_4B C16 QSA#4 RV57 RV58 RV59 MDB40 AF1 DQB1_8 DDBIB1_1/QSB_5B AH3 QSB#5
MDA40 F14 DQA1_8 DDBIA1_1/QSA_5B C12 QSA#5 MDB41 AF3 DQB1_9 DDBIB1_2/QSB_6B AJ8 QSB#6
MDA41 D13 DQA1_9 DDBIA1_2/QSA_6B J11 QSA#6 1 0 1 MDB42 AF6 DQB1_10 DDBIB1_3/QSB_7B AM3 QSB#7
MDA42 F12 DQA1_10 DDBIA1_3/QSA_7B F8 QSA#7 MDB43 AG4 DQB1_11
MDA43 A12 DQA1_11 RV54 RV55 RV59 MDB44 AH5 DQB1_12 ADBIB0/ODTB0 T7 ODTB0
ODTB0 28
MDA44 D11 DQA1_12 ADBIA0/ODTA0 J21 ODTA0 MDB45 AH6 DQB1_13 ADBIB1/ODTB1 W7 ODTB1
ODTA0 27 ODTB1 28
MDA45 F10 DQA1_13 ADBIA1/ODTA1 G19 ODTA1 0 1 1 MDB46 AJ4 DQB1_14
ODTA1 27
MDA46 A10 DQA1_14 MDB47 AK3 DQB1_15 CLKB0 L9 CLKB0
CLKB0 28
MDA47 C10 DQA1_15 CLKA0 H27 CLKA0 MDB48 AF8 DQB1_16 CLKB0B L8 CLKB0#
CLKA0 27 CLKB0# 28
MDA48 G13 DQA1_16 CLKA0B G27 CLKA0# MDB49 AF9 DQB1_17
CLKA0# 27
C MDA49 H13 DQA1_17 MDB50 AG8 DQB1_18 CLKB1 AD8 CLKB1 C
CLKB1 28
MDA50 J13 DQA1_18 CLKA1 J14 CLKA1 MDB51 AG7 DQB1_19 CLKB1B AD7 CLKB1#
CLKA1 27 CLKB1# 28
MDA51 H11 DQA1_19 CLKA1B H14 CLKA1# MDB52 AK9 DQB1_20
CLKA1# 27
MDA52 G10 DQA1_20 MDB53 AL7 DQB1_21 RASB0B T10 RASB0#
RASB0# 28
MDA53 G8 DQA1_21 RASA0B K23 RASA0# MDB54 AM8 DQB1_22 RASB1B Y10 RASB1#
RASA0# 27 RASB1# 28
MDA54 K9 DQA1_22 RASA1B K19 RASA1# MDB55 AM7 DQB1_23
RASA1# 27
MDA55 K10 DQA1_23 MDB56 AK1 DQB1_24 CASB0B W10 CASB0# CASB0# 28
MDA56 G9 DQA1_24 CASA0B K20 CASA0# MDB57 AL4 DQB1_25 CASB1B AA10 CASB1#
CASA0# 27 CASB1# 28
MDA57 A8 DQA1_25 CASA1B K17 CASA1# MDB58 AM6 DQB1_26
CASA1# 27
MDA58 C8 DQA1_26 MDB59 AM1 DQB1_27 CSB0B_0 P10 CSB0#_0
CSB0#_0 28
MDA59 E8 DQA1_27 CSA0B_0 K24 CSA0#_0 MDB60 AN4 DQB1_28 CSB0B_1 L10
CSA0#_0 27
MDA60 A6 DQA1_28 CSA0B_1 K27 MDB61 AP3 DQB1_29
MDA61 C6 DQA1_29 MDB62 AP1 DQB1_30 CSB1B_0 AD10 CSB1#_0 CSB1#_0 28
MDA62 E6 DQA1_30 CSA1B_0 M13 CSA1#_0 MDB63 AP5 DQB1_31 CSB1B_1 AC10
CSA1#_0 27
MDA63 A5 DQA1_31 CSA1B_1 K16
CKEB0 U10 CKEB0 CKEB0 28
+VDD_MEM15_REFDA L18 MVREFDA CKEA0 K21 CKEA0 +VDD_MEM15_REFDB Y12 MVREFDB CKEB1 AA11 CKEB1
+1.5VGS CKEA0 27 CKEB1 28
+VDD_MEM15_REFSA L20 MVREFSA CKEA1 J20 CKEA1 +VDD_MEM15_REFSB AA12 MVREFSB
CKEA1 27
WEB0B N10 WEB0# WEB0# 28
@ RV62 1 2 240_0402_1% L27 NC_MEM_CALRN0 WEA0B K26 WEA0# WEA0# 27 WEB1B AB11 WEB1# WEB1# 28
@ RV63 1 2 240_0402_1% N12 NC_MEM_CALRN1 WEA1B L15 WEA1# WEA1# 27
@ RV64 1 2 240_0402_1%AG12 NC_MEM_CALRN2
MAB0_8/MAB_13 T8 MAB13
MAB13 28
@ RV65 1 2 240_0402_1% M12 NC_MEM_CALRP1 MAA0_8/MAA_13 H23 MAA13 MAA13 27 MAB1_8/MAB_14 W8
RV67 1 2 120_0402_5% M27 MEM_CALRP0 MAA1_8/MAA_14 J19 MAB0_9/MAB_15 U12
RV68 1 2 120_0402_5%AH12 MEM_CALRP2 MAA0_9/MAA_15 M21 MAB1_9/RSVD V12
MAA1_9/RSVD M20
For Chelsea DRAM_RST AH11 DRAM_RST#_R
RV62,RV63,RV64,RV65 non staff
RV67,RV68 from 240ohm
change to 120ohm
B B
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These

Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2
+1.5VGS
+1.5VGS +1.5VGS
1
RV71
1
4.7K_0402_5%
@ RV74 RV75
40.2_0402_1% 40.2_0402_1%
2
+1.5VGS +1.5VGS PX@ PX@
2
1
1 RV76 2 1 RV77 2 DRAM_RST#_R +VDD_MEM15_REFDB +VDD_MEM15_REFSB

RV72 RV73 27,28 DRAM_RST# 51.1_0402_1% 10_0402_5%
40.2_0402_1% 40.2_0402_1% PX@ PX@
1
PX@ PX@ CV175 CV176
2
RV81 0.1U_0402_16V7K RV82 0.1U_0402_16V7K

2
PX@ PX@ 100_0402_1% PX@ 100_0402_1% PX@
2
+VDD_MEM15_REFDA +VDD_MEM15_REFSA CV174 RV80 PX@
120P_0402_50V9 4.99K_0402_1% PX@
2
2
1
1
CV172 CV173
RV78 0.1U_0402_16V7K RV79 0.1U_0402_16V7K
100_0402_1% PX@ 100_0402_1% PX@
2
PX@ PX@
2
A A

ATI_SeymourXT_M2_MEM IF
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
( 1.8V @0mA NC_PCIE_VDDR)

Note: RV2 No stuff for Chelsea 10.19 +1.8VGS
UVG1E
+1.5VGS @ 0_0402_5% RV2 LV6 PX@
For DDR3/GDDR5, MVDDQ = 1.5V PART 5 0F 9 1 2 +PCIE_VDDR 2 1
BLM15BD121SN1D_0402
CV88
CV89
CV92
MEM I/O
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
D
AC7 VDDR1 NC_PCIE_VDDR AA31 1 1 1 D
AD11 VDDR1 NC_PCIE_VDDR AA32
CV87
CV82
CV93
CV94
CV95
CV83
CV96
CV84
CV85
CV97
CV86
CV98
CV99
CV100
CV101
CV102
1 AF7 VDDR1 NC_PCIE_VDDR AA33
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
220U_B2_2.5VM_R35
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG10 VDDR1 NC_PCIE_VDDR AA34

2 2 2
PX@
PX@
PX@
+ AJ7 VDDR1 NC_PCIE_VDDR W30
@ AK8 VDDR1 NC_PCIE_VDDR Y31
AL9 VDDR1 NC_BIF_VDDC V28 (1.8V@200mA
2 PX@ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
G11 VDDR1 NC_BIF_VDDC W29 PCIE_PVDD)
G14 VDDR1 PCIE_PVDD AB37 0.935V
G17
PCIE
VDDR1
G20 VDDR1 PCIE_VDDC G30 (1.0V@1900mA PCIE_VDDC)
G23 VDDR1 PCIE_VDDC G31
CV103
CV104
CV105
CV106
CV107
CV108
G26 VDDR1 PCIE_VDDC H29
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
G29 H30 0.935V
VDDR1 PCIE_VDDC 1 1 1 1 1 1
H10 VDDR1 PCIE_VDDC J29
J7 VDDR1 PCIE_VDDC J30
J9 VDDR1 PCIE_VDDC L28 (0.935V@ 1200mA BIF_VDDC)
2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
VDDR1 CRB Design K11 VDDR1 PCIE_VDDC M28
CV147
CV148
K13 VDDR1 PCIE_VDDC N28
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1u 6 6 K8 VDDR1 PCIE_VDDC R28 1 1
L12 VDDR1 PCIE_VDDC T28
1u 10 5 L16 VDDR1 PCIE_VDDC U28
L21 For Chelsea, Delete 2*1U
10u 6 5 VDDR1
2 2
PX@
PX@
L23 VDDR1
L26 VDDR1 BIF_VDDC N27
BACO
L7 VDDR1 BIF_VDDC T27
+VGA_CORE
VDD_CT CRB Design M11
N11
VDDR1
VDDR1 (0.8~1.1V@ 22000mA VDDC)
PCIE_VDDR CRB Design
0.1u 1 1 P7 VDDR1
CORE
VDDC AA15 0.1u 2 2
R11 VDDR1 VDDC AA17
1u 3 3 1u 1 1
CV109
CV110
CV111
CV112
CV113
CV114
CV115
CV116
CV117
CV118
CV119
CV120
CV121
U11 VDDR1 VDDC AA20
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.8VGS +VDDC_CT U7 AA22
10u 1 1 VDDR1 VDDC 1 1 1 1 1 1 1 1 1 1 1 1 1 10u 1 1
Y11 VDDR1 VDDC AA24
PX@ LV7 (1.8V@250mA VDD_CT) Y7 VDDR1 VDDC AA27
1 2 VDDC AB16
2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
BLM15BD121SN1D_0402 VDDC AB18
CV122
CV123
CV124
CV125
CV126
VDDR3 CRB Design VDDC AB21
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
1 1 1 1 1 VDDC AB23
C 1u 3 3 +3VGS
LEVEL VDDC AB26 C
TRANSLATION VDDC AB28
10u 1 1 2 2 2 2 2
AF26 VDD_CT VDDC AC17 +VGA_CORE
PCIE_VDDC CRB Design
PX@
PX@
PX@
PX@
PX@
AF27 VDD_CT VDDC AC20
AG26 VDD_CT VDDC AC22 1u 7 5 (1@)
CV139
CV140
CV141
CV142
AG27 VDD_CT VDDC AC24

10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10u 1 1
CV127
CV128
CV129
CV130
CV131
CV132
CV133
CV134
CV135
CV136
CV137
CV138
VDDR4 CRB Design 1 1 1 1 VDDC AC27
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDC AD18 1 1 1 1 1 1 1 1 1 1 1 1
0.1u 1 1 I/O VDDC AD21
AF23 VDDR3 VDDC AD23
1u 1 1 2 2 2 2
PX@
PX@
PX@
PX@
AF24 VDDR3 VDDC AD26

2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
AG23 VDDR3 VDDC AF17
+1.8VGS AG24 VDDR3 VDDC AF20 VDDC CRB Design
MPV18 CRB Design PX@ LV8 (1.8V@300mA VDDR4) DVP
VDDC
VDDC
AF22
AG16 1u 30 25
0.1u 2 1 1 2 +VDDR4 AD12 VDDR4 VDDC AG18
+VGA_CORE 10u 10 1
BLM15BD121SN1D_0402 AF11 VDDR4
1u 2 1
CV143
CV144
AF12 AH22
VDDR4 VDDC
22u 0 1
1U_0402_6.3V6K
0.1U_0402_16V7K
1 1 AF13 AH27
10u 1 1 VDDR4 VDDC
VDDC AH28
CV145
CV146
VDDC M26
10U_0603_6.3V6M
22U_0603_6.3V6M
AF15 VDDR4 VDDC N24 1 1
2 2
PX@
PX@
SPV18 CRB Design AG11

AG13
VDDR4
VDDR4
VDDC
VDDC
R18
R21
0.1u 1 1 AG15 VDDR4 VDDC R23
2 2
PX@
PX@
VDDC R26
1u 1 1 VDDC T17
T20
10u 1 1 VDDC
VDDC T22
VDDC T24
VDDC U16
SPV10 CRB Design VDDC
VDDC
U18
U21
0.1u 1 1 VDDC U23
VDDC U26
1u 1 1 VDDC V17
V20
10u 1 1 VDDC
VDDC V22
B B
VDDC V24
VDDC V27
VDDC Y16
VDDC Y18
VDDC Y21
VDDC Y23 +VDDCI
VDDC Y26
VDDC Y28
(DDR3 0.91V@2.2A VDDCI)
VDDCI
VDDCI
AA13
AB13
VDDCI CRB Design
1u 10 9
CV155
CV156
CV157
CV158
CV159
CV160
CV161
CV162
CV163
CV164
CV165
CV167
VDDCI AC12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
VDDCI AC15 1 1 1 1 1 1 1 1 1 1 1 1
VDDCI AD13 10u 3 2
AD16
VDDCI
VDDCI M15
22u 0 1
2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
VDDCI M16
VOLTAGE
VDDCI M18
VDDCI M23
SENESE
N13
ISOLATED
VDDCI
CORE I/O
56 VCC_GPU_SENSE AF28 FB_VDDC VDDCI N15

VDDCI N17
AG28 FB_VDDCI
VDDCI
VDDCI
N20
N22
VDDCI and VDDC should have seperate regulators with a merge option on PCB
54 VDDCI_SEN
VDDCI
VDDCI
R12
R13
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator
56 VSS_GPU_SENSE AH29 FB_GND VDDCI R16
VDDCI T12
VDDCI T15
VDDCI V15
VDDCI Y13
VDDCI and VDDC should have seperate regulators with a merge option on PCB
A
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator A

ATI_SeymourXT_M2_Power
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
UVG1F
PART 6 0F 9
AB39 PCIE_VSS GND A3

E39 PCIE_VSS GND A37
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18
G33 PCIE_VSS GND AA2
G34 PCIE_VSS GND AA21
H31 PCIE_VSS GND AA23
D
H34 PCIE_VSS GND AA26 D
H39 PCIE_VSS GND AA28
J31 PCIE_VSS GND AA6
J34 PCIE_VSS GND AB12
K31 PCIE_VSS GND AB15
L31 PCIE_VSS GND AB22
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27
M39 PCIE_VSS GND AC11
N31 PCIE_VSS GND AC13
UVG1H N34 PCIE_VSS GND AC16
PART 8 0F 9
P31 PCIE_VSS GND AC18
+DPAB_VDD10 0.935V P34 PCIE_VSS GND AC2
DP_VDDR DP_VDDC
P39 PCIE_VSS GND AC21
R34 PCIE_VSS GND AC23
DP_VDDC AP31 +DPAB_VDD10 1 RV48 2 T31 PCIE_VSS GND AC26
+1.8VGS +DPCD_VDD18 DP_VDDC AP32 T34 PCIE_VSS GND AC28
DP_VDDC AN33 0_0603_5% T39 PCIE_VSS GND AC6
DP_VDDC AP33 PX@ U31 PCIE_VSS GND AD15
1 RV47 2 +DPCD_VDD18 AN24 DP_VDDR U34 PCIE_VSS GND AD17
AP24 DP_VDDR DP_VDDC AP13 V34 PCIE_VSS GND AD20
0_0402_5% AP25 DP_VDDR DP_VDDC AT13 V39 PCIE_VSS GND AD22
PX@ AP26 DP_VDDR DP_VDDC AP14 W31 PCIE_VSS GND AD24
AU28 DP_VDDR DP_VDDC AP15 W34 PCIE_VSS GND AD27
AV29 DP_VDDR Y34 PCIE_VSS GND AD9
DP_VDDC AL33 Y39 PCIE_VSS GND AE2
DP_VDDC AM33 GND AE6
AP20 DP_VDDR DP_VDDC AK33 GND AF10
AP21 DP_VDDR DP_VDDC AK34 GND AF16
AP22 DP_VDDR GND AF18
AP23 DP_VDDR GND GND AF21
AU18 DP_VDDR GND AG17
AV19 DP_VDDR F15 GND GND AG2
DP GND
F17 GND GND AG20
DP_VSSR AN27 F19 GND GND AG22
AH34 DP_VDDR DP_VSSR AP27 F21 GND GND AG6
C AJ34 DP_VDDR DP_VSSR AP28 F23 GND GND AG9 C
AF34 DP_VDDR DP_VSSR AW24 F25 GND GND AH21
AG34 DP_VDDR DP_VSSR AW26 F27 GND GND AJ10
AM37 DP_VDDR DP_VSSR AN29 F29 GND GND AJ11
AL38 DP_VDDR DP_VSSR AP29 F31 GND GND AJ2
DP_VSSR AP30 F33 GND GND AJ28
DP_VSSR AW30 F7 GND GND AJ6
DP_VSSR AW32 F9 GND GND AK11
DP_VSSR AN17 G2 GND GND AK31
DP_VSSR AP16 G6 GND GND AK7
DP_VSSR AP17 H9 GND GND AL11
DP_VSSR AW14 J2 GND GND AL14
DP_VSSR AW16 J27 GND GND AL17
DP_VSSR AN19 J6 GND GND AL2
DP_VSSR AP18 J8 GND GND AL20
DP_VSSR AP19 K14 GND
DP_VSSR AW20 K7 GND GND AL23
CALIBRATION
DP_VSSR AW22 L11 GND GND AL26
DP_VSSR AN34 L17 GND GND AL32
DP_VSSR AP39 L2 GND GND AL6
150_0402_1% 2 PX@ 1 RV51 AW28 DPAB_CALR DP_VSSR AR39 L22 GND GND AL8
DP_VSSR AU37 L24 GND GND AM11
DP_VSSR AF39 L6 GND GND AM31
DP_VSSR AH39 M17 GND GND AM9
150_0402_1% 2 PX@ 1 RV50 AW18 DPCD_CALR DP_VSSR AK39 M22 GND GND AN11
DP_VSSR AL34 M24 GND GND AN2
DP_VSSR AV27 N16 GND GND AN30
DP_VSSR AR28 N18 GND GND AN6
150_0402_1% 2 PX@ 1 RV55 AM39 DPEF_CALR DP_VSSR AV17 N2 GND GND AN8
DP_VSSR AR18 N21 GND GND AP11
DP_VSSR AN38 N23 GND GND AP7
DP_VSSR AM35 N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
B
R22 GND GND B19 B
R24 GND GND B21
2160834000A10CHELSE_FCBGA962 R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND
U27 GND
U6 GND
V11 GND
V16 GND
V18 GND
V21 GND
V23 GND
V26 GND
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND VSS_MECH A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39
A A

ATI_SetmourXT_M2_PWR_GND
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
11/25 swap UV5.F8/ UV5.H8 =>MDA3/MDA0

UV5 UV6 UV7 UV8
VREFC_A1 M8 E3 MDA5 MDA10 VREFC_A2 M8 E3 MDA13 MDA5 VREFC_A3 M8 E3 MDA54 VREFC_A4 M8 E3 MDA42 MDA40
VREFD_Q1 VREFCA DQL0 MDA1 MDA14 VREFD_Q2 VREFCA DQL0 MDA14 MDA0 VREFD_Q3 VREFCA DQL0 MDA53 VREFD_Q4 VREFCA DQL0 MDA44
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 MDA6 MDA9 VREFDQ DQL1 MDA9 MDA6 VREFDQ DQL1 MDA55 VREFDQ DQL1 MDA47 MDA45
F2 F2 F2 F2
MAA0 DQL2 MDA3 MDA11 MAA0 DQL2 MDA11 MDA1 MAA0 DQL2 MDA50 MAA0 DQL2 MDA40 MDA42
N3 F8 N3 F8 N3 F8 N3 F8
MAA1 A0 DQL3 MDA4 MDA15 MAA1 A0 DQL3 MDA15 MDA4 MAA1 A0 DQL3 MDA49 MAA1 A0 DQL3 MDA46
P7 H3 P7 H3 P7 H3 P7 H3
P3 H8 P3 H8 P3 H8 P3 H8
MAA3 A2 DQL5 MDA7 MDA8 MAA3 A2 DQL5 MDA8 MDA7 MAA3 A2 DQL5 MDA52 MAA3 A2 DQL5 MDA45 MDA47
N2 G2 N2 G2 N2 G2 N2 G2
P8 H7 P8 H7 P8 H7 P8 H7
MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7
P2 P2 P2 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 R8 R8 R8
D MDA[0..63] MAA7 A6 MDA25 MDA20 MAA7 A6 MDA20 MDA25 MAA7 A6 MDA63 MAA7 A6 MDA32 D
R2 D7 R2 D7 R2 D7 R2 D7
24 MDA[0..63] MAA8 A7 DQU0 MDA31 MDA19 MAA8 A7 DQU0 MDA19 MDA31 MAA8 A7 DQU0 MDA59 MAA8 A7 DQU0 MDA36
T8 C3 T8 C3 T8 C3 T8 C3
MAA9 A8 DQU1 MDA27 MDA23 MAA9 A8 DQU1 MDA23 MDA27 MAA9 A8 DQU1 MDA62 MAA9 A8 DQU1 MDA33
R3 C8 R3 C8 R3 C8 R3 C8
MAA10 A9 DQU2 MDA28 MDA18 MAA10 A9 DQU2 MDA18 MDA28 MAA10 A9 DQU2 MDA56 MAA10 A9 DQU2 MDA39
L7 C2 L7 C2 L7 C2 L7 C2
MAA11 A10/AP DQU3 MDA26 MDA22 MAA11 A10/AP DQU3 MDA22 MDA26 MAA11 A10/AP DQU3 MDA60 MAA11 A10/AP DQU3 MDA35
R7 A7 R7 A7 R7 A7 R7 A7
MAA12 A11 DQU4 MDA30 MDA16 MAA12 A11 DQU4 MDA16 MDA30 MAA12 A11 DQU4 MDA57 MDA58 MAA12 A11 DQU4 MDA38
N7 A2 N7 A2 N7 A2 N7 A2
MAA[13..0] MAA13 A12 DQU5 MDA24 MDA21 MAA13 A12 DQU5 MDA21 MDA24 MAA13 A12 DQU5 MDA61 MAA13 A12 DQU5 MDA34
24 MAA[13..0] T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 MDA29 MDA17 A13 DQU6 MDA17 MDA29 A13 DQU6 MDA58 MDA57 A13 DQU6 MDA37
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

24 A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
DQMA#[7..0] 24 A_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
24 DQMA#[7..0] 24 A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
VDD VDD VDD VDD
K8 K8 K8 K8
VDD VDD VDD VDD
N1 N1 N1 N1
VDD CLKA0 VDD VDD CLKA1 VDD
24 CLKA0 J7 N9 J7 N9 24 CLKA1 J7 N9 J7 N9
CK VDD CLKA0# CK VDD CK VDD CLKA1# CK VDD
24 CLKA0# K7 R1 K7 R1 24 CLKA1# K7 R1 K7 R1
QSA[7..0] CK VDD CKEA0 CK VDD CK VDD CKEA1 CK VDD
24 QSA[7..0] 24 CKEA0 K9 R9 K9 R9 24 CKEA1 K9 R9 K9 R9
CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
24 ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 24 ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
24 CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ 24 CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
24 RASA0# RAS VDDQ RAS VDDQ 24 RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
QSA#[7..0] 24 CASA0# CAS VDDQ CAS VDDQ 24 CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
24 QSA#[7..0] 24 WEA0# WE VDDQ WE VDDQ 24 WEA1# WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSA1 QSA0 VDDQ QSA0 QSA1 VDDQ QSA6 VDDQ QSA5 VDDQ
F3 H2 F3 H2 F3 H2 F3 H2
QSA2 QSA3 DQSL VDDQ QSA3 QSA2 DQSL VDDQ QSA7 DQSL VDDQ QSA4 DQSL VDDQ
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
DQMA#1 DQMA#0 E7 A9 DQMA#0 DQMA#1 E7 A9 DQMA#6 E7 A9 DQMA#5 E7 A9

DQMA#2 DQMA#3 DML VSS DQMA#3 DQMA#2 DML VSS DQMA#7 DML VSS DQMA#4 DML VSS
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
E1 E1 E1 E1
VSS VSS VSS VSS
G8 G8 G8 G8
QSA#1 QSA#0 VSS QSA#0 QSA#1 VSS QSA#6 VSS QSA#5 VSS
C G3 J2 G3 J2 G3 J2 G3 J2 C
QSA#2 QSA#3 DQSL VSS QSA#3 QSA#2 DQSL VSS QSA#7 DQSL VSS QSA#4 DQSL VSS
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M1 M1 M1 M1
VSS VSS VSS VSS
M9 M9 M9 M9
VSS VSS VSS VSS
P1 P1 P1 P1
VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS
24,28 DRAM_RST# T2 P9 P9 P9 P9
RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
RV83 NC/ODT1 VSSQ RV84 NC/ODT1 VSSQ RV85 NC/ODT1 VSSQ RV86 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J9 D1 240_0402_1% J9 D1 240_0402_1% J9 D1 240_0402_1% J9 D1
PX@ NC/CE1 VSSQ PX@ NC/CE1 VSSQ PX@ NC/CE1 VSSQ PX@ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
PX@ H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
CLKA0 1 2
RV87 40.2_0402_1%
PX@
CLKA0# 1 2
RV88 40.2_0402_1%
1
CV177
0.01U_0402_16V7K +1.5VGS +1.5VGS
PX@ +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
2
1
RV89 RV90 RV91 RV92 RV93 RV94 RV95 RV96
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
B B
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
PX@
2
2
CLKA1 1 2
RV97 40.2_0402_1% VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PX@
CV180
CV181
CV182
CV178
CV183
CV184
CV185
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CLKA1# 1 RV99 RV100 RV102 RV103 RV104 RV105 RV106 RV101
CV186
2
RV98 40.2_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
1
CV179 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2
2
0.01U_0402_16V7K PX@ PX@ PX@
2
2
PX@
2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV187
CV188
CV189
CV190
CV191
CV192
CV193
CV194
CV195
CV196
CV197
CV198
CV199
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV200
CV201
CV202
CV203
CV204
CV205
CV206
CV207
CV208
CV209
CV210
CV211
CV212
CV213
CV214
CV215
CV216
CV217
CV218
CV219
CV220
CV221
CV222
CV223
1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A

ATI_SeymourXT_M2_VRAM_A
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
UV9 UV10 UV11 UV12
VREFC_A1_B M8 E3 MDB19 VREFC_A2_B M8 E3 MDB4 VREFC_A3_B M8 E3 MDB55 MDB33 VREFC_A4_B M8 E3 MDB33 MDB55
VREFD_Q1_B H1 VREFCA DQL0 MDB21 VREFD_Q2_B VREFCA DQL0 MDB3 VREFD_Q3_B VREFCA DQL0 MDB50 MDB38 VREFD_Q4_B VREFCA DQL0 MDB38 MDB50
F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 MDB16 MDB17 VREFDQ DQL1 MDB5 VREFDQ DQL1 MDB54 MDB39 VREFDQ DQL1 MDB39 MDB54
F2 F2 F2 F2
MAB0 DQL2 MDB18 MAB0 DQL2 MDB0 MAB0 DQL2 MDB51 MDB36 MAB0 DQL2 MDB36 MDB51
N3 F8 N3 F8 N3 F8 N3 F8
MAB1 A0 DQL3 MDB20 MAB1 A0 DQL3 MDB6 MAB1 A0 DQL3 MDB53 MDB35 MAB1 A0 DQL3 MDB35 MDB53
P7 H3 P7 H3 P7 H3 P7 H3
P3 H8 P3 H8 P3 H8 P3 H8
MAB3 A2 DQL5 MDB17 MDB16 MAB3 A2 DQL5 MDB7 MAB3 A2 DQL5 MDB52 MDB37 MAB3 A2 DQL5 MDB37 MDB52
N2 G2 N2 G2 N2 G2 N2 G2
P8 H7 P8 H7 P8 H7 P8 H7
MAB5 A4 DQL7 MAB5 A4 DQL7 MAB5 A4 DQL7 MAB5 A4 DQL7
P2 P2 P2 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 R8 R8 R8
MAB7 A6 MDB15 MAB7 A6 MDB26 MAB7 A6 MDB40 MDB62 MAB7 A6 MDB62 MDB40
R2 D7 R2 D7 R2 D7 R2 D7
D MDB[0..63] MAB8 A7 DQU0 MDB11 MAB8 A7 DQU0 MDB27 MAB8 A7 DQU0 MDB47 MDB58 MAB8 A7 DQU0 MDB58 MDB47 D
T8 C3 T8 C3 T8 C3 T8 C3
24 MDB[0..63] MAB9 A8 DQU1 MDB14 MAB9 A8 DQU1 MDB24 MDB28 MAB9 A8 DQU1 MDB42 MDB63 MAB9 A8 DQU1 MDB63 MDB42
R3 C8 R3 C8 R3 C8 R3 C8
MAB10 A9 DQU2 MDB10 MAB10 A9 DQU2 MDB31 MAB10 A9 DQU2 MDB46 MDB56 MAB10 A9 DQU2 MDB56 MDB46
L7 C2 L7 C2 L7 C2 L7 C2
MAB11 A10/AP DQU3 MDB12 MAB11 A10/AP DQU3 MDB28 MDB24 MAB11 A10/AP DQU3 MDB43 MDB61 MAB11 A10/AP DQU3 MDB61 MDB43
R7 A7 R7 A7 R7 A7 R7 A7
N7 A2 N7 A2 N7 A2 N7 A2
T3 B8 T3 B8 T3 B8 T3 B8
MAB[13..0] A13 DQU6 MDB8 A13 DQU6 MDB30 A13 DQU6 MDB44 MDB59 A13 DQU6 MDB59 MDB44
24 MAB[13..0] T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

24 B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
24 B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
DQMB#[7..0] 24 B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
24 DQMB#[7..0] K2 K2 K2 K2
VDD VDD VDD VDD
K8 K8 K8 K8
VDD VDD VDD VDD
N1 N1 N1 N1
VDD CLKB0 VDD VDD CLKB1 VDD
24 CLKB0 J7 N9 J7 N9 24 CLKB1 J7 N9 J7 N9
CK VDD CLKB0# CK VDD CK VDD CLKB1# CK VDD
24 CLKB0# K7 R1 K7 R1 24 CLKB1# K7 R1 K7 R1
CK VDD CKEB0 CK VDD CK VDD CKEB1 CK VDD
24 CKEB0 K9 R9 K9 R9 24 CKEB1 K9 R9 K9 R9
QSB[7..0] CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
24 QSB[7..0]
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
24 ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 24 ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
24 CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ 24 CSB1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
24 RASB0# RAS VDDQ RAS VDDQ 24 RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
24 CASB0# CAS VDDQ CAS VDDQ 24 CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
QSB#[7..0] 24 WEB0# WE VDDQ WE VDDQ 24 WEB1# WE VDDQ WE VDDQ
24 QSB#[7..0] E9 E9 E9 E9
VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSB2 VDDQ QSB0 VDDQ QSB4 QSB6 VDDQ QSB6 QSB4 VDDQ
F3 H2 F3 H2 F3 H2 F3 H2
QSB1 DQSL VDDQ QSB3 DQSL VDDQ QSB7 QSB5 DQSL VDDQ QSB5 QSB7 DQSL VDDQ
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
DQMB#2 E7 A9 DQMB#0 E7 A9 DQMB#5 DQMB#6 E7 A9 DQMB#6 DQMB#4 E7 A9

DQMB#1 DML VSS DQMB#3 DML VSS DQMB#7 DQMB#5 DML VSS DQMB#5 DQMB#7 DML VSS
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
E1 E1 E1 E1
VSS VSS VSS VSS
G8 G8 G8 G8
QSB#2 VSS QSB#0 VSS QSB#4 QSB#6 VSS QSB#6 QSB#4 VSS
G3 J2 G3 J2 G3 J2 G3 J2
PX@ QSB#1 DQSL VSS QSB#3 DQSL VSS QSB#7 QSB#5 DQSL VSS QSB#5 QSB#7 DQSL VSS
C B7 J8 B7 J8 B7 J8 B7 J8 C
CLKB0 1 DQSU VSS DQSU VSS DQSU VSS DQSU VSS
2 M1 M1 M1 M1
RV107 40.2_0402_1% VSS VSS VSS VSS
M9 M9 M9 M9
VSS VSS VSS VSS
P1 P1 P1 P1
PX@ VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS DRAM_RST# T2 VSS
24,27 DRAM_RST# T2 P9 P9 P9 P9
CLKB0# 1 RESET VSS RESET VSS RESET VSS RESET VSS
2 T1 T1 T1 T1
RV108 40.2_0402_1% VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
CV224
1
1
0.01U_0402_16V7K J1 B1 J1 B1 J1 B1 J1 B1
PX@ RV109 NC/ODT1 VSSQ RV110 NC/ODT1 VSSQ RV111 NC/ODT1 VSSQ RV112 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
2
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ

240_0402_1% J9 D1 240_0402_1% J9 D1 240_0402_1% J9 D1 240_0402_1% J9 D1
PX@ NC/CE1 VSSQ PX@ NC/CE1 VSSQ PX@ NC/CE1 VSSQ PX@ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
PX@ VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
CLKB1 1 VSSQ VSSQ VSSQ VSSQ
2
RV113 40.2_0402_1% 96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
PX@ H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
CLKB1# 1 2
RV114 40.2_0402_1%
1
CV225
0.01U_0402_16V7K
PX@
2
+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

B B
1
1
RV115 RV116 RV117 RV118 RV119 RV120 RV121 RV122
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2
2
VREFD_Q1_B VREFC_A1_B VREFC_A2_B VREFD_Q2_B VREFC_A3_B VREFD_Q3_B VREFC_A4_B VREFD_Q4_B
CV226
CV227
CV229
CV230
CV231
CV232
CV233
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
CV228
1 1 1 1 1 1 1
0.1U_0402_16V7K
1
1 RV124 RV125 RV126 RV128 RV127 RV129 RV130

RV123 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% PX@ PX@ PX@ PX@ PX@ PX@ PX@
2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2
2
2
PX@
2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
CV234
CV235
CV236
CV237
CV238
CV239
CV240
CV241
CV242
CV243
CV244
CV245
CV246
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV247
CV248
CV249
CV250
CV251
CV252
CV253
CV254
CV255
CV256
CV257
CV258
CV259
CV260
CV261
CV262
CV263
CV264
CV265
CV266
CV267
CV268
CV269
CV270
1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A

ATI_SeymourXT_M2_VRAM_B
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
PCH_DPB_P3_C 0.1U_0402_16V7K 1 2 C1 PCH_DPB_P3 PCH_DPB_P3 15 +3VS

PCH_DPB_N3_C 0.1U_0402_16V7K 1 2 C2 PCH_DPB_N3 PCH_DPB_N3 15 HDMI 2.2K_0402_5%
R2696
PCH_DPB_P2_C 0.1U_0402_16V7K 1 2 C3 PCH_DPB_P2 PCH_DPB_P2 15 1 2
PCH_DPB_N2_C 0.1U_0402_16V7K 1 2 C4 PCH_DPB_N2 PCH_DPB_N2 15
PCH_DPB_P1_C 0.1U_0402_16V7K 1 C5 PCH_DPB_P1
Follow Intel
PCH_DPB_N1_C 0.1U_0402_16V7K 1
2
2 C6 PCH_DPB_N1
PCH_DPB_P1 15
PCH_DPB_N1 15
Feedback putting 5V PULL UP IN CONNECTER SIDE
PCH_DPB_P0_C 0.1U_0402_16V7K 1 C7 PCH_DPB_P0
2.2K ohm
2 PCH_DPB_P0 15
5
PCH_DPB_N0_C 0.1U_0402_16V7K 1 2 C8 PCH_DPB_N0 PCH_DPB_N0 15
D Q147B D
HDMI_L_SCLK 4 3 HDMI_SCLK
15 PCH_DDPB_CLK HDMI_SCLK 30
1
1
R3 680_0402_5%
R4 680_0402_5%
R5 680_0402_5%
R6 680_0402_5%
R7 680_0402_5%
R8 680_0402_5%
R9 680_0402_5%
R10 680_0402_5%
2N7002DWH_SOT363-6
SB00000AR10 @
10P_0402_50V8J
1
2N7002KDW_SOT363-6 C4617
2
2
Q47B
3 4
2
+3VS
R2694
5
+3VS 1 2 1 2
1
R2700
0_0402_5% R2695 2.2K_0402_5%
100K_0402_5%
2
2
1 6 HDMI_SDATA
15 PCH_DDPB_DAT HDMI_SDATA 30
C
2N7002DWH_SOT363-6 @ C
10P_0402_50V8J
SB00000AR10 Q147A 1
SM070001310 400ma 90ohm@100mhz DCR 0.3 C4618
+3VS
@
PCH_DPB_P3_C R2702 1 0_0402_5% HDMI_R_CK+ @1 2
2 2
C509 33P_0402_50V8J
1 1 2 2
1
L28 R2697
WCM-2012-900T_0805 Place closed to JHDMI1
4 3 1M_0402_5%
4 3
2
PCH_DPB_N3_C R2703 1 2 0_0402_5% HDMI_R_CK- @1 2 L27
2
@ C510 33P_0402_50V8J MBK1608221YZF_2P
1 6 HDMI_DETECT 1 2 HP_DETECT
15 PCH_DDPB_HPD
@
20K_0402_5%
PCH_DPB_P0_C R2707 1 2 0_0402_5% HDMI_R_D0+ @1 2 1
Q47A
1
C511 33P_0402_50V8J
1
1 2 2N7002KDW_SOT363-6 D56 C4615
L29 1 2 R2699 220P_0402_50V7K
5V Level BAV99-7-F_SOT23-3
2
WCM-2012-900T_0805 @
4 4 3 3
3
PCH_DPB_N0_C R2708 1 2 0_0402_5% HDMI_R_D0- @1 2
B @ C512 33P_0402_50V8J B
+3VS
PCH_DPB_P1_C R2709 1 @ 2 0_0402_5% HDMI_R_D1+ @1 2
C513 33P_0402_50V8J
1 2 JHDMI1 CONN@
L30 1 2 HP_DETECT 19 HP_DET
WCM-2012-900T_0805 +HDMI_5V_OUT 18 +5V
4 4 3 3 17 DDC/CEC_GND
HDMI_SDATA 16
PCH_DPB_N1_C R2710 0_0402_5% HDMI_R_D1- @1 HDMI_SCLK SDA
1 2 2 15 SCL
@ C514 33P_0402_50V8J 14 Reserved
13 CEC
PCH_DPB_P2_C R2711 1 @ 2 0_0402_5% HDMI_R_D2+ @1 2 HDMI_R_CK- 12
C515 33P_0402_50V8J CK-
11 CK_shield
1 2 HDMI_R_CK+ 10
L31 1 2 HDMI_R_D0- CK+
9 D0-
WCM-2012-900T_0805 8
HDMI_R_D0+ D0_shield
4 4 3 3 7 D0+
HDMI_R_D1- 6
PCH_DPB_N2_C R2712 1 0_0402_5% HDMI_R_D2- @1 D1-
2 2 5 D1_shield
@ C516 33P_0402_50V8J HDMI_R_D1+ 4 23
HDMI_R_D2- D1+ GND
3 D2- GND 22
2 D2_shield GND 21
HDMI_R_D2+ 1 20
A D2+ GND A
TYCO_2041343-1~D

HDMI Conn
0.1
5 4 3 2 1
A B C D E
CRT CONNECTOR
1
D3 @ D13 @ D15 @
+3VS
DAN217_SC59 DAN217_SC59 DAN217_SC59 JCRT1
3
6
1 T65 PAD 11 1
CRT_R_L 1
7
CRT_DDC_DAT 12
PCH_CRT_R PCH_CRT_R L3 1 2 NBQ100505T-800Y_0402 CRT_R_L CRT_G_L 2
15 PCH_CRT_R
8
PCH_CRT_G PCH_CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L HSYNC 13
15 PCH_CRT_G
CRT_B_L 3
PCH_CRT_B PCH_CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L +CRT_VCC 9
15 PCH_CRT_B
VSYNC 14 G 16
T66 PAD 4 G 17
R165 R164 R2729 10
CRT_DDC_CLK
150_0402_1%
150_0402_1%
150_0402_1%
15
1
R160 R157 R2713 5
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1
1
CONN@ C-H_13-12201503CP
C2561 C2571 C2471 C2521 C2551 C2511
USE old footrprint need update
2
2 2 2 2 2 2
2
Remove CRT EMI C and R

C-H_13-12201503CP_15P-T
+3VS
+3VS
+CRT_VCC
2 2
1
1 2 R548 R547
C2611 0.1U_0402_10V7K 2 1 2.2K_0402_5% 2.2K_0402_5%
R159 10K_0402_5%
5
1
2
2
2
Q205A
OE#
P
15 PCH_CRT_HSYNC PCH_CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC PCH_CRT_CLK 1 6 CRT_DDC_CLK
A Y 15 PCH_CRT_CLK
+CRT_VCC L6 10_0402_5%
G
5
U7 2N7002DW -T/R7_SOT363-6
SN74AHCT1G125GW _SOT353-5 Q206B
3
5
1
PCH_CRT_DATA 4 3 CRT_DDC_DAT
15 PCH_CRT_DATA
1 1
OE#
P
15 PCH_CRT_VSYNC PCH_CRT_VSYNC 2 4 D_CRT_VSYNC
1 2 VSYNC 1 1 2N7002DW -T/R7_SOT363-6
A Y L12 10_0402_5% C2841 C2831
10P_0402_50V8J
10P_0402_50V8J
1 1
G
U8 C2821 C2851 470P_0402_50V8J 470P_0402_50V8J
SN74AHCT1G125GW _SOT353-5 C2581 C2591 33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
3
@ @ @ 2 2 @
2 2
D8
3 W=40mils 3
+5VS 1 2 2 1
F1
1.1A_6V_SMD1812P110TF
RB751V_SOD323
+CRT_VCC +HDMI_5V_OUT
+CRT_VCC +HDMI_5V_OUT
1 1
C2601 C4616
1
0.1U_0402_10V7K 0.1U_0402_16V4Z
1
@ 2 2
R575 R576 R545 R546
4.7K_0402_5% 4.7K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2
2
CRT_DDC_CLK HDMI_SDATA
HDMI_SDATA 29
CRT_DDC_DAT HDMI_SCLK HDMI_SCLK 29
4 4
For CRT For HDMI

CRT
0.1
LA-8711
A B C D E
5 4 3 2 1
WLAN&BT Combo module circuits

BT BT
on module on module
Enable Disable
BT_CRTL HI LO WLAN
+1.5VS_W LAN
BT_PWR# LO HI SI# 7/25 change BT_ON# to BT_ON +3V_AOAC +3V_AOAC
D D
11/25 connect EC_PCIE_WAKE# to KBC R84
0_0402_5% JMINI1 CONN@
36 EC_PCIE_W AKE# 1 2 1 1 2 2
3 3 4 4
BT_ON 1 R93 2 BT_ON_L 5 6
0_0402_5% 5 6 LPC_FRAME#
14 MINI1_CLKREQ# 7 7 8 8 LPC_FRAME# 13,36
9 10 LPC_AD3
9 10 LPC_AD3 13,36
11 12 LPC_AD2
14 CLK_PCIE_MINI1# 11 12 LPC_AD2 13,36
13 14 LPC_AD1
1 D 14 CLK_PCIE_MINI1 13 14 LPC_AD1 13,36
15 16 LPC_AD0
15 16 LPC_AD0 13,36
17 BT_ON# BT_ON# 2
G R91
Q26 S PLT_RST# 0_0402_5% 17 18
5,16,21,34,36 PLT_RST#
3
2N7002_SOT23-3 CLK_PCI_DEBUG 1 17 18
16 CLK_PCI_DEBUG 2CLK_PCI_DEBUG_L 19 19 20 20 W L_OFF# W L_OFF# 16
21 22 PLT_RST_BUF# PLT_RST_BUF# 16
21 22 R85
14 PCIE_PRX_DTX_N3 23 23 24 24 1 2 0_0603_5% +3V_AOAC
14 PCIE_PRX_DTX_P3 25 25 26 26
27 27 28 28
29 29 30 30
14 PCIE_PTX_C_DRX_N3 31 31 32 32 Remove SM bus 11/23 by Sharing
14 PCIE_PTX_C_DRX_P3 33 33 34 34
35 36 USB20_N10_R R88 1 2 0_0402_5%
35 36 USB20_N10 16 SI# 7/25 change USB20_N/P4 to USB_N/P9
37 38 USB20_P10_R R89 1 2 0_0402_5%
37 38 USB20_P10 16
39 39 40 40
41 41 42 42
43 44 R90 1 2 0_0402_5% MINI1_LED#
43 44 MINI1_LED# 36
R58 45 46 R101 1 2 0_0402_5%
0_0402_5% 45 46
47 47 48 48
1
C E51TXD_P80DATA 1 2 E51TXD_P80DATA2_R 49 50 C
36 E51TXD_P80DATA 49 50
36 E51RXD_P80CLK 1 2 E51RXD_P80CLK_R 51 51 52 52 R92
53 54 4.7K_0402_5%
0_0402_5% G1 G2
1
R57
(9~16mA)
2
BELLW _80003-2021
R70
+3V_AOAC
100K_0402_5%
2
BT_ON 2 1 E51RXD_P80CLK_R
1K_0402_5%
For Wireless LAN R326
+3V_AOAC SI# 7/19 PIN 51 need add 1K for BT combo card

+1.5VS +1.5VS_W LAN 9/8 SI build BOT limit 0.8, C82,C86
60mil
del: SE053475Z80
R82 0_0603_5% add: SE107475K80
1 1 1 2
C86 C87 1 1 1
C82 C83 C84
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 4.7U_0603_6.3V6K
2 2 2
Mini Card Power Rating
AOAC_PW _ON# 36 Power Primary Power (mA) Auxiliary Power (mA)
1
B B
R370
Peak Normal Normal
1K_0402_5% +3Valw 1000 750
@ C69 +3V 330 250 250 (wake enable)
2
+3V_AOAC 1 2
+3V_AOAC
+1.5VS 500 375 5 (Not wake enable)
2
0.1U_0402_16V4Z
0.047U_0402_16V7K
G
1
C85 1 3 +3VALW
D
2 SI# BOM change R370, C69, Q11 no stuff, Stuff R83

Q11 For AOAC +3VALW change to +3VS
AO3413L_SOT23-3
A A

MiniCard & WLan
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
SI# 8/15 R62 change to +3VALW, R61change to 10 ohm, R63 change to 200K ohm
+LCDVDD INVPWR_B+ L7 B+
LCD POWER CIRCUIT Place closed to JLVDS1
W=60mils FBMA-L11-201209-221LMA30T_0805
2 1
1
+3VALW +3VS +LCDVDD L8
R61 +3VS FBMA-L11-201209-221LMA30T_0805
W=60mils
30_0603_5% 2 1
0.1U_0402_16V7K
1 1 1 1 1
2
R62 1 C56 C57 C58 C59 C60 SM010014520 3000ma
100K_0402_5% 680P_0402_50V7K 68P_0402_50V8J
D
C55 0.1U_0402_16V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z
220ohm@100mhz D
6
2 2 2 2 2 DCR 0.04
2
R63 2
3
200K_0402_5% S Q7
2 2 1 2 AO3413L_SOT23-3
Q6A
1 1 G
D
LCD/LED PANEL Conn.
1
0.01U_0402_25V7K +LCDVDD +3VS
C61
W=60mils W=60mils
2 W=60mils LCD_CLK
R64 1 2 2.2K_0402_5%
1 1 R65 1 2 2.2K_0402_5% LCD_DATA
3
C63 1 1
0.1U_0402_16V4Z @ C64 @ C65
C62 10P_0402_50V8J 10P_0402_50V8J
PCH_ENVDD 5 2 2 C66 2 1 220P_0402_50V7K INVTPWM
15 PCH_ENVDD 2 2
4.7U_0603_6.3V6K
Q6B C67 2 1 220P_0402_50V7K DISPOFF#
4
9/8 SI build BOT limit 0.8, C62
del: SE053475Z80
add: SE107475K80 Check pin definition.
C C
11/23 remove INVT_PWM
INVTPWM
15 DPST_PWM 1 R197 2 0_0402_5%

+LCDVDD
1
@ @
R72 R156 1 2 0_0402_5%
10K_0402_5%
L11 JLVDS1
1 2 USB20_P8_R 1
16 USB20_P8
2
1 2 1
2 2
3 3
4 3 USB20_N8_R 4
16 USB20_N8 4 3 4
LCD_CLK 5
WCM-2012-900T_4P LCD_DATA 5
6 6
15 PCH_TXOUT0+ 7 7
1 R229 2 0_0402_5% 15 PCH_TXOUT0- 8 8
9 9
R76 33_0402_5% @ 10
15 PCH_TXOUT1+ 10
36 BKOFF# BKOFF# 1 2 DISPOFF# 8/19 change stuff L26 by EMI request 11
15 PCH_TXOUT1- 11
12 12
15 PCH_TXOUT2+ 13 13
1
15 PCH_TXOUT2- 14 14
R74 15 15
B 10K_0402_5% 15 PCH_TXCLK+ 16 16 B
15 PCH_TXCLK- 17 17
18
2
USB20_N8_R 18
19 19
USB20_P8_R 20
DISPOFF# 20
D55 21 21
INVTPWM 22
D_MIC_CLK 22
2 2 INVPWR_B+ 23 23
R193 1 24
PCH_LCD_CLK LCD_CLK D_MIC_DATA 1 24
15 PCH_LCD_CLK 2 1 3 3 25 25
0_0402_5% 26
R194 26
PESD5V0U2BT +3VS 27 27
15 PCH_LCD_DATA 2 1 LCD_DATA 28
0_0402_5% @ D_MIC_CLK 28
29 29
6/27 Add ESD solution D_MIC_DATA 30 30
31 GND
32 GND
33 GND
34 GND
35 GND
STARC_111H30-000000-G4-R
100_0402_5% RA13 LA19 FBMA-L10-160808-301LMT_2P
D_MIC_CLK_L_C 2 1D_MIC_CLK_L 1 2 D_MIC_CLK CONN@
38 D_MIC_CLK_L_C D_MIC_DATA_C 1 2 D_MIC_DATA
38 D_MIC_DATA_C LA20 FBMA-L10-160808-301LMT_2P
A A

LVDS Connector
0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
PV# 9/17 JMINI2/JMINI3 change footprint follow ME connector list

+3VS
1
+3VS_MSATA
mSATA Conn. R52
0_0805_5%
1 1
C44 C45
2
JMINI2 CONN@
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2 +3VS_MSATA
2 2 1 2
3 4
3 4 +3VS +3VS_SATA_RE
5 6
5 6
7 8
Change to 0.01U cap. PN 9
11
7
9
8
10
10
12 @ R103 1 2 0_0603_5%
D 11 12 D
13 14
13 14
15 16
15 16
17 18
17 18 +3VS_SATA_RE
19 20
R133 0_0402_5% C621 0.01U_0402_16V7K 19 20 +3VS_SATA_RE
21 22
21 22
13 SATA_PRX_DTX_P1 1 2 SATA_PRX_R1_DTX_P1 SATA_PRX_R_DTX_P1 1 2 SATA_PRX_C_DTX_P1 23 24
23 24
13 SATA_PRX_DTX_N1 1 2 SATA_PRX_R1_DTX_N1 SATA_PRX_R_DTX_N1 1 2 SATA_PRX_C_DTX_N1 25 26
25 26
2
R161 0_0402_5% C615 0.01U_0402_16V7K 27 28
R163 0_0402_5% C622 0.01U_0402_16V7K 27 28 R136
29 30 1 2
29 30
13 SATA_PTX_DRX_N1 1 2 SATA_PTX_R1_DRX_N1 SATA_PTX_R_DRX_N1 1 2 SATA_PTX_C_DRX_N1 31 32 10K_0402_5% C46 @
31 32
13 SATA_PTX_DRX_P1 1 2 SATA_PTX_R1_DRX_P1 SATA_PTX_R_DRX_P1 1 2 SATA_PTX_C_DRX_P1 33 34 C4619
@
R162 0_0402_5% C620 0.01U_0402_16V7K 33 34 0.1U_0402_16V4Z 0.01U_0402_25V7K
35 36
1
35 36 U71 2 1
37 38
37 38
+3VS_MSATA 39 40 7 6
39 40 EN VDD
41 42 16
41 42 SATA_PTX_R1_DRX_P1 VDD
43 44 1
43 44 SATA_PTX_R1_DRX_N1 A_INp
45 46 2 10
45 46 A_INn NC R4610
47 48 PCH side 20 1 2
47 48 SATA_PRX_R1_DTX_P1 REXT
49 50 5
HDD_DETECT# 49 50 SATA_PRX_R1_DTX_N1 B_OUTp A_PRE0 4.99K_0402_1%~D
17 HDD_DETECT# 1 2 51 52 4 9
51 52 B_OUTn A_PRE0 B_PRE0
53 54 8
0_0402_5% G1 G2 B_PRE1 B_PRE0
R59
17
B_PRE1 11/25 add R4610 4.99k -> Parade review
A_PRE1 19 15 SATA_PTX_R_DRX_P1
BELLW_80003-2021 A_PRE1 A_OUTp SATA_PTX_R_DRX_N1
14
@ R143 2 A_OUTn
+3VS_SATA_RE 1 10K_0402_5% 18 Connector side
TEST SATA_PRX_R_DTX_P1
3 11
GND B_INp SATA_PRX_R_DTX_N1
13 12
GND B_INn
21
EPAD
PS8520BTQFN20GTR2_TQFN20_4X4
SI# 7/19 port80 TX/RX change to WLAN CONN

JHDD1 CONN@ +3VS_SATA_RE
+5VS_HDD1
C 1 C
1
2
2
3
3
4
4
2
13 SATA_PTX_DRX_P0 C612 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 5
C613 1 5
13 SATA_PTX_DRX_N0 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 6 R145 @ R147 @ R150 @ R152 @
6
7 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
C614 1 7
2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 8
13 SATA_PRX_DTX_N0 C611 1 SATA_PRX_C_DTX_P0 8
2 0.01U_0402_16V7K 9
1
13 SATA_PRX_DTX_P0 9 B_PRE1 A_PRE1 A_PRE0 B_PRE0
10
10
11
GND
12
GND
2
SATA connector R146 @ R149 @ R151 @ R153 @
ACES_50463-0104A-001 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
100mils
1
+5VS +5VS_HDD1
1 2
R2685 0_0805_5%
10U_0805_10V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
1 1 1 1 Need Vendor check value

C616
C617
C618
C619
2 2 2 2 Reserve SATA Redriver
B B
SATA ODD Conn
Close to JODD
CONN@ JODD1
1 +5Valw
1 SATA_PTX_C_DRX_P2 C1143 1
2 2 0.01U_0402_25V7K SATA_PTX_DRX_P2 13
2 SATA_PTX_C_DRX_N2 C1138 1 +3VS +5Valw
3 2 0.01U_0402_25V7K SATA_PTX_DRX_N2 13
3
4
4 SATA_PRX_C_DTX_N2 C1137 1
5 2 0.01U_0402_25V7K SATA_PRX_DTX_N2 13
5
2
6 SATA_PRX_C_DTX_P2 C1136 1 2 0.01U_0402_25V7K 2
6 SATA_PRX_DTX_P2 13
7
7 R893 C1239 Vgs=-4.5V,Id=3A,Rds<97mohm
8 0_0402_5% 2 1 R79 10K_0402_5% 0.1U_0402_16V7K
8 ODD_DETECT# 17
9 +5VS_ODD
9
2
10 1
1
10
3
S
13 11 R895 R894 Q164
GND 11 0_0402_5% R81 10K_0402_5%
G
14 12 2 1 ODD_DA# 16 1 2 2
GND 12
47K_0402_5% 2
D
1
3
ACES_85201-1205N AO3413_SOT23
C1240 +5VS_ODD
2N7002DWH_SOT363-6 1 0.01U_0402_25V7K
5
QC9B
4
Place components closely ODD CONN.
2N7002DWH_SOT363-6
A 11/24 remove 22uF to sub board 17 ODD_EN# 2
QC9A
A
1

mSATA Connector
C 0.1
LA-8711
5 4 3 2 1
5 4 3 2 1
@ +CR_VDD_3V3
W=60mils W=60mils
R2714 0_1206_5%
+3VALW 1 2 JREAD1 CONN@
Q207 +LAN_VDD_3V3 1.5A SD_CMD_R 3

CMD
These caps close to U1: Pin 11,12,39,58,63,64 4 VSS
1 3 1 5
D
C4620 AO3413L_SOT23-3 @ SD_CLK_R VDD
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
6
CLK
10U_0603_6.3V6M
C4627
1U_0402_6.3V6K 1 1 1 1 1 1 1 7
G
VSS
2
2 C4621 C4622 C4623 C4624 C4625 C4626 SD_D0_R 8
+VSB SD_D1_R DAT0
9
2 2 2 2 2 2 2 SD_D2_R DAT1
1 DAT2
SD_D3_R 2 CD/DAT3
2
R2715 Note:
470K_0402_5% 1. C38: Close to Pin12(DVDD33) for avoiding voltage drop when inserting card. SD_WP 10
2. The rise time of +LAN_VDD_3V3 must >1ms and <100ms for the internal LDO. SD_CD# WP SW
11
D CD SW D
12 14
1
EN_WOL GND SW GND
4.7U_0402_6.3V6M
13 GND SW GND
15
1.5M_0402_5%
1
1
2
D
2 Q208 R2716 1 C4656 T-SOL_156-1000302601_NR
36 WOL_EN
G SSM3K7002FU_SC70-3 C4628
S 0.1U_0603_25V7K 2
3
1
2
+3VS +CR_VDD_3V3
11/20 add 4.7u @ +CR_VDD_3V3
1
R12 R13
R2717 0_0402_5% 100K_0402_5% 100K_0402_5%
+LAN_VDD_3V3 @ R2718 1 2 10K_0402_5% SD_D0 1 2 SD_D0_R
R2719 0_0402_5%
2
1
R2720 1 2 0_0402_5% U70 SD_D1 1 2 SD_D1_R
36 EC_PME#
1
Power Manahement/Isolation R2724 0_0402_5% SD_CD#_Q R14 SD_WP_Q
ISOLATEB 38 SD_D2 1 2 SD_D2_R 100K_0402_5% R15
LANWAKEB ISOLATEB R2725 0_0402_5% 100K_0402_5%
40 LANWAKEB
3
@ R2721 1 2 0_0402_5% Card Reader 19 SD_D0 SD_D3 1 2 SD_D3_R
15 PCH_PCIE_WAKE#
2
SD_D0/MS_D7/xD_D5 SD_D1 R2723 0_0402_5%
18
2
PCI-Express SD_D1/MS_CLK/xD_D6 SD_D2 SD_CMD 1 SD_CMD_R Q209A Q209B
SD_D2/xD_D7 23 2
CLK_PCIE_CD 27 22 SD_D3 R2726 0_0402_5% 2N7002KDWH_SOT363-6 2 SD_CD# 2N7002KDWH_SOT363-6 5 SD_WP
14 CLK_PCIE_CD REFCLK_P SD_D3/MS_D2/xD_D2
CLK_PCIE_CD# 28 17 SD_CLK 1 21 SD_CLK_R
14 CLK_PCIE_CD# REFCLK_N SD_D4/xD_WE#
16
4
SD_D5/xD_CE# C4629@
5,16,21,31,36 PLT_RST# 37 15
LAN_CLKREQ#_R PERSTB SD_D6/MS_INS#/xD_RE#
36 CLKREQB SD_D7/xD_RDY 14 5P_0402_50V8C
C4630 1 2 0.1U_0402_16V7K 20 SD_CLK 2
14 PCIE_PRX_DTX_P1 SD_CLK/MS_D3/xD_D4
PCIE_PRX_C_DTX_P1 30 21 SD_CMD
C4631 1 PCIE_PRX_C_DTX_N1 HSOP SD_CMD/MS_D6/xD_D3 SD_WP_Q
14 PCIE_PRX_DTX_N1 2 0.1U_0402_16V7K 31 HSON SD_WP/MS_D1/xD_WP# 35
PCIE_PTX_C_DRX_P1 25 54 SD_CD#_Q
14 PCIE_PTX_C_DRX_P1 HSIP SD_CD#/MS_D5/xD_ALE
PCIE_PTX_C_DRX_N1 26 34 Reserved for LAN PHY Disable Application
14 PCIE_PTX_C_DRX_N1 HSIN MS_BS/xD_CLE
MS_D4/xD_D0 55
Strapping @ R2728 1.5K_0402_5% EEPROM(TWSI) 56
XTLI SDA MS_D0/xD_D1 GPO @ T1617 PAD~D
+LAN_VDD_3V3 1 2 44
SDA XD_CD#
57
C T19 PAD 42 EMI-ESD C
XTLO SCL/LED_CR
2 1
1M_0402_5% R5232 GPO Pin 50 GPO LAN_ACTIVITY# C4632 1 2 470P_0402_50V8J
Transceiver Interface PN : SA00005B400 GPO
LAN_MDIP0 1 12
LAN_MDIN0 MDIP0 DVDD33 +LAN_VDD_3V3
2 MDIN0 DVDD33 39 Pull H on PCH
+3VS 1 2 ISOLATEB LAN_MDIP1 4 LINK_100_1000# C4633 1 2 470P_0402_50V8J
R2730 1K_0402_5% LAN_MDIN1 MDIP1
5 MDIN1 AVDD33 11
LAN_MDIP2 6 58
MDIP2 AVDD33
1
Y9 LAN_MDIN2 7 63
MDIN2 AVDD33 D58
2
27P_0402_50V8J
27P_0402_50V8J
1 1 LAN_MDIP3 9 64 @
OSC
OSC
C4634 C4635 R2731 LAN_MDIN3 MDIP3 AVDD33 LAN_ACTIVITY#

10 2
15K_0402_5% MDIN3 +LAN_VDD_1V0 R2727 2
41 1
DVDD10 0_0402_5% LINK_100_1000# 3 1
52
GND
GND
2 2 XTLI DVDD10 LAN_CLKREQ#2 LAN_CLKREQ#_R 3

59 14 LAN_CLKREQ# 1
1
XTLO CKXTAL1 Clock PESD5V0U2BT

60 CKXTAL2 AVDD10
3
8
2
AVDD10
AVDD10 61
Regulator and Reference +CR_VDD_3V3
25MHZ_20PF_FSX3M-25.M20FDO +LAN_SROUT1.0V 48 29 +LAN_EVDD10
REGOUT EVDD10
0.1U_0402_10V7K
C4636
ENSWREG 45 VDD33/18 for SD UHS Mode Power
ENSWREG_H
Card_3V3 13 1
+LAN_VDDREG 46 +VDD33/18
VDDREG +VDD33/18
47 33
VDDREG VDD33/18
0.1U_0402_10V7K
C4637
0.1U_0402_10V7K
C4639
R2733 53 C4638 C4640
VDD33/18 2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
R2734 1 2 62 RSET 1 1 1 1
0_0402_5% 24 JLAN1
ENSWREG 2.49K_0402_1% GND @
+LAN_VDD_3V3 2 1 GND 32
LAN_LED0 51 65 @ 12
R2735 LAN_LED1 LED0 LEDs GND9(Exposed Pad) 2 2 2 2 RJ45_TX3- SHLD4
0_0402_5% 49 8
LED1 PR4-
2 1 43 11
@ LED3 RJ45_TX3+ SHLD3
7 PR4+
3.3V : Enable Switching Regulator Close to Pin33 Close to Pin53 RJ45_RX1- 6
RTL8411-CG_QFN64_9X9 PR2-
(Default,For Power Efficiency)
0V : Enable LDO Regulator RJ45_TX2- 5 PR3-
Switching Regulator Circuit RJ45_TX2+
+LAN_VDD_1V0 4
SHI0000AA00 +LAN_VDD_1V0 R2737 PR3+
+LAN_VDD_3V3 L32 W=60mils 1 2 +LAN_EVDD10 +LAN_VDD_1V0 RJ45_RX1+ 3
B
R2736 +LAN_SROUT1.0V 1 PR2+ B
0.1U_0402_16V7K
1U_0402_6.3V6K
2
1 2 +LAN_VDDREG 2.2UH +-5% NLC252018T-2R2J-N 0_0603_5% RJ45_TX0- 2 PR1-
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
DELTA_1008HC-472EJFS-A_2P 1 2 1 1 10
0_0603_5% RJ45_TX0+ SHLD2
1 1 1 1 1 1 1 1 PR1+
C4643 C4644 C4645 C4646 9
C4641 C4642 0.1U_0402_16V7K C4647 C4648 C4649 C4650 C4651 SHLD1
4.7U_0603_6.3V6K 2 1 2 2
2 2 2 2 2 2 2 @ SINGA_2RJ1569-000111F
Close to Pin46,47 4.7U_0603_6.3V6K Close to Pin29

Place each cap. to Pin 3, 8 , 41 , 52 ,61
TS1
LAN_MDIP0 1 24 RJ45_TX0+
TD1+ TX1+
+3VS
Amber LAN_MDIN0 2
TD1- TX1-
23 RJ45_TX0-
510_0402_5% R2739 LED10 +V_DAC 3 22 R2738 1 2 75_0402_5%

LAN_LED0 2 TDCT1 TXCT1
1 LAN_ACTIVITY# 1 2 R2740 1 2 75_0402_5%
+V_DAC 4 21 R2741 1 2 75_0402_5%
HT-110UD_1204 TDCT2 TXCT2 R2742 1 75_0402_5%
2
LAN_MDIP1 5 20 RJ45_RX1+
TD2+ TX2+
C4652 1 2 LAN_MDIN1 6 19 RJ45_RX1- 2
TD2- TX2- C4653
0.01U_0402_16V7K LAN_MDIP2 7 18 RJ45_TX2+ SE167100J80
C4673 TD3+ TX3+ 10P_1808_3KV
1
White +5VS
1 2 LAN_MDIN2 8
TD3- TX3-
17 RJ45_TX2-
1 1
@
LED9 +V_DAC 9 16 C4654 C4655

TDCT3 TXCT3
3
0.1U_0402_16V7K D59 2
1
LAN_LED1 2 R2743 1 LINK_100_1000# 1 2 +V_DAC 10 15 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
3
2
510_0402_5% TDCT4 TXCT4 PESD5V0U2BT L33 2 2
A LAN_MDIP3 11 14 RJ45_TX3+ A
TD4+ TX4+
1
LTW-110DC5-C_WHITE @
3
LAN_MDIN3 12 13 RJ45_TX3-
1
TD4- TX4- 100UH_SSC0301101MCF_0.18A_20%

Add LAN LED White& Amber on M/B
2
10/12 by Karl 350UH_NA0069RLF
SP050006Y00
11/25 change p/n from SP050006X00 to SP050006Y00

LAN&CardReader Realtek RTL8411
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
5 4 3 2 1
A B C D E
USB3.0 need support 2.5A

change USB PWR SW SA00003TV00
USB3.0 +5VALW low active W=80mils
+USB_AS
W=80mils U3
1 8
1000P_0402_50V7K
0.1U_0402_16V4Z
GND VOUT
150U_B2_6.3VM_R45M
2 7
1000P_0402_50V7K
VIN VOUT
3 6 1
VIN VOUT
4 5 1 1
680P_0603_50V7K
EN FLG
1
+
1 1
680P_0603_50V7K
1
C4674 G547I2P81U_MSOP8 C90 C91 C92 C4675
0.1U_0402_16V4Z
C88 C89
2
2 2 2
2
2 2
R94
1 2 USB_OC0# USB_OC0# 16
36 USB_ON# USB_ON# 0_0402_5%

@
1 SI# 8/8 change USB_OC0# to USB30_OC# 1
+USB_AS
11/21 change to OCTEK_USB-09EAEB

+USB_AS JUSB4
11/21 change to OCTEK_USB-09EAEB USB3TXDP2_C 0.1U_0402_10V7K 2 1 C95 USB3TXDP2_C_R 9
SSTX+
1
JUSB1 USB3TXDN2_C 0.1U_0402_10V7K 2 USB3TXDN2_C_R VBUS
1 C96 8
USB3TXDP1_C 0.1U_0402_10V7K 2 SSTX-
1 C94 USB3TXDP1_C_R 9 USB20_N1_C 2
SSTX+ D-
1 7
USB3TXDN1_C 0.1U_0402_10V7K 2 USB3TXDN1_C_R VBUS USB20_N0_C USB20_P1_C GND
1 C93 8 3 10
USB20_N0_C SSTX- USB20_P0_C USB20_N1_C USB3RXDP2_C 0_0402_5% 2 D+ GND
2 1 R97 USB3RXDP2_C_R 6 11
D- USB20_P1_C SSRX+ GND
7 4 12
USB20_P0_C GND USB3RXDN2_C 0_0402_5% 2 GND GND
3 10 1R148 USB3RXDN2_C_R 5 13
D+ GND SSRX- GND
3
USB3RXDP1_C 0_0402_5% 2 1 R95 USB3RXDP1_C_R 6 11
3
SSRX+ GND D10 OCTEK_USB-09EAEB
4 12
3
USB3RXDN1_C 0_0402_5% 2 GND GND
1 R96 USB3RXDN1_C_R 5 13 D11 CONN@
3
SSRX- GND
1
OCTEK_USB-09EAEB
1
CONN@ PESD5V0U2BT
1
PESD5V0U2BT
1
R141 @ 0_0402_5%
R227 @ 0_0402_5% 16 USB3_TX2_N USB3_TX2_N 1 2 USB3TXDN2_C
USB3_TX1_N 1 2 USB3TXDN1_C D9
16 USB3_TX1_N
USB3RXDN1_C_R 1 1 109 USB3RXDN1_C_R L24 USB30@
L21 USB30@ 1 2
USB3RXDP1_C_R USB3RXDP1_C_R 1 2
1 2 2 2 98
1 2
USB3TXDN1_C_R 4 4 77 USB3TXDN1_C_R 4 3
4 3
4 3
4 3 USB3TXDP1_C_R 5 5 66 USB3TXDP1_C_R WCM-2012-900T_4P
WCM-2012-900T_4P 16 USB3_TX2_P USB3_TX2_P 1 2 USB3TXDP2_C
16 USB3_TX1_P USB3_TX1_P 1 2 USB3TXDP1_C 3 3 R142 @ 0_0402_5%
R228 @ 0_0402_5% @
R231 @ 0_0402_5% 8 USB3_RX2_N R2231 2 0_0402_5% USB3RXDN2_C
16 USB3_RX2_N
USB3_RX1_N 1 2 USB3RXDN1_C
16 USB3_RX1_N
IP4292CZ10-TB L25 USB30@
L22 USB30@ 6/27 Add ESD solution 1 2
Part Number = SC300001Y00 1 2
1 2
1 2
2 4 3 2
4 3
4 3
4 3 WCM-2012-900T_4P
WCM-2012-900T_4P D12 USB3_RX2_P 1 2 USB3RXDP2_C
16 USB3_RX2_P
USB3_RX1_P 1 2 USB3RXDP1_C USB3RXDN2_C_R 1 1 109 USB3RXDN2_C_R R224 @ 0_0402_5%
16 USB3_RX1_P
R232 @ 0_0402_5%
USB3RXDP2_C_R 2 2 98 USB3RXDP2_C_R
R233 @ 0_0402_5% R236 @ 0_0402_5%
USB20_N0 1 2 USB20_N0_C USB3TXDN2_C_R 4 4 77 USB3TXDN2_C_R USB20_N1 1 2 USB20_N1_C
16 USB20_N0 16 USB20_N1
L23 USB3TXDP2_C_R 5 5 66 USB3TXDP2_C_R L26
1 2 1 2
1 2 1 2
3 3
4 3 8 4 3
4 3 4 3
WCM-2012-900T_4P IP4292CZ10-TB WCM-2012-900T_4P
USB20_P0 1 2 USB20_P0_C 6/27 Add ESD solution USB20_P1 1 2 USB20_P1_C
16 USB20_P0 16 USB20_P1
R234 @ 0_0402_5% Part Number = SC300001Y00 R235 @ 0_0402_5%
11/21 follow AMD change to 30 pin

CONN@ JIO1 +USB_BS
USB2.0 charger 2 1
SUBWOOFER- 2 1
39 SUBWOOFER- 4 3
SUBWOOFER+ 4 3
39 SUBWOOFER+ 6 5
6 5
USB charger footprint need change to TPS2543 HDDHALT_LED#
8
8 7
7
10 9 +5VALW
13 HDDHALT_LED# SATA_LED# 10 9
12 11 +5VS
13 SATA_LED# PWR_LED# 12 11
14 13 +3VS
36,37 PWR_LED# USB20_P2 14 13
16 USB20_P2 16 15
USB20_N2 16 15
16 USB20_N2 18 17
+5VALW +USB_BS USB20_DP9 18 17
W=80mils 20
20 19
19
USB20_DN9 22 21
USB3RXDN3_C 22 21
24 23
24 23
150U_B2_6.3VM_R35M
USB3RXDP3_C 26 25
26 25
10U_0805_10V4Z
1000P_0402_50V7K
1U_0402_6.3V6K
1 16 USB3_TX3_N 28 27
28 27
0.1U_0402_16V4Z
1 1 1 16 USB3_TX3_P 30 29
30 29
C667
C2543
C669
+ 32 31
1 GND2 GND1
C2507
C927
34 33
GND4 GND3
2 2 2 2 PANAS_AXK8L30124B
2 DC011111151
U2415
1 12
3 IN OUT 3
13 9 PAD @ T68
FAULT# NC
<PCH> USB20_N9 2 11 USB20_DN9

16 USB20_N9 DM_OUTDM_IN
USB20_P9 3 10 USB20_DP9 <CONN>
16 USB20_P9 DP_OUT DP_IN
36 ILIM_SEL ILIM_SEL R2602 1 2 0_0402_5% 4 15 @ R2498 2 1

USB_CHARGE_EN# ILIM_SEL ILIM1
36 USB_CHARGE_EN 5 16 2 1 19.1K_0402_1%
EN ILIM0 R2499 19.1K_0402_1%
USB_CTL1 6
36 USB_CTL1 CTL1
USB_CTL2 7 14
36 USB_CTL2 CTL2 GND
USB_CTL3 8 17
36 USB_CTL3 CTL3 GPAD
TPS2540RTER_QFN16_3X3
+3VS +3VS
State S0 S3, S4, S5

2
+3VALW +3VALW
R4722
@10K_0402_5%
R4723
@10K_0402_5%
Mode CDP DCP
ILIM_ CTL1 CTL2 CTL3 ILIM_
1
CTL1 CTL2 CTL3

0.01U_0402_16V7K
0.1U_0402_16V4Z
USB_CTL1 USB_CTL2 SEL USB30 RX path
SEL
Control pin 2 1
1
C4669
C4668
R4724
100K_0402_5%
R4725
100K_0402_5%
1 1 X 1 0 0 1 1
1 2
U4604
2
6 16
VDD VDD
USB3RXDN3_C 1 15 USB3RXDN3_C_R 0.1U_0402_16V7K 2 1 C4666 USB3_RX3_N 16
USB3RXDP3_C INn OUTn USB3RXDP3_C_R 0.1U_0402_16V7K 2 C4667
2 14 1 USB3_RX3_P 16
INp OUTp
4 12
NC NC
EQ0 19 17 EQ1
DE EQ0 EQ1 EQ_INC
18 11
DE EQ_INC# +3VS +3VS +3VS
1 R4615 2 10 20
REXT PD#
2
2
5
4.99K_0402_1%~D I2C_EN R4617 R4618 R4640
3 7
GND NC
13 8 4.99K_0402_1%~D 4.99K_0402_1%~D 4.99K_0402_1%~D
GND NC @
21 9
GND NC
1
1
4 4
PS8711BTQFN20GTR-A0_TQFN20_3X3 EQ0 EQ1 EQ_INC DE
11/25 change R4615 to 4.99k -> Parade review
2
Place near sub board R4638
4.99K_0402_1%~D
1
USB Con & Daughter Con
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D LA-8041P 0.1
A B C D E
5 4 3 2 1
+3VALW_EC
+3VALW_EC R98 L9 +3VALW_EC
+3VALW 0_0805_5% FBMA-L11-160808-800LMT_0603
1 2 +3VALW_EC 1 2 +EC_VCCA
2
1 1 1 1 2 2 1
0.1U_0402_16V4Z
C100
0.1U_0402_16V4Z
C101
0.1U_0402_16V4Z
C102
0.1U_0402_16V4Z
C103
1000P_0402_50V7K
C104
1000P_0402_50V7K
C105
R154 R125
100K_0402_5% R99 C106 100K_0402_5% +3VS
ECAGND
0.1U_0402_16V4Z
2 2 2 2 1 1 2
0_0402_5%
Project: ID
1
1
NCL50 UMA: 261K
PROJECT_ID NCL50 DIS: 330K BOARD_ID BKOFF# R109 1 2 10K_0402_5%
@
1
1
2
Follow EC request, DB phase +3VALW_EC
D R155 50UMA@ R155 50DIS@ R137 D
use 0 ohm resistor.
261K_0402_1% 330K_0402_1% 0_0402_5% R112
10.31 100K_0402_5%
2 1
2
1
111
125
22
33
96
67
U5
9
EC_ACIN 2 1 ACIN 15,22,48
D5
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
C109 2 1 100P_0402_50V8J
+3VALW_EC R106 2 1 47K_0402_5% EC_RST#
GATEA20 1 21 0_0402_5% 2 R195 1
17 GATEA20 GATEA20/GPIO00 PWM0/GPIO0F SLP_ME_CSW_DEV# 17
C107 2 1 0.1U_0402_16V4Z EC_KBRST# 2 23 MINI1_LED#
17 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM1/GPIO10 MINI1_LED# 31
13 SERIRQ SERIRQ 3 PWM Output 26 R191 2 1 0_0402_5% KBL_OFF# KBL_OFF# 37 R118
LPC_FRAME# SERIRQ# FANPWM0/GPIO12 USB_CTL3 0_0402_5%
13,31 LPC_FRAME# 4 27 USB_CTL3 35
LPC_AD3 LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 VR_HOT#
13,31 LPC_AD3 5 55 VR_HOT# 2 1 H_PROCHOT# 5,47
LPC_AD2 LPC_AD3/LAD3
13,31 LPC_AD2 7 LPC_AD2/LAD2
C108 2 1 100P_0402_50V8J ECAGND
LPC_AD1 8 63 EC_PCIE_WAKE#
13,31 LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 EC_PCIE_WAKE# 31
3
LPC_AD0 10 64 BOARD_ID Reserve EC_PCIE_WAKE#
13,31 LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39
LPC & MISC 65 ADP_I 11.03
+3VALW_EC ADP_I/AD2/GPI3A ADP_I 47,48
CLK_PCI_LPC 12 66 PROJECT_ID
16 CLK_PCI_LPC PLT_RST# CLK_PCI_EC/PCICLK AD3/GPI3B PM_SLP_SUS# H_PROCHOT#_EC 5 2N7002DWH_SOT363-6
10/1 ENE Recommand 5,16,21,31,34 PLT_RST# 13
PCIRST#/GPIO05 AD Input AD4/GPI42
75 PM_SLP_SUS# 15 47 H_PROCHOT#_EC
R104 1 2 47K_0402_5% KSO1 EC_RST# 37 76 ADP_ID Q10B
EC_RST#/ECRST# AD5/GPI43 ADP_ID 46
17 EC_SCI# EC_SCI# 20 Pin76 PU follow EC request
4
R105 KSO2 NMI_DBG# EC_SCI#/GPIO0E
1 2 47K_0402_5% 38 0_0402_5% (Common code to DM3, DM6)
CLKRUN#/GPIO1D R200 2 PCH_VREG_EN# PAD T4
DAC_BRIG/DA0/GPO3C 68 1 11.03
R111 1 2 2.2K_0402_5% EC_SMB_DA1 70 EN_DFAN1
EN_DFAN1/DA1/GPO3D ILIM_SEL EN_DFAN1 37 11/23 change to ADP_ID
37 KSI[0..7] DA Output IREF/DA2/GPO3E
71 ILIM_SEL 35
R113 1 2 2.2K_0402_5% EC_SMB_CK1 KSI0 55 72
KSI1 KSI0/GPIO30 DA3/GPO3F
KSI2
56
57
KSI1/GPIO31 Reserve ILIM_SEL 11.03
+3VALW KSI3 KSI2/GPIO32 TP_ON_OFF_LED#
58 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 83
C KSI4 USB_ON# TP_ON_OFF_LED# 37 C
59 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 84
R110 EC_SMI# KSI5 WLAN_OFF_LED USB_ON# 35
1 2 1K_0402_5% 60 85 WLAN_OFF_LED# 37
KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C PCH_PWROK +3VALW_EC
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 PCH_PWROK 15
KSI7 62 87 TP_CLK
R1101 C222
37 KSO[0..17] KSO0
KSO1
39
40
KSI7/GPIO37
KSO0/GPIO20
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
88 TP_DATA TP_CLK 37
TP_DATA 37
R144
1 2
0_0402_5%
SPI ROM 256KB
SUSACK# KSO2 KSO1/GPIO21 U6
1 2 1 2 41
KSO3 KSO2/GPIO22 AOAC_PW_ON# 20mils
42 97 AOAC_PW_ON# 31 8 4
KSO4 KSO3/GPIO23 SDICS#/GPXIOA00 WOL_EN VCC VSS
33_0402_5% 22P_0402_50V8J 43 KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 98 WOL_EN 34
KSO5 HDA_SDO SPIPIN3
0.1U_0402_16V4Z
KSO5/GPIO25 Int. K/B
44 ME_EN/SDIMOSI/GPXIOA02 99 HDA_SDO 13 3
KSO6 EC_PME# W
R1100 C221 45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109 EC_PME# 34
C110
KSO7 46 SPI Device I/F 7
CLK_PCI_LPC 1 KSO8 KSO7/GPIO27 HOLD
2 1 2 47 KSO8/GPIO28 1
KSO9 48 119 EC_SI_SPI_SO 1 R114 2 0_0402_5% EC_SI_SPI_SO_R EC_SPICS#/FSEL#_R 1
KSO10 KSO9/GPIO29 SPIDI/MISO EC_SO_SPI_SI R115 33_0402_5% EC_SO_SPI_SI_R S
49 KSO10/GPIO2A SPIDO/MOSI
120 1 2
33_0402_5% 22P_0402_50V8J KSO11 EC_SPICLK_L EC_SPICLK_L_R EC_SPICLK_L_R
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 1 R116 2 33_0402_5% 6
C
6/27 add 33 ohm and 22p by EMI request KSO12 51 128 EC_SPICS#/FSEL# 1 R117 2 33_0402_5% EC_SPICS#/FSEL#_R 2
KSO13 KSO12/GPIO2C SPICS# EC_SO_SPI_SI_R EC_SI_SPI_SO_R
52 Delete PX_MODE bcuz PX5.0 is ready. 5 2
換換 Pin21
KSO14 KSO13/GPIO2D D Q
53
73 10.20
KSO15 KSO14/GPIO2E R134 1 0_0402_5% ENBKL MX25L2006EM1I-12G SOP 8P
換換
11/25 SLP_ME_CSW_DEV# KSO16
54 KSO15/GPIO2F GPIO40 2
EC_PECI R119 1
ENBKL 15
81
KSO16/GPIO48 H_PECI/GPIO41
74 243_0402_1% H_PECI H_PECI 5,17 SA00002C100 (S IC FL 1MB MX25L1005AMC-12G SOP
SLP_A# Pin17 KSO17 82 GPIO 89 AOAC_PME#
AOAC_PME# 16 8P 3.3V)
KSO17/GPIO49 FSTCHG/GPIO50
+3VS R120 1 2 10K_0402_5% EC_SCI# 90 2 R217 1 0_0402_5%
BAT_CHG_LED 46
BATT_CHG_LED#/GPIO52 CAP_LOCK#
91 CAP_LOCK# 37
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED#
42,47,48 EC_SMB_CK1 77 92 PWR_LED# 35,37
EC_SMB_DA1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54
42,47,48 EC_SMB_DA1 78 93 R218 2 1 0_0402_5% WLAN_ON_LED# 37
6/27 add 33 ohm and 22p by EMI request
+3VALW_EC R121 1 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 SYSON
14,22 EC_SMB_CK2 2 0_0402_5% 79 95 SYSON 43,51
R122 1 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 VR_ON
14,22 EC_SMB_DA2 2 0_0402_5% 80 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON 55
127 PM_SLP_S4# PM_SLP_S4# 15 C114 22P_0402_50V8J
AC_IN/GPIO59
1
R714 SM Bus EC_SPICLK_L_R 1 2

10K_0402_5%
PM_SLP_S3# PCH_RSMRST# C119 @ 22P_0402_50V8J
B For PCI SERR 15 PM_SLP_S3#
PM_SLP_S5#
6
14
PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03
100
101 0_0402_5% R212
PCH_RSMRST# 15
EC_SPICLK_L_R 1 2 1 2 B
15 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 17
D14 17 EC_SMI# EC_SMI# 15 102 2 1 PCH_DPWROK PCH_DPWROK 15 @ R129 33_0402_5%
2
NMI_DBG# EC_SMI#/GPIO08 EC_ON/GPXIOA05

1 2 GPIO0 GPIO0 17 43 PCH_PWR_EN
PCH_PWR_EN 1 R199 2 43_0402_1%16 103 H_PROCHOT#_EC
GPIO0A EC_SWI#/GPXIOA06 SUSACK#
15 SLP_A# 1 R196 2 0_0402_5% 17 104 SUSACK# 15
AC_LED# GPIO0B ICH_PWROK/GPXIOA07 BKOFF#
46 AC_LED# 18
GPIO0C GPIO BKOFF#/GPXIOA08
105 BKOFF# 32
15 SUSWARN# SUSWARN# 19 GPO RF_OFF#/GPXIOA09 106 CPU1.5V_S3_GATE
SUS_PWR_DN_ACK/GPIO0D CPU1.5V_S3_GATE 9
11/23 remove INVT_PWM 47 BATT_TEMP BATT_TEMP 25 107 USB_CHARGE_EN
FAN_SPEED1 INVT_PWM/PWM2/GPIO11 GPXIOA10 SA_PGOOD USB_CHARGE_EN 35
28 108 SA_PGOOD 52
change to BATT_TEMP 37 FAN_SPEED1 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11
29
E51TXD_P80DATA FANFB1/GPIO15
31 E51TXD_P80DATA 30 EC_TX/GPIO16
E51RXD_P80CLK 31 110 EC_ACIN
31 E51RXD_P80CLK EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 +3VALW_EC
38 EAPD EAPD 32 112 EC_ON
USB_CTL1 ON_OFF/GPIO18 ENBKL/GPXIOD02 ON/OFF# EC_ON 37,49
35 USB_CTL1 34 SUSP_LED#/GPIO19 EAPD/GPXIOD03 114
USB_CTL2 LID_SW# ON/OFF# 37
35 USB_CTL2 36
NUM_LED#/GPIO1A GPI EC_THERM#/GPXIOD04 115 LID_SW# 37
1
116 SUSP# R715
SUSP#/GPXIOD05 SUSP# 9,43,50,51,52,53
PBTN_OUT# 10K_0402_5%
Reserve USB_CTL 11.03 PBTN_OUT#/GPXIOD06
117 PBTN_OUT# 15
11/25 remove 32.768k crystal EC_PME#/GPXIOD07
118
R124 122
EC_XCLK0 XCLK1 +V18R
15 SUSCLK_R 1 2 123 124
2
0_0402_5% XCLK0 V18R
1
AGND
1 C113
GND
GND
GND
GND
GND
1
EC_PME#
C71 R66 4.7U_0603_6.3V6K
220P_0402_50V7K KB930QF-A1_LQFP128_14X14 2
100K_0402_5%
11
24
35
94
113
69
2
20mil
L10
2
ECAGND 2 1
FBMA-L11-160808-800LMT_0603
11/25 remove JFW1 , check with EC already

A R126 100K_0402_5% A
1 2 PLT_RST#
R127 10K_0402_5%
1 2 PCH_DPWROK
R128 10K_0402_5%
1 2 PCH_PWROK
R130 10K_0402_5%
1 2 VR_ON Security Classification Compal Secret Data Compal Electronics, Inc.
EC ENE-KB930 & 9012
Custom 0.1
LA-8041P
5 4 3 2 1
+5VS
PV# 9/13 change power rail form +3VALW->+3VALW_EC
C167 10U_0603_6.3V6M KSO17 C247 1 2 100P_0402_50V8J ACES_51503-03241-001 CONN@
+3VLP +3VALW_EC FAN1 Conn 1 2 KSO16
KSO15
C251
C226
1
1
2
2
100P_0402_50V8J
100P_0402_50V8J 32
+5VS 32
KSO14 C227 1 2 100P_0402_50V8J R372 1 2 360_0402_5% 31
36 CAP_LOCK# 31
U11 KSO13 C229 1 2 100P_0402_50V8J +3VS
2
1 8 KSO12 C228 1 2 100P_0402_50V8J 38 MUTE_LED 29
2
@ R131 EN GND KSO11 C231 100P_0402_50V8J WLAN_AMBER 29
2 7 1 2 28 34
R170 100K_0402_5% +VCC_FAN1 VIN GND KSO10 C230 100P_0402_50V8J WL_WHIT 28 GND
3 6 1 2 36 KSI[0..7] 27 33
VOUT GND KSO9 C233 100P_0402_50V8J KSI7 KSO17 27 GND
36 EN_DFAN1 2 1 4 5 1 2 26
10K_0402_5% R172 300_0402_5% VSET GND KSO8 C232 100P_0402_50V8J KSI6 KSO16 26
1 2 25
1
APL5607KI-TRG_SO8 KSO7 C235 100P_0402_50V8J KSI5 KSO15 25
1 1 2 24
1
KSO6 C234 100P_0402_50V8J KSI4 KSO10 24
2 ON/OFF# 36 1 2 23
C168 C169 KSO5 C237 100P_0402_50V8J KSI3 KSO11 23
1 2 22
ON/OFFBTN# 10U_0603_6.3V6M KSO4 C236 100P_0402_50V8J KSI2 KSO14 22
1 0.1U_0402_16V4Z 1 2 21
+3VS 2 KSO3 C240 100P_0402_50V8J KSI1 KSO13 21
1 2 1 2 20
51ON# KSO2 C238 100P_0402_50V8J KSI0 KSO12 20
2 3 51ON# 46 1 2 19
C170 KSO1 C241 100P_0402_50V8J KSO3 19
1 2 18
C269 1000P_0402_50V7K KSO0 C239 100P_0402_50V8J KSO6 18
D6 1 2 36 KSO[0..17] 17
CHN202UPT_SC70-3 KSO8 17
0.1U_0402_16V7K 1 2 16
16
1
1 KSI7 C243 1 2 100P_0402_50V8J KSO17 KSO7 15
2N7002KDW_SOT363-6
6
R173 KSI6 C242 100P_0402_50V8J KSO16 KSO4 15
1 2 14
10K_0402_5% KSI5 C245 100P_0402_50V8J KSO15 KSO2 14
1 2 13
13
Q42A
40mil KSI4 C244 1 2 100P_0402_50V8J KSO14 KSI0 12
EC_ON JFAN1 CONN@ KSI3 C248 100P_0402_50V8J KSO13 KSO1 12
36,49 EC_ON 2 1 2 11
2
+VCC_FAN1 KSI2 C246 100P_0402_50V8J KSO12 KSO5 11
1 1 2 10
2
1 KSI1 C249 100P_0402_50V8J KSO11 KSI3 10
36 FAN_SPEED1 2 1 2 9
1
R132 2 KSI0 C250 100P_0402_50V8J KSO10 KSI2 9
3 1 2 8
3 KSO9 KSO0 8
1 7
10K_0402_5% C171 KSO8 KSI5 7
4 6
1000P_0402_50V7K GND KSO7 KSI4 6
5 5
1
GND KSO6 KSO9 5
6/27 add 33 ohm and 22p by EMI request 4
4
2 ACES_50273-0030N-001 KSO5 KSI6 3
KSO4 KSI7 3
2
KSO3 KSI1 2
1
KSO2 1
KSO1 JKB1
KSO0
+3VS
1
R1
2K_0402_5%
2
2
LTST-C191KFKT-5A 0603 ORANGE
LED7
Amber
1
If=20mA
SIDE LIGHT
9/27 change K/B symbol
TP_ON_OFF_LED#
36 TP_ON_OFF_LED#
TP/B TO M/B +3VALW +3V_TP
+3V_TP R1104
2 1
TP_CLK R102 1 2 4.7K_0402_5% 0_0603_5%
TP_DATA R107 1 2 4.7K_0402_5%
1
D7 1
1
PESD5V0U2BT
@ C220
3
2 0.1U_0402_16V7K
3
6/27 Add ESD solution
JTP1 CONN@
+3VALW +5VALW
Keyboard backlight Conn 36 TP_CLK
TP_CLK
+3V_TP 1
2
1
2
TP_DATA 3
36 TP_DATA 3
PCH_SMBCLK_R 4
+5VS +5VALW PCH_SMBDATA_R 4
1 5 7
5 G1
1 6 8
6 G2
C116
1
1
ACES_51524-0060N-001
Amber White 2
C117
R80
R367 R371 2
Q9 100K_0402_5%
360_0402_5% 360_0402_5% +5VS_KBL 100P_0402_50V8J
R369
3
S
2
2
WLAN_AMBER WL_WHIT 2 2 1 100P_0402_50V8J
G 9/23 change conn to SP010012G00
2N7002KDW_SOT363-6
2N7002KDW_SOT363-6
6
3
JP14 CONN@ D 1K_0402_5% SI# 7/29 remove the TP colay circuit R214, R215
1
1
2N7002KDW_SOT363-6
1
Q48A
Q48B
0.047U_0402_16V7K
Q49B
2 AO3413L_SOT23-3 11,12,14,40 PCH_SMBCLK R190 2 1 0_0402_5% PCH_SMBCLK_R
2
36 WLAN_OFF_LED# 2 5 WLAN_ON_LED# 36 3 1 5 11,12,14,40 PCH_SMBDATA R210 2 1 0_0402_5% PCH_SMBDATA_R
3 KBL_OFF# 36
4
4
C68
5
1
4
G1
G2
6
2 11/18 for layout spacing: remove CD5/CD6/CD9
ACES_50504-0040N-001
SI# 7/25 Change WLAN LED design SI# 7/25 Add Q49B for K/B back light level shifter
+3VALW
2
R158
47K_0402_5%
H1 H2 H3 H4 H5 H6 H7 H12 H15 H14 H13 H22 H21
+3VALW +5VALW H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_4P6 H_4P6 H_4P6 H_4P6 H_3P3 H_3P3
PCB
1
JPWR1 CONN@ H19 H20

+5VALW 1 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H_2P1X2P6 H_2P1 H_3P3 H_3P3 FD4 FD3 FD1 FD2 ZZZ3
+3VALW 1
2
LID_SW# 2
36 LID_SW# 3
PWR_LED# 3 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
35,36 PWR_LED# 4
1
1
ON/OFFBTN# 4
5 7
5 G1 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
6 8
6 G2
LA-8711
ACES_51524-0060N-001
DA80000SG00
H16 H17 H18
H8 H9 H10 H11 H_4P2 H_4P2 H_4P2
H_2P8 H_2P8 H_2P8 H_2P8
HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA HOLEA
@ @ @
1
@ @ @ @
KB/TP/LED/FAN/Screw/Gsensor
1
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8041P
5 4 3 2 1
DVDD_IO should match

with HDA Bus level(optional for 3.3V signaling or 1.5V signaling) Notes:
Keep PVDD supply and speaker traces routed on the DGND plane. PLACE CLOSE TO U1 PIN 13 If Sense_A total length is greater than
Place AVDD ,PVDD,and DVDD capacitor close to Codec Keep away from AGND and other analog signals 6 inches, chagne C12 to 0.1uF
RA9 1 2 2.49K_0402_1% +AVDD_CODEC
D D
+3VS RA3 +3VS_DVDD +3VS DVDD_IO +AVDD_CODEC RA1 +VDDA_CODEC RA7 1 2 20K_0402_1% HP_JD
HP_JD 41
BLM18BD601SN1D_0603 RA57 0_0402_5% FBMA-L11-201209-221LMA30T_0805
1 2 1 2 2 1 SENSE_A CA1 1 2 1000P_0402_50V7K
+5VS
0.1U_0402_25V6
1 1 2 1 RA58 0_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
CA4
1 1 PVDD 1 2 SENSE_B RA10 1 2 10K_0402_1% +AVDD_CODEC 11/21 RA10 change to 10K(un-used)
CA3
CA6
CA7
0.1U_0402_25V6 CA2 CA5
10U_0603_6.3V UA5
2 2 1 2 CA11 2 1000P_0402_50V7K
1 If Sense_B is un-used, then pull high
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_25V6
1 27 2 2
1 1 1
DVDD_CORE AVDD1 Sense_B to AVDD by 10Kohm resistor
CA8
CA9
AVDD2 38 PLACE CLOSE TO U1 PIN 14
CA10
HDA_BITCLK_AUDIO
3 DVDD_IO PVDD1 45
1
39 2 2 2
@ RA140 PVDD2
10_0402_1% 9 13 SENSE_A
DVDD SENSE_A SENSE_B
SENSE_B 14
2
1 28 MIC_EXTL C223 1 2 1U_0402_6.3V4Z EXT_MIC

HP0_PORTA_L EXT_MIC 41
@ CA101 29 MIC_EXTR
10P_0402_50V8J HP0_PORTA_R VREFOUT_EXT_MIC
VREFOUT_A 23 VREFOUT_EXT_MIC
13 HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO 6
2 HDA_BITCLK HP_OUT_L
HP1_PORTB_L 31 HP_OUT_L 40 MUTE_LED 37
13 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 5 32 HP_OUT_R HP Jack
HDA_SDO HP1_PORTB_R HP_OUT_R 40
1
13 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 10 19 Ext MIC
HDA_SYNC PORTC_L R368
PORTC_R 20
13 HDA_SDIN0 HDA_SDIN0 2 1 SDIN_CODEC 8 24 270_0402_1%
C 33_0402_5% RA11 HDA_SDI VREFOUT_C/GPIO4 C
13 HDA_RST_AUDIO# HDA_RST_AUDIO# 11 15
3 2
HDA_RST# PORTE_L
PORTE_R 16
EAPD#
CH751H-40PT_SOD323-2 17
CH751H-40PT_SOD323-2 PORTF_L QA1B
PORTF_R 18
EAPD 1 2 2 1 DH7 47 MUTE_LED_L 5
36 EAPD EAPD
DH6 40 SPKL+
SPK_PORTD_+L SPKL+ 41
2 41 SPKL- 2N7002KDW_SOT363-6
SPKL- 41
4
DMIC_CLK/GPIO1 SPK_PORTD_-L
39 EAPD_A 4 DMIC0/GPIO2 Internal SPKR
2
44 SPKR+
48
SPK_PORTD_+R
43 SPKR-
SPKR+ 41 (front stereo speaker)
SPDIFOUT0/GPIO3 SPK_PORTD_-R SPKR- 41 10K_0402_5%
MUTE_LED_L 46
D_MIC_CLK_L_C DMIC1/GPIO0/SPDIFOUT1 RA18
32 D_MIC_CLK_L_C MONO_OUT 25 SUB_OUT 39
32 D_MIC_DATA_C D_MIC_DATA_C
1
36 12 MONO_IN
CAP+ PCBEEP
2
+3VS_DVDD +3VS_DVDD
CA12 21
2.2U_0603_16V6K VREFFILT
CAP2 22
1 35 34
CAP- V-
Place C208 close to Codec VREG(+2.5V) 37
1
2.2U_0603_16V6K
2.2U_0603_16V6K
RA14 RA17 7
10U_0603_6.3V6M
DVSS CA13 CA14 2
4.7K_0402_5% 10K_0402_5% 2 1 1
0.1U_0402_25V6
42 PVSS AVSS1 26
CA15
30
2
AVSS2
CA16
49 PAD AVSS3 33
1 1 2 2
B
92HD91B2X5NLGXYAX8_QFN48_7X7 B
HDA_RST_AUDIO# EAPD#
Place C209,C210,CA87,CA89 close to Codec

+AVDD_CODEC
1 1
CA17 CA18 9/27 LDO TPS793475DBVR for audio power
1
0.01U_0402_16V7K 0.1U_0402_25V6
2 2 RA55 +VDDA_CODEC
10K_0402_5%
+5VS UA2
RA56 W=40Mil 5
2
CA97 CA98 VOUT

1 VIN
1 2 1 2 1 2 MONO_IN
BYPASS 4
0.1U_0402_25V6 100K_0402_5% 0.1U_0402_25V6 1 2 3
0.1U_0402_25V6
RA16 EN
1
CA20
2 2
680P_0603_50V7K
10K_0402_5% GND
1
C4678
0.1U_0402_25V6
1
D TPS793475DBVR_SOT23-5 CA19
1 1
1
HDA_SPKR 2
CA38
CA93@1 2 0.1U_0402_25V6 13 HDA_SPKR 2 UA1 RA54 C4679 10U_0805_10V6K
2
G 2N7002H_SOT23-3 CA100 1
CA92@1 2 0.1U_0402_25V6 10K_0402_5% 680P_0603_50V7K
SB Beep S 0.1U_0402_25V6
3
2
2 2
2
RA53 1 2 0_0805_5%
A A
GND GNDA

Audio IDT 92HD91
Custom 0.1
5 4 3 2 1
5 4 3 2 1
+5Valw +5V_SUBAMP
D D
RA12
BLM18BD601SN1D_0603
1 2
UA3
CA29 1 2 2 1 A1 C3 LA1 1 2 FBM-11-160808-601-T_0603

IN+ OUT+ SUBWOOFER+ 35
0.033U_0603_16V7 RA139 47K_0402_5%
RA15
1 2 SUB_OUT_LPF CA27 1 2 2 1 C1
38 SUB_OUT 0.033U_0603_16V7 RA138 47K_0402_5% IN- LA2
OUT- A3 1 2 FBM-11-160808-601-T_0603 SUBWOOFER- 35
4.7K_0402_1%
1 B2 PVDD
CA21 B3
PGND
11/23 add LPF for HP request 2
1000P_0402_50V7K B1 VDD
1
C2 EN GND A2 CA30 CA31
38 EAPD_A
680P_0603_50V7K 680P_0603_50V7K
2
C C
TPA2011D1YFFR_DSBGA9
0.1U_0402_16V4Z
1U_0402_6.3V4Z
2 1
CA87
CA79
1 2
11/23 add 1u/0.1uF for HP request
2011.10.28 Change Sub-woofer Amp to TPA2011D1
B B
A A

Audio Woofer Amplifier
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
5 4 3 2 1
5 4 3 2 1
D D
Headphone Amp
+HP_5V
+HP_5V +5VS
10K_0402_1%
LA22 1 2
RA47 FBM-11-160808-601-T_0603
UA4
CA67 1U_0402_6.3V4Z RA61 0_0402_5%
1 RA19 2 HP_OUT_R_LPF 2 1 1 2 5 12 11/21 change RA40/RA44 from 16-> 30ohm(FAE)
38 HP_OUT_R INR- VDD_12
4.7K_0402_1% 4
INR+ RA40 1
11 2 30_0402_1% HP_R 41
CA68 1U_0402_6.3V4Z RA62 0_0402_5% HPRIGHT RA44 1
14 2 30_0402_1% HP_L 41
HPLEFT
38 HP_OUT_L 1 RA20 2 HP_OUT_L_LPF 2 1 1 2 1
4.7K_0402_1% INL-
2
1000P_0402_50V7K
1000P_0402_50V7K
INL+
1 1 3
GND_3
CA22
CA23
11/23 add LPF for HP request GND_9

9
10
GND_10
6 13
2 2 SD# GND_13
7 19
SDA GND_19
8 21
SCL GND_21
PCH_SMBDATA
11,12,14,37 PCH_SMBDATA
PCH_SMBCLK
11,12,14,37 PCH_SMBCLK
15
CPVSS_15
20 16
1U_0402_6.3V4Z
VDD_20 CPVSS_16
C 1 1 18 17 C
CPP CPN CA83
CA69 CA77 0.1U_0402_16V4Z TI HPA00929
1U_0402_6.3V4Z
2.2U_0402_6.3V6M
1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 1 1 1 2
2 2
CA84 CA78 CA81
1 2 0.1U_0402_16V4Z
1 2 2 2 CA85 1
CA82 1U_0402_6.3V4Z
B B
A A

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio SPK/HP Amplifier
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
5 4 3 2 1
A B C D E
11/25 change SPKR connector follw AMD

Front Class D internal Speaker Connector JSPKR1
1 1
2 2
SPKR+
38 SPKR+
SPKR- +3VALW
38 SPKR-
SPKL+ 3
38 SPKL+ GND1
1 SPKL- 4 1
38 SPKL- GND2
2
ACES_50281-0020N-001
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
CONN@ R4726
1 1 1 1 10K_0402_5%
HP_JD HP_JD 38
CA44
CA45
CA46
CA47
1
JSPKL1
2 2 2 2 1 1
1
D
2 2
2
HP_JD_Q 2 Q1
1 G 2N7002E-T1-E3_SOT23-3
1
@ DA1 DA2 @ S SB570020110
3
3.3_0402_5%
3.3_0402_5%
3.3_0402_5%
3.3_0402_5%
RA37
RA41
RA42
RA43
3 GND1
PJDLC05_SOT23-3 PJDLC05_SOT23-3 4 GND2
ACES_50281-0020N-001
2
2
CONN@
1
11/23 spacing concern: remove DA4/DA5, keep D60 only
1
D60
2 PJDLC05C_SOT23-3 2
EXT_MIC Width = 15mils
Need place rear Audio Codec (UA5) HP_L Width = 15mils
HP_R Width = 15mils
2
JA1
EXT_MIC# 6
1
HPL 2
RA36
HPR 3
VREFOUT_EXT_MIC HP_JD_Q 1 2 HP_JD_1 4
0_0402_5% G 7
R11 5 G 8
4.7K_0402_5%
LA8
SUYIN_010188HR006G269ZL
38 EXT_MIC 2 1 EXT_MIC#
CONN@
BK1608HS601-T_2P
1
AGND
3
CA86
1 Audio Combo Jack 3
1U_0402_6.3V4Z CA60
2 220P_0402_50V7K
2
11/21 add CA86 (FAE)
Need place near JAUD1
AGND
BLM15AG121SN1D_L0402_2P
1 2 HPR
40 HP_R
LA7
1 2 HPL
40 HP_L
LA6 BLM15AG121SN1D_L0402_2P
1 1
3
CA61 CA62 D61

220P_0402_50V7K 220P_0402_50V7K AZ5125-02S.R7G_SOT23-3
2 2
4 4

1
For Combo Jack Need place near JAUD1 Issued Date 2011/11/02 Deciphered Date 2011/11/02 Title
Audio SPK Conn/Jack/MIC
Custom 0.1
LA-8711
A B C D E
5 4 3 2 1
ACCELEROMETER
+3Valw
D D
U25
1 9 +3Valw
Vdd_IO INT2
11 ACCEL_INT# 16
EC_SMB_CK1 INT1
36,47,48 EC_SMB_CK1 4 14
EC_SMB_DA1 SCL/SPC VDD
36,47,48 EC_SMB_DA1 6
SDA/SDI/SDO
7 5
SDO/SA0 GND
+3Valw 2 1 8 12
R166 10K_0402_5% CS GND
RES 10
RES 13 1 1
1
2 15 C218
R167 NC RES C219
3 NC RES 16
0_0402_5% 0.1U_0402_16V7K 10U_0603_6.3V6M
2 2
HP3DC2
2
1
R168
0_0402_5%
2
Must be placed in the center of the system.
C C
Finger printer +3VS
1
C929
0.1U_0402_16V4Z
2
JFP1 CONN@
0_0402_5% 1
R1334 USB20_N3_R 1
16 USB20_N3 2 1 2
2
B R1335 USB20_P3_R B
16 USB20_P3 2 1 3 3
0_0402_5% 4 4
5 5 G1
7
2
6 6 G2
8
D62
2
SCA00001L00 ACES_51524-0060N-001
1
PESD5V0U2BT
1
A A

TCG/BIOS ROM/PS2/LED/SW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8711 0.1
5 4 3 2 1
A B C D E
C267 @ SI# 8/16 Reserve C267 100pF by ESD request

SYSON 1 2
100P_0402_50V8J
+5VALW +5VALW
2
+3VALW TO +3VALW(PCH AUX Power) R174 R175
+5VALW TO +5VS Short J1 for PCH VCCSUS3.3 100K_0402_5% 100K_0402_5%
+5VALW
7/12 SI Change to PAK type
1
1 SI7326DN-T1-E3_PAK1212-8 +5VS +3VALW +3V_PCH SYSON# SUSP 1
U12
1
D
1
1
D
10U_0603_6.3V6M
2 SYSON 2 U13
36,51 SYSON
2
10U_0603_6.3V6M
10U_0603_6.3V6M
5 3 1 1 40mil G 2N7002H_SOT23-3 2 U14

9,36,50,51,52,53 SUSP#
1
C172
1U_0603_25V6
C173
1 1 R176 U15 S G 2N7002H_SOT23-3
1
C174
C175
470_0603_5% SI4800BDY-T1-GE3_SO8 R177 S
3
8 1 100K_0402_5% R178
4
2 2 10K_0402_5%
7 2
2
2 2 6 3 1 1
2
10U_0603_6.3V6M
C177
1U_0603_25V6
C178
1 5
2
6
C176 R179
470_0603_5%
4
10U_0603_6.3V6M 2 2
20mil 10mil
1
5VS_GATE SUSP 2
+VSB 2 1 2
R180
20K_0402_5% 1 Q14A
1
3
6
C179 DMN66D0LDW-7_SOT363-6 20mil 10mil
0.1U_0603_25V7K
+VSB R181 2 1 200K_0402_5% 3V_GATE
SUSP 2 PCH_PWR_EN#
5 2
1
Q14B Q43A
4
1
3
DMN66D0LDW-7_SOT363-6 C180 DMN66D0LDW-7_SOT363-6
0.1U_0603_25V7K
2
PCH_PWR_EN# 5
Q43B
4
DMN66D0LDW-7_SOT363-6 +0.75VS
+1.8VS +1.05VS +1.5V
1
2 2
2
R182
22_0603_5% R183 R184 @ R185
6/24 U16 and U17 to Q16 change to Dule mos package 470_0603_5% 470_0603_5% 470_0603_5%
3 1
6 1
6 1
6
@
2 SUSP 5 SUSP 2 SUSP 2 SYSON#
Q15A Q15B Q17A Q18A
1
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
+3VALW TO +3VS
+3VALW +3VS
SI7326DN-T1-E3_PAK1212-8
U18 1.5VPCIEV
1 11/24 keep 10u + 0.1u *1 only +1.5V TO +1.5VS +1.5VS
2
2
10U_0603_6.3V6M
C181
10U_0603_6.3V6M
C182
1 1 5 3 1 1
10U_0603_6.3V6M
C183
1U_0603_25V6
C184
0.1U_0402_16V7K
R186
10U_0603_6.3V6M
C185
C189
470_0603_5%
1 1 3 1
4
2 2 2 2
1
3 3
1 1
1U_0603_25V6
C187
10U_0603_6.3V6M
C190
QV17 PX@
R188 2 2 AP2301GN-HF_SOT23-3
10mil
2
20mil 47K_0402_5%
6
3VS_GATE 2 2 R187
+VSB 2 1 20mil
470_0603_5%
1
3
C191 2 SUSP +5VALW
1
0.1U_0603_25V7K 20mil 10mil
Q20A +3VALW 2 1 1.5VS_GATE
1
2
SUSP 2 DMN66D0LDW-7_SOT363-6 R77
5
20K_0402_5% 1 R189
Q20B C53 100K_0402_5%
4
3
DMN66D0LDW-7_SOT363-6 0.1U_0603_25V7K 2 SUSP
1
2 Q19A PCH_PWR_EN#
19 PCH_PWR_EN#
1
SUSP# 5 DMN66D0LDW-7_SOT363-6
Q19B
4
3
36 PCH_PWR_EN 5 Q17B
6/24 Q20 and Q21 to Q20 change to Dule mos package
1
4
R192
100K_0402_5%
2
4 4
6/24 Q19 and Q22 to Q19 change to Dule mos package

DC Interface
Custom 0.1
LA-8041P
A B C D E
A B C D E
QC11 (LA-8551P Ver:0.1)

Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply (19V) N/A N/A N/A
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1 +CPU_CORE Core voltage for CPU ON OFF OFF 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS_VCCP +V1.05SP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+VCCP +VCCP (1.05V ) power for PCH ON OFF OFF
+1.5V +1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V) ON ON OFF
+1.5VS +1.5VS switched power rail ON OFF OFF
+1.8VS (+5VALW ) to 1.8V switched power rail to PCH ON OFF OFF

+3VALW +3VALW always on power rail ON ON ON*
+3VALW_EC +3VALW always to KBC ON ON ON*
+LAN_IO +3VALW to +LAN_IO power rail for LAN ON ON ON*
+3V_PCH +3VALW to +3V_PCH power rail for PCH (Short Jumper) ON ON ON*
EC SM Bus1 address
+3VS +3VALW to +3VS power rail ON OFF OFF
+5VALW +5VALWP to +5VALW power rail ON ON ON* Device Address EC SM Bus2 address
+5V_PCH +5VALW to +5V_PCH power rail for PCH (Short resister) ON ON ON* Smart Battery 0001 011X b
Device Address
+5VS +5VALW to +5VS switched power rail ON OFF OFF G-sensor 0101001b
PCH (Reserve) 1010 0110b
2 +VSB B+ to +VSB always on power rail for sequence control ON ON ON* 2
PCH SM Bus address
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Device Address
DDR DIMM0 1010 0000b
DDR DIMM1
CLKOUT DESTINATION
Mini Card1
Mini Card2
PCI0 PCH_LPBACK
TP module
SMBUS Control Table
PCI1 PCI_LPC
WLAN mSATA EC_SMB_CK2 PCH_SMBCLK
BATT TP SODIMM G-Sensor GPU AMP
SOURCE MIINI1 MINI2 PCH_SMBDATA PCH_SMBDATA PCI2 None
EC_SMB_CK1 KB930 V V PCI3 None

EC_SMB_DA1
EC_SMB_CK2 KB930 V V PCI4 None

EC_SMB_DA2
USB Port Table
PCH_SMBCLK 1 External
PCH_SMBDATA PCH
@ V V V USB 2.0 USB 1.1 Port USB Port
3
SATA DESTINATION 0 3
PCH_SMLCLK PCH UHCI0
PCH_SMLDATA V V SATA0 m-SATA,JMINI2
1 USB/B (Right Side)
2
UHCI1
3
SATA1 m-SATA,JMINI1 EHCI1
4
UHCI2
5 m-SATA
SATA2 None 6
UHCI3
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION 7
SATA3 None 8 Camera
UHCI4
CLKOUT_PCIE0 None CLKOUTFLEX0 None 9 Mini Card(WLAN)
SATA4 None 10
EHCI2 UHCI5
CLKOUT_PCIE1 10/100/1G LAN CLKOUTFLEX1 None 11
SATA5 None 12
UHCI6
CLKOUT_PCIE2 None CLKOUTFLEX2 None 13
CLKOUT_PCIE3 WLAN CLKOUTFLEX3 None 1 External

CLK USB 3.0 Port USB Port
CLKOUT_PCIE4 CARD READER Option @ CONN@ USB3.0@ 0
Symbol Note : UMA X X V 1
4
CLKOUT_PCIE5 USB3.0 FL1009-2Q0 : means Digital Ground 4
CLKOUT_PCIE6 None
: means Analog Ground
CLKOUT_PCIE7 None
2011/11/02 2011/11/02 Title
CLKOUT_PEG_B None Issued Date Deciphered Date
Notes List
C 0.1
A B C D E
5 4 3 2 1
BATTERY BATT+ PU21 PU27 +CPU_CORE

12.6V CHARGER ISL6277HRTZ-T +CPU_CORE
BQ24725RGRR
+CPU_CORE_NB +CPU_CORE_NB
PU26 +1.5V +1.5V

D AC ADAPTOR VIN RT8207MZQW D
+0.75VS PU15
19V 90W
APL5508
RAM DDRIII SODIMMX2
PU17 +1.5V VDD_MEM 4A
RT8209MGQW VTT_MEM 0.5A
B+ +0.75VS
+0.75VS
+0.75VS
VGA ATI
+VGA_CORE Whistler/Seymour/Granville
PU10
+VGA_CORE 0.85~1.1V VDDC 47A
TPS51218DSCR
+VDDCI
0.9~1.0V VDDCI 4.6A
+VDDCI
+1.0VSG DPLL_VDDC: 125 mA
PU14 SPV10: 120 mA
G9731G11U +1.0VSG PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
+1.5VSG VRAM 512/1GB/2GB
U41
+1.5VSG VDDR1: 3400 mA 64M / 128Mx16 * 4 / 8
AO4430L
PU5 +1.1VALW
RT8209MGQW PLL_PVDD: 75 mA +1.5VSG 2.4 A
TSVDD: 20 mA
AVDD: 70 mA
C VDD1DI: 100 mA C
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
PU2 +3VALW
U40 PU7 VDD_CT: 110 mA
RT8205EGQW +1.8VSG +1.8VSG VDDR4: 170 mA
+5VALW SI4800 SY8033BDBC +1.8VSG PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
+3VS
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
+INVPWR_B+
+3VS
JUMP +3VSG A2VDD: 130 mA
U38 +3VSG +3VSG VDDR3: 60 mA
SI4800
LCD panel +5VS

15.6"
B+ 300mA U39
+3.3 350mA AO4430L
+5VS
FAN Control
B
APL5607 B
+5VS 500mA
Q63
SI2301
U54 +5VALW VDDIO_33_PCIGP: 131 mA
TPA2301DRG4 VDDPL_33_SYS: 47 mA
+USB_VCCA
VDDPL_33_DAC: 20 mA
+3VS VDDPL_33_ML: 20 mA
+3VS +3VS VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
USB X3 VDDPL_33_SATA: 93 mA
+1.5VS
VDDIO_AZ_S: 26 mA
+5V
Dual+1
2.5A +3VALW VDDPL_33_SSUSB_S: 20 mA
+3VALW VDDPL_33_USB_S: 17 mA
+3VALW VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
SATA Audio Codec EC LAN VDDAN_33_HWM_S: 12 mA
HDD*1 ALC271X ENE KB930 BCM57785 Mini Card*2
ODD*1
VDDIO_33_GBE_S
+5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 201mA +1.5VS 500mA VDDCR_11_GBE_S
+3.3VS 3mA +3.3VS 1A GND VDDIO_GBE_S
+3.3V +3.3VS 25mA +3.3VALW 330mA
RTC
A RTC BAT VDDBT_RTC_G A
Bettary

POWER DELIVERY CHART
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8711 0.1
5 4 3 2 1
5 4 3 2 1
D D
ADPIN PL1 VIN

HCB2012KF-121T50_0805
1 2
7 8
7 8
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
5 5 6 6 1 2
1
PL2
1
ADP_SIGNAL 3 4 HCB2012KF-121T50_0805 PR1 @
PC9
PC10
3 4
PC7
PC8
1K_0402_5%
Charge_LED 1 2 ACIN_LED
2
1 2
2
@ PJP1
ACES_59012-0080N-002
3 PR26
10K_0402_5%
PD1 ADP_SIGNAL 1 2
L30ESD24VC3-2 3P C/A SOT23 ESD ADP_ID 36
@100P_0402_50V8J
1
1
10K_0402_5%
RLZ3.6B_LL34
PR25
PD7
PC11
2
2
2
1
C PD2 C
L30ESD24VC3-2 3P C/A SOT23 ESD
+3VALW
3
+3VLP +3VALW
VIN 2
36 AC_LED#
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
PD3 @ 37.1
LL4148_LL34-2 TP0610K-T1-GE3 1P SOT23-3
PR2
PR3
PR4
PR5
PQ1
1
B B
2
@ @
1
5
PR7 @ PR8 @ PR6
68_1206_5% 68_1206_5% VS 2K_0402_5% 1 AC_LED#
P
PQ2 ACIN_LED 1 B
2 4
PD4 TP0610K-T1-GE3 1P SOT23-3 O
2
2
G
LL4148_LL34-2 BAT_CHG_LED 36
2 1 3 1 PU1
3
BATT+ 74LVC1G02GW_SOT353-5
0.22U_0603_25V7K
100K_0402_5%
1
PC18@
PR9
PC17
0.1U_0603_25V7K
2
PR10
2
22K_0402_1%
5
37 51ON# 1 2
2 AC_LED#
P
Charge_LED A
4
Y BAT_CHG_LED
B 1
G
PU2
3
74LVC1G86GW_SOT353-5
A A

PWR- DCIN / Vin Detector
Custom 0.1
LA8711P
5 4 3 2 1
5 4 3 2 1
D
For KB930 --> Keep PU1 circuit For KB9012 --> Remove PU1 circuit, but keep PR25 D
BATT++ BATT+ (Vth = 0.825V) PH1, PR15, PQ3, PR17,PR18, PR16

VCIN0_PH-->NTC_V
PL3
SMB3025500YA_2P VCIN1_PH-->Turbo_V
BATT++ 2 1 BATT+
1
PC19 PC20
@ PJPB1 1000P_0402_50V7K 0.01U_0402_25V7K
BATT BTJ-08FP0B 8P
2
PR27
1 6.49K +-1% 0402
1
2 2 1 2 +3VLP
3
3
4
4 PR11 PH1 under CPU botten side :
5 1K +-1% 0402
5
6
6 1 2 BATT_TEMP 36
CPU thermal protection at 90 +-3 degree C
7
7
8
8 Recovery at 56 +-3 degree C
9 PR13
GND 100_0402_5%
GND 10
1 2 EC_SMB_DA1 36,42,48 Rset = 3 * Rtmh
PR12
100_0402_5%
1 2
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
EC_SMB_CK1 36,42,48
Rtmh at 90C = 7.8K, Rtml at 56C = 26.1K
C PD5 Rset = 3 * 7.8K = 23.4K ==> 23.7K C
PJPB1 battery connector 3 Rhyst = (23.4K * 26.1K) / (3 * 26.1K - 23.4K) = 11.12K ==> 11.3K
1
2
PD6 +3VLP
1
3
1 PR14
1
2
PC21 23.7K_0402_1%
.1U_0402_16V7K
2
2
PR15
1
PU3 11.3K_0402_1%
1 8
1
VCC TMSNS1 PH1
2 7 100K_0402_1%_NCP15WF104F03RC
GND RHYST1
2
MAINPWON 3 6
49 MAINPWON OT1 TMSNS2
+3VS 4 5 2 1 2 1
OT2 RHYST2 ADP_I 36,48
G718TM1U_SOT23-8 PR16 PR17
5.9K_0402_1%
2
26.1K_0402_1%
1
PR18 PR19
B 100K_0402_1% 10K_0402_1% B
PQ3
TP0610K-T1-GE3 1P SOT23-3
1
5,36 H_PROCHOT#
2
B+ 3 1 +VSB
1
D
0.22U_1206_25V7K
100K_0402_1%
2 1 2 H_PROCHOT#_EC 36
1
@ G
PR20 @
1
1
PR21
S SSM3K7002FU_SC70-3 0_0402_5%
Active point = 71.52W
PC22
3
+5VALW PC23 @ PQ4
0.1U_0603_25V7K
2
Recovery point = 62.62W

2
2
2
PR23
PR22 22K_0402_1%
100K_0402_1% 1 2
PR24
1
0_0402_5% D
1 2 2 PQ5
15,49 SPOK
G SSM3K7002FU_SC70-3
S
3
1
PC24 @
.1U_0402_16V7K
2
A A

PWR- BATTERY CONN
Custom 0.1
LA8711P
5 4 3 2 1
A B C D
for reverse input protection
1
PQ104 D
2
G
2N7002KW _SOT323-3
S
3
1 1
1 2 1 2
PR101 PR102
1M_0402_5% 3M_0402_5%
B+
VIN P1 PQ102
P2
PR103 PL101
PQ101 AON7702L_DFN8-5 PQ103
0.02_1206_1%
AO4474L_SO8 1.2UH +-30% 1231AS-H-1R2N=P3 2.9A AON7702L_DFN8-5
8 1 1 1 4 1 2 1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
7 2 2 2
10U_0805_25V6K
6 3 3 5 2 3 @ 5 3
0.1U_0402_25V6
1
@
PC104
VIN
PC107
5
PC105
0.01U_0402_50V7K
@
1
1
0_0402_5%
PC106
@
1
PC102
PC103
PC108
0_0402_5%
4
4
1
PR104
PC101
PC110
2
PR105
2 PC109
0.1U_0402_25V6
2
1 2 @
2
3
2
PD101
0.1U_0603_25V7K
0.1U_0402_25V6
BAS40CW_SOT323-3 BQ24725_BATDRV 1 2
1
PC111
PC112
PR106
4.12K_0603_1%
PC113 0.047U_0402_25V7K
1
4.12K_0603_1%
4.12K_0603_1%
2
1
1 2
PR108
PR107
5
10_1206_1%
1
PQ105
PR109
2
AON7408L_DFN8-5
2
2
PR110 2
BQ24725_ACP
BQ24725_ACN
0_0603_5% PR111
1
DH_CHG 1 2 4
BQ24725_BST
PD102 BATT+
BQ24725_LX
0_0402_5%
1
1 2 RB751V-40_SOD323-2
DH_CHG
2011/03/18 PC114 PC115 PL102 PR112
3
2
1
10UH_FDSD0630-H-100M-P3_3.8A_20% 0.01_1206_1%
delete VIN voltage 1U_0603_25V6K 1 2
BQ24725_LX 1 2 CHG 1 4
1U_0603_25V6K
detecting circuit
4.7_1206_5%
5
1
20
19
18
17
16
2 3
PR113
PU101 PQ106
1 CSOP1
1 CSON1
2200P_0402_50V7K
VCC
PHASE
HIDRV
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_50V7K
0.1U_0402_25V6
21
AON7408L_DFN8-5
0.1U_0402_25V6
PAD @
PC118
PC119
2
1
PC121
PC116
PC117
DL_CHG
PC122
1 ACN LODRV 15 4
680P_0402_50V7K
PC120
2
2 ACP GND 14
PR114
3
2
1
2
BQ24738ARGRR QFN 20P CHARGER 10_0603_5% @
BQ24725_CMSRC 3 13 SRP 1 2 CSOP1
CMSRC SRP
1
BQ24725_ACDRV 4 12 SRN 1 2 CSON1
2
PR116 ACDRV SRN
PR115
10K_0402_1% 6.8_0603_5% PC123
BQ24725_BATDRV 0.1U_0603_25V7K
1 2 5 11
+3VALW ACOK ACDET BATDRV
IOUT
SDA
SCL
ILIM
3 +3VALW 3
6
10
15,22,36 ACIN 1 2
PR117
0_0402_5% 1 2
PR118
0_0402_5%
0.01U_0402_25V7K
VIN
100K_0402_1%
280K_0402_1%
1
For KB930 --> Keep PR116
1
PR119
PR120
PC124
0_0402_5%
255K_0402_1%
2
1 2
2
154K_0402_1%
2
1
PR122
PR123
1
PR121
2
100_0402_1%
0.1U_0402_25V6
66.5K_0402_1%
PR124
EC_SMB_CK1 36,42,47
1
1
PC125
PR125
2
EC_SMB_DA1 36,42,47
2
2 1 ADP_I 36,47
Vin Dectector PC126
.1U_0402_16V7K
4
Min. Typ Max. 4
H-->L 17.33V
L-->H 16.98V
ILIM and external DPM Security Classification Compal Secret Data Compal Electronics, Inc.
4.36A Issued Date 2011/10/03 Deciphered Date 2014/12/31 Title
PWR- CHARGER
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P 0.1
A B C D
A B C D E
2VREF_8205
1U_0603_16V6K
1
PC302
2
1 1
VL
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
PR303 PR304
20K_0402_1% 20K_0402_1% B++
1 2 1 2
B+ B++ For RF request
For RF request
+3VLP
ENTRIP2
ENTRIP1
PL301
2200P_0402_50V7K
68P_0402_50V8J
FB_3V
FB_5V
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
HCB2012KF-121T50_0805 PR305 PR306
1 2 113K_0402_1% 57.6K_0402_1%
1
PC303
PC304
PC322
1 2 1 2
2200P_0402_50V7K
10U_0805_25V6K
68P_0402_50V8J
PC305
PC306
0.1U_0402_25V6
10U_0805_6.3V6M
2
1
1
PC301
PC307
PC321
PU301
5
PC308
PC309
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
5
PQ302
2
PQ301 25 AON7408L_DFN8-5
2
AON7408L_DFN8-5 P PAD
15,47 SPOK
7 VO2 24 4
VO1
4
2 PC311 2
8 23
PC310 VREG3 PGOOD 0.22U_0603_16V7K
PR307 PR308
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V1 2
3
2
1
BOOT2 BOOT1
0_0402_5%UG_3V 0_0402_5%
1
2
PL302 3 0.22U_0603_16V7K 10 UGATE2 UGATE1 21 UG_5V PL352
4.7UH_TMPC0502H-4R7M-Z01-D_2.8A_20% 1UH_VMPI0703AR-1R0M-Z01_11A_20%
+3VALWP 1 2 LX_3V 11 PHASE2 PHASE1

20 LX_5V 2 1
+5VALWP
1
5
4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
5
4.7_1206_5%
PQ304
PR309
SKIPSEL
PQ303 PD302 PR311 TPCA8057-H_PPAK56-8-5
150U_UD_6.3VM_R15M
PR310
VREG5
1
RLZ5.1B_LL34 499K_0402_1% 1
GND
B+
VIN
+ PC312 @ RT8205LZQW(2) WQFN 24P PWM
NC
EN
1 2 1 2
1 SNUB_3V
2
PC313
150U_B2_6.3VM_R35M 4 @
1SNUB_5V 2
4 PR312 @
Ipeak=5A
13
14
15
16
17
18
2
680P_0603_50V7K
0_0402_5%
MAINPWON 2
1 2
680P_0603_50V7K
Imax=3.5A
PC314
3
2
1
1U_0603_10V6K
MDV2658BURH_POWERDFN33-8-5
200K_0402_1%
1
2
3
PC316
F=500K
2
PC315
@
B++ VL
PR313
0.1U_0603_25V7K
Rtrip=57.6K, OCP=18A
2
@
PC318
Total Capacitor 1050uF,
1
PC317
4.7U_0805_10V6K
2
Ipeak=10A
ENTRIP1
ENTRIP2
2VREF_8205 Imax=7.5A
3
F=400K 3
6
PJP303
2 1
PQ305A PQ305B 2 1 Rtrip=57.6K, OCP=18A
SSM6N7002FU-2N_SOT363-6 2 N_3_5V_001 5 SSM6N7002FU-2N_SOT363-6 @ JUMP_43X118
PJP304
Total Capacitor 1050uF,
1
+5VALWP 2 2 1
1
+5VALW ( UMA 10A,400mils ,Via NO.= 20 )
@ JUMP_43X118
1 2
VL
PR315 PR314
0_0402_5% 100K_0402_5%
1 2
36,37 EC_ON
PJP301
PR316
0_0402_5%
+3VALWP 2 2 1 1
+3VALW ( 5A,200mils ,Via NO.= 10 )
@ JUMP_43X118
MAINPWON 1 2
47 MAINPWON
1
PD301 PR317
LL4148_LL34-2 1M_0402_1% PQ306
2 1 1 2 2 LTC015EUBFS8TL NPN UMT3F
VIN
4.7U_0603_6.3V6K
402K_0402_1%
1
PC319
4 4
PR318
PR319
316K_0402_1%
2
2 1
VS
2

PWR- 3VALWP/5VALWP
Custom LA8711P 0.1
For KB930 --> Keep PD301, PR317, PR319 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
5 4 3 2 1
D D
PJP401
PCHVCCIO_B+ 2 1
2 1 B+
JUMP_43X118
10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0603_25V7K
1
1
+3VS
PC401
PC402
PC403
PC404
5
2200P_0402_50V7K
2
1
PR401
10K_0402_1%
4
2
C C
VTTPWRGOOD 52
PQ401
TPCA8065-H_PPAK56-8-5
PR410 PC405 PL401 +1.05VS
3
2
1
PU401 0_0603_5% 0.1U_0603_25V7K 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
PR402 PCHVCCIO_PGD 1 10 PCHVCCIO_BST 1 2 PCHVCCIO_BST-1 1 2 1 2
69.8K_0402_1% PGOOD VBST
PR411
1
PR403 2 1 PCHVCCIO_CS 2 9 PCHVCCIO_DH 2 1
220U_B2_2.5VM_R15M
TRIP DRVH
5
20K_0402_1% 0_0603_5% 1
1 2 3 8 PCHVCCIO_LX
0.1U_0402_16V7K
9,36,43,51,52,53 SUSP# EN SW +
PR404
PC406
PCHVCCIO_FB PCHVCCIO_VDDP 4.7_1206_5%
4 7
+5VALW +1.05VS
1PCHVCCIO_SNB2
VFB V5IN
1
1
PC407
PC408
2
1U_0402_16V6K 5 TST DRVL 6 PCHVCCIO_DL 4 Peak Current
2
2
1
FB=0.704V TP 11 HR=17.5A
1
PQ402
PR405 TPS51212DSCR_SON10_3X3 PC409 TPCA8059-H_SOP-ADVANCE8-5 CR=9A
3
2
1
10K_0402_1% 1U_0603_10V6K
2
2
PC410
680P_0402_50V7K OCP current
2
PR406
HR= TBD A
4.64K_0402_1% CR= TBD A
2 1 2 1 VCCIO_SENSE 8
PR407
100_0402_1%
1
B B
2 1 VSS_SENSE_VCCIO 8
PR408 PR409
10K_0402_1% 0_0402_5%
Close to PU501.7
2
A A

PWR-1.05VS
Custom 0.1
LA8711P
5 4 3 2 1
5 4 3 2 1
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
PL501
HCB1608KF-121T30_0603 OCP Current 0.9A
D B+ 1 2 1.5V_B+ D
PR501
BST_1.5V 1 2 BOOT_1.5V +1.5V
2.2_0402_5%
680P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
PR502
DH_1.5V_1 1 2 DH_1.5V +0.75VSP
1
1
PC501
0_0402_5%
0.22U_0402_10V6K
PC502
PC503
PC504
PC505
2
SW _1.5V
PC506
10U_0805_6.3V6K
10U_0805_6.3V6K
10U_0805_6.3V6K
2
2
@
1
@
PC507
PC508
PC509
1
5
DL_1.5V
16
17
18
19
20
PU501
2
@
VLDOIN
PHASE
UGATE
BOOT
VTT
PAD 21
4 15 LGATE VTTGND 1
PQ501 PR503 14 2
PL502 SIS412DN-T1-GE3_POW ERPAK8-5 9.53K_0402_1% PGND VTTSNS
1
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC510 CS RT8207MZQW _W QFN20_3X3 GND
5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
PR505 VDDP VTTREF
330U_D2_2.5VY_R15M
5.1_0603_5%
C Ipeak=7.5A +
1
1 2 VDD_1.5V 11 VDD VDDQ 5 +1.5VP C
PGOOD
@ PR504
PC511
4
Imax=5.25A
1
4.7_1206_5%
TON
+5VALW
SNUB_+1.5VP
PQ502 PC512
FB
S5
S3
2
1
2
F=300K FDMC7692S_MLP8-5 0.033U_0402_16V7K
2
PC513
1
2
3
10
6
1U_0603_10V6K
+5VALW
2
PR506
1
10K_0402_1%
@ PC514 FB_1.5V 2 1 +1.5VP
TON_1.5V
680P_0402_50V7K
PC515
2
@
1 2
Mode Level +0.75VSP VTTREF_1.5V .1U_0402_16V7K

PR507
S5 L off off 887K_0402_1%
S3 L off on PR508 1.5V_B+ 1 2
0_0402_5%
S0 H on on
1
1 2 EN_1.5V PC516
36,43 SYSON .1U_0402_16V7K
Note: S3 - sleep ; S5 - power off
2
10K_0402_1%
41.2K_0402_5%
EN_0.75VSP
2
PR509
PR510
1 @ PC517
0.1U_0402_10V7K
B B
2
1
+3VS
10K_0402_1%
@
2
PR512
0_0402_5%
PR511
PJP501
2 1
1 2 9,36,43,50,52,53 SUSP# PR513
D
1
5.1K_0402_1%
1
PAD-OPEN 4x4m 2 1 2 DDR3L_EN 17
G
2
PJP502
.1U_0402_16V7K
S
1
@ PC518 PR514
PC519
+1.5VP 1 2 +1.5V (9A,360mils ,Via NO.= 18)
0.1U_0402_10V7K PQ503 10K_0402_5%
2
PAD-OPEN 4x4m
2
SSM3K7002FU_SC70-3
1
PJP503 High
+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)
PAD-OPEN 3x3m
A A

Issued Date 2012/07/29 Title
2011/07/29 Deciphered Date
PWR-1.5VP / +0.75VSP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8712P 0.01
5 4 3 2 1
5 4 3 2 1
2
@ PC601
D 680P_0402_50V7K D
1
The 1k PD on the VCCSA VIDs are empty.
SNUB_+VCCSA
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
2
4.7_0402_1%
PR601
@
4x4
1
PL601 PU601 PL602
HCB1608KF-121T30_0603 SY8037ADCC DFN 12P PWM 1UH_PCMB042T-1R0MS_4.5A_20%
+5VALW 1 2 +VCCSA_PWR_SRC 12 PVIN LX 1
+VCCSA_PHASE 1 2
+VCCSAP
11 PVIN LX 2
PC602
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
68P_0402_50V8J 10 3 PR602 SA_PGOOD 36
SVIN LX
2
100K_0402_5%
PC603
PC604
PC605
PC606
2200P_0402_50V7K
0.1U_0603_25V7K
+VCCSAP_FB
2 1 9 4 2 1
2
+3VS
22U_0805_10VA
22U_0805_10VA
FB PG
1
PC607
PC608
1
+VCCSA_EN
PC609
PC610
8 VOUT EN 5 1 2
GND
2
2
1 PR603
7 VID1 VID0 6
0_0402_5%
@
0.1U_0402_10V7K
13
PR606
1
100_0402_5%
PC611
2
2
50 VTTPWRGOOD 2 1
1K_0402_5%
1K_0402_5%
PR604
PR605
2
PR607
C C
0_0402_5%
1
2 1 VCCSA_SENSE 9
VCCSA_VID0 9
VCCSA_VID1 9
PJP601
+VCCSAP 1 1 2 2
+VCCSA
JUMP_43X118
+VCCSAP
TDC 3A
Peak Current 4A
PR609
510K_0402_1%
9,36,43,50,51,53 SUSP# 1 2
1
0.47U_0402_6.3V6K
1
1M_0402_5%
PR610
PC617
2
PU602
2
@ @ SY8809DFC_DFN8_2X2
B 1 8 1.8V_FB B
EN FB
1.8V_VIN PL603
+5VALW 1 1 2 2 2 IN PG 7
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
PJP602 1.8V_LX 1.8V_LX
3 LX LX 6 1 2
+1.8VSP
1
JUMP_43X79
PC613
22U_0805_6.3V6M
4 GND GND 5
1
4.7_0402_1%
2
1
PR608
47U 6.3V M X5R 0805 H1.25
47U 6.3V M X5R 0805 H1.25

PC614
PC615
2
2
1 2
PJP603
+1.8VSP 1 1 2 2
+1.8VS
PC616
680P_0402_50V7K
JUMP_43X79
2
1.8VSP
1
PR611
2 TDC 2 A
28.7K_0402_1% Peak Current 3 A
1
PR612 2 1
14.3K_0402_1%
PC618
2
@ 22P_0402_50V8J
A A

PWR-VCCPP/1.8VSP
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA8711P
5 4 3
Compal Electronics, Inc.
2
Date: Sunday, November 27, 2011
1
Sheet 52 of 57
A B C D
1
1.5VPCIEP 1
TDC 2.8A
2
PC927
680P_0402_50V7K Peak Current 4A
OCP current 6A
1 SNUB_+1.5VPCIE
4.7_0402_1%
2
PR917
5x5
PL901 PL904
1
4
HCB1608KF-121T30_0603 1UH_PCMB053T-1R0MS_7A_20%
+5VALW 1 2 10 2 LX_1.5VPCIE 1 2
1.5VPCIEVP
PG
PVIN LX
9 PVIN LX 3
2
150K_0402_1%
22P_0402_50V8J
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
8 SVIN
1
PR916
PR902
22U_0805_6.3VAM
1
PC928
0_0402_5% 6
FB
1
PC924
PC930
PC925
PC929
1 2 EN_1.5VPCIE 5
9,36,43,50,51,52 SUSP#
2
EN
PC902
PU901 DIS@
SS
TP
LX
2
SY8036LDBC DFN 10P PW M
2
1
PC926 DIS@ @ PC923
11
1
22U_0805_6.3VAM 0.1U_0402_10V7K
2
DIS@ DIS@
100K_0402_1%
2
PR918
2 2
1
PU901 UMA@
SY8033BDBC_DFN10_3X3
PJP902
1.5VPCIEVP 1 2 1.5VPCIEV
@ PAD-OPEN 4x4m
PR910
100K_0402_5%
1 2 EN_0.935V
16,23,54,56 PXS_PW REN
@ 0.1U_0402_10V7K
2
PC913
1M_0402_5%
1
PR911
PU902
2
SY8809DFC_DFN8_2X2
1
1 EN FB_0.935V
PJP903
@ FB 8
1 2 2 7 PL902
+5VALW 1 2 IN PG 1UH +-20% SIG4018-1R0 3A
@ JUMP_43X79 LX_0.935V 3 6 LX_0.935V 1 2 0.935VP
LX LX
22P_0402_50V8J
22U_0805_6.3V6M
1
3 3
PC908
11.3K_0402_1%
4 GND GND 5
1
2
4.7_0402_1%
47U 6.3V M X5R 0805 H1.25
47U 6.3V M X5R 0805 H1.25

1
PC909
PR909
PR908
2
1
PC910
PC911
2
2
2
@
1
PC914
680P_0402_50V7K
20K_0402_1%
2
PR912
2
PJP904
0.935VP 1 2 0.935V
@ PAD-OPEN 4x4m
4 4

+1.5VPCIE/0.935V
0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA8711P
A B C D
A B C D
1 1
PR801
VGA@ 100K_0402_5%
1 2 EN_VDDCI
16,23,53,56 PXS_PW REN
0.1U_0402_10V7K
2
+VDDCI
1
VGA@ PR805
VGA@ PC805
1M_0402_5%
TDC 2.8A
2
Peak Current 4A
1
OCP current 6A
PU801
SY8809DFC_DFN8_2X2
PJP801 1 EN FB 8
1 2 2 7 VGA@ PL801
+5VALW 1 2 IN PG 1UH +-20% SIG4018-1R0 3A
@ JUMP_43X79 LX_VDDCI LX_VDDCI
22U_0805_6.3V6M
3 LX LX 6 1 2 +VDDCIP
@22P_0402_50V8J
1
VGA@ PC801
4 GND GND 5
2
PC802
4.7_0402_1%
47U 6.3V M X5R 0805 H1.25
47U 6.3V M X5R 0805 H1.25

1
PR802
2
1
2
VGA@ PR803 2
VGA@ PC803
VGA@ PC804
10_0402_5%
2
2
2
FB_VDDCI 1 2
VGA@ PR804
1
PC806
4.99K_0402_1%
680P_0402_50V7K
VGA@ PR806
2
0_0402_5%
2 1 VDDCI_SEN 25
+3VS
1
VGA@
1
PR807
29.4K_0402_1% PR809 VGA@
1
10K_0402_5%
2
PR808 PR810 VGA@
2
1
3 3
VGA@ 10K_0402_1% D 10K_0402_5%

2 2 1
2
G VDDCI_VID 22
S
1
PQ801 VGA@
1
2N7002W -T/R7_SOT323-3
@ PC808 PR811 @
4700P_0402_25V7K 100K_0402_5%
2
VDDCI_VID
High 1V
Low 0.9V @ PJP802

+VDDCIP 1 2 +VDDCI
PAD-OPEN 4x4m
4 4

+VDDCIP
0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA8711P
A B C D
5 4 3 2 1
2200P_0402_50V7K
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5
1
1
1K_0402_1%
PC202
PC203
@ PC204
@ PC206
PQ201
@ PR201
PC205 PR203 2 1 +VGFX_CORE
39P_0402_50V7K 2.49K_0402_1% PC207 TPCA8065-H_PPAK56-8-5
2
2 1 2 1 @ 330P_0402_50V7K PR202
1 2 10_0402_1% UGATEG 4
VCC_AXG_SENSE 9
2
PR205
330P_0402_50V7K
422_0402_1%
2 1 2 1 2 1 2 1 2 1 VSS_AXG_SENSE 9
PL201
+VGFX_CORE
3
2
1
2
1
@ PC201
PC208 PR204 PC209 PC210 0.36UH_FDU1040J-H-R36M=P3_33A_20%
196K_0402_1%
150P_0402_50V8J 475K_0402_1% 330P_0402_50V7K 0.01U_0402_25V7K 2 1 PHASEG 1 4
PR206
PC212
1
4.7_1206_5%
D PR207 0.22U_0603_10V7K 2 3 D
PR209
10_0402_1% BOOTG 2 1 2 1
2
1
2 1
PR208 PR210 PR211
PC211 2.2_0603_5% 3.65K_0402_1% 1_0402_5%
2
UGATEG
PHASEG
1000P_0402_50V7K
LGATEG
BOOTG
LGATEG
NTCG
2 1 4
ISNG
ISPG
2
PR213 PH201
1
PR212 7.5K_0402_1% 10K_0402_1%_ERTJ0EG103FA
8.06K_0402_1% +1.05VS +3VS +5VS PQ202 PC213 1 2 1 2
680P_0402_50V7K PC214
41
40
39
38
37
36
35
34
33
32
31
3
2
1
2
TPCA8059-H_PPAK56-8-5 .1U_0402_16V7K
2
1 2 1 2
PAD
COMPG
FBG
RTNG
ISUMPG
ISUMNG
NTCG
BOOTG
UGATEG
PHASEG
LGATEG
1
@ PR214 PR216
1.91K_0402_1% PR217 11K_0402_1%
2
@ PC216 0_0603_5% 1 2
2
.1U_0402_16V7K PR215 30 BOOT2
1
BOOT2
2
PR218 130_0402_1% 1 PC215
2
54.9_0402_1% VWG UGATE2 .1U_0402_16V7K
29
UGATE2
2 1 2
1
1
PGOODG PHASE2
28
1
PHASE2
1
+3VS GFX_CORE_PWRGD 3 PC217
ISPG
8 VR_SVID_DAT SDA
2
1.91K_0402_1%
27 LGATE2 PC218 0.047U_0402_16V X7R PR220

@ PR219 SVID_ALERT# LGATE2 1U_0603_10V6K 953_0402_1%
4
2
8 VR_SVID_ALRT# ALERT#
2
499_0402_1% 26
VCCP
PR221
SVID_SCLK 5
2
8 VR_SVID_CLK SCLK PU201 ISNG
25 +5VS 2 1
1
PR222 ISL95835HRTZ-T_TQFN40_5X5 PWM3

36 VR_ON 1 2 6
VR_ON LGATE1 @ PR223
24 Connect to +5V can disable
1
0_0402_5% LGATE1 0_0402_5%

15 VGATE 7
PGOOD
23 PHASE1 GFX portion
PHASE1
36 VR_HOT# 8
VR_HOT# UGATE1
UGATE1 22
1
47P_0402_50V8J
NTC 9 NTC
PC219
21 BOOT1
ISEN3/ FB2
C BOOT1 C
10
2
VW CPU_B+
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VDD
RTN
1
VIN
470KB_0402_5%_ERTJ0EV474J
FB
2
27.4K_0402_1%
PR225
1
PR224
2.2_0603_5%
11
12
13
14
15
16
17
18
19
20
PH202
2
ISEN2
ISEN1
1
NTCG
1comp
FB
2
10P_0402_50V8J
+5VS
1
1000P_0402_50V7K
3.83K_0402_1%
470KB_0402_5%_ERTJ0EV474J
PC221
PC220 PL202
ISEN3
1
1
27.4K_0402_1%
0.22U_0603_25V7K HCB2012KF-121T50_0805
2
2
2
PR226
PR227
1 2
2
1
PH203
PR229
1
PC222
PR228 1_0603_5% CPU_B+ PL203

B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
8.06K_0402_1% HCB2012KF-121T50_0805
2
0.1U_0402_25V6
68U_25V_M_R0.44
68U_25V_M_R0.44
1 1 2 1
1
1
PQ203
2
0.22U_0402_6.3V6K 2
0.22U_0402_10V6K 2
1
+ +
PC226
PC227
@ PC228
@ PC230
PC250
PC231
comp
1
680P_0402_50V7K
PC223
PC224
PC225 TPCA8065-H_PPAK56-8-5
2
1
3.83K_0402_1%
20.5K_0402_1%
1U_0603_10V6K
2
2
2 2
47P_0402_50V8J
PR230
PC229
UGATE2 4
2
1
PR231
1 2
267K_0402_1%
PR232
1
2
PC232
PL204
1
3
2
1
0.36UH_FDUM0640J-H-R36M-P3_22A_20%
PHASE2 1 2
PR233 +CPU_CORE
2
1
2-ph: PR172=20.5K Vboot=0V, Iccmax=54A
4.7_1206_5%
2.2_0603_5%
PC234
PR234
PR236 BOOT2 2 1 2 1
2-ph: PR172=169K Vboot=1.1V, Iccmax=54A
VSUM-
PR235 1000P_0402_50V7K 887_0402_1% VSUM+

330P_0402_50V7K
B 2K_0402_1% PC233 B
1 2 1 2 1 2 1 2 0.22U_0603_10V7K
2
1
LGATE2 4
FB
1.47K_0402_1%
0.033U_0402_16V X7R
PC236
PC235 PR238 PR240

1
11K_0402_1%
0.22U_0402_10V6K
470P_0402_50V7K 1 2 2.61K_0402_1% 3.65K_0402_1%
1
1
PC239
VSUM+ 1 2
1
1
PR239
PC238
PR241
PR237 @ PC237 PR242
2
3
2
1
3K_0402_1% PQ204 680P_0402_50V7K 10K_0402_1%
2
ISEN2 1 2
2
2
1
1
100_0402_1%
TPCA8059-H_PPAK56-8-5 PR243 PR244

2
2
PR245
PH204 1_0402_5% 10K_0402_1%

10K_0402_1%_ERTJ0EG103FA VSUM- 1 2 2 1 ISEN1
@ CPU_B+
2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
VSUM-
5
1
PC240 PQ205
1
PC241
PC242
PC243
@ PC244
@ PC245
.1U_0402_16V7K
2
0.01U_0402_25V7K
2
330P_0402_50V7K
UGATE1 4
PC246
PC247
@
2-ph: PR178=1.47K for ~70A OCP PL205
2
3
2
1
2
2
10_0402_1%
0.36UH_FDUM0640J-H-R36M-P3_22A_20%
PR246
PR247 PHASE1 1 2
10_0402_1% PR248 +CPU_CORE
4.7_1206_5%
2.2_0603_5%
PR249
BOOT1 2 1 2 1
1
1
8
8
VSSSENSE
PC248 PR250
VCCSENSE
+CPU_CORE 0.22U_0603_10V7K 3.65K_0402_1%
2
LGATE1 4 VSUM+ 1 2
1
A A
10K_0402_1%
PQ206 PC249 ISEN1 1 PR251 2
3 680P_0402_50V7K PR253
2
1
2
1_0402_5% 10K_0402_1%
TPCA8059-H_PPAK56-8-5 VSUM- 1 PR252 2 2 1ISEN2
+CPU_CORE +GFX_CORE
Iocp=72A, IccMAX=53A Iocp=40A, IccMAX=24A Security Classification Compal Secret Data Compal Electronics, Inc.
Load line=1.9mohm Load line=3.9mohm 2010/01/25 2009/04/28
CPU_CORE/VGFX_CORE
Issued Date Title
Deciphered Date
DCR=1.1mohm DCR=1.1mohm
Custom
QAZ20 0.3

5 4 3 2 1
A B C D E F G H
1 1
1K_0402_1% PR701 1 2 GPU_VID1 2 1@ PR702 1K_0402_1%
22
22
22
22
GPU_VID1
GPU_VID2
GPU_VID3
GPU_VID4
1K_0402_1% PR703 @ 1 GPU_VID2 1 PR704 1K_0402_1%
PXS_PWREN
16,23,53,54
2 2
+3VS
1K_0402_1% PR705 @ 1 2 GPU_VID3 2 1 PR706 1K_0402_1%
1K_0402_1% PR707 1 2 GPU_VID4 2 1@ PR708 1K_0402_1%
+3VS
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
+5VS
+VGA_B+ PL701
PR709
0.1U_0402_16V7K
2
FBMA-L11-453215800LMA90T_2P
0_0402_5%
80.6K_0402_1%
2
PC702
PR710
PR711
PR712
PR713
PR714
PR715
PR716
PR717
2 1 B+
@ PR718
1
@ 10_0603_1%
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
68P_0402_50V8J
100P_0402_25V8K
220P_0402_25V8K
1
@ PC707
@ PC708
@ PC709
1
1
PC703
PC704
PC705
PC706
32 VGA_EN
+3VS
2
1
5
VGA_VCC
PC710
TPCA8065-H_SOP-ADV8-5
1U_0603_10V6K
31
30
29
28
27
26
25
2
PR719 PU701
PQ701
1K_0402_1%
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
24 PR720 PC711 4
2
VCC 0_0603_5% 0.22U_0603_25V7K
17 VGA_PWRGD 1
PWRGD
PC701 23 VGA_BOOST 1 2VGA_BOOST-11 2
BST
1
2 1000P_0402_50V7K @ PR721 2 2
66.5K_0402_1% IMON VGA_DRVH PR722 PL702
22 2 1
3
2
1
PR723 DRVH 0.36UH_PCMC104T-R36MN1R105_30A_20%
1 2 3 0_0603_5%
2
0_0402_5% CLKEN VGA_SW

21 1 2
25 VSS_GPU_SENSE 2 1 4
SW +VGA_CORE
FBRTN PR724
5
ADP3211MNR2G_QFN32_5X5 20 2 1
4.7_1206_5%
PVCC +5VS
1
1 2 VGA_FB 5 0_0603_5%
FB VGA_DRVL
@ PR725
19 2 1 1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
PC712 PC714
1
VGA_COMP 6 DRVL
PR726 1500P_0402_50V7K 10P_0402_25V8K COMP PC713 + + +
PC715
PC716
PC717
18
0_0402_5% VGA_VCC 7 PGND 2.2U_0603_10V6K 4 4
2
2
GPU
25 VCC_GPU_SENSE 2 1 1 2 1 2VGA_COMP-1
1 2 17
VGA_ILIM 8 AGND PQ702 2 2 2
CSCOMP
680P_0603_50V8J
ILIM
1
PR727 PC719 PR728 33 TPCA8057-H_PPAK56-8-5
CSREF
AGND
RAMP
LLINE
CSFB
1K_0402_1% 1000P_0402_50V8J 39.2K_0402_1%
@ PC720
IREF
RPM
3
2
1
3
2
1
RT
2
PQ703
9
10
11
12
13
14
15
16
2
PR729
9.53K_0402_1%
VGA_IREF
VGA_RAMP
VGA_CSFB
VGA_CSCOMP
VGA_RT
VGA_RPM
VGA_CSCOMP 1
2
PR730
PR731
PR732
237K_0402_1%
301K_0402_1%
PR733 422K_0402_1%
80.6K_0402_1%
Ipeak=59A
1
Imax=45.7A
1
F=300kHZ
1
1
1
PR734 Total capacitor
2
Connect to input caps PC721 PC722 220K_0402_1% 1460u

2
2
1000P_0402_50V7K 560P_0402_50V7K
2
3 3
PR736 2 1 ESR=1.8m ohm
1K_0402_1%
+VGA_B+ 2 1 VGA_RAMP-1 PR735
80.6K_0603_1%
1
PC723 PC724
1000P_0402_50V7K 1000P_0402_50V7K
2
1 2
1
PR737 PR931 PR932 LL

0_0402_5%
0_0402_5%
@ PR738
@ 0 X
2
VGA_CSCOMP 0 @ V
4 4

+VGA_COREP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P 0.3
A B C D E F G H
5 4 3 2 1
D D
+CPU_CORE
+CPU_CORE +VGFX_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.
5 x 22 µF (0805)
1
1
PC1001 PC1002 PC1003 PC1004 PC1005
Socket Bottom 5 x (0805) no-stuff
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M sites
2
2
+VGFX_CORE
7 x 22 µF (0805)
Socket Top 2 x (0805) no-stuff
sites
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1
PC1011
PC1012
PC1013
PC1014
PC1015
PC1016
PC1017
PC1018
PC1006 PC1007 PC1008 PC1009 PC1010
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2
2
C C
2 2 2 2 2 2 2 2
+CPU_CORE
1 1 1 1 1
PC1019 PC1020 PC1021 PC1022 PC1023
+1.05VS
2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 +1.05VS
PC1024
PC1025
PC1026
PC1027
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
PC1028
PC1029
PC1030
PC1031
PC1032
PC1033
PC1034
PC1035
PC1036
PC1037
PC1038
2 2 2 2
2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1
PC1039 PC1040 PC1041 PC1042 PC1043
2 2 2 2 2
22U_0805_6.3V6M
PC1045
1 1 1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
PC1044
PC1046
PC1049
PC1050
+ + + +
2
2 2 2 2
1 1 1 1 1 1
PC1052 PC1053 PC1054 PC1055 PC1056 PC1057
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
B 2 2 2 2 2 2 B
+CPU_CORE
1 1 1 1
+ PC1058 + PC1059 + PC1060 + PC1061
330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y
2 2 2 2
A A

PWR - PROCESSOR DECOUPLING
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA8711P 0.1
5 4 3 2 1

Compal La-8711p r0.1 Schematics

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Compal La-8711p r0.1 Schematics

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A B C D E

PAGANI M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR3L 1333MHz 1.35V DDR3-SO-DIMM X 2

FDI x8 DMI x4 HDD LED & PWR LED

FAN conn. LVDS(1Ch) USB 3.0 x3

PCI-Express x 2 (PCIE2.0 5GT/s) 100MHz X1

RTL8411 page34 port 10 JMINI1 page33 page33 JMINI2 page33

CRT page30 SM bus PS2 SPI

LED page37 EC ROM,

ODD connector board Daughter board

Security Classification Compal Secret Data Compal Electronics, Inc.

+1.8VS (+5VALW ) to 1.8V switched power rail to PCH ON OFF OFF

WLAN BATT EC_SMB_CK2 PCH_SML1CLK

CLKOUT_PCIE3 None CLKOUTFLEX3 None 3 External

PCI EXPRESS* - GRAPHICS

15 FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 CU43 2 1 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_N5

PEG_TX#[14] PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

PEG_TX[6] PEG_HTX_GRX_P8 CU56 PX@ 0.1U_0402_10V6K PEG_HTX_C_GRX_P8

Security Classification Compal Secret Data Compal Electronics, Inc.

Requires a series resistor of 43±5% between processor and PCH.

JTAG & BPM

15 H_PM_SYNC PM_SYNC TRST#

RC16 AR28 XDP_TDI SI# 8/16 Reserve RC81~RC85 by ESD request

2011.10.18 delete all reserved XDP conponent.

H_CPUPWRGD_R C118 1 2 220P_0402_50V7K

2 RC25 SM_RCOMP2 RC26 2 1 200_0402_1% C263 0.1U_0402_16V7K

1 2 1 PU/PD for JTAG signals C265 @ 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

11 DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 11

DDR SYSTEM MEMORY B

4.99K_0402_1% DRAMRST_CNTRL_PCH hgih ,MOS ON

A RC39 Dimm not reset A

CFG Straps for Processor

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG AND DDR

RC15 VAXG17 SB_DIMM_VREFDQ

DDR3 -1.5V RAILS

D BSS138W-7-F_SOT323-3 AM24 AF7

RC82 VAXG28 VDDQ4

A6 C22 1 RC79 2 VCCSA_VID0

1 1 1 1 A2 VCCPLL3 VCCSA_VID[1] C24 1 2 VCCSA_VID1 VCCSA_VID1 52

RC80 0_0402_5% 75_0402_5%

0_0402_5% RUN_ON_CPU1.5VS3# 2N7002DWH_SOT363-6 VID[0] VID[1] 2011 2012

RC73 CC118 0 1 0.80 V Yes Yes

@ RC75 330K_0402_5% 2 0.1U_0402_25V6 Q10A 1 0 0.725 V No Yes

0_0402_5% 2N7002DWH_SOT363-6 1 1 0.675 V No Yes

AT35 VSS1 VSS81 AJ22

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_A_D25 DQ24 DQ29

DDR_CS1_DIMMA# 121 122

1 DDR_A_D57 183 184

1 1 1 1 1 1 1 1 1 1 185 186 DDR_A_DQS#7

201 202 PCH_SMBCLK

SGA00004400 1 1 203 204 +0.75VS

DDR_B_D25 DQ24 DQ29

DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB DDR_CKE1_DIMMB 6

DDR_B_MA13 119 120 M_ODT3 M_ODT3 6

1 DDR_B_D57 183 184

1 1 1 1 1 1 1 1 1 1 185 186 DDR_B_DQS#7

201 202 PCH_SMBCLK

SGA00004400 1 1 203 204 +0.75VS