Received: 21 February 2020 Revised: 22 June 2020 Accepted: 10 August 2020

DOI: 10.1002/mmce.22419

RESEARCH ARTICLE

PVT-compensated low-voltage and low-power CMOS LNA

for IoT applications

Sajad Nejadhasan | Fatemeh Zaheri | Ebrahim Abiri |

Mohammad Reza Salehi

Department of Electronics, Shiraz

University of Technology, Shiraz, Iran
Correspondence
Sajad Nejadhasan, Department of
Electronics, Shiraz University of
Technology, P.O. Box 16315-1618, Shiraz,
Iran.
Email: s.nejadhasan@sutech.ac.ir
Abstract
In this paper, a low-noise amplifier (LNA) with process, voltage, and tempera-
ture (PVT) compensation for low power dissipation applications is designed.
When supply voltage and LNA bias are close to the subthreshold, voltage has
significant impact on power reduction. At this voltage level, the gain is reduced
and various circuit parameters become highly sensitive to PVT variations. In
the proposed LNA circuit, in order to enhance efficiency at low supply voltage,
the cascade technique with gm boosting is used. To improve circuit perfor-
mance when in the subthreshold area, the forward body bias technique is
used. Also, a new PVT compensator is suggested to reduce sensitivity of differ-
ent circuit's parameters to PVT changes. The suggested PVT compensator
employs a current reference circuit with constant output regarding tempera-
ture and voltage variations. This circuit produces a constant current by sub-
tracting two proportional to absolute temperature currents. At a supply voltage
of 0.35 V, the total power consumption is 585 μW. In different process corners,
in the proposed LNA with PVT compensator, gain and noise figure
(NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a
conventional LNA with constant bias. With a 20% deviation in the supply volt-
age, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

KEYWORDS
internet of things (IoTs), low-noise amplifier (LNA), low power, PVT compensation, sub-
threshold amplifier

1 | INTRODUCTION advances in manufacturing technology, and reduction of

In portable and wireless sensor networks, such as in med-
ical applications and the internet of thing (IoT), low-
power receiver-transmitter design is highly significant.
Since LNA is one of the most power consuming receiver
blocks, its design with low power features plays a sub-
stantial role in total power consumption reduction,
which may particularly result in a decrease in power con-
sumed by the whole system. Reduction of transistor
dimensions at the nanometer level, made possible by
supply voltage must be taken into consideration as two
critical factors in decreasing power consumption. On the
other hand, mentioned factors lead to unwanted varia-
tion in LNA parameters in relation to process, voltage,
and temperature (PVT) variations.
To this day, many methodologies have been used in
LNA design. One is high-electron-mobility transistor
(HEMT) with gallium nitride is used in its structure. At
high frequencies, his technology has a large effect in
reducing the noise figure (NF) and increasing the

Int J RF Microw Comput Aided Eng. 2020;e22419. wileyonlinelibrary.com/journal/mmce © 2020 Wiley Periodicals LLC 1 of 16
https://doi.org/10.1002/mmce.22419
2 of 16
linearity of the circuit. HEMT usually works with high
breakdown voltage and is utilized for bandwidth applica-
tions.1,2 LNAs designed with this technology generally
have a high power consumption and are therefore not
suitable to low power applications such as IoT and medi-
cal applications. Another technology used in field effect
transistor (FET) semiconductors is the carbon nanotube
FET (CNFET) technology. Considering the scaling trends
in semiconductor technologies, this technology may
prove to be a potent replacement for the metal oxide
semiconductor field effect transistor (MOSFET).3 Much
research has been done on digital circuits with CNFETs
so far, but considerably less so on radio frequency (RF)
and analog CNFET-based circuits. In Reference 4, an
LNA inductor-less bandwidth circuit with CNFET tech-
nology has been theoretically designed. This circuit has a
higher frequency range, an improved NF and linearity,
but also a higher power consumption as well, compared
to already existing CMOS structures.
Typically, to design a low-power LNA, transistors
must be in the subthreshold area. Under these condi-
tions, the main branch current is strongly affected by
PVT variations. Therefore, since most LNA parameters
are dependent on the mentioned current, these parame-
ters become highly sensitive to PVT changes.5 In this
case, PVT compensators are an appropriate solution.
These circuits consist of a constant or variable current
source that generates the proper bias voltage to control
these changes by factoring the LNA main branch current
changes in.
One way to design a constant current reference circuit
is using band gap reference circuits made with bipolar
junction transistors (BJT). Using BJT transistors, how-
ever, generally increases power consumption.6-9
Moreover, in some other current reference circuits,
only MOSFET transistors are used to generate current or
voltage insensitive to PVT variations. In such circuits, to
achieve reduction in power consumption, transistors are
usually biased in the subthreshold region which is the
main reason for increase of the temperature coefficient
(TC).10,11 In order to produce a constant current in
MOSFET transistors in relation to temperature varia-
tions, various parameters including threshold voltage and
mobility should be taken into consideration, whereas
these parameters vary in different regions of transistors.
In order to produce constant current, proportional to
absolute temperature (PTAT) and complementary to
absolute temperature (CTAT) techniques, and a combina-
tion of them, can be used.12-14 These signals have positive
and negative linear relationships with temperature and
voltage changes, respectively, and so a constant current
can be achieved by merging these signals. However,
using this technique in the presence of process variation
NEJADHASAN ET AL.
can cause a complications. Additionally this technique
drives the circuit to a high sensitive level at low voltages
when voltage variation exists.
In some designs, to compensate for the PVT varia-
tions affecting different LNA parameters, a variable cur-
rent source is used.15 In this technique, the LNA current
variations are compared with a preset variable current
source, then an appropriate error voltage is generated to
control the LNA bias voltage and compensate the PVT
variations.
In this article, a new compensation circuit is proposed
which reduces PVT variations in LNA circuits working at
low voltages. The way it works is by generating an error
signal based on the current variations of the main core of
the LNA circuit that the compensation circuit receives.
This error signal is applied to the biasing of the LNA cir-
cuit and leads to the generating of a constant gm in the
circuit. A constant current source exists in the compensa-
tion circuit, as well as an error voltage generating circuit.
In the current source circuit, the subtraction of two PTAT
currents is used to generate a current constant in relation
to variations of voltage and temperature. Furthermore, in
the LNA that operates with a supply voltage close to the
subthreshold, to improve efficiency the gm boosting tech-
nique is used as an inverter.
The organization of this article is so that Section 2
outlines the general configuration of the LNA circuit
based on the proposed compensator. The structure of the
LNA circuit and the techniques used to improve the vari-
ous design parameters are discussed comprehensively in
Section 3. Section 4 provides the operation of the pro-
posed PVT compensator circuit. Eventually, the post-
layout simulation results and the conclusion are
presented in Sections 5 and 6, respectively.
2 | L N A CI R C U I T
CONFIGURATION
The LNA circuit structure is shown in Figure 1, with
significant parts separated. This circuit is designed with
a common source and in its structure are used the cas-
cade, gm boosting, and π-matching techniques. The
LNA circuit bias is done by mirror current and by
configuring R1, R2, R3, and transistor Mc dimensions,
an appropriate gate voltage can be generated to ini-
tially start the circuit.
To reduce power consumption in the LNA circuit, it
is biased in subthreshold area. Circuit performance in the
subthreshold area reduces gm, gain and improper circuit
operation. Hence, as an alternative solution for eliminat-
ing the mentioned problem, a cascade technique with gm
boosting is used. In this structure transistors M1 and M2
NEJADHASAN ET AL.
F I G U R E 1 Low-noise amplifier
(LNA) circuit structure with
significant parts separation
are connected in a cascading manner, and transistors Mn
and Mp are related to the gm boosting structure. In the gm
boosting method, by simultaneously applying the signal
to gate and bias source, the gate-source voltage swing of
metal oxide semiconductor (MOS) transistor increases. In
this case, improvements, in terms of gain, NF, and com-
plexity reduction regarding Input matching network,
become accessible. The considered gm boosting structure
is inverter based on increasing the gm level to
gmn + gmp.16,17
The forward body bias technique is used to reduce the
required supply voltage for proper circuit performance,
and thus decrease power consumption. By applying the
adequate voltage to transistor body terminal, it is possible
to control Vth and inject the current suitable with a low
supply voltage into the circuit. However, a direct connec-
tion between the voltages and N-type metal oxide semi-
conductor (NMOS) transistor body increases the leakage
current in the P-type and the N-type (PN) junction
between the body and the source, as well as the power
consumption of the circuit. To solve this problem, a diode
connection transistor in reverse form is used between the
applied voltage and the transistor body. This technique is
used in the gm boosting structure as well. Moreover,
π-type matching has been used to have proper input and
output matching. The small dimensions of the capacitors
and inductors is one of the advantages of this matching
technique.
3 of 16
3 | OVERALL STRUCTURE OF
PRO P OS ED LN A
The block diagram configuration of LNA with the pro-
posed compensator circuit is shown in Figure 2. In the
designed LNA, the bias voltage is close to the threshold
voltage. In this case, if the bias voltage applied to the
LNA is constant, variations caused by the PVT will cause
significant changes in the main branch current. As a
result, various circuit parameters, more specifically gain,
will be affected. Considering the mentioned effects, one
of the best methods to shield various circuit parameters
against PVT variations is to use a changeable voltage
instead of a constant one. In this design, an error voltage
generator circuit is used to control the bias voltage of the
LNA, so as to reduce changes in the main parameters of
the circuit that directly result from PVT variations.
In the proposed circuit, the current of the main core
of the circuit is copied and then the current is adjusted
through the error voltage generator circuit. The error
voltage generator circuit generates an error voltage by
comparing a constant current with a fraction of the LNA
current (K
ILNA). The parameter K is the factor that bal-
ances current with the constant reference current (Iref).
Any increase or decrease in ILNA, when compared to Iref,
leads to corresponding changes in node voltage VE which
is applied to the bias circuit as a control voltage. The gen-
erated error voltage leads the P-type metal oxide
4 of 16 NEJADHASAN ET AL.

FIGURE 2 Low-noise amplifier (LNA) circuit block diagram with proposed compensator

semiconductor (PMOS) gate transistor (M8) to transfer

the current to the NMOS diode connection (Mc). There-
fore, the voltage Vbias changes so that LNA current
changes into the desired amount.
To reduce power consumption, a fraction of the LNA
main current (K
ILNA) is generated by the LNA replica
circuit to be compared with a constant current. Also, the
compensator circuit is separated from the LNA circuit so
that feedback does not affect LNA parameters negatively.
For this reason, an interface circuit is used to copy the
current of the LNA main branch and to compare it with
the constant current.

4 | P R O P O S ED P V T
COMPENSATOR C IR CUIT

As illustrated in Figure 1, the PVT compensator cir-
cuit consists of two parts, the error voltage genera-
tor circuit and the constant current reference. The
error voltage generator circuit can be seen in
Figure 3. The error voltage is generated by compar-
ing the copied and constant currents. In order to
adjust the LNA duplicate current produced by the
replica circuit, first its changes must be on a smaller
scale and similar to those currents passing through
the main branch of the LNA, and its value must be
comparable with the reference current. In the rep-
lica circuit, similar circumstances in terms of tran-
sistor types, gate bias and transistor body
connection are created so that the produced copy
current would have the same conditions as the LNA
main current. Since the proposed LNA circuit uses
F I G U R E 3 Proposed error voltage generator circuit in
process, voltage, and temperature (PVT) compensator circuit
the g m boosting technique to increase gain, achiev-
ing control over the changes caused by PVT varia-
tions can be attained by using variable bias in the g m
boosting part of the circuit.
4.1 | Temperature compensation
The error voltage is generated by comparing the replica
circuit current and the constant current. The constant
current reference must be insensitive to temperature and
voltage variations, and provide the proper current despite
process variation as well. In conventional current
NEJADHASAN ET AL. 5 of 16

8 1
sources, several self-biased current sources are usually >
> N c ffi 1:73 × 1016 T 3=2
>
< C
used to generate a current constant with PVT varia- N v ffi 4:8 × 1015 T 3=2 C
tions.18 The crucial point to keep in mind is that a high C ð6Þ
>
> T2 A
number of current sources increases power consumption >
: E g ffi E g ð0Þ −6:5 × 10 − 4 ×
T + 200
significantly.
Drain current changes in the saturation region of
MOS transistor in relation to temperature variation can where Nc, Nv, and Eg represent, respectively, the density
be expressed as Equation (1).19,20 of states in the conduction band, the valance band, and
band gap energy. As a result of the two relationships
β ðT Þ W mentioned, ni increases with temperature growth
I D ðT Þ = ðV GS −V th ðT ÞÞ2 ,βðT Þ = Cox μðT Þ ð1Þ
2 L (dn
dT > 0Þ. Derivative of Equation (4) in respect to tempera-
i

ture, Equation (7) is obtained.

In this case, Vth and VGS are threshold and gate-source

dφF ðT Þ n α2 α3 T
voltages, respectively. In addition, μ and Cox are mobility = α1 ln − − −1:5α1 ð7Þ
dT ni T ðα 4 + T Þ2
and oxide capacitance, respectively. Based on the provided
equation, temperature dependence of the drain current where α1 to α4 are positive coefficients respective to K, q,
can be attributed to β and Vth. The mobility variations and Eg(0). Evaluation of this relation shows that φF
F ðT Þ
with respect to temperature can be shown as Equation (2). decreases with an increase in temperature (dφdT < 0Þ .
The Vth derivative shows that the threshold voltage also

2
300 decreases with an increase in temperature (Equation (8)).
μðT Þ = μ300 ð2Þ
T  
dV th ðT Þ dφF ðT Þ γ
= 2+ ð8Þ
dT dT 2φF ðT Þ
In this equation, μ300 is the mobility at room tempera-
ture. Therefore, if temperature increases, β is reduced. A simple model to show Vth variations in relation to
The second factor affecting the temperature variations of temperature is based on Equation (9). In this case, α is
the drain current is the threshold voltage. Threshold volt- approximately (0.5-5) mV/ K, where it increases with the
age change in relation to temperature variation can be thickness of the oxide layer and the amount of substrate
expressed as Equation (3). impurity.
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
V th ðT Þ = V th0 + γ 2φF ðT Þ + V SB − 2φF ðT Þ ð3Þ V th ðT Þ = V th,300 −αðT −300 Þ ð9Þ

Therefore, the fraction (VGS − Vth(T))2 in Equation (1)

where VSB, Vth0, γ, and φF are source-body voltage, increases when temperature increases, while β(T)
threshold voltage at VSB = 0, body bias coefficient, and decreases. As a result, the drain current variation in the
surface potential, respectively. As seen, the temperature MOSFET transistor, in relation to temperature, is deter-
change of Vth depends on the temperature changes of the mined by the dominance of each of these two parts.
Bulk Fermi surface potential. The changes in φF in Based on Equation (1), the relationship between the
respect to temperature variation is determined by drain current and VGS is of the second degree in transis-
Equation (4). tors with a long channel. In MOSFET transistors with a
short channel, the velocity saturation effect causes the


KT n transistor to enter the saturation area at lower amounts
φF ðT Þ = ln ð4Þ
q ni of VDS. Equation (10) illustrates the drain current of
MOSFET transistors with a short channel in the satura-
Where K, q and ni are the Boltzmann constant, elec- tion area when VDS = Vdsat.21
tron charge, and intrinsic carrier concentration, respec-
 
tively. Changes in concentrations of intrinsic carriers in β V 2dsat
ID = ðV GS −V th ÞV dsat − ð10Þ
silicon in relation to temperature is shown by 2k 2
Equations (5) and (6).
In this equation, Vdsat is the voltage of the pinch of


Eg the channel and k is defined as k = 1 + EVCDSL , where EC is
ni ðT Þ = ðN c N v Þ1=2 exp − ð5Þ
2KT the critical electric field of the transistor. Also according
to this equation the drain current of MOFSET transistors
6 of 16
FIGURE 4 Proposed constant current reference circuit structure
F I G U R E 5 Changes in ID16, ID17, and ID18 relative to
temperature variation
with a short channel in the saturation area is linear.
Therefore the linear effect of the short channel must be
considered when calculating drain current variation in
relation to temperature changes. In the source current
circuit proposed, considering the large dimensions of the
transistors (L > 1 μm), the short channel effect does not
really affect circuit performance.
The proposed constant current generating circuit is
shown in Figure 4. The self-biased current source sec-
tion, which consists of transistors M9 to M12 and resis-
tor R4, produces the main current of the circuit.
Initially, the current generated from the self-biased
source by the transistor M13 is transmitted to the multi-
plier current (ID14). According to the equations men-
tioned, by proper adjustment of VGS and dimensions in
transistors M13 and M14, the ID14 current can be produced
in a manner as to have a positive relation with tempera-
ture change. In the multiplier current section, with
proper adjustment of dimensions of transistors M14 and
M15 and the resistor R5, a current with the same tempera-
ture gradient relating to temperature variation, but with
varying values is produced and transferred to the current
NEJADHASAN ET AL.
subtraction section. A subtracting circuit is used to pro-
duce a constant current in the proposed circuit. There-
fore, by subtracting ID16 and ID17 currents, which have
the same slope in respect to temperature variations, the
ID18 current is produced, with an insensitivity against
temperature feature. The variations of these three cur-
rents in a considered temperature range of 0 C to 100 C
is shown in Figure 5. Considering this figure, the
approximate-linear equation of current ID16, ID17, and
ID18 relative to temperature is shown in Equation (11).
Accordingly, in the considered temperature range, ID18
changes only about 1% (0.01 μA).
ID17 jμA ≈0:01T + 2
! ID18 jμA ≈0:0002T + 1:9 ð11Þ
ID16 jμA ≈0:0098T + 0:1
4.2 | Voltage compensation
The voltage change of the power supply has a direct
impact on VGS of the transistors in Figure 4. Considering
the current of the transistor, ID14 at room temperature
and in the saturation are, based on Equation (12), the
current rises with an increasing VGS (VGS = VG). In such
a situation, the effect of channel length modulation is
neglected.
W
I D14 = Cox μn ðV G − V th,n Þ2 ð12Þ
2L
The voltage variability range considered is around
30% which is appropriate for the desired application. This
change is suitable for IoT applications. By adjusting
NEJADHASAN ET AL. 7 of 16

T A B L E 1 Elements values of the proposed constant current deviation in supply voltage, current ID18 changes about
reference circuit 2% (0.045 μA).
Elements Values Elements Values
W 19:25 μm W 3 μm
ID17 jμA ≈5:3VDD −0:3
L 9 1 μm L 16 5 μm ! ID18 jμA ≈0:3VDD + 1:8 ð13Þ
5 μm 10 μm
W
L 10 1 μm
W
L 17 1 μm ID16 jμA ≈5VDD −2:1
W 10 μm W 12:2 μm
L 11 1 μm L 18 5 μm
W 5 μm W 20 μm
L 12 1 μm L 19 1 μm Table 2 demonstrates a comparison of the perfor-
W 8:8 μm mance of the proposed current source circuit and current
L 13 1 μm R4 10 k
W 10 μm
R5 39 k sources recently reported. In the proposed circuit, the
L 14 5 μm
W 50 μm output current is approximately 2 μA and temperature
- -
L 15 5 μm
range is from 0 C to 100 C. In this temperature range,
the TC, obtained from Equation (14), has the approxi-
mate value of 105 ppm/ C.

I ref,max −I ref,min
TC = × 106 ð14Þ
I ref,27 C ðT max −T min Þ

In the mentioned equation, T max and T min are,

F I G U R E 6 ID16, ID17, and ID18 currents variations vs 30%
deviation in supply voltage
transistor dimensions, in the mentioned range of varia-
tion, the current has been positive and behaving linearly
when voltage increases. Therefore, if in the multiplier
current section, two different currents, with identical
slopes in respect to voltage variation, can be produced, as
mentioned in the previous temperature compensation
section, an output current insensitive to voltage variation
can be created by subtracting the ID16 and ID17 currents.
To generate these two currents, the elements of the mul-
tiplier current section are reset. Therefore, generally
speaking, when selecting the dimensions of transistors
M14 and M15 and resistor R5, conditions of temperature
and voltage variation must be taken into account simulta-
neously. If these elements are properly adjusted, a cur-
rent insensitive to voltage and temperature variations can
be achieved without using an additional current source.
Considering the provided descriptions, various element
values involved in the proposed constant current refer-
ence circuit (Figure 4) are listed in Table 1.
Figure 6 shows the variations of ID16, ID17, and ID18
currents relative to the 30% deviation in supply voltage.
Based on attained results, the approximate-linear equa-
tion of currents ID16, ID17, and ID18 relative to supply volt-
age is written as Equation (13). Thus, with a 30%
respectively, the maximum and minimum tempera-
tures considered in circuit performance. Further-
more, I ref,max and I ref,min are, respectively, the
maximum and minimum amounts of output cur-
rent in the temperature range considered. And
lastly, I ref,27  C is the output current at 27  C.
According to Table 2, the proposed circuit has a
better TC compared to other circuits. With a 30%
change in supply voltage, output current changes
only about ±3.2%.
4.3 | Process compensation
As mentioned earlier, process variation is one of the
major challenges in sub-micron technologies and in low
supply voltage applications. Figure 7 illustrates the mech-
anism related to the process variation compensation pro-
cedure in the proposed circuit with five different corners.
If, at each of considered five corners, a change in the
main branch current of the LNA occurs with a change in
temperature (step 1), it also occurs in step 2 at a smaller-
scale due to the replica circuit. In step 3, the duplicate
current is compared with the constant current ICCR, and
in step 4 the error voltage corresponding to these changes
is generated. By applying this voltage to the PMOS tran-
sistor present in the biasing section of LNA, the desired
bias voltage (Vbias) is generated whose variation is oppo-
site to that of VE (step 5). Finally, the bias voltage pro-
duced compensates the LNA current variations. As a
result, variations of LNA main parameters that are
related to the mentioned current are reduced and miti-
gated, in respect to process and temperature variations.
8 of 16 NEJADHASAN ET AL.

TABLE 2 A comparison of the performance of the proposed current source circuit with other current sources

This work Sim. Sim.22 Sim.5 Meas.23 Meas.24 Meas.25 Sim.26

Process (nm) 65 180 65 180 65 180 180

Temperature range ( C) 0 to 100 0 to 100 −20 to 110 −40 to 125 −30 to 90 −40 to 85 0 to 100
Min. VDD (V) 0.45 1.35 0.4 0.7 1.2 1.25 1.25
IOUT (μA) 2 0.1 1.2 0.0097 9.422 0.0923 0.1

TC (ppm/ C) 105 335 118 149.8 119 176.91 125
Supply Var. (%/V) 12.5 0.037 1.2 0.6 0.1 7.5 0.35
2
Area (mm ) 0.0106 0.012 0.012 0.055 0.089 0.0013 N/A

FIGURE 7 Process variation compensation for five different corners in the proposed circuit

5 | POSTLAYOUT SIMULATION The supply voltage of this circuit is determined as

RESULT
In this section, postlayout simulation results of the LNA
circuit with the proposed PVT compensator are provided,
alongside those of circuits with conventional structures.
Analysis and simulation of the circuits is performed in
65-nm CMOS technology by using the CADENCE Spec-
tre RF simulator. Moreover, the postlayout results are
obtained after design rule check and layout vs schematic
revisions, and noise parameter extraction is done by
Calibre.
0.35 V, and all transistors operate in the subthreshold
region, and therefore power consumption of the proposed
circuit is significantly lower compared to its conventional
counterparts. The LNA circuit with the PVT compensator
only consumes 585 μW, an estimated 90 μW belonging to
the PVT compensator circuit. Given the improvements
made by the PVT compensator circuit, this amount of
power consumption can be neglected. The operating fre-
quency in the simulations is 2.32 GHz. Based on achieved
results and the provided explanations of the designed cir-
cuit, it can be nominated as a suitable candidate to be
NEJADHASAN ET AL. 9 of 16

F I G U R E 8 Gain, input matching, and noise figure

(NF) simulation results of the proposed circuit in nominal circumstances

used in various wireless and portable applications such

as in medical and IoT fields.
Figure 8 depicts the simulation results of the pro-
posed circuit in terms of gain (S21), input matching
(S11), and NF against frequency variation at 27 C and
TT corner. At 2.32 GHz, the values of S21, S11, and NF
achieved are 15.58, −14.5, and 2.28 dB, respectively. As
evidenced by the results obtained, utilizing the cascade
technique with gm boosting has led to a desirable
improvement in efficiency and NF at a low supply
voltage. In the following part, the aforementioned
three parameter changes in relation to PVT variations
and their deviations from nominal values (27 C and
TT) are investigated.
Simulation results of NF, S11 and S21 against tem-
perature variation in the LNA circuit with constant
bias are shown in Figure 9. With temperature varia-
tions in the range of 0 C to 100 C, NF, S11, and S21 var-
iations in different process corners are about 4.26,
27.58, and 20.8 dB, respectively. In the LNA circuit
with constant bias, the worst results for these three
parameters are achieved in SS (slow NMOS and slow
PMOS) analysis at 0 C.
Figure 10 shows the simulation results of NF, S11, and
S21 in the proposed LNA with the PVT compensator cir-
cuit. In this circuit, NF, S11, and S21 changes against tem-
perature variation in the five considered process corners
are approximately equal to, respectively, 0.92, 20.98, and
F I G U R E 9 Simulation results in terms of noise figure (NF),
2.02 dB. As a result, in the proposed circuit, NF and S21
S11, and S21 in low-noise amplifier (LNA) circuit with constant bias
variations decreased 4.6 and 10.3 times, respectively, as against temperature variation in different process corner: A, NF; B,
compared to the conventional LNA with constant bias. S11; C, S21
Also, in the proposed circuit S11 experiences a 24% reduc-
tion when compared to that of the constant bias circuit.
As observed in Figure 9, the largest variation of parame- the temperature and process compensator circuit, the dif-
ters occurs in SS and FF states, where the difference in ference between outputs in the five corners has been
output in these two states leads to a high increase in the aptly reduced, as seen in Figure 10.
range of variation of the intended parameters in the LNA In addition, simulation results relative to NF, S11, and
circuit with constant bias. In the proposed circuit, due to S21 regarding VDD variations in the LNA circuit with
10 of 16 NEJADHASAN ET AL.

F I G U R E 1 0 Simulation results in terms of noise figure (NF),

S11, and S21 in the proposed low-noise amplifier (LNA) circuit with
process, voltage, and temperature (PVT) compensator vs
temperature variation in different process corner: A, NF; B,
S11; C, S21

constant bias are illustrated in Figure 11. In this case,

considered changes are roughly 20% of the original sup-
ply voltage of the circuit. In this circuit, variations
recorded for NF, S11, and S21 are approximately 2.31,
24.28, and 16.23 dB, respectively. FIGURE 11 Noise figure (NF), S11, and S21 results vs VDD
The NF, S11, and S21 results relative to VDD variations variation in the low-noise amplifier (LNA) circuit with constant
in the proposed LNA circuit are shown in Figure 12. In bias: A, NF; B, S11; C, S21
NEJADHASAN ET AL.
FIGURE 12 Noise figure (NF), S11, and S21 relative to VDD
variation in low-noise amplifier (LNA) circuit with process, voltage,
and temperature (PVT) compensator: A, NF; B, S11; C, S21
the LNA circuit with PVT compensator, mentioned
changes are approximately 0.064, 14.43, and 2.47 dB,
11 of 16
respectively. Therefore, in the proposed LNA circuit,
NF and S21 have, respectively, decreased by 34 and 6.5
times compared to the VDD variation. In addition, S11
variations in the LNA circuit with a compensator
block decreased by about 41% compared to the LNA
with constant bias.
Monte Carlo simulation results of the circuit with
constant bias and those of the proposed circuit are shown
in Figures 13 and 14 respectively. This simulation is per-
formed while considering the significant NF and S21
parameters, and includes both process and mismatch
conditions. For 1000 runs, the standard deviations of NF
and S21 in the proposed circuit are 0.16 and 1.53, respec-
tively, which shows 31% and 30% decreases, respectively,
compared to the constant bias circuit. Also, the variation
coefficient (σ/μ) for S21 in both the proposed circuit and
the constant bias circuit are 10.7% and 16.1%,
respectively.
The layout of the proposed LNA circuit is shown
in Figure 15 which includes the LNA circuit and the
PVT compensator. The provided layout area is about
0.49 mm 2 . Placement of the various elements of the
LNA circuit and the PVT compensator part is done
so that noise parameters are reduced. The reduction
of noise parameters has a considerable positive
effect on the results obtained from postlayout
simulations.
Table 3 shows the results of S parameter and NF sim-
ulations, along with their variations in the two circuits.
The first column in each part shows maximum and mini-
mum amounts of the respective parameter at a certain
temperature and a certain state of the corner. The second
column correlates to the values of the parameters at TT
state and 27 C. The Δ column corresponds to the maxi-
mum and minimum changes of each parameter in
respect to their values at TT and room temperature analy-
sis, respectively. By comparing these two techniques, the
robustness of the proposed circuit against PVT variations
is proved.
Table 4 shows a comparison of various parameters
of the proposed circuit, as well as S21 variation analy-
sis with the designs presented. In “S21 Max. deviation,”
the first column shows efficiency variations in the con-
sidered temperature range as compared to its value at
27 C and TT state. In the proposed circuit the maxi-
mum deviation of this parameter as compared to its
value at room temperature is recorded as 0.95 dB. Also
the in terms of ppm and percentage, the variation is
671 and ±3.35, respectively. The second column pre-
sents efficiency variations at the five corner states as
compared to its value at 27 C. The third column illus-
trates efficiency variations by considering the changes
in the five corner states, as well as temperature
12 of 16 NEJADHASAN ET AL.

F I G U R E 1 3 Monte Carlo simulation results of conventional low-noise amplifier (LNA) circuit, for the process and mismatch in terms
of, A, noise figure (NF) and, B, S21

F I G U R E 1 4 Monte Carlo simulation results of the proposed low-noise amplifier (LNA) circuit with process, voltage, and temperature
(PVT) compensator for process and mismatch in terms of, A, noise figure (NF) and, B, S21

variations. And finally, the last column corresponds to In this table, in order to more clearly notice the
the SD to mean ratio (σ/μ) in the Monte Carlo improvements of the proposed circuit against PVT varia-
simulation. tions, constant bias condition results have been presented
NEJADHASAN ET AL. 13 of 16

as well. The circuit presented in Reference 28 is a wide- 6 | CONCLUSIONS

band LNA, whose operation frequency band is in the
0.18 to 2 GHz range. Parameters reported in this refer-
ence are the best values in this frequency range. Based on
attained results, despite the low voltage of the proposed
circuit, it has low power consumption, high gain and
high robustness, and tolerability against PVT variations
in comparison with other well-known designs. Further-
more, in different conditions the presented circuit param-
eters have small variations and their degradation is
negligible.
F I G U R E 1 5 Proposed low-noise amplifier (LNA) with
process, voltage, and temperature (PVT) compensator circuit layout
design
In this article, an LNA circuit with a PVT compensator is
proposed. The transistors of the LNA circuit are biased in
the subthreshold area which has a significant effect in
reducing power consumption of the circuit. In the LNA
circuit, the cascade technique with gm boosting is used
which has led to an increase in efficiency and a reduction
in the NF. Furthermore, π-matching has provided for
proper matching in the input and output of the proposed
LNA circuit. To reduce sensitivity of the circuit to PVT
variations, a compensator circuit is used in the design.
The proposed compensator circuit consists of a current
source circuit and an error generator circuit. In the error
generator circuit, a fraction of the LNA current is com-
pared with the constant current and an error voltage for
the LNA circuit bias is generated. The varying bias cre-
ated controls the variations of the LNA circuit main
branch current and also satisfyingly reduces circuit sensi-
tivity to PVT variations. In the current source circuit, the
two PTAT currents generated are subtracted from each
other and a current constant in relation to PVT variations
is produced. The mentioned circuit consumes 90 μW of
the total power dissipation, which can be ignored when
considering the changes in the LNA main parameters
due to PVT variations it has mitigated. Postlayout simula-
tion results in 65-nm CMOS technology indicated that in
the proposed circuit, gain, and NF variations is compari-
son with conventional circuits in five different corners
were reduced by 10.3 and 4.6 times, respectively. More-
over, with a 20% change in supply voltage, gain and NF
of the proposed circuit decreased by 6.5 and 34 times,
respectively, compared to the conventional design. In
addition, gain, NF, S11, and IIP3 of the proposed LNA cir-
cuit at room temperature and with a supply voltage of

TABLE 3 S-parameter and NF Simulation results and their variations in LNA circuit with and without PVT compensator

Maximum and minimum value without PVT Maximum and minimum value with PVT
compensation compensation

LNA parameters Corner,  C, dB tt, 27 C, dB Δ (dB) Corner,  C, dB tt, 27 C, dB Δ (dB)
 
S21 ff, 0 C, 17.7 15.02 +2.68 ss, 0 C, 15.81 15.58 +0.23
ss, 0 C, −3.1 −18.12 sf, 0 C, 13.79 −1.79
S11 ss, 0 C, −.7.46 −13.53 +6.07 fs, 0 C, −.9.89 −14.5 +4.61
ff, 65 C, −35.04 −21.51 ss, 100 C, −30.87 −16.37
S12 sf, 25 C, −25.76 −26.87 +1.11 sf, 0 C, −25.9 −27.87 +1.97
ff, 100 C, −31.89 −5.02 fs, 0 C, −32.4 −4.53
S22 ss, 0 C, −7.47 −12.73 +5.26 fs, 0 C, −9.18 −12.82 +3.64
ff, 0 C, −14.38 −1.65 ff, 0 C, −14.31 −1.49
NF ss, 0 C, 6.21 2.35 +3.86 tt, 100 C, 2.82 2.28 +0.54
ff, 0 C, 1.95 −0.4 fs, 0 C, 1.9 −0.38
 14 of 16

TABLE 4 Comparison of different proposed circuit parameters with other designs

S21 Max. deviation

Freg. Tech. NF S11 Pd Temp. Temp. max. var. for tt Five. corner max. Temp. + 5 corner σ/μ
(GHz) (nm) VDD Gain (dB) (dB) (mW) range ( C) corner (dB, ppm/ C,%) var. @ 27 C (dB,%) max. var. (dB,%) (%)
This work (with PVT 2.32 65 0.35 15.58 2.28 −14.5 0.585 0 to 100 −0.95, 671, ±3.35 −1.16, ±3.88 −1.79, ±6.5 10.7
compensation)
Sim.
without PVT 2.32 65 0.35 15.02 2.35 −13.53 0.436 0 to 100 −2.42, 1964, ±9.82 −9.67, ±39.98 −18.12 ± 69.2 16.1
compensation Sim.
Sim.5 2.14 65 0.6 9.2 2.82 −26.8 0.402 −20 to 110 −0.35, 415, ±2.6 −0.66, ±5 −0.79, ±6.4 8.34
27
Sim. 2.34 180 N/R 4.52 3.5 −15.31 N/R −40 to 80 0.14, N/R, +3 N/R, +4.5 N/R 13.48
28
Meas. 3.2 65 N/R 9.5 N/R N/R 7.69 0 to 80 N/R, 1554, N/R N/R, ±2.25 N/R 2.19
Sim.29 0.18 to 2 180 1.2 20.8 2.65 −12.5 4.9 −40 to 80 −3.3, 1586, ±7.93 −4.8 ± 13.22 N/R 9.58
Meas.30 2.4 180 0.6 10.4 3.46 −9.2 1.31 N/A N/A N/A N/A N/A
NEJADHASAN ET AL.
NEJADHASAN ET AL.
0.35 V, are roughly 15.02, 2.35, −13.53, and − 16.7 dB,
respectively. Based on the provided layout, the proposed
LNA circuit layout are is approximately 0.49 mm2.
ORCID
Sajad Nejadhasan https://orcid.org/0000-0001-6170-
0762
Fatemeh Zaheri https://orcid.org/0000-0002-0535-1489
Ebrahim Abiri https://orcid.org/0000-0001-5597-3166
Mohammad Reza Salehi https://orcid.org/0000-0002-
7251-3564
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16 of 16
AUTHOR BIOGRAPHIES
Sajad Nejadhasan was born in Iran,
Bushehr, in 1987. He received the
BSc degree in the department of engi-
neering from Persian Gulf University
in 2011 and MSc degree from electri-
cal engineering at Shiraz University
of Technology (SUTech) in 2015, and
is currently working toward the PhD degree in electri-
cal engineering at Shiraz University of Technology.
His research interests include IoT design and design
of receiver block in IoT application.
Fatemeh zaheri was born in Iran,
Bandar Aabbas, in 1995. She received
the BSc degree in Electronics Engi-
neering from Hormozgan University
in 2017 and the MSc degree in elec-
trical engineering from Shiraz Uni-
versity of Technology (SUTech) in
2020. Her research interests include design of a low
power frequency down convertor for IoT application.
Ebrahim Abiri received the BSc
degree in electronics engineering
from Iran University of Science and
Technology (IUST) in 1992, MSc
degree from Shiraz University in
1996, and the PhD degree in elec-
tronic from Iran University of Sci-
ence and Technology (IUST) in 2007. He has
NEJADHASAN ET AL.
authored more than 100 published technical papers in
electronics and power electronics and 4 books. He has
been with the Department of Electrical Engineering,
Shiraz University of Technology (SUTech), since
2007. His current research activities include analog
circuit design, RFIC, and power electronic.
Mohammad Reza Salehi received
his BSc degree in electrical engineer-
ing from Amirkabir University of
Technology (Tehran Polytechnique),
Tehran, the MSc degree in electrical
engineering from Shiraz University,
Shiraz, Iran, and his PhD degree in
electronics at the ENSERG/INPG, France. He has
authored and coauthored over 175 journal and confer-
ence papers and 7 books. He is a member of IEEE and
currently a full professor at Shiraz University of tech-
nology (SUTech) and Regional Information Center for
Science and Technology (RICeST). His research inter-
ests include digital electronics, machine learning, sig-
nal processing, and optical systems.
How to cite this article: Nejadhasan S, Zaheri F,
Abiri E, Salehi MR. PVT-compensated low-voltage
and low-power CMOS LNA for IoT applications.
Int J RF Microw Comput Aided Eng. 2020;e22419.
https://doi.org/10.1002/mmce.22419