SRI RAMAKRISHNA ENGINEERING COLLEGE

[Educational Service : SNR Sons Charitable Trust]

[Autonomous Institution, Accredited by NAAC with ‘A’ Grade]
[Approved by AICTE and Permanently Affiliated to Anna University, Chennai]
[ISO 9001-2008 Certified and all eligible programmes Accredited by NBA]
VATTAMALAIPALAYAM, N.G.G.O. COLONY POST, COIMBATORE – 641 022.

Department of Electronics and Communication Engineering

Internal Test – I
Date 06.01.2022 Programme M.E. VLSI Design
Semester I Class/section I year M.E. VLSI Design
Duration 90 minutes Maximum marks 50
Course Code & Title: 18EC1002 CMOS VLSI Design
Course Outcome Addressed
CO1: Make use of the concepts of MOS transistor to design VLSI circuits.
CO2: Apply the concepts of CMOS design to design the combinational and sequential logic circuits.

PART – A (9 x 2 = 18 marks)
Q. Questions Cognitive Course
No Level Outcome

1. Distinguish enhancement and depletion mode MOSFET. U CO1

2. Define threshold voltage. R CO1
3. Illustrate gate overlap capacitances in a MOS transistor and state the reason for U CO1
its occurrence
4. What is the effect of substrate bias on threshold voltage in MOS transistor? U CO1
5. How is the value of λ decided in layout design process? U CO1
6. Define DIBL R CO1
7. Is nMOS pass transistor preferred for passing logic 1 input? Justify your U CO2
answer.
8. Draw the circuit of NAND gate using CMOS inverter logic. U CO2
9. Draw the circuit of a transmission gate and state its principle of R CO2
operation.
PART – B (2 x 16 = 32 marks)

10. a) Derive the I-V relations in an nMOS enhancement mode transistor in Ap CO1
all the regions of operation and draw the characteristics. (12 marks)
b) What is Latchup? How can it be avoided? (4 marks) U CO1
11. a) i) Describe the principle of operation of enhancement mode MOS U CO1
transistor with neat diagrams. (10 marks)
ii) Implement a 2:1 multiplexer using transmission gates (6 marks) Ap CO2
(or)
b) i) Explain in brief the various second order effects that occur in U CO1
MOS transistor (10 marks)
ii) Implement the logic function Y = [AB+CD]’ using CMOS Ap CO2
inverter based logic. (6 marks)